2 * Copyright (c) 2004, Joerg Sonnenberger <joerg@bec.de>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * $DragonFly: src/sys/bus/pci/pci_pcib.c,v 1.1 2004/02/24 15:21:25 joerg Exp $
29 #include <sys/param.h>
31 #include <sys/kernel.h>
32 #include <sys/malloc.h>
33 #include <sys/module.h>
35 #include <sys/systm.h>
37 #include <machine/resource.h>
39 #include <bus/pci/pcivar.h>
40 #include <bus/pci/pcireg.h>
42 #include "pcib_private.h"
45 * Attach a pci bus device to a motherboard or pci-to-pci bridge bus.
46 * Due to probe recursion it is possible for pci-to-pci bridges (such as
47 * on the DELL2550) to attach before all the motherboard bridges have
48 * attached. We must call device_add_child() with the secondary id
49 * rather then -1 in order to ensure that we do not accidently use
50 * a motherboard PCI id, otherwise the device probe will believe that
51 * the later motherboard bridge bus has already been probed and refuse
52 * to probe it. The result: disappearing busses!
54 * Bridges will cause recursions or duplicate attach attempts. If
55 * we have already attached this bus we don't do it again!
59 pcib_attach_common(device_t dev)
61 struct pcib_softc *sc;
64 sc = device_get_softc(dev);
68 * Get current bridge configuration.
70 sc->command = pci_read_config(dev, PCIR_COMMAND, 1);
71 sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1);
72 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1);
73 sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2);
74 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2);
75 sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1);
78 * Determine current I/O decode.
80 if (sc->command & PCIM_CMD_PORTEN) {
81 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1);
82 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
83 sc->iobase = PCI_PPBIOBASE(pci_read_config(dev, PCIR_IOBASEH_1, 2),
84 pci_read_config(dev, PCIR_IOBASEL_1, 1));
86 sc->iobase = PCI_PPBIOBASE(0, pci_read_config(dev, PCIR_IOBASEL_1, 1));
89 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1);
90 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
91 sc->iolimit = PCI_PPBIOLIMIT(pci_read_config(dev, PCIR_IOLIMITH_1, 2),
92 pci_read_config(dev, PCIR_IOLIMITL_1, 1));
94 sc->iolimit = PCI_PPBIOLIMIT(0, pci_read_config(dev, PCIR_IOLIMITL_1, 1));
99 * Determine current memory decode.
101 if (sc->command & PCIM_CMD_MEMEN) {
102 sc->membase = PCI_PPBMEMBASE(0, pci_read_config(dev, PCIR_MEMBASE_1, 2));
103 sc->memlimit = PCI_PPBMEMLIMIT(0, pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
104 sc->pmembase = PCI_PPBMEMBASE((pci_addr_t)pci_read_config(dev, PCIR_PMBASEH_1, 4),
105 pci_read_config(dev, PCIR_PMBASEL_1, 2));
106 sc->pmemlimit = PCI_PPBMEMLIMIT((pci_addr_t)pci_read_config(dev, PCIR_PMLIMITH_1, 4),
107 pci_read_config(dev, PCIR_PMLIMITL_1, 2));
113 switch (pci_get_devid(dev)) {
114 case 0x12258086: /* Intel 82454KX/GX (Orion) */
118 supbus = pci_read_config(dev, 0x41, 1);
119 if (supbus != 0xff) {
120 sc->secbus = supbus + 1;
121 sc->subbus = supbus + 1;
127 * The i82380FB mobile docking controller is a PCI-PCI bridge,
128 * and it is a subtractive bridge. However, the ProgIf is wrong
129 * so the normal setting of PCIB_SUBTRACTIVE bit doesn't
130 * happen. There's also a Toshiba bridge that behaves this
133 case 0x124b8086: /* Intel 82380FB Mobile */
134 case 0x060513d7: /* Toshiba ???? */
135 sc->flags |= PCIB_SUBTRACTIVE;
140 * Intel 815, 845 and other chipsets say they are PCI-PCI bridges,
141 * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM,
142 * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese.
143 * This means they act as if they were subtractively decoding
144 * bridges and pass all transactions. Mark them and real ProgIf 1
145 * parts as subtractive.
147 if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 ||
148 pci_read_config(dev, PCIR_PROGIF, 1) == 1)
149 sc->flags |= PCIB_SUBTRACTIVE;
152 device_printf(dev, " secondary bus %d\n", sc->secbus);
153 device_printf(dev, " subordinate bus %d\n", sc->subbus);
154 device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, sc->iolimit);
155 device_printf(dev, " memory decode 0x%x-0x%x\n", sc->membase, sc->memlimit);
156 device_printf(dev, " prefetched decode 0x%x-0x%x\n", sc->pmembase, sc->pmemlimit);
157 if (sc->flags & PCIB_SUBTRACTIVE)
158 device_printf(dev, " Subtractively decoded bridge.\n");
162 * XXX If the secondary bus number is zero, we should assign a bus number
163 * since the BIOS hasn't, then initialise the bridge.
167 * XXX If the subordinate bus number is less than the secondary bus number,
168 * we should pick a better value. One sensible alternative would be to
169 * pick 255; the only tradeoff here is that configuration transactions
170 * would be more widely routed than absolutely necessary.
175 pcib_match(device_t dev)
177 switch (pci_get_devid(dev)) {
178 /* Intel -- vendor 0x8086 */
180 return ("Intel 82443LX (440 LX) PCI-PCI (AGP) bridge");
182 return ("Intel 82443BX (440 BX) PCI-PCI (AGP) bridge");
184 return ("Intel 82443GX (440 GX) PCI-PCI (AGP) bridge");
186 return ("Intel 82454NX PCI Expander Bridge");
188 return ("Intel 82801BA/BAM (ICH2) PCI-PCI (AGP) bridge");
190 return ("Intel 82380FB mobile PCI to PCI bridge");
192 return ("Intel 82801AA (ICH) Hub to PCI bridge");
194 return ("Intel 82801AB (ICH0) Hub to PCI bridge");
196 return ("Intel 82801BA/BAM (ICH2) Hub to PCI bridge");
198 return ("Intel 82845 PCI-PCI (AGP) bridge");
200 /* VLSI -- vendor 0x1004 */
202 return ("VLSI 82C534 Eagle II PCI Bus bridge");
204 return ("VLSI 82C538 Eagle II PCI Docking bridge");
206 /* VIA Technologies -- vendor 0x1106 */
208 return ("VIA 8363 (Apollo KT133) PCI-PCI (AGP) bridge");
210 return ("VIA 82C598MVP (Apollo MVP3) PCI-PCI (AGP) bridge");
211 /* Exclude the ACPI function of VT82Cxxx series */
217 /* AcerLabs -- vendor 0x10b9 */
218 /* Funny : The datasheet told me vendor id is "10b8",sub-vendor */
219 /* id is '10b9" but the register always shows "10b9". -Foxfair */
221 return ("AcerLabs M5247 PCI-PCI(AGP Supported) bridge");
222 case 0x524310b9:/* 5243 seems like 5247, need more info to divide*/
223 return ("AcerLabs M5243 PCI-PCI bridge");
225 /* AMD -- vendor 0x1022 */
227 return ("AMD-751 PCI-PCI (1x/2x AGP) bridge");
229 return ("AMD-761 PCI-PCI (4x AGP) bridge");
231 /* DEC -- vendor 0x1011 */
233 return ("DEC 21050 PCI-PCI bridge");
235 return ("DEC 21052 PCI-PCI bridge");
237 return ("DEC 21150 PCI-PCI bridge");
239 return ("DEC 21152 PCI-PCI bridge");
241 return ("DEC 21153 PCI-PCI bridge");
243 return ("DEC 21154 PCI-PCI bridge");
245 /* NVIDIA -- vendor 0x10de */
248 return ("NVIDIA nForce2 PCI-PCI bridge");
252 return ("IBM 82351 PCI-PCI bridge");
253 /* UMC United Microelectronics 0x1060 */
255 return ("UMC UM8881 HB4 486 PCI Chipset");
258 if (pci_get_class(dev) == PCIC_BRIDGE
259 && pci_get_subclass(dev) == PCIS_BRIDGE_PCI)
260 return pci_bridge_type(dev);
265 static int pcib_probe(device_t dev)
269 desc = pcib_match(dev);
271 device_set_desc_copy(dev, desc);
279 pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
281 struct pcib_softc *sc = device_get_softc(dev);
285 *result = sc->secbus;
292 pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
294 struct pcib_softc *sc = device_get_softc(dev);
305 pcib_attach(device_t dev)
307 struct pcib_softc *sc;
310 pcib_attach_common(dev);
311 sc = device_get_softc(dev);
312 /*chipset_attach(dev, device_get_unit(dev));*/
314 if (sc->secbus != 0) {
315 child = device_add_child(dev, "pci", sc->secbus);
317 return bus_generic_attach(dev);
323 * Is the prefetch window open (eg, can we allocate memory in it?)
326 pcib_is_prefetch_open(struct pcib_softc *sc)
328 return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit);
332 * Is the nonprefetch window open (eg, can we allocate memory in it?)
335 pcib_is_nonprefetch_open(struct pcib_softc *sc)
337 return (sc->membase > 0 && sc->membase < sc->memlimit);
341 * Is the io window open (eg, can we allocate ports in it?)
344 pcib_is_io_open(struct pcib_softc *sc)
346 return (sc->iobase > 0 && sc->iobase < sc->iolimit);
350 * We have to trap resource allocation requests and ensure that the bridge
351 * is set up to, or capable of handling them.
354 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
355 u_long start, u_long end, u_long count, u_int flags)
357 struct pcib_softc *sc = device_get_softc(dev);
361 * Fail the allocation for this range if it's not supported.
366 if (!pcib_is_io_open(sc))
368 ok = (start >= sc->iobase && end <= sc->iolimit);
369 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
371 if (start < sc->iobase)
373 if (end > sc->iolimit)
379 if (start < sc->iobase && end > sc->iolimit) {
386 device_printf(dev, "ioport: end (%lx) < start (%lx)\n", end, start);
392 device_printf(dev, "device %s requested unsupported I/O "
393 "range 0x%lx-0x%lx (decoding 0x%x-0x%x)\n",
394 device_get_nameunit(child), start, end,
395 sc->iobase, sc->iolimit);
399 device_printf(dev, "device %s requested decoded I/O range 0x%lx-0x%lx\n",
400 device_get_nameunit(child), start, end);
405 if (pcib_is_nonprefetch_open(sc))
406 ok = ok || (start >= sc->membase && end <= sc->memlimit);
407 if (pcib_is_prefetch_open(sc))
408 ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit);
409 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
412 if (flags & RF_PREFETCHABLE) {
413 if (pcib_is_prefetch_open(sc)) {
414 if (start < sc->pmembase)
415 start = sc->pmembase;
416 if (end > sc->pmemlimit)
421 } else { /* non-prefetchable */
422 if (pcib_is_nonprefetch_open(sc)) {
423 if (start < sc->membase)
425 if (end > sc->memlimit)
433 ok = 1; /* subtractive bridge: always ok */
435 if (pcib_is_nonprefetch_open(sc)) {
436 if (start < sc->membase && end > sc->memlimit) {
441 if (pcib_is_prefetch_open(sc)) {
442 if (start < sc->pmembase && end > sc->pmemlimit) {
443 start = sc->pmembase;
450 device_printf(dev, "memory: end (%lx) < start (%lx)\n", end, start);
455 if (!ok && bootverbose)
457 "device %s requested unsupported memory range "
458 "0x%lx-0x%lx (decoding 0x%x-0x%x, 0x%x-0x%x)\n",
459 device_get_nameunit(child), start, end,
460 sc->membase, sc->memlimit, sc->pmembase,
465 device_printf(dev,"device %s requested decoded memory range 0x%lx-0x%lx\n",
466 device_get_nameunit(child), start, end);
473 * Bridge is OK decoding this resource, so pass it up.
475 return (bus_generic_alloc_resource(dev, child, type, rid, start, end, count, flags));
480 pcib_maxslots(device_t dev)
486 pcib_read_config(device_t dev, int b, int s, int f,
490 * Pass through to the next ppb up the chain (i.e. our
493 return PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)),
494 b, s, f, reg, width);
498 pcib_write_config(device_t dev, int b, int s, int f,
499 int reg, uint32_t val, int width)
502 * Pass through to the next ppb up the chain (i.e. our
505 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)),
506 b, s, f, reg, val, width);
510 * Route an interrupt across a PCI bridge.
513 pcib_route_interrupt(device_t pcib, device_t dev, int pin)
519 device_printf(pcib, "Hi!\n");
523 * The PCI standard defines a swizzle of the child-side device/intpin
524 * to the parent-side intpin as follows.
526 * device = device on child bus
527 * child_intpin = intpin on child bus slot (0-3)
528 * parent_intpin = intpin on parent bus slot (0-3)
530 * parent_intpin = (device + child_intpin) % 4
532 parent_intpin = (pci_get_slot(pcib) + (pin - 1)) % 4;
535 * Our parent is a PCI bus. Its parent must export the pci interface
536 * which includes the ability to route interrupts.
538 bus = device_get_parent(pcib);
539 intnum = PCI_ROUTE_INTERRUPT(device_get_parent(bus), pcib,
541 device_printf(pcib, "routed slot %d INT%c to irq %d\n",
542 pci_get_slot(dev), 'A' + pin - 1, intnum);
547 * Try to read the bus number of a host-PCI bridge using appropriate config
551 host_pcib_get_busno(pci_read_config_fn read_config, int bus, int slot, int func,
556 id = read_config(bus, slot, func, PCIR_DEVVENDOR, 4);
557 if (id == 0xffffffff)
563 /* XXX This is a guess */
564 /* *busnum = read_config(bus, slot, func, 0x41, 1); */
568 /* Intel 82454KX/GX (Orion) */
569 *busnum = read_config(bus, slot, func, 0x4a, 1);
573 * For the 450nx chipset, there is a whole bundle of
574 * things pretending to be host bridges. The MIOC will
575 * be seen first and isn't really a pci bridge (the
576 * actual busses are attached to the PXB's). We need to
577 * read the registers of the MIOC to figure out the
578 * bus numbers for the PXB channels.
580 * Since the MIOC doesn't have a pci bus attached, we
581 * pretend it wasn't there.
587 /* Intel 82454NX PXB#0, Bus#A */
588 *busnum = read_config(bus, 0x10, func, 0xd0, 1);
591 /* Intel 82454NX PXB#0, Bus#B */
592 *busnum = read_config(bus, 0x10, func, 0xd1, 1) + 1;
595 /* Intel 82454NX PXB#1, Bus#A */
596 *busnum = read_config(bus, 0x10, func, 0xd3, 1);
599 /* Intel 82454NX PXB#1, Bus#B */
600 *busnum = read_config(bus, 0x10, func, 0xd4, 1) + 1;
605 /* ServerWorks -- vendor 0x1166 */
617 *busnum = read_config(bus, slot, func, 0x44, 1);
620 /* Don't know how to read bus number. */
627 static device_method_t pcib_methods[] = {
628 /* Device interface */
629 DEVMETHOD(device_probe, pcib_probe),
630 DEVMETHOD(device_attach, pcib_attach),
631 DEVMETHOD(device_shutdown, bus_generic_shutdown),
632 DEVMETHOD(device_suspend, bus_generic_suspend),
633 DEVMETHOD(device_resume, bus_generic_resume),
636 DEVMETHOD(bus_print_child, bus_generic_print_child),
637 DEVMETHOD(bus_read_ivar, pcib_read_ivar),
638 DEVMETHOD(bus_write_ivar, pcib_write_ivar),
639 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource),
640 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
641 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
642 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
643 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
644 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
647 DEVMETHOD(pcib_maxslots, pcib_maxslots),
648 DEVMETHOD(pcib_read_config, pcib_read_config),
649 DEVMETHOD(pcib_write_config, pcib_write_config),
650 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt),
655 static driver_t pcib_driver = {
658 sizeof(struct pcib_softc)
661 devclass_t pcib_devclass;
663 DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0);