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40 #define IGB_MAX_RING_82575 4
41 #define IGB_MAX_RING_I350 8
42 #define IGB_MAX_RING_82580 8
43 #define IGB_MAX_RING_82576 16
44 #define IGB_MIN_RING 1
45 #define IGB_MIN_RING_RSS 2
48 * Max TX/RX interrupt bits
50 #define IGB_MAX_TXRXINT_82575 4 /* XXX not used */
51 #define IGB_MAX_TXRXINT_I350 8
52 #define IGB_MAX_TXRXINT_82580 8
53 #define IGB_MAX_TXRXINT_82576 16
54 #define IGB_MIN_TXRXINT 2 /* XXX VF? */
59 #define IGB_MAX_IVAR_I350 4
60 #define IGB_MAX_IVAR_82580 4
61 #define IGB_MAX_IVAR_82576 8
62 #define IGB_MAX_IVAR_VF 1
65 * IGB_TXD: Maximum number of Transmit Descriptors
67 * This value is the number of transmit descriptors allocated by the driver.
68 * Increasing this value allows the driver to queue more transmits. Each
69 * descriptor is 16 bytes.
70 * Since TDLEN should be multiple of 128bytes, the number of transmit
71 * desscriptors should meet the following condition.
72 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
74 #define IGB_MIN_TXD 256
75 #define IGB_DEFAULT_TXD 1024
76 #define IGB_MAX_TXD 4096
79 * IGB_RXD: Maximum number of Transmit Descriptors
81 * This value is the number of receive descriptors allocated by the driver.
82 * Increasing this value allows the driver to buffer more incoming packets.
83 * Each descriptor is 16 bytes. A receive buffer is also allocated for each
84 * descriptor. The maximum MTU size is 16110.
85 * Since TDLEN should be multiple of 128bytes, the number of transmit
86 * desscriptors should meet the following condition.
87 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
89 #define IGB_MIN_RXD 256
90 #define IGB_DEFAULT_RXD 1024
91 #define IGB_MAX_RXD 4096
94 * This parameter controls when the driver calls the routine to reclaim
95 * transmit descriptors. Cleaning earlier seems a win.
97 #define IGB_TX_CLEANUP_THRESHOLD(sc) ((sc)->num_tx_desc / 2)
100 * This parameter controls whether or not autonegotation is enabled.
101 * 0 - Disable autonegotiation
102 * 1 - Enable autonegotiation
104 #define DO_AUTO_NEG 1
107 * This parameter control whether or not the driver will wait for
108 * autonegotiation to complete.
109 * 1 - Wait for autonegotiation to complete
110 * 0 - Don't wait for autonegotiation to complete
112 #define WAIT_FOR_AUTO_NEG_DEFAULT 0
114 /* Tunables -- End */
116 #define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
117 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
120 #define AUTO_ALL_MODES 0
122 /* PHY master/slave setting */
123 #define IGB_MASTER_SLAVE e1000_ms_hw_default
126 * Micellaneous constants
128 #define IGB_VENDOR_ID 0x8086
130 #define IGB_JUMBO_PBA 0x00000028
131 #define IGB_DEFAULT_PBA 0x00000030
132 #define IGB_SMARTSPEED_DOWNSHIFT 3
133 #define IGB_SMARTSPEED_MAX 15
134 #define IGB_MAX_LOOP 10
136 #define IGB_RX_PTHRESH (hw->mac.type <= e1000_82576 ? 16 : 8)
137 #define IGB_RX_HTHRESH 8
138 #define IGB_RX_WTHRESH 1
140 #define IGB_TX_PTHRESH 8
141 #define IGB_TX_HTHRESH 1
142 #define IGB_TX_WTHRESH 16
144 #define MAX_NUM_MULTICAST_ADDRESSES 128
145 #define IGB_FC_PAUSE_TIME 0x0680
147 #define IGB_INTR_RATE 6000
148 #define IGB_MSIX_RX_RATE 6000
149 #define IGB_MSIX_TX_RATE 4000
152 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
153 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
154 * also optimize cache line size effect. H/W supports up to cache line size 128.
156 #define IGB_DBA_ALIGN 128
158 /* PCI Config defines */
159 #define IGB_MSIX_BAR 3
161 #define IGB_MAX_SCATTER 64
162 #define IGB_VFTA_SIZE 128
163 #define IGB_TSO_SIZE (65535 + \
164 sizeof(struct ether_vlan_header))
165 #define IGB_TSO_SEG_SIZE 4096 /* Max dma segment size */
166 #define IGB_HDR_BUF 128
167 #define IGB_PKTTYPE_MASK 0x0000FFF0
169 #define IGB_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
170 #define IGB_IPVHL_SIZE 1 /* sizeof(ip.ip_vhl) */
171 #define IGB_TXCSUM_MINHL (ETHER_HDR_LEN + EVL_ENCAPLEN + \
174 /* One for TX csum offloading desc, the other 2 are reserved */
175 #define IGB_TX_RESERVED 3
177 /* Large enough for 64K TSO */
178 #define IGB_TX_SPARE 32
180 #define IGB_TX_OACTIVE_MAX 64
182 /* main + 16x RX + 16x TX */
183 #define IGB_NSERIALIZE 33
185 #define IGB_NRSSRK 10
186 #define IGB_RSSRK_SIZE 4
187 #define IGB_RSSRK_VAL(key, i) (key[(i) * IGB_RSSRK_SIZE] | \
188 key[(i) * IGB_RSSRK_SIZE + 1] << 8 | \
189 key[(i) * IGB_RSSRK_SIZE + 2] << 16 | \
190 key[(i) * IGB_RSSRK_SIZE + 3] << 24)
193 #define IGB_RETA_SIZE 4
194 #define IGB_RETA_SHIFT 0
195 #define IGB_RETA_SHIFT_82575 6
197 #define IGB_EITR_INTVL_MASK 0x7ffc
198 #define IGB_EITR_INTVL_SHIFT 2
203 * Bus dma information structure
206 bus_addr_t dma_paddr;
208 bus_dma_tag_t dma_tag;
209 bus_dmamap_t dma_map;
213 * Transmit ring: one per queue
216 struct lwkt_serialize tx_serialize;
217 struct igb_softc *sc;
219 struct igb_dma txdma;
220 bus_dma_tag_t tx_hdr_dtag;
221 bus_dmamap_t tx_hdr_dmap;
222 bus_addr_t tx_hdr_paddr;
223 struct e1000_tx_desc *tx_base;
225 uint32_t next_avail_desc;
226 uint32_t next_to_clean;
229 struct igb_tx_buf *tx_buf;
230 bus_dma_tag_t tx_tag;
237 uint32_t tx_intr_mask;
239 u_long no_desc_avail;
242 u_long ctx_try_pullup;
246 u_long ctx_pullup1_failed;
248 u_long ctx_pullup2_failed;
252 * Receive ring: one per queue
255 struct lwkt_serialize rx_serialize;
256 struct igb_softc *sc;
258 struct igb_dma rxdma;
259 union e1000_adv_rx_desc *rx_base;
262 uint32_t next_to_check;
263 struct igb_rx_buf *rx_buf;
264 bus_dma_tag_t rx_tag;
265 bus_dmamap_t rx_sparemap;
267 uint32_t rx_intr_mask;
270 * First/last mbuf pointers, for
271 * collecting multisegment RX packets.
280 struct igb_msix_data {
281 struct lwkt_serialize *msix_serialize;
282 struct lwkt_serialize msix_serialize0;
283 struct igb_softc *msix_sc;
285 struct igb_rx_ring *msix_rx;
286 struct igb_tx_ring *msix_tx;
288 driver_intr_t *msix_func;
294 struct resource *msix_res;
298 char msix_rate_desc[32];
302 struct arpcom arpcom;
305 struct e1000_osdep osdep;
308 #define IGB_FLAG_SHARED_INTR 0x1
309 #define IGB_FLAG_HAS_MGMT 0x2
311 bus_dma_tag_t parent_tag;
314 struct resource *mem_res;
316 struct ifmedia media;
317 struct callout timer;
321 struct resource *intr_res;
327 uint16_t vf_ifp; /* a VF interface */
329 /* Management and WOL features */
332 /* Info about the interface */
335 uint16_t link_duplex;
337 uint32_t dma_coalesce;
339 /* Multicast array pointer */
345 struct lwkt_serialize *serializes[IGB_NSERIALIZE];
346 struct lwkt_serialize main_serialize;
351 uint32_t sts_intr_mask;
357 struct igb_tx_ring *tx_rings;
366 struct igb_rx_ring *rx_rings;
368 /* Misc stats maintained by the driver */
370 u_long mbuf_defrag_failed;
371 u_long no_tx_dma_setup;
372 u_long watchdog_events;
374 u_long device_control;
378 u_long packet_buf_alloc_rx;
379 u_long packet_buf_alloc_tx;
381 /* sysctl tree glue */
382 struct sysctl_ctx_list sysctl_ctx;
383 struct sysctl_oid *sysctl_tree;
389 struct resource *msix_mem_res;
391 struct igb_msix_data *msix_data;
394 #define IGB_ENABLE_HWRSS(sc) ((sc)->rx_ring_cnt > 1)
398 bus_dmamap_t map; /* bus_dma map for packet */
403 bus_dmamap_t map; /* bus_dma map for packet */
407 #define UPDATE_VF_REG(reg, last, cur) \
409 uint32_t new = E1000_READ_REG(hw, reg); \
411 cur += 0x100000000LL; \
413 cur &= 0xFFFFFFFF00000000LL; \
417 #define IGB_IS_OACTIVE(txr) ((txr)->tx_avail < (txr)->oact_lo_desc)
418 #define IGB_IS_NOT_OACTIVE(txr) ((txr)->tx_avail >= (txr)->oact_hi_desc)
420 #endif /* _IF_IGB_H_ */