1 /* $FreeBSD: src/sys/dev/iir/iir_pci.c,v 1.3.2.3 2002/05/05 08:18:12 asmodai Exp $ */
2 /* $DragonFly: src/sys/dev/raid/iir/iir_pci.c,v 1.5 2005/10/12 17:35:54 dillon Exp $ */
4 * Copyright (c) 2000-01 Intel Corporation
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34 * iir_pci.c: PCI Bus Attachment for Intel Integrated RAID Controller driver
36 * Written by: Achim Leubner <achim.leubner@intel.com>
37 * Fixes/Additions: Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com>
42 #ident "$Id: iir_pci.c 1.1 2001/05/22 20:14:12 achim Exp $"
44 /* #include "opt_iir.h" */
46 #include <sys/param.h>
47 #include <sys/systm.h>
48 #include <sys/kernel.h>
49 #include <sys/module.h>
52 #include <machine/bus_memio.h>
53 #include <machine/bus_pio.h>
54 #include <machine/bus.h>
55 #include <machine/resource.h>
56 #include <machine/clock.h>
59 #include <bus/pci/pcireg.h>
60 #include <bus/pci/pcivar.h>
62 #include <bus/cam/scsi/scsi_all.h>
66 /* Mapping registers for various areas */
67 #define PCI_DPMEM PCIR_MAPS
69 /* Product numbers for Fibre-Channel are greater than or equal to 0x200 */
70 #define GDT_PCI_PRODUCT_FC 0x200
72 /* PCI SRAM structure */
73 #define GDT_MAGIC 0x00 /* u_int32_t, controller ID from BIOS */
74 #define GDT_NEED_DEINIT 0x04 /* u_int16_t, switch between BIOS/driver */
75 #define GDT_SWITCH_SUPPORT 0x06 /* u_int8_t, see GDT_NEED_DEINIT */
76 #define GDT_OS_USED 0x10 /* u_int8_t [16], OS code per service */
77 #define GDT_FW_MAGIC 0x3c /* u_int8_t, controller ID from firmware */
78 #define GDT_SRAM_SZ 0x40
80 /* DPRAM PCI controllers */
81 #define GDT_DPR_IF 0x00 /* interface area */
82 #define GDT_6SR (0xff0 - GDT_SRAM_SZ)
83 #define GDT_SEMA1 0xff1 /* volatile u_int8_t, command semaphore */
84 #define GDT_IRQEN 0xff5 /* u_int8_t, board interrupts enable */
85 #define GDT_EVENT 0xff8 /* u_int8_t, release event */
86 #define GDT_IRQDEL 0xffc /* u_int8_t, acknowledge board interrupt */
87 #define GDT_DPRAM_SZ 0x1000
89 /* PLX register structure (new PCI controllers) */
90 #define GDT_CFG_REG 0x00 /* u_int8_t, DPRAM cfg. (2: < 1MB, 0: any) */
91 #define GDT_SEMA0_REG 0x40 /* volatile u_int8_t, command semaphore */
92 #define GDT_SEMA1_REG 0x41 /* volatile u_int8_t, status semaphore */
93 #define GDT_PLX_STATUS 0x44 /* volatile u_int16_t, command status */
94 #define GDT_PLX_SERVICE 0x46 /* u_int16_t, service */
95 #define GDT_PLX_INFO 0x48 /* u_int32_t [2], additional info */
96 #define GDT_LDOOR_REG 0x60 /* u_int8_t, PCI to local doorbell */
97 #define GDT_EDOOR_REG 0x64 /* volatile u_int8_t, local to PCI doorbell */
98 #define GDT_CONTROL0 0x68 /* u_int8_t, control0 register (unused) */
99 #define GDT_CONTROL1 0x69 /* u_int8_t, board interrupts enable */
100 #define GDT_PLX_SZ 0x80
102 /* DPRAM new PCI controllers */
103 #define GDT_IC 0x00 /* interface */
104 #define GDT_PCINEW_6SR (0x4000 - GDT_SRAM_SZ)
106 #define GDT_PCINEW_SZ 0x4000
108 /* i960 register structure (PCI MPR controllers) */
109 #define GDT_MPR_SEMA0 0x10 /* volatile u_int8_t, command semaphore */
110 #define GDT_MPR_SEMA1 0x12 /* volatile u_int8_t, status semaphore */
111 #define GDT_MPR_STATUS 0x14 /* volatile u_int16_t, command status */
112 #define GDT_MPR_SERVICE 0x16 /* u_int16_t, service */
113 #define GDT_MPR_INFO 0x18 /* u_int32_t [2], additional info */
114 #define GDT_MPR_LDOOR 0x20 /* u_int8_t, PCI to local doorbell */
115 #define GDT_MPR_EDOOR 0x2c /* volatile u_int8_t, locl to PCI doorbell */
116 #define GDT_EDOOR_EN 0x34 /* u_int8_t, board interrupts enable */
117 #define GDT_SEVERITY 0xefc /* u_int8_t, event severity */
118 #define GDT_EVT_BUF 0xf00 /* u_int8_t [256], event buffer */
119 #define GDT_I960_SZ 0x1000
121 /* DPRAM PCI MPR controllers */
122 #define GDT_I960R 0x00 /* 4KB i960 registers */
123 #define GDT_MPR_IC GDT_I960_SZ
124 /* i960 register area */
125 #define GDT_MPR_6SR (GDT_I960_SZ + 0x3000 - GDT_SRAM_SZ)
127 #define GDT_MPR_SZ (0x3000 - GDT_SRAM_SZ)
129 static int iir_pci_probe(device_t dev);
130 static int iir_pci_attach(device_t dev);
132 void gdt_pci_enable_intr(struct gdt_softc *);
134 void gdt_mpr_copy_cmd(struct gdt_softc *, struct gdt_ccb *);
135 u_int8_t gdt_mpr_get_status(struct gdt_softc *);
136 void gdt_mpr_intr(struct gdt_softc *, struct gdt_intr_ctx *);
137 void gdt_mpr_release_event(struct gdt_softc *);
138 void gdt_mpr_set_sema0(struct gdt_softc *);
139 int gdt_mpr_test_busy(struct gdt_softc *);
141 static device_method_t iir_pci_methods[] = {
142 /* Device interface */
143 DEVMETHOD(device_probe, iir_pci_probe),
144 DEVMETHOD(device_attach, iir_pci_attach),
149 static driver_t iir_pci_driver =
153 sizeof(struct gdt_softc)
156 static devclass_t iir_devclass;
158 DRIVER_MODULE(iir, pci, iir_pci_driver, iir_devclass, 0, 0);
161 iir_pci_probe(device_t dev)
163 if (pci_get_vendor(dev) == INTEL_VENDOR_ID &&
164 pci_get_device(dev) == INTEL_DEVICE_ID_IIR) {
165 device_set_desc(dev, "Intel Integrated RAID Controller");
168 if (pci_get_vendor(dev) == GDT_VENDOR_ID &&
169 ((pci_get_device(dev) >= GDT_DEVICE_ID_MIN &&
170 pci_get_device(dev) <= GDT_DEVICE_ID_MAX) ||
171 pci_get_device(dev) == GDT_DEVICE_ID_NEWRX)) {
172 device_set_desc(dev, "ICP Disk Array Controller");
180 iir_pci_attach(device_t dev)
182 struct gdt_softc *gdt;
183 struct resource *io = NULL, *irq = NULL;
184 int retries, rid, error = 0;
190 io = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 0, ~0, 1, RF_ACTIVE);
192 device_printf(dev, "can't allocate register resources\n");
199 irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
200 RF_ACTIVE | RF_SHAREABLE);
202 device_printf(dev, "can't find IRQ value\n");
207 gdt = device_get_softc(dev);
208 bzero(gdt, sizeof(struct gdt_softc));
209 gdt->sc_init_level = 0;
210 gdt->sc_dpmemt = rman_get_bustag(io);
211 gdt->sc_dpmemh = rman_get_bushandle(io);
212 gdt->sc_dpmembase = rman_get_start(io);
213 gdt->sc_hanum = device_get_unit(dev);
214 gdt->sc_bus = pci_get_bus(dev);
215 gdt->sc_slot = pci_get_slot(dev);
216 gdt->sc_device = pci_get_device(dev);
217 gdt->sc_subdevice = pci_get_subdevice(dev);
218 gdt->sc_class = GDT_MPR;
220 if (gdt->sc_device >= GDT_PCI_PRODUCT_FC)
221 gdt->sc_class |= GDT_FC;
224 /* initialize RP controller */
225 /* check and reset interface area */
226 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC,
227 htole32(GDT_MPR_MAGIC));
228 if (bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC) !=
229 htole32(GDT_MPR_MAGIC)) {
230 printf("cannot access DPMEM at 0x%x (shadowed?)\n",
235 bus_space_set_region_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_I960_SZ, htole32(0),
238 /* Disable everything */
239 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_EDOOR_EN,
240 bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh,
242 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_EDOOR, 0xff);
243 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_STATUS,
245 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_CMD_INDEX,
248 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_INFO,
249 htole32(gdt->sc_dpmembase));
250 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_CMD_INDX,
252 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_LDOOR, 1);
255 retries = GDT_RETRIES;
256 while (bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh,
257 GDT_MPR_IC + GDT_S_STATUS) != 0xff) {
258 if (--retries == 0) {
259 printf("DEINIT failed\n");
266 protocol = (u_int8_t)letoh32(bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh,
267 GDT_MPR_IC + GDT_S_INFO));
268 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_STATUS,
270 if (protocol != GDT_PROTOCOL_VERSION) {
271 printf("unsupported protocol %d\n", protocol);
276 /* special commnd to controller BIOS */
277 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_INFO,
279 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh,
280 GDT_MPR_IC + GDT_S_INFO + sizeof (u_int32_t), htole32(0));
281 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh,
282 GDT_MPR_IC + GDT_S_INFO + 2 * sizeof (u_int32_t),
284 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh,
285 GDT_MPR_IC + GDT_S_INFO + 3 * sizeof (u_int32_t),
287 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_CMD_INDX,
289 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_LDOOR, 1);
292 retries = GDT_RETRIES;
293 while (bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh,
294 GDT_MPR_IC + GDT_S_STATUS) != 0xfe) {
295 if (--retries == 0) {
296 printf("initialization error\n");
303 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_STATUS,
306 gdt->sc_ic_all_size = GDT_MPR_SZ;
308 gdt->sc_copy_cmd = gdt_mpr_copy_cmd;
309 gdt->sc_get_status = gdt_mpr_get_status;
310 gdt->sc_intr = gdt_mpr_intr;
311 gdt->sc_release_event = gdt_mpr_release_event;
312 gdt->sc_set_sema0 = gdt_mpr_set_sema0;
313 gdt->sc_test_busy = gdt_mpr_test_busy;
315 /* Allocate a dmatag representing the capabilities of this attachment */
316 /* XXX Should be a child of the PCI bus dma tag */
317 if (bus_dma_tag_create(/*parent*/NULL, /*alignemnt*/1, /*boundary*/0,
318 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
319 /*highaddr*/BUS_SPACE_MAXADDR,
320 /*filter*/NULL, /*filterarg*/NULL,
321 /*maxsize*/BUS_SPACE_MAXSIZE_32BIT,
322 /*nsegments*/GDT_MAXSG,
323 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
324 /*flags*/0, &gdt->sc_parent_dmat) != 0) {
328 gdt->sc_init_level++;
330 if (iir_init(gdt) != 0) {
336 /* Register with the XPT */
339 /* associate interrupt handler */
340 error = bus_setup_intr(dev, irq, 0, iir_intr, gdt, &ih, NULL);
342 device_printf(dev, "Unable to register interrupt handler\n");
347 gdt_pci_enable_intr(gdt);
352 bus_release_resource( dev, SYS_RES_IRQ, 0, irq );
355 bus_release_resource( dev, SYS_RES_MEMORY, rid, io );
361 /* Enable interrupts */
363 gdt_pci_enable_intr(struct gdt_softc *gdt)
365 GDT_DPRINTF(GDT_D_INTR, ("gdt_pci_enable_intr(%p) ", gdt));
367 switch(GDT_CLASS(gdt)) {
369 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh,
370 GDT_MPR_EDOOR, 0xff);
371 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_EDOOR_EN,
372 bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh,
380 * MPR PCI controller-specific functions
384 gdt_mpr_copy_cmd(struct gdt_softc *gdt, struct gdt_ccb *ccb)
386 u_int16_t cp_count = roundup(gdt->sc_cmd_len, sizeof (u_int32_t));
387 u_int16_t dp_offset = gdt->sc_cmd_off;
388 u_int16_t cmd_no = gdt->sc_cmd_cnt++;
390 GDT_DPRINTF(GDT_D_CMD, ("gdt_mpr_copy_cmd(%p) ", gdt));
392 gdt->sc_cmd_off += cp_count;
394 bus_space_write_2(gdt->sc_dpmemt, gdt->sc_dpmemh,
395 GDT_MPR_IC + GDT_COMM_QUEUE + cmd_no * GDT_COMM_Q_SZ + GDT_OFFSET,
396 htole16(GDT_DPMEM_COMMAND_OFFSET + dp_offset));
397 bus_space_write_2(gdt->sc_dpmemt, gdt->sc_dpmemh,
398 GDT_MPR_IC + GDT_COMM_QUEUE + cmd_no * GDT_COMM_Q_SZ + GDT_SERV_ID,
399 htole16(ccb->gc_service));
400 bus_space_write_region_4(gdt->sc_dpmemt, gdt->sc_dpmemh,
401 GDT_MPR_IC + GDT_DPR_CMD + dp_offset,
402 (u_int32_t *)gdt->sc_cmd, cp_count >> 2);
406 gdt_mpr_get_status(struct gdt_softc *gdt)
408 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_get_status(%p) ", gdt));
410 return bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_EDOOR);
414 gdt_mpr_intr(struct gdt_softc *gdt, struct gdt_intr_ctx *ctx)
418 GDT_DPRINTF(GDT_D_INTR, ("gdt_mpr_intr(%p) ", gdt));
420 if (ctx->istatus & 0x80) { /* error flag */
421 ctx->istatus &= ~0x80;
422 ctx->cmd_status = bus_space_read_2(gdt->sc_dpmemt,
423 gdt->sc_dpmemh, GDT_MPR_STATUS);
424 } else /* no error */
425 ctx->cmd_status = GDT_S_OK;
428 bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_INFO);
430 bus_space_read_2(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_SERVICE);
432 bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh,
433 GDT_MPR_INFO + sizeof (u_int32_t));
436 if (ctx->istatus == GDT_ASYNCINDEX) {
437 if (ctx->service != GDT_SCREENSERVICE &&
438 (gdt->sc_fw_vers & 0xff) >= 0x1a) {
439 gdt->sc_dvr.severity =
440 bus_space_read_1(gdt->sc_dpmemt,gdt->sc_dpmemh, GDT_SEVERITY);
441 for (i = 0; i < 256; ++i) {
442 gdt->sc_dvr.event_string[i] =
443 bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh,
445 if (gdt->sc_dvr.event_string[i] == 0)
450 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_EDOOR, 0xff);
451 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_SEMA1, 0);
455 gdt_mpr_release_event(struct gdt_softc *gdt)
457 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_release_event(%p) ", gdt));
459 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_LDOOR, 1);
463 gdt_mpr_set_sema0(struct gdt_softc *gdt)
465 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_set_sema0(%p) ", gdt));
467 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_SEMA0, 1);
471 gdt_mpr_test_busy(struct gdt_softc *gdt)
473 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_test_busy(%p) ", gdt));
475 return (bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh,