2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 * $FreeBSD: head/sys/dev/drm2/radeon/r100.c 255573 2013-09-14 17:24:41Z dumbbell $
31 #include <uapi_drm/radeon_drm.h>
32 #include "radeon_reg.h"
34 #include "radeon_asic.h"
41 #include <linux/firmware.h>
42 #include <linux/module.h>
44 #include "r100_reg_safe.h"
45 #include "rn50_reg_safe.h"
48 #define FIRMWARE_R100 "radeonkmsfw_R100_cp"
49 #define FIRMWARE_R200 "radeonkmsfw_R200_cp"
50 #define FIRMWARE_R300 "radeonkmsfw_R300_cp"
51 #define FIRMWARE_R420 "radeonkmsfw_R420_cp"
52 #define FIRMWARE_RS690 "radeonkmsfw_RS690_cp"
53 #define FIRMWARE_RS600 "radeonkmsfw_RS600_cp"
54 #define FIRMWARE_R520 "radeonkmsfw_R520_cp"
56 MODULE_FIRMWARE(FIRMWARE_R100);
57 MODULE_FIRMWARE(FIRMWARE_R200);
58 MODULE_FIRMWARE(FIRMWARE_R300);
59 MODULE_FIRMWARE(FIRMWARE_R420);
60 MODULE_FIRMWARE(FIRMWARE_RS690);
61 MODULE_FIRMWARE(FIRMWARE_RS600);
62 MODULE_FIRMWARE(FIRMWARE_R520);
64 #include "r100_track.h"
66 /* This files gather functions specifics to:
67 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
68 * and others in some cases.
71 static bool r100_is_in_vblank(struct radeon_device *rdev, int crtc)
74 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)
79 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)
86 static bool r100_is_counter_moving(struct radeon_device *rdev, int crtc)
91 vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
92 vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
94 vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
95 vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
104 * r100_wait_for_vblank - vblank wait asic callback.
106 * @rdev: radeon_device pointer
107 * @crtc: crtc to wait for vblank on
109 * Wait for vblank on the requested crtc (r1xx-r4xx).
111 void r100_wait_for_vblank(struct radeon_device *rdev, int crtc)
115 if (crtc >= rdev->num_crtc)
119 if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN))
122 if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN))
126 /* depending on when we hit vblank, we may be close to active; if so,
127 * wait for another frame.
129 while (r100_is_in_vblank(rdev, crtc)) {
130 if (i++ % 100 == 0) {
131 if (!r100_is_counter_moving(rdev, crtc))
136 while (!r100_is_in_vblank(rdev, crtc)) {
137 if (i++ % 100 == 0) {
138 if (!r100_is_counter_moving(rdev, crtc))
145 * r100_page_flip - pageflip callback.
147 * @rdev: radeon_device pointer
148 * @crtc_id: crtc to cleanup pageflip on
149 * @crtc_base: new address of the crtc (GPU MC address)
151 * Does the actual pageflip (r1xx-r4xx).
152 * During vblank we take the crtc lock and wait for the update_pending
153 * bit to go high, when it does, we release the lock, and allow the
154 * double buffered update to take place.
156 void r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
158 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
159 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
162 /* Lock the graphics update lock */
163 /* update the scanout addresses */
164 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
166 /* Wait for update_pending to go high. */
167 for (i = 0; i < rdev->usec_timeout; i++) {
168 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
172 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
174 /* Unlock the lock, so double-buffering can take place inside vblank */
175 tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
176 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
181 * r100_page_flip_pending - check if page flip is still pending
183 * @rdev: radeon_device pointer
184 * @crtc_id: crtc to check
186 * Check if the last pagefilp is still pending (r1xx-r4xx).
187 * Returns the current update pending status.
189 bool r100_page_flip_pending(struct radeon_device *rdev, int crtc_id)
191 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
193 /* Return current update_pending status: */
194 return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) &
195 RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET);
199 * r100_pm_get_dynpm_state - look up dynpm power state callback.
201 * @rdev: radeon_device pointer
203 * Look up the optimal power state based on the
204 * current state of the GPU (r1xx-r5xx).
205 * Used for dynpm only.
207 void r100_pm_get_dynpm_state(struct radeon_device *rdev)
210 rdev->pm.dynpm_can_upclock = true;
211 rdev->pm.dynpm_can_downclock = true;
213 switch (rdev->pm.dynpm_planned_action) {
214 case DYNPM_ACTION_MINIMUM:
215 rdev->pm.requested_power_state_index = 0;
216 rdev->pm.dynpm_can_downclock = false;
218 case DYNPM_ACTION_DOWNCLOCK:
219 if (rdev->pm.current_power_state_index == 0) {
220 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
221 rdev->pm.dynpm_can_downclock = false;
223 if (rdev->pm.active_crtc_count > 1) {
224 for (i = 0; i < rdev->pm.num_power_states; i++) {
225 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
227 else if (i >= rdev->pm.current_power_state_index) {
228 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
231 rdev->pm.requested_power_state_index = i;
236 rdev->pm.requested_power_state_index =
237 rdev->pm.current_power_state_index - 1;
239 /* don't use the power state if crtcs are active and no display flag is set */
240 if ((rdev->pm.active_crtc_count > 0) &&
241 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
242 RADEON_PM_MODE_NO_DISPLAY)) {
243 rdev->pm.requested_power_state_index++;
246 case DYNPM_ACTION_UPCLOCK:
247 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
248 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
249 rdev->pm.dynpm_can_upclock = false;
251 if (rdev->pm.active_crtc_count > 1) {
252 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
253 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
255 else if (i <= rdev->pm.current_power_state_index) {
256 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
259 rdev->pm.requested_power_state_index = i;
264 rdev->pm.requested_power_state_index =
265 rdev->pm.current_power_state_index + 1;
268 case DYNPM_ACTION_DEFAULT:
269 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
270 rdev->pm.dynpm_can_upclock = false;
272 case DYNPM_ACTION_NONE:
274 DRM_ERROR("Requested mode for not defined action\n");
277 /* only one clock mode per power state */
278 rdev->pm.requested_clock_mode_index = 0;
280 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
281 rdev->pm.power_state[rdev->pm.requested_power_state_index].
282 clock_info[rdev->pm.requested_clock_mode_index].sclk,
283 rdev->pm.power_state[rdev->pm.requested_power_state_index].
284 clock_info[rdev->pm.requested_clock_mode_index].mclk,
285 rdev->pm.power_state[rdev->pm.requested_power_state_index].
290 * r100_pm_init_profile - Initialize power profiles callback.
292 * @rdev: radeon_device pointer
294 * Initialize the power states used in profile mode
296 * Used for profile mode only.
298 void r100_pm_init_profile(struct radeon_device *rdev)
301 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
302 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
303 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
304 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
306 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
307 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
308 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
309 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
311 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
312 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
313 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
314 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
316 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
317 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
318 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
319 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
321 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
322 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
323 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
324 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
326 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
327 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
328 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
329 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
331 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
332 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
333 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
334 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
338 * r100_pm_misc - set additional pm hw parameters callback.
340 * @rdev: radeon_device pointer
342 * Set non-clock parameters associated with a power state
343 * (voltage, pcie lanes, etc.) (r1xx-r4xx).
345 void r100_pm_misc(struct radeon_device *rdev)
347 int requested_index = rdev->pm.requested_power_state_index;
348 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
349 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
350 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
352 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
353 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
354 tmp = RREG32(voltage->gpio.reg);
355 if (voltage->active_high)
356 tmp |= voltage->gpio.mask;
358 tmp &= ~(voltage->gpio.mask);
359 WREG32(voltage->gpio.reg, tmp);
361 udelay(voltage->delay);
363 tmp = RREG32(voltage->gpio.reg);
364 if (voltage->active_high)
365 tmp &= ~voltage->gpio.mask;
367 tmp |= voltage->gpio.mask;
368 WREG32(voltage->gpio.reg, tmp);
370 udelay(voltage->delay);
374 sclk_cntl = RREG32_PLL(SCLK_CNTL);
375 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
376 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
377 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
378 sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
379 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
380 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
381 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
382 sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
384 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
385 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
386 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
387 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
388 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
390 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
392 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
393 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
394 if (voltage->delay) {
395 sclk_more_cntl |= VOLTAGE_DROP_SYNC;
396 switch (voltage->delay) {
398 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
401 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
404 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
407 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
411 sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
413 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
415 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
416 sclk_cntl &= ~FORCE_HDP;
418 sclk_cntl |= FORCE_HDP;
420 WREG32_PLL(SCLK_CNTL, sclk_cntl);
421 WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
422 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
425 if ((rdev->flags & RADEON_IS_PCIE) &&
426 !(rdev->flags & RADEON_IS_IGP) &&
427 rdev->asic->pm.set_pcie_lanes &&
429 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
430 radeon_set_pcie_lanes(rdev,
432 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
437 * r100_pm_prepare - pre-power state change callback.
439 * @rdev: radeon_device pointer
441 * Prepare for a power state change (r1xx-r4xx).
443 void r100_pm_prepare(struct radeon_device *rdev)
445 struct drm_device *ddev = rdev->ddev;
446 struct drm_crtc *crtc;
447 struct radeon_crtc *radeon_crtc;
450 /* disable any active CRTCs */
451 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
452 radeon_crtc = to_radeon_crtc(crtc);
453 if (radeon_crtc->enabled) {
454 if (radeon_crtc->crtc_id) {
455 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
456 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
457 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
459 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
460 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
461 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
468 * r100_pm_finish - post-power state change callback.
470 * @rdev: radeon_device pointer
472 * Clean up after a power state change (r1xx-r4xx).
474 void r100_pm_finish(struct radeon_device *rdev)
476 struct drm_device *ddev = rdev->ddev;
477 struct drm_crtc *crtc;
478 struct radeon_crtc *radeon_crtc;
481 /* enable any active CRTCs */
482 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
483 radeon_crtc = to_radeon_crtc(crtc);
484 if (radeon_crtc->enabled) {
485 if (radeon_crtc->crtc_id) {
486 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
487 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
488 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
490 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
491 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
492 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
499 * r100_gui_idle - gui idle callback.
501 * @rdev: radeon_device pointer
503 * Check of the GUI (2D/3D engines) are idle (r1xx-r5xx).
504 * Returns true if idle, false if not.
506 bool r100_gui_idle(struct radeon_device *rdev)
508 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
514 /* hpd for digital panel detect/disconnect */
516 * r100_hpd_sense - hpd sense callback.
518 * @rdev: radeon_device pointer
519 * @hpd: hpd (hotplug detect) pin
521 * Checks if a digital monitor is connected (r1xx-r4xx).
522 * Returns true if connected, false if not connected.
524 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
526 bool connected = false;
530 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
534 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
544 * r100_hpd_set_polarity - hpd set polarity callback.
546 * @rdev: radeon_device pointer
547 * @hpd: hpd (hotplug detect) pin
549 * Set the polarity of the hpd pin (r1xx-r4xx).
551 void r100_hpd_set_polarity(struct radeon_device *rdev,
552 enum radeon_hpd_id hpd)
555 bool connected = r100_hpd_sense(rdev, hpd);
559 tmp = RREG32(RADEON_FP_GEN_CNTL);
561 tmp &= ~RADEON_FP_DETECT_INT_POL;
563 tmp |= RADEON_FP_DETECT_INT_POL;
564 WREG32(RADEON_FP_GEN_CNTL, tmp);
567 tmp = RREG32(RADEON_FP2_GEN_CNTL);
569 tmp &= ~RADEON_FP2_DETECT_INT_POL;
571 tmp |= RADEON_FP2_DETECT_INT_POL;
572 WREG32(RADEON_FP2_GEN_CNTL, tmp);
580 * r100_hpd_init - hpd setup callback.
582 * @rdev: radeon_device pointer
584 * Setup the hpd pins used by the card (r1xx-r4xx).
585 * Set the polarity, and enable the hpd interrupts.
587 void r100_hpd_init(struct radeon_device *rdev)
589 struct drm_device *dev = rdev->ddev;
590 struct drm_connector *connector;
593 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
594 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
595 enable |= 1 << radeon_connector->hpd.hpd;
596 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
598 radeon_irq_kms_enable_hpd(rdev, enable);
602 * r100_hpd_fini - hpd tear down callback.
604 * @rdev: radeon_device pointer
606 * Tear down the hpd pins used by the card (r1xx-r4xx).
607 * Disable the hpd interrupts.
609 void r100_hpd_fini(struct radeon_device *rdev)
611 struct drm_device *dev = rdev->ddev;
612 struct drm_connector *connector;
613 unsigned disable = 0;
615 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
616 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
617 disable |= 1 << radeon_connector->hpd.hpd;
619 radeon_irq_kms_disable_hpd(rdev, disable);
625 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
627 /* TODO: can we do somethings here ? */
628 /* It seems hw only cache one entry so we should discard this
629 * entry otherwise if first GPU GART read hit this entry it
630 * could end up in wrong address. */
633 int r100_pci_gart_init(struct radeon_device *rdev)
637 if (rdev->gart.ptr) {
638 WARN(1, "R100 PCI GART already initialized\n");
641 /* Initialize common gart structure */
642 r = radeon_gart_init(rdev);
645 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
646 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
647 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
648 return radeon_gart_table_ram_alloc(rdev);
651 int r100_pci_gart_enable(struct radeon_device *rdev)
655 /* discard memory request outside of configured range */
656 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
657 WREG32(RADEON_AIC_CNTL, tmp);
658 /* set address range for PCI address translate */
659 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
660 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
661 /* set PCI GART page-table base address */
662 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
663 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
664 WREG32(RADEON_AIC_CNTL, tmp);
665 r100_pci_gart_tlb_flush(rdev);
666 DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n",
667 (unsigned)(rdev->mc.gtt_size >> 20),
668 (unsigned long long)rdev->gart.table_addr);
669 rdev->gart.ready = true;
673 void r100_pci_gart_disable(struct radeon_device *rdev)
677 /* discard memory request outside of configured range */
678 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
679 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
680 WREG32(RADEON_AIC_LO_ADDR, 0);
681 WREG32(RADEON_AIC_HI_ADDR, 0);
684 void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i,
685 uint64_t addr, uint32_t flags)
687 u32 *gtt = rdev->gart.ptr;
688 gtt[i] = cpu_to_le32(lower_32_bits(addr));
691 void r100_pci_gart_fini(struct radeon_device *rdev)
693 radeon_gart_fini(rdev);
694 r100_pci_gart_disable(rdev);
695 radeon_gart_table_ram_free(rdev);
698 int r100_irq_set(struct radeon_device *rdev)
702 if (!rdev->irq.installed) {
703 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
704 WREG32(R_000040_GEN_INT_CNTL, 0);
707 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
708 tmp |= RADEON_SW_INT_ENABLE;
710 if (rdev->irq.crtc_vblank_int[0] ||
711 atomic_read(&rdev->irq.pflip[0])) {
712 tmp |= RADEON_CRTC_VBLANK_MASK;
714 if (rdev->irq.crtc_vblank_int[1] ||
715 atomic_read(&rdev->irq.pflip[1])) {
716 tmp |= RADEON_CRTC2_VBLANK_MASK;
718 if (rdev->irq.hpd[0]) {
719 tmp |= RADEON_FP_DETECT_MASK;
721 if (rdev->irq.hpd[1]) {
722 tmp |= RADEON_FP2_DETECT_MASK;
724 WREG32(RADEON_GEN_INT_CNTL, tmp);
728 void r100_irq_disable(struct radeon_device *rdev)
732 WREG32(R_000040_GEN_INT_CNTL, 0);
733 /* Wait and acknowledge irq */
735 tmp = RREG32(R_000044_GEN_INT_STATUS);
736 WREG32(R_000044_GEN_INT_STATUS, tmp);
739 static uint32_t r100_irq_ack(struct radeon_device *rdev)
741 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
742 uint32_t irq_mask = RADEON_SW_INT_TEST |
743 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
744 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
747 WREG32(RADEON_GEN_INT_STATUS, irqs);
749 return irqs & irq_mask;
752 irqreturn_t r100_irq_process(struct radeon_device *rdev)
754 uint32_t status, msi_rearm;
755 bool queue_hotplug = false;
757 status = r100_irq_ack(rdev);
761 if (rdev->shutdown) {
766 if (status & RADEON_SW_INT_TEST) {
767 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
769 /* Vertical blank interrupts */
770 if (status & RADEON_CRTC_VBLANK_STAT) {
771 if (rdev->irq.crtc_vblank_int[0]) {
772 drm_handle_vblank(rdev->ddev, 0);
773 rdev->pm.vblank_sync = true;
774 wake_up(&rdev->irq.vblank_queue);
776 if (atomic_read(&rdev->irq.pflip[0]))
777 radeon_crtc_handle_vblank(rdev, 0);
779 if (status & RADEON_CRTC2_VBLANK_STAT) {
780 if (rdev->irq.crtc_vblank_int[1]) {
781 drm_handle_vblank(rdev->ddev, 1);
782 rdev->pm.vblank_sync = true;
783 wake_up(&rdev->irq.vblank_queue);
785 if (atomic_read(&rdev->irq.pflip[1]))
786 radeon_crtc_handle_vblank(rdev, 1);
788 if (status & RADEON_FP_DETECT_STAT) {
789 queue_hotplug = true;
792 if (status & RADEON_FP2_DETECT_STAT) {
793 queue_hotplug = true;
796 status = r100_irq_ack(rdev);
799 taskqueue_enqueue(rdev->tq, &rdev->hotplug_work);
800 if (rdev->msi_enabled) {
801 switch (rdev->family) {
804 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
805 WREG32(RADEON_AIC_CNTL, msi_rearm);
806 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
809 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
816 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
819 return RREG32(RADEON_CRTC_CRNT_FRAME);
821 return RREG32(RADEON_CRTC2_CRNT_FRAME);
825 * r100_ring_hdp_flush - flush Host Data Path via the ring buffer
826 * rdev: radeon device structure
827 * ring: ring buffer struct for emitting packets
829 static void r100_ring_hdp_flush(struct radeon_device *rdev, struct radeon_ring *ring)
831 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
832 radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
833 RADEON_HDP_READ_BUFFER_INVALIDATE);
834 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
835 radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
838 /* Who ever call radeon_fence_emit should call ring_lock and ask
839 * for enough space (today caller are ib schedule and buffer move) */
840 void r100_fence_ring_emit(struct radeon_device *rdev,
841 struct radeon_fence *fence)
843 struct radeon_ring *ring = &rdev->ring[fence->ring];
845 /* We have to make sure that caches are flushed before
846 * CPU might read something from VRAM. */
847 radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
848 radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL);
849 radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
850 radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL);
851 /* Wait until IDLE & CLEAN */
852 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
853 radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
854 r100_ring_hdp_flush(rdev, ring);
855 /* Emit fence sequence & fire IRQ */
856 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
857 radeon_ring_write(ring, fence->seq);
858 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
859 radeon_ring_write(ring, RADEON_SW_INT_FIRE);
862 bool r100_semaphore_ring_emit(struct radeon_device *rdev,
863 struct radeon_ring *ring,
864 struct radeon_semaphore *semaphore,
867 /* Unused on older asics, since we don't have semaphores or multiple rings */
872 int r100_copy_blit(struct radeon_device *rdev,
875 unsigned num_gpu_pages,
876 struct radeon_fence **fence)
878 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
880 uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
882 uint32_t stride_pixels;
887 /* radeon limited to 16k stride */
888 stride_bytes &= 0x3fff;
889 /* radeon pitch is /64 */
890 pitch = stride_bytes / 64;
891 stride_pixels = stride_bytes / 4;
892 num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
894 /* Ask for enough room for blit + flush + fence */
895 ndw = 64 + (10 * num_loops);
896 r = radeon_ring_lock(rdev, ring, ndw);
898 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
901 while (num_gpu_pages > 0) {
902 cur_pages = num_gpu_pages;
903 if (cur_pages > 8191) {
906 num_gpu_pages -= cur_pages;
908 /* pages are in Y direction - height
909 page width in X direction - width */
910 radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8));
911 radeon_ring_write(ring,
912 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
913 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
914 RADEON_GMC_SRC_CLIPPING |
915 RADEON_GMC_DST_CLIPPING |
916 RADEON_GMC_BRUSH_NONE |
917 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
918 RADEON_GMC_SRC_DATATYPE_COLOR |
920 RADEON_DP_SRC_SOURCE_MEMORY |
921 RADEON_GMC_CLR_CMP_CNTL_DIS |
922 RADEON_GMC_WR_MSK_DIS);
923 radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10));
924 radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10));
925 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
926 radeon_ring_write(ring, 0);
927 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
928 radeon_ring_write(ring, num_gpu_pages);
929 radeon_ring_write(ring, num_gpu_pages);
930 radeon_ring_write(ring, cur_pages | (stride_pixels << 16));
932 radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
933 radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL);
934 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
935 radeon_ring_write(ring,
936 RADEON_WAIT_2D_IDLECLEAN |
937 RADEON_WAIT_HOST_IDLECLEAN |
938 RADEON_WAIT_DMA_GUI_IDLE);
940 r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX);
942 radeon_ring_unlock_commit(rdev, ring, false);
946 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
951 for (i = 0; i < rdev->usec_timeout; i++) {
952 tmp = RREG32(R_000E40_RBBM_STATUS);
953 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
961 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
965 r = radeon_ring_lock(rdev, ring, 2);
969 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
970 radeon_ring_write(ring,
971 RADEON_ISYNC_ANY2D_IDLE3D |
972 RADEON_ISYNC_ANY3D_IDLE2D |
973 RADEON_ISYNC_WAIT_IDLEGUI |
974 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
975 radeon_ring_unlock_commit(rdev, ring, false);
979 /* Load the microcode for the CP */
980 static int r100_cp_init_microcode(struct radeon_device *rdev)
982 const char *fw_name = NULL;
987 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
988 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
989 (rdev->family == CHIP_RS200)) {
990 DRM_INFO("Loading R100 Microcode\n");
991 fw_name = FIRMWARE_R100;
992 } else if ((rdev->family == CHIP_R200) ||
993 (rdev->family == CHIP_RV250) ||
994 (rdev->family == CHIP_RV280) ||
995 (rdev->family == CHIP_RS300)) {
996 DRM_INFO("Loading R200 Microcode\n");
997 fw_name = FIRMWARE_R200;
998 } else if ((rdev->family == CHIP_R300) ||
999 (rdev->family == CHIP_R350) ||
1000 (rdev->family == CHIP_RV350) ||
1001 (rdev->family == CHIP_RV380) ||
1002 (rdev->family == CHIP_RS400) ||
1003 (rdev->family == CHIP_RS480)) {
1004 DRM_INFO("Loading R300 Microcode\n");
1005 fw_name = FIRMWARE_R300;
1006 } else if ((rdev->family == CHIP_R420) ||
1007 (rdev->family == CHIP_R423) ||
1008 (rdev->family == CHIP_RV410)) {
1009 DRM_INFO("Loading R400 Microcode\n");
1010 fw_name = FIRMWARE_R420;
1011 } else if ((rdev->family == CHIP_RS690) ||
1012 (rdev->family == CHIP_RS740)) {
1013 DRM_INFO("Loading RS690/RS740 Microcode\n");
1014 fw_name = FIRMWARE_RS690;
1015 } else if (rdev->family == CHIP_RS600) {
1016 DRM_INFO("Loading RS600 Microcode\n");
1017 fw_name = FIRMWARE_RS600;
1018 } else if ((rdev->family == CHIP_RV515) ||
1019 (rdev->family == CHIP_R520) ||
1020 (rdev->family == CHIP_RV530) ||
1021 (rdev->family == CHIP_R580) ||
1022 (rdev->family == CHIP_RV560) ||
1023 (rdev->family == CHIP_RV570)) {
1024 DRM_INFO("Loading R500 Microcode\n");
1025 fw_name = FIRMWARE_R520;
1028 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
1030 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
1032 } else if (rdev->me_fw->datasize % 8) {
1034 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
1035 rdev->me_fw->datasize, fw_name);
1037 release_firmware(rdev->me_fw);
1043 u32 r100_gfx_get_rptr(struct radeon_device *rdev,
1044 struct radeon_ring *ring)
1048 if (rdev->wb.enabled)
1049 rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
1051 rptr = RREG32(RADEON_CP_RB_RPTR);
1056 u32 r100_gfx_get_wptr(struct radeon_device *rdev,
1057 struct radeon_ring *ring)
1061 wptr = RREG32(RADEON_CP_RB_WPTR);
1066 void r100_gfx_set_wptr(struct radeon_device *rdev,
1067 struct radeon_ring *ring)
1069 WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1070 (void)RREG32(RADEON_CP_RB_WPTR);
1074 * r100_cp_fini_microcode - drop the firmware image reference
1076 * @rdev: radeon_device pointer
1078 * Drop the me firmware image reference.
1079 * Called at driver shutdown.
1081 static void r100_cp_fini_microcode (struct radeon_device *rdev)
1083 release_firmware(rdev->me_fw);
1087 static void r100_cp_load_microcode(struct radeon_device *rdev)
1089 const __be32 *fw_data;
1092 if (r100_gui_wait_for_idle(rdev)) {
1093 printk(KERN_WARNING "Failed to wait GUI idle while "
1094 "programming pipes. Bad things might happen.\n");
1098 size = rdev->me_fw->datasize / 4;
1099 fw_data = (const __be32 *)rdev->me_fw->data;
1100 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
1101 for (i = 0; i < size; i += 2) {
1102 WREG32(RADEON_CP_ME_RAM_DATAH,
1103 be32_to_cpup(&fw_data[i]));
1104 WREG32(RADEON_CP_ME_RAM_DATAL,
1105 be32_to_cpup(&fw_data[i + 1]));
1110 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1112 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1116 unsigned pre_write_timer;
1117 unsigned pre_write_limit;
1118 unsigned indirect2_start;
1119 unsigned indirect1_start;
1123 if (r100_debugfs_cp_init(rdev)) {
1124 DRM_ERROR("Failed to register debugfs file for CP !\n");
1127 r = r100_cp_init_microcode(rdev);
1129 DRM_ERROR("Failed to load firmware!\n");
1134 /* Align ring size */
1135 rb_bufsz = order_base_2(ring_size / 8);
1136 ring_size = (1 << (rb_bufsz + 1)) * 4;
1137 r100_cp_load_microcode(rdev);
1138 r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,
1143 /* Each time the cp read 1024 bytes (16 dword/quadword) update
1144 * the rptr copy in system ram */
1146 /* cp will read 128bytes at a time (4 dwords) */
1148 ring->align_mask = 16 - 1;
1149 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
1150 pre_write_timer = 64;
1151 /* Force CP_RB_WPTR write if written more than one time before the
1154 pre_write_limit = 0;
1155 /* Setup the cp cache like this (cache size is 96 dwords) :
1157 * INDIRECT1 16 to 79
1158 * INDIRECT2 80 to 95
1159 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1160 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
1161 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1162 * Idea being that most of the gpu cmd will be through indirect1 buffer
1163 * so it gets the bigger cache.
1165 indirect2_start = 80;
1166 indirect1_start = 16;
1168 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
1169 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
1170 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
1171 REG_SET(RADEON_MAX_FETCH, max_fetch));
1173 tmp |= RADEON_BUF_SWAP_32BIT;
1175 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
1177 /* Set ring address */
1178 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr);
1179 WREG32(RADEON_CP_RB_BASE, ring->gpu_addr);
1180 /* Force read & write ptr to 0 */
1181 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
1182 WREG32(RADEON_CP_RB_RPTR_WR, 0);
1184 WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1186 /* set the wb address whether it's enabled or not */
1187 WREG32(R_00070C_CP_RB_RPTR_ADDR,
1188 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1189 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1191 if (rdev->wb.enabled)
1192 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1194 tmp |= RADEON_RB_NO_UPDATE;
1195 WREG32(R_000770_SCRATCH_UMSK, 0);
1198 WREG32(RADEON_CP_RB_CNTL, tmp);
1200 /* Set cp mode to bus mastering & enable cp*/
1201 WREG32(RADEON_CP_CSQ_MODE,
1202 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1203 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1204 WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1205 WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
1206 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1208 /* at this point everything should be setup correctly to enable master */
1209 pci_enable_busmaster(rdev->dev);
1211 radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1212 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
1214 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1218 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1220 if (!ring->rptr_save_reg /* not resuming from suspend */
1221 && radeon_ring_supports_scratch_reg(rdev, ring)) {
1222 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
1224 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
1225 ring->rptr_save_reg = 0;
1231 void r100_cp_fini(struct radeon_device *rdev)
1233 if (r100_cp_wait_for_idle(rdev)) {
1234 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1237 r100_cp_disable(rdev);
1238 radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg);
1239 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1240 DRM_INFO("radeon: cp finalized\n");
1243 void r100_cp_disable(struct radeon_device *rdev)
1246 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1247 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1248 WREG32(RADEON_CP_CSQ_MODE, 0);
1249 WREG32(RADEON_CP_CSQ_CNTL, 0);
1250 WREG32(R_000770_SCRATCH_UMSK, 0);
1251 if (r100_gui_wait_for_idle(rdev)) {
1252 printk(KERN_WARNING "Failed to wait GUI idle while "
1253 "programming pipes. Bad things might happen.\n");
1260 int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
1261 struct radeon_cs_packet *pkt,
1268 struct radeon_cs_reloc *reloc;
1271 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1273 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1275 radeon_cs_dump_packet(p, pkt);
1279 value = radeon_get_ib_value(p, idx);
1280 tmp = value & 0x003fffff;
1281 tmp += (((u32)reloc->gpu_offset) >> 10);
1283 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1284 if (reloc->tiling_flags & RADEON_TILING_MACRO)
1285 tile_flags |= RADEON_DST_TILE_MACRO;
1286 if (reloc->tiling_flags & RADEON_TILING_MICRO) {
1287 if (reg == RADEON_SRC_PITCH_OFFSET) {
1288 DRM_ERROR("Cannot src blit from microtiled surface\n");
1289 radeon_cs_dump_packet(p, pkt);
1292 tile_flags |= RADEON_DST_TILE_MICRO;
1296 p->ib.ptr[idx] = (value & 0x3fc00000) | tmp;
1298 p->ib.ptr[idx] = (value & 0xffc00000) | tmp;
1302 int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
1303 struct radeon_cs_packet *pkt,
1307 struct radeon_cs_reloc *reloc;
1308 struct r100_cs_track *track;
1310 volatile uint32_t *ib;
1314 track = (struct r100_cs_track *)p->track;
1315 c = radeon_get_ib_value(p, idx++) & 0x1F;
1317 DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
1319 radeon_cs_dump_packet(p, pkt);
1322 track->num_arrays = c;
1323 for (i = 0; i < (c - 1); i+=2, idx+=3) {
1324 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1326 DRM_ERROR("No reloc for packet3 %d\n",
1328 radeon_cs_dump_packet(p, pkt);
1331 idx_value = radeon_get_ib_value(p, idx);
1332 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
1334 track->arrays[i + 0].esize = idx_value >> 8;
1335 track->arrays[i + 0].robj = reloc->robj;
1336 track->arrays[i + 0].esize &= 0x7F;
1337 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1339 DRM_ERROR("No reloc for packet3 %d\n",
1341 radeon_cs_dump_packet(p, pkt);
1344 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset);
1345 track->arrays[i + 1].robj = reloc->robj;
1346 track->arrays[i + 1].esize = idx_value >> 24;
1347 track->arrays[i + 1].esize &= 0x7F;
1350 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1352 DRM_ERROR("No reloc for packet3 %d\n",
1354 radeon_cs_dump_packet(p, pkt);
1357 idx_value = radeon_get_ib_value(p, idx);
1358 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
1359 track->arrays[i + 0].robj = reloc->robj;
1360 track->arrays[i + 0].esize = idx_value >> 8;
1361 track->arrays[i + 0].esize &= 0x7F;
1366 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1367 struct radeon_cs_packet *pkt,
1368 const unsigned *auth, unsigned n,
1369 radeon_packet0_check_t check)
1378 /* Check that register fall into register range
1379 * determined by the number of entry (n) in the
1380 * safe register bitmap.
1382 if (pkt->one_reg_wr) {
1383 if ((reg >> 7) > n) {
1387 if (((reg + (pkt->count << 2)) >> 7) > n) {
1391 for (i = 0; i <= pkt->count; i++, idx++) {
1393 m = 1 << ((reg >> 2) & 31);
1395 r = check(p, pkt, idx, reg);
1400 if (pkt->one_reg_wr) {
1401 if (!(auth[j] & m)) {
1412 * r100_cs_packet_next_vline() - parse userspace VLINE packet
1413 * @parser: parser structure holding parsing context.
1415 * Userspace sends a special sequence for VLINE waits.
1416 * PACKET0 - VLINE_START_END + value
1417 * PACKET0 - WAIT_UNTIL +_value
1418 * RELOC (P3) - crtc_id in reloc.
1420 * This function parses this and relocates the VLINE START END
1421 * and WAIT UNTIL packets to the correct crtc.
1422 * It also detects a switched off crtc and nulls out the
1423 * wait in that case.
1425 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1427 struct drm_crtc *crtc;
1428 struct radeon_crtc *radeon_crtc;
1429 struct radeon_cs_packet p3reloc, waitreloc;
1432 uint32_t header, h_idx, reg;
1433 volatile uint32_t *ib;
1437 /* parse the wait until */
1438 r = radeon_cs_packet_parse(p, &waitreloc, p->idx);
1442 /* check its a wait until and only 1 count */
1443 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1444 waitreloc.count != 0) {
1445 DRM_ERROR("vline wait had illegal wait until segment\n");
1449 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1450 DRM_ERROR("vline wait had illegal wait until\n");
1454 /* jump over the NOP */
1455 r = radeon_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1460 p->idx += waitreloc.count + 2;
1461 p->idx += p3reloc.count + 2;
1463 header = radeon_get_ib_value(p, h_idx);
1464 crtc_id = radeon_get_ib_value(p, h_idx + 5);
1465 reg = R100_CP_PACKET0_GET_REG(header);
1466 crtc = drm_crtc_find(p->rdev->ddev, crtc_id);
1468 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1471 radeon_crtc = to_radeon_crtc(crtc);
1472 crtc_id = radeon_crtc->crtc_id;
1474 if (!crtc->enabled) {
1475 /* if the CRTC isn't enabled - we need to nop out the wait until */
1476 ib[h_idx + 2] = PACKET2(0);
1477 ib[h_idx + 3] = PACKET2(0);
1478 } else if (crtc_id == 1) {
1480 case AVIVO_D1MODE_VLINE_START_END:
1481 header &= ~R300_CP_PACKET0_REG_MASK;
1482 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1484 case RADEON_CRTC_GUI_TRIG_VLINE:
1485 header &= ~R300_CP_PACKET0_REG_MASK;
1486 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1489 DRM_ERROR("unknown crtc reloc\n");
1493 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1499 static int r100_get_vtx_size(uint32_t vtx_fmt)
1503 /* ordered according to bits in spec */
1504 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1506 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1508 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1510 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1512 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1514 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1516 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1518 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1520 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1522 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1524 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1526 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1528 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1530 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1532 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1535 if (vtx_fmt & (0x7 << 15))
1536 vtx_size += (vtx_fmt >> 15) & 0x7;
1537 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1539 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1541 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1543 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1545 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1547 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1552 static int r100_packet0_check(struct radeon_cs_parser *p,
1553 struct radeon_cs_packet *pkt,
1554 unsigned idx, unsigned reg)
1556 struct radeon_cs_reloc *reloc;
1557 struct r100_cs_track *track;
1558 volatile uint32_t *ib;
1566 track = (struct r100_cs_track *)p->track;
1568 idx_value = radeon_get_ib_value(p, idx);
1571 case RADEON_CRTC_GUI_TRIG_VLINE:
1572 r = r100_cs_packet_parse_vline(p);
1574 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1576 radeon_cs_dump_packet(p, pkt);
1580 /* FIXME: only allow PACKET3 blit? easier to check for out of
1582 case RADEON_DST_PITCH_OFFSET:
1583 case RADEON_SRC_PITCH_OFFSET:
1584 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1588 case RADEON_RB3D_DEPTHOFFSET:
1589 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1591 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1593 radeon_cs_dump_packet(p, pkt);
1596 track->zb.robj = reloc->robj;
1597 track->zb.offset = idx_value;
1598 track->zb_dirty = true;
1599 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1601 case RADEON_RB3D_COLOROFFSET:
1602 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1604 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1606 radeon_cs_dump_packet(p, pkt);
1609 track->cb[0].robj = reloc->robj;
1610 track->cb[0].offset = idx_value;
1611 track->cb_dirty = true;
1612 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1614 case RADEON_PP_TXOFFSET_0:
1615 case RADEON_PP_TXOFFSET_1:
1616 case RADEON_PP_TXOFFSET_2:
1617 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1618 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1620 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1622 radeon_cs_dump_packet(p, pkt);
1625 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1626 if (reloc->tiling_flags & RADEON_TILING_MACRO)
1627 tile_flags |= RADEON_TXO_MACRO_TILE;
1628 if (reloc->tiling_flags & RADEON_TILING_MICRO)
1629 tile_flags |= RADEON_TXO_MICRO_TILE_X2;
1631 tmp = idx_value & ~(0x7 << 2);
1633 ib[idx] = tmp + ((u32)reloc->gpu_offset);
1635 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1636 track->textures[i].robj = reloc->robj;
1637 track->tex_dirty = true;
1639 case RADEON_PP_CUBIC_OFFSET_T0_0:
1640 case RADEON_PP_CUBIC_OFFSET_T0_1:
1641 case RADEON_PP_CUBIC_OFFSET_T0_2:
1642 case RADEON_PP_CUBIC_OFFSET_T0_3:
1643 case RADEON_PP_CUBIC_OFFSET_T0_4:
1644 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1645 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1647 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1649 radeon_cs_dump_packet(p, pkt);
1652 track->textures[0].cube_info[i].offset = idx_value;
1653 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1654 track->textures[0].cube_info[i].robj = reloc->robj;
1655 track->tex_dirty = true;
1657 case RADEON_PP_CUBIC_OFFSET_T1_0:
1658 case RADEON_PP_CUBIC_OFFSET_T1_1:
1659 case RADEON_PP_CUBIC_OFFSET_T1_2:
1660 case RADEON_PP_CUBIC_OFFSET_T1_3:
1661 case RADEON_PP_CUBIC_OFFSET_T1_4:
1662 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1663 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1665 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1667 radeon_cs_dump_packet(p, pkt);
1670 track->textures[1].cube_info[i].offset = idx_value;
1671 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1672 track->textures[1].cube_info[i].robj = reloc->robj;
1673 track->tex_dirty = true;
1675 case RADEON_PP_CUBIC_OFFSET_T2_0:
1676 case RADEON_PP_CUBIC_OFFSET_T2_1:
1677 case RADEON_PP_CUBIC_OFFSET_T2_2:
1678 case RADEON_PP_CUBIC_OFFSET_T2_3:
1679 case RADEON_PP_CUBIC_OFFSET_T2_4:
1680 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1681 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1683 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1685 radeon_cs_dump_packet(p, pkt);
1688 track->textures[2].cube_info[i].offset = idx_value;
1689 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1690 track->textures[2].cube_info[i].robj = reloc->robj;
1691 track->tex_dirty = true;
1693 case RADEON_RE_WIDTH_HEIGHT:
1694 track->maxy = ((idx_value >> 16) & 0x7FF);
1695 track->cb_dirty = true;
1696 track->zb_dirty = true;
1698 case RADEON_RB3D_COLORPITCH:
1699 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1701 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1703 radeon_cs_dump_packet(p, pkt);
1706 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1707 if (reloc->tiling_flags & RADEON_TILING_MACRO)
1708 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1709 if (reloc->tiling_flags & RADEON_TILING_MICRO)
1710 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1712 tmp = idx_value & ~(0x7 << 16);
1716 ib[idx] = idx_value;
1718 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1719 track->cb_dirty = true;
1721 case RADEON_RB3D_DEPTHPITCH:
1722 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1723 track->zb_dirty = true;
1725 case RADEON_RB3D_CNTL:
1726 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1732 track->cb[0].cpp = 1;
1737 track->cb[0].cpp = 2;
1740 track->cb[0].cpp = 4;
1743 DRM_ERROR("Invalid color buffer format (%d) !\n",
1744 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1747 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1748 track->cb_dirty = true;
1749 track->zb_dirty = true;
1751 case RADEON_RB3D_ZSTENCILCNTL:
1752 switch (idx_value & 0xf) {
1767 track->zb_dirty = true;
1769 case RADEON_RB3D_ZPASS_ADDR:
1770 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1772 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1774 radeon_cs_dump_packet(p, pkt);
1777 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1779 case RADEON_PP_CNTL:
1781 uint32_t temp = idx_value >> 4;
1782 for (i = 0; i < track->num_texture; i++)
1783 track->textures[i].enabled = !!(temp & (1 << i));
1784 track->tex_dirty = true;
1787 case RADEON_SE_VF_CNTL:
1788 track->vap_vf_cntl = idx_value;
1790 case RADEON_SE_VTX_FMT:
1791 track->vtx_size = r100_get_vtx_size(idx_value);
1793 case RADEON_PP_TEX_SIZE_0:
1794 case RADEON_PP_TEX_SIZE_1:
1795 case RADEON_PP_TEX_SIZE_2:
1796 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1797 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1798 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1799 track->tex_dirty = true;
1801 case RADEON_PP_TEX_PITCH_0:
1802 case RADEON_PP_TEX_PITCH_1:
1803 case RADEON_PP_TEX_PITCH_2:
1804 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1805 track->textures[i].pitch = idx_value + 32;
1806 track->tex_dirty = true;
1808 case RADEON_PP_TXFILTER_0:
1809 case RADEON_PP_TXFILTER_1:
1810 case RADEON_PP_TXFILTER_2:
1811 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1812 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1813 >> RADEON_MAX_MIP_LEVEL_SHIFT);
1814 tmp = (idx_value >> 23) & 0x7;
1815 if (tmp == 2 || tmp == 6)
1816 track->textures[i].roundup_w = false;
1817 tmp = (idx_value >> 27) & 0x7;
1818 if (tmp == 2 || tmp == 6)
1819 track->textures[i].roundup_h = false;
1820 track->tex_dirty = true;
1822 case RADEON_PP_TXFORMAT_0:
1823 case RADEON_PP_TXFORMAT_1:
1824 case RADEON_PP_TXFORMAT_2:
1825 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1826 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1827 track->textures[i].use_pitch = 1;
1829 track->textures[i].use_pitch = 0;
1830 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1831 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1833 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1834 track->textures[i].tex_coord_type = 2;
1835 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1836 case RADEON_TXFORMAT_I8:
1837 case RADEON_TXFORMAT_RGB332:
1838 case RADEON_TXFORMAT_Y8:
1839 track->textures[i].cpp = 1;
1840 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1842 case RADEON_TXFORMAT_AI88:
1843 case RADEON_TXFORMAT_ARGB1555:
1844 case RADEON_TXFORMAT_RGB565:
1845 case RADEON_TXFORMAT_ARGB4444:
1846 case RADEON_TXFORMAT_VYUY422:
1847 case RADEON_TXFORMAT_YVYU422:
1848 case RADEON_TXFORMAT_SHADOW16:
1849 case RADEON_TXFORMAT_LDUDV655:
1850 case RADEON_TXFORMAT_DUDV88:
1851 track->textures[i].cpp = 2;
1852 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1854 case RADEON_TXFORMAT_ARGB8888:
1855 case RADEON_TXFORMAT_RGBA8888:
1856 case RADEON_TXFORMAT_SHADOW32:
1857 case RADEON_TXFORMAT_LDUDUV8888:
1858 track->textures[i].cpp = 4;
1859 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1861 case RADEON_TXFORMAT_DXT1:
1862 track->textures[i].cpp = 1;
1863 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1865 case RADEON_TXFORMAT_DXT23:
1866 case RADEON_TXFORMAT_DXT45:
1867 track->textures[i].cpp = 1;
1868 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1871 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1872 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1873 track->tex_dirty = true;
1875 case RADEON_PP_CUBIC_FACES_0:
1876 case RADEON_PP_CUBIC_FACES_1:
1877 case RADEON_PP_CUBIC_FACES_2:
1879 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1880 for (face = 0; face < 4; face++) {
1881 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1882 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1884 track->tex_dirty = true;
1887 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1894 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1895 struct radeon_cs_packet *pkt,
1896 struct radeon_bo *robj)
1901 value = radeon_get_ib_value(p, idx + 2);
1902 if ((value + 1) > radeon_bo_size(robj)) {
1903 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1904 "(need %u have %lu) !\n",
1906 radeon_bo_size(robj));
1912 static int r100_packet3_check(struct radeon_cs_parser *p,
1913 struct radeon_cs_packet *pkt)
1915 struct radeon_cs_reloc *reloc;
1916 struct r100_cs_track *track;
1918 volatile uint32_t *ib;
1923 track = (struct r100_cs_track *)p->track;
1924 switch (pkt->opcode) {
1925 case PACKET3_3D_LOAD_VBPNTR:
1926 r = r100_packet3_load_vbpntr(p, pkt, idx);
1930 case PACKET3_INDX_BUFFER:
1931 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1933 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1934 radeon_cs_dump_packet(p, pkt);
1937 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->gpu_offset);
1938 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1944 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1945 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1947 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1948 radeon_cs_dump_packet(p, pkt);
1951 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->gpu_offset);
1952 track->num_arrays = 1;
1953 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1955 track->arrays[0].robj = reloc->robj;
1956 track->arrays[0].esize = track->vtx_size;
1958 track->max_indx = radeon_get_ib_value(p, idx+1);
1960 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1961 track->immd_dwords = pkt->count - 1;
1962 r = r100_cs_track_check(p->rdev, track);
1966 case PACKET3_3D_DRAW_IMMD:
1967 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1968 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1971 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1972 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1973 track->immd_dwords = pkt->count - 1;
1974 r = r100_cs_track_check(p->rdev, track);
1978 /* triggers drawing using in-packet vertex data */
1979 case PACKET3_3D_DRAW_IMMD_2:
1980 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1981 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1984 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1985 track->immd_dwords = pkt->count;
1986 r = r100_cs_track_check(p->rdev, track);
1990 /* triggers drawing using in-packet vertex data */
1991 case PACKET3_3D_DRAW_VBUF_2:
1992 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1993 r = r100_cs_track_check(p->rdev, track);
1997 /* triggers drawing of vertex buffers setup elsewhere */
1998 case PACKET3_3D_DRAW_INDX_2:
1999 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
2000 r = r100_cs_track_check(p->rdev, track);
2004 /* triggers drawing using indices to vertex buffer */
2005 case PACKET3_3D_DRAW_VBUF:
2006 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
2007 r = r100_cs_track_check(p->rdev, track);
2011 /* triggers drawing of vertex buffers setup elsewhere */
2012 case PACKET3_3D_DRAW_INDX:
2013 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
2014 r = r100_cs_track_check(p->rdev, track);
2018 /* triggers drawing using indices to vertex buffer */
2019 case PACKET3_3D_CLEAR_HIZ:
2020 case PACKET3_3D_CLEAR_ZMASK:
2021 if (p->rdev->hyperz_filp != p->filp)
2027 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
2033 int r100_cs_parse(struct radeon_cs_parser *p)
2035 struct radeon_cs_packet pkt;
2036 struct r100_cs_track *track;
2039 track = kzalloc(sizeof(*track), GFP_KERNEL);
2042 r100_cs_track_clear(p->rdev, track);
2045 r = radeon_cs_packet_parse(p, &pkt, p->idx);
2051 p->idx += pkt.count + 2;
2053 case RADEON_PACKET_TYPE0:
2054 if (p->rdev->family >= CHIP_R200)
2055 r = r100_cs_parse_packet0(p, &pkt,
2056 p->rdev->config.r100.reg_safe_bm,
2057 p->rdev->config.r100.reg_safe_bm_size,
2058 &r200_packet0_check);
2060 r = r100_cs_parse_packet0(p, &pkt,
2061 p->rdev->config.r100.reg_safe_bm,
2062 p->rdev->config.r100.reg_safe_bm_size,
2063 &r100_packet0_check);
2065 case RADEON_PACKET_TYPE2:
2067 case RADEON_PACKET_TYPE3:
2068 r = r100_packet3_check(p, &pkt);
2071 DRM_ERROR("Unknown packet type %d !\n",
2082 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
2088 static void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2090 DRM_ERROR("pitch %d\n", t->pitch);
2091 DRM_ERROR("use_pitch %d\n", t->use_pitch);
2092 DRM_ERROR("width %d\n", t->width);
2093 DRM_ERROR("width_11 %d\n", t->width_11);
2094 DRM_ERROR("height %d\n", t->height);
2095 DRM_ERROR("height_11 %d\n", t->height_11);
2096 DRM_ERROR("num levels %d\n", t->num_levels);
2097 DRM_ERROR("depth %d\n", t->txdepth);
2098 DRM_ERROR("bpp %d\n", t->cpp);
2099 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
2100 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
2101 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2102 DRM_ERROR("compress format %d\n", t->compress_format);
2105 static int r100_track_compress_size(int compress_format, int w, int h)
2107 int block_width, block_height, block_bytes;
2108 int wblocks, hblocks;
2115 switch (compress_format) {
2116 case R100_TRACK_COMP_DXT1:
2121 case R100_TRACK_COMP_DXT35:
2127 hblocks = (h + block_height - 1) / block_height;
2128 wblocks = (w + block_width - 1) / block_width;
2129 if (wblocks < min_wblocks)
2130 wblocks = min_wblocks;
2131 sz = wblocks * hblocks * block_bytes;
2135 static int r100_cs_track_cube(struct radeon_device *rdev,
2136 struct r100_cs_track *track, unsigned idx)
2138 unsigned face, w, h;
2139 struct radeon_bo *cube_robj;
2141 unsigned compress_format = track->textures[idx].compress_format;
2143 for (face = 0; face < 5; face++) {
2144 cube_robj = track->textures[idx].cube_info[face].robj;
2145 w = track->textures[idx].cube_info[face].width;
2146 h = track->textures[idx].cube_info[face].height;
2148 if (compress_format) {
2149 size = r100_track_compress_size(compress_format, w, h);
2152 size *= track->textures[idx].cpp;
2154 size += track->textures[idx].cube_info[face].offset;
2156 if (size > radeon_bo_size(cube_robj)) {
2157 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2158 size, radeon_bo_size(cube_robj));
2159 r100_cs_track_texture_print(&track->textures[idx]);
2166 static int r100_cs_track_texture_check(struct radeon_device *rdev,
2167 struct r100_cs_track *track)
2169 struct radeon_bo *robj;
2171 unsigned u, i, w, h, d;
2174 for (u = 0; u < track->num_texture; u++) {
2175 if (!track->textures[u].enabled)
2177 if (track->textures[u].lookup_disable)
2179 robj = track->textures[u].robj;
2181 DRM_ERROR("No texture bound to unit %u\n", u);
2185 for (i = 0; i <= track->textures[u].num_levels; i++) {
2186 if (track->textures[u].use_pitch) {
2187 if (rdev->family < CHIP_R300)
2188 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2190 w = track->textures[u].pitch / (1 << i);
2192 w = track->textures[u].width;
2193 if (rdev->family >= CHIP_RV515)
2194 w |= track->textures[u].width_11;
2196 if (track->textures[u].roundup_w)
2197 w = roundup_pow_of_two(w);
2199 h = track->textures[u].height;
2200 if (rdev->family >= CHIP_RV515)
2201 h |= track->textures[u].height_11;
2203 if (track->textures[u].roundup_h)
2204 h = roundup_pow_of_two(h);
2205 if (track->textures[u].tex_coord_type == 1) {
2206 d = (1 << track->textures[u].txdepth) / (1 << i);
2212 if (track->textures[u].compress_format) {
2214 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
2215 /* compressed textures are block based */
2219 size *= track->textures[u].cpp;
2221 switch (track->textures[u].tex_coord_type) {
2226 if (track->separate_cube) {
2227 ret = r100_cs_track_cube(rdev, track, u);
2234 DRM_ERROR("Invalid texture coordinate type %u for unit "
2235 "%u\n", track->textures[u].tex_coord_type, u);
2238 if (size > radeon_bo_size(robj)) {
2239 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2240 "%lu\n", u, size, radeon_bo_size(robj));
2241 r100_cs_track_texture_print(&track->textures[u]);
2248 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2254 unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
2256 if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
2257 !track->blend_read_enable)
2260 for (i = 0; i < num_cb; i++) {
2261 if (track->cb[i].robj == NULL) {
2262 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2265 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2266 size += track->cb[i].offset;
2267 if (size > radeon_bo_size(track->cb[i].robj)) {
2268 DRM_ERROR("[drm] Buffer too small for color buffer %d "
2269 "(need %lu have %lu) !\n", i, size,
2270 radeon_bo_size(track->cb[i].robj));
2271 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2272 i, track->cb[i].pitch, track->cb[i].cpp,
2273 track->cb[i].offset, track->maxy);
2277 track->cb_dirty = false;
2279 if (track->zb_dirty && track->z_enabled) {
2280 if (track->zb.robj == NULL) {
2281 DRM_ERROR("[drm] No buffer for z buffer !\n");
2284 size = track->zb.pitch * track->zb.cpp * track->maxy;
2285 size += track->zb.offset;
2286 if (size > radeon_bo_size(track->zb.robj)) {
2287 DRM_ERROR("[drm] Buffer too small for z buffer "
2288 "(need %lu have %lu) !\n", size,
2289 radeon_bo_size(track->zb.robj));
2290 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2291 track->zb.pitch, track->zb.cpp,
2292 track->zb.offset, track->maxy);
2296 track->zb_dirty = false;
2298 if (track->aa_dirty && track->aaresolve) {
2299 if (track->aa.robj == NULL) {
2300 DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
2303 /* I believe the format comes from colorbuffer0. */
2304 size = track->aa.pitch * track->cb[0].cpp * track->maxy;
2305 size += track->aa.offset;
2306 if (size > radeon_bo_size(track->aa.robj)) {
2307 DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
2308 "(need %lu have %lu) !\n", i, size,
2309 radeon_bo_size(track->aa.robj));
2310 DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
2311 i, track->aa.pitch, track->cb[0].cpp,
2312 track->aa.offset, track->maxy);
2316 track->aa_dirty = false;
2318 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2319 if (track->vap_vf_cntl & (1 << 14)) {
2320 nverts = track->vap_alt_nverts;
2322 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2324 switch (prim_walk) {
2326 for (i = 0; i < track->num_arrays; i++) {
2327 size = track->arrays[i].esize * track->max_indx * 4;
2328 if (track->arrays[i].robj == NULL) {
2329 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2330 "bound\n", prim_walk, i);
2333 if (size > radeon_bo_size(track->arrays[i].robj)) {
2334 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2335 "need %lu dwords have %lu dwords\n",
2336 prim_walk, i, size >> 2,
2337 radeon_bo_size(track->arrays[i].robj)
2339 DRM_ERROR("Max indices %u\n", track->max_indx);
2345 for (i = 0; i < track->num_arrays; i++) {
2346 size = track->arrays[i].esize * (nverts - 1) * 4;
2347 if (track->arrays[i].robj == NULL) {
2348 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2349 "bound\n", prim_walk, i);
2352 if (size > radeon_bo_size(track->arrays[i].robj)) {
2353 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2354 "need %lu dwords have %lu dwords\n",
2355 prim_walk, i, size >> 2,
2356 radeon_bo_size(track->arrays[i].robj)
2363 size = track->vtx_size * nverts;
2364 if (size != track->immd_dwords) {
2365 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
2366 track->immd_dwords, size);
2367 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
2368 nverts, track->vtx_size);
2373 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
2378 if (track->tex_dirty) {
2379 track->tex_dirty = false;
2380 return r100_cs_track_texture_check(rdev, track);
2385 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
2389 track->cb_dirty = true;
2390 track->zb_dirty = true;
2391 track->tex_dirty = true;
2392 track->aa_dirty = true;
2394 if (rdev->family < CHIP_R300) {
2396 if (rdev->family <= CHIP_RS200)
2397 track->num_texture = 3;
2399 track->num_texture = 6;
2401 track->separate_cube = 1;
2404 track->num_texture = 16;
2406 track->separate_cube = 0;
2407 track->aaresolve = false;
2408 track->aa.robj = NULL;
2411 for (i = 0; i < track->num_cb; i++) {
2412 track->cb[i].robj = NULL;
2413 track->cb[i].pitch = 8192;
2414 track->cb[i].cpp = 16;
2415 track->cb[i].offset = 0;
2417 track->z_enabled = true;
2418 track->zb.robj = NULL;
2419 track->zb.pitch = 8192;
2421 track->zb.offset = 0;
2422 track->vtx_size = 0x7F;
2423 track->immd_dwords = 0xFFFFFFFFUL;
2424 track->num_arrays = 11;
2425 track->max_indx = 0x00FFFFFFUL;
2426 for (i = 0; i < track->num_arrays; i++) {
2427 track->arrays[i].robj = NULL;
2428 track->arrays[i].esize = 0x7F;
2430 for (i = 0; i < track->num_texture; i++) {
2431 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
2432 track->textures[i].pitch = 16536;
2433 track->textures[i].width = 16536;
2434 track->textures[i].height = 16536;
2435 track->textures[i].width_11 = 1 << 11;
2436 track->textures[i].height_11 = 1 << 11;
2437 track->textures[i].num_levels = 12;
2438 if (rdev->family <= CHIP_RS200) {
2439 track->textures[i].tex_coord_type = 0;
2440 track->textures[i].txdepth = 0;
2442 track->textures[i].txdepth = 16;
2443 track->textures[i].tex_coord_type = 1;
2445 track->textures[i].cpp = 64;
2446 track->textures[i].robj = NULL;
2447 /* CS IB emission code makes sure texture unit are disabled */
2448 track->textures[i].enabled = false;
2449 track->textures[i].lookup_disable = false;
2450 track->textures[i].roundup_w = true;
2451 track->textures[i].roundup_h = true;
2452 if (track->separate_cube)
2453 for (face = 0; face < 5; face++) {
2454 track->textures[i].cube_info[face].robj = NULL;
2455 track->textures[i].cube_info[face].width = 16536;
2456 track->textures[i].cube_info[face].height = 16536;
2457 track->textures[i].cube_info[face].offset = 0;
2463 * Global GPU functions
2465 static void r100_errata(struct radeon_device *rdev)
2467 rdev->pll_errata = 0;
2469 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
2470 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2473 if (rdev->family == CHIP_RV100 ||
2474 rdev->family == CHIP_RS100 ||
2475 rdev->family == CHIP_RS200) {
2476 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
2480 static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
2485 for (i = 0; i < rdev->usec_timeout; i++) {
2486 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
2495 int r100_gui_wait_for_idle(struct radeon_device *rdev)
2500 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
2501 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
2502 " Bad things might happen.\n");
2504 for (i = 0; i < rdev->usec_timeout; i++) {
2505 tmp = RREG32(RADEON_RBBM_STATUS);
2506 if (!(tmp & RADEON_RBBM_ACTIVE)) {
2514 int r100_mc_wait_for_idle(struct radeon_device *rdev)
2519 for (i = 0; i < rdev->usec_timeout; i++) {
2520 /* read MC_STATUS */
2521 tmp = RREG32(RADEON_MC_STATUS);
2522 if (tmp & RADEON_MC_IDLE) {
2530 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2534 rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2535 if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2536 radeon_ring_lockup_update(rdev, ring);
2539 return radeon_ring_test_lockup(rdev, ring);
2542 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
2543 void r100_enable_bm(struct radeon_device *rdev)
2546 /* Enable bus mastering */
2547 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
2548 WREG32(RADEON_BUS_CNTL, tmp);
2551 void r100_bm_disable(struct radeon_device *rdev)
2555 /* disable bus mastering */
2556 tmp = RREG32(R_000030_BUS_CNTL);
2557 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2559 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2561 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2562 tmp = RREG32(RADEON_BUS_CNTL);
2564 pci_disable_busmaster(rdev->dev);
2568 int r100_asic_reset(struct radeon_device *rdev)
2570 struct r100_mc_save save;
2574 status = RREG32(R_000E40_RBBM_STATUS);
2575 if (!G_000E40_GUI_ACTIVE(status)) {
2578 r100_mc_stop(rdev, &save);
2579 status = RREG32(R_000E40_RBBM_STATUS);
2580 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2582 WREG32(RADEON_CP_CSQ_CNTL, 0);
2583 tmp = RREG32(RADEON_CP_RB_CNTL);
2584 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2585 WREG32(RADEON_CP_RB_RPTR_WR, 0);
2586 WREG32(RADEON_CP_RB_WPTR, 0);
2587 WREG32(RADEON_CP_RB_CNTL, tmp);
2588 /* save PCI state */
2589 pci_save_state(device_get_parent(rdev->dev));
2590 /* disable bus mastering */
2591 r100_bm_disable(rdev);
2592 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2593 S_0000F0_SOFT_RESET_RE(1) |
2594 S_0000F0_SOFT_RESET_PP(1) |
2595 S_0000F0_SOFT_RESET_RB(1));
2596 RREG32(R_0000F0_RBBM_SOFT_RESET);
2598 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2600 status = RREG32(R_000E40_RBBM_STATUS);
2601 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2603 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2604 RREG32(R_0000F0_RBBM_SOFT_RESET);
2606 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2608 status = RREG32(R_000E40_RBBM_STATUS);
2609 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2610 /* restore PCI & busmastering */
2611 pci_restore_state(device_get_parent(rdev->dev));
2612 r100_enable_bm(rdev);
2613 /* Check if GPU is idle */
2614 if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2615 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2616 dev_err(rdev->dev, "failed to reset GPU\n");
2619 dev_info(rdev->dev, "GPU reset succeed\n");
2620 r100_mc_resume(rdev, &save);
2624 void r100_set_common_regs(struct radeon_device *rdev)
2626 struct drm_device *dev = rdev->ddev;
2627 bool force_dac2 = false;
2630 /* set these so they don't interfere with anything */
2631 WREG32(RADEON_OV0_SCALE_CNTL, 0);
2632 WREG32(RADEON_SUBPIC_CNTL, 0);
2633 WREG32(RADEON_VIPH_CONTROL, 0);
2634 WREG32(RADEON_I2C_CNTL_1, 0);
2635 WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2636 WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2637 WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2639 /* always set up dac2 on rn50 and some rv100 as lots
2640 * of servers seem to wire it up to a VGA port but
2641 * don't report it in the bios connector
2644 switch (dev->pdev->device) {
2653 /* DELL triple head servers */
2654 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2655 ((dev->pdev->subsystem_device == 0x016c) ||
2656 (dev->pdev->subsystem_device == 0x016d) ||
2657 (dev->pdev->subsystem_device == 0x016e) ||
2658 (dev->pdev->subsystem_device == 0x016f) ||
2659 (dev->pdev->subsystem_device == 0x0170) ||
2660 (dev->pdev->subsystem_device == 0x017d) ||
2661 (dev->pdev->subsystem_device == 0x017e) ||
2662 (dev->pdev->subsystem_device == 0x0183) ||
2663 (dev->pdev->subsystem_device == 0x018a) ||
2664 (dev->pdev->subsystem_device == 0x019a)))
2670 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2671 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2672 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2674 /* For CRT on DAC2, don't turn it on if BIOS didn't
2675 enable it, even it's detected.
2678 /* force it to crtc0 */
2679 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2680 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2681 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2683 /* set up the TV DAC */
2684 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2685 RADEON_TV_DAC_STD_MASK |
2686 RADEON_TV_DAC_RDACPD |
2687 RADEON_TV_DAC_GDACPD |
2688 RADEON_TV_DAC_BDACPD |
2689 RADEON_TV_DAC_BGADJ_MASK |
2690 RADEON_TV_DAC_DACADJ_MASK);
2691 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2692 RADEON_TV_DAC_NHOLD |
2693 RADEON_TV_DAC_STD_PS2 |
2696 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2697 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2698 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2701 /* switch PM block to ACPI mode */
2702 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2703 tmp &= ~RADEON_PM_MODE_SEL;
2704 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2711 static void r100_vram_get_type(struct radeon_device *rdev)
2715 rdev->mc.vram_is_ddr = false;
2716 if (rdev->flags & RADEON_IS_IGP)
2717 rdev->mc.vram_is_ddr = true;
2718 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2719 rdev->mc.vram_is_ddr = true;
2720 if ((rdev->family == CHIP_RV100) ||
2721 (rdev->family == CHIP_RS100) ||
2722 (rdev->family == CHIP_RS200)) {
2723 tmp = RREG32(RADEON_MEM_CNTL);
2724 if (tmp & RV100_HALF_MODE) {
2725 rdev->mc.vram_width = 32;
2727 rdev->mc.vram_width = 64;
2729 if (rdev->flags & RADEON_SINGLE_CRTC) {
2730 rdev->mc.vram_width /= 4;
2731 rdev->mc.vram_is_ddr = true;
2733 } else if (rdev->family <= CHIP_RV280) {
2734 tmp = RREG32(RADEON_MEM_CNTL);
2735 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2736 rdev->mc.vram_width = 128;
2738 rdev->mc.vram_width = 64;
2742 rdev->mc.vram_width = 128;
2746 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2751 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2753 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2754 * that is has the 2nd generation multifunction PCI interface
2756 if (rdev->family == CHIP_RV280 ||
2757 rdev->family >= CHIP_RV350) {
2758 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2759 ~RADEON_HDP_APER_CNTL);
2760 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2761 return aper_size * 2;
2764 /* Older cards have all sorts of funny issues to deal with. First
2765 * check if it's a multifunction card by reading the PCI config
2766 * header type... Limit those to one aperture size
2768 byte = pci_read_config(rdev->dev, 0xe, 1);
2770 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2771 DRM_INFO("Limiting VRAM to one aperture\n");
2775 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2776 * have set it up. We don't write this as it's broken on some ASICs but
2777 * we expect the BIOS to have done the right thing (might be too optimistic...)
2779 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2780 return aper_size * 2;
2784 void r100_vram_init_sizes(struct radeon_device *rdev)
2786 u64 config_aper_size;
2788 /* work out accessible VRAM */
2789 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
2790 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
2791 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2792 /* FIXME we don't use the second aperture yet when we could use it */
2793 if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2794 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2795 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2796 if (rdev->flags & RADEON_IS_IGP) {
2798 /* read NB_TOM to get the amount of ram stolen for the GPU */
2799 tom = RREG32(RADEON_NB_TOM);
2800 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2801 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2802 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2804 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2805 /* Some production boards of m6 will report 0
2808 if (rdev->mc.real_vram_size == 0) {
2809 rdev->mc.real_vram_size = 8192 * 1024;
2810 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2812 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2813 * Novell bug 204882 + along with lots of ubuntu ones
2815 if (rdev->mc.aper_size > config_aper_size)
2816 config_aper_size = rdev->mc.aper_size;
2818 if (config_aper_size > rdev->mc.real_vram_size)
2819 rdev->mc.mc_vram_size = config_aper_size;
2821 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2825 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2829 temp = RREG32(RADEON_CONFIG_CNTL);
2830 if (state == false) {
2831 temp &= ~RADEON_CFG_VGA_RAM_EN;
2832 temp |= RADEON_CFG_VGA_IO_DIS;
2834 temp &= ~RADEON_CFG_VGA_IO_DIS;
2836 WREG32(RADEON_CONFIG_CNTL, temp);
2839 static void r100_mc_init(struct radeon_device *rdev)
2843 r100_vram_get_type(rdev);
2844 r100_vram_init_sizes(rdev);
2845 base = rdev->mc.aper_base;
2846 if (rdev->flags & RADEON_IS_IGP)
2847 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2848 radeon_vram_location(rdev, &rdev->mc, base);
2849 rdev->mc.gtt_base_align = 0;
2850 if (!(rdev->flags & RADEON_IS_AGP))
2851 radeon_gtt_location(rdev, &rdev->mc);
2852 radeon_update_bandwidth_info(rdev);
2857 * Indirect registers accessor
2859 void r100_pll_errata_after_index(struct radeon_device *rdev)
2861 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2862 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2863 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2867 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2869 /* This workarounds is necessary on RV100, RS100 and RS200 chips
2870 * or the chip could hang on a subsequent access
2872 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2876 /* This function is required to workaround a hardware bug in some (all?)
2877 * revisions of the R300. This workaround should be called after every
2878 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
2879 * may not be correct.
2881 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2884 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2885 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2886 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2887 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2888 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2892 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2896 spin_lock(&rdev->pll_idx_lock);
2897 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2898 r100_pll_errata_after_index(rdev);
2899 data = RREG32(RADEON_CLOCK_CNTL_DATA);
2900 r100_pll_errata_after_data(rdev);
2901 spin_unlock(&rdev->pll_idx_lock);
2905 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2907 spin_lock(&rdev->pll_idx_lock);
2908 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2909 r100_pll_errata_after_index(rdev);
2910 WREG32(RADEON_CLOCK_CNTL_DATA, v);
2911 r100_pll_errata_after_data(rdev);
2912 spin_unlock(&rdev->pll_idx_lock);
2915 static void r100_set_safe_registers(struct radeon_device *rdev)
2917 if (ASIC_IS_RN50(rdev)) {
2918 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2919 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2920 } else if (rdev->family < CHIP_R200) {
2921 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2922 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2924 r200_set_safe_registers(rdev);
2931 #if defined(CONFIG_DEBUG_FS)
2932 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2934 struct drm_info_node *node = (struct drm_info_node *) m->private;
2935 struct drm_device *dev = node->minor->dev;
2936 struct radeon_device *rdev = dev->dev_private;
2937 uint32_t reg, value;
2940 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2941 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2942 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2943 for (i = 0; i < 64; i++) {
2944 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2945 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2946 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2947 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2948 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2953 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2955 struct drm_info_node *node = (struct drm_info_node *) m->private;
2956 struct drm_device *dev = node->minor->dev;
2957 struct radeon_device *rdev = dev->dev_private;
2958 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2960 unsigned count, i, j;
2962 radeon_ring_free_size(rdev, ring);
2963 rdp = RREG32(RADEON_CP_RB_RPTR);
2964 wdp = RREG32(RADEON_CP_RB_WPTR);
2965 count = (rdp + ring->ring_size - wdp) & ring->ptr_mask;
2966 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2967 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2968 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2969 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
2970 seq_printf(m, "%u dwords in ring\n", count);
2972 for (j = 0; j <= count; j++) {
2973 i = (rdp + j) & ring->ptr_mask;
2974 seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
2981 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2983 struct drm_info_node *node = (struct drm_info_node *) m->private;
2984 struct drm_device *dev = node->minor->dev;
2985 struct radeon_device *rdev = dev->dev_private;
2986 uint32_t csq_stat, csq2_stat, tmp;
2987 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2990 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2991 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2992 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2993 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2994 r_rptr = (csq_stat >> 0) & 0x3ff;
2995 r_wptr = (csq_stat >> 10) & 0x3ff;
2996 ib1_rptr = (csq_stat >> 20) & 0x3ff;
2997 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2998 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2999 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
3000 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
3001 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
3002 seq_printf(m, "Ring rptr %u\n", r_rptr);
3003 seq_printf(m, "Ring wptr %u\n", r_wptr);
3004 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
3005 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
3006 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
3007 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
3008 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
3009 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
3010 seq_printf(m, "Ring fifo:\n");
3011 for (i = 0; i < 256; i++) {
3012 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3013 tmp = RREG32(RADEON_CP_CSQ_DATA);
3014 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
3016 seq_printf(m, "Indirect1 fifo:\n");
3017 for (i = 256; i <= 512; i++) {
3018 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3019 tmp = RREG32(RADEON_CP_CSQ_DATA);
3020 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
3022 seq_printf(m, "Indirect2 fifo:\n");
3023 for (i = 640; i < ib1_wptr; i++) {
3024 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3025 tmp = RREG32(RADEON_CP_CSQ_DATA);
3026 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
3031 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
3033 struct drm_info_node *node = (struct drm_info_node *) m->private;
3034 struct drm_device *dev = node->minor->dev;
3035 struct radeon_device *rdev = dev->dev_private;
3038 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
3039 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
3040 tmp = RREG32(RADEON_MC_FB_LOCATION);
3041 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
3042 tmp = RREG32(RADEON_BUS_CNTL);
3043 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
3044 tmp = RREG32(RADEON_MC_AGP_LOCATION);
3045 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
3046 tmp = RREG32(RADEON_AGP_BASE);
3047 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
3048 tmp = RREG32(RADEON_HOST_PATH_CNTL);
3049 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
3050 tmp = RREG32(0x01D0);
3051 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
3052 tmp = RREG32(RADEON_AIC_LO_ADDR);
3053 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
3054 tmp = RREG32(RADEON_AIC_HI_ADDR);
3055 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
3056 tmp = RREG32(0x01E4);
3057 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
3061 static struct drm_info_list r100_debugfs_rbbm_list[] = {
3062 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
3065 static struct drm_info_list r100_debugfs_cp_list[] = {
3066 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
3067 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
3070 static struct drm_info_list r100_debugfs_mc_info_list[] = {
3071 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
3075 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
3077 #if defined(CONFIG_DEBUG_FS)
3078 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
3084 int r100_debugfs_cp_init(struct radeon_device *rdev)
3086 #if defined(CONFIG_DEBUG_FS)
3087 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
3093 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
3095 #if defined(CONFIG_DEBUG_FS)
3096 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
3102 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
3103 uint32_t tiling_flags, uint32_t pitch,
3104 uint32_t offset, uint32_t obj_size)
3106 int surf_index = reg * 16;
3109 if (rdev->family <= CHIP_RS200) {
3110 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3111 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3112 flags |= RADEON_SURF_TILE_COLOR_BOTH;
3113 if (tiling_flags & RADEON_TILING_MACRO)
3114 flags |= RADEON_SURF_TILE_COLOR_MACRO;
3115 /* setting pitch to 0 disables tiling */
3116 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3119 } else if (rdev->family <= CHIP_RV280) {
3120 if (tiling_flags & (RADEON_TILING_MACRO))
3121 flags |= R200_SURF_TILE_COLOR_MACRO;
3122 if (tiling_flags & RADEON_TILING_MICRO)
3123 flags |= R200_SURF_TILE_COLOR_MICRO;
3125 if (tiling_flags & RADEON_TILING_MACRO)
3126 flags |= R300_SURF_TILE_MACRO;
3127 if (tiling_flags & RADEON_TILING_MICRO)
3128 flags |= R300_SURF_TILE_MICRO;
3131 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
3132 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
3133 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
3134 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
3136 /* r100/r200 divide by 16 */
3137 if (rdev->family < CHIP_R300)
3138 flags |= pitch / 16;
3143 DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
3144 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
3145 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
3146 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
3150 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
3152 int surf_index = reg * 16;
3153 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
3156 void r100_bandwidth_update(struct radeon_device *rdev)
3158 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
3159 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
3160 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
3161 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
3162 fixed20_12 memtcas_ff[8] = {
3167 dfixed_init_half(1),
3168 dfixed_init_half(2),
3171 fixed20_12 memtcas_rs480_ff[8] = {
3177 dfixed_init_half(1),
3178 dfixed_init_half(2),
3179 dfixed_init_half(3),
3181 fixed20_12 memtcas2_ff[8] = {
3191 fixed20_12 memtrbs[8] = {
3193 dfixed_init_half(1),
3195 dfixed_init_half(2),
3197 dfixed_init_half(3),
3201 fixed20_12 memtrbs_r4xx[8] = {
3211 fixed20_12 min_mem_eff;
3212 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
3213 fixed20_12 cur_latency_mclk, cur_latency_sclk;
3214 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
3215 disp_drain_rate2, read_return_rate;
3216 fixed20_12 time_disp1_drop_priority;
3218 int cur_size = 16; /* in octawords */
3219 int critical_point = 0, critical_point2;
3220 /* uint32_t read_return_rate, time_disp1_drop_priority; */
3221 int stop_req, max_stop_req;
3222 struct drm_display_mode *mode1 = NULL;
3223 struct drm_display_mode *mode2 = NULL;
3224 uint32_t pixel_bytes1 = 0;
3225 uint32_t pixel_bytes2 = 0;
3227 radeon_update_display_priority(rdev);
3229 if (rdev->mode_info.crtcs[0]->base.enabled) {
3230 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
3231 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.primary->fb->bits_per_pixel / 8;
3233 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3234 if (rdev->mode_info.crtcs[1]->base.enabled) {
3235 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
3236 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.primary->fb->bits_per_pixel / 8;
3240 min_mem_eff.full = dfixed_const_8(0);
3242 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
3243 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
3244 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
3245 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
3246 /* check crtc enables */
3248 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
3250 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
3251 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
3255 * determine is there is enough bw for current mode
3257 sclk_ff = rdev->pm.sclk;
3258 mclk_ff = rdev->pm.mclk;
3260 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
3261 temp_ff.full = dfixed_const(temp);
3262 mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
3266 peak_disp_bw.full = 0;
3268 temp_ff.full = dfixed_const(1000);
3269 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
3270 pix_clk.full = dfixed_div(pix_clk, temp_ff);
3271 temp_ff.full = dfixed_const(pixel_bytes1);
3272 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
3275 temp_ff.full = dfixed_const(1000);
3276 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
3277 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
3278 temp_ff.full = dfixed_const(pixel_bytes2);
3279 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
3282 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
3283 if (peak_disp_bw.full >= mem_bw.full) {
3284 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
3285 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
3288 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
3289 temp = RREG32(RADEON_MEM_TIMING_CNTL);
3290 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
3291 mem_trcd = ((temp >> 2) & 0x3) + 1;
3292 mem_trp = ((temp & 0x3)) + 1;
3293 mem_tras = ((temp & 0x70) >> 4) + 1;
3294 } else if (rdev->family == CHIP_R300 ||
3295 rdev->family == CHIP_R350) { /* r300, r350 */
3296 mem_trcd = (temp & 0x7) + 1;
3297 mem_trp = ((temp >> 8) & 0x7) + 1;
3298 mem_tras = ((temp >> 11) & 0xf) + 4;
3299 } else if (rdev->family == CHIP_RV350 ||
3300 rdev->family <= CHIP_RV380) {
3302 mem_trcd = (temp & 0x7) + 3;
3303 mem_trp = ((temp >> 8) & 0x7) + 3;
3304 mem_tras = ((temp >> 11) & 0xf) + 6;
3305 } else if (rdev->family == CHIP_R420 ||
3306 rdev->family == CHIP_R423 ||
3307 rdev->family == CHIP_RV410) {
3309 mem_trcd = (temp & 0xf) + 3;
3312 mem_trp = ((temp >> 8) & 0xf) + 3;
3315 mem_tras = ((temp >> 12) & 0x1f) + 6;
3318 } else { /* RV200, R200 */
3319 mem_trcd = (temp & 0x7) + 1;
3320 mem_trp = ((temp >> 8) & 0x7) + 1;
3321 mem_tras = ((temp >> 12) & 0xf) + 4;
3324 trcd_ff.full = dfixed_const(mem_trcd);
3325 trp_ff.full = dfixed_const(mem_trp);
3326 tras_ff.full = dfixed_const(mem_tras);
3328 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
3329 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3330 data = (temp & (7 << 20)) >> 20;
3331 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
3332 if (rdev->family == CHIP_RS480) /* don't think rs400 */
3333 tcas_ff = memtcas_rs480_ff[data];
3335 tcas_ff = memtcas_ff[data];
3337 tcas_ff = memtcas2_ff[data];
3339 if (rdev->family == CHIP_RS400 ||
3340 rdev->family == CHIP_RS480) {
3341 /* extra cas latency stored in bits 23-25 0-4 clocks */
3342 data = (temp >> 23) & 0x7;
3344 tcas_ff.full += dfixed_const(data);
3347 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
3348 /* on the R300, Tcas is included in Trbs.
3350 temp = RREG32(RADEON_MEM_CNTL);
3351 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
3353 if (R300_MEM_USE_CD_CH_ONLY & temp) {
3354 temp = RREG32(R300_MC_IND_INDEX);
3355 temp &= ~R300_MC_IND_ADDR_MASK;
3356 temp |= R300_MC_READ_CNTL_CD_mcind;
3357 WREG32(R300_MC_IND_INDEX, temp);
3358 temp = RREG32(R300_MC_IND_DATA);
3359 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
3361 temp = RREG32(R300_MC_READ_CNTL_AB);
3362 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3365 temp = RREG32(R300_MC_READ_CNTL_AB);
3366 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3368 if (rdev->family == CHIP_RV410 ||
3369 rdev->family == CHIP_R420 ||
3370 rdev->family == CHIP_R423)
3371 trbs_ff = memtrbs_r4xx[data];
3373 trbs_ff = memtrbs[data];
3374 tcas_ff.full += trbs_ff.full;
3377 sclk_eff_ff.full = sclk_ff.full;
3379 if (rdev->flags & RADEON_IS_AGP) {
3380 fixed20_12 agpmode_ff;
3381 agpmode_ff.full = dfixed_const(radeon_agpmode);
3382 temp_ff.full = dfixed_const_666(16);
3383 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
3385 /* TODO PCIE lanes may affect this - agpmode == 16?? */
3387 if (ASIC_IS_R300(rdev)) {
3388 sclk_delay_ff.full = dfixed_const(250);
3390 if ((rdev->family == CHIP_RV100) ||
3391 rdev->flags & RADEON_IS_IGP) {
3392 if (rdev->mc.vram_is_ddr)
3393 sclk_delay_ff.full = dfixed_const(41);
3395 sclk_delay_ff.full = dfixed_const(33);
3397 if (rdev->mc.vram_width == 128)
3398 sclk_delay_ff.full = dfixed_const(57);
3400 sclk_delay_ff.full = dfixed_const(41);
3404 mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
3406 if (rdev->mc.vram_is_ddr) {
3407 if (rdev->mc.vram_width == 32) {
3408 k1.full = dfixed_const(40);
3411 k1.full = dfixed_const(20);
3415 k1.full = dfixed_const(40);
3419 temp_ff.full = dfixed_const(2);
3420 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
3421 temp_ff.full = dfixed_const(c);
3422 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
3423 temp_ff.full = dfixed_const(4);
3424 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
3425 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
3426 mc_latency_mclk.full += k1.full;
3428 mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
3429 mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
3432 HW cursor time assuming worst case of full size colour cursor.
3434 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
3435 temp_ff.full += trcd_ff.full;
3436 if (temp_ff.full < tras_ff.full)
3437 temp_ff.full = tras_ff.full;
3438 cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
3440 temp_ff.full = dfixed_const(cur_size);
3441 cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
3443 Find the total latency for the display data.
3445 disp_latency_overhead.full = dfixed_const(8);
3446 disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
3447 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
3448 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
3450 if (mc_latency_mclk.full > mc_latency_sclk.full)
3451 disp_latency.full = mc_latency_mclk.full;
3453 disp_latency.full = mc_latency_sclk.full;
3455 /* setup Max GRPH_STOP_REQ default value */
3456 if (ASIC_IS_RV100(rdev))
3457 max_stop_req = 0x5c;
3459 max_stop_req = 0x7c;
3463 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
3464 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
3466 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
3468 if (stop_req > max_stop_req)
3469 stop_req = max_stop_req;
3472 Find the drain rate of the display buffer.
3474 temp_ff.full = dfixed_const((16/pixel_bytes1));
3475 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
3478 Find the critical point of the display buffer.
3480 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
3481 crit_point_ff.full += dfixed_const_half(0);
3483 critical_point = dfixed_trunc(crit_point_ff);
3485 if (rdev->disp_priority == 2) {
3490 The critical point should never be above max_stop_req-4. Setting
3491 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3493 if (max_stop_req - critical_point < 4)
3496 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3497 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3498 critical_point = 0x10;
3501 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3502 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3503 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3504 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3505 if ((rdev->family == CHIP_R350) &&
3506 (stop_req > 0x15)) {
3509 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3510 temp |= RADEON_GRPH_BUFFER_SIZE;
3511 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
3512 RADEON_GRPH_CRITICAL_AT_SOF |
3513 RADEON_GRPH_STOP_CNTL);
3515 Write the result into the register.
3517 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3518 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3521 if ((rdev->family == CHIP_RS400) ||
3522 (rdev->family == CHIP_RS480)) {
3523 /* attempt to program RS400 disp regs correctly ??? */
3524 temp = RREG32(RS400_DISP1_REG_CNTL);
3525 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3526 RS400_DISP1_STOP_REQ_LEVEL_MASK);
3527 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3528 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3529 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3530 temp = RREG32(RS400_DMIF_MEM_CNTL1);
3531 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3532 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3533 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3534 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3535 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
3539 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
3540 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
3541 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3546 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3548 if (stop_req > max_stop_req)
3549 stop_req = max_stop_req;
3552 Find the drain rate of the display buffer.
3554 temp_ff.full = dfixed_const((16/pixel_bytes2));
3555 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
3557 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3558 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3559 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3560 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3561 if ((rdev->family == CHIP_R350) &&
3562 (stop_req > 0x15)) {
3565 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3566 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3567 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
3568 RADEON_GRPH_CRITICAL_AT_SOF |
3569 RADEON_GRPH_STOP_CNTL);
3571 if ((rdev->family == CHIP_RS100) ||
3572 (rdev->family == CHIP_RS200))
3573 critical_point2 = 0;
3575 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3576 temp_ff.full = dfixed_const(temp);
3577 temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
3578 if (sclk_ff.full < temp_ff.full)
3579 temp_ff.full = sclk_ff.full;
3581 read_return_rate.full = temp_ff.full;
3584 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
3585 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
3587 time_disp1_drop_priority.full = 0;
3589 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
3590 crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3591 crit_point_ff.full += dfixed_const_half(0);
3593 critical_point2 = dfixed_trunc(crit_point_ff);
3595 if (rdev->disp_priority == 2) {
3596 critical_point2 = 0;
3599 if (max_stop_req - critical_point2 < 4)
3600 critical_point2 = 0;
3604 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3605 /* some R300 cards have problem with this set to 0 */
3606 critical_point2 = 0x10;
3609 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3610 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3612 if ((rdev->family == CHIP_RS400) ||
3613 (rdev->family == CHIP_RS480)) {
3615 /* attempt to program RS400 disp2 regs correctly ??? */
3616 temp = RREG32(RS400_DISP2_REQ_CNTL1);
3617 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3618 RS400_DISP2_STOP_REQ_LEVEL_MASK);
3619 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3620 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3621 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3622 temp = RREG32(RS400_DISP2_REQ_CNTL2);
3623 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3624 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3625 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3626 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3627 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3629 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3630 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3631 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
3632 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3635 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
3636 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3640 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3647 r = radeon_scratch_get(rdev, &scratch);
3649 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3652 WREG32(scratch, 0xCAFEDEAD);
3653 r = radeon_ring_lock(rdev, ring, 2);
3655 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3656 radeon_scratch_free(rdev, scratch);
3659 radeon_ring_write(ring, PACKET0(scratch, 0));
3660 radeon_ring_write(ring, 0xDEADBEEF);
3661 radeon_ring_unlock_commit(rdev, ring, false);
3662 for (i = 0; i < rdev->usec_timeout; i++) {
3663 tmp = RREG32(scratch);
3664 if (tmp == 0xDEADBEEF) {
3669 if (i < rdev->usec_timeout) {
3670 DRM_INFO("ring test succeeded in %d usecs\n", i);
3672 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
3676 radeon_scratch_free(rdev, scratch);
3680 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3682 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3684 if (ring->rptr_save_reg) {
3685 u32 next_rptr = ring->wptr + 2 + 3;
3686 radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0));
3687 radeon_ring_write(ring, next_rptr);
3690 radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1));
3691 radeon_ring_write(ring, ib->gpu_addr);
3692 radeon_ring_write(ring, ib->length_dw);
3695 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3697 struct radeon_ib ib;
3703 r = radeon_scratch_get(rdev, &scratch);
3705 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3708 WREG32(scratch, 0xCAFEDEAD);
3709 r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256);
3711 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3714 ib.ptr[0] = PACKET0(scratch, 0);
3715 ib.ptr[1] = 0xDEADBEEF;
3716 ib.ptr[2] = PACKET2(0);
3717 ib.ptr[3] = PACKET2(0);
3718 ib.ptr[4] = PACKET2(0);
3719 ib.ptr[5] = PACKET2(0);
3720 ib.ptr[6] = PACKET2(0);
3721 ib.ptr[7] = PACKET2(0);
3723 r = radeon_ib_schedule(rdev, &ib, NULL, false);
3725 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3728 r = radeon_fence_wait(ib.fence, false);
3730 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3733 for (i = 0; i < rdev->usec_timeout; i++) {
3734 tmp = RREG32(scratch);
3735 if (tmp == 0xDEADBEEF) {
3740 if (i < rdev->usec_timeout) {
3741 DRM_INFO("ib test succeeded in %u usecs\n", i);
3743 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3748 radeon_ib_free(rdev, &ib);
3750 radeon_scratch_free(rdev, scratch);
3754 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3756 /* Shutdown CP we shouldn't need to do that but better be safe than
3759 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3760 WREG32(R_000740_CP_CSQ_CNTL, 0);
3762 /* Save few CRTC registers */
3763 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3764 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3765 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3766 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3767 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3768 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3769 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3772 /* Disable VGA aperture access */
3773 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3774 /* Disable cursor, overlay, crtc */
3775 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3776 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3777 S_000054_CRTC_DISPLAY_DIS(1));
3778 WREG32(R_000050_CRTC_GEN_CNTL,
3779 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3780 S_000050_CRTC_DISP_REQ_EN_B(1));
3781 WREG32(R_000420_OV0_SCALE_CNTL,
3782 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3783 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3784 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3785 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3786 S_000360_CUR2_LOCK(1));
3787 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3788 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3789 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3790 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3791 WREG32(R_000360_CUR2_OFFSET,
3792 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3796 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3798 /* Update base address for crtc */
3799 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3800 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3801 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3803 /* Restore CRTC registers */
3804 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3805 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3806 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3807 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3808 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3812 void r100_vga_render_disable(struct radeon_device *rdev)
3816 tmp = RREG8(R_0003C2_GENMO_WT);
3817 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3820 static void r100_debugfs(struct radeon_device *rdev)
3824 r = r100_debugfs_mc_info_init(rdev);
3826 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3829 static void r100_mc_program(struct radeon_device *rdev)
3831 struct r100_mc_save save;
3833 /* Stops all mc clients */
3834 r100_mc_stop(rdev, &save);
3835 if (rdev->flags & RADEON_IS_AGP) {
3836 WREG32(R_00014C_MC_AGP_LOCATION,
3837 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3838 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3839 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3840 if (rdev->family > CHIP_RV200)
3841 WREG32(R_00015C_AGP_BASE_2,
3842 upper_32_bits(rdev->mc.agp_base) & 0xff);
3844 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3845 WREG32(R_000170_AGP_BASE, 0);
3846 if (rdev->family > CHIP_RV200)
3847 WREG32(R_00015C_AGP_BASE_2, 0);
3849 /* Wait for mc idle */
3850 if (r100_mc_wait_for_idle(rdev))
3851 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3852 /* Program MC, should be a 32bits limited address space */
3853 WREG32(R_000148_MC_FB_LOCATION,
3854 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3855 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3856 r100_mc_resume(rdev, &save);
3859 static void r100_clock_startup(struct radeon_device *rdev)
3863 if (radeon_dynclks != -1 && radeon_dynclks)
3864 radeon_legacy_set_clock_gating(rdev, 1);
3865 /* We need to force on some of the block */
3866 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3867 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3868 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3869 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3870 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3873 static int r100_startup(struct radeon_device *rdev)
3877 /* set common regs */
3878 r100_set_common_regs(rdev);
3880 r100_mc_program(rdev);
3882 r100_clock_startup(rdev);
3883 /* Initialize GART (initialize after TTM so we can allocate
3884 * memory through TTM but finalize after TTM) */
3885 r100_enable_bm(rdev);
3886 if (rdev->flags & RADEON_IS_PCI) {
3887 r = r100_pci_gart_enable(rdev);
3892 /* allocate wb buffer */
3893 r = radeon_wb_init(rdev);
3897 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3899 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3904 if (!rdev->irq.installed) {
3905 r = radeon_irq_kms_init(rdev);
3911 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3912 /* 1M ring buffer */
3913 r = r100_cp_init(rdev, 1024 * 1024);
3915 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
3919 r = radeon_ib_pool_init(rdev);
3921 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3928 int r100_resume(struct radeon_device *rdev)
3932 /* Make sur GART are not working */
3933 if (rdev->flags & RADEON_IS_PCI)
3934 r100_pci_gart_disable(rdev);
3935 /* Resume clock before doing reset */
3936 r100_clock_startup(rdev);
3937 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3938 if (radeon_asic_reset(rdev)) {
3939 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3940 RREG32(R_000E40_RBBM_STATUS),
3941 RREG32(R_0007C0_CP_STAT));
3944 radeon_combios_asic_init(rdev->ddev);
3945 /* Resume clock after posting */
3946 r100_clock_startup(rdev);
3947 /* Initialize surface registers */
3948 radeon_surface_init(rdev);
3950 rdev->accel_working = true;
3951 r = r100_startup(rdev);
3953 rdev->accel_working = false;
3958 int r100_suspend(struct radeon_device *rdev)
3960 radeon_pm_suspend(rdev);
3961 r100_cp_disable(rdev);
3962 radeon_wb_disable(rdev);
3963 r100_irq_disable(rdev);
3964 if (rdev->flags & RADEON_IS_PCI)
3965 r100_pci_gart_disable(rdev);
3969 void r100_fini(struct radeon_device *rdev)
3971 radeon_pm_fini(rdev);
3973 radeon_wb_fini(rdev);
3974 radeon_ib_pool_fini(rdev);
3975 radeon_gem_fini(rdev);
3976 if (rdev->flags & RADEON_IS_PCI)
3977 r100_pci_gart_fini(rdev);
3978 radeon_agp_fini(rdev);
3979 radeon_irq_kms_fini(rdev);
3980 radeon_fence_driver_fini(rdev);
3981 radeon_bo_fini(rdev);
3982 radeon_atombios_fini(rdev);
3983 r100_cp_fini_microcode(rdev);
3989 * Due to how kexec works, it can leave the hw fully initialised when it
3990 * boots the new kernel. However doing our init sequence with the CP and
3991 * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
3992 * do some quick sanity checks and restore sane values to avoid this
3995 void r100_restore_sanity(struct radeon_device *rdev)
3999 tmp = RREG32(RADEON_CP_CSQ_CNTL);
4001 WREG32(RADEON_CP_CSQ_CNTL, 0);
4003 tmp = RREG32(RADEON_CP_RB_CNTL);
4005 WREG32(RADEON_CP_RB_CNTL, 0);
4007 tmp = RREG32(RADEON_SCRATCH_UMSK);
4009 WREG32(RADEON_SCRATCH_UMSK, 0);
4013 int r100_init(struct radeon_device *rdev)
4017 /* Register debugfs file specific to this group of asics */
4020 r100_vga_render_disable(rdev);
4021 /* Initialize scratch registers */
4022 radeon_scratch_init(rdev);
4023 /* Initialize surface registers */
4024 radeon_surface_init(rdev);
4025 /* sanity check some register to avoid hangs like after kexec */
4026 r100_restore_sanity(rdev);
4027 /* TODO: disable VGA need to use VGA request */
4029 if (!radeon_get_bios(rdev)) {
4030 if (ASIC_IS_AVIVO(rdev))
4033 if (rdev->is_atom_bios) {
4034 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
4037 r = radeon_combios_init(rdev);
4041 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
4042 if (radeon_asic_reset(rdev)) {
4044 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
4045 RREG32(R_000E40_RBBM_STATUS),
4046 RREG32(R_0007C0_CP_STAT));
4048 /* check if cards are posted or not */
4049 if (radeon_boot_test_post_card(rdev) == false)
4051 /* Set asic errata */
4053 /* Initialize clocks */
4054 radeon_get_clock_info(rdev->ddev);
4055 /* initialize AGP */
4056 if (rdev->flags & RADEON_IS_AGP) {
4057 r = radeon_agp_init(rdev);
4059 radeon_agp_disable(rdev);
4062 /* initialize VRAM */
4065 r = radeon_fence_driver_init(rdev);
4068 /* Memory manager */
4069 r = radeon_bo_init(rdev);
4072 if (rdev->flags & RADEON_IS_PCI) {
4073 r = r100_pci_gart_init(rdev);
4077 r100_set_safe_registers(rdev);
4079 /* Initialize power management */
4080 radeon_pm_init(rdev);
4082 rdev->accel_working = true;
4083 r = r100_startup(rdev);
4085 /* Somethings want wront with the accel init stop accel */
4086 dev_err(rdev->dev, "Disabling GPU acceleration\n");
4088 radeon_wb_fini(rdev);
4089 radeon_ib_pool_fini(rdev);
4090 radeon_irq_kms_fini(rdev);
4091 if (rdev->flags & RADEON_IS_PCI)
4092 r100_pci_gart_fini(rdev);
4093 rdev->accel_working = false;
4098 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
4099 bool always_indirect)
4101 if (reg < rdev->rmmio_size && !always_indirect)
4102 return bus_read_4(rdev->rmmio, reg);
4106 spin_lock(&rdev->mmio_idx_lock);
4107 bus_write_4(rdev->rmmio, RADEON_MM_INDEX, reg);
4108 ret = bus_read_4(rdev->rmmio, RADEON_MM_DATA);
4109 spin_unlock(&rdev->mmio_idx_lock);
4115 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
4116 bool always_indirect)
4118 if (reg < rdev->rmmio_size && !always_indirect)
4119 bus_write_4(rdev->rmmio, reg, v);
4121 spin_lock(&rdev->mmio_idx_lock);
4122 bus_write_4(rdev->rmmio, RADEON_MM_INDEX, reg);
4123 bus_write_4(rdev->rmmio, RADEON_MM_DATA, v);
4124 spin_unlock(&rdev->mmio_idx_lock);
4128 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
4130 if (reg < rdev->rio_mem_size)
4131 return bus_read_4(rdev->rio_mem, reg);
4133 /* XXX No locking? -- dumbbell@ */
4134 bus_write_4(rdev->rio_mem, RADEON_MM_INDEX, reg);
4135 return bus_read_4(rdev->rio_mem, RADEON_MM_DATA);
4139 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
4141 if (reg < rdev->rio_mem_size)
4142 bus_write_4(rdev->rio_mem, reg, v);
4144 /* XXX No locking? -- dumbbell@ */
4145 bus_write_4(rdev->rio_mem, RADEON_MM_INDEX, reg);
4146 bus_write_4(rdev->rio_mem, RADEON_MM_DATA, v);