2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_vr.c,v 1.26.2.13 2003/02/06 04:46:20 silby Exp $
33 * $DragonFly: src/sys/dev/netif/vr/if_vr.c,v 1.30 2005/06/20 13:04:52 joerg Exp $
37 * VIA Rhine fast ethernet PCI NIC driver
39 * Supports various network adapters based on the VIA Rhine
40 * and Rhine II PCI controllers, including the D-Link DFE530TX.
41 * Datasheets are available at http://www.via.com.tw.
43 * Written by Bill Paul <wpaul@ctr.columbia.edu>
44 * Electrical Engineering Department
45 * Columbia University, New York City
49 * The VIA Rhine controllers are similar in some respects to the
50 * the DEC tulip chips, except less complicated. The controller
51 * uses an MII bus and an external physical layer interface. The
52 * receiver has a one entry perfect filter and a 64-bit hash table
53 * multicast filter. Transmit and receive descriptors are similar
56 * The Rhine has a serious flaw in its transmit DMA mechanism:
57 * transmit buffers must be longword aligned. Unfortunately,
58 * FreeBSD doesn't guarantee that mbufs will be filled in starting
59 * at longword boundaries, so we have to do a buffer copy before
63 #include <sys/param.h>
64 #include <sys/systm.h>
65 #include <sys/sockio.h>
67 #include <sys/malloc.h>
68 #include <sys/kernel.h>
69 #include <sys/socket.h>
70 #include <sys/thread2.h>
73 #include <net/ifq_var.h>
74 #include <net/if_arp.h>
75 #include <net/ethernet.h>
76 #include <net/if_dl.h>
77 #include <net/if_media.h>
81 #include <vm/vm.h> /* for vtophys */
82 #include <vm/pmap.h> /* for vtophys */
83 #include <machine/bus_pio.h>
84 #include <machine/bus_memio.h>
85 #include <machine/bus.h>
86 #include <machine/resource.h>
90 #include <dev/netif/mii_layer/mii.h>
91 #include <dev/netif/mii_layer/miivar.h>
93 #include <bus/pci/pcireg.h>
94 #include <bus/pci/pcivar.h>
98 #include <dev/netif/vr/if_vrreg.h>
100 /* "controller miibus0" required. See GENERIC if you get errors here. */
101 #include "miibus_if.h"
106 * Various supported device vendors/types and their names.
108 static struct vr_type vr_devs[] = {
109 { VIA_VENDORID, VIA_DEVICEID_RHINE,
110 "VIA VT3043 Rhine I 10/100BaseTX" },
111 { VIA_VENDORID, VIA_DEVICEID_RHINE_II,
112 "VIA VT86C100A Rhine II 10/100BaseTX" },
113 { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2,
114 "VIA VT6102 Rhine II 10/100BaseTX" },
115 { VIA_VENDORID, VIA_DEVICEID_RHINE_III,
116 "VIA VT6105 Rhine III 10/100BaseTX" },
117 { VIA_VENDORID, VIA_DEVICEID_RHINE_III_M,
118 "VIA VT6105M Rhine III 10/100BaseTX" },
119 { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II,
120 "Delta Electronics Rhine II 10/100BaseTX" },
121 { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II,
122 "Addtron Technology Rhine II 10/100BaseTX" },
126 static int vr_probe(device_t);
127 static int vr_attach(device_t);
128 static int vr_detach(device_t);
130 static int vr_newbuf(struct vr_softc *, struct vr_chain_onefrag *,
132 static int vr_encap(struct vr_softc *, struct vr_chain *, struct mbuf * );
134 static void vr_rxeof(struct vr_softc *);
135 static void vr_rxeoc(struct vr_softc *);
136 static void vr_txeof(struct vr_softc *);
137 static void vr_txeoc(struct vr_softc *);
138 static void vr_tick(void *);
139 static void vr_intr(void *);
140 static void vr_start(struct ifnet *);
141 static int vr_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
142 static void vr_init(void *);
143 static void vr_stop(struct vr_softc *);
144 static void vr_watchdog(struct ifnet *);
145 static void vr_shutdown(device_t);
146 static int vr_ifmedia_upd(struct ifnet *);
147 static void vr_ifmedia_sts(struct ifnet *, struct ifmediareq *);
150 static void vr_mii_sync(struct vr_softc *);
151 static void vr_mii_send(struct vr_softc *, uint32_t, int);
153 static int vr_mii_readreg(struct vr_softc *, struct vr_mii_frame *);
154 static int vr_mii_writereg(struct vr_softc *, struct vr_mii_frame *);
155 static int vr_miibus_readreg(device_t, int, int);
156 static int vr_miibus_writereg(device_t, int, int, int);
157 static void vr_miibus_statchg(device_t);
159 static void vr_setcfg(struct vr_softc *, int);
160 static void vr_setmulti(struct vr_softc *);
161 static void vr_reset(struct vr_softc *);
162 static int vr_list_rx_init(struct vr_softc *);
163 static int vr_list_tx_init(struct vr_softc *);
164 #ifdef DEVICE_POLLING
165 static void vr_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
169 #define VR_RES SYS_RES_IOPORT
170 #define VR_RID VR_PCI_LOIO
172 #define VR_RES SYS_RES_MEMORY
173 #define VR_RID VR_PCI_LOMEM
176 static device_method_t vr_methods[] = {
177 /* Device interface */
178 DEVMETHOD(device_probe, vr_probe),
179 DEVMETHOD(device_attach, vr_attach),
180 DEVMETHOD(device_detach, vr_detach),
181 DEVMETHOD(device_shutdown, vr_shutdown),
184 DEVMETHOD(bus_print_child, bus_generic_print_child),
185 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
188 DEVMETHOD(miibus_readreg, vr_miibus_readreg),
189 DEVMETHOD(miibus_writereg, vr_miibus_writereg),
190 DEVMETHOD(miibus_statchg, vr_miibus_statchg),
195 static driver_t vr_driver = {
198 sizeof(struct vr_softc)
201 static devclass_t vr_devclass;
203 DECLARE_DUMMY_MODULE(if_vr);
204 DRIVER_MODULE(if_vr, pci, vr_driver, vr_devclass, 0, 0);
205 DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0);
207 #define VR_SETBIT(sc, reg, x) \
208 CSR_WRITE_1(sc, reg, \
209 CSR_READ_1(sc, reg) | (x))
211 #define VR_CLRBIT(sc, reg, x) \
212 CSR_WRITE_1(sc, reg, \
213 CSR_READ_1(sc, reg) & ~(x))
215 #define VR_SETBIT16(sc, reg, x) \
216 CSR_WRITE_2(sc, reg, \
217 CSR_READ_2(sc, reg) | (x))
219 #define VR_CLRBIT16(sc, reg, x) \
220 CSR_WRITE_2(sc, reg, \
221 CSR_READ_2(sc, reg) & ~(x))
223 #define VR_SETBIT32(sc, reg, x) \
224 CSR_WRITE_4(sc, reg, \
225 CSR_READ_4(sc, reg) | (x))
227 #define VR_CLRBIT32(sc, reg, x) \
228 CSR_WRITE_4(sc, reg, \
229 CSR_READ_4(sc, reg) & ~(x))
232 CSR_WRITE_1(sc, VR_MIICMD, \
233 CSR_READ_1(sc, VR_MIICMD) | (x))
236 CSR_WRITE_1(sc, VR_MIICMD, \
237 CSR_READ_1(sc, VR_MIICMD) & ~(x))
241 * Sync the PHYs by setting data bit and strobing the clock 32 times.
244 vr_mii_sync(struct vr_softc *sc)
248 SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN);
250 for (i = 0; i < 32; i++) {
251 SIO_SET(VR_MIICMD_CLK);
253 SIO_CLR(VR_MIICMD_CLK);
259 * Clock a series of bits through the MII.
262 vr_mii_send(struct vr_softc *sc, uint32_t bits, int cnt)
266 SIO_CLR(VR_MIICMD_CLK);
268 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
270 SIO_SET(VR_MIICMD_DATAIN);
272 SIO_CLR(VR_MIICMD_DATAIN);
274 SIO_CLR(VR_MIICMD_CLK);
276 SIO_SET(VR_MIICMD_CLK);
282 * Read an PHY register through the MII.
285 vr_mii_readreg(struct vr_softc *sc, struct vr_mii_frame *frame)
292 /* Set up frame for RX. */
293 frame->mii_stdelim = VR_MII_STARTDELIM;
294 frame->mii_opcode = VR_MII_READOP;
295 frame->mii_turnaround = 0;
298 CSR_WRITE_1(sc, VR_MIICMD, 0);
299 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM);
301 /* Turn on data xmit. */
302 SIO_SET(VR_MIICMD_DIR);
306 /* Send command/address info. */
307 vr_mii_send(sc, frame->mii_stdelim, 2);
308 vr_mii_send(sc, frame->mii_opcode, 2);
309 vr_mii_send(sc, frame->mii_phyaddr, 5);
310 vr_mii_send(sc, frame->mii_regaddr, 5);
313 SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN));
315 SIO_SET(VR_MIICMD_CLK);
319 SIO_CLR(VR_MIICMD_DIR);
322 SIO_CLR(VR_MIICMD_CLK);
324 ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT;
325 SIO_SET(VR_MIICMD_CLK);
329 * Now try reading data bits. If the ack failed, we still
330 * need to clock through 16 cycles to keep the PHY(s) in sync.
333 for(i = 0; i < 16; i++) {
334 SIO_CLR(VR_MIICMD_CLK);
336 SIO_SET(VR_MIICMD_CLK);
342 for (i = 0x8000; i; i >>= 1) {
343 SIO_CLR(VR_MIICMD_CLK);
346 if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT)
347 frame->mii_data |= i;
350 SIO_SET(VR_MIICMD_CLK);
355 SIO_CLR(VR_MIICMD_CLK);
357 SIO_SET(VR_MIICMD_CLK);
372 /* Set the PHY address. */
373 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)|
376 /* Set the register address. */
377 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr);
378 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB);
380 for (i = 0; i < 10000; i++) {
381 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0)
385 frame->mii_data = CSR_READ_2(sc, VR_MIIDATA);
395 * Write to a PHY register through the MII.
398 vr_mii_writereg(struct vr_softc *sc, struct vr_mii_frame *frame)
404 CSR_WRITE_1(sc, VR_MIICMD, 0);
405 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM);
407 /* Set up frame for TX. */
408 frame->mii_stdelim = VR_MII_STARTDELIM;
409 frame->mii_opcode = VR_MII_WRITEOP;
410 frame->mii_turnaround = VR_MII_TURNAROUND;
412 /* Turn on data output. */
413 SIO_SET(VR_MIICMD_DIR);
417 vr_mii_send(sc, frame->mii_stdelim, 2);
418 vr_mii_send(sc, frame->mii_opcode, 2);
419 vr_mii_send(sc, frame->mii_phyaddr, 5);
420 vr_mii_send(sc, frame->mii_regaddr, 5);
421 vr_mii_send(sc, frame->mii_turnaround, 2);
422 vr_mii_send(sc, frame->mii_data, 16);
425 SIO_SET(VR_MIICMD_CLK);
427 SIO_CLR(VR_MIICMD_CLK);
431 SIO_CLR(VR_MIICMD_DIR);
443 /* Set the PHY-adress */
444 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)|
447 /* Set the register address and data to write. */
448 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr);
449 CSR_WRITE_2(sc, VR_MIIDATA, frame->mii_data);
451 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB);
453 for (i = 0; i < 10000; i++) {
454 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0)
466 vr_miibus_readreg(device_t dev, int phy, int reg)
468 struct vr_mii_frame frame;
471 sc = device_get_softc(dev);
473 switch (sc->vr_revid) {
474 case REV_ID_VT6102_APOLLO:
482 bzero(&frame, sizeof(frame));
484 frame.mii_phyaddr = phy;
485 frame.mii_regaddr = reg;
486 vr_mii_readreg(sc, &frame);
488 return(frame.mii_data);
492 vr_miibus_writereg(device_t dev, int phy, int reg, int data)
494 struct vr_mii_frame frame;
497 sc = device_get_softc(dev);
499 switch (sc->vr_revid) {
500 case REV_ID_VT6102_APOLLO:
508 bzero(&frame, sizeof(frame));
510 frame.mii_phyaddr = phy;
511 frame.mii_regaddr = reg;
512 frame.mii_data = data;
514 vr_mii_writereg(sc, &frame);
520 vr_miibus_statchg(device_t dev)
522 struct mii_data *mii;
525 sc = device_get_softc(dev);
526 mii = device_get_softc(sc->vr_miibus);
527 vr_setcfg(sc, mii->mii_media_active);
531 * Program the 64-bit multicast hash filter.
534 vr_setmulti(struct vr_softc *sc)
537 uint32_t hashes[2] = { 0, 0 };
538 struct ifmultiaddr *ifma;
542 ifp = &sc->arpcom.ac_if;
544 rxfilt = CSR_READ_1(sc, VR_RXCFG);
546 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
547 rxfilt |= VR_RXCFG_RX_MULTI;
548 CSR_WRITE_1(sc, VR_RXCFG, rxfilt);
549 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF);
550 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF);
554 /* First, zero out all the existing hash bits. */
555 CSR_WRITE_4(sc, VR_MAR0, 0);
556 CSR_WRITE_4(sc, VR_MAR1, 0);
558 /* Now program new ones. */
559 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
560 ifma = ifma->ifma_link.le_next) {
563 if (ifma->ifma_addr->sa_family != AF_LINK)
566 /* use the lower 6 bits */
568 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
569 ETHER_ADDR_LEN) >> 26) & 0x0000003F;
571 hashes[0] |= (1 << h);
573 hashes[1] |= (1 << (h - 32));
578 rxfilt |= VR_RXCFG_RX_MULTI;
580 rxfilt &= ~VR_RXCFG_RX_MULTI;
582 CSR_WRITE_4(sc, VR_MAR0, hashes[0]);
583 CSR_WRITE_4(sc, VR_MAR1, hashes[1]);
584 CSR_WRITE_1(sc, VR_RXCFG, rxfilt);
588 * In order to fiddle with the
589 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
590 * first have to put the transmit and/or receive logic in the idle state.
593 vr_setcfg(struct vr_softc *sc, int media)
597 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) {
599 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON));
602 if ((media & IFM_GMASK) == IFM_FDX)
603 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX);
605 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX);
608 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON);
612 vr_reset(struct vr_softc *sc)
616 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET);
618 for (i = 0; i < VR_TIMEOUT; i++) {
620 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET))
623 if (i == VR_TIMEOUT) {
624 struct ifnet *ifp = &sc->arpcom.ac_if;
626 if (sc->vr_revid < REV_ID_VT3065_A) {
627 if_printf(ifp, "reset never completed!\n");
629 /* Use newer force reset command */
630 if_printf(ifp, "Using force reset command.\n");
631 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST);
635 /* Wait a little while for the chip to get its brains in order. */
640 * Probe for a VIA Rhine chip. Check the PCI vendor and device
641 * IDs against our list and return a device name if we find a match.
644 vr_probe(device_t dev)
649 vid = pci_get_vendor(dev);
650 did = pci_get_device(dev);
652 for (t = vr_devs; t->vr_name != NULL; ++t) {
653 if (vid == t->vr_vid && did == t->vr_did) {
654 device_set_desc(dev, t->vr_name);
663 * Attach the interface. Allocate softc structures, do ifmedia
664 * setup and ethernet/BPF attach.
667 vr_attach(device_t dev)
670 uint8_t eaddr[ETHER_ADDR_LEN];
677 sc = device_get_softc(dev);
678 callout_init(&sc->vr_stat_timer);
681 * Handle power management nonsense.
683 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
684 uint32_t iobase, membase, irq;
686 /* Save important PCI config data. */
687 iobase = pci_read_config(dev, VR_PCI_LOIO, 4);
688 membase = pci_read_config(dev, VR_PCI_LOMEM, 4);
689 irq = pci_read_config(dev, VR_PCI_INTLINE, 4);
691 /* Reset the power state. */
692 device_printf(dev, "chip is in D%d power mode "
693 "-- setting to D0\n", pci_get_powerstate(dev));
694 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
696 /* Restore PCI config data. */
697 pci_write_config(dev, VR_PCI_LOIO, iobase, 4);
698 pci_write_config(dev, VR_PCI_LOMEM, membase, 4);
699 pci_write_config(dev, VR_PCI_INTLINE, irq, 4);
702 pci_enable_busmaster(dev);
705 sc->vr_res = bus_alloc_resource_any(dev, VR_RES, &rid, RF_ACTIVE);
707 if (sc->vr_res == NULL) {
708 device_printf(dev, "couldn't map ports/memory\n");
713 sc->vr_btag = rman_get_bustag(sc->vr_res);
714 sc->vr_bhandle = rman_get_bushandle(sc->vr_res);
716 /* Allocate interrupt */
718 sc->vr_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
719 RF_SHAREABLE | RF_ACTIVE);
721 if (sc->vr_irq == NULL) {
722 device_printf(dev, "couldn't map interrupt\n");
723 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res);
728 error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET,
729 vr_intr, sc, &sc->vr_intrhand, NULL);
732 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq);
733 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res);
734 device_printf(dev, "couldn't set up irq\n");
739 * Windows may put the chip in suspend mode when it
740 * shuts down. Be sure to kick it in the head to wake it
743 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1));
745 ifp = &sc->arpcom.ac_if;
746 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
748 /* Reset the adapter. */
752 * Turn on bit2 (MIION) in PCI configuration register 0x53 during
753 * initialization and disable AUTOPOLL.
755 pci_write_config(dev, VR_PCI_MODE,
756 pci_read_config(dev, VR_PCI_MODE, 4) | (VR_MODE3_MIION << 24), 4);
757 VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL);
760 * Get station address. The way the Rhine chips work,
761 * you're not allowed to directly access the EEPROM once
762 * they've been programmed a special way. Consequently,
763 * we need to read the node address from the PAR0 and PAR1
766 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD);
768 for (i = 0; i < ETHER_ADDR_LEN; i++)
769 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i);
771 sc->vr_ldata = contigmalloc(sizeof(struct vr_list_data), M_DEVBUF,
772 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
774 if (sc->vr_ldata == NULL) {
775 device_printf(dev, "no memory for list buffers!\n");
776 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand);
777 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq);
778 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res);
783 bzero(sc->vr_ldata, sizeof(struct vr_list_data));
786 ifp->if_mtu = ETHERMTU;
787 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
788 ifp->if_ioctl = vr_ioctl;
789 ifp->if_start = vr_start;
790 #ifdef DEVICE_POLLING
791 ifp->if_poll = vr_poll;
793 ifp->if_watchdog = vr_watchdog;
794 ifp->if_init = vr_init;
795 ifp->if_baudrate = 10000000;
796 ifq_set_maxlen(&ifp->if_snd, VR_TX_LIST_CNT - 1);
797 ifq_set_ready(&ifp->if_snd);
802 if (mii_phy_probe(dev, &sc->vr_miibus,
803 vr_ifmedia_upd, vr_ifmedia_sts)) {
804 if_printf(ifp, "MII without any phy!\n");
805 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand);
806 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq);
807 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res);
808 contigfree(sc->vr_ldata,
809 sizeof(struct vr_list_data), M_DEVBUF);
814 /* Call MI attach routine. */
815 ether_ifattach(ifp, eaddr);
823 vr_detach(device_t dev)
825 struct vr_softc *sc = device_get_softc(dev);
826 struct ifnet *ifp = &sc->arpcom.ac_if;
833 bus_generic_detach(dev);
834 device_delete_child(dev, sc->vr_miibus);
836 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand);
840 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq);
841 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res);
843 contigfree(sc->vr_ldata, sizeof(struct vr_list_data), M_DEVBUF);
849 * Initialize the transmit descriptors.
852 vr_list_tx_init(struct vr_softc *sc)
854 struct vr_chain_data *cd;
855 struct vr_list_data *ld;
860 for (i = 0; i < VR_TX_LIST_CNT; i++) {
861 cd->vr_tx_chain[i].vr_ptr = &ld->vr_tx_list[i];
862 if (i == (VR_TX_LIST_CNT - 1))
866 cd->vr_tx_chain[i].vr_nextdesc = &cd->vr_tx_chain[nexti];
869 cd->vr_tx_free = &cd->vr_tx_chain[0];
870 cd->vr_tx_tail = cd->vr_tx_head = NULL;
877 * Initialize the RX descriptors and allocate mbufs for them. Note that
878 * we arrange the descriptors in a closed ring, so that the last descriptor
879 * points back to the first.
882 vr_list_rx_init(struct vr_softc *sc)
884 struct vr_chain_data *cd;
885 struct vr_list_data *ld;
891 for (i = 0; i < VR_RX_LIST_CNT; i++) {
892 cd->vr_rx_chain[i].vr_ptr = (struct vr_desc *)&ld->vr_rx_list[i];
893 if (vr_newbuf(sc, &cd->vr_rx_chain[i], NULL) == ENOBUFS)
895 if (i == (VR_RX_LIST_CNT - 1))
899 cd->vr_rx_chain[i].vr_nextdesc = &cd->vr_rx_chain[nexti];
900 ld->vr_rx_list[i].vr_next = vtophys(&ld->vr_rx_list[nexti]);
903 cd->vr_rx_head = &cd->vr_rx_chain[0];
909 * Initialize an RX descriptor and attach an MBUF cluster.
910 * Note: the length fields are only 11 bits wide, which means the
911 * largest size we can specify is 2047. This is important because
912 * MCLBYTES is 2048, so we have to subtract one otherwise we'll
913 * overflow the field and make a mess.
916 vr_newbuf(struct vr_softc *sc, struct vr_chain_onefrag *c, struct mbuf *m)
918 struct mbuf *m_new = NULL;
921 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
924 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
927 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
928 m_new->m_data = m_new->m_ext.ext_buf;
931 m_adj(m_new, sizeof(uint64_t));
934 c->vr_ptr->vr_status = VR_RXSTAT;
935 c->vr_ptr->vr_data = vtophys(mtod(m_new, caddr_t));
936 c->vr_ptr->vr_ctl = VR_RXCTL | VR_RXLEN;
942 * A frame has been uploaded: pass the resulting mbuf chain up to
943 * the higher level protocols.
946 vr_rxeof(struct vr_softc *sc)
950 struct vr_chain_onefrag *cur_rx;
954 ifp = &sc->arpcom.ac_if;
956 while(!((rxstat = sc->vr_cdata.vr_rx_head->vr_ptr->vr_status) &
958 struct mbuf *m0 = NULL;
960 cur_rx = sc->vr_cdata.vr_rx_head;
961 sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc;
965 * If an error occurs, update stats, clear the
966 * status word and leave the mbuf cluster in place:
967 * it should simply get re-used next time this descriptor
968 * comes up in the ring.
970 if (rxstat & VR_RXSTAT_RXERR) {
972 if_printf(ifp, "rx error (%02x):", rxstat & 0x000000ff);
973 if (rxstat & VR_RXSTAT_CRCERR)
974 printf(" crc error");
975 if (rxstat & VR_RXSTAT_FRAMEALIGNERR)
976 printf(" frame alignment error\n");
977 if (rxstat & VR_RXSTAT_FIFOOFLOW)
978 printf(" FIFO overflow");
979 if (rxstat & VR_RXSTAT_GIANT)
980 printf(" received giant packet");
981 if (rxstat & VR_RXSTAT_RUNT)
982 printf(" received runt packet");
983 if (rxstat & VR_RXSTAT_BUSERR)
984 printf(" system bus error");
985 if (rxstat & VR_RXSTAT_BUFFERR)
986 printf("rx buffer error");
988 vr_newbuf(sc, cur_rx, m);
992 /* No errors; receive the packet. */
993 total_len = VR_RXBYTES(cur_rx->vr_ptr->vr_status);
996 * XXX The VIA Rhine chip includes the CRC with every
997 * received frame, and there's no way to turn this
998 * behavior off (at least, I can't find anything in
999 * the manual that explains how to do it) so we have
1000 * to trim off the CRC manually.
1002 total_len -= ETHER_CRC_LEN;
1004 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1005 total_len + ETHER_ALIGN, 0, ifp, NULL);
1006 vr_newbuf(sc, cur_rx, m);
1011 m_adj(m0, ETHER_ALIGN);
1015 (*ifp->if_input)(ifp, m);
1020 vr_rxeoc(struct vr_softc *sc)
1025 ifp = &sc->arpcom.ac_if;
1029 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON);
1032 /* Wait for receiver to stop */
1034 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON);
1036 ; /* Wait for receiver to stop */
1039 if_printf(ifp, "rx shutdown error!\n");
1040 sc->vr_flags |= VR_F_RESTART;
1046 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr));
1047 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON);
1048 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO);
1052 * A frame was downloaded to the chip. It's safe for us to clean up
1056 vr_txeof(struct vr_softc *sc)
1058 struct vr_chain *cur_tx;
1061 ifp = &sc->arpcom.ac_if;
1063 /* Reset the timeout timer; if_txeoc will clear it. */
1067 if (sc->vr_cdata.vr_tx_head == NULL)
1071 * Go through our tx list and free mbufs for those
1072 * frames that have been transmitted.
1074 while(sc->vr_cdata.vr_tx_head->vr_mbuf != NULL) {
1078 cur_tx = sc->vr_cdata.vr_tx_head;
1079 txstat = cur_tx->vr_ptr->vr_status;
1081 if ((txstat & VR_TXSTAT_ABRT) ||
1082 (txstat & VR_TXSTAT_UDF)) {
1084 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_TX_ON);
1086 ; /* Wait for chip to shutdown */
1088 if_printf(ifp, "tx shutdown timeout\n");
1089 sc->vr_flags |= VR_F_RESTART;
1092 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN;
1093 CSR_WRITE_4(sc, VR_TXADDR, vtophys(cur_tx->vr_ptr));
1097 if (txstat & VR_TXSTAT_OWN)
1100 if (txstat & VR_TXSTAT_ERRSUM) {
1102 if (txstat & VR_TXSTAT_DEFER)
1103 ifp->if_collisions++;
1104 if (txstat & VR_TXSTAT_LATECOLL)
1105 ifp->if_collisions++;
1108 ifp->if_collisions +=(txstat & VR_TXSTAT_COLLCNT) >> 3;
1111 if (cur_tx->vr_mbuf != NULL) {
1112 m_freem(cur_tx->vr_mbuf);
1113 cur_tx->vr_mbuf = NULL;
1116 if (sc->vr_cdata.vr_tx_head == sc->vr_cdata.vr_tx_tail) {
1117 sc->vr_cdata.vr_tx_head = NULL;
1118 sc->vr_cdata.vr_tx_tail = NULL;
1122 sc->vr_cdata.vr_tx_head = cur_tx->vr_nextdesc;
1127 * TX 'end of channel' interrupt handler.
1130 vr_txeoc(struct vr_softc *sc)
1134 ifp = &sc->arpcom.ac_if;
1136 if (sc->vr_cdata.vr_tx_head == NULL) {
1137 ifp->if_flags &= ~IFF_OACTIVE;
1138 sc->vr_cdata.vr_tx_tail = NULL;
1146 struct vr_softc *sc = xsc;
1147 struct mii_data *mii;
1151 if (sc->vr_flags & VR_F_RESTART) {
1152 if_printf(&sc->arpcom.ac_if, "restarting\n");
1156 sc->vr_flags &= ~VR_F_RESTART;
1159 mii = device_get_softc(sc->vr_miibus);
1162 callout_reset(&sc->vr_stat_timer, hz, vr_tick, sc);
1170 struct vr_softc *sc;
1175 ifp = &sc->arpcom.ac_if;
1177 /* Supress unwanted interrupts. */
1178 if (!(ifp->if_flags & IFF_UP)) {
1183 /* Disable interrupts. */
1184 if ((ifp->if_flags & IFF_POLLING) == 0)
1185 CSR_WRITE_2(sc, VR_IMR, 0x0000);
1188 status = CSR_READ_2(sc, VR_ISR);
1190 CSR_WRITE_2(sc, VR_ISR, status);
1192 if ((status & VR_INTRS) == 0)
1195 if (status & VR_ISR_RX_OK)
1198 if (status & VR_ISR_RX_DROPPED) {
1199 if_printf(ifp, "rx packet lost\n");
1203 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) ||
1204 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) {
1205 if_printf(ifp, "receive error (%04x)", status);
1206 if (status & VR_ISR_RX_NOBUF)
1207 printf(" no buffers");
1208 if (status & VR_ISR_RX_OFLOW)
1209 printf(" overflow");
1210 if (status & VR_ISR_RX_DROPPED)
1211 printf(" packet lost");
1216 if ((status & VR_ISR_BUSERR) || (status & VR_ISR_TX_UNDERRUN)) {
1222 if ((status & VR_ISR_TX_OK) || (status & VR_ISR_TX_ABRT) ||
1223 (status & VR_ISR_TX_ABRT2) || (status & VR_ISR_UDFI)) {
1225 if ((status & VR_ISR_UDFI) ||
1226 (status & VR_ISR_TX_ABRT2) ||
1227 (status & VR_ISR_TX_ABRT)) {
1229 if (sc->vr_cdata.vr_tx_head != NULL) {
1230 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON);
1231 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO);
1240 /* Re-enable interrupts. */
1241 if ((ifp->if_flags & IFF_POLLING) == 0)
1242 CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
1244 if (!ifq_is_empty(&ifp->if_snd))
1249 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1250 * pointers to the fragment pointers.
1253 vr_encap(struct vr_softc *sc, struct vr_chain *c, struct mbuf *m_head)
1256 struct vr_desc *f = NULL;
1263 * The VIA Rhine wants packet buffers to be longword
1264 * aligned, but very often our mbufs aren't. Rather than
1265 * waste time trying to decide when to copy and when not
1266 * to copy, just do it all the time.
1268 m_new = m_getl(m_head->m_pkthdr.len, MB_DONTWAIT, MT_DATA, M_PKTHDR,
1270 if (m_new == NULL) {
1271 if_printf(&sc->arpcom.ac_if, "no memory for tx list\n");
1274 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1275 mtod(m_new, caddr_t));
1276 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1278 * The Rhine chip doesn't auto-pad, so we have to make
1279 * sure to pad short frames out to the minimum frame length
1282 if (m_new->m_len < VR_MIN_FRAMELEN) {
1283 m_new->m_pkthdr.len += VR_MIN_FRAMELEN - m_new->m_len;
1284 m_new->m_len = m_new->m_pkthdr.len;
1287 f->vr_data = vtophys(mtod(m_new, caddr_t));
1288 f->vr_ctl = total_len = m_new->m_len;
1289 f->vr_ctl |= VR_TXCTL_TLINK|VR_TXCTL_FIRSTFRAG;
1294 c->vr_ptr->vr_ctl |= VR_TXCTL_LASTFRAG|VR_TXCTL_FINT;
1295 c->vr_ptr->vr_next = vtophys(c->vr_nextdesc->vr_ptr);
1301 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1302 * to the mbuf data regions directly in the transmit lists. We also save a
1303 * copy of the pointers since the transmit list fragment pointers are
1304 * physical addresses.
1307 vr_start(struct ifnet *ifp)
1309 struct vr_softc *sc;
1310 struct mbuf *m_head = NULL;
1311 struct vr_chain *cur_tx = NULL, *start_tx;
1315 if (ifp->if_flags & IFF_OACTIVE)
1318 /* Check for an available queue slot. If there are none, punt. */
1319 if (sc->vr_cdata.vr_tx_free->vr_mbuf != NULL) {
1320 ifp->if_flags |= IFF_OACTIVE;
1324 start_tx = sc->vr_cdata.vr_tx_free;
1326 while(sc->vr_cdata.vr_tx_free->vr_mbuf == NULL) {
1327 m_head = ifq_poll(&ifp->if_snd);
1331 /* Pick a descriptor off the free list. */
1332 cur_tx = sc->vr_cdata.vr_tx_free;
1333 sc->vr_cdata.vr_tx_free = cur_tx->vr_nextdesc;
1335 /* Pack the data into the descriptor. */
1336 if (vr_encap(sc, cur_tx, m_head)) {
1337 ifp->if_flags |= IFF_OACTIVE;
1342 m_head = ifq_dequeue(&ifp->if_snd);
1343 if (cur_tx != start_tx)
1344 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN;
1346 BPF_MTAP(ifp, m_head);
1349 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN;
1350 VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/VR_CMD_TX_GO);
1353 /* If there are no frames queued, bail. */
1357 sc->vr_cdata.vr_tx_tail = cur_tx;
1359 if (sc->vr_cdata.vr_tx_head == NULL)
1360 sc->vr_cdata.vr_tx_head = start_tx;
1363 * Set a timeout in case the chip goes out to lunch.
1371 struct vr_softc *sc = xsc;
1372 struct ifnet *ifp = &sc->arpcom.ac_if;
1373 struct mii_data *mii;
1376 mii = device_get_softc(sc->vr_miibus);
1380 /* Cancel pending I/O and free all RX/TX buffers. */
1384 /* Set our station address. */
1385 for (i = 0; i < ETHER_ADDR_LEN; i++)
1386 CSR_WRITE_1(sc, VR_PAR0 + i, sc->arpcom.ac_enaddr[i]);
1389 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH);
1390 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD);
1393 * BCR0 and BCR1 can override the RXCFG and TXCFG registers,
1394 * so we must set both.
1396 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH);
1397 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES);
1399 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH);
1400 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTHRESHSTORENFWD);
1402 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH);
1403 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES);
1405 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH);
1406 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD);
1408 /* Init circular RX list. */
1409 if (vr_list_rx_init(sc) == ENOBUFS) {
1412 if_printf(ifp, "initialization failed: no memory for rx buffers\n");
1416 /* Init tx descriptors. */
1417 vr_list_tx_init(sc);
1419 /* If we want promiscuous mode, set the allframes bit. */
1420 if (ifp->if_flags & IFF_PROMISC)
1421 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC);
1423 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC);
1425 /* Set capture broadcast bit to capture broadcast frames. */
1426 if (ifp->if_flags & IFF_BROADCAST)
1427 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD);
1429 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD);
1432 * Program the multicast filter, if necessary.
1437 * Load the address of the RX list.
1439 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr));
1441 /* Enable receiver and transmitter. */
1442 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START|
1443 VR_CMD_TX_ON|VR_CMD_RX_ON|
1446 CSR_WRITE_4(sc, VR_TXADDR, vtophys(&sc->vr_ldata->vr_tx_list[0]));
1449 * Enable interrupts, unless we are polling.
1451 CSR_WRITE_2(sc, VR_ISR, 0xFFFF);
1452 if ((ifp->if_flags & IFF_POLLING) == 0)
1453 CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
1457 ifp->if_flags |= IFF_RUNNING;
1458 ifp->if_flags &= ~IFF_OACTIVE;
1462 callout_reset(&sc->vr_stat_timer, hz, vr_tick, sc);
1466 * Set media options.
1469 vr_ifmedia_upd(struct ifnet *ifp)
1471 struct vr_softc *sc;
1475 if (ifp->if_flags & IFF_UP)
1482 * Report current media status.
1485 vr_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1487 struct vr_softc *sc;
1488 struct mii_data *mii;
1491 mii = device_get_softc(sc->vr_miibus);
1493 ifmr->ifm_active = mii->mii_media_active;
1494 ifmr->ifm_status = mii->mii_media_status;
1498 vr_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1500 struct vr_softc *sc = ifp->if_softc;
1501 struct ifreq *ifr = (struct ifreq *) data;
1502 struct mii_data *mii;
1509 if (ifp->if_flags & IFF_UP) {
1512 if (ifp->if_flags & IFF_RUNNING)
1524 mii = device_get_softc(sc->vr_miibus);
1525 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1528 error = ether_ioctl(ifp, command, data);
1537 #ifdef DEVICE_POLLING
1540 vr_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1542 struct vr_softc *sc = ifp->if_softc;
1546 /* disable interrupts */
1547 CSR_WRITE_2(sc, VR_IMR, 0x0000);
1549 case POLL_DEREGISTER:
1550 /* enable interrupts */
1551 CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
1561 vr_watchdog(struct ifnet *ifp)
1563 struct vr_softc *sc;
1568 if_printf(ifp, "watchdog timeout\n");
1570 #ifdef DEVICE_POLLING
1571 if (++sc->vr_wdogerrors == 1 && (ifp->if_flags & IFF_POLLING) == 0) {
1572 if_printf(ifp, "ints don't seem to be working, "
1573 "emergency switch to polling\n");
1574 emergency_poll_enable("if_vr");
1575 ether_poll_register(ifp); /* XXX illegal */
1584 if (!ifq_is_empty(&ifp->if_snd))
1589 * Stop the adapter and free any mbufs allocated to the
1593 vr_stop(struct vr_softc *sc)
1598 ifp = &sc->arpcom.ac_if;
1601 callout_stop(&sc->vr_stat_timer);
1603 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP);
1604 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON));
1605 CSR_WRITE_2(sc, VR_IMR, 0x0000);
1606 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000);
1607 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000);
1610 * Free data in the RX lists.
1612 for (i = 0; i < VR_RX_LIST_CNT; i++) {
1613 if (sc->vr_cdata.vr_rx_chain[i].vr_mbuf != NULL) {
1614 m_freem(sc->vr_cdata.vr_rx_chain[i].vr_mbuf);
1615 sc->vr_cdata.vr_rx_chain[i].vr_mbuf = NULL;
1618 bzero((char *)&sc->vr_ldata->vr_rx_list,
1619 sizeof(sc->vr_ldata->vr_rx_list));
1622 * Free the TX list buffers.
1624 for (i = 0; i < VR_TX_LIST_CNT; i++) {
1625 if (sc->vr_cdata.vr_tx_chain[i].vr_mbuf != NULL) {
1626 m_freem(sc->vr_cdata.vr_tx_chain[i].vr_mbuf);
1627 sc->vr_cdata.vr_tx_chain[i].vr_mbuf = NULL;
1631 bzero((char *)&sc->vr_ldata->vr_tx_list,
1632 sizeof(sc->vr_ldata->vr_tx_list));
1634 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1638 * Stop all chip I/O so that the kernel's probe routines don't
1639 * get confused by errant DMAs when rebooting.
1642 vr_shutdown(device_t dev)
1644 struct vr_softc *sc;
1646 sc = device_get_softc(dev);