2 * Copyright (c) 2014 The DragonFly Project. All rights reserved.
4 * This code is derived from software contributed to The DragonFly Project
5 * by Matthew Dillon <dillon@backplane.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * Intel 4th generation mobile cpus integrated I2C device, smbus driver.
37 * See ig4_reg.h for datasheet reference and notes.
40 #include <sys/param.h>
41 #include <sys/systm.h>
42 #include <sys/kernel.h>
43 #include <sys/module.h>
44 #include <sys/errno.h>
46 #include <sys/syslog.h>
48 #include <sys/sysctl.h>
52 #include <bus/pci/pcivar.h>
53 #include <bus/pci/pcireg.h>
54 #include <bus/smbus/smbconf.h>
61 #define TRANS_NORMAL 1
65 static void ig4iic_intr(void *cookie);
66 static void ig4iic_dump(ig4iic_softc_t *sc);
69 SYSCTL_INT(_debug, OID_AUTO, ig4_dump, CTLTYPE_INT | CTLFLAG_RW,
73 * Low-level inline support functions
77 reg_write(ig4iic_softc_t *sc, uint32_t reg, uint32_t value)
79 bus_space_write_4(sc->regs_t, sc->regs_h, reg, value);
80 bus_space_barrier(sc->regs_t, sc->regs_h, reg, 4,
81 BUS_SPACE_BARRIER_WRITE);
86 reg_read(ig4iic_softc_t *sc, uint32_t reg)
90 bus_space_barrier(sc->regs_t, sc->regs_h, reg, 4,
91 BUS_SPACE_BARRIER_READ);
92 value = bus_space_read_4(sc->regs_t, sc->regs_h, reg);
97 * Enable or disable the controller and wait for the controller to acknowledge
102 set_controller(ig4iic_softc_t *sc, uint32_t ctl)
108 if (ctl & IG4_I2C_ENABLE) {
109 reg_write(sc, IG4_REG_INTR_MASK, IG4_INTR_STOP_DET |
111 reg_read(sc, IG4_REG_CLR_INTR);
113 reg_write(sc, IG4_REG_INTR_MASK, 0);
115 reg_write(sc, IG4_REG_I2C_EN, ctl);
116 error = SMB_ETIMEOUT;
118 for (retry = 100; retry > 0; --retry) {
119 v = reg_read(sc, IG4_REG_ENABLE_STATUS);
120 if (((v ^ ctl) & IG4_I2C_ENABLE) == 0) {
124 tsleep(sc, 0, "i2cslv", 1);
130 * Wait up to 25ms for the requested status using a 25uS polling loop.
134 wait_status(ig4iic_softc_t *sc, uint32_t status)
142 error = SMB_ETIMEOUT;
143 count = sys_cputimer->count();
144 limit = sys_cputimer->freq / 40;
148 * Check requested status
150 v = reg_read(sc, IG4_REG_I2C_STA);
157 * When waiting for receive data break-out if the interrupt
158 * loaded data into the FIFO.
160 if (status & IG4_STATUS_RX_NOTEMPTY) {
161 if (sc->rpos != sc->rnext) {
168 * When waiting for the transmit FIFO to become empty,
169 * reset the timeout if we see a change in the transmit
170 * FIFO level as progress is being made.
172 if (status & IG4_STATUS_TX_EMPTY) {
173 v = reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK;
176 count = sys_cputimer->count();
181 * Stop if we've run out of time.
183 if (sys_cputimer->count() - count > limit)
187 * When waiting for receive data let the interrupt do its
188 * work, otherwise poll with the lock held.
190 if (status & IG4_STATUS_RX_NOTEMPTY) {
191 lksleep(sc, &sc->lk, 0, "i2cwait", (hz + 99) / 100);
201 * Read I2C data. The data might have already been read by
202 * the interrupt code, otherwise it is sitting in the data
207 data_read(ig4iic_softc_t *sc)
211 if (sc->rpos == sc->rnext) {
212 c = (uint8_t)reg_read(sc, IG4_REG_DATA_CMD);
214 c = sc->rbuf[sc->rpos & IG4_RBUFMASK];
221 * Set the slave address. The controller must be disabled when
222 * changing the address.
224 * This operation does not issue anything to the I2C bus but sets
225 * the target address for when the controller later issues a START.
229 set_slave_addr(ig4iic_softc_t *sc, uint8_t slave, int trans_op)
235 use_10bit = sc->use_10bit;
236 if (trans_op & SMB_TRANS_7BIT)
238 if (trans_op & SMB_TRANS_10BIT)
241 if (sc->slave_valid && sc->last_slave == slave &&
242 sc->use_10bit == use_10bit) {
245 sc->use_10bit = use_10bit;
248 * Wait for TXFIFO to drain before disabling the controller.
250 * If a write message has not been completed it's really a
251 * programming error, but for now in that case issue an extra
254 * If a read message has not been completed it's also a programming
255 * error, for now just ignore it.
257 wait_status(sc, IG4_STATUS_TX_NOTFULL);
258 if (sc->write_started) {
259 reg_write(sc, IG4_REG_DATA_CMD, IG4_DATA_STOP);
260 sc->write_started = 0;
262 if (sc->read_started)
263 sc->read_started = 0;
264 wait_status(sc, IG4_STATUS_TX_EMPTY);
266 set_controller(sc, 0);
267 ctl = reg_read(sc, IG4_REG_CTL);
268 ctl &= ~IG4_CTL_10BIT;
269 ctl |= IG4_CTL_RESTARTEN;
273 tar |= IG4_TAR_10BIT;
274 ctl |= IG4_CTL_10BIT;
276 reg_write(sc, IG4_REG_CTL, ctl);
277 reg_write(sc, IG4_REG_TAR_ADD, tar);
278 set_controller(sc, IG4_I2C_ENABLE);
280 sc->last_slave = slave;
284 * Issue START with byte command, possible count, and a variable length
285 * read or write buffer, then possible turn-around read. The read also
286 * has a possible count received.
290 * Quick: START+ADDR+RD/WR STOP
292 * Normal: START+ADDR+WR CMD DATA..DATA STOP
295 * RESTART+ADDR RDATA..RDATA STOP
296 * (can also be used for I2C transactions)
298 * Process Call: START+ADDR+WR CMD DATAL DATAH
299 * RESTART+ADDR+RD RDATAL RDATAH STOP
301 * Block: START+ADDR+RD CMD
302 * RESTART+ADDR+RD RCOUNT DATA... STOP
305 * RESTART+ADDR+WR WCOUNT DATA... STOP
307 * For I2C - basically, no *COUNT fields, possibly no *CMD field. If the
308 * sender needs to issue a 2-byte command it will incorporate it
309 * into the write buffer and also set NOCMD.
311 * Generally speaking, the START+ADDR / RESTART+ADDR is handled automatically
312 * by the controller at the beginning of a command sequence or on a data
313 * direction turn-around, and we only need to tell it when to issue the STOP.
316 smb_transaction(ig4iic_softc_t *sc, char cmd, int op,
317 char *wbuf, int wcount, char *rbuf, int rcount, int *actualp)
324 * Debugging - dump registers
327 unit = device_get_unit(sc->dev);
328 if (ig4_dump & (1 << unit)) {
329 ig4_dump &= ~(1 << unit);
335 * Issue START or RESTART with next data byte, clear any previous
336 * abort condition that may have been holding the txfifo in reset.
338 last = IG4_DATA_RESTART;
339 reg_read(sc, IG4_REG_CLR_TX_ABORT);
344 * Issue command if not told otherwise (smbus).
346 if ((op & SMB_TRANS_NOCMD) == 0) {
347 error = wait_status(sc, IG4_STATUS_TX_NOTFULL);
351 if (wcount == 0 && rcount == 0 && (op & SMB_TRANS_NOSTOP) == 0)
352 last |= IG4_DATA_STOP;
353 reg_write(sc, IG4_REG_DATA_CMD, last);
358 * Clean out any previously received data.
360 if (sc->rpos != sc->rnext &&
361 (op & SMB_TRANS_NOREPORT) == 0) {
362 device_printf(sc->dev,
363 "discarding %d bytes of spurious data\n",
364 sc->rnext - sc->rpos);
370 * If writing and not told otherwise, issue the write count (smbus).
372 if (wcount && (op & SMB_TRANS_NOCNT) == 0) {
373 error = wait_status(sc, IG4_STATUS_TX_NOTFULL);
377 reg_write(sc, IG4_REG_DATA_CMD, last);
385 error = wait_status(sc, IG4_STATUS_TX_NOTFULL);
388 last |= (u_char)*wbuf;
389 if (wcount == 1 && rcount == 0 && (op & SMB_TRANS_NOSTOP) == 0)
390 last |= IG4_DATA_STOP;
391 reg_write(sc, IG4_REG_DATA_CMD, last);
398 * Issue reads to xmit FIFO (strange, I know) to tell the controller
399 * to clock in data. At the moment just issue one read ahead to
400 * pipeline the incoming data.
402 * NOTE: In the case of NOCMD and wcount == 0 we still issue a
403 * RESTART here, even if the data direction has not changed
404 * from the previous CHAINing call. This we force the RESTART.
405 * (A new START is issued automatically by the controller in
406 * the other nominal cases such as a data direction change or
407 * a previous STOP was issued).
409 * If this will be the last byte read we must also issue the STOP
410 * at the end of the read.
413 last = IG4_DATA_RESTART | IG4_DATA_COMMAND_RD;
415 (op & (SMB_TRANS_NOSTOP | SMB_TRANS_NOCNT)) ==
417 last |= IG4_DATA_STOP;
419 reg_write(sc, IG4_REG_DATA_CMD, last);
420 last = IG4_DATA_COMMAND_RD;
424 * Bulk read (i2c) and count field handling (smbus)
428 * Maintain a pipeline by queueing the allowance for the next
429 * read before waiting for the current read.
432 if (op & SMB_TRANS_NOCNT)
433 last = (rcount == 2) ? IG4_DATA_STOP : 0;
436 reg_write(sc, IG4_REG_DATA_CMD, IG4_DATA_COMMAND_RD |
439 error = wait_status(sc, IG4_STATUS_RX_NOTEMPTY);
441 if ((op & SMB_TRANS_NOREPORT) == 0) {
442 device_printf(sc->dev,
443 "rx timeout addr 0x%02x\n",
448 last = data_read(sc);
450 if (op & SMB_TRANS_NOCNT) {
451 *rbuf = (u_char)last;
458 * Handle count field (smbus), which is not part of
459 * the rcount'ed buffer. The first read data in a
460 * bulk transfer is the count.
462 * XXX if rcount is loaded as 0 how do I generate a
463 * STOP now without issuing another RD or WR?
465 if (rcount > (u_char)last)
466 rcount = (u_char)last;
467 op |= SMB_TRANS_NOCNT;
472 /* XXX wait for xmit buffer to become empty */
473 last = reg_read(sc, IG4_REG_TX_ABRT_SOURCE);
479 * SMBUS API FUNCTIONS
481 * Called from ig4iic_pci_attach/detach()
484 ig4iic_attach(ig4iic_softc_t *sc)
489 lockmgr(&sc->lk, LK_EXCLUSIVE);
491 v = reg_read(sc, IG4_REG_COMP_TYPE);
492 kprintf("type %08x", v);
493 v = reg_read(sc, IG4_REG_COMP_PARAM1);
494 kprintf(" params %08x", v);
495 v = reg_read(sc, IG4_REG_GENERAL);
496 kprintf(" general %08x", v);
497 if ((v & IG4_GENERAL_SWMODE) == 0) {
498 v |= IG4_GENERAL_SWMODE;
499 reg_write(sc, IG4_REG_GENERAL, v);
500 v = reg_read(sc, IG4_REG_GENERAL);
501 kprintf(" (updated %08x)", v);
504 v = reg_read(sc, IG4_REG_SW_LTR_VALUE);
505 kprintf(" swltr %08x", v);
506 v = reg_read(sc, IG4_REG_AUTO_LTR_VALUE);
507 kprintf(" autoltr %08x", v);
509 v = reg_read(sc, IG4_REG_COMP_VER);
510 kprintf(" version %08x\n", v);
511 if (v != IG4_COMP_VER) {
516 v = reg_read(sc, IG4_REG_SS_SCL_HCNT);
517 kprintf("SS_SCL_HCNT=%08x", v);
518 v = reg_read(sc, IG4_REG_SS_SCL_LCNT);
519 kprintf(" LCNT=%08x", v);
520 v = reg_read(sc, IG4_REG_FS_SCL_HCNT);
521 kprintf(" FS_SCL_HCNT=%08x", v);
522 v = reg_read(sc, IG4_REG_FS_SCL_LCNT);
523 kprintf(" LCNT=%08x\n", v);
524 v = reg_read(sc, IG4_REG_SDA_HOLD);
525 kprintf("HOLD %08x\n", v);
527 v = reg_read(sc, IG4_REG_SS_SCL_HCNT);
528 reg_write(sc, IG4_REG_FS_SCL_HCNT, v);
529 v = reg_read(sc, IG4_REG_SS_SCL_LCNT);
530 reg_write(sc, IG4_REG_FS_SCL_LCNT, v);
533 * Program based on a 25000 Hz clock. This is a bit of a
534 * hack (obviously). The defaults are 400 and 470 for standard
535 * and 60 and 130 for fast. The defaults for standard fail
536 * utterly (presumably cause an abort) because the clock time
537 * is ~18.8ms by default. This brings it down to ~4ms (for now).
539 reg_write(sc, IG4_REG_SS_SCL_HCNT, 100);
540 reg_write(sc, IG4_REG_SS_SCL_LCNT, 125);
541 reg_write(sc, IG4_REG_FS_SCL_HCNT, 100);
542 reg_write(sc, IG4_REG_FS_SCL_LCNT, 125);
545 * Use a threshold of 1 so we get interrupted on each character,
546 * allowing us to use lksleep() in our poll code. Not perfect
547 * but this is better than using DELAY() for receiving data.
549 reg_write(sc, IG4_REG_RX_TL, 1);
551 reg_write(sc, IG4_REG_CTL,
553 IG4_CTL_SLAVE_DISABLE |
557 * When ig4 is attached via ACPI, (child) devices should access the
558 * smbus via I2cSerialBus ACPI resources instead.
560 if (strcmp("acpi", device_get_name(device_get_parent(sc->dev))) != 0) {
561 sc->smb = device_add_child(sc->dev, "smbus", -1);
562 if (sc->smb == NULL) {
563 device_printf(sc->dev, "smbus driver not found\n");
569 sc->acpismb = device_add_child(sc->dev, "smbacpi", -1);
570 if (sc->acpismb == NULL) {
571 device_printf(sc->dev, "smbacpi driver not found\n");
572 if (sc->smb == NULL) {
580 * Don't do this, it blows up the PCI config
582 reg_write(sc, IG4_REG_RESETS, IG4_RESETS_ASSERT);
583 reg_write(sc, IG4_REG_RESETS, IG4_RESETS_DEASSERT);
587 * Interrupt on STOP detect or receive character ready
589 if (set_controller(sc, 0))
590 device_printf(sc->dev, "controller error during attach-1\n");
591 if (set_controller(sc, IG4_I2C_ENABLE))
592 device_printf(sc->dev, "controller error during attach-2\n");
593 error = bus_setup_intr(sc->dev, sc->intr_res, 0,
594 ig4iic_intr, sc, &sc->intr_handle, NULL);
596 device_printf(sc->dev,
597 "Unable to setup irq: error %d\n", error);
601 /* Attach us to the smbus */
602 lockmgr(&sc->lk, LK_RELEASE);
603 error = bus_generic_attach(sc->dev);
604 lockmgr(&sc->lk, LK_EXCLUSIVE);
606 device_printf(sc->dev,
607 "failed to attach child: error %d\n", error);
610 sc->generic_attached = 1;
613 lockmgr(&sc->lk, LK_RELEASE);
618 ig4iic_detach(ig4iic_softc_t *sc)
622 lockmgr(&sc->lk, LK_EXCLUSIVE);
624 reg_write(sc, IG4_REG_INTR_MASK, 0);
625 set_controller(sc, 0);
627 if (sc->generic_attached) {
628 error = bus_generic_detach(sc->dev);
631 sc->generic_attached = 0;
634 device_delete_child(sc->dev, sc->smb);
638 device_delete_child(sc->dev, sc->acpismb);
641 if (sc->intr_handle) {
642 bus_teardown_intr(sc->dev, sc->intr_res, sc->intr_handle);
643 sc->intr_handle = NULL;
648 lockmgr(&sc->lk, LK_RELEASE);
653 ig4iic_smb_callback(device_t dev, int index, void *data)
655 ig4iic_softc_t *sc = device_get_softc(dev);
658 lockmgr(&sc->lk, LK_EXCLUSIVE);
661 case SMB_REQUEST_BUS:
664 case SMB_RELEASE_BUS:
672 lockmgr(&sc->lk, LK_RELEASE);
678 * Quick command. i.e. START + cmd + R/W + STOP and no data. It is
679 * unclear to me how I could implement this with the intel i2c controller
680 * because the controler sends STARTs and STOPs automatically with data.
683 ig4iic_smb_quick(device_t dev, u_char slave, int how)
685 ig4iic_softc_t *sc = device_get_softc(dev);
688 lockmgr(&sc->lk, LK_EXCLUSIVE);
692 error = SMB_ENOTSUPP;
695 error = SMB_ENOTSUPP;
698 error = SMB_ENOTSUPP;
701 lockmgr(&sc->lk, LK_RELEASE);
707 * Incremental send byte without stop (?). It is unclear why the slave
708 * address is specified if this presumably is used in combination with
709 * ig4iic_smb_quick().
711 * (Also, how would this work anyway? Issue the last byte with writeb()?)
714 ig4iic_smb_sendb(device_t dev, u_char slave, char byte)
716 ig4iic_softc_t *sc = device_get_softc(dev);
720 lockmgr(&sc->lk, LK_EXCLUSIVE);
722 set_slave_addr(sc, slave, 0);
724 if (wait_status(sc, IG4_STATUS_TX_NOTFULL) == 0) {
725 reg_write(sc, IG4_REG_DATA_CMD, cmd);
728 error = SMB_ETIMEOUT;
731 lockmgr(&sc->lk, LK_RELEASE);
736 * Incremental receive byte without stop (?). It is unclear why the slave
737 * address is specified if this presumably is used in combination with
738 * ig4iic_smb_quick().
741 ig4iic_smb_recvb(device_t dev, u_char slave, char *byte)
743 ig4iic_softc_t *sc = device_get_softc(dev);
746 lockmgr(&sc->lk, LK_EXCLUSIVE);
748 set_slave_addr(sc, slave, 0);
749 reg_write(sc, IG4_REG_DATA_CMD, IG4_DATA_COMMAND_RD);
750 if (wait_status(sc, IG4_STATUS_RX_NOTEMPTY) == 0) {
751 *byte = data_read(sc);
755 error = SMB_ETIMEOUT;
758 lockmgr(&sc->lk, LK_RELEASE);
763 * Write command and single byte in transaction.
766 ig4iic_smb_writeb(device_t dev, u_char slave, char cmd, char byte)
768 ig4iic_softc_t *sc = device_get_softc(dev);
771 lockmgr(&sc->lk, LK_EXCLUSIVE);
773 set_slave_addr(sc, slave, 0);
774 error = smb_transaction(sc, cmd, SMB_TRANS_NOCNT,
775 &byte, 1, NULL, 0, NULL);
777 lockmgr(&sc->lk, LK_RELEASE);
782 * Write command and single word in transaction.
785 ig4iic_smb_writew(device_t dev, u_char slave, char cmd, short word)
787 ig4iic_softc_t *sc = device_get_softc(dev);
791 lockmgr(&sc->lk, LK_EXCLUSIVE);
793 set_slave_addr(sc, slave, 0);
794 buf[0] = word & 0xFF;
796 error = smb_transaction(sc, cmd, SMB_TRANS_NOCNT,
797 buf, 2, NULL, 0, NULL);
799 lockmgr(&sc->lk, LK_RELEASE);
804 * write command and read single byte in transaction.
807 ig4iic_smb_readb(device_t dev, u_char slave, char cmd, char *byte)
809 ig4iic_softc_t *sc = device_get_softc(dev);
812 lockmgr(&sc->lk, LK_EXCLUSIVE);
814 set_slave_addr(sc, slave, 0);
815 error = smb_transaction(sc, cmd, SMB_TRANS_NOCNT,
816 NULL, 0, byte, 1, NULL);
818 lockmgr(&sc->lk, LK_RELEASE);
823 * write command and read word in transaction.
826 ig4iic_smb_readw(device_t dev, u_char slave, char cmd, short *word)
828 ig4iic_softc_t *sc = device_get_softc(dev);
832 lockmgr(&sc->lk, LK_EXCLUSIVE);
834 set_slave_addr(sc, slave, 0);
835 if ((error = smb_transaction(sc, cmd, SMB_TRANS_NOCNT,
836 NULL, 0, buf, 2, NULL)) == 0) {
837 *word = (u_char)buf[0] | ((u_char)buf[1] << 8);
840 lockmgr(&sc->lk, LK_RELEASE);
845 * write command and word and read word in transaction
848 ig4iic_smb_pcall(device_t dev, u_char slave, char cmd,
849 short sdata, short *rdata)
851 ig4iic_softc_t *sc = device_get_softc(dev);
856 lockmgr(&sc->lk, LK_EXCLUSIVE);
858 set_slave_addr(sc, slave, 0);
859 wbuf[0] = sdata & 0xFF;
860 wbuf[1] = sdata >> 8;
861 if ((error = smb_transaction(sc, cmd, SMB_TRANS_NOCNT,
862 wbuf, 2, rbuf, 2, NULL)) == 0) {
863 *rdata = (u_char)rbuf[0] | ((u_char)rbuf[1] << 8);
866 lockmgr(&sc->lk, LK_RELEASE);
871 ig4iic_smb_bwrite(device_t dev, u_char slave, char cmd,
872 u_char wcount, char *buf)
874 ig4iic_softc_t *sc = device_get_softc(dev);
877 lockmgr(&sc->lk, LK_EXCLUSIVE);
879 set_slave_addr(sc, slave, 0);
880 error = smb_transaction(sc, cmd, 0,
881 buf, wcount, NULL, 0, NULL);
883 lockmgr(&sc->lk, LK_RELEASE);
888 ig4iic_smb_bread(device_t dev, u_char slave, char cmd,
889 u_char *countp_char, char *buf)
891 ig4iic_softc_t *sc = device_get_softc(dev);
892 int rcount = *countp_char;
895 lockmgr(&sc->lk, LK_EXCLUSIVE);
897 set_slave_addr(sc, slave, 0);
898 error = smb_transaction(sc, cmd, 0,
899 NULL, 0, buf, rcount, &rcount);
900 *countp_char = rcount;
902 lockmgr(&sc->lk, LK_RELEASE);
907 ig4iic_smb_trans(device_t dev, int slave, char cmd, int op,
908 char *wbuf, int wcount, char *rbuf, int rcount,
911 ig4iic_softc_t *sc = device_get_softc(dev);
914 lockmgr(&sc->lk, LK_EXCLUSIVE);
916 set_slave_addr(sc, slave, op);
917 error = smb_transaction(sc, cmd, op,
918 wbuf, wcount, rbuf, rcount, actualp);
920 lockmgr(&sc->lk, LK_RELEASE);
925 * Interrupt Operation
929 ig4iic_intr(void *cookie)
931 ig4iic_softc_t *sc = cookie;
934 lockmgr(&sc->lk, LK_EXCLUSIVE);
935 /* reg_write(sc, IG4_REG_INTR_MASK, IG4_INTR_STOP_DET);*/
936 reg_read(sc, IG4_REG_CLR_INTR);
937 status = reg_read(sc, IG4_REG_I2C_STA);
938 while (status & IG4_STATUS_RX_NOTEMPTY) {
939 sc->rbuf[sc->rnext & IG4_RBUFMASK] =
940 (uint8_t)reg_read(sc, IG4_REG_DATA_CMD);
942 status = reg_read(sc, IG4_REG_I2C_STA);
945 lockmgr(&sc->lk, LK_RELEASE);
948 #define REGDUMP(sc, reg) \
949 device_printf(sc->dev, " %-23s %08x\n", #reg, reg_read(sc, reg))
953 ig4iic_dump(ig4iic_softc_t *sc)
955 device_printf(sc->dev, "ig4iic register dump:\n");
956 REGDUMP(sc, IG4_REG_CTL);
957 REGDUMP(sc, IG4_REG_TAR_ADD);
958 REGDUMP(sc, IG4_REG_SS_SCL_HCNT);
959 REGDUMP(sc, IG4_REG_SS_SCL_LCNT);
960 REGDUMP(sc, IG4_REG_FS_SCL_HCNT);
961 REGDUMP(sc, IG4_REG_FS_SCL_LCNT);
962 REGDUMP(sc, IG4_REG_INTR_STAT);
963 REGDUMP(sc, IG4_REG_INTR_MASK);
964 REGDUMP(sc, IG4_REG_RAW_INTR_STAT);
965 REGDUMP(sc, IG4_REG_RX_TL);
966 REGDUMP(sc, IG4_REG_TX_TL);
967 REGDUMP(sc, IG4_REG_I2C_EN);
968 REGDUMP(sc, IG4_REG_I2C_STA);
969 REGDUMP(sc, IG4_REG_TXFLR);
970 REGDUMP(sc, IG4_REG_RXFLR);
971 REGDUMP(sc, IG4_REG_SDA_HOLD);
972 REGDUMP(sc, IG4_REG_TX_ABRT_SOURCE);
973 REGDUMP(sc, IG4_REG_SLV_DATA_NACK);
974 REGDUMP(sc, IG4_REG_DMA_CTRL);
975 REGDUMP(sc, IG4_REG_DMA_TDLR);
976 REGDUMP(sc, IG4_REG_DMA_RDLR);
977 REGDUMP(sc, IG4_REG_SDA_SETUP);
978 REGDUMP(sc, IG4_REG_ENABLE_STATUS);
979 REGDUMP(sc, IG4_REG_COMP_PARAM1);
980 REGDUMP(sc, IG4_REG_COMP_VER);
981 REGDUMP(sc, IG4_REG_COMP_TYPE);
982 REGDUMP(sc, IG4_REG_CLK_PARMS);
983 REGDUMP(sc, IG4_REG_RESETS);
984 REGDUMP(sc, IG4_REG_GENERAL);
985 REGDUMP(sc, IG4_REG_SW_LTR_VALUE);
986 REGDUMP(sc, IG4_REG_AUTO_LTR_VALUE);
990 DRIVER_MODULE(smbus, ig4iic, smbus_driver, smbus_devclass, NULL, NULL);