1 /**************************************************************************
3 Copyright © 2006 Dave Airlie
7 Permission is hereby granted, free of charge, to any person obtaining a
8 copy of this software and associated documentation files (the
9 "Software"), to deal in the Software without restriction, including
10 without limitation the rights to use, copy, modify, merge, publish,
11 distribute, sub license, and/or sell copies of the Software, and to
12 permit persons to whom the Software is furnished to do so, subject to
13 the following conditions:
15 The above copyright notice and this permission notice (including the
16 next paragraph) shall be included in all copies or substantial portions
19 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
23 ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 **************************************************************************/
31 #define CH7xxx_REG_VID 0x4a
32 #define CH7xxx_REG_DID 0x4b
34 #define CH7011_VID 0x83 /* 7010 as well */
35 #define CH7010B_VID 0x05
36 #define CH7009A_VID 0x84
37 #define CH7009B_VID 0x85
38 #define CH7301_VID 0x95
40 #define CH7xxx_VID 0x84
41 #define CH7xxx_DID 0x17
42 #define CH7010_DID 0x16
44 #define CH7xxx_NUM_REGS 0x4c
46 #define CH7xxx_CM 0x1c
47 #define CH7xxx_CM_XCM (1<<0)
48 #define CH7xxx_CM_MCP (1<<2)
49 #define CH7xxx_INPUT_CLOCK 0x1d
50 #define CH7xxx_GPIO 0x1e
51 #define CH7xxx_GPIO_HPIR (1<<3)
52 #define CH7xxx_IDF 0x1f
54 #define CH7xxx_IDF_HSP (1<<3)
55 #define CH7xxx_IDF_VSP (1<<4)
57 #define CH7xxx_CONNECTION_DETECT 0x20
58 #define CH7xxx_CDET_DVI (1<<5)
60 #define CH7301_DAC_CNTL 0x21
61 #define CH7301_HOTPLUG 0x23
62 #define CH7xxx_TCTL 0x31
63 #define CH7xxx_TVCO 0x32
64 #define CH7xxx_TPCP 0x33
65 #define CH7xxx_TPD 0x34
66 #define CH7xxx_TPVT 0x35
67 #define CH7xxx_TLPF 0x36
68 #define CH7xxx_TCT 0x37
69 #define CH7301_TEST_PATTERN 0x48
71 #define CH7xxx_PM 0x49
72 #define CH7xxx_PM_FPD (1<<0)
73 #define CH7301_PM_DACPD0 (1<<1)
74 #define CH7301_PM_DACPD1 (1<<2)
75 #define CH7301_PM_DACPD2 (1<<3)
76 #define CH7xxx_PM_DVIL (1<<6)
77 #define CH7xxx_PM_DVIP (1<<7)
79 #define CH7301_SYNC_POLARITY 0x56
80 #define CH7301_SYNC_RGB_YUV (1<<0)
81 #define CH7301_SYNC_POL_DVI (1<<5)
84 * driver for the Chrontel 7xxx DVI chip over DVO.
87 static struct ch7xxx_id_struct {
91 { CH7011_VID, "CH7011" },
92 { CH7010B_VID, "CH7010B" },
93 { CH7009A_VID, "CH7009A" },
94 { CH7009B_VID, "CH7009B" },
95 { CH7301_VID, "CH7301" },
98 static struct ch7xxx_did_struct {
102 { CH7xxx_DID, "CH7XXX" },
103 { CH7010_DID, "CH7010B" },
110 static char *ch7xxx_get_id(uint8_t vid)
114 for (i = 0; i < ARRAY_SIZE(ch7xxx_ids); i++) {
115 if (ch7xxx_ids[i].vid == vid)
116 return ch7xxx_ids[i].name;
122 static char *ch7xxx_get_did(uint8_t did)
126 for (i = 0; i < ARRAY_SIZE(ch7xxx_dids); i++) {
127 if (ch7xxx_dids[i].did == did)
128 return ch7xxx_dids[i].name;
134 /** Reads an 8 bit register */
135 static bool ch7xxx_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch)
137 struct intel_iic_softc *sc;
138 struct ch7xxx_priv *ch7xxx = dvo->dev_priv;
139 struct i2c_adapter *adapter = dvo->i2c_bus;
143 struct i2c_msg msgs[] = {
145 .slave = dvo->slave_addr << 1,
151 .slave = dvo->slave_addr << 1,
161 sc = device_get_softc(adapter);
163 if (iicbus_transfer(adapter, msgs, 2) == 0) {
168 if (!ch7xxx->quiet) {
169 DRM_DEBUG_KMS("Unable to read register 0x%02x from %s:%02x.\n",
170 addr, sc->name, dvo->slave_addr);
175 /** Writes an 8 bit register */
176 static bool ch7xxx_writeb(struct intel_dvo_device *dvo, int addr, uint8_t ch)
178 struct intel_iic_softc *sc;
179 struct ch7xxx_priv *ch7xxx = dvo->dev_priv;
180 struct i2c_adapter *adapter = dvo->i2c_bus;
182 struct i2c_msg msg = {
183 .slave = dvo->slave_addr << 1,
192 sc = device_get_softc(adapter);
194 if (iicbus_transfer(adapter, &msg, 1) == 0)
197 if (!ch7xxx->quiet) {
198 DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n",
199 addr, sc->name, dvo->slave_addr);
205 static bool ch7xxx_init(struct intel_dvo_device *dvo,
206 struct i2c_adapter *adapter)
208 struct intel_iic_softc *sc;
209 /* this will detect the CH7xxx chip on the specified i2c bus */
210 struct ch7xxx_priv *ch7xxx;
211 uint8_t vendor, device;
214 sc = device_get_softc(adapter);
216 ch7xxx = kzalloc(sizeof(struct ch7xxx_priv), GFP_KERNEL);
220 dvo->i2c_bus = adapter;
221 dvo->dev_priv = ch7xxx;
222 ch7xxx->quiet = true;
224 if (!ch7xxx_readb(dvo, CH7xxx_REG_VID, &vendor))
227 name = ch7xxx_get_id(vendor);
229 DRM_DEBUG_KMS("ch7xxx not detected; got 0x%02x from %s "
231 vendor, sc->name, dvo->slave_addr);
236 if (!ch7xxx_readb(dvo, CH7xxx_REG_DID, &device))
239 devid = ch7xxx_get_did(device);
241 DRM_DEBUG_KMS("ch7xxx not detected; got 0x%02x from %s "
243 vendor, sc->name, dvo->slave_addr);
247 ch7xxx->quiet = false;
248 DRM_DEBUG_KMS("Detected %s chipset, vendor/device ID 0x%02x/0x%02x\n",
249 name, vendor, device);
256 static enum drm_connector_status ch7xxx_detect(struct intel_dvo_device *dvo)
258 uint8_t cdet, orig_pm, pm;
260 ch7xxx_readb(dvo, CH7xxx_PM, &orig_pm);
263 pm &= ~CH7xxx_PM_FPD;
264 pm |= CH7xxx_PM_DVIL | CH7xxx_PM_DVIP;
266 ch7xxx_writeb(dvo, CH7xxx_PM, pm);
268 ch7xxx_readb(dvo, CH7xxx_CONNECTION_DETECT, &cdet);
270 ch7xxx_writeb(dvo, CH7xxx_PM, orig_pm);
272 if (cdet & CH7xxx_CDET_DVI)
273 return connector_status_connected;
274 return connector_status_disconnected;
277 static enum drm_mode_status ch7xxx_mode_valid(struct intel_dvo_device *dvo,
278 struct drm_display_mode *mode)
280 if (mode->clock > 165000)
281 return MODE_CLOCK_HIGH;
286 static void ch7xxx_mode_set(struct intel_dvo_device *dvo,
287 struct drm_display_mode *mode,
288 struct drm_display_mode *adjusted_mode)
290 uint8_t tvco, tpcp, tpd, tlpf, idf;
292 if (mode->clock <= 65000) {
304 ch7xxx_writeb(dvo, CH7xxx_TCTL, 0x00);
305 ch7xxx_writeb(dvo, CH7xxx_TVCO, tvco);
306 ch7xxx_writeb(dvo, CH7xxx_TPCP, tpcp);
307 ch7xxx_writeb(dvo, CH7xxx_TPD, tpd);
308 ch7xxx_writeb(dvo, CH7xxx_TPVT, 0x30);
309 ch7xxx_writeb(dvo, CH7xxx_TLPF, tlpf);
310 ch7xxx_writeb(dvo, CH7xxx_TCT, 0x00);
312 ch7xxx_readb(dvo, CH7xxx_IDF, &idf);
314 idf &= ~(CH7xxx_IDF_HSP | CH7xxx_IDF_VSP);
315 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
316 idf |= CH7xxx_IDF_HSP;
318 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
319 idf |= CH7xxx_IDF_VSP;
321 ch7xxx_writeb(dvo, CH7xxx_IDF, idf);
324 /* set the CH7xxx power state */
325 static void ch7xxx_dpms(struct intel_dvo_device *dvo, bool enable)
328 ch7xxx_writeb(dvo, CH7xxx_PM, CH7xxx_PM_DVIL | CH7xxx_PM_DVIP);
330 ch7xxx_writeb(dvo, CH7xxx_PM, CH7xxx_PM_FPD);
333 static bool ch7xxx_get_hw_state(struct intel_dvo_device *dvo)
337 ch7xxx_readb(dvo, CH7xxx_PM, &val);
339 if (val & (CH7xxx_PM_DVIL | CH7xxx_PM_DVIP))
345 static void ch7xxx_dump_regs(struct intel_dvo_device *dvo)
349 for (i = 0; i < CH7xxx_NUM_REGS; i++) {
352 DRM_DEBUG_KMS("\n %02X: ", i);
353 ch7xxx_readb(dvo, i, &val);
354 DRM_DEBUG_KMS("%02X ", val);
358 static void ch7xxx_destroy(struct intel_dvo_device *dvo)
360 struct ch7xxx_priv *ch7xxx = dvo->dev_priv;
364 dvo->dev_priv = NULL;
368 struct intel_dvo_dev_ops ch7xxx_ops = {
370 .detect = ch7xxx_detect,
371 .mode_valid = ch7xxx_mode_valid,
372 .mode_set = ch7xxx_mode_set,
374 .get_hw_state = ch7xxx_get_hw_state,
375 .dump_regs = ch7xxx_dump_regs,
376 .destroy = ch7xxx_destroy,