2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2000, 2001
4 * Bill Paul <william.paul@windriver.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
33 * $FreeBSD: src/sys/dev/lge/if_lge.c,v 1.5.2.2 2001/12/14 19:49:23 jlemon Exp $
34 * $DragonFly: src/sys/dev/netif/lge/if_lge.c,v 1.20 2005/05/23 16:00:44 joerg Exp $
38 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public
39 * documentation not available, but ask me nicely.
41 * Written by Bill Paul <william.paul@windriver.com>
46 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs.
47 * It's a 64-bit PCI part that supports TCP/IP checksum offload,
48 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There
49 * are three supported methods for data transfer between host and
50 * NIC: programmed I/O, traditional scatter/gather DMA and Packet
51 * Propulsion Technology (tm) DMA. The latter mechanism is a form
52 * of double buffer DMA where the packet data is copied to a
53 * pre-allocated DMA buffer who's physical address has been loaded
54 * into a table at device initialization time. The rationale is that
55 * the virtual to physical address translation needed for normal
56 * scatter/gather DMA is more expensive than the data copy needed
57 * for double buffering. This may be true in Windows NT and the like,
58 * but it isn't true for us, at least on the x86 arch. This driver
59 * uses the scatter/gather I/O method for both TX and RX.
61 * The LXT1001 only supports TCP/IP checksum offload on receive.
62 * Also, the VLAN tagging is done using a 16-entry table which allows
63 * the chip to perform hardware filtering based on VLAN tags. Sadly,
64 * our vlan support doesn't currently play well with this kind of
68 * - Jeff James at Intel, for arranging to have the LXT1001 manual
69 * released (at long last)
70 * - Beny Chen at D-Link, for actually sending it to me
71 * - Brad Short and Keith Alexis at SMC, for sending me sample
72 * SMC9462SX and SMC9462TX adapters for testing
73 * - Paul Saab at Y!, for not killing me (though it remains to be seen
74 * if in fact he did me much of a favor)
77 #include <sys/param.h>
78 #include <sys/systm.h>
79 #include <sys/sockio.h>
81 #include <sys/malloc.h>
82 #include <sys/kernel.h>
83 #include <sys/socket.h>
86 #include <net/ifq_var.h>
87 #include <net/if_arp.h>
88 #include <net/ethernet.h>
89 #include <net/if_dl.h>
90 #include <net/if_media.h>
94 #include <vm/vm.h> /* for vtophys */
95 #include <vm/pmap.h> /* for vtophys */
96 #include <machine/bus.h>
97 #include <machine/resource.h>
101 #include <dev/netif/mii_layer/mii.h>
102 #include <dev/netif/mii_layer/miivar.h>
104 #include <bus/pci/pcireg.h>
105 #include <bus/pci/pcivar.h>
107 #define LGE_USEIOSPACE
109 #include "if_lgereg.h"
111 /* "controller miibus0" required. See GENERIC if you get errors here. */
112 #include "miibus_if.h"
115 * Various supported device vendors/types and their names.
117 static struct lge_type lge_devs[] = {
118 { LGE_VENDORID, LGE_DEVICEID, "Level 1 Gigabit Ethernet" },
122 static int lge_probe(device_t);
123 static int lge_attach(device_t);
124 static int lge_detach(device_t);
126 static int lge_alloc_jumbo_mem(struct lge_softc *);
127 static void lge_free_jumbo_mem(struct lge_softc *);
128 static void *lge_jalloc(struct lge_softc *);
129 static void lge_jfree(caddr_t, u_int);
130 static void lge_jref(caddr_t, u_int);
132 static int lge_newbuf(struct lge_softc *, struct lge_rx_desc *,
134 static int lge_encap(struct lge_softc *, struct mbuf *, uint32_t *);
135 static void lge_rxeof(struct lge_softc *, int);
136 static void lge_rxeoc(struct lge_softc *);
137 static void lge_txeof(struct lge_softc *);
138 static void lge_intr(void *);
139 static void lge_tick(void *);
140 static void lge_start(struct ifnet *);
141 static int lge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
142 static void lge_init(void *);
143 static void lge_stop(struct lge_softc *);
144 static void lge_watchdog(struct ifnet *);
145 static void lge_shutdown(device_t);
146 static int lge_ifmedia_upd(struct ifnet *);
147 static void lge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
149 static void lge_eeprom_getword(struct lge_softc *, int, uint16_t *);
150 static void lge_read_eeprom(struct lge_softc *, caddr_t, int, int);
152 static int lge_miibus_readreg(device_t, int, int);
153 static int lge_miibus_writereg(device_t, int, int, int);
154 static void lge_miibus_statchg(device_t);
156 static void lge_setmulti(struct lge_softc *);
157 static uint32_t lge_crc(struct lge_softc *, caddr_t);
158 static void lge_reset(struct lge_softc *);
159 static int lge_list_rx_init(struct lge_softc *);
160 static int lge_list_tx_init(struct lge_softc *);
162 #ifdef LGE_USEIOSPACE
163 #define LGE_RES SYS_RES_IOPORT
164 #define LGE_RID LGE_PCI_LOIO
166 #define LGE_RES SYS_RES_MEMORY
167 #define LGE_RID LGE_PCI_LOMEM
170 static device_method_t lge_methods[] = {
171 /* Device interface */
172 DEVMETHOD(device_probe, lge_probe),
173 DEVMETHOD(device_attach, lge_attach),
174 DEVMETHOD(device_detach, lge_detach),
175 DEVMETHOD(device_shutdown, lge_shutdown),
178 DEVMETHOD(bus_print_child, bus_generic_print_child),
179 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
182 DEVMETHOD(miibus_readreg, lge_miibus_readreg),
183 DEVMETHOD(miibus_writereg, lge_miibus_writereg),
184 DEVMETHOD(miibus_statchg, lge_miibus_statchg),
189 static DEFINE_CLASS_0(lge, lge_driver, lge_methods, sizeof(struct lge_softc));
190 static devclass_t lge_devclass;
192 DECLARE_DUMMY_MODULE(if_lge);
193 DRIVER_MODULE(if_lge, pci, lge_driver, lge_devclass, 0, 0);
194 DRIVER_MODULE(miibus, lge, miibus_driver, miibus_devclass, 0, 0);
196 #define LGE_SETBIT(sc, reg, x) \
197 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
199 #define LGE_CLRBIT(sc, reg, x) \
200 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
203 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | (x))
206 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~(x))
209 * Read a word of data stored in the EEPROM at address 'addr.'
212 lge_eeprom_getword(struct lge_softc *sc, int addr, uint16_t *dest)
217 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ|
218 LGE_EECTL_SINGLEACCESS | ((addr >> 1) << 8));
220 for (i = 0; i < LGE_TIMEOUT; i++) {
221 if ((CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ) == 0)
225 if (i == LGE_TIMEOUT) {
226 printf("lge%d: EEPROM read timed out\n", sc->lge_unit);
230 val = CSR_READ_4(sc, LGE_EEDATA);
233 *dest = (val >> 16) & 0xFFFF;
235 *dest = val & 0xFFFF;
239 * Read a sequence of words from the EEPROM.
242 lge_read_eeprom(struct lge_softc *sc, caddr_t dest, int off, int cnt)
245 uint16_t word = 0, *ptr;
247 for (i = 0; i < cnt; i++) {
248 lge_eeprom_getword(sc, off + i, &word);
249 ptr = (uint16_t *)(dest + (i * 2));
255 lge_miibus_readreg(device_t dev, int phy, int reg)
257 struct lge_softc *sc = device_get_softc(dev);
261 * If we have a non-PCS PHY, pretend that the internal
262 * autoneg stuff at PHY address 0 isn't there so that
263 * the miibus code will find only the GMII PHY.
265 if (sc->lge_pcs == 0 && phy == 0)
268 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ);
270 for (i = 0; i < LGE_TIMEOUT; i++) {
271 if ((CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY) == 0)
275 if (i == LGE_TIMEOUT) {
276 printf("lge%d: PHY read timed out\n", sc->lge_unit);
280 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16);
284 lge_miibus_writereg(device_t dev, int phy, int reg, int data)
286 struct lge_softc *sc = device_get_softc(dev);
289 CSR_WRITE_4(sc, LGE_GMIICTL,
290 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE);
292 for (i = 0; i < LGE_TIMEOUT; i++) {
293 if ((CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY) == 0)
297 if (i == LGE_TIMEOUT) {
298 printf("lge%d: PHY write timed out\n", sc->lge_unit);
306 lge_miibus_statchg(device_t dev)
308 struct lge_softc *sc = device_get_softc(dev);;
309 struct mii_data *mii = device_get_softc(sc->lge_miibus);
311 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED);
312 switch (IFM_SUBTYPE(mii->mii_media_active)) {
315 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000);
318 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100);
321 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10);
325 * Choose something, even if it's wrong. Clearing
326 * all the bits will hose autoneg on the internal
329 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000);
333 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
334 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX);
336 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX);
340 lge_crc(struct lge_softc *sc, caddr_t addr)
346 /* Compute CRC for the address value. */
347 crc = 0xFFFFFFFF; /* initial value */
349 for (i = 0; i < 6; i++) {
351 for (j = 0; j < 8; j++) {
352 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
356 crc = (crc ^ 0x04c11db6) | carry;
361 * return the filter bit position
363 return((crc >> 26) & 0x0000003F);
367 lge_setmulti(struct lge_softc *sc)
369 struct ifnet *ifp = &sc->arpcom.ac_if;
370 struct ifmultiaddr *ifma;
371 uint32_t h = 0, hashes[2] = { 0, 0 };
373 /* Make sure multicast hash table is enabled. */
374 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_MCAST);
376 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
377 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF);
378 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF);
382 /* first, zot all the existing hash bits */
383 CSR_WRITE_4(sc, LGE_MAR0, 0);
384 CSR_WRITE_4(sc, LGE_MAR1, 0);
386 /* now program new ones */
387 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
388 if (ifma->ifma_addr->sa_family != AF_LINK)
390 h = lge_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
392 hashes[0] |= (1 << h);
394 hashes[1] |= (1 << (h - 32));
397 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]);
398 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]);
404 lge_reset(struct lge_softc *sc)
408 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0 | LGE_MODE1_SOFTRST);
410 for (i = 0; i < LGE_TIMEOUT; i++) {
411 if ((CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST) == 0)
415 if (i == LGE_TIMEOUT)
416 printf("lge%d: reset never completed\n", sc->lge_unit);
418 /* Wait a little while for the chip to get its brains in order. */
423 * Probe for a Level 1 chip. Check the PCI vendor and device
424 * IDs against our list and return a device name if we find a match.
427 lge_probe(device_t dev)
430 uint16_t vendor, product;
432 vendor = pci_get_vendor(dev);
433 product = pci_get_device(dev);
435 for (t = lge_devs; t->lge_name != NULL; t++) {
436 if (vendor == t->lge_vid && product == t->lge_did) {
437 device_set_desc(dev, t->lge_name);
446 * Attach the interface. Allocate softc structures, do ifmedia
447 * setup and ethernet/BPF attach.
450 lge_attach(device_t dev)
452 uint8_t eaddr[ETHER_ADDR_LEN];
454 struct lge_softc *sc;
456 int unit, error = 0, rid, s;
460 sc = device_get_softc(dev);
461 unit = device_get_unit(dev);
462 callout_init(&sc->lge_stat_timer);
465 * Handle power management nonsense.
467 command = pci_read_config(dev, LGE_PCI_CAPID, 4) & 0x000000FF;
468 if (command == 0x01) {
470 command = pci_read_config(dev, LGE_PCI_PWRMGMTCTRL, 4);
471 if (command & LGE_PSTATE_MASK) {
472 uint32_t iobase, membase, irq;
474 /* Save important PCI config data. */
475 iobase = pci_read_config(dev, LGE_PCI_LOIO, 4);
476 membase = pci_read_config(dev, LGE_PCI_LOMEM, 4);
477 irq = pci_read_config(dev, LGE_PCI_INTLINE, 4);
479 /* Reset the power state. */
480 printf("lge%d: chip is in D%d power mode "
481 "-- setting to D0\n", unit, command & LGE_PSTATE_MASK);
482 command &= 0xFFFFFFFC;
483 pci_write_config(dev, LGE_PCI_PWRMGMTCTRL, command, 4);
485 /* Restore PCI config data. */
486 pci_write_config(dev, LGE_PCI_LOIO, iobase, 4);
487 pci_write_config(dev, LGE_PCI_LOMEM, membase, 4);
488 pci_write_config(dev, LGE_PCI_INTLINE, irq, 4);
493 * Map control/status registers.
495 command = pci_read_config(dev, PCIR_COMMAND, 4);
496 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
497 pci_write_config(dev, PCIR_COMMAND, command, 4);
498 command = pci_read_config(dev, PCIR_COMMAND, 4);
500 #ifdef LGE_USEIOSPACE
501 if (!(command & PCIM_CMD_PORTEN)) {
502 printf("lge%d: failed to enable I/O ports!\n", unit);
507 if (!(command & PCIM_CMD_MEMEN)) {
508 printf("lge%d: failed to enable memory mapping!\n", unit);
515 sc->lge_res = bus_alloc_resource(dev, LGE_RES, &rid,
516 0, ~0, 1, RF_ACTIVE);
518 if (sc->lge_res == NULL) {
519 printf("lge%d: couldn't map ports/memory\n", unit);
524 sc->lge_btag = rman_get_bustag(sc->lge_res);
525 sc->lge_bhandle = rman_get_bushandle(sc->lge_res);
527 /* Allocate interrupt */
529 sc->lge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
530 RF_SHAREABLE | RF_ACTIVE);
532 if (sc->lge_irq == NULL) {
533 printf("lge%d: couldn't map interrupt\n", unit);
534 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
539 error = bus_setup_intr(dev, sc->lge_irq, INTR_TYPE_NET,
540 lge_intr, sc, &sc->lge_intrhand);
543 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
544 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
545 printf("lge%d: couldn't set up irq\n", unit);
549 /* Reset the adapter. */
553 * Get station address from the EEPROM.
555 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1);
556 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1);
557 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1);
561 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF,
562 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
564 if (sc->lge_ldata == NULL) {
565 printf("lge%d: no memory for list buffers!\n", unit);
566 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
567 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
568 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
572 bzero(sc->lge_ldata, sizeof(struct lge_list_data));
574 /* Try to allocate memory for jumbo buffers. */
575 if (lge_alloc_jumbo_mem(sc)) {
576 printf("lge%d: jumbo buffer allocation failed\n",
578 contigfree(sc->lge_ldata, sizeof(struct lge_list_data),
580 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
581 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
582 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
587 ifp = &sc->arpcom.ac_if;
589 if_initname(ifp, "lge", unit);
590 ifp->if_mtu = ETHERMTU;
591 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
592 ifp->if_ioctl = lge_ioctl;
593 ifp->if_start = lge_start;
594 ifp->if_watchdog = lge_watchdog;
595 ifp->if_init = lge_init;
596 ifp->if_baudrate = 1000000000;
597 ifq_set_maxlen(&ifp->if_snd, LGE_TX_LIST_CNT - 1);
598 ifq_set_ready(&ifp->if_snd);
599 ifp->if_capabilities = IFCAP_RXCSUM;
600 ifp->if_capenable = ifp->if_capabilities;
602 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH)
610 if (mii_phy_probe(dev, &sc->lge_miibus,
611 lge_ifmedia_upd, lge_ifmedia_sts)) {
612 printf("lge%d: MII without any PHY!\n", sc->lge_unit);
613 contigfree(sc->lge_ldata,
614 sizeof(struct lge_list_data), M_DEVBUF);
615 lge_free_jumbo_mem(sc);
616 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
617 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
618 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
624 * Call MI attach routine.
626 ether_ifattach(ifp, eaddr);
634 lge_detach(device_t dev)
636 struct lge_softc *sc= device_get_softc(dev);
637 struct ifnet *ifp = &sc->arpcom.ac_if;
646 bus_generic_detach(dev);
647 device_delete_child(dev, sc->lge_miibus);
649 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
650 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
651 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
653 contigfree(sc->lge_ldata, sizeof(struct lge_list_data), M_DEVBUF);
654 lge_free_jumbo_mem(sc);
662 * Initialize the transmit descriptors.
665 lge_list_tx_init(struct lge_softc *sc)
667 struct lge_list_data *ld;
668 struct lge_ring_data *cd;
673 for (i = 0; i < LGE_TX_LIST_CNT; i++) {
674 ld->lge_tx_list[i].lge_mbuf = NULL;
675 ld->lge_tx_list[i].lge_ctl = 0;
678 cd->lge_tx_prod = cd->lge_tx_cons = 0;
685 * Initialize the RX descriptors and allocate mbufs for them. Note that
686 * we arralge the descriptors in a closed ring, so that the last descriptor
687 * points back to the first.
690 lge_list_rx_init(struct lge_softc *sc)
692 struct lge_list_data *ld;
693 struct lge_ring_data *cd;
699 cd->lge_rx_prod = cd->lge_rx_cons = 0;
701 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0);
703 for (i = 0; i < LGE_RX_LIST_CNT; i++) {
704 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0)
706 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS)
710 /* Clear possible 'rx command queue empty' interrupt. */
711 CSR_READ_4(sc, LGE_ISR);
717 * Initialize an RX descriptor and attach an MBUF cluster.
720 lge_newbuf(struct lge_softc *sc, struct lge_rx_desc *c, struct mbuf *m)
722 struct mbuf *m_new = NULL;
726 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
728 printf("lge%d: no memory for rx list "
729 "-- packet dropped!\n", sc->lge_unit);
733 /* Allocate the jumbo buffer */
734 buf = lge_jalloc(sc);
737 printf("lge%d: jumbo allocation failed "
738 "-- packet dropped!\n", sc->lge_unit);
743 /* Attach the buffer to the mbuf */
744 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf;
745 m_new->m_flags |= M_EXT | M_EXT_OLD;
746 m_new->m_ext.ext_size = m_new->m_pkthdr.len =
747 m_new->m_len = LGE_MCLBYTES;
748 m_new->m_ext.ext_nfree.old = lge_jfree;
749 m_new->m_ext.ext_nref.old = lge_jref;
752 m_new->m_len = m_new->m_pkthdr.len = LGE_MCLBYTES;
753 m_new->m_data = m_new->m_ext.ext_buf;
757 * Adjust alignment so packet payload begins on a
758 * longword boundary. Mandatory for Alpha, useful on
761 m_adj(m_new, ETHER_ALIGN);
764 c->lge_fragptr_hi = 0;
765 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t));
766 c->lge_fraglen = m_new->m_len;
767 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1);
771 * Put this buffer in the RX command FIFO. To do this,
772 * we just write the physical address of the descriptor
773 * into the RX descriptor address registers. Note that
774 * there are two registers, one high DWORD and one low
775 * DWORD, which lets us specify a 64-bit address if
776 * desired. We only use a 32-bit address for now.
777 * Writing to the low DWORD register is what actually
778 * causes the command to be issued, so we do that
781 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c));
782 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT);
788 lge_alloc_jumbo_mem(struct lge_softc *sc)
790 struct lge_jpool_entry *entry;
794 /* Grab a big chunk o' storage. */
795 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF,
796 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
798 if (sc->lge_cdata.lge_jumbo_buf == NULL) {
799 printf("lge%d: no memory for jumbo buffers!\n", sc->lge_unit);
803 SLIST_INIT(&sc->lge_jfree_listhead);
804 SLIST_INIT(&sc->lge_jinuse_listhead);
807 * Now divide it up into 9K pieces and save the addresses
810 ptr = sc->lge_cdata.lge_jumbo_buf;
811 for (i = 0; i < LGE_JSLOTS; i++) {
813 aptr = (uint64_t **)ptr;
814 aptr[0] = (uint64_t *)sc;
815 ptr += sizeof(uint64_t);
816 sc->lge_cdata.lge_jslots[i].lge_buf = ptr;
817 sc->lge_cdata.lge_jslots[i].lge_inuse = 0;
819 entry = malloc(sizeof(struct lge_jpool_entry),
822 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead,
823 entry, jpool_entries);
830 lge_free_jumbo_mem(struct lge_softc *sc)
832 struct lge_jpool_entry *entry;
835 for (i = 0; i < LGE_JSLOTS; i++) {
836 entry = SLIST_FIRST(&sc->lge_jfree_listhead);
837 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries);
838 free(entry, M_DEVBUF);
841 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF);
845 * Allocate a jumbo buffer.
848 lge_jalloc(struct lge_softc *sc)
850 struct lge_jpool_entry *entry;
852 entry = SLIST_FIRST(&sc->lge_jfree_listhead);
856 printf("lge%d: no free jumbo buffers\n", sc->lge_unit);
861 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries);
862 SLIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries);
863 sc->lge_cdata.lge_jslots[entry->slot].lge_inuse = 1;
865 return(sc->lge_cdata.lge_jslots[entry->slot].lge_buf);
869 * Adjust usage count on a jumbo buffer. In general this doesn't
870 * get used much because our jumbo buffers don't get passed around
871 * a lot, but it's implemented for correctness.
874 lge_jref(caddr_t buf, u_int size)
876 struct lge_softc *sc;
880 /* Extract the softc struct pointer. */
881 aptr = (uint64_t **)(buf - sizeof(uint64_t));
882 sc = (struct lge_softc *)(aptr[0]);
885 panic("lge_jref: can't find softc pointer!");
887 if (size != LGE_MCLBYTES)
888 panic("lge_jref: adjusting refcount of buf of wrong size!");
890 /* calculate the slot this buffer belongs to */
892 i = ((vm_offset_t)aptr
893 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN;
895 if ((i < 0) || (i >= LGE_JSLOTS))
896 panic("lge_jref: asked to reference buffer "
897 "that we don't manage!");
898 else if (sc->lge_cdata.lge_jslots[i].lge_inuse == 0)
899 panic("lge_jref: buffer already free!");
901 sc->lge_cdata.lge_jslots[i].lge_inuse++;
905 * Release a jumbo buffer.
908 lge_jfree(caddr_t buf, u_int size)
910 struct lge_softc *sc;
913 struct lge_jpool_entry *entry;
915 /* Extract the softc struct pointer. */
916 aptr = (uint64_t **)(buf - sizeof(uint64_t));
917 sc = (struct lge_softc *)(aptr[0]);
920 panic("lge_jfree: can't find softc pointer!");
922 if (size != LGE_MCLBYTES)
923 panic("lge_jfree: freeing buffer of wrong size!");
925 /* calculate the slot this buffer belongs to */
926 i = ((vm_offset_t)aptr
927 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN;
929 if ((i < 0) || (i >= LGE_JSLOTS))
930 panic("lge_jfree: asked to free buffer that we don't manage!");
931 else if (sc->lge_cdata.lge_jslots[i].lge_inuse == 0)
932 panic("lge_jfree: buffer already free!");
934 sc->lge_cdata.lge_jslots[i].lge_inuse--;
935 if(sc->lge_cdata.lge_jslots[i].lge_inuse == 0) {
936 entry = SLIST_FIRST(&sc->lge_jinuse_listhead);
938 panic("lge_jfree: buffer not in use!");
940 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead,
942 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead,
943 entry, jpool_entries);
949 * A frame has been uploaded: pass the resulting mbuf chain up to
950 * the higher level protocols.
953 lge_rxeof(struct lge_softc *sc, int cnt)
955 struct ifnet *ifp = &sc->arpcom.ac_if;
957 struct lge_rx_desc *cur_rx;
958 int c, i, total_len = 0;
959 uint32_t rxsts, rxctl;
962 /* Find out how many frames were processed. */
964 i = sc->lge_cdata.lge_rx_cons;
968 struct mbuf *m0 = NULL;
970 cur_rx = &sc->lge_ldata->lge_rx_list[i];
971 rxctl = cur_rx->lge_ctl;
972 rxsts = cur_rx->lge_sts;
973 m = cur_rx->lge_mbuf;
974 cur_rx->lge_mbuf = NULL;
975 total_len = LGE_RXBYTES(cur_rx);
976 LGE_INC(i, LGE_RX_LIST_CNT);
980 * If an error occurs, update stats, clear the
981 * status word and leave the mbuf cluster in place:
982 * it should simply get re-used next time this descriptor
983 * comes up in the ring.
985 if (rxctl & LGE_RXCTL_ERRMASK) {
987 lge_newbuf(sc, &LGE_RXTAIL(sc), m);
991 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) {
992 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
993 total_len + ETHER_ALIGN, 0, ifp, NULL);
994 lge_newbuf(sc, &LGE_RXTAIL(sc), m);
996 printf("lge%d: no receive buffers "
997 "available -- packet dropped!\n",
1002 m_adj(m0, ETHER_ALIGN);
1005 m->m_pkthdr.rcvif = ifp;
1006 m->m_pkthdr.len = m->m_len = total_len;
1011 /* Do IP checksum checking. */
1012 if (rxsts & LGE_RXSTS_ISIP)
1013 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1014 if (!(rxsts & LGE_RXSTS_IPCSUMERR))
1015 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1016 if ((rxsts & LGE_RXSTS_ISTCP &&
1017 !(rxsts & LGE_RXSTS_TCPCSUMERR)) ||
1018 (rxsts & LGE_RXSTS_ISUDP &&
1019 !(rxsts & LGE_RXSTS_UDPCSUMERR))) {
1020 m->m_pkthdr.csum_flags |=
1021 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1022 m->m_pkthdr.csum_data = 0xffff;
1025 (*ifp->if_input)(ifp, m);
1028 sc->lge_cdata.lge_rx_cons = i;
1032 lge_rxeoc(struct lge_softc *sc)
1034 struct ifnet *ifp = &sc->arpcom.ac_if;
1036 ifp->if_flags &= ~IFF_RUNNING;
1041 * A frame was downloaded to the chip. It's safe for us to clean up
1045 lge_txeof(struct lge_softc *sc)
1047 struct ifnet *ifp = &sc->arpcom.ac_if;
1048 struct lge_tx_desc *cur_tx = NULL;
1049 uint32_t idx, txdone;
1051 /* Clear the timeout timer. */
1055 * Go through our tx list and free mbufs for those
1056 * frames that have been transmitted.
1058 idx = sc->lge_cdata.lge_tx_cons;
1059 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT);
1061 while (idx != sc->lge_cdata.lge_tx_prod && txdone) {
1062 cur_tx = &sc->lge_ldata->lge_tx_list[idx];
1065 if (cur_tx->lge_mbuf != NULL) {
1066 m_freem(cur_tx->lge_mbuf);
1067 cur_tx->lge_mbuf = NULL;
1069 cur_tx->lge_ctl = 0;
1072 LGE_INC(idx, LGE_TX_LIST_CNT);
1076 sc->lge_cdata.lge_tx_cons = idx;
1079 ifp->if_flags &= ~IFF_OACTIVE;
1085 struct lge_softc *sc = xsc;
1086 struct mii_data *mii;
1087 struct ifnet *ifp = &sc->arpcom.ac_if;
1092 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS);
1093 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL);
1094 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS);
1095 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL);
1097 if (!sc->lge_link) {
1098 mii = device_get_softc(sc->lge_miibus);
1101 if (mii->mii_media_status & IFM_ACTIVE &&
1102 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1104 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX||
1105 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T)
1106 printf("lge%d: gigabit link up\n",
1108 if (!ifq_is_empty(&ifp->if_snd))
1109 (*ifp->if_start)(ifp);
1113 callout_reset(&sc->lge_stat_timer, hz, lge_tick, sc);
1121 struct lge_softc *sc = arg;
1122 struct ifnet *ifp = &sc->arpcom.ac_if;
1125 /* Supress unwanted interrupts */
1126 if ((ifp->if_flags & IFF_UP) == 0) {
1133 * Reading the ISR register clears all interrupts, and
1134 * clears the 'interrupts enabled' bit in the IMR
1137 status = CSR_READ_4(sc, LGE_ISR);
1139 if ((status & LGE_INTRS) == 0)
1142 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE)))
1145 if (status & LGE_ISR_RXDMA_DONE)
1146 lge_rxeof(sc, LGE_RX_DMACNT(status));
1148 if (status & LGE_ISR_RXCMDFIFO_EMPTY)
1151 if (status & LGE_ISR_PHY_INTR) {
1153 callout_stop(&sc->lge_stat_timer);
1158 /* Re-enable interrupts. */
1159 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB);
1161 if (!ifq_is_empty(&ifp->if_snd))
1162 (*ifp->if_start)(ifp);
1166 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1167 * pointers to the fragment pointers.
1170 lge_encap(struct lge_softc *sc, struct mbuf *m_head, uint32_t *txidx)
1172 struct lge_frag *f = NULL;
1173 struct lge_tx_desc *cur_tx;
1175 int frag = 0, tot_len = 0;
1178 * Start packing the mbufs in this chain into
1179 * the fragment pointers. Stop when we run out
1180 * of fragments or hit the end of the mbuf chain.
1183 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx];
1186 for (m = m_head; m != NULL; m = m->m_next) {
1187 if (m->m_len != 0) {
1188 tot_len += m->m_len;
1189 f = &cur_tx->lge_frags[frag];
1190 f->lge_fraglen = m->m_len;
1191 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t));
1192 f->lge_fragptr_hi = 0;
1200 cur_tx->lge_mbuf = m_head;
1201 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len;
1202 LGE_INC((*txidx), LGE_TX_LIST_CNT);
1204 /* Queue for transmit */
1205 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx));
1211 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1212 * to the mbuf data regions directly in the transmit lists. We also save a
1213 * copy of the pointers since the transmit list fragment pointers are
1214 * physical addresses.
1218 lge_start(struct ifnet *ifp)
1220 struct lge_softc *sc = ifp->if_softc;
1221 struct mbuf *m_head = NULL;
1227 idx = sc->lge_cdata.lge_tx_prod;
1229 if (ifp->if_flags & IFF_OACTIVE)
1232 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) {
1233 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0)
1236 m_head = ifq_poll(&ifp->if_snd);
1240 if (lge_encap(sc, m_head, &idx)) {
1241 ifp->if_flags |= IFF_OACTIVE;
1244 m_head = ifq_dequeue(&ifp->if_snd);
1246 BPF_MTAP(ifp, m_head);
1249 sc->lge_cdata.lge_tx_prod = idx;
1252 * Set a timeout in case the chip goes out to lunch.
1260 struct lge_softc *sc = xsc;
1261 struct ifnet *ifp = &sc->arpcom.ac_if;
1262 struct mii_data *mii;
1265 if (ifp->if_flags & IFF_RUNNING)
1271 * Cancel pending I/O and free all RX/TX buffers.
1276 mii = device_get_softc(sc->lge_miibus);
1278 /* Set MAC address */
1279 CSR_WRITE_4(sc, LGE_PAR0, *(uint32_t *)(&sc->arpcom.ac_enaddr[0]));
1280 CSR_WRITE_4(sc, LGE_PAR1, *(uint32_t *)(&sc->arpcom.ac_enaddr[4]));
1282 /* Init circular RX list. */
1283 if (lge_list_rx_init(sc) == ENOBUFS) {
1284 printf("lge%d: initialization failed: no "
1285 "memory for rx buffers\n", sc->lge_unit);
1292 * Init tx descriptors.
1294 lge_list_tx_init(sc);
1296 /* Set initial value for MODE1 register. */
1297 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST |
1298 LGE_MODE1_TX_CRC | LGE_MODE1_TXPAD |
1299 LGE_MODE1_RX_FLOWCTL | LGE_MODE1_SETRST_CTL0 |
1300 LGE_MODE1_SETRST_CTL1 | LGE_MODE1_SETRST_CTL2);
1302 /* If we want promiscuous mode, set the allframes bit. */
1303 if (ifp->if_flags & IFF_PROMISC) {
1304 CSR_WRITE_4(sc, LGE_MODE1,
1305 LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_PROMISC);
1307 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC);
1311 * Set the capture broadcast bit to capture broadcast frames.
1313 if (ifp->if_flags & IFF_BROADCAST) {
1314 CSR_WRITE_4(sc, LGE_MODE1,
1315 LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_BCAST);
1317 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST);
1320 /* Packet padding workaround? */
1321 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD);
1323 /* No error frames */
1324 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS);
1326 /* Receive large frames */
1327 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_GIANTS);
1329 /* Workaround: disable RX/TX flow control */
1330 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL);
1331 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL);
1333 /* Make sure to strip CRC from received frames */
1334 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC);
1336 /* Turn off magic packet mode */
1337 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB);
1339 /* Turn off all VLAN stuff */
1340 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX | LGE_MODE1_VLAN_TX |
1341 LGE_MODE1_VLAN_STRIP | LGE_MODE1_VLAN_INSERT);
1343 /* Workarond: FIFO overflow */
1344 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF);
1345 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT);
1348 * Load the multicast filter.
1353 * Enable hardware checksum validation for all received IPv4
1354 * packets, do not reject packets with bad checksums.
1356 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM |
1357 LGE_MODE2_RX_TCPCSUM | LGE_MODE2_RX_UDPCSUM |
1358 LGE_MODE2_RX_ERRCSUM);
1361 * Enable the delivery of PHY interrupts based on
1362 * link/speed/duplex status chalges.
1364 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0 | LGE_MODE1_GMIIPOLL);
1366 /* Enable receiver and transmitter. */
1367 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0);
1368 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_ENB);
1370 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0);
1371 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1 | LGE_MODE1_TX_ENB);
1374 * Enable interrupts.
1376 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0 |
1377 LGE_IMR_SETRST_CTL1 | LGE_IMR_INTR_ENB|LGE_INTRS);
1379 lge_ifmedia_upd(ifp);
1381 ifp->if_flags |= IFF_RUNNING;
1382 ifp->if_flags &= ~IFF_OACTIVE;
1386 callout_reset(&sc->lge_stat_timer, hz, lge_tick, sc);
1390 * Set media options.
1393 lge_ifmedia_upd(struct ifnet *ifp)
1395 struct lge_softc *sc = ifp->if_softc;
1396 struct mii_data *mii = device_get_softc(sc->lge_miibus);
1399 if (mii->mii_instance) {
1400 struct mii_softc *miisc;
1401 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1402 mii_phy_reset(miisc);
1410 * Report current media status.
1413 lge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1415 struct lge_softc *sc = ifp->if_softc;;
1416 struct mii_data *mii;
1418 mii = device_get_softc(sc->lge_miibus);
1420 ifmr->ifm_active = mii->mii_media_active;
1421 ifmr->ifm_status = mii->mii_media_status;
1425 lge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1427 struct lge_softc *sc = ifp->if_softc;
1428 struct ifreq *ifr = (struct ifreq *) data;
1429 struct mii_data *mii;
1437 error = ether_ioctl(ifp, command, data);
1440 if (ifr->ifr_mtu > LGE_JUMBO_MTU)
1443 ifp->if_mtu = ifr->ifr_mtu;
1446 if (ifp->if_flags & IFF_UP) {
1447 if (ifp->if_flags & IFF_RUNNING &&
1448 ifp->if_flags & IFF_PROMISC &&
1449 !(sc->lge_if_flags & IFF_PROMISC)) {
1450 CSR_WRITE_4(sc, LGE_MODE1,
1451 LGE_MODE1_SETRST_CTL1|
1452 LGE_MODE1_RX_PROMISC);
1453 } else if (ifp->if_flags & IFF_RUNNING &&
1454 !(ifp->if_flags & IFF_PROMISC) &&
1455 sc->lge_if_flags & IFF_PROMISC) {
1456 CSR_WRITE_4(sc, LGE_MODE1,
1457 LGE_MODE1_RX_PROMISC);
1459 ifp->if_flags &= ~IFF_RUNNING;
1463 if (ifp->if_flags & IFF_RUNNING)
1466 sc->lge_if_flags = ifp->if_flags;
1476 mii = device_get_softc(sc->lge_miibus);
1477 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1490 lge_watchdog(struct ifnet *ifp)
1492 struct lge_softc *sc = ifp->if_softc;
1495 printf("lge%d: watchdog timeout\n", sc->lge_unit);
1499 ifp->if_flags &= ~IFF_RUNNING;
1502 if (!ifq_is_empty(&ifp->if_snd))
1503 (*ifp->if_start)(ifp);
1507 * Stop the adapter and free any mbufs allocated to the
1511 lge_stop(struct lge_softc *sc)
1513 struct ifnet *ifp = &sc->arpcom.ac_if;
1517 callout_stop(&sc->lge_stat_timer);
1518 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB);
1520 /* Disable receiver and transmitter. */
1521 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB);
1525 * Free data in the RX lists.
1527 for (i = 0; i < LGE_RX_LIST_CNT; i++) {
1528 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) {
1529 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf);
1530 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL;
1533 bzero(&sc->lge_ldata->lge_rx_list, sizeof(sc->lge_ldata->lge_rx_list));
1536 * Free the TX list buffers.
1538 for (i = 0; i < LGE_TX_LIST_CNT; i++) {
1539 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) {
1540 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf);
1541 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL;
1545 bzero(&sc->lge_ldata->lge_tx_list, sizeof(sc->lge_ldata->lge_tx_list));
1547 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1551 * Stop all chip I/O so that the kernel's probe routines don't
1552 * get confused by errant DMAs when rebooting.
1555 lge_shutdown(device_t dev)
1557 struct lge_softc *sc = device_get_softc(dev);