1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997,
3 1998, 1999, 2000 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
27 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "insn-flags.h"
32 #include "insn-codes.h"
36 #include "basic-block.h"
43 #if !defined PREFERRED_STACK_BOUNDARY && defined STACK_BOUNDARY
44 #define PREFERRED_STACK_BOUNDARY STACK_BOUNDARY
47 /* This file contains the reload pass of the compiler, which is
48 run after register allocation has been done. It checks that
49 each insn is valid (operands required to be in registers really
50 are in registers of the proper class) and fixes up invalid ones
51 by copying values temporarily into registers for the insns
54 The results of register allocation are described by the vector
55 reg_renumber; the insns still contain pseudo regs, but reg_renumber
56 can be used to find which hard reg, if any, a pseudo reg is in.
58 The technique we always use is to free up a few hard regs that are
59 called ``reload regs'', and for each place where a pseudo reg
60 must be in a hard reg, copy it temporarily into one of the reload regs.
62 Reload regs are allocated locally for every instruction that needs
63 reloads. When there are pseudos which are allocated to a register that
64 has been chosen as a reload reg, such pseudos must be ``spilled''.
65 This means that they go to other hard regs, or to stack slots if no other
66 available hard regs can be found. Spilling can invalidate more
67 insns, requiring additional need for reloads, so we must keep checking
68 until the process stabilizes.
70 For machines with different classes of registers, we must keep track
71 of the register class needed for each reload, and make sure that
72 we allocate enough reload registers of each class.
74 The file reload.c contains the code that checks one insn for
75 validity and reports the reloads that it needs. This file
76 is in charge of scanning the entire rtl code, accumulating the
77 reload needs, spilling, assigning reload registers to use for
78 fixing up each insn, and generating the new insns to copy values
79 into the reload registers. */
82 #ifndef REGISTER_MOVE_COST
83 #define REGISTER_MOVE_COST(x, y) 2
86 /* During reload_as_needed, element N contains a REG rtx for the hard reg
87 into which reg N has been reloaded (perhaps for a previous insn). */
88 static rtx *reg_last_reload_reg;
90 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
91 for an output reload that stores into reg N. */
92 static char *reg_has_output_reload;
94 /* Indicates which hard regs are reload-registers for an output reload
95 in the current insn. */
96 static HARD_REG_SET reg_is_output_reload;
98 /* Element N is the constant value to which pseudo reg N is equivalent,
99 or zero if pseudo reg N is not equivalent to a constant.
100 find_reloads looks at this in order to replace pseudo reg N
101 with the constant it stands for. */
102 rtx *reg_equiv_constant;
104 /* Element N is a memory location to which pseudo reg N is equivalent,
105 prior to any register elimination (such as frame pointer to stack
106 pointer). Depending on whether or not it is a valid address, this value
107 is transferred to either reg_equiv_address or reg_equiv_mem. */
108 rtx *reg_equiv_memory_loc;
110 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
111 This is used when the address is not valid as a memory address
112 (because its displacement is too big for the machine.) */
113 rtx *reg_equiv_address;
115 /* Element N is the memory slot to which pseudo reg N is equivalent,
116 or zero if pseudo reg N is not equivalent to a memory slot. */
119 /* Widest width in which each pseudo reg is referred to (via subreg). */
120 static int *reg_max_ref_width;
122 /* Element N is the list of insns that initialized reg N from its equivalent
123 constant or memory slot. */
124 static rtx *reg_equiv_init;
126 /* Vector to remember old contents of reg_renumber before spilling. */
127 static short *reg_old_renumber;
129 /* During reload_as_needed, element N contains the last pseudo regno reloaded
130 into hard register N. If that pseudo reg occupied more than one register,
131 reg_reloaded_contents points to that pseudo for each spill register in
132 use; all of these must remain set for an inheritance to occur. */
133 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
135 /* During reload_as_needed, element N contains the insn for which
136 hard register N was last used. Its contents are significant only
137 when reg_reloaded_valid is set for this register. */
138 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
140 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
141 static HARD_REG_SET reg_reloaded_valid;
142 /* Indicate if the register was dead at the end of the reload.
143 This is only valid if reg_reloaded_contents is set and valid. */
144 static HARD_REG_SET reg_reloaded_dead;
146 /* Number of spill-regs so far; number of valid elements of spill_regs. */
149 /* In parallel with spill_regs, contains REG rtx's for those regs.
150 Holds the last rtx used for any given reg, or 0 if it has never
151 been used for spilling yet. This rtx is reused, provided it has
153 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
155 /* In parallel with spill_regs, contains nonzero for a spill reg
156 that was stored after the last time it was used.
157 The precise value is the insn generated to do the store. */
158 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
160 /* This is the register that was stored with spill_reg_store. This is a
161 copy of reload_out / reload_out_reg when the value was stored; if
162 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
163 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
165 /* This table is the inverse mapping of spill_regs:
166 indexed by hard reg number,
167 it contains the position of that reg in spill_regs,
168 or -1 for something that is not in spill_regs.
170 ?!? This is no longer accurate. */
171 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
173 /* This reg set indicates registers that can't be used as spill registers for
174 the currently processed insn. These are the hard registers which are live
175 during the insn, but not allocated to pseudos, as well as fixed
177 static HARD_REG_SET bad_spill_regs;
179 /* These are the hard registers that can't be used as spill register for any
180 insn. This includes registers used for user variables and registers that
181 we can't eliminate. A register that appears in this set also can't be used
182 to retry register allocation. */
183 static HARD_REG_SET bad_spill_regs_global;
185 /* Describes order of use of registers for reloading
186 of spilled pseudo-registers. `n_spills' is the number of
187 elements that are actually valid; new ones are added at the end.
189 Both spill_regs and spill_reg_order are used on two occasions:
190 once during find_reload_regs, where they keep track of the spill registers
191 for a single insn, but also during reload_as_needed where they show all
192 the registers ever used by reload. For the latter case, the information
193 is calculated during finish_spills. */
194 static short spill_regs[FIRST_PSEUDO_REGISTER];
196 /* This vector of reg sets indicates, for each pseudo, which hard registers
197 may not be used for retrying global allocation because the register was
198 formerly spilled from one of them. If we allowed reallocating a pseudo to
199 a register that it was already allocated to, reload might not
201 static HARD_REG_SET *pseudo_previous_regs;
203 /* This vector of reg sets indicates, for each pseudo, which hard
204 registers may not be used for retrying global allocation because they
205 are used as spill registers during one of the insns in which the
207 static HARD_REG_SET *pseudo_forbidden_regs;
209 /* All hard regs that have been used as spill registers for any insn are
210 marked in this set. */
211 static HARD_REG_SET used_spill_regs;
213 /* Index of last register assigned as a spill register. We allocate in
214 a round-robin fashion. */
215 static int last_spill_reg;
217 /* Describes order of preference for putting regs into spill_regs.
218 Contains the numbers of all the hard regs, in order most preferred first.
219 This order is different for each function.
220 It is set up by order_regs_for_reload.
221 Empty elements at the end contain -1. */
222 static short potential_reload_regs[FIRST_PSEUDO_REGISTER];
224 /* Nonzero if indirect addressing is supported on the machine; this means
225 that spilling (REG n) does not require reloading it into a register in
226 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
227 value indicates the level of indirect addressing supported, e.g., two
228 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
230 static char spill_indirect_levels;
232 /* Nonzero if indirect addressing is supported when the innermost MEM is
233 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
234 which these are valid is the same as spill_indirect_levels, above. */
235 char indirect_symref_ok;
237 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
238 char double_reg_address_ok;
240 /* Record the stack slot for each spilled hard register. */
241 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
243 /* Width allocated so far for that stack slot. */
244 static int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
246 /* Record which pseudos needed to be spilled. */
247 static regset spilled_pseudos;
249 /* First uid used by insns created by reload in this function.
250 Used in find_equiv_reg. */
251 int reload_first_uid;
253 /* Flag set by local-alloc or global-alloc if anything is live in
254 a call-clobbered reg across calls. */
255 int caller_save_needed;
257 /* Set to 1 while reload_as_needed is operating.
258 Required by some machines to handle any generated moves differently. */
259 int reload_in_progress = 0;
261 /* These arrays record the insn_code of insns that may be needed to
262 perform input and output reloads of special objects. They provide a
263 place to pass a scratch register. */
264 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
265 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
267 /* This obstack is used for allocation of rtl during register elimination.
268 The allocated storage can be freed once find_reloads has processed the
270 struct obstack reload_obstack;
272 /* Points to the beginning of the reload_obstack. All insn_chain structures
273 are allocated first. */
274 char *reload_startobj;
276 /* The point after all insn_chain structures. Used to quickly deallocate
277 memory used while processing one insn. */
278 char *reload_firstobj;
280 #define obstack_chunk_alloc xmalloc
281 #define obstack_chunk_free free
283 /* List of labels that must never be deleted. */
284 extern rtx forced_labels;
286 /* List of insn_chain instructions, one for every insn that reload needs to
288 struct insn_chain *reload_insn_chain;
291 extern tree current_function_decl;
293 extern union tree_node *current_function_decl;
296 /* List of all insns needing reloads. */
297 static struct insn_chain *insns_need_reload;
299 /* This structure is used to record information about register eliminations.
300 Each array entry describes one possible way of eliminating a register
301 in favor of another. If there is more than one way of eliminating a
302 particular register, the most preferred should be specified first. */
306 int from; /* Register number to be eliminated. */
307 int to; /* Register number used as replacement. */
308 int initial_offset; /* Initial difference between values. */
309 int can_eliminate; /* Non-zero if this elimination can be done. */
310 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
311 insns made by reload. */
312 int offset; /* Current offset between the two regs. */
313 int previous_offset; /* Offset at end of previous insn. */
314 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
315 rtx from_rtx; /* REG rtx for the register to be eliminated.
316 We cannot simply compare the number since
317 we might then spuriously replace a hard
318 register corresponding to a pseudo
319 assigned to the reg to be eliminated. */
320 rtx to_rtx; /* REG rtx for the replacement. */
323 static struct elim_table * reg_eliminate = 0;
325 /* This is an intermediate structure to initialize the table. It has
326 exactly the members provided by ELIMINABLE_REGS. */
327 static struct elim_table_1
331 } reg_eliminate_1[] =
333 /* If a set of eliminable registers was specified, define the table from it.
334 Otherwise, default to the normal case of the frame pointer being
335 replaced by the stack pointer. */
337 #ifdef ELIMINABLE_REGS
340 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
343 #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate_1/sizeof reg_eliminate_1[0])
345 /* Record the number of pending eliminations that have an offset not equal
346 to their initial offset. If non-zero, we use a new copy of each
347 replacement result in any insns encountered. */
348 int num_not_at_initial_offset;
350 /* Count the number of registers that we may be able to eliminate. */
351 static int num_eliminable;
352 /* And the number of registers that are equivalent to a constant that
353 can be eliminated to frame_pointer / arg_pointer + constant. */
354 static int num_eliminable_invariants;
356 /* For each label, we record the offset of each elimination. If we reach
357 a label by more than one path and an offset differs, we cannot do the
358 elimination. This information is indexed by the number of the label.
359 The first table is an array of flags that records whether we have yet
360 encountered a label and the second table is an array of arrays, one
361 entry in the latter array for each elimination. */
363 static char *offsets_known_at;
364 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
366 /* Number of labels in the current function. */
368 static int num_labels;
370 struct hard_reg_n_uses
376 static void maybe_fix_stack_asms PROTO((void));
377 static void calculate_needs_all_insns PROTO((int));
378 static void calculate_needs PROTO((struct insn_chain *));
379 static void find_reload_regs PROTO((struct insn_chain *chain,
381 static void find_tworeg_group PROTO((struct insn_chain *, int,
383 static void find_group PROTO((struct insn_chain *, int,
385 static int possible_group_p PROTO((struct insn_chain *, int));
386 static void count_possible_groups PROTO((struct insn_chain *, int));
387 static int modes_equiv_for_class_p PROTO((enum machine_mode,
390 static void delete_caller_save_insns PROTO((void));
392 static void spill_failure PROTO((rtx));
393 static void new_spill_reg PROTO((struct insn_chain *, int, int,
395 static void maybe_mark_pseudo_spilled PROTO((int));
396 static void delete_dead_insn PROTO((rtx));
397 static void alter_reg PROTO((int, int));
398 static void set_label_offsets PROTO((rtx, rtx, int));
399 static int eliminate_regs_in_insn PROTO((rtx, int));
400 static void update_eliminable_offsets PROTO((void));
401 static void mark_not_eliminable PROTO((rtx, rtx));
402 static void set_initial_elim_offsets PROTO((void));
403 static void verify_initial_elim_offsets PROTO((void));
404 static void set_initial_label_offsets PROTO((void));
405 static void set_offsets_for_label PROTO((rtx));
406 static void init_elim_table PROTO((void));
407 static void update_eliminables PROTO((HARD_REG_SET *));
408 static void spill_hard_reg PROTO((int, FILE *, int));
409 static int finish_spills PROTO((int, FILE *));
410 static void ior_hard_reg_set PROTO((HARD_REG_SET *, HARD_REG_SET *));
411 static void scan_paradoxical_subregs PROTO((rtx));
412 static int hard_reg_use_compare PROTO((const GENERIC_PTR, const GENERIC_PTR));
413 static void count_pseudo PROTO((struct hard_reg_n_uses *, int));
414 static void order_regs_for_reload PROTO((struct insn_chain *));
415 static void reload_as_needed PROTO((int));
416 static void forget_old_reloads_1 PROTO((rtx, rtx));
417 static int reload_reg_class_lower PROTO((const GENERIC_PTR, const GENERIC_PTR));
418 static void mark_reload_reg_in_use PROTO((int, int, enum reload_type,
420 static void clear_reload_reg_in_use PROTO((int, int, enum reload_type,
422 static int reload_reg_free_p PROTO((int, int, enum reload_type));
423 static int reload_reg_free_for_value_p PROTO((int, int, enum reload_type, rtx, rtx, int, int));
424 static int free_for_value_p PROTO((int, enum machine_mode, int,
425 enum reload_type, rtx, rtx,
427 static int reload_reg_reaches_end_p PROTO((int, int, enum reload_type));
428 static int allocate_reload_reg PROTO((struct insn_chain *, int, int,
430 static int conflicts_with_override PROTO((rtx));
431 static void choose_reload_regs PROTO((struct insn_chain *));
432 static void merge_assigned_reloads PROTO((rtx));
433 static void emit_reload_insns PROTO((struct insn_chain *));
434 static void delete_output_reload PROTO((rtx, int, int));
435 static void delete_address_reloads PROTO((rtx, rtx));
436 static void delete_address_reloads_1 PROTO((rtx, rtx, rtx));
437 static rtx inc_for_reload PROTO((rtx, rtx, rtx, int));
438 static int constraint_accepts_reg_p PROTO((const char *, rtx));
439 static void reload_cse_regs_1 PROTO((rtx));
440 static void reload_cse_invalidate_regno PROTO((int, enum machine_mode, int));
441 static int reload_cse_mem_conflict_p PROTO((rtx, rtx));
442 static void reload_cse_invalidate_mem PROTO((rtx));
443 static void reload_cse_invalidate_rtx PROTO((rtx, rtx));
444 static int reload_cse_regno_equal_p PROTO((int, rtx, enum machine_mode));
445 static int reload_cse_noop_set_p PROTO((rtx, rtx));
446 static int reload_cse_simplify_set PROTO((rtx, rtx));
447 static int reload_cse_simplify_operands PROTO((rtx));
448 static void reload_cse_check_clobber PROTO((rtx, rtx));
449 static void reload_cse_record_set PROTO((rtx, rtx));
450 static void reload_combine PROTO((void));
451 static void reload_combine_note_use PROTO((rtx *, rtx));
452 static void reload_combine_note_store PROTO((rtx, rtx));
453 static void reload_cse_move2add PROTO((rtx));
454 static void move2add_note_store PROTO((rtx, rtx));
456 static void add_auto_inc_notes PROTO((rtx, rtx));
459 /* Initialize the reload pass once per compilation. */
466 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
467 Set spill_indirect_levels to the number of levels such addressing is
468 permitted, zero if it is not permitted at all. */
471 = gen_rtx_MEM (Pmode,
473 gen_rtx_REG (Pmode, LAST_VIRTUAL_REGISTER + 1),
475 spill_indirect_levels = 0;
477 while (memory_address_p (QImode, tem))
479 spill_indirect_levels++;
480 tem = gen_rtx_MEM (Pmode, tem);
483 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
485 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
486 indirect_symref_ok = memory_address_p (QImode, tem);
488 /* See if reg+reg is a valid (and offsettable) address. */
490 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
492 tem = gen_rtx_PLUS (Pmode,
493 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
494 gen_rtx_REG (Pmode, i));
495 /* This way, we make sure that reg+reg is an offsettable address. */
496 tem = plus_constant (tem, 4);
498 if (memory_address_p (QImode, tem))
500 double_reg_address_ok = 1;
505 /* Initialize obstack for our rtl allocation. */
506 gcc_obstack_init (&reload_obstack);
507 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
510 /* List of insn chains that are currently unused. */
511 static struct insn_chain *unused_insn_chains = 0;
513 /* Allocate an empty insn_chain structure. */
517 struct insn_chain *c;
519 if (unused_insn_chains == 0)
521 c = (struct insn_chain *)
522 obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
523 c->live_before = OBSTACK_ALLOC_REG_SET (&reload_obstack);
524 c->live_after = OBSTACK_ALLOC_REG_SET (&reload_obstack);
528 c = unused_insn_chains;
529 unused_insn_chains = c->next;
531 c->is_caller_save_insn = 0;
532 c->need_operand_change = 0;
538 /* Small utility function to set all regs in hard reg set TO which are
539 allocated to pseudos in regset FROM. */
541 compute_use_by_pseudos (to, from)
546 EXECUTE_IF_SET_IN_REG_SET
547 (from, FIRST_PSEUDO_REGISTER, regno,
549 int r = reg_renumber[regno];
553 /* reload_combine uses the information from
554 BASIC_BLOCK->global_live_at_start, which might still
555 contain registers that have not actually been allocated
556 since they have an equivalence. */
557 if (! reload_completed)
562 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
564 SET_HARD_REG_BIT (*to, r + nregs);
569 /* Global variables used by reload and its subroutines. */
571 /* Set during calculate_needs if an insn needs register elimination. */
572 static int something_needs_elimination;
573 /* Set during calculate_needs if an insn needs an operand changed. */
574 int something_needs_operands_changed;
576 /* Nonzero means we couldn't get enough spill regs. */
579 /* Main entry point for the reload pass.
581 FIRST is the first insn of the function being compiled.
583 GLOBAL nonzero means we were called from global_alloc
584 and should attempt to reallocate any pseudoregs that we
585 displace from hard regs we will use for reloads.
586 If GLOBAL is zero, we do not have enough information to do that,
587 so any pseudo reg that is spilled must go to the stack.
589 DUMPFILE is the global-reg debugging dump file stream, or 0.
590 If it is nonzero, messages are written to it to describe
591 which registers are seized as reload regs, which pseudo regs
592 are spilled from them, and where the pseudo regs are reallocated to.
594 Return value is nonzero if reload failed
595 and we must not do any more for this function. */
598 reload (first, global, dumpfile)
605 register struct elim_table *ep;
607 /* The two pointers used to track the true location of the memory used
608 for label offsets. */
609 char *real_known_ptr = NULL_PTR;
610 int (*real_at_ptr)[NUM_ELIMINABLE_REGS];
612 /* Make sure even insns with volatile mem refs are recognizable. */
617 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
619 /* Make sure that the last insn in the chain
620 is not something that needs reloading. */
621 emit_note (NULL_PTR, NOTE_INSN_DELETED);
623 /* Enable find_equiv_reg to distinguish insns made by reload. */
624 reload_first_uid = get_max_uid ();
626 #ifdef SECONDARY_MEMORY_NEEDED
627 /* Initialize the secondary memory table. */
628 clear_secondary_mem ();
631 /* We don't have a stack slot for any spill reg yet. */
632 bzero ((char *) spill_stack_slot, sizeof spill_stack_slot);
633 bzero ((char *) spill_stack_slot_width, sizeof spill_stack_slot_width);
635 /* Initialize the save area information for caller-save, in case some
639 /* Compute which hard registers are now in use
640 as homes for pseudo registers.
641 This is done here rather than (eg) in global_alloc
642 because this point is reached even if not optimizing. */
643 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
646 /* A function that receives a nonlocal goto must save all call-saved
648 if (current_function_has_nonlocal_label)
649 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
651 if (! call_used_regs[i] && ! fixed_regs[i])
652 regs_ever_live[i] = 1;
655 /* Find all the pseudo registers that didn't get hard regs
656 but do have known equivalent constants or memory slots.
657 These include parameters (known equivalent to parameter slots)
658 and cse'd or loop-moved constant memory addresses.
660 Record constant equivalents in reg_equiv_constant
661 so they will be substituted by find_reloads.
662 Record memory equivalents in reg_mem_equiv so they can
663 be substituted eventually by altering the REG-rtx's. */
665 reg_equiv_constant = (rtx *) xmalloc (max_regno * sizeof (rtx));
666 bzero ((char *) reg_equiv_constant, max_regno * sizeof (rtx));
667 reg_equiv_memory_loc = (rtx *) xmalloc (max_regno * sizeof (rtx));
668 bzero ((char *) reg_equiv_memory_loc, max_regno * sizeof (rtx));
669 reg_equiv_mem = (rtx *) xmalloc (max_regno * sizeof (rtx));
670 bzero ((char *) reg_equiv_mem, max_regno * sizeof (rtx));
671 reg_equiv_init = (rtx *) xmalloc (max_regno * sizeof (rtx));
672 bzero ((char *) reg_equiv_init, max_regno * sizeof (rtx));
673 reg_equiv_address = (rtx *) xmalloc (max_regno * sizeof (rtx));
674 bzero ((char *) reg_equiv_address, max_regno * sizeof (rtx));
675 reg_max_ref_width = (int *) xmalloc (max_regno * sizeof (int));
676 bzero ((char *) reg_max_ref_width, max_regno * sizeof (int));
677 reg_old_renumber = (short *) xmalloc (max_regno * sizeof (short));
678 bcopy ((PTR) reg_renumber, (PTR) reg_old_renumber, max_regno * sizeof (short));
679 pseudo_forbidden_regs
680 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
682 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
684 CLEAR_HARD_REG_SET (bad_spill_regs_global);
685 bzero ((char *) pseudo_previous_regs, max_regno * sizeof (HARD_REG_SET));
687 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
688 Also find all paradoxical subregs and find largest such for each pseudo.
689 On machines with small register classes, record hard registers that
690 are used for user variables. These can never be used for spills.
691 Also look for a "constant" NOTE_INSN_SETJMP. This means that all
692 caller-saved registers must be marked live. */
694 num_eliminable_invariants = 0;
695 for (insn = first; insn; insn = NEXT_INSN (insn))
697 rtx set = single_set (insn);
699 if (GET_CODE (insn) == NOTE && CONST_CALL_P (insn)
700 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
701 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
702 if (! call_used_regs[i])
703 regs_ever_live[i] = 1;
705 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
707 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
709 #ifdef LEGITIMATE_PIC_OPERAND_P
710 && (! function_invariant_p (XEXP (note, 0))
712 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
716 rtx x = XEXP (note, 0);
717 i = REGNO (SET_DEST (set));
718 if (i > LAST_VIRTUAL_REGISTER)
720 if (GET_CODE (x) == MEM)
722 /* If the operand is a PLUS, the MEM may be shared,
723 so make sure we have an unshared copy here. */
724 if (GET_CODE (XEXP (x, 0)) == PLUS)
727 reg_equiv_memory_loc[i] = x;
729 else if (function_invariant_p (x))
731 if (GET_CODE (x) == PLUS)
733 /* This is PLUS of frame pointer and a constant,
734 and might be shared. Unshare it. */
735 reg_equiv_constant[i] = copy_rtx (x);
736 num_eliminable_invariants++;
738 else if (x == frame_pointer_rtx
739 || x == arg_pointer_rtx)
741 reg_equiv_constant[i] = x;
742 num_eliminable_invariants++;
744 else if (LEGITIMATE_CONSTANT_P (x))
745 reg_equiv_constant[i] = x;
747 reg_equiv_memory_loc[i]
748 = force_const_mem (GET_MODE (SET_DEST (set)), x);
753 /* If this register is being made equivalent to a MEM
754 and the MEM is not SET_SRC, the equivalencing insn
755 is one with the MEM as a SET_DEST and it occurs later.
756 So don't mark this insn now. */
757 if (GET_CODE (x) != MEM
758 || rtx_equal_p (SET_SRC (set), x))
760 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
765 /* If this insn is setting a MEM from a register equivalent to it,
766 this is the equivalencing insn. */
767 else if (set && GET_CODE (SET_DEST (set)) == MEM
768 && GET_CODE (SET_SRC (set)) == REG
769 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
770 && rtx_equal_p (SET_DEST (set),
771 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
772 reg_equiv_init[REGNO (SET_SRC (set))]
773 = gen_rtx_INSN_LIST (VOIDmode, insn,
774 reg_equiv_init[REGNO (SET_SRC (set))]);
776 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
777 scan_paradoxical_subregs (PATTERN (insn));
782 num_labels = max_label_num () - get_first_label_num ();
784 /* Allocate the tables used to store offset information at labels. */
785 /* We used to use alloca here, but the size of what it would try to
786 allocate would occasionally cause it to exceed the stack limit and
787 cause a core dump. */
788 real_known_ptr = xmalloc (num_labels);
790 = (int (*)[NUM_ELIMINABLE_REGS])
791 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
793 offsets_known_at = real_known_ptr - get_first_label_num ();
795 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ());
797 /* Alter each pseudo-reg rtx to contain its hard reg number.
798 Assign stack slots to the pseudos that lack hard regs or equivalents.
799 Do not touch virtual registers. */
801 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
804 /* If we have some registers we think can be eliminated, scan all insns to
805 see if there is an insn that sets one of these registers to something
806 other than itself plus a constant. If so, the register cannot be
807 eliminated. Doing this scan here eliminates an extra pass through the
808 main reload loop in the most common case where register elimination
810 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
811 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
812 || GET_CODE (insn) == CALL_INSN)
813 note_stores (PATTERN (insn), mark_not_eliminable);
815 #ifndef REGISTER_CONSTRAINTS
816 /* If all the pseudo regs have hard regs,
817 except for those that are never referenced,
818 we know that no reloads are needed. */
819 /* But that is not true if there are register constraints, since
820 in that case some pseudos might be in the wrong kind of hard reg. */
822 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
823 if (reg_renumber[i] == -1 && REG_N_REFS (i) != 0)
826 if (i == max_regno && num_eliminable == 0 && ! caller_save_needed)
828 free (real_known_ptr);
830 free (reg_equiv_constant);
831 free (reg_equiv_memory_loc);
832 free (reg_equiv_mem);
833 free (reg_equiv_init);
834 free (reg_equiv_address);
835 free (reg_max_ref_width);
836 free (reg_old_renumber);
837 free (pseudo_previous_regs);
838 free (pseudo_forbidden_regs);
843 maybe_fix_stack_asms ();
845 insns_need_reload = 0;
846 something_needs_elimination = 0;
848 /* Initialize to -1, which means take the first spill register. */
851 spilled_pseudos = ALLOCA_REG_SET ();
853 /* Spill any hard regs that we know we can't eliminate. */
854 CLEAR_HARD_REG_SET (used_spill_regs);
855 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
856 if (! ep->can_eliminate)
857 spill_hard_reg (ep->from, dumpfile, 1);
859 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
860 if (frame_pointer_needed)
861 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, dumpfile, 1);
863 finish_spills (global, dumpfile);
865 /* From now on, we may need to generate moves differently. We may also
866 allow modifications of insns which cause them to not be recognized.
867 Any such modifications will be cleaned up during reload itself. */
868 reload_in_progress = 1;
870 /* This loop scans the entire function each go-round
871 and repeats until one repetition spills no additional hard regs. */
874 int something_changed;
876 struct insn_chain *chain;
878 HOST_WIDE_INT starting_frame_size;
880 /* Round size of stack frame to BIGGEST_ALIGNMENT. This must be done
881 here because the stack size may be a part of the offset computation
882 for register elimination, and there might have been new stack slots
883 created in the last iteration of this loop. */
884 assign_stack_local (BLKmode, 0, 0);
886 starting_frame_size = get_frame_size ();
888 set_initial_elim_offsets ();
889 set_initial_label_offsets ();
891 /* For each pseudo register that has an equivalent location defined,
892 try to eliminate any eliminable registers (such as the frame pointer)
893 assuming initial offsets for the replacement register, which
896 If the resulting location is directly addressable, substitute
897 the MEM we just got directly for the old REG.
899 If it is not addressable but is a constant or the sum of a hard reg
900 and constant, it is probably not addressable because the constant is
901 out of range, in that case record the address; we will generate
902 hairy code to compute the address in a register each time it is
903 needed. Similarly if it is a hard register, but one that is not
904 valid as an address register.
906 If the location is not addressable, but does not have one of the
907 above forms, assign a stack slot. We have to do this to avoid the
908 potential of producing lots of reloads if, e.g., a location involves
909 a pseudo that didn't get a hard register and has an equivalent memory
910 location that also involves a pseudo that didn't get a hard register.
912 Perhaps at some point we will improve reload_when_needed handling
913 so this problem goes away. But that's very hairy. */
915 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
916 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
918 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
920 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
922 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
923 else if (CONSTANT_P (XEXP (x, 0))
924 || (GET_CODE (XEXP (x, 0)) == REG
925 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
926 || (GET_CODE (XEXP (x, 0)) == PLUS
927 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
928 && (REGNO (XEXP (XEXP (x, 0), 0))
929 < FIRST_PSEUDO_REGISTER)
930 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
931 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
934 /* Make a new stack slot. Then indicate that something
935 changed so we go back and recompute offsets for
936 eliminable registers because the allocation of memory
937 below might change some offset. reg_equiv_{mem,address}
938 will be set up for this pseudo on the next pass around
940 reg_equiv_memory_loc[i] = 0;
941 reg_equiv_init[i] = 0;
946 if (caller_save_needed)
949 /* If we allocated another stack slot, redo elimination bookkeeping. */
950 if (starting_frame_size != get_frame_size ())
953 if (caller_save_needed)
955 save_call_clobbered_regs ();
956 /* That might have allocated new insn_chain structures. */
957 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
960 calculate_needs_all_insns (global);
962 CLEAR_REG_SET (spilled_pseudos);
965 something_changed = 0;
967 /* If we allocated any new memory locations, make another pass
968 since it might have changed elimination offsets. */
969 if (starting_frame_size != get_frame_size ())
970 something_changed = 1;
973 HARD_REG_SET to_spill;
974 CLEAR_HARD_REG_SET (to_spill);
975 update_eliminables (&to_spill);
976 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
977 if (TEST_HARD_REG_BIT (to_spill, i))
979 spill_hard_reg (i, dumpfile, 1);
982 /* Regardless of the state of spills, if we previously had
983 a register that we thought we could eliminate, but no can
984 not eliminate, we must run another pass.
986 Consider pseudos which have an entry in reg_equiv_* which
987 reference an eliminable register. We must make another pass
988 to update reg_equiv_* so that we do not substitute in the
989 old value from when we thought the elimination could be
991 something_changed = 1;
995 CLEAR_HARD_REG_SET (used_spill_regs);
996 /* Try to satisfy the needs for each insn. */
997 for (chain = insns_need_reload; chain != 0;
998 chain = chain->next_need_reload)
999 find_reload_regs (chain, dumpfile);
1004 if (insns_need_reload != 0 || did_spill)
1005 something_changed |= finish_spills (global, dumpfile);
1007 if (! something_changed)
1010 if (caller_save_needed)
1011 delete_caller_save_insns ();
1014 /* If global-alloc was run, notify it of any register eliminations we have
1017 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1018 if (ep->can_eliminate)
1019 mark_elimination (ep->from, ep->to);
1021 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1022 If that insn didn't set the register (i.e., it copied the register to
1023 memory), just delete that insn instead of the equivalencing insn plus
1024 anything now dead. If we call delete_dead_insn on that insn, we may
1025 delete the insn that actually sets the register if the register dies
1026 there and that is incorrect. */
1028 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1030 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1033 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1035 rtx equiv_insn = XEXP (list, 0);
1036 if (GET_CODE (equiv_insn) == NOTE)
1038 if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1039 delete_dead_insn (equiv_insn);
1042 PUT_CODE (equiv_insn, NOTE);
1043 NOTE_SOURCE_FILE (equiv_insn) = 0;
1044 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1050 /* Use the reload registers where necessary
1051 by generating move instructions to move the must-be-register
1052 values into or out of the reload registers. */
1054 if (insns_need_reload != 0 || something_needs_elimination
1055 || something_needs_operands_changed)
1057 int old_frame_size = get_frame_size ();
1059 reload_as_needed (global);
1061 if (old_frame_size != get_frame_size ())
1065 verify_initial_elim_offsets ();
1068 /* If we were able to eliminate the frame pointer, show that it is no
1069 longer live at the start of any basic block. If it ls live by
1070 virtue of being in a pseudo, that pseudo will be marked live
1071 and hence the frame pointer will be known to be live via that
1074 if (! frame_pointer_needed)
1075 for (i = 0; i < n_basic_blocks; i++)
1076 CLEAR_REGNO_REG_SET (BASIC_BLOCK (i)->global_live_at_start,
1077 HARD_FRAME_POINTER_REGNUM);
1079 /* Come here (with failure set nonzero) if we can't get enough spill regs
1080 and we decide not to abort about it. */
1083 reload_in_progress = 0;
1085 /* Now eliminate all pseudo regs by modifying them into
1086 their equivalent memory references.
1087 The REG-rtx's for the pseudos are modified in place,
1088 so all insns that used to refer to them now refer to memory.
1090 For a reg that has a reg_equiv_address, all those insns
1091 were changed by reloading so that no insns refer to it any longer;
1092 but the DECL_RTL of a variable decl may refer to it,
1093 and if so this causes the debugging info to mention the variable. */
1095 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1100 int is_readonly = 0;
1102 if (reg_equiv_memory_loc[i])
1104 in_struct = MEM_IN_STRUCT_P (reg_equiv_memory_loc[i]);
1105 is_scalar = MEM_SCALAR_P (reg_equiv_memory_loc[i]);
1106 is_readonly = RTX_UNCHANGING_P (reg_equiv_memory_loc[i]);
1109 if (reg_equiv_mem[i])
1110 addr = XEXP (reg_equiv_mem[i], 0);
1112 if (reg_equiv_address[i])
1113 addr = reg_equiv_address[i];
1117 if (reg_renumber[i] < 0)
1119 rtx reg = regno_reg_rtx[i];
1120 XEXP (reg, 0) = addr;
1121 REG_USERVAR_P (reg) = 0;
1122 RTX_UNCHANGING_P (reg) = is_readonly;
1123 MEM_IN_STRUCT_P (reg) = in_struct;
1124 MEM_SCALAR_P (reg) = is_scalar;
1125 /* We have no alias information about this newly created
1127 MEM_ALIAS_SET (reg) = 0;
1128 PUT_CODE (reg, MEM);
1130 else if (reg_equiv_mem[i])
1131 XEXP (reg_equiv_mem[i], 0) = addr;
1135 /* We must set reload_completed now since the cleanup_subreg_operands call
1136 below will re-recognize each insn and reload may have generated insns
1137 which are only valid during and after reload. */
1138 reload_completed = 1;
1140 /* Make a pass over all the insns and delete all USEs which we
1141 inserted only to tag a REG_EQUAL note on them. Remove all
1142 REG_DEAD and REG_UNUSED notes. Delete all CLOBBER insns and
1143 simplify (subreg (reg)) operands. Also remove all REG_RETVAL and
1144 REG_LIBCALL notes since they are no longer useful or accurate.
1145 Strip and regenerate REG_INC notes that may have been moved
1148 for (insn = first; insn; insn = NEXT_INSN (insn))
1149 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1153 if ((GET_CODE (PATTERN (insn)) == USE
1154 && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1155 || GET_CODE (PATTERN (insn)) == CLOBBER)
1157 PUT_CODE (insn, NOTE);
1158 NOTE_SOURCE_FILE (insn) = 0;
1159 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1163 pnote = ®_NOTES (insn);
1166 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1167 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1168 || REG_NOTE_KIND (*pnote) == REG_INC
1169 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1170 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1171 *pnote = XEXP (*pnote, 1);
1173 pnote = &XEXP (*pnote, 1);
1177 add_auto_inc_notes (insn, PATTERN (insn));
1180 /* And simplify (subreg (reg)) if it appears as an operand. */
1181 cleanup_subreg_operands (insn);
1184 /* If we are doing stack checking, give a warning if this function's
1185 frame size is larger than we expect. */
1186 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1188 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1189 static int verbose_warned = 0;
1191 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1192 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1193 size += UNITS_PER_WORD;
1195 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1197 warning ("frame size too large for reliable stack checking");
1198 if (! verbose_warned)
1200 warning ("try reducing the number of local variables");
1206 /* Indicate that we no longer have known memory locations or constants. */
1207 if (reg_equiv_constant)
1208 free (reg_equiv_constant);
1209 reg_equiv_constant = 0;
1210 if (reg_equiv_memory_loc)
1211 free (reg_equiv_memory_loc);
1212 reg_equiv_memory_loc = 0;
1215 free (real_known_ptr);
1219 free (reg_equiv_mem);
1220 free (reg_equiv_init);
1221 free (reg_equiv_address);
1222 free (reg_max_ref_width);
1223 free (reg_old_renumber);
1224 free (pseudo_previous_regs);
1225 free (pseudo_forbidden_regs);
1227 FREE_REG_SET (spilled_pseudos);
1229 CLEAR_HARD_REG_SET (used_spill_regs);
1230 for (i = 0; i < n_spills; i++)
1231 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1233 /* Free all the insn_chain structures at once. */
1234 obstack_free (&reload_obstack, reload_startobj);
1235 unused_insn_chains = 0;
1240 /* Yet another special case. Unfortunately, reg-stack forces people to
1241 write incorrect clobbers in asm statements. These clobbers must not
1242 cause the register to appear in bad_spill_regs, otherwise we'll call
1243 fatal_insn later. We clear the corresponding regnos in the live
1244 register sets to avoid this.
1245 The whole thing is rather sick, I'm afraid. */
1247 maybe_fix_stack_asms ()
1250 char *constraints[MAX_RECOG_OPERANDS];
1251 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1252 struct insn_chain *chain;
1254 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1257 HARD_REG_SET clobbered, allowed;
1260 if (GET_RTX_CLASS (GET_CODE (chain->insn)) != 'i'
1261 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1263 pat = PATTERN (chain->insn);
1264 if (GET_CODE (pat) != PARALLEL)
1267 CLEAR_HARD_REG_SET (clobbered);
1268 CLEAR_HARD_REG_SET (allowed);
1270 /* First, make a mask of all stack regs that are clobbered. */
1271 for (i = 0; i < XVECLEN (pat, 0); i++)
1273 rtx t = XVECEXP (pat, 0, i);
1274 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1275 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1278 /* Get the operand values and constraints out of the insn. */
1279 decode_asm_operands (pat, recog_operand, recog_operand_loc,
1280 constraints, operand_mode);
1282 /* For every operand, see what registers are allowed. */
1283 for (i = 0; i < noperands; i++)
1285 char *p = constraints[i];
1286 /* For every alternative, we compute the class of registers allowed
1287 for reloading in CLS, and merge its contents into the reg set
1289 int cls = (int) NO_REGS;
1295 if (c == '\0' || c == ',' || c == '#')
1297 /* End of one alternative - mark the regs in the current
1298 class, and reset the class. */
1299 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1304 } while (c != '\0' && c != ',');
1312 case '=': case '+': case '*': case '%': case '?': case '!':
1313 case '0': case '1': case '2': case '3': case '4': case 'm':
1314 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1315 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1316 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1318 #ifdef EXTRA_CONSTRAINT
1319 case 'Q': case 'R': case 'S': case 'T': case 'U':
1324 cls = (int) reg_class_subunion[cls][(int) BASE_REG_CLASS];
1329 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1333 cls = (int) reg_class_subunion[cls][(int) REG_CLASS_FROM_LETTER (c)];
1338 /* Those of the registers which are clobbered, but allowed by the
1339 constraints, must be usable as reload registers. So clear them
1340 out of the life information. */
1341 AND_HARD_REG_SET (allowed, clobbered);
1342 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1343 if (TEST_HARD_REG_BIT (allowed, i))
1345 CLEAR_REGNO_REG_SET (chain->live_before, i);
1346 CLEAR_REGNO_REG_SET (chain->live_after, i);
1354 /* Walk the chain of insns, and determine for each whether it needs reloads
1355 and/or eliminations. Build the corresponding insns_need_reload list, and
1356 set something_needs_elimination as appropriate. */
1358 calculate_needs_all_insns (global)
1361 struct insn_chain **pprev_reload = &insns_need_reload;
1362 struct insn_chain **pchain;
1364 something_needs_elimination = 0;
1366 for (pchain = &reload_insn_chain; *pchain != 0; pchain = &(*pchain)->next)
1369 struct insn_chain *chain;
1374 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1375 include REG_LABEL), we need to see what effects this has on the
1376 known offsets at labels. */
1378 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1379 || (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
1380 && REG_NOTES (insn) != 0))
1381 set_label_offsets (insn, insn, 0);
1383 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1385 rtx old_body = PATTERN (insn);
1386 int old_code = INSN_CODE (insn);
1387 rtx old_notes = REG_NOTES (insn);
1388 int did_elimination = 0;
1389 int operands_changed = 0;
1390 rtx set = single_set (insn);
1392 /* Skip insns that only set an equivalence. */
1393 if (set && GET_CODE (SET_DEST (set)) == REG
1394 && reg_renumber[REGNO (SET_DEST (set))] < 0
1395 && reg_equiv_constant[REGNO (SET_DEST (set))])
1397 /* Must clear out the shortcuts, in case they were set last
1399 chain->need_elim = 0;
1400 chain->need_reload = 0;
1401 chain->need_operand_change = 0;
1405 /* If needed, eliminate any eliminable registers. */
1406 if (num_eliminable || num_eliminable_invariants)
1407 did_elimination = eliminate_regs_in_insn (insn, 0);
1409 /* Analyze the instruction. */
1410 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1411 global, spill_reg_order);
1413 /* If a no-op set needs more than one reload, this is likely
1414 to be something that needs input address reloads. We
1415 can't get rid of this cleanly later, and it is of no use
1416 anyway, so discard it now.
1417 We only do this when expensive_optimizations is enabled,
1418 since this complements reload inheritance / output
1419 reload deletion, and it can make debugging harder. */
1420 if (flag_expensive_optimizations && n_reloads > 1)
1422 rtx set = single_set (insn);
1424 && SET_SRC (set) == SET_DEST (set)
1425 && GET_CODE (SET_SRC (set)) == REG
1426 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1428 PUT_CODE (insn, NOTE);
1429 NOTE_SOURCE_FILE (insn) = 0;
1430 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1435 update_eliminable_offsets ();
1437 /* Remember for later shortcuts which insns had any reloads or
1438 register eliminations. */
1439 chain->need_elim = did_elimination;
1440 chain->need_reload = n_reloads > 0;
1441 chain->need_operand_change = operands_changed;
1443 /* Discard any register replacements done. */
1444 if (did_elimination)
1446 obstack_free (&reload_obstack, reload_firstobj);
1447 PATTERN (insn) = old_body;
1448 INSN_CODE (insn) = old_code;
1449 REG_NOTES (insn) = old_notes;
1450 something_needs_elimination = 1;
1453 something_needs_operands_changed |= operands_changed;
1457 *pprev_reload = chain;
1458 pprev_reload = &chain->next_need_reload;
1460 calculate_needs (chain);
1467 /* Compute the most additional registers needed by one instruction,
1468 given by CHAIN. Collect information separately for each class of regs.
1470 To compute the number of reload registers of each class needed for an
1471 insn, we must simulate what choose_reload_regs can do. We do this by
1472 splitting an insn into an "input" and an "output" part. RELOAD_OTHER
1473 reloads are used in both. The input part uses those reloads,
1474 RELOAD_FOR_INPUT reloads, which must be live over the entire input section
1475 of reloads, and the maximum of all the RELOAD_FOR_INPUT_ADDRESS and
1476 RELOAD_FOR_OPERAND_ADDRESS reloads, which conflict with the inputs.
1478 The registers needed for output are RELOAD_OTHER and RELOAD_FOR_OUTPUT,
1479 which are live for the entire output portion, and the maximum of all the
1480 RELOAD_FOR_OUTPUT_ADDRESS reloads for each operand.
1482 The total number of registers needed is the maximum of the
1483 inputs and outputs. */
1486 calculate_needs (chain)
1487 struct insn_chain *chain;
1491 /* Each `struct needs' corresponds to one RELOAD_... type. */
1495 struct needs output;
1497 struct needs other_addr;
1498 struct needs op_addr;
1499 struct needs op_addr_reload;
1500 struct needs in_addr[MAX_RECOG_OPERANDS];
1501 struct needs in_addr_addr[MAX_RECOG_OPERANDS];
1502 struct needs out_addr[MAX_RECOG_OPERANDS];
1503 struct needs out_addr_addr[MAX_RECOG_OPERANDS];
1506 bzero ((char *) chain->group_size, sizeof chain->group_size);
1507 for (i = 0; i < N_REG_CLASSES; i++)
1508 chain->group_mode[i] = VOIDmode;
1509 bzero ((char *) &insn_needs, sizeof insn_needs);
1511 /* Count each reload once in every class
1512 containing the reload's own class. */
1514 for (i = 0; i < n_reloads; i++)
1516 register enum reg_class *p;
1517 enum reg_class class = reload_reg_class[i];
1519 enum machine_mode mode;
1520 struct needs *this_needs;
1522 /* Don't count the dummy reloads, for which one of the
1523 regs mentioned in the insn can be used for reloading.
1524 Don't count optional reloads.
1525 Don't count reloads that got combined with others. */
1526 if (reload_reg_rtx[i] != 0
1527 || reload_optional[i] != 0
1528 || (reload_out[i] == 0 && reload_in[i] == 0
1529 && ! reload_secondary_p[i]))
1532 mode = reload_inmode[i];
1533 if (GET_MODE_SIZE (reload_outmode[i]) > GET_MODE_SIZE (mode))
1534 mode = reload_outmode[i];
1535 size = CLASS_MAX_NREGS (class, mode);
1537 /* Decide which time-of-use to count this reload for. */
1538 switch (reload_when_needed[i])
1541 this_needs = &insn_needs.other;
1543 case RELOAD_FOR_INPUT:
1544 this_needs = &insn_needs.input;
1546 case RELOAD_FOR_OUTPUT:
1547 this_needs = &insn_needs.output;
1549 case RELOAD_FOR_INSN:
1550 this_needs = &insn_needs.insn;
1552 case RELOAD_FOR_OTHER_ADDRESS:
1553 this_needs = &insn_needs.other_addr;
1555 case RELOAD_FOR_INPUT_ADDRESS:
1556 this_needs = &insn_needs.in_addr[reload_opnum[i]];
1558 case RELOAD_FOR_INPADDR_ADDRESS:
1559 this_needs = &insn_needs.in_addr_addr[reload_opnum[i]];
1561 case RELOAD_FOR_OUTPUT_ADDRESS:
1562 this_needs = &insn_needs.out_addr[reload_opnum[i]];
1564 case RELOAD_FOR_OUTADDR_ADDRESS:
1565 this_needs = &insn_needs.out_addr_addr[reload_opnum[i]];
1567 case RELOAD_FOR_OPERAND_ADDRESS:
1568 this_needs = &insn_needs.op_addr;
1570 case RELOAD_FOR_OPADDR_ADDR:
1571 this_needs = &insn_needs.op_addr_reload;
1579 enum machine_mode other_mode, allocate_mode;
1581 /* Count number of groups needed separately from
1582 number of individual regs needed. */
1583 this_needs->groups[(int) class]++;
1584 p = reg_class_superclasses[(int) class];
1585 while (*p != LIM_REG_CLASSES)
1586 this_needs->groups[(int) *p++]++;
1588 /* Record size and mode of a group of this class. */
1589 /* If more than one size group is needed,
1590 make all groups the largest needed size. */
1591 if (chain->group_size[(int) class] < size)
1593 other_mode = chain->group_mode[(int) class];
1594 allocate_mode = mode;
1596 chain->group_size[(int) class] = size;
1597 chain->group_mode[(int) class] = mode;
1602 allocate_mode = chain->group_mode[(int) class];
1605 /* Crash if two dissimilar machine modes both need
1606 groups of consecutive regs of the same class. */
1608 if (other_mode != VOIDmode && other_mode != allocate_mode
1609 && ! modes_equiv_for_class_p (allocate_mode,
1611 fatal_insn ("Two dissimilar machine modes both need groups of consecutive regs of the same class",
1616 this_needs->regs[(unsigned char)reload_nongroup[i]][(int) class] += 1;
1617 p = reg_class_superclasses[(int) class];
1618 while (*p != LIM_REG_CLASSES)
1619 this_needs->regs[(unsigned char)reload_nongroup[i]][(int) *p++] += 1;
1625 /* All reloads have been counted for this insn;
1626 now merge the various times of use.
1627 This sets insn_needs, etc., to the maximum total number
1628 of registers needed at any point in this insn. */
1630 for (i = 0; i < N_REG_CLASSES; i++)
1632 int j, in_max, out_max;
1634 /* Compute normal and nongroup needs. */
1635 for (j = 0; j <= 1; j++)
1638 for (in_max = 0, out_max = 0, k = 0; k < reload_n_operands; k++)
1640 in_max = MAX (in_max,
1641 (insn_needs.in_addr[k].regs[j][i]
1642 + insn_needs.in_addr_addr[k].regs[j][i]));
1643 out_max = MAX (out_max, insn_needs.out_addr[k].regs[j][i]);
1644 out_max = MAX (out_max,
1645 insn_needs.out_addr_addr[k].regs[j][i]);
1648 /* RELOAD_FOR_INSN reloads conflict with inputs, outputs,
1649 and operand addresses but not things used to reload
1650 them. Similarly, RELOAD_FOR_OPERAND_ADDRESS reloads
1651 don't conflict with things needed to reload inputs or
1654 in_max = MAX (MAX (insn_needs.op_addr.regs[j][i],
1655 insn_needs.op_addr_reload.regs[j][i]),
1658 out_max = MAX (out_max, insn_needs.insn.regs[j][i]);
1660 insn_needs.input.regs[j][i]
1661 = MAX (insn_needs.input.regs[j][i]
1662 + insn_needs.op_addr.regs[j][i]
1663 + insn_needs.insn.regs[j][i],
1664 in_max + insn_needs.input.regs[j][i]);
1666 insn_needs.output.regs[j][i] += out_max;
1667 insn_needs.other.regs[j][i]
1668 += MAX (MAX (insn_needs.input.regs[j][i],
1669 insn_needs.output.regs[j][i]),
1670 insn_needs.other_addr.regs[j][i]);
1674 /* Now compute group needs. */
1675 for (in_max = 0, out_max = 0, j = 0; j < reload_n_operands; j++)
1677 in_max = MAX (in_max, insn_needs.in_addr[j].groups[i]);
1678 in_max = MAX (in_max, insn_needs.in_addr_addr[j].groups[i]);
1679 out_max = MAX (out_max, insn_needs.out_addr[j].groups[i]);
1680 out_max = MAX (out_max, insn_needs.out_addr_addr[j].groups[i]);
1683 in_max = MAX (MAX (insn_needs.op_addr.groups[i],
1684 insn_needs.op_addr_reload.groups[i]),
1686 out_max = MAX (out_max, insn_needs.insn.groups[i]);
1688 insn_needs.input.groups[i]
1689 = MAX (insn_needs.input.groups[i]
1690 + insn_needs.op_addr.groups[i]
1691 + insn_needs.insn.groups[i],
1692 in_max + insn_needs.input.groups[i]);
1694 insn_needs.output.groups[i] += out_max;
1695 insn_needs.other.groups[i]
1696 += MAX (MAX (insn_needs.input.groups[i],
1697 insn_needs.output.groups[i]),
1698 insn_needs.other_addr.groups[i]);
1701 /* Record the needs for later. */
1702 chain->need = insn_needs.other;
1705 /* Find a group of exactly 2 registers.
1707 First try to fill out the group by spilling a single register which
1708 would allow completion of the group.
1710 Then try to create a new group from a pair of registers, neither of
1711 which are explicitly used.
1713 Then try to create a group from any pair of registers. */
1716 find_tworeg_group (chain, class, dumpfile)
1717 struct insn_chain *chain;
1722 /* First, look for a register that will complete a group. */
1723 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1727 j = potential_reload_regs[i];
1728 if (j >= 0 && ! TEST_HARD_REG_BIT (bad_spill_regs, j)
1729 && ((j > 0 && (other = j - 1, spill_reg_order[other] >= 0)
1730 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1731 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1732 && HARD_REGNO_MODE_OK (other, chain->group_mode[class])
1733 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, other)
1734 /* We don't want one part of another group.
1735 We could get "two groups" that overlap! */
1736 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, other))
1737 || (j < FIRST_PSEUDO_REGISTER - 1
1738 && (other = j + 1, spill_reg_order[other] >= 0)
1739 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1740 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1741 && HARD_REGNO_MODE_OK (j, chain->group_mode[class])
1742 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, other)
1743 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, other))))
1745 register enum reg_class *p;
1747 /* We have found one that will complete a group,
1748 so count off one group as provided. */
1749 chain->need.groups[class]--;
1750 p = reg_class_superclasses[class];
1751 while (*p != LIM_REG_CLASSES)
1753 if (chain->group_size [(int) *p] <= chain->group_size [class])
1754 chain->need.groups[(int) *p]--;
1758 /* Indicate both these regs are part of a group. */
1759 SET_HARD_REG_BIT (chain->counted_for_groups, j);
1760 SET_HARD_REG_BIT (chain->counted_for_groups, other);
1764 /* We can't complete a group, so start one. */
1765 if (i == FIRST_PSEUDO_REGISTER)
1766 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1769 j = potential_reload_regs[i];
1770 /* Verify that J+1 is a potential reload reg. */
1771 for (k = 0; k < FIRST_PSEUDO_REGISTER; k++)
1772 if (potential_reload_regs[k] == j + 1)
1774 if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1775 && k < FIRST_PSEUDO_REGISTER
1776 && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0
1777 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1778 && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1)
1779 && HARD_REGNO_MODE_OK (j, chain->group_mode[class])
1780 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, j + 1)
1781 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + 1))
1785 /* I should be the index in potential_reload_regs
1786 of the new reload reg we have found. */
1788 new_spill_reg (chain, i, class, 0, dumpfile);
1791 /* Find a group of more than 2 registers.
1792 Look for a sufficient sequence of unspilled registers, and spill them all
1796 find_group (chain, class, dumpfile)
1797 struct insn_chain *chain;
1803 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1805 int j = potential_reload_regs[i];
1808 && j + chain->group_size[class] <= FIRST_PSEUDO_REGISTER
1809 && HARD_REGNO_MODE_OK (j, chain->group_mode[class]))
1812 /* Check each reg in the sequence. */
1813 for (k = 0; k < chain->group_size[class]; k++)
1814 if (! (spill_reg_order[j + k] < 0
1815 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + k)
1816 && TEST_HARD_REG_BIT (reg_class_contents[class], j + k)))
1818 /* We got a full sequence, so spill them all. */
1819 if (k == chain->group_size[class])
1821 register enum reg_class *p;
1822 for (k = 0; k < chain->group_size[class]; k++)
1825 SET_HARD_REG_BIT (chain->counted_for_groups, j + k);
1826 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++)
1827 if (potential_reload_regs[idx] == j + k)
1829 new_spill_reg (chain, idx, class, 0, dumpfile);
1832 /* We have found one that will complete a group,
1833 so count off one group as provided. */
1834 chain->need.groups[class]--;
1835 p = reg_class_superclasses[class];
1836 while (*p != LIM_REG_CLASSES)
1838 if (chain->group_size [(int) *p]
1839 <= chain->group_size [class])
1840 chain->need.groups[(int) *p]--;
1847 /* There are no groups left. */
1848 spill_failure (chain->insn);
1852 /* If pseudo REG conflicts with one of our reload registers, mark it as
1855 maybe_mark_pseudo_spilled (reg)
1859 int r = reg_renumber[reg];
1864 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1865 for (i = 0; i < n_spills; i++)
1866 if (r <= spill_regs[i] && r + nregs > spill_regs[i])
1868 SET_REGNO_REG_SET (spilled_pseudos, reg);
1873 /* Find more reload regs to satisfy the remaining need of an insn, which
1875 Do it by ascending class number, since otherwise a reg
1876 might be spilled for a big class and might fail to count
1877 for a smaller class even though it belongs to that class.
1879 Count spilled regs in `spills', and add entries to
1880 `spill_regs' and `spill_reg_order'.
1882 ??? Note there is a problem here.
1883 When there is a need for a group in a high-numbered class,
1884 and also need for non-group regs that come from a lower class,
1885 the non-group regs are chosen first. If there aren't many regs,
1886 they might leave no room for a group.
1888 This was happening on the 386. To fix it, we added the code
1889 that calls possible_group_p, so that the lower class won't
1890 break up the last possible group.
1892 Really fixing the problem would require changes above
1893 in counting the regs already spilled, and in choose_reload_regs.
1894 It might be hard to avoid introducing bugs there. */
1897 find_reload_regs (chain, dumpfile)
1898 struct insn_chain *chain;
1902 short *group_needs = chain->need.groups;
1903 short *simple_needs = chain->need.regs[0];
1904 short *nongroup_needs = chain->need.regs[1];
1907 fprintf (dumpfile, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1909 /* Compute the order of preference for hard registers to spill.
1910 Store them by decreasing preference in potential_reload_regs. */
1912 order_regs_for_reload (chain);
1914 /* So far, no hard regs have been spilled. */
1916 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1917 spill_reg_order[i] = -1;
1919 CLEAR_HARD_REG_SET (chain->used_spill_regs);
1920 CLEAR_HARD_REG_SET (chain->counted_for_groups);
1921 CLEAR_HARD_REG_SET (chain->counted_for_nongroups);
1923 for (class = 0; class < N_REG_CLASSES; class++)
1925 /* First get the groups of registers.
1926 If we got single registers first, we might fragment
1928 while (group_needs[class] > 0)
1930 /* If any single spilled regs happen to form groups,
1931 count them now. Maybe we don't really need
1932 to spill another group. */
1933 count_possible_groups (chain, class);
1935 if (group_needs[class] <= 0)
1938 /* Groups of size 2, the only groups used on most machines,
1939 are treated specially. */
1940 if (chain->group_size[class] == 2)
1941 find_tworeg_group (chain, class, dumpfile);
1943 find_group (chain, class, dumpfile);
1948 /* Now similarly satisfy all need for single registers. */
1950 while (simple_needs[class] > 0 || nongroup_needs[class] > 0)
1952 /* If we spilled enough regs, but they weren't counted
1953 against the non-group need, see if we can count them now.
1954 If so, we can avoid some actual spilling. */
1955 if (simple_needs[class] <= 0 && nongroup_needs[class] > 0)
1956 for (i = 0; i < n_spills; i++)
1958 int regno = spill_regs[i];
1959 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1960 && !TEST_HARD_REG_BIT (chain->counted_for_groups, regno)
1961 && !TEST_HARD_REG_BIT (chain->counted_for_nongroups, regno)
1962 && nongroup_needs[class] > 0)
1964 register enum reg_class *p;
1966 SET_HARD_REG_BIT (chain->counted_for_nongroups, regno);
1967 nongroup_needs[class]--;
1968 p = reg_class_superclasses[class];
1969 while (*p != LIM_REG_CLASSES)
1970 nongroup_needs[(int) *p++]--;
1974 if (simple_needs[class] <= 0 && nongroup_needs[class] <= 0)
1977 /* Consider the potential reload regs that aren't
1978 yet in use as reload regs, in order of preference.
1979 Find the most preferred one that's in this class. */
1981 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1983 int regno = potential_reload_regs[i];
1985 && TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1986 /* If this reg will not be available for groups,
1987 pick one that does not foreclose possible groups.
1988 This is a kludge, and not very general,
1989 but it should be sufficient to make the 386 work,
1990 and the problem should not occur on machines with
1992 && (nongroup_needs[class] == 0
1993 || possible_group_p (chain, regno)))
1997 /* If we couldn't get a register, try to get one even if we
1998 might foreclose possible groups. This may cause problems
1999 later, but that's better than aborting now, since it is
2000 possible that we will, in fact, be able to form the needed
2001 group even with this allocation. */
2003 if (i >= FIRST_PSEUDO_REGISTER
2004 && asm_noperands (chain->insn) < 0)
2005 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2006 if (potential_reload_regs[i] >= 0
2007 && TEST_HARD_REG_BIT (reg_class_contents[class],
2008 potential_reload_regs[i]))
2011 /* I should be the index in potential_reload_regs
2012 of the new reload reg we have found. */
2014 new_spill_reg (chain, i, class, 1, dumpfile);
2020 /* We know which hard regs to use, now mark the pseudos that live in them
2021 as needing to be kicked out. */
2022 EXECUTE_IF_SET_IN_REG_SET
2023 (chain->live_before, FIRST_PSEUDO_REGISTER, i,
2025 maybe_mark_pseudo_spilled (i);
2027 EXECUTE_IF_SET_IN_REG_SET
2028 (chain->live_after, FIRST_PSEUDO_REGISTER, i,
2030 maybe_mark_pseudo_spilled (i);
2033 IOR_HARD_REG_SET (used_spill_regs, chain->used_spill_regs);
2037 dump_needs (chain, dumpfile)
2038 struct insn_chain *chain;
2041 static char *reg_class_names[] = REG_CLASS_NAMES;
2043 struct needs *n = &chain->need;
2045 for (i = 0; i < N_REG_CLASSES; i++)
2047 if (n->regs[i][0] > 0)
2049 ";; Need %d reg%s of class %s.\n",
2050 n->regs[i][0], n->regs[i][0] == 1 ? "" : "s",
2051 reg_class_names[i]);
2052 if (n->regs[i][1] > 0)
2054 ";; Need %d nongroup reg%s of class %s.\n",
2055 n->regs[i][1], n->regs[i][1] == 1 ? "" : "s",
2056 reg_class_names[i]);
2057 if (n->groups[i] > 0)
2059 ";; Need %d group%s (%smode) of class %s.\n",
2060 n->groups[i], n->groups[i] == 1 ? "" : "s",
2061 mode_name[(int) chain->group_mode[i]],
2062 reg_class_names[i]);
2066 /* Delete all insns that were inserted by emit_caller_save_insns during
2069 delete_caller_save_insns ()
2071 struct insn_chain *c = reload_insn_chain;
2075 while (c != 0 && c->is_caller_save_insn)
2077 struct insn_chain *next = c->next;
2080 if (insn == BLOCK_HEAD (c->block))
2081 BLOCK_HEAD (c->block) = NEXT_INSN (insn);
2082 if (insn == BLOCK_END (c->block))
2083 BLOCK_END (c->block) = PREV_INSN (insn);
2084 if (c == reload_insn_chain)
2085 reload_insn_chain = next;
2087 if (NEXT_INSN (insn) != 0)
2088 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
2089 if (PREV_INSN (insn) != 0)
2090 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
2093 next->prev = c->prev;
2095 c->prev->next = next;
2096 c->next = unused_insn_chains;
2097 unused_insn_chains = c;
2105 /* Nonzero if, after spilling reg REGNO for non-groups,
2106 it will still be possible to find a group if we still need one. */
2109 possible_group_p (chain, regno)
2110 struct insn_chain *chain;
2114 int class = (int) NO_REGS;
2116 for (i = 0; i < (int) N_REG_CLASSES; i++)
2117 if (chain->need.groups[i] > 0)
2123 if (class == (int) NO_REGS)
2126 /* Consider each pair of consecutive registers. */
2127 for (i = 0; i < FIRST_PSEUDO_REGISTER - 1; i++)
2129 /* Ignore pairs that include reg REGNO. */
2130 if (i == regno || i + 1 == regno)
2133 /* Ignore pairs that are outside the class that needs the group.
2134 ??? Here we fail to handle the case where two different classes
2135 independently need groups. But this never happens with our
2136 current machine descriptions. */
2137 if (! (TEST_HARD_REG_BIT (reg_class_contents[class], i)
2138 && TEST_HARD_REG_BIT (reg_class_contents[class], i + 1)))
2141 /* A pair of consecutive regs we can still spill does the trick. */
2142 if (spill_reg_order[i] < 0 && spill_reg_order[i + 1] < 0
2143 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2144 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1))
2147 /* A pair of one already spilled and one we can spill does it
2148 provided the one already spilled is not otherwise reserved. */
2149 if (spill_reg_order[i] < 0
2150 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2151 && spill_reg_order[i + 1] >= 0
2152 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, i + 1)
2153 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, i + 1))
2155 if (spill_reg_order[i + 1] < 0
2156 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1)
2157 && spill_reg_order[i] >= 0
2158 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, i)
2159 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, i))
2166 /* Count any groups of CLASS that can be formed from the registers recently
2170 count_possible_groups (chain, class)
2171 struct insn_chain *chain;
2177 /* Now find all consecutive groups of spilled registers
2178 and mark each group off against the need for such groups.
2179 But don't count them against ordinary need, yet. */
2181 if (chain->group_size[class] == 0)
2184 CLEAR_HARD_REG_SET (new);
2186 /* Make a mask of all the regs that are spill regs in class I. */
2187 for (i = 0; i < n_spills; i++)
2189 int regno = spill_regs[i];
2191 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
2192 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, regno)
2193 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, regno))
2194 SET_HARD_REG_BIT (new, regno);
2197 /* Find each consecutive group of them. */
2198 for (i = 0; i < FIRST_PSEUDO_REGISTER && chain->need.groups[class] > 0; i++)
2199 if (TEST_HARD_REG_BIT (new, i)
2200 && i + chain->group_size[class] <= FIRST_PSEUDO_REGISTER
2201 && HARD_REGNO_MODE_OK (i, chain->group_mode[class]))
2203 for (j = 1; j < chain->group_size[class]; j++)
2204 if (! TEST_HARD_REG_BIT (new, i + j))
2207 if (j == chain->group_size[class])
2209 /* We found a group. Mark it off against this class's need for
2210 groups, and against each superclass too. */
2211 register enum reg_class *p;
2213 chain->need.groups[class]--;
2214 p = reg_class_superclasses[class];
2215 while (*p != LIM_REG_CLASSES)
2217 if (chain->group_size [(int) *p] <= chain->group_size [class])
2218 chain->need.groups[(int) *p]--;
2222 /* Don't count these registers again. */
2223 for (j = 0; j < chain->group_size[class]; j++)
2224 SET_HARD_REG_BIT (chain->counted_for_groups, i + j);
2227 /* Skip to the last reg in this group. When i is incremented above,
2228 it will then point to the first reg of the next possible group. */
2233 /* ALLOCATE_MODE is a register mode that needs to be reloaded. OTHER_MODE is
2234 another mode that needs to be reloaded for the same register class CLASS.
2235 If any reg in CLASS allows ALLOCATE_MODE but not OTHER_MODE, fail.
2236 ALLOCATE_MODE will never be smaller than OTHER_MODE.
2238 This code used to also fail if any reg in CLASS allows OTHER_MODE but not
2239 ALLOCATE_MODE. This test is unnecessary, because we will never try to put
2240 something of mode ALLOCATE_MODE into an OTHER_MODE register. Testing this
2241 causes unnecessary failures on machines requiring alignment of register
2242 groups when the two modes are different sizes, because the larger mode has
2243 more strict alignment rules than the smaller mode. */
2246 modes_equiv_for_class_p (allocate_mode, other_mode, class)
2247 enum machine_mode allocate_mode, other_mode;
2248 enum reg_class class;
2251 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
2253 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno)
2254 && HARD_REGNO_MODE_OK (regno, allocate_mode)
2255 && ! HARD_REGNO_MODE_OK (regno, other_mode))
2261 /* Handle the failure to find a register to spill.
2262 INSN should be one of the insns which needed this particular spill reg. */
2265 spill_failure (insn)
2268 if (asm_noperands (PATTERN (insn)) >= 0)
2269 error_for_asm (insn, "`asm' needs too many reloads");
2271 fatal_insn ("Unable to find a register to spill.", insn);
2274 /* Add a new register to the tables of available spill-registers.
2275 CHAIN is the insn for which the register will be used; we decrease the
2277 I is the index of this register in potential_reload_regs.
2278 CLASS is the regclass whose need is being satisfied.
2279 NONGROUP is 0 if this register is part of a group.
2280 DUMPFILE is the same as the one that `reload' got. */
2283 new_spill_reg (chain, i, class, nongroup, dumpfile)
2284 struct insn_chain *chain;
2290 register enum reg_class *p;
2291 int regno = potential_reload_regs[i];
2293 if (i >= FIRST_PSEUDO_REGISTER)
2295 spill_failure (chain->insn);
2300 if (TEST_HARD_REG_BIT (bad_spill_regs, regno))
2302 static char *reg_class_names[] = REG_CLASS_NAMES;
2304 if (asm_noperands (PATTERN (chain->insn)) < 0)
2306 /* The error message is still correct - we know only that it wasn't
2307 an asm statement that caused the problem, but one of the global
2308 registers declared by the users might have screwed us. */
2309 error ("fixed or forbidden register %d (%s) was spilled for class %s.",
2310 regno, reg_names[regno], reg_class_names[class]);
2311 error ("This may be due to a compiler bug or to impossible asm");
2312 error ("statements or clauses.");
2313 fatal_insn ("This is the instruction:", chain->insn);
2315 error_for_asm (chain->insn, "Invalid `asm' statement:");
2316 error_for_asm (chain->insn,
2317 "fixed or forbidden register %d (%s) was spilled for class %s.",
2318 regno, reg_names[regno], reg_class_names[class]);
2323 /* Make reg REGNO an additional reload reg. */
2325 potential_reload_regs[i] = -1;
2326 spill_regs[n_spills] = regno;
2327 spill_reg_order[regno] = n_spills;
2329 fprintf (dumpfile, "Spilling reg %d.\n", regno);
2330 SET_HARD_REG_BIT (chain->used_spill_regs, regno);
2332 /* Clear off the needs we just satisfied. */
2334 chain->need.regs[0][class]--;
2335 p = reg_class_superclasses[class];
2336 while (*p != LIM_REG_CLASSES)
2337 chain->need.regs[0][(int) *p++]--;
2339 if (nongroup && chain->need.regs[1][class] > 0)
2341 SET_HARD_REG_BIT (chain->counted_for_nongroups, regno);
2342 chain->need.regs[1][class]--;
2343 p = reg_class_superclasses[class];
2344 while (*p != LIM_REG_CLASSES)
2345 chain->need.regs[1][(int) *p++]--;
2351 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2352 data that is dead in INSN. */
2355 delete_dead_insn (insn)
2358 rtx prev = prev_real_insn (insn);
2361 /* If the previous insn sets a register that dies in our insn, delete it
2363 if (prev && GET_CODE (PATTERN (prev)) == SET
2364 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
2365 && reg_mentioned_p (prev_dest, PATTERN (insn))
2366 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2367 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2368 delete_dead_insn (prev);
2370 PUT_CODE (insn, NOTE);
2371 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
2372 NOTE_SOURCE_FILE (insn) = 0;
2375 /* Modify the home of pseudo-reg I.
2376 The new home is present in reg_renumber[I].
2378 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2379 or it may be -1, meaning there is none or it is not relevant.
2380 This is used so that all pseudos spilled from a given hard reg
2381 can share one stack slot. */
2384 alter_reg (i, from_reg)
2388 /* When outputting an inline function, this can happen
2389 for a reg that isn't actually used. */
2390 if (regno_reg_rtx[i] == 0)
2393 /* If the reg got changed to a MEM at rtl-generation time,
2395 if (GET_CODE (regno_reg_rtx[i]) != REG)
2398 /* Modify the reg-rtx to contain the new hard reg
2399 number or else to contain its pseudo reg number. */
2400 REGNO (regno_reg_rtx[i])
2401 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
2403 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2404 allocate a stack slot for it. */
2406 if (reg_renumber[i] < 0
2407 && REG_N_REFS (i) > 0
2408 && reg_equiv_constant[i] == 0
2409 && reg_equiv_memory_loc[i] == 0)
2412 int inherent_size = PSEUDO_REGNO_BYTES (i);
2413 int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2416 /* Each pseudo reg has an inherent size which comes from its own mode,
2417 and a total size which provides room for paradoxical subregs
2418 which refer to the pseudo reg in wider modes.
2420 We can use a slot already allocated if it provides both
2421 enough inherent space and enough total space.
2422 Otherwise, we allocate a new slot, making sure that it has no less
2423 inherent space, and no less total space, then the previous slot. */
2426 /* No known place to spill from => no slot to reuse. */
2427 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
2428 inherent_size == total_size ? 0 : -1);
2429 if (BYTES_BIG_ENDIAN)
2430 /* Cancel the big-endian correction done in assign_stack_local.
2431 Get the address of the beginning of the slot.
2432 This is so we can do a big-endian correction unconditionally
2434 adjust = inherent_size - total_size;
2436 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2438 /* Reuse a stack slot if possible. */
2439 else if (spill_stack_slot[from_reg] != 0
2440 && spill_stack_slot_width[from_reg] >= total_size
2441 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2443 x = spill_stack_slot[from_reg];
2444 /* Allocate a bigger slot. */
2447 /* Compute maximum size needed, both for inherent size
2448 and for total size. */
2449 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2451 if (spill_stack_slot[from_reg])
2453 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2455 mode = GET_MODE (spill_stack_slot[from_reg]);
2456 if (spill_stack_slot_width[from_reg] > total_size)
2457 total_size = spill_stack_slot_width[from_reg];
2459 /* Make a slot with that size. */
2460 x = assign_stack_local (mode, total_size,
2461 inherent_size == total_size ? 0 : -1);
2463 if (BYTES_BIG_ENDIAN)
2465 /* Cancel the big-endian correction done in assign_stack_local.
2466 Get the address of the beginning of the slot.
2467 This is so we can do a big-endian correction unconditionally
2469 adjust = GET_MODE_SIZE (mode) - total_size;
2471 stack_slot = gen_rtx_MEM (mode_for_size (total_size
2474 plus_constant (XEXP (x, 0), adjust));
2476 spill_stack_slot[from_reg] = stack_slot;
2477 spill_stack_slot_width[from_reg] = total_size;
2480 /* On a big endian machine, the "address" of the slot
2481 is the address of the low part that fits its inherent mode. */
2482 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2483 adjust += (total_size - inherent_size);
2485 /* If we have any adjustment to make, or if the stack slot is the
2486 wrong mode, make a new stack slot. */
2487 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
2489 x = gen_rtx_MEM (GET_MODE (regno_reg_rtx[i]),
2490 plus_constant (XEXP (x, 0), adjust));
2492 /* If this was shared among registers, must ensure we never
2493 set it readonly since that can cause scheduling
2494 problems. Note we would only have in this adjustment
2495 case in any event, since the code above doesn't set it. */
2498 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2501 /* Save the stack slot for later. */
2502 reg_equiv_memory_loc[i] = x;
2506 /* Mark the slots in regs_ever_live for the hard regs
2507 used by pseudo-reg number REGNO. */
2510 mark_home_live (regno)
2513 register int i, lim;
2514 i = reg_renumber[regno];
2517 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2519 regs_ever_live[i++] = 1;
2522 /* This function handles the tracking of elimination offsets around branches.
2524 X is a piece of RTL being scanned.
2526 INSN is the insn that it came from, if any.
2528 INITIAL_P is non-zero if we are to set the offset to be the initial
2529 offset and zero if we are setting the offset of the label to be the
2533 set_label_offsets (x, insn, initial_p)
2538 enum rtx_code code = GET_CODE (x);
2541 struct elim_table *p;
2546 if (LABEL_REF_NONLOCAL_P (x))
2551 /* ... fall through ... */
2554 /* If we know nothing about this label, set the desired offsets. Note
2555 that this sets the offset at a label to be the offset before a label
2556 if we don't know anything about the label. This is not correct for
2557 the label after a BARRIER, but is the best guess we can make. If
2558 we guessed wrong, we will suppress an elimination that might have
2559 been possible had we been able to guess correctly. */
2561 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2563 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2564 offsets_at[CODE_LABEL_NUMBER (x)][i]
2565 = (initial_p ? reg_eliminate[i].initial_offset
2566 : reg_eliminate[i].offset);
2567 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2570 /* Otherwise, if this is the definition of a label and it is
2571 preceded by a BARRIER, set our offsets to the known offset of
2575 && (tem = prev_nonnote_insn (insn)) != 0
2576 && GET_CODE (tem) == BARRIER)
2577 set_offsets_for_label (insn);
2579 /* If neither of the above cases is true, compare each offset
2580 with those previously recorded and suppress any eliminations
2581 where the offsets disagree. */
2583 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2584 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2585 != (initial_p ? reg_eliminate[i].initial_offset
2586 : reg_eliminate[i].offset))
2587 reg_eliminate[i].can_eliminate = 0;
2592 set_label_offsets (PATTERN (insn), insn, initial_p);
2594 /* ... fall through ... */
2598 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2599 and hence must have all eliminations at their initial offsets. */
2600 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2601 if (REG_NOTE_KIND (tem) == REG_LABEL)
2602 set_label_offsets (XEXP (tem, 0), insn, 1);
2607 /* Each of the labels in the address vector must be at their initial
2608 offsets. We want the first field for ADDR_VEC and the second
2609 field for ADDR_DIFF_VEC. */
2611 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2612 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2617 /* We only care about setting PC. If the source is not RETURN,
2618 IF_THEN_ELSE, or a label, disable any eliminations not at
2619 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2620 isn't one of those possibilities. For branches to a label,
2621 call ourselves recursively.
2623 Note that this can disable elimination unnecessarily when we have
2624 a non-local goto since it will look like a non-constant jump to
2625 someplace in the current function. This isn't a significant
2626 problem since such jumps will normally be when all elimination
2627 pairs are back to their initial offsets. */
2629 if (SET_DEST (x) != pc_rtx)
2632 switch (GET_CODE (SET_SRC (x)))
2639 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2643 tem = XEXP (SET_SRC (x), 1);
2644 if (GET_CODE (tem) == LABEL_REF)
2645 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2646 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2649 tem = XEXP (SET_SRC (x), 2);
2650 if (GET_CODE (tem) == LABEL_REF)
2651 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2652 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2660 /* If we reach here, all eliminations must be at their initial
2661 offset because we are doing a jump to a variable address. */
2662 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2663 if (p->offset != p->initial_offset)
2664 p->can_eliminate = 0;
2672 /* Used for communication between the next two function to properly share
2673 the vector for an ASM_OPERANDS. */
2675 static struct rtvec_def *old_asm_operands_vec, *new_asm_operands_vec;
2677 /* Scan X and replace any eliminable registers (such as fp) with a
2678 replacement (such as sp), plus an offset.
2680 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2681 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2682 MEM, we are allowed to replace a sum of a register and the constant zero
2683 with the register, which we cannot do outside a MEM. In addition, we need
2684 to record the fact that a register is referenced outside a MEM.
2686 If INSN is an insn, it is the insn containing X. If we replace a REG
2687 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2688 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2689 the REG is being modified.
2691 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2692 That's used when we eliminate in expressions stored in notes.
2693 This means, do not set ref_outside_mem even if the reference
2696 If we see a modification to a register we know about, take the
2697 appropriate action (see case SET, below).
2699 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2700 replacements done assuming all offsets are at their initial values. If
2701 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2702 encounter, return the actual location so that find_reloads will do
2703 the proper thing. */
2706 eliminate_regs (x, mem_mode, insn)
2708 enum machine_mode mem_mode;
2711 enum rtx_code code = GET_CODE (x);
2712 struct elim_table *ep;
2719 if (! current_function_decl)
2738 /* This is only for the benefit of the debugging backends, which call
2739 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2740 removed after CSE. */
2741 new = eliminate_regs (XEXP (x, 0), 0, insn);
2742 if (GET_CODE (new) == MEM)
2743 return XEXP (new, 0);
2749 /* First handle the case where we encounter a bare register that
2750 is eliminable. Replace it with a PLUS. */
2751 if (regno < FIRST_PSEUDO_REGISTER)
2753 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2755 if (ep->from_rtx == x && ep->can_eliminate)
2758 /* Refs inside notes don't count for this purpose. */
2759 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2760 || GET_CODE (insn) == INSN_LIST)))
2761 ep->ref_outside_mem = 1;
2762 return plus_constant (ep->to_rtx, ep->previous_offset);
2766 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2767 && reg_equiv_constant[regno]
2768 && ! CONSTANT_P (reg_equiv_constant[regno]))
2769 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2774 /* If this is the sum of an eliminable register and a constant, rework
2776 if (GET_CODE (XEXP (x, 0)) == REG
2777 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2778 && CONSTANT_P (XEXP (x, 1)))
2780 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2782 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2785 /* Refs inside notes don't count for this purpose. */
2786 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2787 || GET_CODE (insn) == INSN_LIST)))
2788 ep->ref_outside_mem = 1;
2790 /* The only time we want to replace a PLUS with a REG (this
2791 occurs when the constant operand of the PLUS is the negative
2792 of the offset) is when we are inside a MEM. We won't want
2793 to do so at other times because that would change the
2794 structure of the insn in a way that reload can't handle.
2795 We special-case the commonest situation in
2796 eliminate_regs_in_insn, so just replace a PLUS with a
2797 PLUS here, unless inside a MEM. */
2798 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2799 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2802 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2803 plus_constant (XEXP (x, 1),
2804 ep->previous_offset));
2807 /* If the register is not eliminable, we are done since the other
2808 operand is a constant. */
2812 /* If this is part of an address, we want to bring any constant to the
2813 outermost PLUS. We will do this by doing register replacement in
2814 our operands and seeing if a constant shows up in one of them.
2816 We assume here this is part of an address (or a "load address" insn)
2817 since an eliminable register is not likely to appear in any other
2820 If we have (plus (eliminable) (reg)), we want to produce
2821 (plus (plus (replacement) (reg) (const))). If this was part of a
2822 normal add insn, (plus (replacement) (reg)) will be pushed as a
2823 reload. This is the desired action. */
2826 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2827 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2829 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2831 /* If one side is a PLUS and the other side is a pseudo that
2832 didn't get a hard register but has a reg_equiv_constant,
2833 we must replace the constant here since it may no longer
2834 be in the position of any operand. */
2835 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2836 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2837 && reg_renumber[REGNO (new1)] < 0
2838 && reg_equiv_constant != 0
2839 && reg_equiv_constant[REGNO (new1)] != 0)
2840 new1 = reg_equiv_constant[REGNO (new1)];
2841 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2842 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2843 && reg_renumber[REGNO (new0)] < 0
2844 && reg_equiv_constant[REGNO (new0)] != 0)
2845 new0 = reg_equiv_constant[REGNO (new0)];
2847 new = form_sum (new0, new1);
2849 /* As above, if we are not inside a MEM we do not want to
2850 turn a PLUS into something else. We might try to do so here
2851 for an addition of 0 if we aren't optimizing. */
2852 if (! mem_mode && GET_CODE (new) != PLUS)
2853 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2861 /* If this is the product of an eliminable register and a
2862 constant, apply the distribute law and move the constant out
2863 so that we have (plus (mult ..) ..). This is needed in order
2864 to keep load-address insns valid. This case is pathological.
2865 We ignore the possibility of overflow here. */
2866 if (GET_CODE (XEXP (x, 0)) == REG
2867 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2868 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2869 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2871 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2874 /* Refs inside notes don't count for this purpose. */
2875 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2876 || GET_CODE (insn) == INSN_LIST)))
2877 ep->ref_outside_mem = 1;
2880 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2881 ep->previous_offset * INTVAL (XEXP (x, 1)));
2884 /* ... fall through ... */
2889 case DIV: case UDIV:
2890 case MOD: case UMOD:
2891 case AND: case IOR: case XOR:
2892 case ROTATERT: case ROTATE:
2893 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2895 case GE: case GT: case GEU: case GTU:
2896 case LE: case LT: case LEU: case LTU:
2898 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2900 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2902 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2903 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2908 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2911 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2912 if (new != XEXP (x, 0))
2914 /* If this is a REG_DEAD note, it is not valid anymore.
2915 Using the eliminated version could result in creating a
2916 REG_DEAD note for the stack or frame pointer. */
2917 if (GET_MODE (x) == REG_DEAD)
2919 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2922 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2926 /* ... fall through ... */
2929 /* Now do eliminations in the rest of the chain. If this was
2930 an EXPR_LIST, this might result in allocating more memory than is
2931 strictly needed, but it simplifies the code. */
2934 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2935 if (new != XEXP (x, 1))
2936 return gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2944 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2945 if (ep->to_rtx == XEXP (x, 0))
2947 int size = GET_MODE_SIZE (mem_mode);
2949 /* If more bytes than MEM_MODE are pushed, account for them. */
2950 #ifdef PUSH_ROUNDING
2951 if (ep->to_rtx == stack_pointer_rtx)
2952 size = PUSH_ROUNDING (size);
2954 if (code == PRE_DEC || code == POST_DEC)
2960 /* Fall through to generic unary operation case. */
2961 case STRICT_LOW_PART:
2963 case SIGN_EXTEND: case ZERO_EXTEND:
2964 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2965 case FLOAT: case FIX:
2966 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2970 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2971 if (new != XEXP (x, 0))
2972 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2976 /* Similar to above processing, but preserve SUBREG_WORD.
2977 Convert (subreg (mem)) to (mem) if not paradoxical.
2978 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2979 pseudo didn't get a hard reg, we must replace this with the
2980 eliminated version of the memory location because push_reloads
2981 may do the replacement in certain circumstances. */
2982 if (GET_CODE (SUBREG_REG (x)) == REG
2983 && (GET_MODE_SIZE (GET_MODE (x))
2984 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2985 && reg_equiv_memory_loc != 0
2986 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2989 new = eliminate_regs (reg_equiv_memory_loc[REGNO (SUBREG_REG (x))],
2992 /* If we didn't change anything, we must retain the pseudo. */
2993 if (new == reg_equiv_memory_loc[REGNO (SUBREG_REG (x))])
2994 new = SUBREG_REG (x);
2997 /* In this case, we must show that the pseudo is used in this
2998 insn so that delete_output_reload will do the right thing. */
2999 if (insn != 0 && GET_CODE (insn) != EXPR_LIST
3000 && GET_CODE (insn) != INSN_LIST)
3001 REG_NOTES (emit_insn_before (gen_rtx_USE (VOIDmode,
3004 = gen_rtx_EXPR_LIST (REG_EQUAL, new, NULL_RTX);
3006 /* Ensure NEW isn't shared in case we have to reload it. */
3007 new = copy_rtx (new);
3010 new = SUBREG_REG (x);
3014 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
3016 if (new != XEXP (x, 0))
3018 int x_size = GET_MODE_SIZE (GET_MODE (x));
3019 int new_size = GET_MODE_SIZE (GET_MODE (new));
3021 if (GET_CODE (new) == MEM
3022 && ((x_size < new_size
3023 #ifdef WORD_REGISTER_OPERATIONS
3024 /* On these machines, combine can create rtl of the form
3025 (set (subreg:m1 (reg:m2 R) 0) ...)
3026 where m1 < m2, and expects something interesting to
3027 happen to the entire word. Moreover, it will use the
3028 (reg:m2 R) later, expecting all bits to be preserved.
3029 So if the number of words is the same, preserve the
3030 subreg so that push_reloads can see it. */
3031 && ! ((x_size-1)/UNITS_PER_WORD == (new_size-1)/UNITS_PER_WORD)
3034 || (x_size == new_size))
3037 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
3038 enum machine_mode mode = GET_MODE (x);
3040 if (BYTES_BIG_ENDIAN)
3041 offset += (MIN (UNITS_PER_WORD,
3042 GET_MODE_SIZE (GET_MODE (new)))
3043 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
3045 PUT_MODE (new, mode);
3046 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
3050 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_WORD (x));
3056 /* If using a register that is the source of an eliminate we still
3057 think can be performed, note it cannot be performed since we don't
3058 know how this register is used. */
3059 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3060 if (ep->from_rtx == XEXP (x, 0))
3061 ep->can_eliminate = 0;
3063 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
3064 if (new != XEXP (x, 0))
3065 return gen_rtx_fmt_e (code, GET_MODE (x), new);
3069 /* If clobbering a register that is the replacement register for an
3070 elimination we still think can be performed, note that it cannot
3071 be performed. Otherwise, we need not be concerned about it. */
3072 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3073 if (ep->to_rtx == XEXP (x, 0))
3074 ep->can_eliminate = 0;
3076 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
3077 if (new != XEXP (x, 0))
3078 return gen_rtx_fmt_e (code, GET_MODE (x), new);
3084 /* Properly handle sharing input and constraint vectors. */
3085 if (ASM_OPERANDS_INPUT_VEC (x) != old_asm_operands_vec)
3087 /* When we come to a new vector not seen before,
3088 scan all its elements; keep the old vector if none
3089 of them changes; otherwise, make a copy. */
3090 old_asm_operands_vec = ASM_OPERANDS_INPUT_VEC (x);
3091 temp_vec = (rtx *) alloca (XVECLEN (x, 3) * sizeof (rtx));
3092 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
3093 temp_vec[i] = eliminate_regs (ASM_OPERANDS_INPUT (x, i),
3096 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
3097 if (temp_vec[i] != ASM_OPERANDS_INPUT (x, i))
3100 if (i == ASM_OPERANDS_INPUT_LENGTH (x))
3101 new_asm_operands_vec = old_asm_operands_vec;
3103 new_asm_operands_vec
3104 = gen_rtvec_v (ASM_OPERANDS_INPUT_LENGTH (x), temp_vec);
3107 /* If we had to copy the vector, copy the entire ASM_OPERANDS. */
3108 if (new_asm_operands_vec == old_asm_operands_vec)
3111 new = gen_rtx_ASM_OPERANDS (VOIDmode, ASM_OPERANDS_TEMPLATE (x),
3112 ASM_OPERANDS_OUTPUT_CONSTRAINT (x),
3113 ASM_OPERANDS_OUTPUT_IDX (x),
3114 new_asm_operands_vec,
3115 ASM_OPERANDS_INPUT_CONSTRAINT_VEC (x),
3116 ASM_OPERANDS_SOURCE_FILE (x),
3117 ASM_OPERANDS_SOURCE_LINE (x));
3118 new->volatil = x->volatil;
3123 /* Check for setting a register that we know about. */
3124 if (GET_CODE (SET_DEST (x)) == REG)
3126 /* See if this is setting the replacement register for an
3129 If DEST is the hard frame pointer, we do nothing because we
3130 assume that all assignments to the frame pointer are for
3131 non-local gotos and are being done at a time when they are valid
3132 and do not disturb anything else. Some machines want to
3133 eliminate a fake argument pointer (or even a fake frame pointer)
3134 with either the real frame or the stack pointer. Assignments to
3135 the hard frame pointer must not prevent this elimination. */
3137 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3139 if (ep->to_rtx == SET_DEST (x)
3140 && SET_DEST (x) != hard_frame_pointer_rtx)
3142 /* If it is being incremented, adjust the offset. Otherwise,
3143 this elimination can't be done. */
3144 rtx src = SET_SRC (x);
3146 if (GET_CODE (src) == PLUS
3147 && XEXP (src, 0) == SET_DEST (x)
3148 && GET_CODE (XEXP (src, 1)) == CONST_INT)
3149 ep->offset -= INTVAL (XEXP (src, 1));
3151 ep->can_eliminate = 0;
3154 /* Now check to see we are assigning to a register that can be
3155 eliminated. If so, it must be as part of a PARALLEL, since we
3156 will not have been called if this is a single SET. So indicate
3157 that we can no longer eliminate this reg. */
3158 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3160 if (ep->from_rtx == SET_DEST (x) && ep->can_eliminate)
3161 ep->can_eliminate = 0;
3164 /* Now avoid the loop below in this common case. */
3166 rtx new0 = eliminate_regs (SET_DEST (x), 0, insn);
3167 rtx new1 = eliminate_regs (SET_SRC (x), 0, insn);
3169 /* If SET_DEST changed from a REG to a MEM and INSN is an insn,
3170 write a CLOBBER insn. */
3171 if (GET_CODE (SET_DEST (x)) == REG && GET_CODE (new0) == MEM
3172 && insn != 0 && GET_CODE (insn) != EXPR_LIST
3173 && GET_CODE (insn) != INSN_LIST)
3174 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, SET_DEST (x)), insn);
3176 if (new0 != SET_DEST (x) || new1 != SET_SRC (x))
3177 return gen_rtx_SET (VOIDmode, new0, new1);
3183 /* This is only for the benefit of the debugging backends, which call
3184 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
3185 removed after CSE. */
3186 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
3187 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
3189 /* Our only special processing is to pass the mode of the MEM to our
3190 recursive call and copy the flags. While we are here, handle this
3191 case more efficiently. */
3192 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), insn);
3193 if (new != XEXP (x, 0))
3195 new = gen_rtx_MEM (GET_MODE (x), new);
3196 new->volatil = x->volatil;
3197 new->unchanging = x->unchanging;
3198 new->in_struct = x->in_struct;
3208 /* Process each of our operands recursively. If any have changed, make a
3210 fmt = GET_RTX_FORMAT (code);
3211 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3215 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
3216 if (new != XEXP (x, i) && ! copied)
3218 rtx new_x = rtx_alloc (code);
3219 bcopy ((char *) x, (char *) new_x,
3220 (sizeof (*new_x) - sizeof (new_x->fld)
3221 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
3227 else if (*fmt == 'E')
3230 for (j = 0; j < XVECLEN (x, i); j++)
3232 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
3233 if (new != XVECEXP (x, i, j) && ! copied_vec)
3235 rtvec new_v = gen_rtvec_vv (XVECLEN (x, i),
3239 rtx new_x = rtx_alloc (code);
3240 bcopy ((char *) x, (char *) new_x,
3241 (sizeof (*new_x) - sizeof (new_x->fld)
3242 + (sizeof (new_x->fld[0])
3243 * GET_RTX_LENGTH (code))));
3247 XVEC (x, i) = new_v;
3250 XVECEXP (x, i, j) = new;
3258 /* Scan INSN and eliminate all eliminable registers in it.
3260 If REPLACE is nonzero, do the replacement destructively. Also
3261 delete the insn as dead it if it is setting an eliminable register.
3263 If REPLACE is zero, do all our allocations in reload_obstack.
3265 If no eliminations were done and this insn doesn't require any elimination
3266 processing (these are not identical conditions: it might be updating sp,
3267 but not referencing fp; this needs to be seen during reload_as_needed so
3268 that the offset between fp and sp can be taken into consideration), zero
3269 is returned. Otherwise, 1 is returned. */
3272 eliminate_regs_in_insn (insn, replace)
3276 rtx old_body = PATTERN (insn);
3277 rtx old_set = single_set (insn);
3280 struct elim_table *ep;
3283 push_obstacks (&reload_obstack, &reload_obstack);
3285 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
3286 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3288 /* Check for setting an eliminable register. */
3289 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3290 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3292 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3293 /* If this is setting the frame pointer register to the
3294 hardware frame pointer register and this is an elimination
3295 that will be done (tested above), this insn is really
3296 adjusting the frame pointer downward to compensate for
3297 the adjustment done before a nonlocal goto. */
3298 if (ep->from == FRAME_POINTER_REGNUM
3299 && ep->to == HARD_FRAME_POINTER_REGNUM)
3301 rtx src = SET_SRC (old_set);
3302 int offset = 0, ok = 0;
3303 rtx prev_insn, prev_set;
3305 if (src == ep->to_rtx)
3307 else if (GET_CODE (src) == PLUS
3308 && GET_CODE (XEXP (src, 0)) == CONST_INT
3309 && XEXP (src, 1) == ep->to_rtx)
3310 offset = INTVAL (XEXP (src, 0)), ok = 1;
3311 else if (GET_CODE (src) == PLUS
3312 && GET_CODE (XEXP (src, 1)) == CONST_INT
3313 && XEXP (src, 0) == ep->to_rtx)
3314 offset = INTVAL (XEXP (src, 1)), ok = 1;
3315 else if ((prev_insn = prev_nonnote_insn (insn)) != 0
3316 && (prev_set = single_set (prev_insn)) != 0
3317 && rtx_equal_p (SET_DEST (prev_set), src))
3319 src = SET_SRC (prev_set);
3320 if (src == ep->to_rtx)
3322 else if (GET_CODE (src) == PLUS
3323 && GET_CODE (XEXP (src, 0)) == CONST_INT
3324 && XEXP (src, 1) == ep->to_rtx)
3325 offset = INTVAL (XEXP (src, 0)), ok = 1;
3326 else if (GET_CODE (src) == PLUS
3327 && GET_CODE (XEXP (src, 1)) == CONST_INT
3328 && XEXP (src, 0) == ep->to_rtx)
3329 offset = INTVAL (XEXP (src, 1)), ok = 1;
3337 = plus_constant (ep->to_rtx, offset - ep->offset);
3339 /* First see if this insn remains valid when we
3340 make the change. If not, keep the INSN_CODE
3341 the same and let reload fit it up. */
3342 validate_change (insn, &SET_SRC (old_set), src, 1);
3343 validate_change (insn, &SET_DEST (old_set),
3345 if (! apply_change_group ())
3347 SET_SRC (old_set) = src;
3348 SET_DEST (old_set) = ep->to_rtx;
3358 /* In this case this insn isn't serving a useful purpose. We
3359 will delete it in reload_as_needed once we know that this
3360 elimination is, in fact, being done.
3362 If REPLACE isn't set, we can't delete this insn, but needn't
3363 process it since it won't be used unless something changes. */
3365 delete_dead_insn (insn);
3370 /* Check for (set (reg) (plus (reg from) (offset))) where the offset
3371 in the insn is the negative of the offset in FROM. Substitute
3372 (set (reg) (reg to)) for the insn and change its code.
3374 We have to do this here, rather than in eliminate_regs, so that we can
3375 change the insn code. */
3377 if (GET_CODE (SET_SRC (old_set)) == PLUS
3378 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
3379 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT)
3380 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3382 if (ep->from_rtx == XEXP (SET_SRC (old_set), 0)
3383 && ep->can_eliminate)
3385 /* We must stop at the first elimination that will be used.
3386 If this one would replace the PLUS with a REG, do it
3387 now. Otherwise, quit the loop and let eliminate_regs
3388 do its normal replacement. */
3389 if (ep->offset == - INTVAL (XEXP (SET_SRC (old_set), 1)))
3391 /* We assume here that we don't need a PARALLEL of
3392 any CLOBBERs for this assignment. There's not
3393 much we can do if we do need it. */
3394 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3397 INSN_CODE (insn) = -1;
3406 old_asm_operands_vec = 0;
3408 /* Replace the body of this insn with a substituted form. If we changed
3409 something, return non-zero.
3411 If we are replacing a body that was a (set X (plus Y Z)), try to
3412 re-recognize the insn. We do this in case we had a simple addition
3413 but now can do this as a load-address. This saves an insn in this
3416 new_body = eliminate_regs (old_body, 0, replace ? insn : NULL_RTX);
3417 if (new_body != old_body)
3419 /* If we aren't replacing things permanently and we changed something,
3420 make another copy to ensure that all the RTL is new. Otherwise
3421 things can go wrong if find_reload swaps commutative operands
3422 and one is inside RTL that has been copied while the other is not. */
3424 /* Don't copy an asm_operands because (1) there's no need and (2)
3425 copy_rtx can't do it properly when there are multiple outputs. */
3426 if (! replace && asm_noperands (old_body) < 0)
3427 new_body = copy_rtx (new_body);
3429 /* If we had a move insn but now we don't, rerecognize it. This will
3430 cause spurious re-recognition if the old move had a PARALLEL since
3431 the new one still will, but we can't call single_set without
3432 having put NEW_BODY into the insn and the re-recognition won't
3433 hurt in this rare case. */
3435 && ((GET_CODE (SET_SRC (old_set)) == REG
3436 && (GET_CODE (new_body) != SET
3437 || GET_CODE (SET_SRC (new_body)) != REG))
3438 /* If this was a load from or store to memory, compare
3439 the MEM in recog_operand to the one in the insn. If they
3440 are not equal, then rerecognize the insn. */
3442 && ((GET_CODE (SET_SRC (old_set)) == MEM
3443 && SET_SRC (old_set) != recog_operand[1])
3444 || (GET_CODE (SET_DEST (old_set)) == MEM
3445 && SET_DEST (old_set) != recog_operand[0])))
3446 /* If this was an add insn before, rerecognize. */
3447 || GET_CODE (SET_SRC (old_set)) == PLUS))
3449 if (! validate_change (insn, &PATTERN (insn), new_body, 0))
3450 /* If recognition fails, store the new body anyway.
3451 It's normal to have recognition failures here
3452 due to bizarre memory addresses; reloading will fix them. */
3453 PATTERN (insn) = new_body;
3456 PATTERN (insn) = new_body;
3461 /* Loop through all elimination pairs. See if any have changed.
3463 We also detect a cases where register elimination cannot be done,
3464 namely, if a register would be both changed and referenced outside a MEM
3465 in the resulting insn since such an insn is often undefined and, even if
3466 not, we cannot know what meaning will be given to it. Note that it is
3467 valid to have a register used in an address in an insn that changes it
3468 (presumably with a pre- or post-increment or decrement).
3470 If anything changes, return nonzero. */
3472 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3474 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3475 ep->can_eliminate = 0;
3477 ep->ref_outside_mem = 0;
3479 if (ep->previous_offset != ep->offset)
3484 /* If we changed something, perform elimination in REG_NOTES. This is
3485 needed even when REPLACE is zero because a REG_DEAD note might refer
3486 to a register that we eliminate and could cause a different number
3487 of spill registers to be needed in the final reload pass than in
3489 if (val && REG_NOTES (insn) != 0)
3490 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3498 /* Loop through all elimination pairs.
3499 Recalculate the number not at initial offset.
3501 Compute the maximum offset (minimum offset if the stack does not
3502 grow downward) for each elimination pair. */
3505 update_eliminable_offsets ()
3507 struct elim_table *ep;
3509 num_not_at_initial_offset = 0;
3510 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3512 ep->previous_offset = ep->offset;
3513 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3514 num_not_at_initial_offset++;
3518 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3519 replacement we currently believe is valid, mark it as not eliminable if X
3520 modifies DEST in any way other than by adding a constant integer to it.
3522 If DEST is the frame pointer, we do nothing because we assume that
3523 all assignments to the hard frame pointer are nonlocal gotos and are being
3524 done at a time when they are valid and do not disturb anything else.
3525 Some machines want to eliminate a fake argument pointer with either the
3526 frame or stack pointer. Assignments to the hard frame pointer must not
3527 prevent this elimination.
3529 Called via note_stores from reload before starting its passes to scan
3530 the insns of the function. */
3533 mark_not_eliminable (dest, x)
3537 register unsigned int i;
3539 /* A SUBREG of a hard register here is just changing its mode. We should
3540 not see a SUBREG of an eliminable hard register, but check just in
3542 if (GET_CODE (dest) == SUBREG)
3543 dest = SUBREG_REG (dest);
3545 if (dest == hard_frame_pointer_rtx)
3548 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3549 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3550 && (GET_CODE (x) != SET
3551 || GET_CODE (SET_SRC (x)) != PLUS
3552 || XEXP (SET_SRC (x), 0) != dest
3553 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3555 reg_eliminate[i].can_eliminate_previous
3556 = reg_eliminate[i].can_eliminate = 0;
3561 /* Verify that the initial elimination offsets did not change since the
3562 last call to set_initial_elim_offsets. This is used to catch cases
3563 where something illegal happened during reload_as_needed that could
3564 cause incorrect code to be generated if we did not check for it. */
3566 verify_initial_elim_offsets ()
3570 #ifdef ELIMINABLE_REGS
3571 struct elim_table *ep;
3573 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3575 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3576 if (t != ep->initial_offset)
3580 INITIAL_FRAME_POINTER_OFFSET (t);
3581 if (t != reg_eliminate[0].initial_offset)
3586 /* Reset all offsets on eliminable registers to their initial values. */
3588 set_initial_elim_offsets ()
3590 struct elim_table *ep = reg_eliminate;
3592 #ifdef ELIMINABLE_REGS
3593 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3595 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3596 ep->previous_offset = ep->offset = ep->initial_offset;
3599 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3600 ep->previous_offset = ep->offset = ep->initial_offset;
3603 num_not_at_initial_offset = 0;
3606 /* Initialize the known label offsets.
3607 Set a known offset for each forced label to be at the initial offset
3608 of each elimination. We do this because we assume that all
3609 computed jumps occur from a location where each elimination is
3610 at its initial offset.
3611 For all other labels, show that we don't know the offsets. */
3614 set_initial_label_offsets ()
3617 bzero ((char *) &offsets_known_at[get_first_label_num ()], num_labels);
3619 for (x = forced_labels; x; x = XEXP (x, 1))
3621 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3624 /* Set all elimination offsets to the known values for the code label given
3627 set_offsets_for_label (insn)
3631 int label_nr = CODE_LABEL_NUMBER (insn);
3632 struct elim_table *ep;
3634 num_not_at_initial_offset = 0;
3635 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3637 ep->offset = ep->previous_offset = offsets_at[label_nr][i];
3638 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3639 num_not_at_initial_offset++;
3643 /* See if anything that happened changes which eliminations are valid.
3644 For example, on the Sparc, whether or not the frame pointer can
3645 be eliminated can depend on what registers have been used. We need
3646 not check some conditions again (such as flag_omit_frame_pointer)
3647 since they can't have changed. */
3650 update_eliminables (pset)
3653 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3654 int previous_frame_pointer_needed = frame_pointer_needed;
3656 struct elim_table *ep;
3658 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3659 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3660 #ifdef ELIMINABLE_REGS
3661 || ! CAN_ELIMINATE (ep->from, ep->to)
3664 ep->can_eliminate = 0;
3666 /* Look for the case where we have discovered that we can't replace
3667 register A with register B and that means that we will now be
3668 trying to replace register A with register C. This means we can
3669 no longer replace register C with register B and we need to disable
3670 such an elimination, if it exists. This occurs often with A == ap,
3671 B == sp, and C == fp. */
3673 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3675 struct elim_table *op;
3676 register int new_to = -1;
3678 if (! ep->can_eliminate && ep->can_eliminate_previous)
3680 /* Find the current elimination for ep->from, if there is a
3682 for (op = reg_eliminate;
3683 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3684 if (op->from == ep->from && op->can_eliminate)
3690 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3692 for (op = reg_eliminate;
3693 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3694 if (op->from == new_to && op->to == ep->to)
3695 op->can_eliminate = 0;
3699 /* See if any registers that we thought we could eliminate the previous
3700 time are no longer eliminable. If so, something has changed and we
3701 must spill the register. Also, recompute the number of eliminable
3702 registers and see if the frame pointer is needed; it is if there is
3703 no elimination of the frame pointer that we can perform. */
3705 frame_pointer_needed = 1;
3706 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3708 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3709 && ep->to != HARD_FRAME_POINTER_REGNUM)
3710 frame_pointer_needed = 0;
3712 if (! ep->can_eliminate && ep->can_eliminate_previous)
3714 ep->can_eliminate_previous = 0;
3715 SET_HARD_REG_BIT (*pset, ep->from);
3720 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3721 /* If we didn't need a frame pointer last time, but we do now, spill
3722 the hard frame pointer. */
3723 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3724 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3728 /* Initialize the table of registers to eliminate. */
3732 struct elim_table *ep;
3733 #ifdef ELIMINABLE_REGS
3734 struct elim_table_1 *ep1;
3739 reg_eliminate = (struct elim_table *)
3740 xmalloc(sizeof(struct elim_table) * NUM_ELIMINABLE_REGS);
3741 bzero ((PTR) reg_eliminate,
3742 sizeof(struct elim_table) * NUM_ELIMINABLE_REGS);
3745 /* Does this function require a frame pointer? */
3747 frame_pointer_needed = (! flag_omit_frame_pointer
3748 #ifdef EXIT_IGNORE_STACK
3749 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3750 and restore sp for alloca. So we can't eliminate
3751 the frame pointer in that case. At some point,
3752 we should improve this by emitting the
3753 sp-adjusting insns for this case. */
3754 || (current_function_calls_alloca
3755 && EXIT_IGNORE_STACK)
3757 || FRAME_POINTER_REQUIRED);
3761 #ifdef ELIMINABLE_REGS
3762 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3763 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3765 ep->from = ep1->from;
3767 ep->can_eliminate = ep->can_eliminate_previous
3768 = (CAN_ELIMINATE (ep->from, ep->to)
3769 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3772 reg_eliminate[0].from = reg_eliminate_1[0].from;
3773 reg_eliminate[0].to = reg_eliminate_1[0].to;
3774 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3775 = ! frame_pointer_needed;
3778 /* Count the number of eliminable registers and build the FROM and TO
3779 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3780 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3781 We depend on this. */
3782 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3784 num_eliminable += ep->can_eliminate;
3785 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3786 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3790 /* Kick all pseudos out of hard register REGNO.
3791 If DUMPFILE is nonzero, log actions taken on that file.
3793 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3794 because we found we can't eliminate some register. In the case, no pseudos
3795 are allowed to be in the register, even if they are only in a block that
3796 doesn't require spill registers, unlike the case when we are spilling this
3797 hard reg to produce another spill register.
3799 Return nonzero if any pseudos needed to be kicked out. */
3802 spill_hard_reg (regno, dumpfile, cant_eliminate)
3811 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3812 regs_ever_live[regno] = 1;
3815 /* Spill every pseudo reg that was allocated to this reg
3816 or to something that overlaps this reg. */
3818 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3819 if (reg_renumber[i] >= 0
3820 && reg_renumber[i] <= regno
3822 + HARD_REGNO_NREGS (reg_renumber[i],
3823 PSEUDO_REGNO_MODE (i))
3825 SET_REGNO_REG_SET (spilled_pseudos, i);
3828 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3829 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3831 ior_hard_reg_set (set1, set2)
3832 HARD_REG_SET *set1, *set2;
3834 IOR_HARD_REG_SET (*set1, *set2);
3837 /* After find_reload_regs has been run for all insn that need reloads,
3838 and/or spill_hard_regs was called, this function is used to actually
3839 spill pseudo registers and try to reallocate them. It also sets up the
3840 spill_regs array for use by choose_reload_regs. */
3843 finish_spills (global, dumpfile)
3847 struct insn_chain *chain;
3848 int something_changed = 0;
3851 /* Build the spill_regs array for the function. */
3852 /* If there are some registers still to eliminate and one of the spill regs
3853 wasn't ever used before, additional stack space may have to be
3854 allocated to store this register. Thus, we may have changed the offset
3855 between the stack and frame pointers, so mark that something has changed.
3857 One might think that we need only set VAL to 1 if this is a call-used
3858 register. However, the set of registers that must be saved by the
3859 prologue is not identical to the call-used set. For example, the
3860 register used by the call insn for the return PC is a call-used register,
3861 but must be saved by the prologue. */
3864 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3865 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3867 spill_reg_order[i] = n_spills;
3868 spill_regs[n_spills++] = i;
3869 if (num_eliminable && ! regs_ever_live[i])
3870 something_changed = 1;
3871 regs_ever_live[i] = 1;
3874 spill_reg_order[i] = -1;
3876 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3877 if (REGNO_REG_SET_P (spilled_pseudos, i))
3879 /* Record the current hard register the pseudo is allocated to in
3880 pseudo_previous_regs so we avoid reallocating it to the same
3881 hard reg in a later pass. */
3882 if (reg_renumber[i] < 0)
3884 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3885 /* Mark it as no longer having a hard register home. */
3886 reg_renumber[i] = -1;
3887 /* We will need to scan everything again. */
3888 something_changed = 1;
3891 /* Retry global register allocation if possible. */
3894 bzero ((char *) pseudo_forbidden_regs, max_regno * sizeof (HARD_REG_SET));
3895 /* For every insn that needs reloads, set the registers used as spill
3896 regs in pseudo_forbidden_regs for every pseudo live across the
3898 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3900 EXECUTE_IF_SET_IN_REG_SET
3901 (chain->live_before, FIRST_PSEUDO_REGISTER, i,
3903 ior_hard_reg_set (pseudo_forbidden_regs + i,
3904 &chain->used_spill_regs);
3906 EXECUTE_IF_SET_IN_REG_SET
3907 (chain->live_after, FIRST_PSEUDO_REGISTER, i,
3909 ior_hard_reg_set (pseudo_forbidden_regs + i,
3910 &chain->used_spill_regs);
3914 /* Retry allocating the spilled pseudos. For each reg, merge the
3915 various reg sets that indicate which hard regs can't be used,
3916 and call retry_global_alloc.
3917 We change spill_pseudos here to only contain pseudos that did not
3918 get a new hard register. */
3919 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3920 if (reg_old_renumber[i] != reg_renumber[i])
3922 HARD_REG_SET forbidden;
3923 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3924 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3925 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3926 retry_global_alloc (i, forbidden);
3927 if (reg_renumber[i] >= 0)
3928 CLEAR_REGNO_REG_SET (spilled_pseudos, i);
3932 /* Fix up the register information in the insn chain.
3933 This involves deleting those of the spilled pseudos which did not get
3934 a new hard register home from the live_{before,after} sets. */
3935 for (chain = reload_insn_chain; chain; chain = chain->next)
3937 HARD_REG_SET used_by_pseudos;
3938 HARD_REG_SET used_by_pseudos2;
3940 AND_COMPL_REG_SET (chain->live_before, spilled_pseudos);
3941 AND_COMPL_REG_SET (chain->live_after, spilled_pseudos);
3943 /* Mark any unallocated hard regs as available for spills. That
3944 makes inheritance work somewhat better. */
3945 if (chain->need_reload)
3947 REG_SET_TO_HARD_REG_SET (used_by_pseudos, chain->live_before);
3948 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, chain->live_after);
3949 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3951 /* Save the old value for the sanity test below. */
3952 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3954 compute_use_by_pseudos (&used_by_pseudos, chain->live_before);
3955 compute_use_by_pseudos (&used_by_pseudos, chain->live_after);
3956 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3957 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3959 /* Make sure we only enlarge the set. */
3960 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3966 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3967 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3969 int regno = reg_renumber[i];
3970 if (reg_old_renumber[i] == regno)
3973 alter_reg (i, reg_old_renumber[i]);
3974 reg_old_renumber[i] = regno;
3978 fprintf (dumpfile, " Register %d now on stack.\n\n", i);
3980 fprintf (dumpfile, " Register %d now in %d.\n\n",
3981 i, reg_renumber[i]);
3985 return something_changed;
3988 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3989 Also mark any hard registers used to store user variables as
3990 forbidden from being used for spill registers. */
3993 scan_paradoxical_subregs (x)
3998 register enum rtx_code code = GET_CODE (x);
4004 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
4005 && REG_USERVAR_P (x))
4006 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
4022 if (GET_CODE (SUBREG_REG (x)) == REG
4023 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
4024 reg_max_ref_width[REGNO (SUBREG_REG (x))]
4025 = GET_MODE_SIZE (GET_MODE (x));
4032 fmt = GET_RTX_FORMAT (code);
4033 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4036 scan_paradoxical_subregs (XEXP (x, i));
4037 else if (fmt[i] == 'E')
4040 for (j = XVECLEN (x, i) - 1; j >=0; j--)
4041 scan_paradoxical_subregs (XVECEXP (x, i, j));
4047 hard_reg_use_compare (p1p, p2p)
4048 const GENERIC_PTR p1p;
4049 const GENERIC_PTR p2p;
4051 struct hard_reg_n_uses *p1 = (struct hard_reg_n_uses *)p1p;
4052 struct hard_reg_n_uses *p2 = (struct hard_reg_n_uses *)p2p;
4053 int bad1 = TEST_HARD_REG_BIT (bad_spill_regs, p1->regno);
4054 int bad2 = TEST_HARD_REG_BIT (bad_spill_regs, p2->regno);
4056 return p1->regno - p2->regno;
4061 if (p1->uses > p2->uses)
4063 if (p1->uses < p2->uses)
4065 /* If regs are equally good, sort by regno,
4066 so that the results of qsort leave nothing to chance. */
4067 return p1->regno - p2->regno;
4070 /* Used for communication between order_regs_for_reload and count_pseudo.
4071 Used to avoid counting one pseudo twice. */
4072 static regset pseudos_counted;
4074 /* Update the costs in N_USES, considering that pseudo REG is live. */
4076 count_pseudo (n_uses, reg)
4077 struct hard_reg_n_uses *n_uses;
4080 int r = reg_renumber[reg];
4083 if (REGNO_REG_SET_P (pseudos_counted, reg))
4085 SET_REGNO_REG_SET (pseudos_counted, reg);
4090 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
4092 n_uses[r++].uses += REG_N_REFS (reg);
4094 /* Choose the order to consider regs for use as reload registers
4095 based on how much trouble would be caused by spilling one.
4096 Store them in order of decreasing preference in potential_reload_regs. */
4099 order_regs_for_reload (chain)
4100 struct insn_chain *chain;
4104 struct hard_reg_n_uses hard_reg_n_uses[FIRST_PSEUDO_REGISTER];
4106 pseudos_counted = ALLOCA_REG_SET ();
4108 COPY_HARD_REG_SET (bad_spill_regs, bad_spill_regs_global);
4110 /* Count number of uses of each hard reg by pseudo regs allocated to it
4111 and then order them by decreasing use. */
4113 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4117 hard_reg_n_uses[i].regno = i;
4118 hard_reg_n_uses[i].uses = 0;
4120 /* Test the various reasons why we can't use a register for
4121 spilling in this insn. */
4123 || REGNO_REG_SET_P (chain->live_before, i)
4124 || REGNO_REG_SET_P (chain->live_after, i))
4126 SET_HARD_REG_BIT (bad_spill_regs, i);
4130 /* Now find out which pseudos are allocated to it, and update
4132 CLEAR_REG_SET (pseudos_counted);
4134 EXECUTE_IF_SET_IN_REG_SET
4135 (chain->live_before, FIRST_PSEUDO_REGISTER, j,
4137 count_pseudo (hard_reg_n_uses, j);
4139 EXECUTE_IF_SET_IN_REG_SET
4140 (chain->live_after, FIRST_PSEUDO_REGISTER, j,
4142 count_pseudo (hard_reg_n_uses, j);
4146 FREE_REG_SET (pseudos_counted);
4148 /* Prefer registers not so far used, for use in temporary loading.
4149 Among them, if REG_ALLOC_ORDER is defined, use that order.
4150 Otherwise, prefer registers not preserved by calls. */
4152 #ifdef REG_ALLOC_ORDER
4153 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4155 int regno = reg_alloc_order[i];
4157 if (hard_reg_n_uses[regno].uses == 0
4158 && ! TEST_HARD_REG_BIT (bad_spill_regs, regno))
4159 potential_reload_regs[o++] = regno;
4162 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4164 if (hard_reg_n_uses[i].uses == 0 && call_used_regs[i]
4165 && ! TEST_HARD_REG_BIT (bad_spill_regs, i))
4166 potential_reload_regs[o++] = i;
4168 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4170 if (hard_reg_n_uses[i].uses == 0 && ! call_used_regs[i]
4171 && ! TEST_HARD_REG_BIT (bad_spill_regs, i))
4172 potential_reload_regs[o++] = i;
4176 qsort (hard_reg_n_uses, FIRST_PSEUDO_REGISTER,
4177 sizeof hard_reg_n_uses[0], hard_reg_use_compare);
4179 /* Now add the regs that are already used,
4180 preferring those used less often. The fixed and otherwise forbidden
4181 registers will be at the end of this list. */
4183 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4184 if (hard_reg_n_uses[i].uses != 0
4185 && ! TEST_HARD_REG_BIT (bad_spill_regs, hard_reg_n_uses[i].regno))
4186 potential_reload_regs[o++] = hard_reg_n_uses[i].regno;
4187 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4188 if (TEST_HARD_REG_BIT (bad_spill_regs, hard_reg_n_uses[i].regno))
4189 potential_reload_regs[o++] = hard_reg_n_uses[i].regno;
4192 /* Reload pseudo-registers into hard regs around each insn as needed.
4193 Additional register load insns are output before the insn that needs it
4194 and perhaps store insns after insns that modify the reloaded pseudo reg.
4196 reg_last_reload_reg and reg_reloaded_contents keep track of
4197 which registers are already available in reload registers.
4198 We update these for the reloads that we perform,
4199 as the insns are scanned. */
4202 reload_as_needed (live_known)
4205 struct insn_chain *chain;
4206 #if defined (AUTO_INC_DEC) || defined (INSN_CLOBBERS_REGNO_P)
4211 bzero ((char *) spill_reg_rtx, sizeof spill_reg_rtx);
4212 bzero ((char *) spill_reg_store, sizeof spill_reg_store);
4213 reg_last_reload_reg = (rtx *) alloca (max_regno * sizeof (rtx));
4214 bzero ((char *) reg_last_reload_reg, max_regno * sizeof (rtx));
4215 reg_has_output_reload = (char *) alloca (max_regno);
4216 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4218 set_initial_elim_offsets ();
4220 for (chain = reload_insn_chain; chain; chain = chain->next)
4223 rtx insn = chain->insn;
4224 rtx old_next = NEXT_INSN (insn);
4226 /* If we pass a label, copy the offsets from the label information
4227 into the current offsets of each elimination. */
4228 if (GET_CODE (insn) == CODE_LABEL)
4229 set_offsets_for_label (insn);
4231 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
4233 rtx oldpat = PATTERN (insn);
4235 /* If this is a USE and CLOBBER of a MEM, ensure that any
4236 references to eliminable registers have been removed. */
4238 if ((GET_CODE (PATTERN (insn)) == USE
4239 || GET_CODE (PATTERN (insn)) == CLOBBER)
4240 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
4241 XEXP (XEXP (PATTERN (insn), 0), 0)
4242 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4243 GET_MODE (XEXP (PATTERN (insn), 0)),
4246 /* If we need to do register elimination processing, do so.
4247 This might delete the insn, in which case we are done. */
4248 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4250 eliminate_regs_in_insn (insn, 1);
4251 if (GET_CODE (insn) == NOTE)
4253 update_eliminable_offsets ();
4258 /* If need_elim is nonzero but need_reload is zero, one might think
4259 that we could simply set n_reloads to 0. However, find_reloads
4260 could have done some manipulation of the insn (such as swapping
4261 commutative operands), and these manipulations are lost during
4262 the first pass for every insn that needs register elimination.
4263 So the actions of find_reloads must be redone here. */
4265 if (! chain->need_elim && ! chain->need_reload
4266 && ! chain->need_operand_change)
4268 /* First find the pseudo regs that must be reloaded for this insn.
4269 This info is returned in the tables reload_... (see reload.h).
4270 Also modify the body of INSN by substituting RELOAD
4271 rtx's for those pseudo regs. */
4274 bzero (reg_has_output_reload, max_regno);
4275 CLEAR_HARD_REG_SET (reg_is_output_reload);
4277 find_reloads (insn, 1, spill_indirect_levels, live_known,
4283 rtx next = NEXT_INSN (insn);
4286 prev = PREV_INSN (insn);
4288 /* Now compute which reload regs to reload them into. Perhaps
4289 reusing reload regs from previous insns, or else output
4290 load insns to reload them. Maybe output store insns too.
4291 Record the choices of reload reg in reload_reg_rtx. */
4292 choose_reload_regs (chain);
4294 /* Merge any reloads that we didn't combine for fear of
4295 increasing the number of spill registers needed but now
4296 discover can be safely merged. */
4297 if (SMALL_REGISTER_CLASSES)
4298 merge_assigned_reloads (insn);
4300 /* Generate the insns to reload operands into or out of
4301 their reload regs. */
4302 emit_reload_insns (chain);
4304 /* Substitute the chosen reload regs from reload_reg_rtx
4305 into the insn's body (or perhaps into the bodies of other
4306 load and store insn that we just made for reloading
4307 and that we moved the structure into). */
4310 /* If this was an ASM, make sure that all the reload insns
4311 we have generated are valid. If not, give an error
4314 if (asm_noperands (PATTERN (insn)) >= 0)
4315 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4316 if (p != insn && GET_RTX_CLASS (GET_CODE (p)) == 'i'
4317 && (recog_memoized (p) < 0
4318 || (extract_insn (p), ! constrain_operands (1))))
4320 error_for_asm (insn,
4321 "`asm' operand requires impossible reload");
4323 NOTE_SOURCE_FILE (p) = 0;
4324 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
4328 if (num_eliminable && chain->need_elim)
4329 update_eliminable_offsets ();
4331 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4332 is no longer validly lying around to save a future reload.
4333 Note that this does not detect pseudos that were reloaded
4334 for this insn in order to be stored in
4335 (obeying register constraints). That is correct; such reload
4336 registers ARE still valid. */
4337 note_stores (oldpat, forget_old_reloads_1);
4339 /* There may have been CLOBBER insns placed after INSN. So scan
4340 between INSN and NEXT and use them to forget old reloads. */
4341 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4342 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
4343 note_stores (PATTERN (x), forget_old_reloads_1);
4346 /* Likewise for regs altered by auto-increment in this insn.
4347 REG_INC notes have been changed by reloading:
4348 find_reloads_address_1 records substitutions for them,
4349 which have been performed by subst_reloads above. */
4350 for (i = n_reloads - 1; i >= 0; i--)
4352 rtx in_reg = reload_in_reg[i];
4355 enum rtx_code code = GET_CODE (in_reg);
4356 /* PRE_INC / PRE_DEC will have the reload register ending up
4357 with the same value as the stack slot, but that doesn't
4358 hold true for POST_INC / POST_DEC. Either we have to
4359 convert the memory access to a true POST_INC / POST_DEC,
4360 or we can't use the reload register for inheritance. */
4361 if ((code == POST_INC || code == POST_DEC)
4362 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4363 REGNO (reload_reg_rtx[i]))
4364 /* Make sure it is the inc/dec pseudo, and not
4365 some other (e.g. output operand) pseudo. */
4366 && (reg_reloaded_contents[REGNO (reload_reg_rtx[i])]
4367 == REGNO (XEXP (in_reg, 0))))
4370 rtx reload_reg = reload_reg_rtx[i];
4371 enum machine_mode mode = GET_MODE (reload_reg);
4375 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4377 /* We really want to ignore REG_INC notes here, so
4378 use PATTERN (p) as argument to reg_set_p . */
4379 if (reg_set_p (reload_reg, PATTERN (p)))
4381 n = count_occurrences (PATTERN (p), reload_reg);
4386 n = validate_replace_rtx (reload_reg,
4387 gen_rtx (code, mode,
4391 /* We must also verify that the constraints
4392 are met after the replacement. */
4395 n = constrain_operands (1);
4399 /* If the constraints were not met, then
4400 undo the replacement. */
4403 validate_replace_rtx (gen_rtx (code, mode,
4415 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4417 /* Mark this as having an output reload so that the
4418 REG_INC processing code below won't invalidate
4419 the reload for inheritance. */
4420 SET_HARD_REG_BIT (reg_is_output_reload,
4421 REGNO (reload_reg));
4422 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4425 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX);
4427 else if ((code == PRE_INC || code == PRE_DEC)
4428 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4429 REGNO (reload_reg_rtx[i]))
4430 /* Make sure it is the inc/dec pseudo, and not
4431 some other (e.g. output operand) pseudo. */
4432 && (reg_reloaded_contents[REGNO (reload_reg_rtx[i])]
4433 == REGNO (XEXP (in_reg, 0))))
4435 SET_HARD_REG_BIT (reg_is_output_reload,
4436 REGNO (reload_reg_rtx[i]));
4437 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4441 /* If a pseudo that got a hard register is auto-incremented,
4442 we must purge records of copying it into pseudos without
4444 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4445 if (REG_NOTE_KIND (x) == REG_INC)
4447 /* See if this pseudo reg was reloaded in this insn.
4448 If so, its last-reload info is still valid
4449 because it is based on this insn's reload. */
4450 for (i = 0; i < n_reloads; i++)
4451 if (reload_out[i] == XEXP (x, 0))
4455 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX);
4459 /* A reload reg's contents are unknown after a label. */
4460 if (GET_CODE (insn) == CODE_LABEL)
4461 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4463 /* Don't assume a reload reg is still good after a call insn
4464 if it is a call-used reg. */
4465 else if (GET_CODE (insn) == CALL_INSN)
4466 AND_COMPL_HARD_REG_SET(reg_reloaded_valid, call_used_reg_set);
4468 /* In case registers overlap, allow certain insns to invalidate
4469 particular hard registers. */
4471 #ifdef INSN_CLOBBERS_REGNO_P
4472 for (i = 0 ; i < FIRST_PSEUDO_REGISTER; i++)
4473 if (TEST_HARD_REG_BIT (reg_reloaded_valid, i)
4474 && INSN_CLOBBERS_REGNO_P (insn, i))
4475 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i);
4484 /* Discard all record of any value reloaded from X,
4485 or reloaded in X from someplace else;
4486 unless X is an output reload reg of the current insn.
4488 X may be a hard reg (the reload reg)
4489 or it may be a pseudo reg that was reloaded from. */
4492 forget_old_reloads_1 (x, ignored)
4494 rtx ignored ATTRIBUTE_UNUSED;
4500 /* note_stores does give us subregs of hard regs. */
4501 while (GET_CODE (x) == SUBREG)
4503 offset += SUBREG_WORD (x);
4507 if (GET_CODE (x) != REG)
4510 regno = REGNO (x) + offset;
4512 if (regno >= FIRST_PSEUDO_REGISTER)
4517 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4518 /* Storing into a spilled-reg invalidates its contents.
4519 This can happen if a block-local pseudo is allocated to that reg
4520 and it wasn't spilled because this block's total need is 0.
4521 Then some insn might have an optional reload and use this reg. */
4522 for (i = 0; i < nr; i++)
4523 /* But don't do this if the reg actually serves as an output
4524 reload reg in the current instruction. */
4526 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4528 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4529 spill_reg_store[regno + i] = 0;
4533 /* Since value of X has changed,
4534 forget any value previously copied from it. */
4537 /* But don't forget a copy if this is the output reload
4538 that establishes the copy's validity. */
4539 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4540 reg_last_reload_reg[regno + nr] = 0;
4543 /* For each reload, the mode of the reload register. */
4544 static enum machine_mode reload_mode[MAX_RELOADS];
4546 /* For each reload, the largest number of registers it will require. */
4547 static int reload_nregs[MAX_RELOADS];
4549 /* Comparison function for qsort to decide which of two reloads
4550 should be handled first. *P1 and *P2 are the reload numbers. */
4553 reload_reg_class_lower (r1p, r2p)
4554 const GENERIC_PTR r1p;
4555 const GENERIC_PTR r2p;
4557 register int r1 = *(short *)r1p, r2 = *(short *)r2p;
4560 /* Consider required reloads before optional ones. */
4561 t = reload_optional[r1] - reload_optional[r2];
4565 /* Count all solitary classes before non-solitary ones. */
4566 t = ((reg_class_size[(int) reload_reg_class[r2]] == 1)
4567 - (reg_class_size[(int) reload_reg_class[r1]] == 1));
4571 /* Aside from solitaires, consider all multi-reg groups first. */
4572 t = reload_nregs[r2] - reload_nregs[r1];
4576 /* Consider reloads in order of increasing reg-class number. */
4577 t = (int) reload_reg_class[r1] - (int) reload_reg_class[r2];
4581 /* If reloads are equally urgent, sort by reload number,
4582 so that the results of qsort leave nothing to chance. */
4586 /* The following HARD_REG_SETs indicate when each hard register is
4587 used for a reload of various parts of the current insn. */
4589 /* If reg is unavailable for all reloads. */
4590 static HARD_REG_SET reload_reg_unavailable;
4591 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4592 static HARD_REG_SET reload_reg_used;
4593 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4594 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4595 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4596 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4597 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4598 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4599 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4600 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4601 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4602 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4603 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4604 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4605 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4606 static HARD_REG_SET reload_reg_used_in_op_addr;
4607 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4608 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4609 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4610 static HARD_REG_SET reload_reg_used_in_insn;
4611 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4612 static HARD_REG_SET reload_reg_used_in_other_addr;
4614 /* If reg is in use as a reload reg for any sort of reload. */
4615 static HARD_REG_SET reload_reg_used_at_all;
4617 /* If reg is use as an inherited reload. We just mark the first register
4619 static HARD_REG_SET reload_reg_used_for_inherit;
4621 /* Records which hard regs are used in any way, either as explicit use or
4622 by being allocated to a pseudo during any point of the current insn. */
4623 static HARD_REG_SET reg_used_in_insn;
4625 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4626 TYPE. MODE is used to indicate how many consecutive regs are
4630 mark_reload_reg_in_use (regno, opnum, type, mode)
4633 enum reload_type type;
4634 enum machine_mode mode;
4636 int nregs = HARD_REGNO_NREGS (regno, mode);
4639 for (i = regno; i < nregs + regno; i++)
4644 SET_HARD_REG_BIT (reload_reg_used, i);
4647 case RELOAD_FOR_INPUT_ADDRESS:
4648 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4651 case RELOAD_FOR_INPADDR_ADDRESS:
4652 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4655 case RELOAD_FOR_OUTPUT_ADDRESS:
4656 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4659 case RELOAD_FOR_OUTADDR_ADDRESS:
4660 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4663 case RELOAD_FOR_OPERAND_ADDRESS:
4664 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4667 case RELOAD_FOR_OPADDR_ADDR:
4668 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4671 case RELOAD_FOR_OTHER_ADDRESS:
4672 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4675 case RELOAD_FOR_INPUT:
4676 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4679 case RELOAD_FOR_OUTPUT:
4680 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4683 case RELOAD_FOR_INSN:
4684 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4688 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4692 /* Similarly, but show REGNO is no longer in use for a reload. */
4695 clear_reload_reg_in_use (regno, opnum, type, mode)
4698 enum reload_type type;
4699 enum machine_mode mode;
4701 int nregs = HARD_REGNO_NREGS (regno, mode);
4702 int start_regno, end_regno;
4704 /* A complication is that for some reload types, inheritance might
4705 allow multiple reloads of the same types to share a reload register.
4706 We set check_opnum if we have to check only reloads with the same
4707 operand number, and check_any if we have to check all reloads. */
4708 int check_opnum = 0;
4710 HARD_REG_SET *used_in_set;
4715 used_in_set = &reload_reg_used;
4718 case RELOAD_FOR_INPUT_ADDRESS:
4719 used_in_set = &reload_reg_used_in_input_addr[opnum];
4722 case RELOAD_FOR_INPADDR_ADDRESS:
4724 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4727 case RELOAD_FOR_OUTPUT_ADDRESS:
4728 used_in_set = &reload_reg_used_in_output_addr[opnum];
4731 case RELOAD_FOR_OUTADDR_ADDRESS:
4733 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4736 case RELOAD_FOR_OPERAND_ADDRESS:
4737 used_in_set = &reload_reg_used_in_op_addr;
4740 case RELOAD_FOR_OPADDR_ADDR:
4742 used_in_set = &reload_reg_used_in_op_addr_reload;
4745 case RELOAD_FOR_OTHER_ADDRESS:
4746 used_in_set = &reload_reg_used_in_other_addr;
4750 case RELOAD_FOR_INPUT:
4751 used_in_set = &reload_reg_used_in_input[opnum];
4754 case RELOAD_FOR_OUTPUT:
4755 used_in_set = &reload_reg_used_in_output[opnum];
4758 case RELOAD_FOR_INSN:
4759 used_in_set = &reload_reg_used_in_insn;
4764 /* We resolve conflicts with remaining reloads of the same type by
4765 excluding the intervals of of reload registers by them from the
4766 interval of freed reload registers. Since we only keep track of
4767 one set of interval bounds, we might have to exclude somewhat
4768 more then what would be necessary if we used a HARD_REG_SET here.
4769 But this should only happen very infrequently, so there should
4770 be no reason to worry about it. */
4772 start_regno = regno;
4773 end_regno = regno + nregs;
4774 if (check_opnum || check_any)
4776 for (i = n_reloads - 1; i >= 0; i--)
4778 if (reload_when_needed[i] == type
4779 && (check_any || reload_opnum[i] == opnum)
4780 && reload_reg_rtx[i])
4782 int conflict_start = true_regnum (reload_reg_rtx[i]);
4785 + HARD_REGNO_NREGS (conflict_start, reload_mode[i]));
4787 /* If there is an overlap with the first to-be-freed register,
4788 adjust the interval start. */
4789 if (conflict_start <= start_regno && conflict_end > start_regno)
4790 start_regno = conflict_end;
4791 /* Otherwise, if there is a conflict with one of the other
4792 to-be-freed registers, adjust the interval end. */
4793 if (conflict_start > start_regno && conflict_start < end_regno)
4794 end_regno = conflict_start;
4798 for (i = start_regno; i < end_regno; i++)
4799 CLEAR_HARD_REG_BIT (*used_in_set, i);
4802 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4803 specified by OPNUM and TYPE. */
4806 reload_reg_free_p (regno, opnum, type)
4809 enum reload_type type;
4813 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4814 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4820 /* In use for anything means we can't use it for RELOAD_OTHER. */
4821 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4822 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4823 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4826 for (i = 0; i < reload_n_operands; i++)
4827 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4828 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4829 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4830 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4831 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4832 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4837 case RELOAD_FOR_INPUT:
4838 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4839 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4842 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4845 /* If it is used for some other input, can't use it. */
4846 for (i = 0; i < reload_n_operands; i++)
4847 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4850 /* If it is used in a later operand's address, can't use it. */
4851 for (i = opnum + 1; i < reload_n_operands; i++)
4852 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4853 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4858 case RELOAD_FOR_INPUT_ADDRESS:
4859 /* Can't use a register if it is used for an input address for this
4860 operand or used as an input in an earlier one. */
4861 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4862 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4865 for (i = 0; i < opnum; i++)
4866 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4871 case RELOAD_FOR_INPADDR_ADDRESS:
4872 /* Can't use a register if it is used for an input address
4873 for this operand or used as an input in an earlier
4875 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4878 for (i = 0; i < opnum; i++)
4879 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4884 case RELOAD_FOR_OUTPUT_ADDRESS:
4885 /* Can't use a register if it is used for an output address for this
4886 operand or used as an output in this or a later operand. */
4887 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4890 for (i = opnum; i < reload_n_operands; i++)
4891 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4896 case RELOAD_FOR_OUTADDR_ADDRESS:
4897 /* Can't use a register if it is used for an output address
4898 for this operand or used as an output in this or a
4900 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4903 for (i = opnum; i < reload_n_operands; i++)
4904 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4909 case RELOAD_FOR_OPERAND_ADDRESS:
4910 for (i = 0; i < reload_n_operands; i++)
4911 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4914 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4915 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4917 case RELOAD_FOR_OPADDR_ADDR:
4918 for (i = 0; i < reload_n_operands; i++)
4919 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4922 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4924 case RELOAD_FOR_OUTPUT:
4925 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4926 outputs, or an operand address for this or an earlier output. */
4927 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4930 for (i = 0; i < reload_n_operands; i++)
4931 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4934 for (i = 0; i <= opnum; i++)
4935 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4936 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4941 case RELOAD_FOR_INSN:
4942 for (i = 0; i < reload_n_operands; i++)
4943 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4944 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4947 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4948 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4950 case RELOAD_FOR_OTHER_ADDRESS:
4951 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4956 /* Return 1 if the value in reload reg REGNO, as used by a reload
4957 needed for the part of the insn specified by OPNUM and TYPE,
4958 is still available in REGNO at the end of the insn.
4960 We can assume that the reload reg was already tested for availability
4961 at the time it is needed, and we should not check this again,
4962 in case the reg has already been marked in use. */
4965 reload_reg_reaches_end_p (regno, opnum, type)
4968 enum reload_type type;
4975 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4976 its value must reach the end. */
4979 /* If this use is for part of the insn,
4980 its value reaches if no subsequent part uses the same register.
4981 Just like the above function, don't try to do this with lots
4984 case RELOAD_FOR_OTHER_ADDRESS:
4985 /* Here we check for everything else, since these don't conflict
4986 with anything else and everything comes later. */
4988 for (i = 0; i < reload_n_operands; i++)
4989 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4990 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4991 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4992 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4993 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4994 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4997 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4998 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4999 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
5001 case RELOAD_FOR_INPUT_ADDRESS:
5002 case RELOAD_FOR_INPADDR_ADDRESS:
5003 /* Similar, except that we check only for this and subsequent inputs
5004 and the address of only subsequent inputs and we do not need
5005 to check for RELOAD_OTHER objects since they are known not to
5008 for (i = opnum; i < reload_n_operands; i++)
5009 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5012 for (i = opnum + 1; i < reload_n_operands; i++)
5013 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5014 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5017 for (i = 0; i < reload_n_operands; i++)
5018 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5019 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5020 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5023 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5026 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5027 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
5029 case RELOAD_FOR_INPUT:
5030 /* Similar to input address, except we start at the next operand for
5031 both input and input address and we do not check for
5032 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5035 for (i = opnum + 1; i < reload_n_operands; i++)
5036 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5037 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5038 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5041 /* ... fall through ... */
5043 case RELOAD_FOR_OPERAND_ADDRESS:
5044 /* Check outputs and their addresses. */
5046 for (i = 0; i < reload_n_operands; i++)
5047 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5048 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5049 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5054 case RELOAD_FOR_OPADDR_ADDR:
5055 for (i = 0; i < reload_n_operands; i++)
5056 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5057 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5058 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5061 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5062 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
5064 case RELOAD_FOR_INSN:
5065 /* These conflict with other outputs with RELOAD_OTHER. So
5066 we need only check for output addresses. */
5070 /* ... fall through ... */
5072 case RELOAD_FOR_OUTPUT:
5073 case RELOAD_FOR_OUTPUT_ADDRESS:
5074 case RELOAD_FOR_OUTADDR_ADDRESS:
5075 /* We already know these can't conflict with a later output. So the
5076 only thing to check are later output addresses. */
5077 for (i = opnum + 1; i < reload_n_operands; i++)
5078 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5079 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5088 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5091 This function uses the same algorithm as reload_reg_free_p above. */
5094 reloads_conflict (r1, r2)
5097 enum reload_type r1_type = reload_when_needed[r1];
5098 enum reload_type r2_type = reload_when_needed[r2];
5099 int r1_opnum = reload_opnum[r1];
5100 int r2_opnum = reload_opnum[r2];
5102 /* RELOAD_OTHER conflicts with everything. */
5103 if (r2_type == RELOAD_OTHER)
5106 /* Otherwise, check conflicts differently for each type. */
5110 case RELOAD_FOR_INPUT:
5111 return (r2_type == RELOAD_FOR_INSN
5112 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5113 || r2_type == RELOAD_FOR_OPADDR_ADDR
5114 || r2_type == RELOAD_FOR_INPUT
5115 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5116 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5117 && r2_opnum > r1_opnum));
5119 case RELOAD_FOR_INPUT_ADDRESS:
5120 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5121 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5123 case RELOAD_FOR_INPADDR_ADDRESS:
5124 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5125 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5127 case RELOAD_FOR_OUTPUT_ADDRESS:
5128 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5129 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
5131 case RELOAD_FOR_OUTADDR_ADDRESS:
5132 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5133 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
5135 case RELOAD_FOR_OPERAND_ADDRESS:
5136 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5137 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5139 case RELOAD_FOR_OPADDR_ADDR:
5140 return (r2_type == RELOAD_FOR_INPUT
5141 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5143 case RELOAD_FOR_OUTPUT:
5144 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5145 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5146 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5147 && r2_opnum <= r1_opnum));
5149 case RELOAD_FOR_INSN:
5150 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5151 || r2_type == RELOAD_FOR_INSN
5152 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5154 case RELOAD_FOR_OTHER_ADDRESS:
5155 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5165 /* Vector of reload-numbers showing the order in which the reloads should
5167 short reload_order[MAX_RELOADS];
5169 /* Indexed by reload number, 1 if incoming value
5170 inherited from previous insns. */
5171 char reload_inherited[MAX_RELOADS];
5173 /* For an inherited reload, this is the insn the reload was inherited from,
5174 if we know it. Otherwise, this is 0. */
5175 rtx reload_inheritance_insn[MAX_RELOADS];
5177 /* If non-zero, this is a place to get the value of the reload,
5178 rather than using reload_in. */
5179 rtx reload_override_in[MAX_RELOADS];
5181 /* For each reload, the hard register number of the register used,
5182 or -1 if we did not need a register for this reload. */
5183 int reload_spill_index[MAX_RELOADS];
5185 /* Subroutine of free_for_value_p, used to check a single register. */
5188 reload_reg_free_for_value_p (regno, opnum, type, value, out, reloadnum,
5189 ignore_address_reloads)
5192 enum reload_type type;
5195 int ignore_address_reloads;
5198 /* Set if we see an input reload that must not share its reload register
5199 with any new earlyclobber, but might otherwise share the reload
5200 register with an output or input-output reload. */
5201 int check_earlyclobber = 0;
5205 /* ??? reload_reg_used is abused to hold the registers that are not
5206 available as spill registers, including hard registers that are
5207 earlyclobbered in asms. As a temporary measure, reject anything
5208 in reload_reg_used. */
5209 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5212 if (out == const0_rtx)
5218 /* We use some pseudo 'time' value to check if the lifetimes of the
5219 new register use would overlap with the one of a previous reload
5220 that is not read-only or uses a different value.
5221 The 'time' used doesn't have to be linear in any shape or form, just
5223 Some reload types use different 'buckets' for each operand.
5224 So there are MAX_RECOG_OPERANDS different time values for each
5226 We compute TIME1 as the time when the register for the prospective
5227 new reload ceases to be live, and TIME2 for each existing
5228 reload as the time when that the reload register of that reload
5230 Where there is little to be gained by exact lifetime calculations,
5231 we just make conservative assumptions, i.e. a longer lifetime;
5232 this is done in the 'default:' cases. */
5235 case RELOAD_FOR_OTHER_ADDRESS:
5236 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5237 time1 = copy ? 0 : 1;
5240 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5242 /* For each input, we might have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5243 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5244 respectively, to the time values for these, we get distinct time
5245 values. To get distinct time values for each operand, we have to
5246 multiply opnum by at least three. We round that up to four because
5247 multiply by four is often cheaper. */
5248 case RELOAD_FOR_INPADDR_ADDRESS:
5249 time1 = opnum * 4 + 2;
5251 case RELOAD_FOR_INPUT_ADDRESS:
5252 time1 = opnum * 4 + 3;
5254 case RELOAD_FOR_INPUT:
5255 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5256 executes (inclusive). */
5257 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5259 case RELOAD_FOR_OPADDR_ADDR:
5261 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5262 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5264 case RELOAD_FOR_OPERAND_ADDRESS:
5265 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5267 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5269 case RELOAD_FOR_OUTADDR_ADDRESS:
5270 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5272 case RELOAD_FOR_OUTPUT_ADDRESS:
5273 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5276 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5279 for (i = 0; i < n_reloads; i++)
5281 rtx reg = reload_reg_rtx[i];
5282 if (reg && GET_CODE (reg) == REG
5283 && ((unsigned) regno - true_regnum (reg)
5284 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned)1)
5287 if (! reload_in[i] || ! rtx_equal_p (reload_in[i], value)
5288 || reload_out[i] || out)
5291 switch (reload_when_needed[i])
5293 case RELOAD_FOR_OTHER_ADDRESS:
5296 case RELOAD_FOR_INPADDR_ADDRESS:
5297 /* find_reloads makes sure that a
5298 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5299 by at most one - the first -
5300 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5301 address reload is inherited, the address address reload
5302 goes away, so we can ignore this conflict. */
5303 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5304 && ignore_address_reloads
5305 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5306 Then the address address is still needed to store
5307 back the new address. */
5308 && ! reload_out[reloadnum])
5310 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5311 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5313 if (type == RELOAD_FOR_INPUT && opnum == reload_opnum[i]
5314 && ignore_address_reloads
5315 /* Unless we are reloading an auto_inc expression. */
5316 && ! reload_out[reloadnum])
5318 time2 = reload_opnum[i] * 4 + 2;
5320 case RELOAD_FOR_INPUT_ADDRESS:
5321 if (type == RELOAD_FOR_INPUT && opnum == reload_opnum[i]
5322 && ignore_address_reloads
5323 && ! reload_out[reloadnum])
5325 time2 = reload_opnum[i] * 4 + 3;
5327 case RELOAD_FOR_INPUT:
5328 time2 = reload_opnum[i] * 4 + 4;
5329 check_earlyclobber = 1;
5331 /* reload_opnum[i] * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5332 == MAX_RECOG_OPERAND * 4 */
5333 case RELOAD_FOR_OPADDR_ADDR:
5334 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5335 && ignore_address_reloads
5336 && ! reload_out[reloadnum])
5338 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5340 case RELOAD_FOR_OPERAND_ADDRESS:
5341 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5342 check_earlyclobber = 1;
5344 case RELOAD_FOR_INSN:
5345 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5347 case RELOAD_FOR_OUTPUT:
5348 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5349 instruction is executed. */
5350 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5352 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5353 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5355 case RELOAD_FOR_OUTADDR_ADDRESS:
5356 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5357 && ignore_address_reloads
5358 && ! reload_out[reloadnum])
5360 time2 = MAX_RECOG_OPERANDS * 4 + 4 + reload_opnum[i];
5362 case RELOAD_FOR_OUTPUT_ADDRESS:
5363 time2 = MAX_RECOG_OPERANDS * 4 + 5 + reload_opnum[i];
5366 /* If there is no conflict in the input part, handle this
5367 like an output reload. */
5368 if (! reload_in[i] || rtx_equal_p (reload_in[i], value))
5370 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5371 /* Earlyclobbered outputs must conflict with inputs. */
5372 if (earlyclobber_operand_p (reload_out[i]))
5373 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5377 /* RELOAD_OTHER might be live beyond instruction execution,
5378 but this is not obvious when we set time2 = 1. So check
5379 here if there might be a problem with the new reload
5380 clobbering the register used by the RELOAD_OTHER. */
5388 && (! reload_in[i] || reload_out[i]
5389 || ! rtx_equal_p (reload_in[i], value)))
5390 || (out && reload_out_reg[reloadnum]
5391 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5397 /* Earlyclobbered outputs must conflict with inputs. */
5398 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5404 /* Return 1 if the value in reload reg REGNO, as used by a reload
5405 needed for the part of the insn specified by OPNUM and TYPE,
5406 may be used to load VALUE into it.
5408 MODE is the mode in which the register is used, this is needed to
5409 determine how many hard regs to test.
5411 Other read-only reloads with the same value do not conflict
5412 unless OUT is non-zero and these other reloads have to live while
5413 output reloads live.
5414 If OUT is CONST0_RTX, this is a special case: it means that the
5415 test should not be for using register REGNO as reload register, but
5416 for copying from register REGNO into the reload register.
5418 RELOADNUM is the number of the reload we want to load this value for;
5419 a reload does not conflict with itself.
5421 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5422 reloads that load an address for the very reload we are considering.
5424 The caller has to make sure that there is no conflict with the return
5428 free_for_value_p (regno, mode, opnum, type, value, out, reloadnum,
5429 ignore_address_reloads)
5431 enum machine_mode mode;
5433 enum reload_type type;
5436 int ignore_address_reloads;
5438 int nregs = HARD_REGNO_NREGS (regno, mode);
5440 if (! reload_reg_free_for_value_p (regno + nregs, opnum, type, value, out,
5441 reloadnum, ignore_address_reloads))
5446 /* Determine whether the reload reg X overlaps any rtx'es used for
5447 overriding inheritance. Return nonzero if so. */
5450 conflicts_with_override (x)
5454 for (i = 0; i < n_reloads; i++)
5455 if (reload_override_in[i]
5456 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5461 /* Find a spill register to use as a reload register for reload R.
5462 LAST_RELOAD is non-zero if this is the last reload for the insn being
5465 Set reload_reg_rtx[R] to the register allocated.
5467 If NOERROR is nonzero, we return 1 if successful,
5468 or 0 if we couldn't find a spill reg and we didn't change anything. */
5471 allocate_reload_reg (chain, r, last_reload, noerror)
5472 struct insn_chain *chain;
5477 rtx insn = chain->insn;
5478 int i, pass, count, regno;
5481 /* If we put this reload ahead, thinking it is a group,
5482 then insist on finding a group. Otherwise we can grab a
5483 reg that some other reload needs.
5484 (That can happen when we have a 68000 DATA_OR_FP_REG
5485 which is a group of data regs or one fp reg.)
5486 We need not be so restrictive if there are no more reloads
5489 ??? Really it would be nicer to have smarter handling
5490 for that kind of reg class, where a problem like this is normal.
5491 Perhaps those classes should be avoided for reloading
5492 by use of more alternatives. */
5494 int force_group = reload_nregs[r] > 1 && ! last_reload;
5496 /* If we want a single register and haven't yet found one,
5497 take any reg in the right class and not in use.
5498 If we want a consecutive group, here is where we look for it.
5500 We use two passes so we can first look for reload regs to
5501 reuse, which are already in use for other reloads in this insn,
5502 and only then use additional registers.
5503 I think that maximizing reuse is needed to make sure we don't
5504 run out of reload regs. Suppose we have three reloads, and
5505 reloads A and B can share regs. These need two regs.
5506 Suppose A and B are given different regs.
5507 That leaves none for C. */
5508 for (pass = 0; pass < 2; pass++)
5510 /* I is the index in spill_regs.
5511 We advance it round-robin between insns to use all spill regs
5512 equally, so that inherited reloads have a chance
5513 of leapfrogging each other. Don't do this, however, when we have
5514 group needs and failure would be fatal; if we only have a relatively
5515 small number of spill registers, and more than one of them has
5516 group needs, then by starting in the middle, we may end up
5517 allocating the first one in such a way that we are not left with
5518 sufficient groups to handle the rest. */
5520 if (noerror || ! force_group)
5525 for (count = 0; count < n_spills; count++)
5527 int class = (int) reload_reg_class[r];
5533 regnum = spill_regs[i];
5535 if ((reload_reg_free_p (regnum, reload_opnum[r],
5536 reload_when_needed[r])
5538 /* We check reload_reg_used to make sure we
5539 don't clobber the return register. */
5540 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5541 && free_for_value_p (regnum, reload_mode[r],
5543 reload_when_needed[r],
5544 reload_in[r], reload_out[r], r, 1)))
5545 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5546 && HARD_REGNO_MODE_OK (regnum, reload_mode[r])
5547 /* Look first for regs to share, then for unshared. But
5548 don't share regs used for inherited reloads; they are
5549 the ones we want to preserve. */
5551 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5553 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5556 int nr = HARD_REGNO_NREGS (regnum, reload_mode[r]);
5557 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5558 (on 68000) got us two FP regs. If NR is 1,
5559 we would reject both of them. */
5561 nr = CLASS_MAX_NREGS (reload_reg_class[r], reload_mode[r]);
5562 /* If we need only one reg, we have already won. */
5565 /* But reject a single reg if we demand a group. */
5570 /* Otherwise check that as many consecutive regs as we need
5572 Also, don't use for a group registers that are
5573 needed for nongroups. */
5574 if (! TEST_HARD_REG_BIT (chain->counted_for_nongroups, regnum))
5577 regno = regnum + nr - 1;
5578 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5579 && spill_reg_order[regno] >= 0
5580 && reload_reg_free_p (regno, reload_opnum[r],
5581 reload_when_needed[r])
5582 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups,
5592 /* If we found something on pass 1, omit pass 2. */
5593 if (count < n_spills)
5597 /* We should have found a spill register by now. */
5598 if (count == n_spills)
5605 /* I is the index in SPILL_REG_RTX of the reload register we are to
5606 allocate. Get an rtx for it and find its register number. */
5608 new = spill_reg_rtx[i];
5610 if (new == 0 || GET_MODE (new) != reload_mode[r])
5611 spill_reg_rtx[i] = new
5612 = gen_rtx_REG (reload_mode[r], spill_regs[i]);
5614 regno = true_regnum (new);
5616 /* Detect when the reload reg can't hold the reload mode.
5617 This used to be one `if', but Sequent compiler can't handle that. */
5618 if (HARD_REGNO_MODE_OK (regno, reload_mode[r]))
5620 enum machine_mode test_mode = VOIDmode;
5622 test_mode = GET_MODE (reload_in[r]);
5623 /* If reload_in[r] has VOIDmode, it means we will load it
5624 in whatever mode the reload reg has: to wit, reload_mode[r].
5625 We have already tested that for validity. */
5626 /* Aside from that, we need to test that the expressions
5627 to reload from or into have modes which are valid for this
5628 reload register. Otherwise the reload insns would be invalid. */
5629 if (! (reload_in[r] != 0 && test_mode != VOIDmode
5630 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5631 if (! (reload_out[r] != 0
5632 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (reload_out[r]))))
5634 /* The reg is OK. */
5637 /* Mark as in use for this insn the reload regs we use
5639 mark_reload_reg_in_use (spill_regs[i], reload_opnum[r],
5640 reload_when_needed[r], reload_mode[r]);
5642 reload_reg_rtx[r] = new;
5643 reload_spill_index[r] = spill_regs[i];
5648 /* The reg is not OK. */
5653 if (asm_noperands (PATTERN (insn)) < 0)
5654 /* It's the compiler's fault. */
5655 fatal_insn ("Could not find a spill register", insn);
5657 /* It's the user's fault; the operand's mode and constraint
5658 don't match. Disable this reload so we don't crash in final. */
5659 error_for_asm (insn,
5660 "`asm' operand constraint incompatible with operand size");
5663 reload_reg_rtx[r] = 0;
5664 reload_optional[r] = 1;
5665 reload_secondary_p[r] = 1;
5670 /* Assign hard reg targets for the pseudo-registers we must reload
5671 into hard regs for this insn.
5672 Also output the instructions to copy them in and out of the hard regs.
5674 For machines with register classes, we are responsible for
5675 finding a reload reg in the proper class. */
5678 choose_reload_regs (chain)
5679 struct insn_chain *chain;
5681 rtx insn = chain->insn;
5683 int max_group_size = 1;
5684 enum reg_class group_class = NO_REGS;
5688 rtx save_reload_reg_rtx[MAX_RELOADS];
5689 char save_reload_inherited[MAX_RELOADS];
5690 rtx save_reload_inheritance_insn[MAX_RELOADS];
5691 rtx save_reload_override_in[MAX_RELOADS];
5692 int save_reload_spill_index[MAX_RELOADS];
5693 HARD_REG_SET save_reload_reg_used;
5694 HARD_REG_SET save_reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
5695 HARD_REG_SET save_reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
5696 HARD_REG_SET save_reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
5697 HARD_REG_SET save_reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
5698 HARD_REG_SET save_reload_reg_used_in_input[MAX_RECOG_OPERANDS];
5699 HARD_REG_SET save_reload_reg_used_in_output[MAX_RECOG_OPERANDS];
5700 HARD_REG_SET save_reload_reg_used_in_op_addr;
5701 HARD_REG_SET save_reload_reg_used_in_op_addr_reload;
5702 HARD_REG_SET save_reload_reg_used_in_insn;
5703 HARD_REG_SET save_reload_reg_used_in_other_addr;
5704 HARD_REG_SET save_reload_reg_used_at_all;
5706 bzero (reload_inherited, MAX_RELOADS);
5707 bzero ((char *) reload_inheritance_insn, MAX_RELOADS * sizeof (rtx));
5708 bzero ((char *) reload_override_in, MAX_RELOADS * sizeof (rtx));
5710 CLEAR_HARD_REG_SET (reload_reg_used);
5711 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5712 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5713 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5714 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5715 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5717 CLEAR_HARD_REG_SET (reg_used_in_insn);
5720 REG_SET_TO_HARD_REG_SET (tmp, chain->live_before);
5721 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5722 REG_SET_TO_HARD_REG_SET (tmp, chain->live_after);
5723 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5724 compute_use_by_pseudos (®_used_in_insn, chain->live_before);
5725 compute_use_by_pseudos (®_used_in_insn, chain->live_after);
5727 for (i = 0; i < reload_n_operands; i++)
5729 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5730 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5731 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5732 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5733 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5734 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5737 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5739 #if 0 /* Not needed, now that we can always retry without inheritance. */
5740 /* See if we have more mandatory reloads than spill regs.
5741 If so, then we cannot risk optimizations that could prevent
5742 reloads from sharing one spill register.
5744 Since we will try finding a better register than reload_reg_rtx
5745 unless it is equal to reload_in or reload_out, count such reloads. */
5749 for (j = 0; j < n_reloads; j++)
5750 if (! reload_optional[j]
5751 && (reload_in[j] != 0 || reload_out[j] != 0 || reload_secondary_p[j])
5752 && (reload_reg_rtx[j] == 0
5753 || (! rtx_equal_p (reload_reg_rtx[j], reload_in[j])
5754 && ! rtx_equal_p (reload_reg_rtx[j], reload_out[j]))))
5761 /* In order to be certain of getting the registers we need,
5762 we must sort the reloads into order of increasing register class.
5763 Then our grabbing of reload registers will parallel the process
5764 that provided the reload registers.
5766 Also note whether any of the reloads wants a consecutive group of regs.
5767 If so, record the maximum size of the group desired and what
5768 register class contains all the groups needed by this insn. */
5770 for (j = 0; j < n_reloads; j++)
5772 reload_order[j] = j;
5773 reload_spill_index[j] = -1;
5776 = (reload_inmode[j] == VOIDmode
5777 || (GET_MODE_SIZE (reload_outmode[j])
5778 > GET_MODE_SIZE (reload_inmode[j])))
5779 ? reload_outmode[j] : reload_inmode[j];
5781 reload_nregs[j] = CLASS_MAX_NREGS (reload_reg_class[j], reload_mode[j]);
5783 if (reload_nregs[j] > 1)
5785 max_group_size = MAX (reload_nregs[j], max_group_size);
5786 group_class = reg_class_superunion[(int)reload_reg_class[j]][(int)group_class];
5789 /* If we have already decided to use a certain register,
5790 don't use it in another way. */
5791 if (reload_reg_rtx[j])
5792 mark_reload_reg_in_use (REGNO (reload_reg_rtx[j]), reload_opnum[j],
5793 reload_when_needed[j], reload_mode[j]);
5797 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5799 bcopy ((char *) reload_reg_rtx, (char *) save_reload_reg_rtx,
5800 sizeof reload_reg_rtx);
5801 bcopy (reload_inherited, save_reload_inherited, sizeof reload_inherited);
5802 bcopy ((char *) reload_inheritance_insn,
5803 (char *) save_reload_inheritance_insn,
5804 sizeof reload_inheritance_insn);
5805 bcopy ((char *) reload_override_in, (char *) save_reload_override_in,
5806 sizeof reload_override_in);
5807 bcopy ((char *) reload_spill_index, (char *) save_reload_spill_index,
5808 sizeof reload_spill_index);
5809 COPY_HARD_REG_SET (save_reload_reg_used, reload_reg_used);
5810 COPY_HARD_REG_SET (save_reload_reg_used_at_all, reload_reg_used_at_all);
5811 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr,
5812 reload_reg_used_in_op_addr);
5814 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr_reload,
5815 reload_reg_used_in_op_addr_reload);
5817 COPY_HARD_REG_SET (save_reload_reg_used_in_insn,
5818 reload_reg_used_in_insn);
5819 COPY_HARD_REG_SET (save_reload_reg_used_in_other_addr,
5820 reload_reg_used_in_other_addr);
5822 for (i = 0; i < reload_n_operands; i++)
5824 COPY_HARD_REG_SET (save_reload_reg_used_in_output[i],
5825 reload_reg_used_in_output[i]);
5826 COPY_HARD_REG_SET (save_reload_reg_used_in_input[i],
5827 reload_reg_used_in_input[i]);
5828 COPY_HARD_REG_SET (save_reload_reg_used_in_input_addr[i],
5829 reload_reg_used_in_input_addr[i]);
5830 COPY_HARD_REG_SET (save_reload_reg_used_in_inpaddr_addr[i],
5831 reload_reg_used_in_inpaddr_addr[i]);
5832 COPY_HARD_REG_SET (save_reload_reg_used_in_output_addr[i],
5833 reload_reg_used_in_output_addr[i]);
5834 COPY_HARD_REG_SET (save_reload_reg_used_in_outaddr_addr[i],
5835 reload_reg_used_in_outaddr_addr[i]);
5838 /* If -O, try first with inheritance, then turning it off.
5839 If not -O, don't do inheritance.
5840 Using inheritance when not optimizing leads to paradoxes
5841 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5842 because one side of the comparison might be inherited. */
5844 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5846 /* Process the reloads in order of preference just found.
5847 Beyond this point, subregs can be found in reload_reg_rtx.
5849 This used to look for an existing reloaded home for all
5850 of the reloads, and only then perform any new reloads.
5851 But that could lose if the reloads were done out of reg-class order
5852 because a later reload with a looser constraint might have an old
5853 home in a register needed by an earlier reload with a tighter constraint.
5855 To solve this, we make two passes over the reloads, in the order
5856 described above. In the first pass we try to inherit a reload
5857 from a previous insn. If there is a later reload that needs a
5858 class that is a proper subset of the class being processed, we must
5859 also allocate a spill register during the first pass.
5861 Then make a second pass over the reloads to allocate any reloads
5862 that haven't been given registers yet. */
5864 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5866 for (j = 0; j < n_reloads; j++)
5868 register int r = reload_order[j];
5869 rtx search_equiv = NULL_RTX;
5871 /* Ignore reloads that got marked inoperative. */
5872 if (reload_out[r] == 0 && reload_in[r] == 0
5873 && ! reload_secondary_p[r])
5876 /* If find_reloads chose to use reload_in or reload_out as a reload
5877 register, we don't need to chose one. Otherwise, try even if it
5878 found one since we might save an insn if we find the value lying
5880 Try also when reload_in is a pseudo without a hard reg. */
5881 if (reload_in[r] != 0 && reload_reg_rtx[r] != 0
5882 && (rtx_equal_p (reload_in[r], reload_reg_rtx[r])
5883 || (rtx_equal_p (reload_out[r], reload_reg_rtx[r])
5884 && GET_CODE (reload_in[r]) != MEM
5885 && true_regnum (reload_in[r]) < FIRST_PSEUDO_REGISTER)))
5888 #if 0 /* No longer needed for correct operation.
5889 It might give better code, or might not; worth an experiment? */
5890 /* If this is an optional reload, we can't inherit from earlier insns
5891 until we are sure that any non-optional reloads have been allocated.
5892 The following code takes advantage of the fact that optional reloads
5893 are at the end of reload_order. */
5894 if (reload_optional[r] != 0)
5895 for (i = 0; i < j; i++)
5896 if ((reload_out[reload_order[i]] != 0
5897 || reload_in[reload_order[i]] != 0
5898 || reload_secondary_p[reload_order[i]])
5899 && ! reload_optional[reload_order[i]]
5900 && reload_reg_rtx[reload_order[i]] == 0)
5901 allocate_reload_reg (chain, reload_order[i], 0, inheritance);
5904 /* First see if this pseudo is already available as reloaded
5905 for a previous insn. We cannot try to inherit for reloads
5906 that are smaller than the maximum number of registers needed
5907 for groups unless the register we would allocate cannot be used
5910 We could check here to see if this is a secondary reload for
5911 an object that is already in a register of the desired class.
5912 This would avoid the need for the secondary reload register.
5913 But this is complex because we can't easily determine what
5914 objects might want to be loaded via this reload. So let a
5915 register be allocated here. In `emit_reload_insns' we suppress
5916 one of the loads in the case described above. */
5921 register int regno = -1;
5922 enum machine_mode mode;
5924 if (reload_in[r] == 0)
5926 else if (GET_CODE (reload_in[r]) == REG)
5928 regno = REGNO (reload_in[r]);
5929 mode = GET_MODE (reload_in[r]);
5931 else if (GET_CODE (reload_in_reg[r]) == REG)
5933 regno = REGNO (reload_in_reg[r]);
5934 mode = GET_MODE (reload_in_reg[r]);
5936 else if (GET_CODE (reload_in_reg[r]) == SUBREG
5937 && GET_CODE (SUBREG_REG (reload_in_reg[r])) == REG)
5939 word = SUBREG_WORD (reload_in_reg[r]);
5940 regno = REGNO (SUBREG_REG (reload_in_reg[r]));
5941 if (regno < FIRST_PSEUDO_REGISTER)
5943 mode = GET_MODE (reload_in_reg[r]);
5946 else if ((GET_CODE (reload_in_reg[r]) == PRE_INC
5947 || GET_CODE (reload_in_reg[r]) == PRE_DEC
5948 || GET_CODE (reload_in_reg[r]) == POST_INC
5949 || GET_CODE (reload_in_reg[r]) == POST_DEC)
5950 && GET_CODE (XEXP (reload_in_reg[r], 0)) == REG)
5952 regno = REGNO (XEXP (reload_in_reg[r], 0));
5953 mode = GET_MODE (XEXP (reload_in_reg[r], 0));
5954 reload_out[r] = reload_in[r];
5958 /* This won't work, since REGNO can be a pseudo reg number.
5959 Also, it takes much more hair to keep track of all the things
5960 that can invalidate an inherited reload of part of a pseudoreg. */
5961 else if (GET_CODE (reload_in[r]) == SUBREG
5962 && GET_CODE (SUBREG_REG (reload_in[r])) == REG)
5963 regno = REGNO (SUBREG_REG (reload_in[r])) + SUBREG_WORD (reload_in[r]);
5966 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5968 enum reg_class class = reload_reg_class[r], last_class;
5969 rtx last_reg = reg_last_reload_reg[regno];
5971 i = REGNO (last_reg) + word;
5972 last_class = REGNO_REG_CLASS (i);
5973 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5974 >= GET_MODE_SIZE (mode) + word * UNITS_PER_WORD)
5975 && reg_reloaded_contents[i] == regno
5976 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5977 && HARD_REGNO_MODE_OK (i, reload_mode[r])
5978 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5979 /* Even if we can't use this register as a reload
5980 register, we might use it for reload_override_in,
5981 if copying it to the desired class is cheap
5983 || ((REGISTER_MOVE_COST (last_class, class)
5984 < MEMORY_MOVE_COST (mode, class, 1))
5985 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5986 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5990 #ifdef SECONDARY_MEMORY_NEEDED
5991 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5996 && (reload_nregs[r] == max_group_size
5997 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5999 && free_for_value_p (i, reload_mode[r], reload_opnum[r],
6000 reload_when_needed[r], reload_in[r],
6003 /* If a group is needed, verify that all the subsequent
6004 registers still have their values intact. */
6006 = HARD_REGNO_NREGS (i, reload_mode[r]);
6009 for (k = 1; k < nr; k++)
6010 if (reg_reloaded_contents[i + k] != regno
6011 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
6018 last_reg = (GET_MODE (last_reg) == mode
6019 ? last_reg : gen_rtx_REG (mode, i));
6021 /* We found a register that contains the
6022 value we need. If this register is the
6023 same as an `earlyclobber' operand of the
6024 current insn, just mark it as a place to
6025 reload from since we can't use it as the
6026 reload register itself. */
6028 for (i1 = 0; i1 < n_earlyclobbers; i1++)
6029 if (reg_overlap_mentioned_for_reload_p
6030 (reg_last_reload_reg[regno],
6031 reload_earlyclobbers[i1]))
6034 if (i1 != n_earlyclobbers
6035 || ! (free_for_value_p (i, reload_mode[r],
6037 reload_when_needed[r],
6039 reload_out[r], r, 1))
6040 /* Don't use it if we'd clobber a pseudo reg. */
6041 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
6043 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
6044 /* Don't clobber the frame pointer. */
6045 || (i == HARD_FRAME_POINTER_REGNUM
6047 /* Don't really use the inherited spill reg
6048 if we need it wider than we've got it. */
6049 || (GET_MODE_SIZE (reload_mode[r])
6050 > GET_MODE_SIZE (mode))
6051 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
6054 /* If find_reloads chose reload_out as reload
6055 register, stay with it - that leaves the
6056 inherited register for subsequent reloads. */
6057 || (reload_out[r] && reload_reg_rtx[r]
6058 && rtx_equal_p (reload_out[r],
6059 reload_reg_rtx[r])))
6061 if (! reload_optional[r])
6063 reload_override_in[r] = last_reg;
6064 reload_inheritance_insn[r]
6065 = reg_reloaded_insn[i];
6071 /* We can use this as a reload reg. */
6072 /* Mark the register as in use for this part of
6074 mark_reload_reg_in_use (i,
6076 reload_when_needed[r],
6078 reload_reg_rtx[r] = last_reg;
6079 reload_inherited[r] = 1;
6080 reload_inheritance_insn[r]
6081 = reg_reloaded_insn[i];
6082 reload_spill_index[r] = i;
6083 for (k = 0; k < nr; k++)
6084 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6092 /* Here's another way to see if the value is already lying around. */
6094 && reload_in[r] != 0
6095 && ! reload_inherited[r]
6096 && reload_out[r] == 0
6097 && (CONSTANT_P (reload_in[r])
6098 || GET_CODE (reload_in[r]) == PLUS
6099 || GET_CODE (reload_in[r]) == REG
6100 || GET_CODE (reload_in[r]) == MEM)
6101 && (reload_nregs[r] == max_group_size
6102 || ! reg_classes_intersect_p (reload_reg_class[r], group_class)))
6103 search_equiv = reload_in[r];
6104 /* If this is an output reload from a simple move insn, look
6105 if an equivalence for the input is available. */
6106 else if (inheritance && reload_in[r] == 0 && reload_out[r] != 0)
6108 rtx set = single_set (insn);
6111 && rtx_equal_p (reload_out[r], SET_DEST (set))
6112 && CONSTANT_P (SET_SRC (set)))
6113 search_equiv = SET_SRC (set);
6119 = find_equiv_reg (search_equiv, insn, reload_reg_class[r],
6120 -1, NULL_PTR, 0, reload_mode[r]);
6125 if (GET_CODE (equiv) == REG)
6126 regno = REGNO (equiv);
6127 else if (GET_CODE (equiv) == SUBREG)
6129 /* This must be a SUBREG of a hard register.
6130 Make a new REG since this might be used in an
6131 address and not all machines support SUBREGs
6133 regno = REGNO (SUBREG_REG (equiv)) + SUBREG_WORD (equiv);
6134 equiv = gen_rtx_REG (reload_mode[r], regno);
6140 /* If we found a spill reg, reject it unless it is free
6141 and of the desired class. */
6143 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)
6144 && ! free_for_value_p (regno, reload_mode[r],
6146 reload_when_needed[r],
6147 reload_in[r], reload_out[r], r,
6149 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
6153 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, reload_mode[r]))
6156 /* We found a register that contains the value we need.
6157 If this register is the same as an `earlyclobber' operand
6158 of the current insn, just mark it as a place to reload from
6159 since we can't use it as the reload register itself. */
6162 for (i = 0; i < n_earlyclobbers; i++)
6163 if (reg_overlap_mentioned_for_reload_p (equiv,
6164 reload_earlyclobbers[i]))
6166 if (! reload_optional[r])
6167 reload_override_in[r] = equiv;
6172 /* If the equiv register we have found is explicitly clobbered
6173 in the current insn, it depends on the reload type if we
6174 can use it, use it for reload_override_in, or not at all.
6175 In particular, we then can't use EQUIV for a
6176 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6178 if (equiv != 0 && regno_clobbered_p (regno, insn,
6181 switch (reload_when_needed[r])
6183 case RELOAD_FOR_OTHER_ADDRESS:
6184 case RELOAD_FOR_INPADDR_ADDRESS:
6185 case RELOAD_FOR_INPUT_ADDRESS:
6186 case RELOAD_FOR_OPADDR_ADDR:
6189 case RELOAD_FOR_INPUT:
6190 case RELOAD_FOR_OPERAND_ADDRESS:
6191 if (! reload_optional[r])
6192 reload_override_in[r] = equiv;
6199 else if (regno_clobbered_p (regno, insn, reload_mode[r], 1))
6200 switch (reload_when_needed[r])
6202 case RELOAD_FOR_OTHER_ADDRESS:
6203 case RELOAD_FOR_INPADDR_ADDRESS:
6204 case RELOAD_FOR_INPUT_ADDRESS:
6205 case RELOAD_FOR_OPADDR_ADDR:
6206 case RELOAD_FOR_OPERAND_ADDRESS:
6207 case RELOAD_FOR_INPUT:
6210 if (! reload_optional[r])
6211 reload_override_in[r] = equiv;
6218 /* If we found an equivalent reg, say no code need be generated
6219 to load it, and use it as our reload reg. */
6220 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
6222 int nr = HARD_REGNO_NREGS (regno, reload_mode[r]);
6224 reload_reg_rtx[r] = equiv;
6225 reload_inherited[r] = 1;
6227 /* If reg_reloaded_valid is not set for this register,
6228 there might be a stale spill_reg_store lying around.
6229 We must clear it, since otherwise emit_reload_insns
6230 might delete the store. */
6231 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6232 spill_reg_store[regno] = NULL_RTX;
6233 /* If any of the hard registers in EQUIV are spill
6234 registers, mark them as in use for this insn. */
6235 for (k = 0; k < nr; k++)
6237 i = spill_reg_order[regno + k];
6240 mark_reload_reg_in_use (regno, reload_opnum[r],
6241 reload_when_needed[r],
6243 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6250 /* If we found a register to use already, or if this is an optional
6251 reload, we are done. */
6252 if (reload_reg_rtx[r] != 0 || reload_optional[r] != 0)
6255 #if 0 /* No longer needed for correct operation. Might or might not
6256 give better code on the average. Want to experiment? */
6258 /* See if there is a later reload that has a class different from our
6259 class that intersects our class or that requires less register
6260 than our reload. If so, we must allocate a register to this
6261 reload now, since that reload might inherit a previous reload
6262 and take the only available register in our class. Don't do this
6263 for optional reloads since they will force all previous reloads
6264 to be allocated. Also don't do this for reloads that have been
6267 for (i = j + 1; i < n_reloads; i++)
6269 int s = reload_order[i];
6271 if ((reload_in[s] == 0 && reload_out[s] == 0
6272 && ! reload_secondary_p[s])
6273 || reload_optional[s])
6276 if ((reload_reg_class[s] != reload_reg_class[r]
6277 && reg_classes_intersect_p (reload_reg_class[r],
6278 reload_reg_class[s]))
6279 || reload_nregs[s] < reload_nregs[r])
6286 allocate_reload_reg (chain, r, j == n_reloads - 1, inheritance);
6290 /* Now allocate reload registers for anything non-optional that
6291 didn't get one yet. */
6292 for (j = 0; j < n_reloads; j++)
6294 register int r = reload_order[j];
6296 /* Ignore reloads that got marked inoperative. */
6297 if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r])
6300 /* Skip reloads that already have a register allocated or are
6302 if (reload_reg_rtx[r] != 0 || reload_optional[r])
6305 if (! allocate_reload_reg (chain, r, j == n_reloads - 1, inheritance))
6309 /* If that loop got all the way, we have won. */
6313 /* Loop around and try without any inheritance. */
6314 /* First undo everything done by the failed attempt
6315 to allocate with inheritance. */
6316 bcopy ((char *) save_reload_reg_rtx, (char *) reload_reg_rtx,
6317 sizeof reload_reg_rtx);
6318 bcopy ((char *) save_reload_inherited, (char *) reload_inherited,
6319 sizeof reload_inherited);
6320 bcopy ((char *) save_reload_inheritance_insn,
6321 (char *) reload_inheritance_insn,
6322 sizeof reload_inheritance_insn);
6323 bcopy ((char *) save_reload_override_in, (char *) reload_override_in,
6324 sizeof reload_override_in);
6325 bcopy ((char *) save_reload_spill_index, (char *) reload_spill_index,
6326 sizeof reload_spill_index);
6327 COPY_HARD_REG_SET (reload_reg_used, save_reload_reg_used);
6328 COPY_HARD_REG_SET (reload_reg_used_at_all, save_reload_reg_used_at_all);
6329 COPY_HARD_REG_SET (reload_reg_used_in_op_addr,
6330 save_reload_reg_used_in_op_addr);
6331 COPY_HARD_REG_SET (reload_reg_used_in_op_addr_reload,
6332 save_reload_reg_used_in_op_addr_reload);
6333 COPY_HARD_REG_SET (reload_reg_used_in_insn,
6334 save_reload_reg_used_in_insn);
6335 COPY_HARD_REG_SET (reload_reg_used_in_other_addr,
6336 save_reload_reg_used_in_other_addr);
6338 for (i = 0; i < reload_n_operands; i++)
6340 COPY_HARD_REG_SET (reload_reg_used_in_input[i],
6341 save_reload_reg_used_in_input[i]);
6342 COPY_HARD_REG_SET (reload_reg_used_in_output[i],
6343 save_reload_reg_used_in_output[i]);
6344 COPY_HARD_REG_SET (reload_reg_used_in_input_addr[i],
6345 save_reload_reg_used_in_input_addr[i]);
6346 COPY_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i],
6347 save_reload_reg_used_in_inpaddr_addr[i]);
6348 COPY_HARD_REG_SET (reload_reg_used_in_output_addr[i],
6349 save_reload_reg_used_in_output_addr[i]);
6350 COPY_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i],
6351 save_reload_reg_used_in_outaddr_addr[i]);
6355 /* If we thought we could inherit a reload, because it seemed that
6356 nothing else wanted the same reload register earlier in the insn,
6357 verify that assumption, now that all reloads have been assigned.
6358 Likewise for reloads where reload_override_in has been set. */
6360 /* If doing expensive optimizations, do one preliminary pass that doesn't
6361 cancel any inheritance, but removes reloads that have been needed only
6362 for reloads that we know can be inherited. */
6363 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6365 for (j = 0; j < n_reloads; j++)
6367 register int r = reload_order[j];
6369 if (reload_inherited[r] && reload_reg_rtx[r])
6370 check_reg = reload_reg_rtx[r];
6371 else if (reload_override_in[r]
6372 && (GET_CODE (reload_override_in[r]) == REG
6373 || GET_CODE (reload_override_in[r]) == SUBREG))
6374 check_reg = reload_override_in[r];
6377 if (! free_for_value_p (true_regnum (check_reg), reload_mode[r],
6378 reload_opnum[r], reload_when_needed[r],
6380 (reload_inherited[r]
6381 ? reload_out[r] : const0_rtx),
6386 reload_inherited[r] = 0;
6387 reload_override_in[r] = 0;
6389 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6390 reload_override_in, then we do not need its related
6391 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6392 likewise for other reload types.
6393 We handle this by removing a reload when its only replacement
6394 is mentioned in reload_in of the reload we are going to inherit.
6395 A special case are auto_inc expressions; even if the input is
6396 inherited, we still need the address for the output. We can
6397 recognize them because they have RELOAD_OUT set but not
6399 If we suceeded removing some reload and we are doing a preliminary
6400 pass just to remove such reloads, make another pass, since the
6401 removal of one reload might allow us to inherit another one. */
6402 else if ((! reload_out[r] || reload_out_reg[r])
6404 && remove_address_replacements (reload_in[r]) && pass)
6409 /* Now that reload_override_in is known valid,
6410 actually override reload_in. */
6411 for (j = 0; j < n_reloads; j++)
6412 if (reload_override_in[j])
6413 reload_in[j] = reload_override_in[j];
6415 /* If this reload won't be done because it has been cancelled or is
6416 optional and not inherited, clear reload_reg_rtx so other
6417 routines (such as subst_reloads) don't get confused. */
6418 for (j = 0; j < n_reloads; j++)
6419 if (reload_reg_rtx[j] != 0
6420 && ((reload_optional[j] && ! reload_inherited[j])
6421 || (reload_in[j] == 0 && reload_out[j] == 0
6422 && ! reload_secondary_p[j])))
6424 int regno = true_regnum (reload_reg_rtx[j]);
6426 if (spill_reg_order[regno] >= 0)
6427 clear_reload_reg_in_use (regno, reload_opnum[j],
6428 reload_when_needed[j], reload_mode[j]);
6429 reload_reg_rtx[j] = 0;
6430 reload_spill_index[j] = -1;
6433 /* Record which pseudos and which spill regs have output reloads. */
6434 for (j = 0; j < n_reloads; j++)
6436 register int r = reload_order[j];
6438 i = reload_spill_index[r];
6440 /* I is nonneg if this reload uses a register.
6441 If reload_reg_rtx[r] is 0, this is an optional reload
6442 that we opted to ignore. */
6443 if (reload_out_reg[r] != 0 && GET_CODE (reload_out_reg[r]) == REG
6444 && reload_reg_rtx[r] != 0)
6446 register int nregno = REGNO (reload_out_reg[r]);
6449 if (nregno < FIRST_PSEUDO_REGISTER)
6450 nr = HARD_REGNO_NREGS (nregno, reload_mode[r]);
6453 reg_has_output_reload[nregno + nr] = 1;
6457 nr = HARD_REGNO_NREGS (i, reload_mode[r]);
6459 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6462 if (reload_when_needed[r] != RELOAD_OTHER
6463 && reload_when_needed[r] != RELOAD_FOR_OUTPUT
6464 && reload_when_needed[r] != RELOAD_FOR_INSN)
6470 /* Deallocate the reload register for reload R. This is called from
6471 remove_address_replacements. */
6473 deallocate_reload_reg (r)
6478 if (! reload_reg_rtx[r])
6480 regno = true_regnum (reload_reg_rtx[r]);
6481 reload_reg_rtx[r] = 0;
6482 if (spill_reg_order[regno] >= 0)
6483 clear_reload_reg_in_use (regno, reload_opnum[r], reload_when_needed[r],
6485 reload_spill_index[r] = -1;
6488 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
6489 reloads of the same item for fear that we might not have enough reload
6490 registers. However, normally they will get the same reload register
6491 and hence actually need not be loaded twice.
6493 Here we check for the most common case of this phenomenon: when we have
6494 a number of reloads for the same object, each of which were allocated
6495 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6496 reload, and is not modified in the insn itself. If we find such,
6497 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6498 This will not increase the number of spill registers needed and will
6499 prevent redundant code. */
6502 merge_assigned_reloads (insn)
6507 /* Scan all the reloads looking for ones that only load values and
6508 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6509 assigned and not modified by INSN. */
6511 for (i = 0; i < n_reloads; i++)
6513 int conflicting_input = 0;
6514 int max_input_address_opnum = -1;
6515 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6517 if (reload_in[i] == 0 || reload_when_needed[i] == RELOAD_OTHER
6518 || reload_out[i] != 0 || reload_reg_rtx[i] == 0
6519 || reg_set_p (reload_reg_rtx[i], insn))
6522 /* Look at all other reloads. Ensure that the only use of this
6523 reload_reg_rtx is in a reload that just loads the same value
6524 as we do. Note that any secondary reloads must be of the identical
6525 class since the values, modes, and result registers are the
6526 same, so we need not do anything with any secondary reloads. */
6528 for (j = 0; j < n_reloads; j++)
6530 if (i == j || reload_reg_rtx[j] == 0
6531 || ! reg_overlap_mentioned_p (reload_reg_rtx[j],
6535 if (reload_when_needed[j] == RELOAD_FOR_INPUT_ADDRESS
6536 && reload_opnum[j] > max_input_address_opnum)
6537 max_input_address_opnum = reload_opnum[j];
6539 /* If the reload regs aren't exactly the same (e.g, different modes)
6540 or if the values are different, we can't merge this reload.
6541 But if it is an input reload, we might still merge
6542 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6544 if (! rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j])
6545 || reload_out[j] != 0 || reload_in[j] == 0
6546 || ! rtx_equal_p (reload_in[i], reload_in[j]))
6548 if (reload_when_needed[j] != RELOAD_FOR_INPUT
6549 || ((reload_when_needed[i] != RELOAD_FOR_INPUT_ADDRESS
6550 || reload_opnum[i] > reload_opnum[j])
6551 && reload_when_needed[i] != RELOAD_FOR_OTHER_ADDRESS))
6553 conflicting_input = 1;
6554 if (min_conflicting_input_opnum > reload_opnum[j])
6555 min_conflicting_input_opnum = reload_opnum[j];
6559 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6560 we, in fact, found any matching reloads. */
6563 && max_input_address_opnum <= min_conflicting_input_opnum)
6565 for (j = 0; j < n_reloads; j++)
6566 if (i != j && reload_reg_rtx[j] != 0
6567 && rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j])
6568 && (! conflicting_input
6569 || reload_when_needed[j] == RELOAD_FOR_INPUT_ADDRESS
6570 || reload_when_needed[j] == RELOAD_FOR_OTHER_ADDRESS))
6572 reload_when_needed[i] = RELOAD_OTHER;
6574 reload_spill_index[j] = -1;
6575 transfer_replacements (i, j);
6578 /* If this is now RELOAD_OTHER, look for any reloads that load
6579 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6580 if they were for inputs, RELOAD_OTHER for outputs. Note that
6581 this test is equivalent to looking for reloads for this operand
6584 if (reload_when_needed[i] == RELOAD_OTHER)
6585 for (j = 0; j < n_reloads; j++)
6586 if (reload_in[j] != 0
6587 && reload_when_needed[i] != RELOAD_OTHER
6588 && reg_overlap_mentioned_for_reload_p (reload_in[j],
6590 reload_when_needed[j]
6591 = ((reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS
6592 || reload_when_needed[i] == RELOAD_FOR_INPADDR_ADDRESS)
6593 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6599 /* Output insns to reload values in and out of the chosen reload regs. */
6602 emit_reload_insns (chain)
6603 struct insn_chain *chain;
6605 rtx insn = chain->insn;
6608 rtx input_reload_insns[MAX_RECOG_OPERANDS];
6609 rtx other_input_address_reload_insns = 0;
6610 rtx other_input_reload_insns = 0;
6611 rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6612 rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6613 rtx output_reload_insns[MAX_RECOG_OPERANDS];
6614 rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6615 rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6616 rtx operand_reload_insns = 0;
6617 rtx other_operand_reload_insns = 0;
6618 rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6619 rtx following_insn = NEXT_INSN (insn);
6620 rtx before_insn = PREV_INSN (insn);
6622 /* Values to be put in spill_reg_store are put here first. */
6623 rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6624 HARD_REG_SET reg_reloaded_died;
6626 CLEAR_HARD_REG_SET (reg_reloaded_died);
6628 for (j = 0; j < reload_n_operands; j++)
6629 input_reload_insns[j] = input_address_reload_insns[j]
6630 = inpaddr_address_reload_insns[j]
6631 = output_reload_insns[j] = output_address_reload_insns[j]
6632 = outaddr_address_reload_insns[j]
6633 = other_output_reload_insns[j] = 0;
6635 /* Now output the instructions to copy the data into and out of the
6636 reload registers. Do these in the order that the reloads were reported,
6637 since reloads of base and index registers precede reloads of operands
6638 and the operands may need the base and index registers reloaded. */
6640 for (j = 0; j < n_reloads; j++)
6643 rtx oldequiv_reg = 0;
6644 rtx this_reload_insn = 0;
6645 int expect_occurrences = 1;
6647 if (reload_reg_rtx[j]
6648 && REGNO (reload_reg_rtx[j]) < FIRST_PSEUDO_REGISTER)
6649 new_spill_reg_store[REGNO (reload_reg_rtx[j])] = 0;
6651 old = (reload_in[j] && GET_CODE (reload_in[j]) == MEM
6652 ? reload_in_reg[j] : reload_in[j]);
6655 /* AUTO_INC reloads need to be handled even if inherited. We got an
6656 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6657 && (! reload_inherited[j] || (reload_out[j] && ! reload_out_reg[j]))
6658 && ! rtx_equal_p (reload_reg_rtx[j], old)
6659 && reload_reg_rtx[j] != 0)
6661 register rtx reloadreg = reload_reg_rtx[j];
6663 enum machine_mode mode;
6666 /* Determine the mode to reload in.
6667 This is very tricky because we have three to choose from.
6668 There is the mode the insn operand wants (reload_inmode[J]).
6669 There is the mode of the reload register RELOADREG.
6670 There is the intrinsic mode of the operand, which we could find
6671 by stripping some SUBREGs.
6672 It turns out that RELOADREG's mode is irrelevant:
6673 we can change that arbitrarily.
6675 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6676 then the reload reg may not support QImode moves, so use SImode.
6677 If foo is in memory due to spilling a pseudo reg, this is safe,
6678 because the QImode value is in the least significant part of a
6679 slot big enough for a SImode. If foo is some other sort of
6680 memory reference, then it is impossible to reload this case,
6681 so previous passes had better make sure this never happens.
6683 Then consider a one-word union which has SImode and one of its
6684 members is a float, being fetched as (SUBREG:SF union:SI).
6685 We must fetch that as SFmode because we could be loading into
6686 a float-only register. In this case OLD's mode is correct.
6688 Consider an immediate integer: it has VOIDmode. Here we need
6689 to get a mode from something else.
6691 In some cases, there is a fourth mode, the operand's
6692 containing mode. If the insn specifies a containing mode for
6693 this operand, it overrides all others.
6695 I am not sure whether the algorithm here is always right,
6696 but it does the right things in those cases. */
6698 mode = GET_MODE (old);
6699 if (mode == VOIDmode)
6700 mode = reload_inmode[j];
6702 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6703 /* If we need a secondary register for this operation, see if
6704 the value is already in a register in that class. Don't
6705 do this if the secondary register will be used as a scratch
6708 if (reload_secondary_in_reload[j] >= 0
6709 && reload_secondary_in_icode[j] == CODE_FOR_nothing
6712 = find_equiv_reg (old, insn,
6713 reload_reg_class[reload_secondary_in_reload[j]],
6714 -1, NULL_PTR, 0, mode);
6717 /* If reloading from memory, see if there is a register
6718 that already holds the same value. If so, reload from there.
6719 We can pass 0 as the reload_reg_p argument because
6720 any other reload has either already been emitted,
6721 in which case find_equiv_reg will see the reload-insn,
6722 or has yet to be emitted, in which case it doesn't matter
6723 because we will use this equiv reg right away. */
6725 if (oldequiv == 0 && optimize
6726 && (GET_CODE (old) == MEM
6727 || (GET_CODE (old) == REG
6728 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6729 && reg_renumber[REGNO (old)] < 0)))
6730 oldequiv = find_equiv_reg (old, insn, ALL_REGS,
6731 -1, NULL_PTR, 0, mode);
6735 int regno = true_regnum (oldequiv);
6737 /* Don't use OLDEQUIV if any other reload changes it at an
6738 earlier stage of this insn or at this stage. */
6739 if (! free_for_value_p (regno, reload_mode[j],
6741 reload_when_needed[j],
6742 reload_in[j], const0_rtx, j, 0))
6745 /* If it is no cheaper to copy from OLDEQUIV into the
6746 reload register than it would be to move from memory,
6747 don't use it. Likewise, if we need a secondary register
6751 && ((REGNO_REG_CLASS (regno) != reload_reg_class[j]
6752 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno),
6753 reload_reg_class[j])
6754 >= MEMORY_MOVE_COST (mode, reload_reg_class[j], 1)))
6755 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6756 || (SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
6760 #ifdef SECONDARY_MEMORY_NEEDED
6761 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6762 reload_reg_class[j],
6769 /* delete_output_reload is only invoked properly if old contains
6770 the original pseudo register. Since this is replaced with a
6771 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6772 find the pseudo in RELOAD_IN_REG. */
6774 && reload_override_in[j]
6775 && GET_CODE (reload_in_reg[j]) == REG)
6778 old = reload_in_reg[j];
6782 else if (GET_CODE (oldequiv) == REG)
6783 oldequiv_reg = oldequiv;
6784 else if (GET_CODE (oldequiv) == SUBREG)
6785 oldequiv_reg = SUBREG_REG (oldequiv);
6787 /* If we are reloading from a register that was recently stored in
6788 with an output-reload, see if we can prove there was
6789 actually no need to store the old value in it. */
6791 if (optimize && GET_CODE (oldequiv) == REG
6792 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6793 && spill_reg_store[REGNO (oldequiv)]
6794 && GET_CODE (old) == REG
6795 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6796 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6797 reload_out_reg[j])))
6798 delete_output_reload (insn, j, REGNO (oldequiv));
6800 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6801 then load RELOADREG from OLDEQUIV. Note that we cannot use
6802 gen_lowpart_common since it can do the wrong thing when
6803 RELOADREG has a multi-word mode. Note that RELOADREG
6804 must always be a REG here. */
6806 if (GET_MODE (reloadreg) != mode)
6807 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6808 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6809 oldequiv = SUBREG_REG (oldequiv);
6810 if (GET_MODE (oldequiv) != VOIDmode
6811 && mode != GET_MODE (oldequiv))
6812 oldequiv = gen_rtx_SUBREG (mode, oldequiv, 0);
6814 /* Switch to the right place to emit the reload insns. */
6815 switch (reload_when_needed[j])
6818 where = &other_input_reload_insns;
6820 case RELOAD_FOR_INPUT:
6821 where = &input_reload_insns[reload_opnum[j]];
6823 case RELOAD_FOR_INPUT_ADDRESS:
6824 where = &input_address_reload_insns[reload_opnum[j]];
6826 case RELOAD_FOR_INPADDR_ADDRESS:
6827 where = &inpaddr_address_reload_insns[reload_opnum[j]];
6829 case RELOAD_FOR_OUTPUT_ADDRESS:
6830 where = &output_address_reload_insns[reload_opnum[j]];
6832 case RELOAD_FOR_OUTADDR_ADDRESS:
6833 where = &outaddr_address_reload_insns[reload_opnum[j]];
6835 case RELOAD_FOR_OPERAND_ADDRESS:
6836 where = &operand_reload_insns;
6838 case RELOAD_FOR_OPADDR_ADDR:
6839 where = &other_operand_reload_insns;
6841 case RELOAD_FOR_OTHER_ADDRESS:
6842 where = &other_input_address_reload_insns;
6848 push_to_sequence (*where);
6851 /* Auto-increment addresses must be reloaded in a special way. */
6852 if (reload_out[j] && ! reload_out_reg[j])
6854 /* We are not going to bother supporting the case where a
6855 incremented register can't be copied directly from
6856 OLDEQUIV since this seems highly unlikely. */
6857 if (reload_secondary_in_reload[j] >= 0)
6860 if (reload_inherited[j])
6861 oldequiv = reloadreg;
6863 old = XEXP (reload_in_reg[j], 0);
6865 if (optimize && GET_CODE (oldequiv) == REG
6866 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6867 && spill_reg_store[REGNO (oldequiv)]
6868 && GET_CODE (old) == REG
6869 && (dead_or_set_p (insn,
6870 spill_reg_stored_to[REGNO (oldequiv)])
6871 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6873 delete_output_reload (insn, j, REGNO (oldequiv));
6875 /* Prevent normal processing of this reload. */
6877 /* Output a special code sequence for this case. */
6878 new_spill_reg_store[REGNO (reloadreg)]
6879 = inc_for_reload (reloadreg, oldequiv, reload_out[j],
6883 /* If we are reloading a pseudo-register that was set by the previous
6884 insn, see if we can get rid of that pseudo-register entirely
6885 by redirecting the previous insn into our reload register. */
6887 else if (optimize && GET_CODE (old) == REG
6888 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6889 && dead_or_set_p (insn, old)
6890 /* This is unsafe if some other reload
6891 uses the same reg first. */
6892 && ! conflicts_with_override (reloadreg)
6893 && free_for_value_p (REGNO (reloadreg), reload_mode[j],
6894 reload_opnum[j], reload_when_needed[j],
6895 old, reload_out[j], j, 0))
6897 rtx temp = PREV_INSN (insn);
6898 while (temp && GET_CODE (temp) == NOTE)
6899 temp = PREV_INSN (temp);
6901 && GET_CODE (temp) == INSN
6902 && GET_CODE (PATTERN (temp)) == SET
6903 && SET_DEST (PATTERN (temp)) == old
6904 /* Make sure we can access insn_operand_constraint. */
6905 && asm_noperands (PATTERN (temp)) < 0
6906 /* This is unsafe if prev insn rejects our reload reg. */
6907 && constraint_accepts_reg_p (insn_operand_constraint[recog_memoized (temp)][0],
6909 /* This is unsafe if operand occurs more than once in current
6910 insn. Perhaps some occurrences aren't reloaded. */
6911 && count_occurrences (PATTERN (insn), old) == 1
6912 /* Don't risk splitting a matching pair of operands. */
6913 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
6915 /* Store into the reload register instead of the pseudo. */
6916 SET_DEST (PATTERN (temp)) = reloadreg;
6918 /* If the previous insn is an output reload, the source is
6919 a reload register, and its spill_reg_store entry will
6920 contain the previous destination. This is now
6922 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6923 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6925 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6926 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6929 /* If these are the only uses of the pseudo reg,
6930 pretend for GDB it lives in the reload reg we used. */
6931 if (REG_N_DEATHS (REGNO (old)) == 1
6932 && REG_N_SETS (REGNO (old)) == 1)
6934 reg_renumber[REGNO (old)] = REGNO (reload_reg_rtx[j]);
6935 alter_reg (REGNO (old), -1);
6941 /* We can't do that, so output an insn to load RELOADREG. */
6945 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6946 rtx second_reload_reg = 0;
6947 enum insn_code icode;
6949 /* If we have a secondary reload, pick up the secondary register
6950 and icode, if any. If OLDEQUIV and OLD are different or
6951 if this is an in-out reload, recompute whether or not we
6952 still need a secondary register and what the icode should
6953 be. If we still need a secondary register and the class or
6954 icode is different, go back to reloading from OLD if using
6955 OLDEQUIV means that we got the wrong type of register. We
6956 cannot have different class or icode due to an in-out reload
6957 because we don't make such reloads when both the input and
6958 output need secondary reload registers. */
6960 if (reload_secondary_in_reload[j] >= 0)
6962 int secondary_reload = reload_secondary_in_reload[j];
6963 rtx real_oldequiv = oldequiv;
6967 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6968 and similarly for OLD.
6969 See comments in get_secondary_reload in reload.c. */
6970 /* If it is a pseudo that cannot be replaced with its
6971 equivalent MEM, we must fall back to reload_in, which
6972 will have all the necessary substitutions registered.
6973 Likewise for a pseudo that can't be replaced with its
6974 equivalent constant.
6976 Take extra care for subregs of such pseudos. Note that
6977 we cannot use reg_equiv_mem in this case because it is
6978 not in the right mode. */
6981 if (GET_CODE (tmp) == SUBREG)
6982 tmp = SUBREG_REG (tmp);
6983 if (GET_CODE (tmp) == REG
6984 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6985 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6986 || reg_equiv_constant[REGNO (tmp)] != 0))
6988 if (! reg_equiv_mem[REGNO (tmp)]
6989 || num_not_at_initial_offset
6990 || GET_CODE (oldequiv) == SUBREG)
6991 real_oldequiv = reload_in[j];
6993 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6997 if (GET_CODE (tmp) == SUBREG)
6998 tmp = SUBREG_REG (tmp);
6999 if (GET_CODE (tmp) == REG
7000 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7001 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
7002 || reg_equiv_constant[REGNO (tmp)] != 0))
7004 if (! reg_equiv_mem[REGNO (tmp)]
7005 || num_not_at_initial_offset
7006 || GET_CODE (old) == SUBREG)
7007 real_old = reload_in[j];
7009 real_old = reg_equiv_mem[REGNO (tmp)];
7012 second_reload_reg = reload_reg_rtx[secondary_reload];
7013 icode = reload_secondary_in_icode[j];
7015 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
7016 || (reload_in[j] != 0 && reload_out[j] != 0))
7018 enum reg_class new_class
7019 = SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
7020 mode, real_oldequiv);
7022 if (new_class == NO_REGS)
7023 second_reload_reg = 0;
7026 enum insn_code new_icode;
7027 enum machine_mode new_mode;
7029 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
7030 REGNO (second_reload_reg)))
7031 oldequiv = old, real_oldequiv = real_old;
7034 new_icode = reload_in_optab[(int) mode];
7035 if (new_icode != CODE_FOR_nothing
7036 && ((insn_operand_predicate[(int) new_icode][0]
7037 && ! ((*insn_operand_predicate[(int) new_icode][0])
7039 || (insn_operand_predicate[(int) new_icode][1]
7040 && ! ((*insn_operand_predicate[(int) new_icode][1])
7041 (real_oldequiv, mode)))))
7042 new_icode = CODE_FOR_nothing;
7044 if (new_icode == CODE_FOR_nothing)
7047 new_mode = insn_operand_mode[(int) new_icode][2];
7049 if (GET_MODE (second_reload_reg) != new_mode)
7051 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
7053 oldequiv = old, real_oldequiv = real_old;
7056 = gen_rtx_REG (new_mode,
7057 REGNO (second_reload_reg));
7063 /* If we still need a secondary reload register, check
7064 to see if it is being used as a scratch or intermediate
7065 register and generate code appropriately. If we need
7066 a scratch register, use REAL_OLDEQUIV since the form of
7067 the insn may depend on the actual address if it is
7070 if (second_reload_reg)
7072 if (icode != CODE_FOR_nothing)
7074 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
7075 second_reload_reg));
7080 /* See if we need a scratch register to load the
7081 intermediate register (a tertiary reload). */
7082 enum insn_code tertiary_icode
7083 = reload_secondary_in_icode[secondary_reload];
7085 if (tertiary_icode != CODE_FOR_nothing)
7087 rtx third_reload_reg
7088 = reload_reg_rtx[reload_secondary_in_reload[secondary_reload]];
7090 emit_insn ((GEN_FCN (tertiary_icode)
7091 (second_reload_reg, real_oldequiv,
7092 third_reload_reg)));
7095 gen_reload (second_reload_reg, real_oldequiv,
7097 reload_when_needed[j]);
7099 oldequiv = second_reload_reg;
7105 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
7107 rtx real_oldequiv = oldequiv;
7109 if ((GET_CODE (oldequiv) == REG
7110 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
7111 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
7112 || reg_equiv_constant[REGNO (oldequiv)] != 0))
7113 || (GET_CODE (oldequiv) == SUBREG
7114 && GET_CODE (SUBREG_REG (oldequiv)) == REG
7115 && (REGNO (SUBREG_REG (oldequiv))
7116 >= FIRST_PSEUDO_REGISTER)
7117 && ((reg_equiv_memory_loc
7118 [REGNO (SUBREG_REG (oldequiv))] != 0)
7119 || (reg_equiv_constant
7120 [REGNO (SUBREG_REG (oldequiv))] != 0))))
7121 real_oldequiv = reload_in[j];
7122 gen_reload (reloadreg, real_oldequiv, reload_opnum[j],
7123 reload_when_needed[j]);
7128 this_reload_insn = get_last_insn ();
7129 /* End this sequence. */
7130 *where = get_insns ();
7133 /* Update reload_override_in so that delete_address_reloads_1
7134 can see the actual register usage. */
7136 reload_override_in[j] = oldequiv;
7139 /* When inheriting a wider reload, we have a MEM in reload_in[j],
7140 e.g. inheriting a SImode output reload for
7141 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7142 if (optimize && reload_inherited[j] && reload_in[j]
7143 && GET_CODE (reload_in[j]) == MEM
7144 && GET_CODE (reload_in_reg[j]) == MEM
7145 && reload_spill_index[j] >= 0
7146 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7149 = count_occurrences (PATTERN (insn), reload_in[j]) == 1 ? 0 : -1;
7151 = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7154 /* If we are reloading a register that was recently stored in with an
7155 output-reload, see if we can prove there was
7156 actually no need to store the old value in it. */
7159 && (reload_inherited[j] || reload_override_in[j])
7160 && reload_reg_rtx[j]
7161 && GET_CODE (reload_reg_rtx[j]) == REG
7162 && spill_reg_store[REGNO (reload_reg_rtx[j])] != 0
7164 /* There doesn't seem to be any reason to restrict this to pseudos
7165 and doing so loses in the case where we are copying from a
7166 register of the wrong class. */
7167 && REGNO (spill_reg_stored_to[REGNO (reload_reg_rtx[j])])
7168 >= FIRST_PSEUDO_REGISTER
7170 /* The insn might have already some references to stackslots
7171 replaced by MEMs, while reload_out_reg still names the
7173 && (dead_or_set_p (insn,
7174 spill_reg_stored_to[REGNO (reload_reg_rtx[j])])
7175 || rtx_equal_p (spill_reg_stored_to[REGNO (reload_reg_rtx[j])],
7176 reload_out_reg[j])))
7177 delete_output_reload (insn, j, REGNO (reload_reg_rtx[j]));
7179 /* Input-reloading is done. Now do output-reloading,
7180 storing the value from the reload-register after the main insn
7181 if reload_out[j] is nonzero.
7183 ??? At some point we need to support handling output reloads of
7184 JUMP_INSNs or insns that set cc0. */
7186 /* If this is an output reload that stores something that is
7187 not loaded in this same reload, see if we can eliminate a previous
7190 rtx pseudo = reload_out_reg[j];
7193 && GET_CODE (pseudo) == REG
7194 && ! rtx_equal_p (reload_in_reg[j], pseudo)
7195 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7196 && reg_last_reload_reg[REGNO (pseudo)])
7198 int pseudo_no = REGNO (pseudo);
7199 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7201 /* We don't need to test full validity of last_regno for
7202 inherit here; we only want to know if the store actually
7203 matches the pseudo. */
7204 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7205 && reg_reloaded_contents[last_regno] == pseudo_no
7206 && spill_reg_store[last_regno]
7207 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7208 delete_output_reload (insn, j, last_regno);
7212 old = reload_out_reg[j];
7214 && reload_reg_rtx[j] != old
7215 && reload_reg_rtx[j] != 0)
7217 register rtx reloadreg = reload_reg_rtx[j];
7218 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
7219 register rtx second_reloadreg = 0;
7222 enum machine_mode mode;
7225 /* An output operand that dies right away does need a reload,
7226 but need not be copied from it. Show the new location in the
7228 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
7229 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7231 XEXP (note, 0) = reload_reg_rtx[j];
7234 /* Likewise for a SUBREG of an operand that dies. */
7235 else if (GET_CODE (old) == SUBREG
7236 && GET_CODE (SUBREG_REG (old)) == REG
7237 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7240 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
7244 else if (GET_CODE (old) == SCRATCH)
7245 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7246 but we don't want to make an output reload. */
7250 /* Strip off of OLD any size-increasing SUBREGs such as
7251 (SUBREG:SI foo:QI 0). */
7253 while (GET_CODE (old) == SUBREG && SUBREG_WORD (old) == 0
7254 && (GET_MODE_SIZE (GET_MODE (old))
7255 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (old)))))
7256 old = SUBREG_REG (old);
7259 /* If is a JUMP_INSN, we can't support output reloads yet. */
7260 if (GET_CODE (insn) == JUMP_INSN)
7263 if (reload_when_needed[j] == RELOAD_OTHER)
7266 push_to_sequence (output_reload_insns[reload_opnum[j]]);
7268 old = reload_out[j];
7270 /* Determine the mode to reload in.
7271 See comments above (for input reloading). */
7273 mode = GET_MODE (old);
7274 if (mode == VOIDmode)
7276 /* VOIDmode should never happen for an output. */
7277 if (asm_noperands (PATTERN (insn)) < 0)
7278 /* It's the compiler's fault. */
7279 fatal_insn ("VOIDmode on an output", insn);
7280 error_for_asm (insn, "output operand is constant in `asm'");
7281 /* Prevent crash--use something we know is valid. */
7283 old = gen_rtx_REG (mode, REGNO (reloadreg));
7286 if (GET_MODE (reloadreg) != mode)
7287 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
7289 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
7291 /* If we need two reload regs, set RELOADREG to the intermediate
7292 one, since it will be stored into OLD. We might need a secondary
7293 register only for an input reload, so check again here. */
7295 if (reload_secondary_out_reload[j] >= 0)
7299 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
7300 && reg_equiv_mem[REGNO (old)] != 0)
7301 real_old = reg_equiv_mem[REGNO (old)];
7303 if((SECONDARY_OUTPUT_RELOAD_CLASS (reload_reg_class[j],
7307 second_reloadreg = reloadreg;
7308 reloadreg = reload_reg_rtx[reload_secondary_out_reload[j]];
7310 /* See if RELOADREG is to be used as a scratch register
7311 or as an intermediate register. */
7312 if (reload_secondary_out_icode[j] != CODE_FOR_nothing)
7314 emit_insn ((GEN_FCN (reload_secondary_out_icode[j])
7315 (real_old, second_reloadreg, reloadreg)));
7320 /* See if we need both a scratch and intermediate reload
7323 int secondary_reload = reload_secondary_out_reload[j];
7324 enum insn_code tertiary_icode
7325 = reload_secondary_out_icode[secondary_reload];
7327 if (GET_MODE (reloadreg) != mode)
7328 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
7330 if (tertiary_icode != CODE_FOR_nothing)
7333 = reload_reg_rtx[reload_secondary_out_reload[secondary_reload]];
7336 /* Copy primary reload reg to secondary reload reg.
7337 (Note that these have been swapped above, then
7338 secondary reload reg to OLD using our insn. */
7340 /* If REAL_OLD is a paradoxical SUBREG, remove it
7341 and try to put the opposite SUBREG on
7343 if (GET_CODE (real_old) == SUBREG
7344 && (GET_MODE_SIZE (GET_MODE (real_old))
7345 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
7346 && 0 != (tem = gen_lowpart_common
7347 (GET_MODE (SUBREG_REG (real_old)),
7349 real_old = SUBREG_REG (real_old), reloadreg = tem;
7351 gen_reload (reloadreg, second_reloadreg,
7352 reload_opnum[j], reload_when_needed[j]);
7353 emit_insn ((GEN_FCN (tertiary_icode)
7354 (real_old, reloadreg, third_reloadreg)));
7359 /* Copy between the reload regs here and then to
7362 gen_reload (reloadreg, second_reloadreg,
7363 reload_opnum[j], reload_when_needed[j]);
7369 /* Output the last reload insn. */
7374 /* Don't output the last reload if OLD is not the dest of
7375 INSN and is in the src and is clobbered by INSN. */
7376 if (! flag_expensive_optimizations
7377 || GET_CODE (old) != REG
7378 || !(set = single_set (insn))
7379 || rtx_equal_p (old, SET_DEST (set))
7380 || !reg_mentioned_p (old, SET_SRC (set))
7381 || !regno_clobbered_p (REGNO (old), insn, reload_mode[j], 0))
7382 gen_reload (old, reloadreg, reload_opnum[j],
7383 reload_when_needed[j]);
7386 /* Look at all insns we emitted, just to be safe. */
7387 for (p = get_insns (); p; p = NEXT_INSN (p))
7388 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
7390 rtx pat = PATTERN (p);
7392 /* If this output reload doesn't come from a spill reg,
7393 clear any memory of reloaded copies of the pseudo reg.
7394 If this output reload comes from a spill reg,
7395 reg_has_output_reload will make this do nothing. */
7396 note_stores (pat, forget_old_reloads_1);
7398 if (reg_mentioned_p (reload_reg_rtx[j], pat))
7400 rtx set = single_set (insn);
7401 if (reload_spill_index[j] < 0
7403 && SET_SRC (set) == reload_reg_rtx[j])
7405 int src = REGNO (SET_SRC (set));
7407 reload_spill_index[j] = src;
7408 SET_HARD_REG_BIT (reg_is_output_reload, src);
7409 if (find_regno_note (insn, REG_DEAD, src))
7410 SET_HARD_REG_BIT (reg_reloaded_died, src);
7412 if (REGNO (reload_reg_rtx[j]) < FIRST_PSEUDO_REGISTER)
7414 int s = reload_secondary_out_reload[j];
7415 set = single_set (p);
7416 /* If this reload copies only to the secondary reload
7417 register, the secondary reload does the actual
7419 if (s >= 0 && set == NULL_RTX)
7420 ; /* We can't tell what function the secondary reload
7421 has and where the actual store to the pseudo is
7422 made; leave new_spill_reg_store alone. */
7424 && SET_SRC (set) == reload_reg_rtx[j]
7425 && SET_DEST (set) == reload_reg_rtx[s])
7427 /* Usually the next instruction will be the
7428 secondary reload insn; if we can confirm
7429 that it is, setting new_spill_reg_store to
7430 that insn will allow an extra optimization. */
7431 rtx s_reg = reload_reg_rtx[s];
7432 rtx next = NEXT_INSN (p);
7433 reload_out[s] = reload_out[j];
7434 reload_out_reg[s] = reload_out_reg[j];
7435 set = single_set (next);
7436 if (set && SET_SRC (set) == s_reg
7437 && ! new_spill_reg_store[REGNO (s_reg)])
7439 SET_HARD_REG_BIT (reg_is_output_reload,
7441 new_spill_reg_store[REGNO (s_reg)] = next;
7445 new_spill_reg_store[REGNO (reload_reg_rtx[j])] = p;
7450 if (reload_when_needed[j] == RELOAD_OTHER)
7452 emit_insns (other_output_reload_insns[reload_opnum[j]]);
7453 other_output_reload_insns[reload_opnum[j]] = get_insns ();
7456 output_reload_insns[reload_opnum[j]] = get_insns ();
7462 /* Now write all the insns we made for reloads in the order expected by
7463 the allocation functions. Prior to the insn being reloaded, we write
7464 the following reloads:
7466 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7468 RELOAD_OTHER reloads.
7470 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7471 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7472 RELOAD_FOR_INPUT reload for the operand.
7474 RELOAD_FOR_OPADDR_ADDRS reloads.
7476 RELOAD_FOR_OPERAND_ADDRESS reloads.
7478 After the insn being reloaded, we write the following:
7480 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7481 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7482 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7483 reloads for the operand. The RELOAD_OTHER output reloads are
7484 output in descending order by reload number. */
7486 emit_insns_before (other_input_address_reload_insns, insn);
7487 emit_insns_before (other_input_reload_insns, insn);
7489 for (j = 0; j < reload_n_operands; j++)
7491 emit_insns_before (inpaddr_address_reload_insns[j], insn);
7492 emit_insns_before (input_address_reload_insns[j], insn);
7493 emit_insns_before (input_reload_insns[j], insn);
7496 emit_insns_before (other_operand_reload_insns, insn);
7497 emit_insns_before (operand_reload_insns, insn);
7499 for (j = 0; j < reload_n_operands; j++)
7501 emit_insns_before (outaddr_address_reload_insns[j], following_insn);
7502 emit_insns_before (output_address_reload_insns[j], following_insn);
7503 emit_insns_before (output_reload_insns[j], following_insn);
7504 emit_insns_before (other_output_reload_insns[j], following_insn);
7507 /* Keep basic block info up to date. */
7510 if (BLOCK_HEAD (chain->block) == insn)
7511 BLOCK_HEAD (chain->block) = NEXT_INSN (before_insn);
7512 if (BLOCK_END (chain->block) == insn)
7513 BLOCK_END (chain->block) = PREV_INSN (following_insn);
7516 /* For all the spill regs newly reloaded in this instruction,
7517 record what they were reloaded from, so subsequent instructions
7518 can inherit the reloads.
7520 Update spill_reg_store for the reloads of this insn.
7521 Copy the elements that were updated in the loop above. */
7523 for (j = 0; j < n_reloads; j++)
7525 register int r = reload_order[j];
7526 register int i = reload_spill_index[r];
7528 /* If this is a non-inherited input reload from a pseudo, we must
7529 clear any memory of a previous store to the same pseudo. Only do
7530 something if there will not be an output reload for the pseudo
7532 if (reload_in_reg[r] != 0
7533 && ! (reload_inherited[r] || reload_override_in[r]))
7535 rtx reg = reload_in_reg[r];
7537 if (GET_CODE (reg) == SUBREG)
7538 reg = SUBREG_REG (reg);
7540 if (GET_CODE (reg) == REG
7541 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7542 && ! reg_has_output_reload[REGNO (reg)])
7544 int nregno = REGNO (reg);
7546 if (reg_last_reload_reg[nregno])
7548 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7550 if (reg_reloaded_contents[last_regno] == nregno)
7551 spill_reg_store[last_regno] = 0;
7556 /* I is nonneg if this reload used a register.
7557 If reload_reg_rtx[r] is 0, this is an optional reload
7558 that we opted to ignore. */
7560 if (i >= 0 && reload_reg_rtx[r] != 0)
7563 = HARD_REGNO_NREGS (i, GET_MODE (reload_reg_rtx[r]));
7565 int part_reaches_end = 0;
7566 int all_reaches_end = 1;
7568 /* For a multi register reload, we need to check if all or part
7569 of the value lives to the end. */
7570 for (k = 0; k < nr; k++)
7572 if (reload_reg_reaches_end_p (i + k, reload_opnum[r],
7573 reload_when_needed[r]))
7574 part_reaches_end = 1;
7576 all_reaches_end = 0;
7579 /* Ignore reloads that don't reach the end of the insn in
7581 if (all_reaches_end)
7583 /* First, clear out memory of what used to be in this spill reg.
7584 If consecutive registers are used, clear them all. */
7586 for (k = 0; k < nr; k++)
7587 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7589 /* Maybe the spill reg contains a copy of reload_out. */
7590 if (reload_out[r] != 0
7591 && (GET_CODE (reload_out[r]) == REG
7593 || ! reload_out_reg[r]
7595 || GET_CODE (reload_out_reg[r]) == REG))
7597 rtx out = (GET_CODE (reload_out[r]) == REG
7601 /* AUTO_INC */ : XEXP (reload_in_reg[r], 0));
7602 register int nregno = REGNO (out);
7603 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7604 : HARD_REGNO_NREGS (nregno,
7605 GET_MODE (reload_reg_rtx[r])));
7607 spill_reg_store[i] = new_spill_reg_store[i];
7608 spill_reg_stored_to[i] = out;
7609 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
7611 /* If NREGNO is a hard register, it may occupy more than
7612 one register. If it does, say what is in the
7613 rest of the registers assuming that both registers
7614 agree on how many words the object takes. If not,
7615 invalidate the subsequent registers. */
7617 if (nregno < FIRST_PSEUDO_REGISTER)
7618 for (k = 1; k < nnr; k++)
7619 reg_last_reload_reg[nregno + k]
7621 ? gen_rtx_REG (reg_raw_mode[REGNO (reload_reg_rtx[r]) + k],
7622 REGNO (reload_reg_rtx[r]) + k)
7625 /* Now do the inverse operation. */
7626 for (k = 0; k < nr; k++)
7628 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7629 reg_reloaded_contents[i + k]
7630 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7633 reg_reloaded_insn[i + k] = insn;
7634 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7638 /* Maybe the spill reg contains a copy of reload_in. Only do
7639 something if there will not be an output reload for
7640 the register being reloaded. */
7641 else if (reload_out_reg[r] == 0
7642 && reload_in[r] != 0
7643 && ((GET_CODE (reload_in[r]) == REG
7644 && REGNO (reload_in[r]) >= FIRST_PSEUDO_REGISTER
7645 && ! reg_has_output_reload[REGNO (reload_in[r])])
7646 || (GET_CODE (reload_in_reg[r]) == REG
7647 && ! reg_has_output_reload[REGNO (reload_in_reg[r])]))
7648 && ! reg_set_p (reload_reg_rtx[r], PATTERN (insn)))
7650 register int nregno;
7653 if (GET_CODE (reload_in[r]) == REG
7654 && REGNO (reload_in[r]) >= FIRST_PSEUDO_REGISTER)
7655 nregno = REGNO (reload_in[r]);
7656 else if (GET_CODE (reload_in_reg[r]) == REG)
7657 nregno = REGNO (reload_in_reg[r]);
7659 nregno = REGNO (XEXP (reload_in_reg[r], 0));
7661 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7662 : HARD_REGNO_NREGS (nregno,
7663 GET_MODE (reload_reg_rtx[r])));
7665 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
7667 if (nregno < FIRST_PSEUDO_REGISTER)
7668 for (k = 1; k < nnr; k++)
7669 reg_last_reload_reg[nregno + k]
7671 ? gen_rtx_REG (reg_raw_mode[REGNO (reload_reg_rtx[r]) + k],
7672 REGNO (reload_reg_rtx[r]) + k)
7675 /* Unless we inherited this reload, show we haven't
7676 recently done a store.
7677 Previous stores of inherited auto_inc expressions
7678 also have to be discarded. */
7679 if (! reload_inherited[r]
7680 || (reload_out[r] && ! reload_out_reg[r]))
7681 spill_reg_store[i] = 0;
7683 for (k = 0; k < nr; k++)
7685 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7686 reg_reloaded_contents[i + k]
7687 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7690 reg_reloaded_insn[i + k] = insn;
7691 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7696 /* However, if part of the reload reaches the end, then we must
7697 invalidate the old info for the part that survives to the end. */
7698 else if (part_reaches_end)
7700 for (k = 0; k < nr; k++)
7701 if (reload_reg_reaches_end_p (i + k,
7703 reload_when_needed[r]))
7704 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7708 /* The following if-statement was #if 0'd in 1.34 (or before...).
7709 It's reenabled in 1.35 because supposedly nothing else
7710 deals with this problem. */
7712 /* If a register gets output-reloaded from a non-spill register,
7713 that invalidates any previous reloaded copy of it.
7714 But forget_old_reloads_1 won't get to see it, because
7715 it thinks only about the original insn. So invalidate it here. */
7716 if (i < 0 && reload_out[r] != 0
7717 && (GET_CODE (reload_out[r]) == REG
7718 || (GET_CODE (reload_out[r]) == MEM
7719 && GET_CODE (reload_out_reg[r]) == REG)))
7721 rtx out = (GET_CODE (reload_out[r]) == REG
7722 ? reload_out[r] : reload_out_reg[r]);
7723 register int nregno = REGNO (out);
7724 if (nregno >= FIRST_PSEUDO_REGISTER)
7726 rtx src_reg, store_insn;
7728 reg_last_reload_reg[nregno] = 0;
7730 /* If we can find a hard register that is stored, record
7731 the storing insn so that we may delete this insn with
7732 delete_output_reload. */
7733 src_reg = reload_reg_rtx[r];
7735 /* If this is an optional reload, try to find the source reg
7736 from an input reload. */
7739 rtx set = single_set (insn);
7740 if (set && SET_DEST (set) == reload_out[r])
7744 src_reg = SET_SRC (set);
7746 for (k = 0; k < n_reloads; k++)
7748 if (reload_in[k] == src_reg)
7750 src_reg = reload_reg_rtx[k];
7757 store_insn = new_spill_reg_store[REGNO (src_reg)];
7758 if (src_reg && GET_CODE (src_reg) == REG
7759 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7761 int src_regno = REGNO (src_reg);
7762 int nr = HARD_REGNO_NREGS (src_regno, reload_mode[r]);
7763 /* The place where to find a death note varies with
7764 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7765 necessarily checked exactly in the code that moves
7766 notes, so just check both locations. */
7767 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7769 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7772 spill_reg_store[src_regno + nr] = store_insn;
7773 spill_reg_stored_to[src_regno + nr] = out;
7774 reg_reloaded_contents[src_regno + nr] = nregno;
7775 reg_reloaded_insn[src_regno + nr] = store_insn;
7776 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7777 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7778 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7780 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7782 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7784 reg_last_reload_reg[nregno] = src_reg;
7789 int num_regs = HARD_REGNO_NREGS (nregno,GET_MODE (reload_out[r]));
7791 while (num_regs-- > 0)
7792 reg_last_reload_reg[nregno + num_regs] = 0;
7796 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7799 /* Emit code to perform a reload from IN (which may be a reload register) to
7800 OUT (which may also be a reload register). IN or OUT is from operand
7801 OPNUM with reload type TYPE.
7803 Returns first insn emitted. */
7806 gen_reload (out, in, opnum, type)
7810 enum reload_type type;
7812 rtx last = get_last_insn ();
7815 /* If IN is a paradoxical SUBREG, remove it and try to put the
7816 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7817 if (GET_CODE (in) == SUBREG
7818 && (GET_MODE_SIZE (GET_MODE (in))
7819 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7820 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7821 in = SUBREG_REG (in), out = tem;
7822 else if (GET_CODE (out) == SUBREG
7823 && (GET_MODE_SIZE (GET_MODE (out))
7824 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7825 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7826 out = SUBREG_REG (out), in = tem;
7828 /* How to do this reload can get quite tricky. Normally, we are being
7829 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7830 register that didn't get a hard register. In that case we can just
7831 call emit_move_insn.
7833 We can also be asked to reload a PLUS that adds a register or a MEM to
7834 another register, constant or MEM. This can occur during frame pointer
7835 elimination and while reloading addresses. This case is handled by
7836 trying to emit a single insn to perform the add. If it is not valid,
7837 we use a two insn sequence.
7839 Finally, we could be called to handle an 'o' constraint by putting
7840 an address into a register. In that case, we first try to do this
7841 with a named pattern of "reload_load_address". If no such pattern
7842 exists, we just emit a SET insn and hope for the best (it will normally
7843 be valid on machines that use 'o').
7845 This entire process is made complex because reload will never
7846 process the insns we generate here and so we must ensure that
7847 they will fit their constraints and also by the fact that parts of
7848 IN might be being reloaded separately and replaced with spill registers.
7849 Because of this, we are, in some sense, just guessing the right approach
7850 here. The one listed above seems to work.
7852 ??? At some point, this whole thing needs to be rethought. */
7854 if (GET_CODE (in) == PLUS
7855 && (GET_CODE (XEXP (in, 0)) == REG
7856 || GET_CODE (XEXP (in, 0)) == SUBREG
7857 || GET_CODE (XEXP (in, 0)) == MEM)
7858 && (GET_CODE (XEXP (in, 1)) == REG
7859 || GET_CODE (XEXP (in, 1)) == SUBREG
7860 || CONSTANT_P (XEXP (in, 1))
7861 || GET_CODE (XEXP (in, 1)) == MEM))
7863 /* We need to compute the sum of a register or a MEM and another
7864 register, constant, or MEM, and put it into the reload
7865 register. The best possible way of doing this is if the machine
7866 has a three-operand ADD insn that accepts the required operands.
7868 The simplest approach is to try to generate such an insn and see if it
7869 is recognized and matches its constraints. If so, it can be used.
7871 It might be better not to actually emit the insn unless it is valid,
7872 but we need to pass the insn as an operand to `recog' and
7873 `extract_insn' and it is simpler to emit and then delete the insn if
7874 not valid than to dummy things up. */
7876 rtx op0, op1, tem, insn;
7879 op0 = find_replacement (&XEXP (in, 0));
7880 op1 = find_replacement (&XEXP (in, 1));
7882 /* Since constraint checking is strict, commutativity won't be
7883 checked, so we need to do that here to avoid spurious failure
7884 if the add instruction is two-address and the second operand
7885 of the add is the same as the reload reg, which is frequently
7886 the case. If the insn would be A = B + A, rearrange it so
7887 it will be A = A + B as constrain_operands expects. */
7889 if (GET_CODE (XEXP (in, 1)) == REG
7890 && REGNO (out) == REGNO (XEXP (in, 1)))
7891 tem = op0, op0 = op1, op1 = tem;
7893 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7894 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7896 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7897 code = recog_memoized (insn);
7901 extract_insn (insn);
7902 /* We want constrain operands to treat this insn strictly in
7903 its validity determination, i.e., the way it would after reload
7905 if (constrain_operands (1))
7909 delete_insns_since (last);
7911 /* If that failed, we must use a conservative two-insn sequence.
7912 use move to copy constant, MEM, or pseudo register to the reload
7913 register since "move" will be able to handle an arbitrary operand,
7914 unlike add which can't, in general. Then add the registers.
7916 If there is another way to do this for a specific machine, a
7917 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7920 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7922 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7923 || (GET_CODE (op1) == REG
7924 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7925 || (code != CODE_FOR_nothing
7926 && ! (*insn_operand_predicate[code][2]) (op1, insn_operand_mode[code][2])))
7927 tem = op0, op0 = op1, op1 = tem;
7929 gen_reload (out, op0, opnum, type);
7931 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7932 This fixes a problem on the 32K where the stack pointer cannot
7933 be used as an operand of an add insn. */
7935 if (rtx_equal_p (op0, op1))
7938 insn = emit_insn (gen_add2_insn (out, op1));
7940 /* If that failed, copy the address register to the reload register.
7941 Then add the constant to the reload register. */
7943 code = recog_memoized (insn);
7947 extract_insn (insn);
7948 /* We want constrain operands to treat this insn strictly in
7949 its validity determination, i.e., the way it would after reload
7951 if (constrain_operands (1))
7953 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7955 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7960 delete_insns_since (last);
7962 gen_reload (out, op1, opnum, type);
7963 insn = emit_insn (gen_add2_insn (out, op0));
7964 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7967 #ifdef SECONDARY_MEMORY_NEEDED
7968 /* If we need a memory location to do the move, do it that way. */
7969 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7970 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7971 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7972 REGNO_REG_CLASS (REGNO (out)),
7975 /* Get the memory to use and rewrite both registers to its mode. */
7976 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7978 if (GET_MODE (loc) != GET_MODE (out))
7979 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7981 if (GET_MODE (loc) != GET_MODE (in))
7982 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7984 gen_reload (loc, in, opnum, type);
7985 gen_reload (out, loc, opnum, type);
7989 /* If IN is a simple operand, use gen_move_insn. */
7990 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7991 emit_insn (gen_move_insn (out, in));
7993 #ifdef HAVE_reload_load_address
7994 else if (HAVE_reload_load_address)
7995 emit_insn (gen_reload_load_address (out, in));
7998 /* Otherwise, just write (set OUT IN) and hope for the best. */
8000 emit_insn (gen_rtx_SET (VOIDmode, out, in));
8002 /* Return the first insn emitted.
8003 We can not just return get_last_insn, because there may have
8004 been multiple instructions emitted. Also note that gen_move_insn may
8005 emit more than one insn itself, so we can not assume that there is one
8006 insn emitted per emit_insn_before call. */
8008 return last ? NEXT_INSN (last) : get_insns ();
8011 /* Delete a previously made output-reload
8012 whose result we now believe is not needed.
8013 First we double-check.
8015 INSN is the insn now being processed.
8016 LAST_RELOAD_REG is the hard register number for which we want to delete
8017 the last output reload.
8018 J is the reload-number that originally used REG. The caller has made
8019 certain that reload J doesn't use REG any longer for input. */
8022 delete_output_reload (insn, j, last_reload_reg)
8025 int last_reload_reg;
8027 rtx output_reload_insn = spill_reg_store[last_reload_reg];
8028 rtx reg = spill_reg_stored_to[last_reload_reg];
8031 int n_inherited = 0;
8035 /* Get the raw pseudo-register referred to. */
8037 while (GET_CODE (reg) == SUBREG)
8038 reg = SUBREG_REG (reg);
8039 substed = reg_equiv_memory_loc[REGNO (reg)];
8041 /* This is unsafe if the operand occurs more often in the current
8042 insn than it is inherited. */
8043 for (k = n_reloads - 1; k >= 0; k--)
8045 rtx reg2 = reload_in[k];
8048 if (GET_CODE (reg2) == MEM || reload_override_in[k])
8049 reg2 = reload_in_reg[k];
8051 if (reload_out[k] && ! reload_out_reg[k])
8052 reg2 = XEXP (reload_in_reg[k], 0);
8054 while (GET_CODE (reg2) == SUBREG)
8055 reg2 = SUBREG_REG (reg2);
8056 if (rtx_equal_p (reg2, reg))
8058 if (reload_inherited[k] || reload_override_in[k] || k == j)
8061 reg2 = reload_out_reg[k];
8064 while (GET_CODE (reg2) == SUBREG)
8065 reg2 = XEXP (reg2, 0);
8066 if (rtx_equal_p (reg2, reg))
8073 n_occurrences = count_occurrences (PATTERN (insn), reg);
8075 n_occurrences += count_occurrences (PATTERN (insn),
8076 eliminate_regs (substed, 0,
8078 if (n_occurrences > n_inherited)
8081 /* If the pseudo-reg we are reloading is no longer referenced
8082 anywhere between the store into it and here,
8083 and no jumps or labels intervene, then the value can get
8084 here through the reload reg alone.
8085 Otherwise, give up--return. */
8086 for (i1 = NEXT_INSN (output_reload_insn);
8087 i1 != insn; i1 = NEXT_INSN (i1))
8089 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
8091 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
8092 && reg_mentioned_p (reg, PATTERN (i1)))
8094 /* If this is USE in front of INSN, we only have to check that
8095 there are no more references than accounted for by inheritance. */
8096 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
8098 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8099 i1 = NEXT_INSN (i1);
8101 if (n_occurrences <= n_inherited && i1 == insn)
8107 /* The caller has already checked that REG dies or is set in INSN.
8108 It has also checked that we are optimizing, and thus some inaccurancies
8109 in the debugging information are acceptable.
8110 So we could just delete output_reload_insn.
8111 But in some cases we can improve the debugging information without
8112 sacrificing optimization - maybe even improving the code:
8113 See if the pseudo reg has been completely replaced
8114 with reload regs. If so, delete the store insn
8115 and forget we had a stack slot for the pseudo. */
8116 if (reload_out[j] != reload_in[j]
8117 && REG_N_DEATHS (REGNO (reg)) == 1
8118 && REG_N_SETS (REGNO (reg)) == 1
8119 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
8120 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8124 /* We know that it was used only between here
8125 and the beginning of the current basic block.
8126 (We also know that the last use before INSN was
8127 the output reload we are thinking of deleting, but never mind that.)
8128 Search that range; see if any ref remains. */
8129 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8131 rtx set = single_set (i2);
8133 /* Uses which just store in the pseudo don't count,
8134 since if they are the only uses, they are dead. */
8135 if (set != 0 && SET_DEST (set) == reg)
8137 if (GET_CODE (i2) == CODE_LABEL
8138 || GET_CODE (i2) == JUMP_INSN)
8140 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
8141 && reg_mentioned_p (reg, PATTERN (i2)))
8143 /* Some other ref remains; just delete the output reload we
8145 delete_address_reloads (output_reload_insn, insn);
8146 PUT_CODE (output_reload_insn, NOTE);
8147 NOTE_SOURCE_FILE (output_reload_insn) = 0;
8148 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
8153 /* Delete the now-dead stores into this pseudo. */
8154 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8156 rtx set = single_set (i2);
8158 if (set != 0 && SET_DEST (set) == reg)
8160 delete_address_reloads (i2, insn);
8161 /* This might be a basic block head,
8162 thus don't use delete_insn. */
8163 PUT_CODE (i2, NOTE);
8164 NOTE_SOURCE_FILE (i2) = 0;
8165 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
8167 if (GET_CODE (i2) == CODE_LABEL
8168 || GET_CODE (i2) == JUMP_INSN)
8172 /* For the debugging info,
8173 say the pseudo lives in this reload reg. */
8174 reg_renumber[REGNO (reg)] = REGNO (reload_reg_rtx[j]);
8175 alter_reg (REGNO (reg), -1);
8177 delete_address_reloads (output_reload_insn, insn);
8178 PUT_CODE (output_reload_insn, NOTE);
8179 NOTE_SOURCE_FILE (output_reload_insn) = 0;
8180 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
8184 /* We are going to delete DEAD_INSN. Recursively delete loads of
8185 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8186 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8188 delete_address_reloads (dead_insn, current_insn)
8189 rtx dead_insn, current_insn;
8191 rtx set = single_set (dead_insn);
8192 rtx set2, dst, prev, next;
8195 rtx dst = SET_DEST (set);
8196 if (GET_CODE (dst) == MEM)
8197 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8199 /* If we deleted the store from a reloaded post_{in,de}c expression,
8200 we can delete the matching adds. */
8201 prev = PREV_INSN (dead_insn);
8202 next = NEXT_INSN (dead_insn);
8203 if (! prev || ! next)
8205 set = single_set (next);
8206 set2 = single_set (prev);
8208 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8209 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
8210 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
8212 dst = SET_DEST (set);
8213 if (! rtx_equal_p (dst, SET_DEST (set2))
8214 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8215 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8216 || (INTVAL (XEXP (SET_SRC (set), 1))
8217 != - INTVAL (XEXP (SET_SRC (set2), 1))))
8223 /* Subfunction of delete_address_reloads: process registers found in X. */
8225 delete_address_reloads_1 (dead_insn, x, current_insn)
8226 rtx dead_insn, x, current_insn;
8228 rtx prev, set, dst, i2;
8230 enum rtx_code code = GET_CODE (x);
8234 char *fmt= GET_RTX_FORMAT (code);
8235 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8238 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8239 else if (fmt[i] == 'E')
8241 for (j = XVECLEN (x, i) - 1; j >=0; j--)
8242 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8249 if (spill_reg_order[REGNO (x)] < 0)
8252 /* Scan backwards for the insn that sets x. This might be a way back due
8254 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8256 code = GET_CODE (prev);
8257 if (code == CODE_LABEL || code == JUMP_INSN)
8259 if (GET_RTX_CLASS (code) != 'i')
8261 if (reg_set_p (x, PATTERN (prev)))
8263 if (reg_referenced_p (x, PATTERN (prev)))
8266 if (! prev || INSN_UID (prev) < reload_first_uid)
8268 /* Check that PREV only sets the reload register. */
8269 set = single_set (prev);
8272 dst = SET_DEST (set);
8273 if (GET_CODE (dst) != REG
8274 || ! rtx_equal_p (dst, x))
8276 if (! reg_set_p (dst, PATTERN (dead_insn)))
8278 /* Check if DST was used in a later insn -
8279 it might have been inherited. */
8280 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8282 if (GET_CODE (i2) == CODE_LABEL)
8284 if (GET_RTX_CLASS (GET_CODE (i2)) != 'i')
8286 if (reg_referenced_p (dst, PATTERN (i2)))
8288 /* If there is a reference to the register in the current insn,
8289 it might be loaded in a non-inherited reload. If no other
8290 reload uses it, that means the register is set before
8292 if (i2 == current_insn)
8294 for (j = n_reloads - 1; j >= 0; j--)
8295 if ((reload_reg_rtx[j] == dst && reload_inherited[j])
8296 || reload_override_in[j] == dst)
8298 for (j = n_reloads - 1; j >= 0; j--)
8299 if (reload_in[j] && reload_reg_rtx[j] == dst)
8306 if (GET_CODE (i2) == JUMP_INSN)
8308 /* If DST is still live at CURRENT_INSN, check if it is used for
8309 any reload. Note that even if CURRENT_INSN sets DST, we still
8310 have to check the reloads. */
8311 if (i2 == current_insn)
8313 for (j = n_reloads - 1; j >= 0; j--)
8314 if ((reload_reg_rtx[j] == dst && reload_inherited[j])
8315 || reload_override_in[j] == dst)
8317 /* ??? We can't finish the loop here, because dst might be
8318 allocated to a pseudo in this block if no reload in this
8319 block needs any of the clsses containing DST - see
8320 spill_hard_reg. There is no easy way to tell this, so we
8321 have to scan till the end of the basic block. */
8323 if (reg_set_p (dst, PATTERN (i2)))
8327 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8328 reg_reloaded_contents[REGNO (dst)] = -1;
8329 /* Can't use delete_insn here because PREV might be a basic block head. */
8330 PUT_CODE (prev, NOTE);
8331 NOTE_LINE_NUMBER (prev) = NOTE_INSN_DELETED;
8332 NOTE_SOURCE_FILE (prev) = 0;
8335 /* Output reload-insns to reload VALUE into RELOADREG.
8336 VALUE is an autoincrement or autodecrement RTX whose operand
8337 is a register or memory location;
8338 so reloading involves incrementing that location.
8339 IN is either identical to VALUE, or some cheaper place to reload from.
8341 INC_AMOUNT is the number to increment or decrement by (always positive).
8342 This cannot be deduced from VALUE.
8344 Return the instruction that stores into RELOADREG. */
8347 inc_for_reload (reloadreg, in, value, inc_amount)
8352 /* REG or MEM to be copied and incremented. */
8353 rtx incloc = XEXP (value, 0);
8354 /* Nonzero if increment after copying. */
8355 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
8361 rtx real_in = in == value ? XEXP (in, 0) : in;
8363 /* No hard register is equivalent to this register after
8364 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
8365 we could inc/dec that register as well (maybe even using it for
8366 the source), but I'm not sure it's worth worrying about. */
8367 if (GET_CODE (incloc) == REG)
8368 reg_last_reload_reg[REGNO (incloc)] = 0;
8370 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8371 inc_amount = - inc_amount;
8373 inc = GEN_INT (inc_amount);
8375 /* If this is post-increment, first copy the location to the reload reg. */
8376 if (post && real_in != reloadreg)
8377 emit_insn (gen_move_insn (reloadreg, real_in));
8381 /* See if we can directly increment INCLOC. Use a method similar to
8382 that in gen_reload. */
8384 last = get_last_insn ();
8385 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8386 gen_rtx_PLUS (GET_MODE (incloc),
8389 code = recog_memoized (add_insn);
8392 extract_insn (add_insn);
8393 if (constrain_operands (1))
8395 /* If this is a pre-increment and we have incremented the value
8396 where it lives, copy the incremented value to RELOADREG to
8397 be used as an address. */
8400 emit_insn (gen_move_insn (reloadreg, incloc));
8405 delete_insns_since (last);
8408 /* If couldn't do the increment directly, must increment in RELOADREG.
8409 The way we do this depends on whether this is pre- or post-increment.
8410 For pre-increment, copy INCLOC to the reload register, increment it
8411 there, then save back. */
8415 if (in != reloadreg)
8416 emit_insn (gen_move_insn (reloadreg, real_in));
8417 emit_insn (gen_add2_insn (reloadreg, inc));
8418 store = emit_insn (gen_move_insn (incloc, reloadreg));
8423 Because this might be a jump insn or a compare, and because RELOADREG
8424 may not be available after the insn in an input reload, we must do
8425 the incrementation before the insn being reloaded for.
8427 We have already copied IN to RELOADREG. Increment the copy in
8428 RELOADREG, save that back, then decrement RELOADREG so it has
8429 the original value. */
8431 emit_insn (gen_add2_insn (reloadreg, inc));
8432 store = emit_insn (gen_move_insn (incloc, reloadreg));
8433 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
8439 /* Return 1 if we are certain that the constraint-string STRING allows
8440 the hard register REG. Return 0 if we can't be sure of this. */
8443 constraint_accepts_reg_p (string, reg)
8448 int regno = true_regnum (reg);
8451 /* Initialize for first alternative. */
8453 /* Check that each alternative contains `g' or `r'. */
8455 switch (c = *string++)
8458 /* If an alternative lacks `g' or `r', we lose. */
8461 /* If an alternative lacks `g' or `r', we lose. */
8464 /* Initialize for next alternative. */
8469 /* Any general reg wins for this alternative. */
8470 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
8474 /* Any reg in specified class wins for this alternative. */
8476 enum reg_class class = REG_CLASS_FROM_LETTER (c);
8478 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
8484 /* Return the number of places FIND appears within X, but don't count
8485 an occurrence if some SET_DEST is FIND. */
8488 count_occurrences (x, find)
8489 register rtx x, find;
8492 register enum rtx_code code;
8493 register char *format_ptr;
8501 code = GET_CODE (x);
8516 if (GET_CODE (find) == MEM && rtx_equal_p (x, find))
8520 if (SET_DEST (x) == find)
8521 return count_occurrences (SET_SRC (x), find);
8528 format_ptr = GET_RTX_FORMAT (code);
8531 for (i = 0; i < GET_RTX_LENGTH (code); i++)
8533 switch (*format_ptr++)
8536 count += count_occurrences (XEXP (x, i), find);
8540 if (XVEC (x, i) != NULL)
8542 for (j = 0; j < XVECLEN (x, i); j++)
8543 count += count_occurrences (XVECEXP (x, i, j), find);
8551 /* This array holds values which are equivalent to a hard register
8552 during reload_cse_regs. Each array element is an EXPR_LIST of
8553 values. Each time a hard register is set, we set the corresponding
8554 array element to the value. Each time a hard register is copied
8555 into memory, we add the memory location to the corresponding array
8556 element. We don't store values or memory addresses with side
8557 effects in this array.
8559 If the value is a CONST_INT, then the mode of the containing
8560 EXPR_LIST is the mode in which that CONST_INT was referenced.
8562 We sometimes clobber a specific entry in a list. In that case, we
8563 just set XEXP (list-entry, 0) to 0. */
8565 static rtx *reg_values;
8567 /* This is a preallocated REG rtx which we use as a temporary in
8568 reload_cse_invalidate_regno, so that we don't need to allocate a
8569 new one each time through a loop in that function. */
8571 static rtx invalidate_regno_rtx;
8573 /* Invalidate any entries in reg_values which depend on REGNO,
8574 including those for REGNO itself. This is called if REGNO is
8575 changing. If CLOBBER is true, then always forget anything we
8576 currently know about REGNO. MODE is the mode of the assignment to
8577 REGNO, which is used to determine how many hard registers are being
8578 changed. If MODE is VOIDmode, then only REGNO is being changed;
8579 this is used when invalidating call clobbered registers across a
8583 reload_cse_invalidate_regno (regno, mode, clobber)
8585 enum machine_mode mode;
8591 /* Our callers don't always go through true_regnum; we may see a
8592 pseudo-register here from a CLOBBER or the like. We probably
8593 won't ever see a pseudo-register that has a real register number,
8594 for we check anyhow for safety. */
8595 if (regno >= FIRST_PSEUDO_REGISTER)
8596 regno = reg_renumber[regno];
8600 if (mode == VOIDmode)
8601 endregno = regno + 1;
8603 endregno = regno + HARD_REGNO_NREGS (regno, mode);
8606 for (i = regno; i < endregno; i++)
8609 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8613 for (x = reg_values[i]; x; x = XEXP (x, 1))
8615 if (XEXP (x, 0) != 0
8616 && refers_to_regno_p (regno, endregno, XEXP (x, 0), NULL_PTR))
8618 /* If this is the only entry on the list, clear
8619 reg_values[i]. Otherwise, just clear this entry on
8621 if (XEXP (x, 1) == 0 && x == reg_values[i])
8631 /* We must look at earlier registers, in case REGNO is part of a
8632 multi word value but is not the first register. If an earlier
8633 register has a value in a mode which overlaps REGNO, then we must
8634 invalidate that earlier register. Note that we do not need to
8635 check REGNO or later registers (we must not check REGNO itself,
8636 because we would incorrectly conclude that there was a conflict). */
8638 for (i = 0; i < regno; i++)
8642 for (x = reg_values[i]; x; x = XEXP (x, 1))
8644 if (XEXP (x, 0) != 0)
8646 PUT_MODE (invalidate_regno_rtx, GET_MODE (x));
8647 REGNO (invalidate_regno_rtx) = i;
8648 if (refers_to_regno_p (regno, endregno, invalidate_regno_rtx,
8651 reload_cse_invalidate_regno (i, VOIDmode, 1);
8659 /* The memory at address MEM_BASE is being changed.
8660 Return whether this change will invalidate VAL. */
8663 reload_cse_mem_conflict_p (mem_base, val)
8671 code = GET_CODE (val);
8674 /* Get rid of a few simple cases quickly. */
8687 if (GET_MODE (mem_base) == BLKmode
8688 || GET_MODE (val) == BLKmode)
8690 if (anti_dependence (val, mem_base))
8692 /* The address may contain nested MEMs. */
8699 fmt = GET_RTX_FORMAT (code);
8701 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8705 if (reload_cse_mem_conflict_p (mem_base, XEXP (val, i)))
8708 else if (fmt[i] == 'E')
8712 for (j = 0; j < XVECLEN (val, i); j++)
8713 if (reload_cse_mem_conflict_p (mem_base, XVECEXP (val, i, j)))
8721 /* Invalidate any entries in reg_values which are changed because of a
8722 store to MEM_RTX. If this is called because of a non-const call
8723 instruction, MEM_RTX is (mem:BLK const0_rtx). */
8726 reload_cse_invalidate_mem (mem_rtx)
8731 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8735 for (x = reg_values[i]; x; x = XEXP (x, 1))
8737 if (XEXP (x, 0) != 0
8738 && reload_cse_mem_conflict_p (mem_rtx, XEXP (x, 0)))
8740 /* If this is the only entry on the list, clear
8741 reg_values[i]. Otherwise, just clear this entry on
8743 if (XEXP (x, 1) == 0 && x == reg_values[i])
8754 /* Invalidate DEST, which is being assigned to or clobbered. The
8755 second parameter exists so that this function can be passed to
8756 note_stores; it is ignored. */
8759 reload_cse_invalidate_rtx (dest, ignore)
8761 rtx ignore ATTRIBUTE_UNUSED;
8763 while (GET_CODE (dest) == STRICT_LOW_PART
8764 || GET_CODE (dest) == SIGN_EXTRACT
8765 || GET_CODE (dest) == ZERO_EXTRACT
8766 || GET_CODE (dest) == SUBREG)
8767 dest = XEXP (dest, 0);
8769 if (GET_CODE (dest) == REG)
8770 reload_cse_invalidate_regno (REGNO (dest), GET_MODE (dest), 1);
8771 else if (GET_CODE (dest) == MEM)
8772 reload_cse_invalidate_mem (dest);
8775 /* Do a very simple CSE pass over the hard registers.
8777 This function detects no-op moves where we happened to assign two
8778 different pseudo-registers to the same hard register, and then
8779 copied one to the other. Reload will generate a useless
8780 instruction copying a register to itself.
8782 This function also detects cases where we load a value from memory
8783 into two different registers, and (if memory is more expensive than
8784 registers) changes it to simply copy the first register into the
8787 Another optimization is performed that scans the operands of each
8788 instruction to see whether the value is already available in a
8789 hard register. It then replaces the operand with the hard register
8790 if possible, much like an optional reload would. */
8793 reload_cse_regs_1 (first)
8801 init_alias_analysis ();
8803 reg_values = (rtx *) alloca (FIRST_PSEUDO_REGISTER * sizeof (rtx));
8804 bzero ((char *)reg_values, FIRST_PSEUDO_REGISTER * sizeof (rtx));
8806 /* Create our EXPR_LIST structures on reload_obstack, so that we can
8807 free them when we are done. */
8808 push_obstacks (&reload_obstack, &reload_obstack);
8809 firstobj = (char *) obstack_alloc (&reload_obstack, 0);
8811 /* We pass this to reload_cse_invalidate_mem to invalidate all of
8812 memory for a non-const call instruction. */
8813 callmem = gen_rtx_MEM (BLKmode, const0_rtx);
8815 /* This is used in reload_cse_invalidate_regno to avoid consing a
8816 new REG in a loop in that function. */
8817 invalidate_regno_rtx = gen_rtx_REG (VOIDmode, 0);
8819 for (insn = first; insn; insn = NEXT_INSN (insn))
8823 if (GET_CODE (insn) == CODE_LABEL)
8825 /* Forget all the register values at a code label. We don't
8826 try to do anything clever around jumps. */
8827 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8833 #ifdef NON_SAVING_SETJMP
8834 if (NON_SAVING_SETJMP && GET_CODE (insn) == NOTE
8835 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
8837 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8844 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
8847 /* If this is a call instruction, forget anything stored in a
8848 call clobbered register, or, if this is not a const call, in
8850 if (GET_CODE (insn) == CALL_INSN)
8852 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8853 if (call_used_regs[i])
8854 reload_cse_invalidate_regno (i, VOIDmode, 1);
8856 if (! CONST_CALL_P (insn))
8857 reload_cse_invalidate_mem (callmem);
8861 /* Forget all the register values at a volatile asm. */
8862 if (GET_CODE (insn) == INSN
8863 && GET_CODE (PATTERN (insn)) == ASM_OPERANDS
8864 && MEM_VOLATILE_P (PATTERN (insn)))
8865 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8868 body = PATTERN (insn);
8869 if (GET_CODE (body) == SET)
8872 if (reload_cse_noop_set_p (body, insn))
8874 /* If this sets the return value of the function, we must keep
8875 a USE around, in case this is in a different basic block
8876 than the final USE. Otherwise, we could loose important
8877 register lifeness information on SMALL_REGISTER_CLASSES
8878 machines, where return registers might be used as spills:
8879 subsequent passes assume that spill registers are dead at
8880 the end of a basic block. */
8881 if (REG_FUNCTION_VALUE_P (SET_DEST (body)))
8884 PATTERN (insn) = gen_rtx_USE (VOIDmode, SET_DEST (body));
8885 INSN_CODE (insn) = -1;
8886 REG_NOTES (insn) = NULL_RTX;
8887 push_obstacks (&reload_obstack, &reload_obstack);
8891 PUT_CODE (insn, NOTE);
8892 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8893 NOTE_SOURCE_FILE (insn) = 0;
8896 /* We're done with this insn. */
8900 /* It's not a no-op, but we can try to simplify it. */
8901 count += reload_cse_simplify_set (body, insn);
8904 apply_change_group ();
8906 reload_cse_simplify_operands (insn);
8908 reload_cse_record_set (body, body);
8910 else if (GET_CODE (body) == PARALLEL)
8913 rtx value = NULL_RTX;
8915 /* If every action in a PARALLEL is a noop, we can delete
8916 the entire PARALLEL. */
8917 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8919 rtx part = XVECEXP (body, 0, i);
8920 if (GET_CODE (part) == SET)
8922 if (! reload_cse_noop_set_p (part, insn))
8924 if (REG_FUNCTION_VALUE_P (SET_DEST (part)))
8928 value = SET_DEST (part);
8931 else if (GET_CODE (part) != CLOBBER)
8939 PATTERN (insn) = gen_rtx_USE (VOIDmode, value);
8940 INSN_CODE (insn) = -1;
8941 REG_NOTES (insn) = NULL_RTX;
8942 push_obstacks (&reload_obstack, &reload_obstack);
8946 PUT_CODE (insn, NOTE);
8947 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8948 NOTE_SOURCE_FILE (insn) = 0;
8951 /* We're done with this insn. */
8955 /* It's not a no-op, but we can try to simplify it. */
8956 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8957 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
8958 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
8961 apply_change_group ();
8963 reload_cse_simplify_operands (insn);
8965 /* Look through the PARALLEL and record the values being
8966 set, if possible. Also handle any CLOBBERs. */
8967 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8969 rtx x = XVECEXP (body, 0, i);
8971 if (GET_CODE (x) == SET)
8972 reload_cse_record_set (x, body);
8974 note_stores (x, reload_cse_invalidate_rtx);
8978 note_stores (body, reload_cse_invalidate_rtx);
8981 /* Clobber any registers which appear in REG_INC notes. We
8982 could keep track of the changes to their values, but it is
8983 unlikely to help. */
8987 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
8988 if (REG_NOTE_KIND (x) == REG_INC)
8989 reload_cse_invalidate_rtx (XEXP (x, 0), NULL_RTX);
8993 /* Look for any CLOBBERs in CALL_INSN_FUNCTION_USAGE, but only
8994 after we have processed the insn. */
8995 if (GET_CODE (insn) == CALL_INSN)
8999 for (x = CALL_INSN_FUNCTION_USAGE (insn); x; x = XEXP (x, 1))
9000 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
9001 reload_cse_invalidate_rtx (XEXP (XEXP (x, 0), 0), NULL_RTX);
9005 /* Free all the temporary structures we created, and go back to the
9006 regular obstacks. */
9007 obstack_free (&reload_obstack, firstobj);
9011 /* Call cse / combine like post-reload optimization phases.
9012 FIRST is the first instruction. */
9014 reload_cse_regs (first)
9017 reload_cse_regs_1 (first);
9019 reload_cse_move2add (first);
9020 if (flag_expensive_optimizations)
9021 reload_cse_regs_1 (first);
9024 /* Return whether the values known for REGNO are equal to VAL. MODE
9025 is the mode of the object that VAL is being copied to; this matters
9026 if VAL is a CONST_INT. */
9029 reload_cse_regno_equal_p (regno, val, mode)
9032 enum machine_mode mode;
9039 for (x = reg_values[regno]; x; x = XEXP (x, 1))
9040 if (XEXP (x, 0) != 0
9041 && rtx_equal_p (XEXP (x, 0), val)
9042 && (! flag_float_store || GET_CODE (XEXP (x, 0)) != MEM
9043 || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT)
9044 && (GET_CODE (val) != CONST_INT
9045 || mode == GET_MODE (x)
9046 || (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
9047 /* On a big endian machine if the value spans more than
9048 one register then this register holds the high part of
9049 it and we can't use it.
9051 ??? We should also compare with the high part of the
9053 && !(WORDS_BIG_ENDIAN
9054 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
9055 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
9056 GET_MODE_BITSIZE (GET_MODE (x))))))
9062 /* See whether a single set is a noop. SET is the set instruction we
9063 are should check, and INSN is the instruction from which it came. */
9066 reload_cse_noop_set_p (set, insn)
9071 enum machine_mode dest_mode;
9075 src = SET_SRC (set);
9076 dest = SET_DEST (set);
9077 dest_mode = GET_MODE (dest);
9079 if (side_effects_p (src))
9082 dreg = true_regnum (dest);
9083 sreg = true_regnum (src);
9085 /* Check for setting a register to itself. In this case, we don't
9086 have to worry about REG_DEAD notes. */
9087 if (dreg >= 0 && dreg == sreg)
9093 /* Check for setting a register to itself. */
9097 /* Check for setting a register to a value which we already know
9098 is in the register. */
9099 else if (reload_cse_regno_equal_p (dreg, src, dest_mode))
9102 /* Check for setting a register DREG to another register SREG
9103 where SREG is equal to a value which is already in DREG. */
9108 for (x = reg_values[sreg]; x; x = XEXP (x, 1))
9112 if (XEXP (x, 0) == 0)
9115 if (dest_mode == GET_MODE (x))
9117 else if (GET_MODE_BITSIZE (dest_mode)
9118 < GET_MODE_BITSIZE (GET_MODE (x)))
9119 tmp = gen_lowpart_common (dest_mode, XEXP (x, 0));
9124 && reload_cse_regno_equal_p (dreg, tmp, dest_mode))
9132 else if (GET_CODE (dest) == MEM)
9134 /* Check for storing a register to memory when we know that the
9135 register is equivalent to the memory location. */
9137 && reload_cse_regno_equal_p (sreg, dest, dest_mode)
9138 && ! side_effects_p (dest))
9145 /* Try to simplify a single SET instruction. SET is the set pattern.
9146 INSN is the instruction it came from.
9147 This function only handles one case: if we set a register to a value
9148 which is not a register, we try to find that value in some other register
9149 and change the set into a register copy. */
9152 reload_cse_simplify_set (set, insn)
9158 enum machine_mode dest_mode;
9159 enum reg_class dclass;
9162 dreg = true_regnum (SET_DEST (set));
9166 src = SET_SRC (set);
9167 if (side_effects_p (src) || true_regnum (src) >= 0)
9170 dclass = REGNO_REG_CLASS (dreg);
9172 /* If memory loads are cheaper than register copies, don't change them. */
9173 if (GET_CODE (src) == MEM
9174 && MEMORY_MOVE_COST (GET_MODE (src), dclass, 1) < 2)
9177 /* If the constant is cheaper than a register, don't change it. */
9178 if (CONSTANT_P (src)
9179 && rtx_cost (src, SET) < 2)
9182 dest_mode = GET_MODE (SET_DEST (set));
9183 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
9186 && REGISTER_MOVE_COST (REGNO_REG_CLASS (i), dclass) == 2
9187 && reload_cse_regno_equal_p (i, src, dest_mode))
9191 /* Pop back to the real obstacks while changing the insn. */
9194 validated = validate_change (insn, &SET_SRC (set),
9195 gen_rtx_REG (dest_mode, i), 1);
9197 /* Go back to the obstack we are using for temporary
9199 push_obstacks (&reload_obstack, &reload_obstack);
9208 /* Try to replace operands in INSN with equivalent values that are already
9209 in registers. This can be viewed as optional reloading.
9211 For each non-register operand in the insn, see if any hard regs are
9212 known to be equivalent to that operand. Record the alternatives which
9213 can accept these hard registers. Among all alternatives, select the
9214 ones which are better or equal to the one currently matching, where
9215 "better" is in terms of '?' and '!' constraints. Among the remaining
9216 alternatives, select the one which replaces most operands with
9220 reload_cse_simplify_operands (insn)
9223 #ifdef REGISTER_CONSTRAINTS
9226 const char *constraints[MAX_RECOG_OPERANDS];
9228 /* Vector recording how bad an alternative is. */
9229 int *alternative_reject;
9230 /* Vector recording how many registers can be introduced by choosing
9231 this alternative. */
9232 int *alternative_nregs;
9233 /* Array of vectors recording, for each operand and each alternative,
9234 which hard register to substitute, or -1 if the operand should be
9236 int *op_alt_regno[MAX_RECOG_OPERANDS];
9237 /* Array of alternatives, sorted in order of decreasing desirability. */
9238 int *alternative_order;
9239 rtx reg = gen_rtx_REG (VOIDmode, -1);
9241 extract_insn (insn);
9243 if (recog_n_alternatives == 0 || recog_n_operands == 0)
9246 /* Figure out which alternative currently matches. */
9247 if (! constrain_operands (1))
9248 fatal_insn_not_found (insn);
9250 alternative_reject = (int *) alloca (recog_n_alternatives * sizeof (int));
9251 alternative_nregs = (int *) alloca (recog_n_alternatives * sizeof (int));
9252 alternative_order = (int *) alloca (recog_n_alternatives * sizeof (int));
9253 bzero ((char *)alternative_reject, recog_n_alternatives * sizeof (int));
9254 bzero ((char *)alternative_nregs, recog_n_alternatives * sizeof (int));
9256 for (i = 0; i < recog_n_operands; i++)
9258 enum machine_mode mode;
9262 op_alt_regno[i] = (int *) alloca (recog_n_alternatives * sizeof (int));
9263 for (j = 0; j < recog_n_alternatives; j++)
9264 op_alt_regno[i][j] = -1;
9266 p = constraints[i] = recog_constraints[i];
9267 mode = recog_operand_mode[i];
9269 /* Add the reject values for each alternative given by the constraints
9270 for this operand. */
9278 alternative_reject[j] += 3;
9280 alternative_reject[j] += 300;
9283 /* We won't change operands which are already registers. We
9284 also don't want to modify output operands. */
9285 regno = true_regnum (recog_operand[i]);
9287 || constraints[i][0] == '='
9288 || constraints[i][0] == '+')
9291 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
9293 int class = (int) NO_REGS;
9295 if (! reload_cse_regno_equal_p (regno, recog_operand[i], mode))
9298 REGNO (reg) = regno;
9299 PUT_MODE (reg, mode);
9301 /* We found a register equal to this operand. Now look for all
9302 alternatives that can accept this register and have not been
9303 assigned a register they can use yet. */
9312 case '=': case '+': case '?':
9313 case '#': case '&': case '!':
9315 case '0': case '1': case '2': case '3': case '4':
9316 case 'm': case '<': case '>': case 'V': case 'o':
9317 case 'E': case 'F': case 'G': case 'H':
9318 case 's': case 'i': case 'n':
9319 case 'I': case 'J': case 'K': case 'L':
9320 case 'M': case 'N': case 'O': case 'P':
9321 #ifdef EXTRA_CONSTRAINT
9322 case 'Q': case 'R': case 'S': case 'T': case 'U':
9325 /* These don't say anything we care about. */
9329 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
9334 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)];
9337 case ',': case '\0':
9338 /* See if REGNO fits this alternative, and set it up as the
9339 replacement register if we don't have one for this
9340 alternative yet and the operand being replaced is not
9341 a cheap CONST_INT. */
9342 if (op_alt_regno[i][j] == -1
9343 && reg_fits_class_p (reg, class, 0, mode)
9344 && (GET_CODE (recog_operand[i]) != CONST_INT
9345 || rtx_cost (recog_operand[i], SET) > rtx_cost (reg, SET)))
9347 alternative_nregs[j]++;
9348 op_alt_regno[i][j] = regno;
9360 /* Record all alternatives which are better or equal to the currently
9361 matching one in the alternative_order array. */
9362 for (i = j = 0; i < recog_n_alternatives; i++)
9363 if (alternative_reject[i] <= alternative_reject[which_alternative])
9364 alternative_order[j++] = i;
9365 recog_n_alternatives = j;
9367 /* Sort it. Given a small number of alternatives, a dumb algorithm
9368 won't hurt too much. */
9369 for (i = 0; i < recog_n_alternatives - 1; i++)
9372 int best_reject = alternative_reject[alternative_order[i]];
9373 int best_nregs = alternative_nregs[alternative_order[i]];
9376 for (j = i + 1; j < recog_n_alternatives; j++)
9378 int this_reject = alternative_reject[alternative_order[j]];
9379 int this_nregs = alternative_nregs[alternative_order[j]];
9381 if (this_reject < best_reject
9382 || (this_reject == best_reject && this_nregs < best_nregs))
9385 best_reject = this_reject;
9386 best_nregs = this_nregs;
9390 tmp = alternative_order[best];
9391 alternative_order[best] = alternative_order[i];
9392 alternative_order[i] = tmp;
9395 /* Substitute the operands as determined by op_alt_regno for the best
9397 j = alternative_order[0];
9399 /* Pop back to the real obstacks while changing the insn. */
9402 for (i = 0; i < recog_n_operands; i++)
9404 enum machine_mode mode = recog_operand_mode[i];
9405 if (op_alt_regno[i][j] == -1)
9408 validate_change (insn, recog_operand_loc[i],
9409 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
9412 for (i = recog_n_dups - 1; i >= 0; i--)
9414 int op = recog_dup_num[i];
9415 enum machine_mode mode = recog_operand_mode[op];
9417 if (op_alt_regno[op][j] == -1)
9420 validate_change (insn, recog_dup_loc[i],
9421 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
9424 /* Go back to the obstack we are using for temporary
9426 push_obstacks (&reload_obstack, &reload_obstack);
9428 return apply_change_group ();
9434 /* These two variables are used to pass information from
9435 reload_cse_record_set to reload_cse_check_clobber. */
9437 static int reload_cse_check_clobbered;
9438 static rtx reload_cse_check_src;
9440 /* See if DEST overlaps with RELOAD_CSE_CHECK_SRC. If it does, set
9441 RELOAD_CSE_CHECK_CLOBBERED. This is called via note_stores. The
9442 second argument, which is passed by note_stores, is ignored. */
9445 reload_cse_check_clobber (dest, ignore)
9447 rtx ignore ATTRIBUTE_UNUSED;
9449 if (reg_overlap_mentioned_p (dest, reload_cse_check_src))
9450 reload_cse_check_clobbered = 1;
9453 /* Record the result of a SET instruction. SET is the set pattern.
9454 BODY is the pattern of the insn that it came from. */
9457 reload_cse_record_set (set, body)
9463 enum machine_mode dest_mode;
9465 dest = SET_DEST (set);
9466 src = SET_SRC (set);
9467 dreg = true_regnum (dest);
9468 sreg = true_regnum (src);
9469 dest_mode = GET_MODE (dest);
9471 /* Some machines don't define AUTO_INC_DEC, but they still use push
9472 instructions. We need to catch that case here in order to
9473 invalidate the stack pointer correctly. Note that invalidating
9474 the stack pointer is different from invalidating DEST. */
9476 while (GET_CODE (x) == SUBREG
9477 || GET_CODE (x) == ZERO_EXTRACT
9478 || GET_CODE (x) == SIGN_EXTRACT
9479 || GET_CODE (x) == STRICT_LOW_PART)
9481 if (push_operand (x, GET_MODE (x)))
9483 reload_cse_invalidate_rtx (stack_pointer_rtx, NULL_RTX);
9484 reload_cse_invalidate_rtx (dest, NULL_RTX);
9488 /* We can only handle an assignment to a register, or a store of a
9489 register to a memory location. For other cases, we just clobber
9490 the destination. We also have to just clobber if there are side
9491 effects in SRC or DEST. */
9492 if ((dreg < 0 && GET_CODE (dest) != MEM)
9493 || side_effects_p (src)
9494 || side_effects_p (dest))
9496 reload_cse_invalidate_rtx (dest, NULL_RTX);
9501 /* We don't try to handle values involving CC, because it's a pain
9502 to keep track of when they have to be invalidated. */
9503 if (reg_mentioned_p (cc0_rtx, src)
9504 || reg_mentioned_p (cc0_rtx, dest))
9506 reload_cse_invalidate_rtx (dest, NULL_RTX);
9511 /* If BODY is a PARALLEL, then we need to see whether the source of
9512 SET is clobbered by some other instruction in the PARALLEL. */
9513 if (GET_CODE (body) == PARALLEL)
9517 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
9521 x = XVECEXP (body, 0, i);
9525 reload_cse_check_clobbered = 0;
9526 reload_cse_check_src = src;
9527 note_stores (x, reload_cse_check_clobber);
9528 if (reload_cse_check_clobbered)
9530 reload_cse_invalidate_rtx (dest, NULL_RTX);
9540 /* This is an assignment to a register. Update the value we
9541 have stored for the register. */
9546 /* This is a copy from one register to another. Any values
9547 which were valid for SREG are now valid for DREG. If the
9548 mode changes, we use gen_lowpart_common to extract only
9549 the part of the value that is copied. */
9550 reg_values[dreg] = 0;
9551 for (x = reg_values[sreg]; x; x = XEXP (x, 1))
9555 if (XEXP (x, 0) == 0)
9557 if (dest_mode == GET_MODE (XEXP (x, 0)))
9559 else if (GET_MODE_BITSIZE (dest_mode)
9560 > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
9563 tmp = gen_lowpart_common (dest_mode, XEXP (x, 0));
9565 reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, tmp,
9570 reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, src, NULL_RTX);
9572 /* We've changed DREG, so invalidate any values held by other
9573 registers that depend upon it. */
9574 reload_cse_invalidate_regno (dreg, dest_mode, 0);
9576 /* If this assignment changes more than one hard register,
9577 forget anything we know about the others. */
9578 for (i = 1; i < HARD_REGNO_NREGS (dreg, dest_mode); i++)
9579 reg_values[dreg + i] = 0;
9581 else if (GET_CODE (dest) == MEM)
9583 /* Invalidate conflicting memory locations. */
9584 reload_cse_invalidate_mem (dest);
9586 /* If we're storing a register to memory, add DEST to the list
9588 if (sreg >= 0 && ! side_effects_p (dest))
9589 reg_values[sreg] = gen_rtx_EXPR_LIST (dest_mode, dest,
9594 /* We should have bailed out earlier. */
9599 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
9601 This code might also be useful when reload gave up on reg+reg addresssing
9602 because of clashes between the return register and INDEX_REG_CLASS. */
9604 /* The maximum number of uses of a register we can keep track of to
9605 replace them with reg+reg addressing. */
9606 #define RELOAD_COMBINE_MAX_USES 6
9608 /* INSN is the insn where a register has ben used, and USEP points to the
9609 location of the register within the rtl. */
9610 struct reg_use { rtx insn, *usep; };
9612 /* If the register is used in some unknown fashion, USE_INDEX is negative.
9613 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
9614 indicates where it becomes live again.
9615 Otherwise, USE_INDEX is the index of the last encountered use of the
9616 register (which is first among these we have seen since we scan backwards),
9617 OFFSET contains the constant offset that is added to the register in
9618 all encountered uses, and USE_RUID indicates the first encountered, i.e.
9619 last, of these uses.
9620 STORE_RUID is always meaningful if we only want to use a value in a
9621 register in a different place: it denotes the next insn in the insn
9622 stream (i.e. the last ecountered) that sets or clobbers the register. */
9625 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
9630 } reg_state[FIRST_PSEUDO_REGISTER];
9632 /* Reverse linear uid. This is increased in reload_combine while scanning
9633 the instructions from last to first. It is used to set last_label_ruid
9634 and the store_ruid / use_ruid fields in reg_state. */
9635 static int reload_combine_ruid;
9637 #define LABEL_LIVE(LABEL) \
9638 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
9644 int first_index_reg = 1, last_index_reg = 0;
9646 int last_label_ruid;
9647 int min_labelno, n_labels;
9648 HARD_REG_SET ever_live_at_start, *label_live;
9650 /* If reg+reg can be used in offsetable memory adresses, the main chunk of
9651 reload has already used it where appropriate, so there is no use in
9652 trying to generate it now. */
9653 if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
9656 /* To avoid wasting too much time later searching for an index register,
9657 determine the minimum and maximum index register numbers. */
9658 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9660 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i))
9662 if (! last_index_reg)
9664 first_index_reg = i;
9667 /* If no index register is available, we can quit now. */
9668 if (first_index_reg > last_index_reg)
9671 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
9672 information is a bit fuzzy immediately after reload, but it's
9673 still good enough to determine which registers are live at a jump
9675 min_labelno = get_first_label_num ();
9676 n_labels = max_label_num () - min_labelno;
9677 label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET));
9678 CLEAR_HARD_REG_SET (ever_live_at_start);
9679 for (i = n_basic_blocks - 1; i >= 0; i--)
9681 insn = BLOCK_HEAD (i);
9682 if (GET_CODE (insn) == CODE_LABEL)
9686 REG_SET_TO_HARD_REG_SET (live, BASIC_BLOCK (i)->global_live_at_start);
9687 compute_use_by_pseudos (&live, BASIC_BLOCK (i)->global_live_at_start);
9688 COPY_HARD_REG_SET (LABEL_LIVE (insn), live);
9689 IOR_HARD_REG_SET (ever_live_at_start, live);
9693 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
9694 last_label_ruid = reload_combine_ruid = 0;
9695 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9697 reg_state[i].store_ruid = reload_combine_ruid;
9699 reg_state[i].use_index = -1;
9701 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9704 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
9708 /* We cannot do our optimization across labels. Invalidating all the use
9709 information we have would be costly, so we just note where the label
9710 is and then later disable any optimization that would cross it. */
9711 if (GET_CODE (insn) == CODE_LABEL)
9712 last_label_ruid = reload_combine_ruid;
9713 if (GET_CODE (insn) == BARRIER)
9715 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9716 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9718 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
9720 reload_combine_ruid++;
9722 /* Look for (set (REGX) (CONST_INT))
9723 (set (REGX) (PLUS (REGX) (REGY)))
9725 ... (MEM (REGX)) ...
9727 (set (REGZ) (CONST_INT))
9729 ... (MEM (PLUS (REGZ) (REGY)))... .
9731 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
9732 and that we know all uses of REGX before it dies. */
9733 set = single_set (insn);
9735 && GET_CODE (SET_DEST (set)) == REG
9736 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)),
9737 GET_MODE (SET_DEST (set)))
9739 && GET_CODE (SET_SRC (set)) == PLUS
9740 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG
9741 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
9742 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
9744 rtx reg = SET_DEST (set);
9745 rtx plus = SET_SRC (set);
9746 rtx base = XEXP (plus, 1);
9747 rtx prev = prev_nonnote_insn (insn);
9748 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
9749 int regno = REGNO (reg);
9751 rtx reg_sum = NULL_RTX;
9753 /* Now, we need an index register.
9754 We'll set index_reg to this index register, const_reg to the
9755 register that is to be loaded with the constant
9756 (denoted as REGZ in the substitution illustration above),
9757 and reg_sum to the register-register that we want to use to
9758 substitute uses of REG (typically in MEMs) with.
9759 First check REG and BASE for being index registers;
9760 we can use them even if they are not dead. */
9761 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
9762 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
9770 /* Otherwise, look for a free index register. Since we have
9771 checked above that neiter REG nor BASE are index registers,
9772 if we find anything at all, it will be different from these
9774 for (i = first_index_reg; i <= last_index_reg; i++)
9776 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i)
9777 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
9778 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
9779 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1)
9781 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i);
9782 const_reg = index_reg;
9783 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
9788 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
9789 (REGY), i.e. BASE, is not clobbered before the last use we'll
9792 && GET_CODE (SET_SRC (prev_set)) == CONST_INT
9793 && rtx_equal_p (SET_DEST (prev_set), reg)
9794 && reg_state[regno].use_index >= 0
9795 && reg_state[REGNO (base)].store_ruid <= reg_state[regno].use_ruid
9800 /* Change destination register and - if necessary - the
9801 constant value in PREV, the constant loading instruction. */
9802 validate_change (prev, &SET_DEST (prev_set), const_reg, 1);
9803 if (reg_state[regno].offset != const0_rtx)
9804 validate_change (prev,
9805 &SET_SRC (prev_set),
9806 GEN_INT (INTVAL (SET_SRC (prev_set))
9807 + INTVAL (reg_state[regno].offset)),
9809 /* Now for every use of REG that we have recorded, replace REG
9811 for (i = reg_state[regno].use_index;
9812 i < RELOAD_COMBINE_MAX_USES; i++)
9813 validate_change (reg_state[regno].reg_use[i].insn,
9814 reg_state[regno].reg_use[i].usep,
9817 if (apply_change_group ())
9821 /* Delete the reg-reg addition. */
9822 PUT_CODE (insn, NOTE);
9823 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9824 NOTE_SOURCE_FILE (insn) = 0;
9826 if (reg_state[regno].offset != const0_rtx)
9828 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
9830 for (np = ®_NOTES (prev); *np; )
9832 if (REG_NOTE_KIND (*np) == REG_EQUAL
9833 || REG_NOTE_KIND (*np) == REG_EQUIV)
9834 *np = XEXP (*np, 1);
9836 np = &XEXP (*np, 1);
9839 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
9840 reg_state[REGNO (const_reg)].store_ruid = reload_combine_ruid;
9845 note_stores (PATTERN (insn), reload_combine_note_store);
9846 if (GET_CODE (insn) == CALL_INSN)
9850 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9852 if (call_used_regs[i])
9854 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9855 reg_state[i].store_ruid = reload_combine_ruid;
9858 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
9859 link = XEXP (link, 1))
9861 rtx use = XEXP (link, 0);
9862 int regno = REGNO (XEXP (use, 0));
9863 if (GET_CODE (use) == CLOBBER)
9865 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
9866 reg_state[regno].store_ruid = reload_combine_ruid;
9869 reg_state[regno].use_index = -1;
9872 if (GET_CODE (insn) == JUMP_INSN && GET_CODE (PATTERN (insn)) != RETURN)
9874 /* Non-spill registers might be used at the call destination in
9875 some unknown fashion, so we have to mark the unknown use. */
9877 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
9878 && JUMP_LABEL (insn))
9879 live = &LABEL_LIVE (JUMP_LABEL (insn));
9881 live = &ever_live_at_start;
9882 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9884 if (TEST_HARD_REG_BIT (*live, i))
9885 reg_state[i].use_index = -1;
9888 reload_combine_note_use (&PATTERN (insn), insn);
9889 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9891 if (REG_NOTE_KIND (note) == REG_INC
9892 && GET_CODE (XEXP (note, 0)) == REG)
9894 int regno = REGNO (XEXP (note, 0));
9896 reg_state[regno].store_ruid = reload_combine_ruid;
9897 reg_state[regno].use_index = -1;
9904 /* Check if DST is a register or a subreg of a register; if it is,
9905 update reg_state[regno].store_ruid and reg_state[regno].use_index
9906 accordingly. Called via note_stores from reload_combine. */
9908 reload_combine_note_store (dst, set)
9913 unsigned size = GET_MODE_SIZE (GET_MODE (dst));
9915 if (GET_CODE (dst) == SUBREG)
9917 regno = SUBREG_WORD (dst);
9918 dst = SUBREG_REG (dst);
9920 if (GET_CODE (dst) != REG)
9922 regno += REGNO (dst);
9924 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
9925 careful with registers / register parts that are not full words.
9927 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
9928 if (GET_CODE (set) != SET
9929 || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
9930 || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT
9931 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
9933 for (i = (size - 1) / UNITS_PER_WORD + regno; i >= regno; i--)
9935 reg_state[i].use_index = -1;
9936 reg_state[i].store_ruid = reload_combine_ruid;
9941 for (i = (size - 1) / UNITS_PER_WORD + regno; i >= regno; i--)
9943 reg_state[i].store_ruid = reload_combine_ruid;
9944 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9949 /* XP points to a piece of rtl that has to be checked for any uses of
9951 *XP is the pattern of INSN, or a part of it.
9952 Called from reload_combine, and recursively by itself. */
9954 reload_combine_note_use (xp, insn)
9958 enum rtx_code code = x->code;
9961 rtx offset = const0_rtx; /* For the REG case below. */
9966 if (GET_CODE (SET_DEST (x)) == REG)
9968 reload_combine_note_use (&SET_SRC (x), insn);
9974 /* If this is the USE of a return value, we can't change it. */
9975 if (GET_CODE (XEXP (x, 0)) == REG && REG_FUNCTION_VALUE_P (XEXP (x, 0)))
9977 /* Mark the return register as used in an unknown fashion. */
9978 rtx reg = XEXP (x, 0);
9979 int regno = REGNO (reg);
9980 int nregs = HARD_REGNO_NREGS (regno, GET_MODE (reg));
9982 while (--nregs >= 0)
9983 reg_state[regno + nregs].use_index = -1;
9989 if (GET_CODE (SET_DEST (x)) == REG)
9994 /* We are interested in (plus (reg) (const_int)) . */
9995 if (GET_CODE (XEXP (x, 0)) != REG || GET_CODE (XEXP (x, 1)) != CONST_INT)
9997 offset = XEXP (x, 1);
10002 int regno = REGNO (x);
10006 /* Some spurious USEs of pseudo registers might remain.
10007 Just ignore them. */
10008 if (regno >= FIRST_PSEUDO_REGISTER)
10011 nregs = HARD_REGNO_NREGS (regno, GET_MODE (x));
10013 /* We can't substitute into multi-hard-reg uses. */
10016 while (--nregs >= 0)
10017 reg_state[regno + nregs].use_index = -1;
10021 /* If this register is already used in some unknown fashion, we
10023 If we decrement the index from zero to -1, we can't store more
10024 uses, so this register becomes used in an unknown fashion. */
10025 use_index = --reg_state[regno].use_index;
10029 if (use_index != RELOAD_COMBINE_MAX_USES - 1)
10031 /* We have found another use for a register that is already
10032 used later. Check if the offsets match; if not, mark the
10033 register as used in an unknown fashion. */
10034 if (! rtx_equal_p (offset, reg_state[regno].offset))
10036 reg_state[regno].use_index = -1;
10042 /* This is the first use of this register we have seen since we
10043 marked it as dead. */
10044 reg_state[regno].offset = offset;
10045 reg_state[regno].use_ruid = reload_combine_ruid;
10047 reg_state[regno].reg_use[use_index].insn = insn;
10048 reg_state[regno].reg_use[use_index].usep = xp;
10056 /* Recursively process the components of X. */
10057 fmt = GET_RTX_FORMAT (code);
10058 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10061 reload_combine_note_use (&XEXP (x, i), insn);
10062 else if (fmt[i] == 'E')
10064 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
10065 reload_combine_note_use (&XVECEXP (x, i, j), insn);
10070 /* See if we can reduce the cost of a constant by replacing a move with
10072 /* We cannot do our optimization across labels. Invalidating all the
10073 information about register contents we have would be costly, so we
10074 use last_label_luid (local variable of reload_cse_move2add) to note
10075 where the label is and then later disable any optimization that would
10077 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
10078 reg_set_luid[n] is larger than last_label_luid[n] . */
10079 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
10080 /* reg_offset[n] has to be CONST_INT for it and reg_base_reg[n] /
10081 reg_mode[n] to be valid.
10082 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is negative, register n
10083 has been set to reg_offset[n] in mode reg_mode[n] .
10084 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is non-negative,
10085 register n has been set to the sum of reg_offset[n] and register
10086 reg_base_reg[n], calculated in mode reg_mode[n] . */
10087 static rtx reg_offset[FIRST_PSEUDO_REGISTER];
10088 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
10089 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
10090 /* move2add_luid is linearily increased while scanning the instructions
10091 from first to last. It is used to set reg_set_luid in
10092 reload_cse_move2add and move2add_note_store. */
10093 static int move2add_luid;
10095 /* Generate a CONST_INT and force it in the range of MODE. */
10097 gen_mode_int (mode, value)
10098 enum machine_mode mode;
10099 HOST_WIDE_INT value;
10101 HOST_WIDE_INT cval = value & GET_MODE_MASK (mode);
10102 int width = GET_MODE_BITSIZE (mode);
10104 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number,
10106 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
10107 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
10108 cval |= (HOST_WIDE_INT) -1 << width;
10110 return GEN_INT (cval);
10114 reload_cse_move2add (first)
10119 int last_label_luid;
10121 for (i = FIRST_PSEUDO_REGISTER-1; i >= 0; i--)
10122 reg_set_luid[i] = 0;
10124 last_label_luid = 0;
10126 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
10130 if (GET_CODE (insn) == CODE_LABEL)
10131 last_label_luid = move2add_luid;
10132 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
10134 pat = PATTERN (insn);
10135 /* For simplicity, we only perform this optimization on
10136 straightforward SETs. */
10137 if (GET_CODE (pat) == SET
10138 && GET_CODE (SET_DEST (pat)) == REG)
10140 rtx reg = SET_DEST (pat);
10141 int regno = REGNO (reg);
10142 rtx src = SET_SRC (pat);
10144 /* Check if we have valid information on the contents of this
10145 register in the mode of REG. */
10146 /* ??? We don't know how zero / sign extension is handled, hence
10147 we can't go from a narrower to a wider mode. */
10148 if (reg_set_luid[regno] > last_label_luid
10149 && (GET_MODE_SIZE (GET_MODE (reg))
10150 <= GET_MODE_SIZE (reg_mode[regno]))
10151 && GET_CODE (reg_offset[regno]) == CONST_INT)
10153 /* Try to transform (set (REGX) (CONST_INT A))
10155 (set (REGX) (CONST_INT B))
10157 (set (REGX) (CONST_INT A))
10159 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
10161 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0)
10165 = gen_mode_int (GET_MODE (reg),
10166 INTVAL (src) - INTVAL (reg_offset[regno]));
10167 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
10168 use (set (reg) (reg)) instead.
10169 We don't delete this insn, nor do we convert it into a
10170 note, to avoid losing register notes or the return
10171 value flag. jump2 already knowns how to get rid of
10173 if (new_src == const0_rtx)
10174 success = validate_change (insn, &SET_SRC (pat), reg, 0);
10175 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET)
10176 && have_add2_insn (GET_MODE (reg)))
10177 success = validate_change (insn, &PATTERN (insn),
10178 gen_add2_insn (reg, new_src), 0);
10179 reg_set_luid[regno] = move2add_luid;
10180 reg_mode[regno] = GET_MODE (reg);
10181 reg_offset[regno] = src;
10185 /* Try to transform (set (REGX) (REGY))
10186 (set (REGX) (PLUS (REGX) (CONST_INT A)))
10188 (set (REGX) (REGY))
10189 (set (REGX) (PLUS (REGX) (CONST_INT B)))
10192 (set (REGX) (PLUS (REGX) (CONST_INT A)))
10194 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
10195 else if (GET_CODE (src) == REG
10196 && reg_base_reg[regno] == REGNO (src)
10197 && reg_set_luid[regno] > reg_set_luid[REGNO (src)])
10199 rtx next = next_nonnote_insn (insn);
10202 set = single_set (next);
10205 && SET_DEST (set) == reg
10206 && GET_CODE (SET_SRC (set)) == PLUS
10207 && XEXP (SET_SRC (set), 0) == reg
10208 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
10210 rtx src3 = XEXP (SET_SRC (set), 1);
10212 = gen_mode_int (GET_MODE (reg),
10214 - INTVAL (reg_offset[regno]));
10217 if (new_src == const0_rtx)
10218 /* See above why we create (set (reg) (reg)) here. */
10220 = validate_change (next, &SET_SRC (set), reg, 0);
10221 else if ((rtx_cost (new_src, PLUS)
10222 < 2 + rtx_cost (src3, SET))
10223 && have_add2_insn (GET_MODE (reg)))
10225 = validate_change (next, &PATTERN (next),
10226 gen_add2_insn (reg, new_src), 0);
10229 /* INSN might be the first insn in a basic block
10230 if the preceding insn is a conditional jump
10231 or a possible-throwing call. */
10232 PUT_CODE (insn, NOTE);
10233 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
10234 NOTE_SOURCE_FILE (insn) = 0;
10237 reg_set_luid[regno] = move2add_luid;
10238 reg_mode[regno] = GET_MODE (reg);
10239 reg_offset[regno] = src3;
10246 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
10248 if (REG_NOTE_KIND (note) == REG_INC
10249 && GET_CODE (XEXP (note, 0)) == REG)
10251 /* Indicate that this register has been recently written to,
10252 but the exact contents are not available. */
10253 int regno = REGNO (XEXP (note, 0));
10254 if (regno < FIRST_PSEUDO_REGISTER)
10256 reg_set_luid[regno] = move2add_luid;
10257 reg_offset[regno] = note;
10261 note_stores (PATTERN (insn), move2add_note_store);
10262 /* If this is a CALL_INSN, all call used registers are stored with
10264 if (GET_CODE (insn) == CALL_INSN)
10266 for (i = FIRST_PSEUDO_REGISTER-1; i >= 0; i--)
10268 if (call_used_regs[i])
10270 reg_set_luid[i] = move2add_luid;
10271 reg_offset[i] = insn; /* Invalidate contents. */
10278 /* SET is a SET or CLOBBER that sets DST.
10279 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
10280 Called from reload_cse_move2add via note_stores. */
10282 move2add_note_store (dst, set)
10288 enum machine_mode mode = GET_MODE (dst);
10289 if (GET_CODE (dst) == SUBREG)
10291 regno = SUBREG_WORD (dst);
10292 dst = SUBREG_REG (dst);
10294 if (GET_CODE (dst) != REG)
10297 regno += REGNO (dst);
10299 if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET
10300 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
10301 && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT
10302 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
10304 rtx src = SET_SRC (set);
10306 reg_mode[regno] = mode;
10307 switch (GET_CODE (src))
10311 rtx src0 = XEXP (src, 0);
10312 if (GET_CODE (src0) == REG)
10314 if (REGNO (src0) != regno
10315 || reg_offset[regno] != const0_rtx)
10317 reg_base_reg[regno] = REGNO (src0);
10318 reg_set_luid[regno] = move2add_luid;
10320 reg_offset[regno] = XEXP (src, 1);
10323 reg_set_luid[regno] = move2add_luid;
10324 reg_offset[regno] = set; /* Invalidate contents. */
10329 reg_base_reg[regno] = REGNO (SET_SRC (set));
10330 reg_offset[regno] = const0_rtx;
10331 reg_set_luid[regno] = move2add_luid;
10335 reg_base_reg[regno] = -1;
10336 reg_offset[regno] = SET_SRC (set);
10337 reg_set_luid[regno] = move2add_luid;
10343 for (i = regno + HARD_REGNO_NREGS (regno, mode) - 1; i >= regno; i--)
10345 /* Indicate that this register has been recently written to,
10346 but the exact contents are not available. */
10347 reg_set_luid[i] = move2add_luid;
10348 reg_offset[i] = dst;
10353 #ifdef AUTO_INC_DEC
10355 add_auto_inc_notes (insn, x)
10359 enum rtx_code code = GET_CODE (x);
10363 if (code == MEM && auto_inc_p (XEXP (x, 0)))
10366 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
10370 /* Scan all the operand sub-expressions. */
10371 fmt = GET_RTX_FORMAT (code);
10372 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10375 add_auto_inc_notes (insn, XEXP (x, i));
10376 else if (fmt[i] == 'E')
10377 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
10378 add_auto_inc_notes (insn, XVECEXP (x, i, j));