2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk>
3 * and Duncan Barclay<dmlb@dmlb.org>
4 * Modifications for FreeBSD-stable by Edwin Groothuis
5 * <edwin at mavetju.org
6 * < http://lists.freebsd.org/mailman/listinfo/freebsd-bugs>>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * $FreeBSD: src/sys/dev/bfe/if_bfe.c 1.4.4.7 2004/03/02 08:41:33 julian Exp v
32 * $DragonFly: src/sys/dev/netif/bfe/if_bfe.c,v 1.17 2005/06/13 21:07:55 joerg Exp $
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/sockio.h>
39 #include <sys/malloc.h>
40 #include <sys/kernel.h>
41 #include <sys/socket.h>
42 #include <sys/queue.h>
43 #include <sys/thread2.h>
46 #include <net/ifq_var.h>
47 #include <net/if_arp.h>
48 #include <net/ethernet.h>
49 #include <net/if_dl.h>
50 #include <net/if_media.h>
54 #include <net/if_types.h>
55 #include <net/vlan/if_vlan_var.h>
57 #include <netinet/in_systm.h>
58 #include <netinet/in.h>
59 #include <netinet/ip.h>
61 #include <machine/bus_memio.h>
62 #include <machine/bus.h>
63 #include <machine/resource.h>
67 #include <bus/pci/pcireg.h>
68 #include <bus/pci/pcivar.h>
69 #include <bus/pci/pcidevs.h>
71 #include <dev/netif/mii_layer/mii.h>
72 #include <dev/netif/mii_layer/miivar.h>
74 #include "if_bfereg.h"
76 MODULE_DEPEND(bfe, pci, 1, 1, 1);
77 MODULE_DEPEND(bfe, miibus, 1, 1, 1);
79 /* "controller miibus0" required. See GENERIC if you get errors here. */
80 #include "miibus_if.h"
82 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */
84 static struct bfe_type bfe_devs[] = {
85 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401,
86 "Broadcom BCM4401 Fast Ethernet" },
90 static int bfe_probe(device_t);
91 static int bfe_attach(device_t);
92 static int bfe_detach(device_t);
93 static void bfe_release_resources(struct bfe_softc *);
94 static void bfe_intr(void *);
95 static void bfe_start(struct ifnet *);
96 static int bfe_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
97 static void bfe_init(void *);
98 static void bfe_stop(struct bfe_softc *);
99 static void bfe_watchdog(struct ifnet *);
100 static void bfe_shutdown(device_t);
101 static void bfe_tick(void *);
102 static void bfe_txeof(struct bfe_softc *);
103 static void bfe_rxeof(struct bfe_softc *);
104 static void bfe_set_rx_mode(struct bfe_softc *);
105 static int bfe_list_rx_init(struct bfe_softc *);
106 static int bfe_list_newbuf(struct bfe_softc *, int, struct mbuf*);
107 static void bfe_rx_ring_free(struct bfe_softc *);
109 static void bfe_pci_setup(struct bfe_softc *, uint32_t);
110 static int bfe_ifmedia_upd(struct ifnet *);
111 static void bfe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
112 static int bfe_miibus_readreg(device_t, int, int);
113 static int bfe_miibus_writereg(device_t, int, int, int);
114 static void bfe_miibus_statchg(device_t);
115 static int bfe_wait_bit(struct bfe_softc *, uint32_t, uint32_t,
117 static void bfe_get_config(struct bfe_softc *sc);
118 static void bfe_read_eeprom(struct bfe_softc *, uint8_t *);
119 static void bfe_stats_update(struct bfe_softc *);
120 static void bfe_clear_stats (struct bfe_softc *);
121 static int bfe_readphy(struct bfe_softc *, uint32_t, uint32_t*);
122 static int bfe_writephy(struct bfe_softc *, uint32_t, uint32_t);
123 static int bfe_resetphy(struct bfe_softc *);
124 static int bfe_setupphy(struct bfe_softc *);
125 static void bfe_chip_reset(struct bfe_softc *);
126 static void bfe_chip_halt(struct bfe_softc *);
127 static void bfe_core_reset(struct bfe_softc *);
128 static void bfe_core_disable(struct bfe_softc *);
129 static int bfe_dma_alloc(device_t);
130 static void bfe_dma_map_desc(void *, bus_dma_segment_t *, int, int);
131 static void bfe_dma_map(void *, bus_dma_segment_t *, int, int);
132 static void bfe_cam_write(struct bfe_softc *, u_char *, int);
134 static device_method_t bfe_methods[] = {
135 /* Device interface */
136 DEVMETHOD(device_probe, bfe_probe),
137 DEVMETHOD(device_attach, bfe_attach),
138 DEVMETHOD(device_detach, bfe_detach),
139 DEVMETHOD(device_shutdown, bfe_shutdown),
142 DEVMETHOD(bus_print_child, bus_generic_print_child),
143 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
146 DEVMETHOD(miibus_readreg, bfe_miibus_readreg),
147 DEVMETHOD(miibus_writereg, bfe_miibus_writereg),
148 DEVMETHOD(miibus_statchg, bfe_miibus_statchg),
153 static driver_t bfe_driver = {
156 sizeof(struct bfe_softc)
159 static devclass_t bfe_devclass;
161 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0);
162 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0);
165 * Probe for a Broadcom 4401 chip.
168 bfe_probe(device_t dev)
171 uint16_t vendor, product;
173 vendor = pci_get_vendor(dev);
174 product = pci_get_device(dev);
176 for (t = bfe_devs; t->bfe_name != NULL; t++) {
177 if (vendor == t->bfe_vid && product == t->bfe_did) {
178 device_set_desc_copy(dev, t->bfe_name);
187 bfe_dma_alloc(device_t dev)
189 struct bfe_softc *sc;
192 sc = device_get_softc(dev);
195 error = bus_dma_tag_create(NULL, /* parent */
196 PAGE_SIZE, 0, /* alignment, boundary */
197 BUS_SPACE_MAXADDR, /* lowaddr */
198 BUS_SPACE_MAXADDR_32BIT, /* highaddr */
199 NULL, NULL, /* filter, filterarg */
200 MAXBSIZE, /* maxsize */
201 BUS_SPACE_UNRESTRICTED, /* num of segments */
202 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */
203 BUS_DMA_ALLOCNOW, /* flags */
204 &sc->bfe_parent_tag);
207 device_printf(dev, "could not allocate dma tag\n");
212 /* tag for TX ring */
213 error = bus_dma_tag_create(sc->bfe_parent_tag, BFE_TX_LIST_SIZE,
214 BFE_TX_LIST_SIZE, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
215 NULL, NULL, BFE_TX_LIST_SIZE, 1,
216 BUS_SPACE_MAXSIZE_32BIT, 0, &sc->bfe_tx_tag);
219 device_printf(dev, "could not allocate dma tag\n");
223 /* tag for RX ring */
224 error = bus_dma_tag_create(sc->bfe_parent_tag, BFE_RX_LIST_SIZE,
225 BFE_RX_LIST_SIZE, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
226 NULL, NULL, BFE_RX_LIST_SIZE, 1,
227 BUS_SPACE_MAXSIZE_32BIT, 0, &sc->bfe_rx_tag);
230 device_printf(dev, "could not allocate dma tag\n");
235 error = bus_dma_tag_create(sc->bfe_parent_tag, ETHER_ALIGN, 0,
236 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES,
237 1, BUS_SPACE_MAXSIZE_32BIT, 0,
241 device_printf(dev, "could not allocate dma tag\n");
245 /* pre allocate dmamaps for RX list */
246 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
247 error = bus_dmamap_create(sc->bfe_tag, 0, &sc->bfe_rx_ring[i].bfe_map);
249 device_printf(dev, "cannot create DMA map for RX\n");
254 /* pre allocate dmamaps for TX list */
255 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
256 error = bus_dmamap_create(sc->bfe_tag, 0, &sc->bfe_tx_ring[i].bfe_map);
258 device_printf(dev, "cannot create DMA map for TX\n");
263 /* Alloc dma for rx ring */
264 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list,
265 BUS_DMA_WAITOK, &sc->bfe_rx_map);
270 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
271 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map,
272 sc->bfe_rx_list, sizeof(struct bfe_desc),
273 bfe_dma_map, &sc->bfe_rx_dma, 0);
278 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD);
280 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list,
281 BUS_DMA_WAITOK, &sc->bfe_tx_map);
285 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map,
286 sc->bfe_tx_list, sizeof(struct bfe_desc),
287 bfe_dma_map, &sc->bfe_tx_dma, 0);
291 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
292 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD);
298 bfe_attach(device_t dev)
301 struct bfe_softc *sc;
304 sc = device_get_softc(dev);
307 callout_init(&sc->bfe_stat_timer);
310 * Handle power management nonsense.
312 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
313 uint32_t membase, irq;
315 /* Save important PCI config data. */
316 membase = pci_read_config(dev, BFE_PCI_MEMLO, 4);
317 irq = pci_read_config(dev, BFE_PCI_INTLINE, 4);
319 /* Reset the power state. */
320 device_printf(dev, "chip is in D%d power mode"
321 " -- setting to D0\n", pci_get_powerstate(dev));
323 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
325 /* Restore PCI config data. */
326 pci_write_config(dev, BFE_PCI_MEMLO, membase, 4);
327 pci_write_config(dev, BFE_PCI_INTLINE, irq, 4);
331 * Map control/status registers.
333 pci_enable_busmaster(dev);
336 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
338 if (sc->bfe_res == NULL) {
339 device_printf(dev, "couldn't map memory\n");
344 sc->bfe_btag = rman_get_bustag(sc->bfe_res);
345 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res);
347 /* Allocate interrupt */
350 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
351 RF_SHAREABLE | RF_ACTIVE);
352 if (sc->bfe_irq == NULL) {
353 device_printf(dev, "couldn't map interrupt\n");
358 if (bfe_dma_alloc(dev)) {
359 device_printf(dev, "failed to allocate DMA resources\n");
360 bfe_release_resources(sc);
365 /* Set up ifnet structure */
366 ifp = &sc->arpcom.ac_if;
368 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
369 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
370 ifp->if_ioctl = bfe_ioctl;
371 ifp->if_start = bfe_start;
372 ifp->if_watchdog = bfe_watchdog;
373 ifp->if_init = bfe_init;
374 ifp->if_mtu = ETHERMTU;
375 ifp->if_baudrate = 10000000;
376 ifq_set_maxlen(&ifp->if_snd, BFE_TX_QLEN);
377 ifq_set_ready(&ifp->if_snd);
381 /* Reset the chip and turn on the PHY */
384 if (mii_phy_probe(dev, &sc->bfe_miibus,
385 bfe_ifmedia_upd, bfe_ifmedia_sts)) {
386 device_printf(dev, "MII without any PHY!\n");
391 ether_ifattach(ifp, sc->arpcom.ac_enaddr);
394 * Hook interrupt last to avoid having to lock softc
396 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET,
397 bfe_intr, sc, &sc->bfe_intrhand, NULL);
401 bfe_release_resources(sc);
402 device_printf(dev, "couldn't set up irq\n");
407 bfe_release_resources(sc);
412 bfe_detach(device_t dev)
414 struct bfe_softc *sc = device_get_softc(dev);
415 struct ifnet *ifp = &sc->arpcom.ac_if;
419 if (device_is_attached(dev)) {
426 if (sc->bfe_miibus != NULL)
427 device_delete_child(dev, sc->bfe_miibus);
428 bus_generic_detach(dev);
430 bfe_release_resources(sc);
438 * Stop all chip I/O so that the kernel's probe routines don't
439 * get confused by errant DMAs when rebooting.
442 bfe_shutdown(device_t dev)
444 struct bfe_softc *sc = device_get_softc(dev);
454 bfe_miibus_readreg(device_t dev, int phy, int reg)
456 struct bfe_softc *sc;
459 sc = device_get_softc(dev);
460 if (phy != sc->bfe_phyaddr)
462 bfe_readphy(sc, reg, &ret);
468 bfe_miibus_writereg(device_t dev, int phy, int reg, int val)
470 struct bfe_softc *sc;
472 sc = device_get_softc(dev);
473 if (phy != sc->bfe_phyaddr)
475 bfe_writephy(sc, reg, val);
481 bfe_miibus_statchg(device_t dev)
487 bfe_tx_ring_free(struct bfe_softc *sc)
491 for (i = 0; i < BFE_TX_LIST_CNT; i++)
492 if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) {
493 m_freem(sc->bfe_tx_ring[i].bfe_mbuf);
494 sc->bfe_tx_ring[i].bfe_mbuf = NULL;
495 bus_dmamap_unload(sc->bfe_tag,
496 sc->bfe_tx_ring[i].bfe_map);
497 bus_dmamap_destroy(sc->bfe_tag,
498 sc->bfe_tx_ring[i].bfe_map);
500 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
501 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD);
505 bfe_rx_ring_free(struct bfe_softc *sc)
509 for (i = 0; i < BFE_RX_LIST_CNT; i++)
510 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) {
511 m_freem(sc->bfe_rx_ring[i].bfe_mbuf);
512 sc->bfe_rx_ring[i].bfe_mbuf = NULL;
513 bus_dmamap_unload(sc->bfe_tag,
514 sc->bfe_rx_ring[i].bfe_map);
515 bus_dmamap_destroy(sc->bfe_tag,
516 sc->bfe_rx_ring[i].bfe_map);
518 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
519 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD);
524 bfe_list_rx_init(struct bfe_softc *sc)
528 for (i = 0; i < BFE_RX_LIST_CNT; i++)
529 if (bfe_list_newbuf(sc, i, NULL) == ENOBUFS)
532 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD);
533 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc)));
541 bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m)
543 struct bfe_rxheader *rx_header;
548 if ((c < 0) || (c >= BFE_RX_LIST_CNT))
552 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
555 m->m_len = m->m_pkthdr.len = MCLBYTES;
558 m->m_data = m->m_ext.ext_buf;
560 rx_header = mtod(m, struct bfe_rxheader *);
562 rx_header->flags = 0;
564 /* Map the mbuf into DMA */
566 d = &sc->bfe_rx_list[c];
567 r = &sc->bfe_rx_ring[c];
568 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *),
569 MCLBYTES, bfe_dma_map_desc, d, 0);
570 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREWRITE);
572 ctrl = ETHER_MAX_LEN + 32;
574 if(c == BFE_RX_LIST_CNT - 1)
575 ctrl |= BFE_DESC_EOT;
579 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD);
584 bfe_get_config(struct bfe_softc *sc)
588 bfe_read_eeprom(sc, eeprom);
590 sc->arpcom.ac_enaddr[0] = eeprom[79];
591 sc->arpcom.ac_enaddr[1] = eeprom[78];
592 sc->arpcom.ac_enaddr[2] = eeprom[81];
593 sc->arpcom.ac_enaddr[3] = eeprom[80];
594 sc->arpcom.ac_enaddr[4] = eeprom[83];
595 sc->arpcom.ac_enaddr[5] = eeprom[82];
597 sc->bfe_phyaddr = eeprom[90] & 0x1f;
598 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1;
600 sc->bfe_core_unit = 0;
601 sc->bfe_dma_offset = BFE_PCI_DMA;
605 bfe_pci_setup(struct bfe_softc *sc, uint32_t cores)
607 uint32_t bar_orig, pci_rev, val;
609 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4);
610 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4);
611 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK;
613 val = CSR_READ_4(sc, BFE_SBINTVEC);
615 CSR_WRITE_4(sc, BFE_SBINTVEC, val);
617 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2);
618 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST;
619 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val);
621 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4);
625 bfe_clear_stats(struct bfe_softc *sc)
631 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ);
632 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
634 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
641 bfe_resetphy(struct bfe_softc *sc)
647 bfe_writephy(sc, 0, BMCR_RESET);
649 bfe_readphy(sc, 0, &val);
650 if (val & BMCR_RESET) {
652 if_printf(&sc->arpcom.ac_if,
653 "PHY Reset would not complete.\n");
662 bfe_chip_halt(struct bfe_softc *sc)
666 /* disable interrupts - not that it actually does..*/
667 CSR_WRITE_4(sc, BFE_IMASK, 0);
668 CSR_READ_4(sc, BFE_IMASK);
670 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
671 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1);
673 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
674 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
681 bfe_chip_reset(struct bfe_softc *sc)
687 /* Set the interrupt vector for the enet core */
688 bfe_pci_setup(sc, BFE_INTVEC_ENET0);
691 val = CSR_READ_4(sc, BFE_SBTMSLOW) & (BFE_RESET | BFE_REJECT | BFE_CLOCK);
692 if (val == BFE_CLOCK) {
693 /* It is, so shut it down */
694 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0);
695 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
696 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1);
697 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
698 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0;
699 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK)
700 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 100, 0);
701 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
702 sc->bfe_rx_prod = sc->bfe_rx_cons = 0;
709 * We want the phy registers to be accessible even when
710 * the driver is "downed" so initialize MDC preamble, frequency,
711 * and whether internal or external phy here.
714 /* 4402 has 62.5Mhz SB clock and internal phy */
715 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d);
717 /* Internal or external PHY? */
718 val = CSR_READ_4(sc, BFE_DEVCTRL);
719 if (!(val & BFE_IPP))
720 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL);
721 else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) {
722 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR);
726 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB);
727 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) &
731 * We don't want lazy interrupts, so just send them at the end of a
734 BFE_OR(sc, BFE_RCV_LAZY, 0);
736 /* Set max lengths, accounting for VLAN tags */
737 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32);
738 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32);
740 /* Set watermark XXX - magic */
741 CSR_WRITE_4(sc, BFE_TX_WMARK, 56);
744 * Initialise DMA channels - not forgetting dma addresses need to be
745 * added to BFE_PCI_DMA
747 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE);
748 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA);
750 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) |
752 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA);
761 bfe_core_disable(struct bfe_softc *sc)
763 if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET)
767 * Set reject, wait for it set, then wait for the core to stop being busy
768 * Then set reset and reject and enable the clocks
770 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK));
771 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0);
772 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1);
773 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT |
775 CSR_READ_4(sc, BFE_SBTMSLOW);
777 /* Leave reset and reject set */
778 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET));
783 bfe_core_reset(struct bfe_softc *sc)
787 /* Disable the core */
788 bfe_core_disable(sc);
790 /* and bring it back up */
791 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC));
792 CSR_READ_4(sc, BFE_SBTMSLOW);
795 /* Chip bug, clear SERR, IB and TO if they are set. */
796 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR)
797 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0);
798 val = CSR_READ_4(sc, BFE_SBIMSTATE);
799 if (val & (BFE_IBE | BFE_TO))
800 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO));
802 /* Clear reset and allow it to move through the core */
803 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC));
804 CSR_READ_4(sc, BFE_SBTMSLOW);
807 /* Leave the clock set */
808 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK);
809 CSR_READ_4(sc, BFE_SBTMSLOW);
814 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index)
818 val = ((uint32_t) data[2]) << 24;
819 val |= ((uint32_t) data[3]) << 16;
820 val |= ((uint32_t) data[4]) << 8;
821 val |= ((uint32_t) data[5]);
822 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val);
823 val = (BFE_CAM_HI_VALID |
824 (((uint32_t) data[0]) << 8) |
825 (((uint32_t) data[1])));
826 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val);
827 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE |
828 (index << BFE_CAM_INDEX_SHIFT)));
829 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1);
833 bfe_set_rx_mode(struct bfe_softc *sc)
835 struct ifnet *ifp = &sc->arpcom.ac_if;
839 val = CSR_READ_4(sc, BFE_RXCONF);
841 if (ifp->if_flags & IFF_PROMISC)
842 val |= BFE_RXCONF_PROMISC;
844 val &= ~BFE_RXCONF_PROMISC;
846 if (ifp->if_flags & IFF_BROADCAST)
847 val &= ~BFE_RXCONF_DBCAST;
849 val |= BFE_RXCONF_DBCAST;
852 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0);
853 bfe_cam_write(sc, sc->arpcom.ac_enaddr, i++);
855 CSR_WRITE_4(sc, BFE_RXCONF, val);
856 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE);
860 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error)
865 *ptr = segs->ds_addr;
869 bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error)
874 /* The chip needs all addresses to be added to BFE_PCI_DMA */
875 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA;
879 bfe_release_resources(struct bfe_softc *sc)
886 if (sc->bfe_intrhand != NULL)
887 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand);
889 if (sc->bfe_irq != NULL)
890 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq);
892 if (sc->bfe_res != NULL)
893 bus_release_resource(dev, SYS_RES_MEMORY, 0x10, sc->bfe_res);
895 if (sc->bfe_tx_tag != NULL) {
896 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map);
897 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, sc->bfe_tx_map);
898 bus_dma_tag_destroy(sc->bfe_tx_tag);
899 sc->bfe_tx_tag = NULL;
902 if (sc->bfe_rx_tag != NULL) {
903 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map);
904 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, sc->bfe_rx_map);
905 bus_dma_tag_destroy(sc->bfe_rx_tag);
906 sc->bfe_rx_tag = NULL;
909 if (sc->bfe_tag != NULL) {
910 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
911 bus_dmamap_destroy(sc->bfe_tag,
912 sc->bfe_tx_ring[i].bfe_map);
914 bus_dma_tag_destroy(sc->bfe_tag);
918 if (sc->bfe_parent_tag != NULL)
919 bus_dma_tag_destroy(sc->bfe_parent_tag);
923 bfe_read_eeprom(struct bfe_softc *sc, uint8_t *data)
926 uint16_t *ptr = (uint16_t *)data;
928 for (i = 0; i < 128; i += 2)
929 ptr[i/2] = CSR_READ_4(sc, 4096 + i);
933 bfe_wait_bit(struct bfe_softc *sc, uint32_t reg, uint32_t bit,
934 u_long timeout, const int clear)
938 for (i = 0; i < timeout; i++) {
939 uint32_t val = CSR_READ_4(sc, reg);
941 if (clear && !(val & bit))
943 if (!clear && (val & bit))
948 if_printf(&sc->arpcom.ac_if,
949 "BUG! Timeout waiting for bit %08x of register "
950 "%x to %s.\n", bit, reg,
951 (clear ? "clear" : "set"));
958 bfe_readphy(struct bfe_softc *sc, uint32_t reg, uint32_t *val)
965 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
966 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
967 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) |
968 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
969 (reg << BFE_MDIO_RA_SHIFT) |
970 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT)));
971 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
972 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA;
979 bfe_writephy(struct bfe_softc *sc, uint32_t reg, uint32_t val)
985 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
986 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
987 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) |
988 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
989 (reg << BFE_MDIO_RA_SHIFT) |
990 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) |
991 (val & BFE_MDIO_DATA_DATA)));
992 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
1000 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it
1004 bfe_setupphy(struct bfe_softc *sc)
1010 /* Enable activity LED */
1011 bfe_readphy(sc, 26, &val);
1012 bfe_writephy(sc, 26, val & 0x7fff);
1013 bfe_readphy(sc, 26, &val);
1015 /* Enable traffic meter LED mode */
1016 bfe_readphy(sc, 27, &val);
1017 bfe_writephy(sc, 27, val | (1 << 6));
1024 bfe_stats_update(struct bfe_softc *sc)
1029 val = &sc->bfe_hwstats.tx_good_octets;
1030 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
1031 *val++ += CSR_READ_4(sc, reg);
1032 val = &sc->bfe_hwstats.rx_good_octets;
1033 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
1034 *val++ += CSR_READ_4(sc, reg);
1038 bfe_txeof(struct bfe_softc *sc)
1040 struct ifnet *ifp = &sc->arpcom.ac_if;
1041 uint32_t i, chipidx;
1045 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK;
1046 chipidx /= sizeof(struct bfe_desc);
1048 i = sc->bfe_tx_cons;
1049 /* Go through the mbufs and free those that have been transmitted */
1050 while (i != chipidx) {
1051 struct bfe_data *r = &sc->bfe_tx_ring[i];
1052 if (r->bfe_mbuf != NULL) {
1054 m_freem(r->bfe_mbuf);
1056 bus_dmamap_unload(sc->bfe_tag, r->bfe_map);
1059 BFE_INC(i, BFE_TX_LIST_CNT);
1062 if (i != sc->bfe_tx_cons) {
1063 /* we freed up some mbufs */
1064 sc->bfe_tx_cons = i;
1065 ifp->if_flags &= ~IFF_OACTIVE;
1067 if (sc->bfe_tx_cnt == 0)
1075 /* Pass a received packet up the stack */
1077 bfe_rxeof(struct bfe_softc *sc)
1079 struct ifnet *ifp = &sc->arpcom.ac_if;
1081 struct bfe_rxheader *rxheader;
1083 uint32_t cons, status, current, len, flags;
1087 cons = sc->bfe_rx_cons;
1088 status = CSR_READ_4(sc, BFE_DMARX_STAT);
1089 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc);
1091 while (current != cons) {
1092 r = &sc->bfe_rx_ring[cons];
1094 rxheader = mtod(m, struct bfe_rxheader*);
1095 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTWRITE);
1096 len = rxheader->len;
1099 bus_dmamap_unload(sc->bfe_tag, r->bfe_map);
1100 flags = rxheader->flags;
1102 len -= ETHER_CRC_LEN;
1104 /* flag an error and try again */
1105 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) {
1107 if (flags & BFE_RX_FLAG_SERR)
1108 ifp->if_collisions++;
1109 bfe_list_newbuf(sc, cons, m);
1110 BFE_INC(cons, BFE_RX_LIST_CNT);
1114 /* Go past the rx header */
1115 if (bfe_list_newbuf(sc, cons, NULL) != 0) {
1116 bfe_list_newbuf(sc, cons, m);
1117 BFE_INC(cons, BFE_RX_LIST_CNT);
1122 m_adj(m, BFE_RX_OFFSET);
1123 m->m_len = m->m_pkthdr.len = len;
1126 m->m_pkthdr.rcvif = ifp;
1128 (*ifp->if_input)(ifp, m);
1129 BFE_INC(cons, BFE_RX_LIST_CNT);
1131 sc->bfe_rx_cons = cons;
1139 struct bfe_softc *sc = xsc;
1140 struct ifnet *ifp = &sc->arpcom.ac_if;
1141 uint32_t istat, imask, flag;
1145 istat = CSR_READ_4(sc, BFE_ISTAT);
1146 imask = CSR_READ_4(sc, BFE_IMASK);
1149 * Defer unsolicited interrupts - This is necessary because setting the
1150 * chips interrupt mask register to 0 doesn't actually stop the
1154 CSR_WRITE_4(sc, BFE_ISTAT, istat);
1155 CSR_READ_4(sc, BFE_ISTAT);
1157 /* not expecting this interrupt, disregard it */
1163 if (istat & BFE_ISTAT_ERRORS) {
1164 flag = CSR_READ_4(sc, BFE_DMATX_STAT);
1165 if (flag & BFE_STAT_EMASK)
1168 flag = CSR_READ_4(sc, BFE_DMARX_STAT);
1169 if (flag & BFE_RX_FLAG_ERRORS)
1172 ifp->if_flags &= ~IFF_RUNNING;
1176 /* A packet was received */
1177 if (istat & BFE_ISTAT_RX)
1180 /* A packet was sent */
1181 if (istat & BFE_ISTAT_TX)
1184 /* We have packets pending, fire them out */
1185 if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd))
1192 bfe_encap(struct bfe_softc *sc, struct mbuf *m_head, uint32_t *txidx)
1194 struct bfe_desc *d = NULL;
1195 struct bfe_data *r = NULL;
1197 uint32_t frag, cur, cnt = 0;
1199 if (BFE_TX_LIST_CNT - sc->bfe_tx_cnt < 2)
1203 * Start packing the mbufs in this chain into
1204 * the fragment pointers. Stop when we run out
1205 * of fragments or hit the end of the mbuf chain.
1208 cur = frag = *txidx;
1211 for (m = m_head; m != NULL; m = m->m_next) {
1212 if (m->m_len != 0) {
1213 if ((BFE_TX_LIST_CNT - (sc->bfe_tx_cnt + cnt)) < 2)
1216 d = &sc->bfe_tx_list[cur];
1217 r = &sc->bfe_tx_ring[cur];
1218 d->bfe_ctrl = BFE_DESC_LEN & m->m_len;
1219 /* always intterupt on completion */
1220 d->bfe_ctrl |= BFE_DESC_IOC;
1222 /* Set start of frame */
1223 d->bfe_ctrl |= BFE_DESC_SOF;
1224 if (cur == BFE_TX_LIST_CNT - 1)
1226 * Tell the chip to wrap to the start of the
1229 d->bfe_ctrl |= BFE_DESC_EOT;
1231 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void*),
1232 m->m_len, bfe_dma_map_desc, d, 0);
1233 bus_dmamap_sync(sc->bfe_tag, r->bfe_map,
1234 BUS_DMASYNC_PREREAD);
1237 BFE_INC(cur, BFE_TX_LIST_CNT);
1245 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF;
1246 sc->bfe_tx_ring[frag].bfe_mbuf = m_head;
1247 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD);
1250 sc->bfe_tx_cnt += cnt;
1255 * Set up to transmit a packet
1258 bfe_start(struct ifnet *ifp)
1260 struct bfe_softc *sc = ifp->if_softc;
1261 struct mbuf *m_head = NULL;
1267 * not much point trying to send if the link is down or we have nothing to
1270 if (!sc->bfe_link) {
1275 if (ifp->if_flags & IFF_OACTIVE) {
1280 idx = sc->bfe_tx_prod;
1282 while (sc->bfe_tx_ring[idx].bfe_mbuf == NULL) {
1283 m_head = ifq_poll(&ifp->if_snd);
1288 * Pack the data into the tx ring. If we dont have enough room, let
1289 * the chip drain the ring
1291 if (bfe_encap(sc, m_head, &idx)) {
1292 ifp->if_flags |= IFF_OACTIVE;
1295 m_head = ifq_dequeue(&ifp->if_snd);
1298 * If there's a BPF listener, bounce a copy of this frame
1301 BPF_MTAP(ifp, m_head);
1304 sc->bfe_tx_prod = idx;
1305 /* Transmit - twice due to apparent hardware bug */
1306 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc));
1307 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc));
1310 * Set a timeout in case the chip goes out to lunch.
1320 struct bfe_softc *sc = (struct bfe_softc*)xsc;
1321 struct ifnet *ifp = &sc->arpcom.ac_if;
1325 if (ifp->if_flags & IFF_RUNNING) {
1333 if (bfe_list_rx_init(sc) == ENOBUFS) {
1334 if_printf(ifp, "bfe_init failed. "
1335 " Not enough memory for list buffers\n");
1341 bfe_set_rx_mode(sc);
1343 /* Enable the chip and core */
1344 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE);
1345 /* Enable interrupts */
1346 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF);
1348 bfe_ifmedia_upd(ifp);
1349 ifp->if_flags |= IFF_RUNNING;
1350 ifp->if_flags &= ~IFF_OACTIVE;
1352 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc);
1357 * Set media options.
1360 bfe_ifmedia_upd(struct ifnet *ifp)
1362 struct bfe_softc *sc = ifp->if_softc;
1363 struct mii_data *mii;
1367 mii = device_get_softc(sc->bfe_miibus);
1369 if (mii->mii_instance) {
1370 struct mii_softc *miisc;
1371 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1372 miisc = LIST_NEXT(miisc, mii_list))
1373 mii_phy_reset(miisc);
1382 * Report current media status.
1385 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1387 struct bfe_softc *sc = ifp->if_softc;
1388 struct mii_data *mii;
1392 mii = device_get_softc(sc->bfe_miibus);
1394 ifmr->ifm_active = mii->mii_media_active;
1395 ifmr->ifm_status = mii->mii_media_status;
1401 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1403 struct bfe_softc *sc = ifp->if_softc;
1404 struct ifreq *ifr = (struct ifreq *) data;
1405 struct mii_data *mii;
1412 if (ifp->if_flags & IFF_UP)
1413 if (ifp->if_flags & IFF_RUNNING)
1414 bfe_set_rx_mode(sc);
1417 else if (ifp->if_flags & IFF_RUNNING)
1422 if (ifp->if_flags & IFF_RUNNING)
1423 bfe_set_rx_mode(sc);
1427 mii = device_get_softc(sc->bfe_miibus);
1428 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
1432 error = ether_ioctl(ifp, command, data);
1442 bfe_watchdog(struct ifnet *ifp)
1444 struct bfe_softc *sc = ifp->if_softc;
1446 if_printf(ifp, "watchdog timeout -- resetting\n");
1450 ifp->if_flags &= ~IFF_RUNNING;
1461 struct bfe_softc *sc = xsc;
1462 struct mii_data *mii;
1466 mii = device_get_softc(sc->bfe_miibus);
1468 bfe_stats_update(sc);
1469 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc);
1477 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE &&
1478 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
1488 * Stop the adapter and free any mbufs allocated to the
1492 bfe_stop(struct bfe_softc *sc)
1494 struct ifnet *ifp = &sc->arpcom.ac_if;
1498 callout_stop(&sc->bfe_stat_timer);
1501 bfe_tx_ring_free(sc);
1502 bfe_rx_ring_free(sc);
1504 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);