1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
79 #include "coretypes.h"
86 #include "hard-reg-set.h"
87 #include "basic-block.h"
88 #include "insn-config.h"
90 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
92 #include "insn-attr.h"
98 #include "insn-codes.h"
99 #include "rtlhooks-def.h"
100 /* Include output.h for dump_file. */
104 #include "tree-pass.h"
106 /* Number of attempts to combine instructions in this function. */
108 static int combine_attempts;
110 /* Number of attempts that got as far as substitution in this function. */
112 static int combine_merges;
114 /* Number of instructions combined with added SETs in this function. */
116 static int combine_extras;
118 /* Number of instructions combined in this function. */
120 static int combine_successes;
122 /* Totals over entire compilation. */
124 static int total_attempts, total_merges, total_extras, total_successes;
126 /* combine_instructions may try to replace the right hand side of the
127 second instruction with the value of an associated REG_EQUAL note
128 before throwing it at try_combine. That is problematic when there
129 is a REG_DEAD note for a register used in the old right hand side
130 and can cause distribute_notes to do wrong things. This is the
131 second instruction if it has been so modified, null otherwise. */
135 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
137 static rtx i2mod_old_rhs;
139 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
141 static rtx i2mod_new_rhs;
143 /* Vector mapping INSN_UIDs to cuids.
144 The cuids are like uids but increase monotonically always.
145 Combine always uses cuids so that it can compare them.
146 But actually renumbering the uids, which we used to do,
147 proves to be a bad idea because it makes it hard to compare
148 the dumps produced by earlier passes with those from later passes. */
150 static int *uid_cuid;
151 static int max_uid_cuid;
153 /* Get the cuid of an insn. */
155 #define INSN_CUID(INSN) \
156 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
158 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
159 BITS_PER_WORD would invoke undefined behavior. Work around it. */
161 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
162 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
164 /* Maximum register number, which is the size of the tables below. */
166 static unsigned int combine_max_regno;
169 /* Record last point of death of (hard or pseudo) register n. */
172 /* Record last point of modification of (hard or pseudo) register n. */
175 /* The next group of fields allows the recording of the last value assigned
176 to (hard or pseudo) register n. We use this information to see if an
177 operation being processed is redundant given a prior operation performed
178 on the register. For example, an `and' with a constant is redundant if
179 all the zero bits are already known to be turned off.
181 We use an approach similar to that used by cse, but change it in the
184 (1) We do not want to reinitialize at each label.
185 (2) It is useful, but not critical, to know the actual value assigned
186 to a register. Often just its form is helpful.
188 Therefore, we maintain the following fields:
190 last_set_value the last value assigned
191 last_set_label records the value of label_tick when the
192 register was assigned
193 last_set_table_tick records the value of label_tick when a
194 value using the register is assigned
195 last_set_invalid set to nonzero when it is not valid
196 to use the value of this register in some
199 To understand the usage of these tables, it is important to understand
200 the distinction between the value in last_set_value being valid and
201 the register being validly contained in some other expression in the
204 (The next two parameters are out of date).
206 reg_stat[i].last_set_value is valid if it is nonzero, and either
207 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
209 Register I may validly appear in any expression returned for the value
210 of another register if reg_n_sets[i] is 1. It may also appear in the
211 value for register J if reg_stat[j].last_set_invalid is zero, or
212 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
214 If an expression is found in the table containing a register which may
215 not validly appear in an expression, the register is replaced by
216 something that won't match, (clobber (const_int 0)). */
218 /* Record last value assigned to (hard or pseudo) register n. */
222 /* Record the value of label_tick when an expression involving register n
223 is placed in last_set_value. */
225 int last_set_table_tick;
227 /* Record the value of label_tick when the value for register n is placed in
232 /* These fields are maintained in parallel with last_set_value and are
233 used to store the mode in which the register was last set, the bits
234 that were known to be zero when it was last set, and the number of
235 sign bits copies it was known to have when it was last set. */
237 unsigned HOST_WIDE_INT last_set_nonzero_bits;
238 char last_set_sign_bit_copies;
239 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
241 /* Set nonzero if references to register n in expressions should not be
242 used. last_set_invalid is set nonzero when this register is being
243 assigned to and last_set_table_tick == label_tick. */
245 char last_set_invalid;
247 /* Some registers that are set more than once and used in more than one
248 basic block are nevertheless always set in similar ways. For example,
249 a QImode register may be loaded from memory in two places on a machine
250 where byte loads zero extend.
252 We record in the following fields if a register has some leading bits
253 that are always equal to the sign bit, and what we know about the
254 nonzero bits of a register, specifically which bits are known to be
257 If an entry is zero, it means that we don't know anything special. */
259 unsigned char sign_bit_copies;
261 unsigned HOST_WIDE_INT nonzero_bits;
264 static struct reg_stat *reg_stat;
266 /* Record the cuid of the last insn that invalidated memory
267 (anything that writes memory, and subroutine calls, but not pushes). */
269 static int mem_last_set;
271 /* Record the cuid of the last CALL_INSN
272 so we can tell whether a potential combination crosses any calls. */
274 static int last_call_cuid;
276 /* When `subst' is called, this is the insn that is being modified
277 (by combining in a previous insn). The PATTERN of this insn
278 is still the old pattern partially modified and it should not be
279 looked at, but this may be used to examine the successors of the insn
280 to judge whether a simplification is valid. */
282 static rtx subst_insn;
284 /* This is the lowest CUID that `subst' is currently dealing with.
285 get_last_value will not return a value if the register was set at or
286 after this CUID. If not for this mechanism, we could get confused if
287 I2 or I1 in try_combine were an insn that used the old value of a register
288 to obtain a new value. In that case, we might erroneously get the
289 new value of the register when we wanted the old one. */
291 static int subst_low_cuid;
293 /* This contains any hard registers that are used in newpat; reg_dead_at_p
294 must consider all these registers to be always live. */
296 static HARD_REG_SET newpat_used_regs;
298 /* This is an insn to which a LOG_LINKS entry has been added. If this
299 insn is the earlier than I2 or I3, combine should rescan starting at
302 static rtx added_links_insn;
304 /* Basic block in which we are performing combines. */
305 static basic_block this_basic_block;
307 /* A bitmap indicating which blocks had registers go dead at entry.
308 After combine, we'll need to re-do global life analysis with
309 those blocks as starting points. */
310 static sbitmap refresh_blocks;
312 /* The following array records the insn_rtx_cost for every insn
313 in the instruction stream. */
315 static int *uid_insn_cost;
317 /* Length of the currently allocated uid_insn_cost array. */
319 static int last_insn_cost;
321 /* Incremented for each label. */
323 static int label_tick;
325 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
326 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
328 static enum machine_mode nonzero_bits_mode;
330 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
331 be safely used. It is zero while computing them and after combine has
332 completed. This former test prevents propagating values based on
333 previously set values, which can be incorrect if a variable is modified
336 static int nonzero_sign_valid;
339 /* Record one modification to rtl structure
340 to be undone by storing old_contents into *where.
341 is_int is 1 if the contents are an int. */
347 union {rtx r; int i;} old_contents;
348 union {rtx *r; int *i;} where;
351 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
352 num_undo says how many are currently recorded.
354 other_insn is nonzero if we have modified some other insn in the process
355 of working on subst_insn. It must be verified too. */
364 static struct undobuf undobuf;
366 /* Number of times the pseudo being substituted for
367 was found and replaced. */
369 static int n_occurrences;
371 static rtx reg_nonzero_bits_for_combine (rtx, enum machine_mode, rtx,
373 unsigned HOST_WIDE_INT,
374 unsigned HOST_WIDE_INT *);
375 static rtx reg_num_sign_bit_copies_for_combine (rtx, enum machine_mode, rtx,
377 unsigned int, unsigned int *);
378 static void do_SUBST (rtx *, rtx);
379 static void do_SUBST_INT (int *, int);
380 static void init_reg_last (void);
381 static void setup_incoming_promotions (void);
382 static void set_nonzero_bits_and_sign_copies (rtx, rtx, void *);
383 static int cant_combine_insn_p (rtx);
384 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
385 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
386 static int contains_muldiv (rtx);
387 static rtx try_combine (rtx, rtx, rtx, int *);
388 static void undo_all (void);
389 static void undo_commit (void);
390 static rtx *find_split_point (rtx *, rtx);
391 static rtx subst (rtx, rtx, rtx, int, int);
392 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
393 static rtx simplify_if_then_else (rtx);
394 static rtx simplify_set (rtx);
395 static rtx simplify_logical (rtx);
396 static rtx expand_compound_operation (rtx);
397 static rtx expand_field_assignment (rtx);
398 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
399 rtx, unsigned HOST_WIDE_INT, int, int, int);
400 static rtx extract_left_shift (rtx, int);
401 static rtx make_compound_operation (rtx, enum rtx_code);
402 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
403 unsigned HOST_WIDE_INT *);
404 static rtx force_to_mode (rtx, enum machine_mode,
405 unsigned HOST_WIDE_INT, rtx, int);
406 static rtx if_then_else_cond (rtx, rtx *, rtx *);
407 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
408 static int rtx_equal_for_field_assignment_p (rtx, rtx);
409 static rtx make_field_assignment (rtx);
410 static rtx apply_distributive_law (rtx);
411 static rtx distribute_and_simplify_rtx (rtx, int);
412 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
413 unsigned HOST_WIDE_INT);
414 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
415 HOST_WIDE_INT, enum machine_mode, int *);
416 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
418 static int recog_for_combine (rtx *, rtx, rtx *);
419 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
420 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
421 static void update_table_tick (rtx);
422 static void record_value_for_reg (rtx, rtx, rtx);
423 static void check_promoted_subreg (rtx, rtx);
424 static void record_dead_and_set_regs_1 (rtx, rtx, void *);
425 static void record_dead_and_set_regs (rtx);
426 static int get_last_value_validate (rtx *, rtx, int, int);
427 static rtx get_last_value (rtx);
428 static int use_crosses_set_p (rtx, int);
429 static void reg_dead_at_p_1 (rtx, rtx, void *);
430 static int reg_dead_at_p (rtx, rtx);
431 static void move_deaths (rtx, rtx, int, rtx, rtx *);
432 static int reg_bitfield_target_p (rtx, rtx);
433 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx);
434 static void distribute_links (rtx);
435 static void mark_used_regs_combine (rtx);
436 static int insn_cuid (rtx);
437 static void record_promoted_value (rtx, rtx);
438 static int unmentioned_reg_p_1 (rtx *, void *);
439 static bool unmentioned_reg_p (rtx, rtx);
442 /* It is not safe to use ordinary gen_lowpart in combine.
443 See comments in gen_lowpart_for_combine. */
444 #undef RTL_HOOKS_GEN_LOWPART
445 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
447 /* Our implementation of gen_lowpart never emits a new pseudo. */
448 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
449 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
451 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
452 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
454 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
455 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
457 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
460 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
461 insn. The substitution can be undone by undo_all. If INTO is already
462 set to NEWVAL, do not record this change. Because computing NEWVAL might
463 also call SUBST, we have to compute it before we put anything into
467 do_SUBST (rtx *into, rtx newval)
472 if (oldval == newval)
475 /* We'd like to catch as many invalid transformations here as
476 possible. Unfortunately, there are way too many mode changes
477 that are perfectly valid, so we'd waste too much effort for
478 little gain doing the checks here. Focus on catching invalid
479 transformations involving integer constants. */
480 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
481 && GET_CODE (newval) == CONST_INT)
483 /* Sanity check that we're replacing oldval with a CONST_INT
484 that is a valid sign-extension for the original mode. */
485 gcc_assert (INTVAL (newval)
486 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
488 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
489 CONST_INT is not valid, because after the replacement, the
490 original mode would be gone. Unfortunately, we can't tell
491 when do_SUBST is called to replace the operand thereof, so we
492 perform this test on oldval instead, checking whether an
493 invalid replacement took place before we got here. */
494 gcc_assert (!(GET_CODE (oldval) == SUBREG
495 && GET_CODE (SUBREG_REG (oldval)) == CONST_INT));
496 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
497 && GET_CODE (XEXP (oldval, 0)) == CONST_INT));
501 buf = undobuf.frees, undobuf.frees = buf->next;
503 buf = xmalloc (sizeof (struct undo));
507 buf->old_contents.r = oldval;
510 buf->next = undobuf.undos, undobuf.undos = buf;
513 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
515 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
516 for the value of a HOST_WIDE_INT value (including CONST_INT) is
520 do_SUBST_INT (int *into, int newval)
525 if (oldval == newval)
529 buf = undobuf.frees, undobuf.frees = buf->next;
531 buf = xmalloc (sizeof (struct undo));
535 buf->old_contents.i = oldval;
538 buf->next = undobuf.undos, undobuf.undos = buf;
541 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
543 /* Subroutine of try_combine. Determine whether the combine replacement
544 patterns NEWPAT and NEWI2PAT are cheaper according to insn_rtx_cost
545 that the original instruction sequence I1, I2 and I3. Note that I1
546 and/or NEWI2PAT may be NULL_RTX. This function returns false, if the
547 costs of all instructions can be estimated, and the replacements are
548 more expensive than the original sequence. */
551 combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat)
553 int i1_cost, i2_cost, i3_cost;
554 int new_i2_cost, new_i3_cost;
555 int old_cost, new_cost;
557 /* Lookup the original insn_rtx_costs. */
558 i2_cost = INSN_UID (i2) <= last_insn_cost
559 ? uid_insn_cost[INSN_UID (i2)] : 0;
560 i3_cost = INSN_UID (i3) <= last_insn_cost
561 ? uid_insn_cost[INSN_UID (i3)] : 0;
565 i1_cost = INSN_UID (i1) <= last_insn_cost
566 ? uid_insn_cost[INSN_UID (i1)] : 0;
567 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0)
568 ? i1_cost + i2_cost + i3_cost : 0;
572 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
576 /* Calculate the replacement insn_rtx_costs. */
577 new_i3_cost = insn_rtx_cost (newpat);
580 new_i2_cost = insn_rtx_cost (newi2pat);
581 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
582 ? new_i2_cost + new_i3_cost : 0;
586 new_cost = new_i3_cost;
590 if (undobuf.other_insn)
592 int old_other_cost, new_other_cost;
594 old_other_cost = (INSN_UID (undobuf.other_insn) <= last_insn_cost
595 ? uid_insn_cost[INSN_UID (undobuf.other_insn)] : 0);
596 new_other_cost = insn_rtx_cost (PATTERN (undobuf.other_insn));
597 if (old_other_cost > 0 && new_other_cost > 0)
599 old_cost += old_other_cost;
600 new_cost += new_other_cost;
606 /* Disallow this recombination if both new_cost and old_cost are
607 greater than zero, and new_cost is greater than old cost. */
609 && new_cost > old_cost)
616 "rejecting combination of insns %d, %d and %d\n",
617 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
618 fprintf (dump_file, "original costs %d + %d + %d = %d\n",
619 i1_cost, i2_cost, i3_cost, old_cost);
624 "rejecting combination of insns %d and %d\n",
625 INSN_UID (i2), INSN_UID (i3));
626 fprintf (dump_file, "original costs %d + %d = %d\n",
627 i2_cost, i3_cost, old_cost);
632 fprintf (dump_file, "replacement costs %d + %d = %d\n",
633 new_i2_cost, new_i3_cost, new_cost);
636 fprintf (dump_file, "replacement cost %d\n", new_cost);
642 /* Update the uid_insn_cost array with the replacement costs. */
643 uid_insn_cost[INSN_UID (i2)] = new_i2_cost;
644 uid_insn_cost[INSN_UID (i3)] = new_i3_cost;
646 uid_insn_cost[INSN_UID (i1)] = 0;
651 /* Main entry point for combiner. F is the first insn of the function.
652 NREGS is the first unused pseudo-reg number.
654 Return nonzero if the combiner has turned an indirect jump
655 instruction into a direct jump. */
657 combine_instructions (rtx f, unsigned int nregs)
665 rtx links, nextlinks;
666 sbitmap_iterator sbi;
668 int new_direct_jump_p = 0;
670 combine_attempts = 0;
673 combine_successes = 0;
675 combine_max_regno = nregs;
677 rtl_hooks = combine_rtl_hooks;
679 reg_stat = xcalloc (nregs, sizeof (struct reg_stat));
681 init_recog_no_volatile ();
683 /* Compute maximum uid value so uid_cuid can be allocated. */
685 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
686 if (INSN_UID (insn) > i)
689 uid_cuid = xmalloc ((i + 1) * sizeof (int));
692 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
694 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
695 problems when, for example, we have j <<= 1 in a loop. */
697 nonzero_sign_valid = 0;
699 /* Compute the mapping from uids to cuids.
700 Cuids are numbers assigned to insns, like uids,
701 except that cuids increase monotonically through the code.
703 Scan all SETs and see if we can deduce anything about what
704 bits are known to be zero for some registers and how many copies
705 of the sign bit are known to exist for those registers.
707 Also set any known values so that we can use it while searching
708 for what bits are known to be set. */
712 setup_incoming_promotions ();
714 refresh_blocks = sbitmap_alloc (last_basic_block);
715 sbitmap_zero (refresh_blocks);
717 /* Allocate array of current insn_rtx_costs. */
718 uid_insn_cost = xcalloc (max_uid_cuid + 1, sizeof (int));
719 last_insn_cost = max_uid_cuid;
721 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
723 uid_cuid[INSN_UID (insn)] = ++i;
729 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
731 record_dead_and_set_regs (insn);
734 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
735 if (REG_NOTE_KIND (links) == REG_INC)
736 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
740 /* Record the current insn_rtx_cost of this instruction. */
741 if (NONJUMP_INSN_P (insn))
742 uid_insn_cost[INSN_UID (insn)] = insn_rtx_cost (PATTERN (insn));
744 fprintf(dump_file, "insn_cost %d: %d\n",
745 INSN_UID (insn), uid_insn_cost[INSN_UID (insn)]);
752 nonzero_sign_valid = 1;
754 /* Now scan all the insns in forward order. */
760 setup_incoming_promotions ();
762 FOR_EACH_BB (this_basic_block)
764 for (insn = BB_HEAD (this_basic_block);
765 insn != NEXT_INSN (BB_END (this_basic_block));
766 insn = next ? next : NEXT_INSN (insn))
773 else if (INSN_P (insn))
775 /* See if we know about function return values before this
776 insn based upon SUBREG flags. */
777 check_promoted_subreg (insn, PATTERN (insn));
779 /* Try this insn with each insn it links back to. */
781 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
782 if ((next = try_combine (insn, XEXP (links, 0),
783 NULL_RTX, &new_direct_jump_p)) != 0)
786 /* Try each sequence of three linked insns ending with this one. */
788 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
790 rtx link = XEXP (links, 0);
792 /* If the linked insn has been replaced by a note, then there
793 is no point in pursuing this chain any further. */
797 for (nextlinks = LOG_LINKS (link);
799 nextlinks = XEXP (nextlinks, 1))
800 if ((next = try_combine (insn, link,
802 &new_direct_jump_p)) != 0)
807 /* Try to combine a jump insn that uses CC0
808 with a preceding insn that sets CC0, and maybe with its
809 logical predecessor as well.
810 This is how we make decrement-and-branch insns.
811 We need this special code because data flow connections
812 via CC0 do not get entered in LOG_LINKS. */
815 && (prev = prev_nonnote_insn (insn)) != 0
816 && NONJUMP_INSN_P (prev)
817 && sets_cc0_p (PATTERN (prev)))
819 if ((next = try_combine (insn, prev,
820 NULL_RTX, &new_direct_jump_p)) != 0)
823 for (nextlinks = LOG_LINKS (prev); nextlinks;
824 nextlinks = XEXP (nextlinks, 1))
825 if ((next = try_combine (insn, prev,
827 &new_direct_jump_p)) != 0)
831 /* Do the same for an insn that explicitly references CC0. */
832 if (NONJUMP_INSN_P (insn)
833 && (prev = prev_nonnote_insn (insn)) != 0
834 && NONJUMP_INSN_P (prev)
835 && sets_cc0_p (PATTERN (prev))
836 && GET_CODE (PATTERN (insn)) == SET
837 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
839 if ((next = try_combine (insn, prev,
840 NULL_RTX, &new_direct_jump_p)) != 0)
843 for (nextlinks = LOG_LINKS (prev); nextlinks;
844 nextlinks = XEXP (nextlinks, 1))
845 if ((next = try_combine (insn, prev,
847 &new_direct_jump_p)) != 0)
851 /* Finally, see if any of the insns that this insn links to
852 explicitly references CC0. If so, try this insn, that insn,
853 and its predecessor if it sets CC0. */
854 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
855 if (NONJUMP_INSN_P (XEXP (links, 0))
856 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
857 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
858 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
859 && NONJUMP_INSN_P (prev)
860 && sets_cc0_p (PATTERN (prev))
861 && (next = try_combine (insn, XEXP (links, 0),
862 prev, &new_direct_jump_p)) != 0)
866 /* Try combining an insn with two different insns whose results it
868 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
869 for (nextlinks = XEXP (links, 1); nextlinks;
870 nextlinks = XEXP (nextlinks, 1))
871 if ((next = try_combine (insn, XEXP (links, 0),
873 &new_direct_jump_p)) != 0)
876 /* Try this insn with each REG_EQUAL note it links back to. */
877 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
880 rtx temp = XEXP (links, 0);
881 if ((set = single_set (temp)) != 0
882 && (note = find_reg_equal_equiv_note (temp)) != 0
883 && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
884 /* Avoid using a register that may already been marked
885 dead by an earlier instruction. */
886 && ! unmentioned_reg_p (note, SET_SRC (set))
887 && (GET_MODE (note) == VOIDmode
888 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
889 : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
891 /* Temporarily replace the set's source with the
892 contents of the REG_EQUAL note. The insn will
893 be deleted or recognized by try_combine. */
894 rtx orig = SET_SRC (set);
895 SET_SRC (set) = note;
897 i2mod_old_rhs = copy_rtx (orig);
898 i2mod_new_rhs = copy_rtx (note);
899 next = try_combine (insn, i2mod, NULL_RTX,
904 SET_SRC (set) = orig;
909 record_dead_and_set_regs (insn);
918 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, j, sbi)
919 BASIC_BLOCK (j)->flags |= BB_DIRTY;
920 new_direct_jump_p |= purge_all_dead_edges ();
921 delete_noop_moves ();
923 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES,
924 PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE
925 | PROP_KILL_DEAD_CODE);
928 sbitmap_free (refresh_blocks);
929 free (uid_insn_cost);
934 struct undo *undo, *next;
935 for (undo = undobuf.frees; undo; undo = next)
943 total_attempts += combine_attempts;
944 total_merges += combine_merges;
945 total_extras += combine_extras;
946 total_successes += combine_successes;
948 nonzero_sign_valid = 0;
949 rtl_hooks = general_rtl_hooks;
951 /* Make recognizer allow volatile MEMs again. */
954 return new_direct_jump_p;
957 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
963 for (i = 0; i < combine_max_regno; i++)
964 memset (reg_stat + i, 0, offsetof (struct reg_stat, sign_bit_copies));
967 /* Set up any promoted values for incoming argument registers. */
970 setup_incoming_promotions (void)
974 enum machine_mode mode;
976 rtx first = get_insns ();
978 if (targetm.calls.promote_function_args (TREE_TYPE (cfun->decl)))
980 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
981 /* Check whether this register can hold an incoming pointer
982 argument. FUNCTION_ARG_REGNO_P tests outgoing register
983 numbers, so translate if necessary due to register windows. */
984 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
985 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
988 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
991 gen_rtx_CLOBBER (mode, const0_rtx)));
996 /* Called via note_stores. If X is a pseudo that is narrower than
997 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
999 If we are setting only a portion of X and we can't figure out what
1000 portion, assume all bits will be used since we don't know what will
1003 Similarly, set how many bits of X are known to be copies of the sign bit
1004 at all locations in the function. This is the smallest number implied
1008 set_nonzero_bits_and_sign_copies (rtx x, rtx set,
1009 void *data ATTRIBUTE_UNUSED)
1014 && REGNO (x) >= FIRST_PSEUDO_REGISTER
1015 /* If this register is undefined at the start of the file, we can't
1016 say what its contents were. */
1017 && ! REGNO_REG_SET_P
1018 (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start, REGNO (x))
1019 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1021 if (set == 0 || GET_CODE (set) == CLOBBER)
1023 reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1024 reg_stat[REGNO (x)].sign_bit_copies = 1;
1028 /* If this is a complex assignment, see if we can convert it into a
1029 simple assignment. */
1030 set = expand_field_assignment (set);
1032 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1033 set what we know about X. */
1035 if (SET_DEST (set) == x
1036 || (GET_CODE (SET_DEST (set)) == SUBREG
1037 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1038 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1039 && SUBREG_REG (SET_DEST (set)) == x))
1041 rtx src = SET_SRC (set);
1043 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1044 /* If X is narrower than a word and SRC is a non-negative
1045 constant that would appear negative in the mode of X,
1046 sign-extend it for use in reg_stat[].nonzero_bits because some
1047 machines (maybe most) will actually do the sign-extension
1048 and this is the conservative approach.
1050 ??? For 2.5, try to tighten up the MD files in this regard
1051 instead of this kludge. */
1053 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1054 && GET_CODE (src) == CONST_INT
1056 && 0 != (INTVAL (src)
1057 & ((HOST_WIDE_INT) 1
1058 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1059 src = GEN_INT (INTVAL (src)
1060 | ((HOST_WIDE_INT) (-1)
1061 << GET_MODE_BITSIZE (GET_MODE (x))));
1064 /* Don't call nonzero_bits if it cannot change anything. */
1065 if (reg_stat[REGNO (x)].nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1066 reg_stat[REGNO (x)].nonzero_bits
1067 |= nonzero_bits (src, nonzero_bits_mode);
1068 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1069 if (reg_stat[REGNO (x)].sign_bit_copies == 0
1070 || reg_stat[REGNO (x)].sign_bit_copies > num)
1071 reg_stat[REGNO (x)].sign_bit_copies = num;
1075 reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1076 reg_stat[REGNO (x)].sign_bit_copies = 1;
1081 /* See if INSN can be combined into I3. PRED and SUCC are optionally
1082 insns that were previously combined into I3 or that will be combined
1083 into the merger of INSN and I3.
1085 Return 0 if the combination is not allowed for any reason.
1087 If the combination is allowed, *PDEST will be set to the single
1088 destination of INSN and *PSRC to the single source, and this function
1092 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
1093 rtx *pdest, rtx *psrc)
1096 rtx set = 0, src, dest;
1101 int all_adjacent = (succ ? (next_active_insn (insn) == succ
1102 && next_active_insn (succ) == i3)
1103 : next_active_insn (insn) == i3);
1105 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1106 or a PARALLEL consisting of such a SET and CLOBBERs.
1108 If INSN has CLOBBER parallel parts, ignore them for our processing.
1109 By definition, these happen during the execution of the insn. When it
1110 is merged with another insn, all bets are off. If they are, in fact,
1111 needed and aren't also supplied in I3, they may be added by
1112 recog_for_combine. Otherwise, it won't match.
1114 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1117 Get the source and destination of INSN. If more than one, can't
1120 if (GET_CODE (PATTERN (insn)) == SET)
1121 set = PATTERN (insn);
1122 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1123 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1125 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1127 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1130 switch (GET_CODE (elt))
1132 /* This is important to combine floating point insns
1133 for the SH4 port. */
1135 /* Combining an isolated USE doesn't make sense.
1136 We depend here on combinable_i3pat to reject them. */
1137 /* The code below this loop only verifies that the inputs of
1138 the SET in INSN do not change. We call reg_set_between_p
1139 to verify that the REG in the USE does not change between
1141 If the USE in INSN was for a pseudo register, the matching
1142 insn pattern will likely match any register; combining this
1143 with any other USE would only be safe if we knew that the
1144 used registers have identical values, or if there was
1145 something to tell them apart, e.g. different modes. For
1146 now, we forgo such complicated tests and simply disallow
1147 combining of USES of pseudo registers with any other USE. */
1148 if (REG_P (XEXP (elt, 0))
1149 && GET_CODE (PATTERN (i3)) == PARALLEL)
1151 rtx i3pat = PATTERN (i3);
1152 int i = XVECLEN (i3pat, 0) - 1;
1153 unsigned int regno = REGNO (XEXP (elt, 0));
1157 rtx i3elt = XVECEXP (i3pat, 0, i);
1159 if (GET_CODE (i3elt) == USE
1160 && REG_P (XEXP (i3elt, 0))
1161 && (REGNO (XEXP (i3elt, 0)) == regno
1162 ? reg_set_between_p (XEXP (elt, 0),
1163 PREV_INSN (insn), i3)
1164 : regno >= FIRST_PSEUDO_REGISTER))
1171 /* We can ignore CLOBBERs. */
1176 /* Ignore SETs whose result isn't used but not those that
1177 have side-effects. */
1178 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1179 && (!(note = find_reg_note (insn, REG_EH_REGION, NULL_RTX))
1180 || INTVAL (XEXP (note, 0)) <= 0)
1181 && ! side_effects_p (elt))
1184 /* If we have already found a SET, this is a second one and
1185 so we cannot combine with this insn. */
1193 /* Anything else means we can't combine. */
1199 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1200 so don't do anything with it. */
1201 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1210 set = expand_field_assignment (set);
1211 src = SET_SRC (set), dest = SET_DEST (set);
1213 /* Don't eliminate a store in the stack pointer. */
1214 if (dest == stack_pointer_rtx
1215 /* Don't combine with an insn that sets a register to itself if it has
1216 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1217 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1218 /* Can't merge an ASM_OPERANDS. */
1219 || GET_CODE (src) == ASM_OPERANDS
1220 /* Can't merge a function call. */
1221 || GET_CODE (src) == CALL
1222 /* Don't eliminate a function call argument. */
1224 && (find_reg_fusage (i3, USE, dest)
1226 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1227 && global_regs[REGNO (dest)])))
1228 /* Don't substitute into an incremented register. */
1229 || FIND_REG_INC_NOTE (i3, dest)
1230 || (succ && FIND_REG_INC_NOTE (succ, dest))
1231 /* Don't substitute into a non-local goto, this confuses CFG. */
1232 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1234 /* Don't combine the end of a libcall into anything. */
1235 /* ??? This gives worse code, and appears to be unnecessary, since no
1236 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1237 use REG_RETVAL notes for noconflict blocks, but other code here
1238 makes sure that those insns don't disappear. */
1239 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1241 /* Make sure that DEST is not used after SUCC but before I3. */
1242 || (succ && ! all_adjacent
1243 && reg_used_between_p (dest, succ, i3))
1244 /* Make sure that the value that is to be substituted for the register
1245 does not use any registers whose values alter in between. However,
1246 If the insns are adjacent, a use can't cross a set even though we
1247 think it might (this can happen for a sequence of insns each setting
1248 the same destination; last_set of that register might point to
1249 a NOTE). If INSN has a REG_EQUIV note, the register is always
1250 equivalent to the memory so the substitution is valid even if there
1251 are intervening stores. Also, don't move a volatile asm or
1252 UNSPEC_VOLATILE across any other insns. */
1255 || ! find_reg_note (insn, REG_EQUIV, src))
1256 && use_crosses_set_p (src, INSN_CUID (insn)))
1257 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1258 || GET_CODE (src) == UNSPEC_VOLATILE))
1259 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1260 better register allocation by not doing the combine. */
1261 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1262 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1263 /* Don't combine across a CALL_INSN, because that would possibly
1264 change whether the life span of some REGs crosses calls or not,
1265 and it is a pain to update that information.
1266 Exception: if source is a constant, moving it later can't hurt.
1267 Accept that special case, because it helps -fforce-addr a lot. */
1268 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1271 /* DEST must either be a REG or CC0. */
1274 /* If register alignment is being enforced for multi-word items in all
1275 cases except for parameters, it is possible to have a register copy
1276 insn referencing a hard register that is not allowed to contain the
1277 mode being copied and which would not be valid as an operand of most
1278 insns. Eliminate this problem by not combining with such an insn.
1280 Also, on some machines we don't want to extend the life of a hard
1284 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1285 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1286 /* Don't extend the life of a hard register unless it is
1287 user variable (if we have few registers) or it can't
1288 fit into the desired register (meaning something special
1290 Also avoid substituting a return register into I3, because
1291 reload can't handle a conflict with constraints of other
1293 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1294 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1297 else if (GET_CODE (dest) != CC0)
1301 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1302 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1303 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1305 /* Don't substitute for a register intended as a clobberable
1307 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1308 if (rtx_equal_p (reg, dest))
1311 /* If the clobber represents an earlyclobber operand, we must not
1312 substitute an expression containing the clobbered register.
1313 As we do not analyze the constraint strings here, we have to
1314 make the conservative assumption. However, if the register is
1315 a fixed hard reg, the clobber cannot represent any operand;
1316 we leave it up to the machine description to either accept or
1317 reject use-and-clobber patterns. */
1319 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1320 || !fixed_regs[REGNO (reg)])
1321 if (reg_overlap_mentioned_p (reg, src))
1325 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1326 or not), reject, unless nothing volatile comes between it and I3 */
1328 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1330 /* Make sure succ doesn't contain a volatile reference. */
1331 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1334 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1335 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1339 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1340 to be an explicit register variable, and was chosen for a reason. */
1342 if (GET_CODE (src) == ASM_OPERANDS
1343 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1346 /* If there are any volatile insns between INSN and I3, reject, because
1347 they might affect machine state. */
1349 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1350 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1353 /* If INSN contains an autoincrement or autodecrement, make sure that
1354 register is not used between there and I3, and not already used in
1355 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1356 Also insist that I3 not be a jump; if it were one
1357 and the incremented register were spilled, we would lose. */
1360 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1361 if (REG_NOTE_KIND (link) == REG_INC
1363 || reg_used_between_p (XEXP (link, 0), insn, i3)
1364 || (pred != NULL_RTX
1365 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1366 || (succ != NULL_RTX
1367 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1368 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1373 /* Don't combine an insn that follows a CC0-setting insn.
1374 An insn that uses CC0 must not be separated from the one that sets it.
1375 We do, however, allow I2 to follow a CC0-setting insn if that insn
1376 is passed as I1; in that case it will be deleted also.
1377 We also allow combining in this case if all the insns are adjacent
1378 because that would leave the two CC0 insns adjacent as well.
1379 It would be more logical to test whether CC0 occurs inside I1 or I2,
1380 but that would be much slower, and this ought to be equivalent. */
1382 p = prev_nonnote_insn (insn);
1383 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1388 /* If we get here, we have passed all the tests and the combination is
1397 /* LOC is the location within I3 that contains its pattern or the component
1398 of a PARALLEL of the pattern. We validate that it is valid for combining.
1400 One problem is if I3 modifies its output, as opposed to replacing it
1401 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1402 so would produce an insn that is not equivalent to the original insns.
1406 (set (reg:DI 101) (reg:DI 100))
1407 (set (subreg:SI (reg:DI 101) 0) <foo>)
1409 This is NOT equivalent to:
1411 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1412 (set (reg:DI 101) (reg:DI 100))])
1414 Not only does this modify 100 (in which case it might still be valid
1415 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1417 We can also run into a problem if I2 sets a register that I1
1418 uses and I1 gets directly substituted into I3 (not via I2). In that
1419 case, we would be getting the wrong value of I2DEST into I3, so we
1420 must reject the combination. This case occurs when I2 and I1 both
1421 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1422 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1423 of a SET must prevent combination from occurring.
1425 Before doing the above check, we first try to expand a field assignment
1426 into a set of logical operations.
1428 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1429 we place a register that is both set and used within I3. If more than one
1430 such register is detected, we fail.
1432 Return 1 if the combination is valid, zero otherwise. */
1435 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1436 int i1_not_in_src, rtx *pi3dest_killed)
1440 if (GET_CODE (x) == SET)
1443 rtx dest = SET_DEST (set);
1444 rtx src = SET_SRC (set);
1445 rtx inner_dest = dest;
1448 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1449 || GET_CODE (inner_dest) == SUBREG
1450 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1451 inner_dest = XEXP (inner_dest, 0);
1453 /* Check for the case where I3 modifies its output, as discussed
1454 above. We don't want to prevent pseudos from being combined
1455 into the address of a MEM, so only prevent the combination if
1456 i1 or i2 set the same MEM. */
1457 if ((inner_dest != dest &&
1458 (!MEM_P (inner_dest)
1459 || rtx_equal_p (i2dest, inner_dest)
1460 || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1461 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1462 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1464 /* This is the same test done in can_combine_p except we can't test
1465 all_adjacent; we don't have to, since this instruction will stay
1466 in place, thus we are not considering increasing the lifetime of
1469 Also, if this insn sets a function argument, combining it with
1470 something that might need a spill could clobber a previous
1471 function argument; the all_adjacent test in can_combine_p also
1472 checks this; here, we do a more specific test for this case. */
1474 || (REG_P (inner_dest)
1475 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1476 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1477 GET_MODE (inner_dest))))
1478 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1481 /* If DEST is used in I3, it is being killed in this insn, so
1482 record that for later. We have to consider paradoxical
1483 subregs here, since they kill the whole register, but we
1484 ignore partial subregs, STRICT_LOW_PART, etc.
1485 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1486 STACK_POINTER_REGNUM, since these are always considered to be
1487 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1489 if (GET_CODE (subdest) == SUBREG
1490 && (GET_MODE_SIZE (GET_MODE (subdest))
1491 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
1492 subdest = SUBREG_REG (subdest);
1495 && reg_referenced_p (subdest, PATTERN (i3))
1496 && REGNO (subdest) != FRAME_POINTER_REGNUM
1497 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1498 && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
1500 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1501 && (REGNO (subdest) != ARG_POINTER_REGNUM
1502 || ! fixed_regs [REGNO (subdest)])
1504 && REGNO (subdest) != STACK_POINTER_REGNUM)
1506 if (*pi3dest_killed)
1509 *pi3dest_killed = subdest;
1513 else if (GET_CODE (x) == PARALLEL)
1517 for (i = 0; i < XVECLEN (x, 0); i++)
1518 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1519 i1_not_in_src, pi3dest_killed))
1526 /* Return 1 if X is an arithmetic expression that contains a multiplication
1527 and division. We don't count multiplications by powers of two here. */
1530 contains_muldiv (rtx x)
1532 switch (GET_CODE (x))
1534 case MOD: case DIV: case UMOD: case UDIV:
1538 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1539 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1542 return contains_muldiv (XEXP (x, 0))
1543 || contains_muldiv (XEXP (x, 1));
1546 return contains_muldiv (XEXP (x, 0));
1552 /* Determine whether INSN can be used in a combination. Return nonzero if
1553 not. This is used in try_combine to detect early some cases where we
1554 can't perform combinations. */
1557 cant_combine_insn_p (rtx insn)
1562 /* If this isn't really an insn, we can't do anything.
1563 This can occur when flow deletes an insn that it has merged into an
1564 auto-increment address. */
1565 if (! INSN_P (insn))
1568 /* Never combine loads and stores involving hard regs that are likely
1569 to be spilled. The register allocator can usually handle such
1570 reg-reg moves by tying. If we allow the combiner to make
1571 substitutions of likely-spilled regs, reload might die.
1572 As an exception, we allow combinations involving fixed regs; these are
1573 not available to the register allocator so there's no risk involved. */
1575 set = single_set (insn);
1578 src = SET_SRC (set);
1579 dest = SET_DEST (set);
1580 if (GET_CODE (src) == SUBREG)
1581 src = SUBREG_REG (src);
1582 if (GET_CODE (dest) == SUBREG)
1583 dest = SUBREG_REG (dest);
1584 if (REG_P (src) && REG_P (dest)
1585 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1586 && ! fixed_regs[REGNO (src)]
1587 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
1588 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1589 && ! fixed_regs[REGNO (dest)]
1590 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
1596 struct likely_spilled_retval_info
1598 unsigned regno, nregs;
1602 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
1603 hard registers that are known to be written to / clobbered in full. */
1605 likely_spilled_retval_1 (rtx x, rtx set, void *data)
1607 struct likely_spilled_retval_info *info = data;
1608 unsigned regno, nregs;
1611 if (!REG_P (XEXP (set, 0)))
1614 if (regno >= info->regno + info->nregs)
1616 nregs = hard_regno_nregs[regno][GET_MODE (x)];
1617 if (regno + nregs <= info->regno)
1619 new_mask = (2U << (nregs - 1)) - 1;
1620 if (regno < info->regno)
1621 new_mask >>= info->regno - regno;
1623 new_mask <<= regno - info->regno;
1624 info->mask &= new_mask;
1627 /* Return nonzero iff part of the return value is live during INSN, and
1628 it is likely spilled. This can happen when more than one insn is needed
1629 to copy the return value, e.g. when we consider to combine into the
1630 second copy insn for a complex value. */
1633 likely_spilled_retval_p (rtx insn)
1635 rtx use = BB_END (this_basic_block);
1637 unsigned regno, nregs;
1638 /* We assume here that no machine mode needs more than
1639 32 hard registers when the value overlaps with a register
1640 for which FUNCTION_VALUE_REGNO_P is true. */
1642 struct likely_spilled_retval_info info;
1644 if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
1646 reg = XEXP (PATTERN (use), 0);
1647 if (!REG_P (reg) || !FUNCTION_VALUE_REGNO_P (REGNO (reg)))
1649 regno = REGNO (reg);
1650 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
1653 mask = (2U << (nregs - 1)) - 1;
1655 /* Disregard parts of the return value that are set later. */
1659 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
1660 note_stores (PATTERN (insn), likely_spilled_retval_1, &info);
1663 /* Check if any of the (probably) live return value registers is
1668 if ((mask & 1 << nregs)
1669 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno + nregs)))
1675 /* Adjust INSN after we made a change to its destination.
1677 Changing the destination can invalidate notes that say something about
1678 the results of the insn and a LOG_LINK pointing to the insn. */
1681 adjust_for_new_dest (rtx insn)
1685 /* For notes, be conservative and simply remove them. */
1686 loc = ®_NOTES (insn);
1689 enum reg_note kind = REG_NOTE_KIND (*loc);
1690 if (kind == REG_EQUAL || kind == REG_EQUIV)
1691 *loc = XEXP (*loc, 1);
1693 loc = &XEXP (*loc, 1);
1696 /* The new insn will have a destination that was previously the destination
1697 of an insn just above it. Call distribute_links to make a LOG_LINK from
1698 the next use of that destination. */
1699 distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
1702 /* Return TRUE if combine can reuse reg X in mode MODE.
1703 ADDED_SETS is nonzero if the original set is still required. */
1705 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
1713 /* Allow hard registers if the new mode is legal, and occupies no more
1714 registers than the old mode. */
1715 if (regno < FIRST_PSEUDO_REGISTER)
1716 return (HARD_REGNO_MODE_OK (regno, mode)
1717 && (hard_regno_nregs[regno][GET_MODE (x)]
1718 >= hard_regno_nregs[regno][mode]));
1720 /* Or a pseudo that is only used once. */
1721 return (REG_N_SETS (regno) == 1 && !added_sets
1722 && !REG_USERVAR_P (x));
1725 /* Try to combine the insns I1 and I2 into I3.
1726 Here I1 and I2 appear earlier than I3.
1727 I1 can be zero; then we combine just I2 into I3.
1729 If we are combining three insns and the resulting insn is not recognized,
1730 try splitting it into two insns. If that happens, I2 and I3 are retained
1731 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1734 Return 0 if the combination does not work. Then nothing is changed.
1735 If we did the combination, return the insn at which combine should
1738 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1739 new direct jump instruction. */
1742 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
1744 /* New patterns for I3 and I2, respectively. */
1745 rtx newpat, newi2pat = 0;
1746 rtvec newpat_vec_with_clobbers = 0;
1747 int substed_i2 = 0, substed_i1 = 0;
1748 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1749 int added_sets_1, added_sets_2;
1750 /* Total number of SETs to put into I3. */
1752 /* Nonzero if I2's body now appears in I3. */
1754 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1755 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1756 /* Contains I3 if the destination of I3 is used in its source, which means
1757 that the old life of I3 is being killed. If that usage is placed into
1758 I2 and not in I3, a REG_DEAD note must be made. */
1759 rtx i3dest_killed = 0;
1760 /* SET_DEST and SET_SRC of I2 and I1. */
1761 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1762 /* PATTERN (I1) and PATTERN (I2), or a copy of it in certain cases. */
1763 rtx i1pat = 0, i2pat = 0;
1764 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1765 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1766 int i2dest_killed = 0, i1dest_killed = 0;
1767 int i1_feeds_i3 = 0;
1768 /* Notes that must be added to REG_NOTES in I3 and I2. */
1769 rtx new_i3_notes, new_i2_notes;
1770 /* Notes that we substituted I3 into I2 instead of the normal case. */
1771 int i3_subst_into_i2 = 0;
1772 /* Notes that I1, I2 or I3 is a MULT operation. */
1781 /* Exit early if one of the insns involved can't be used for
1783 if (cant_combine_insn_p (i3)
1784 || cant_combine_insn_p (i2)
1785 || (i1 && cant_combine_insn_p (i1))
1786 || likely_spilled_retval_p (i3)
1787 /* We also can't do anything if I3 has a
1788 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1791 /* ??? This gives worse code, and appears to be unnecessary, since no
1792 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1793 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1799 undobuf.other_insn = 0;
1801 /* Reset the hard register usage information. */
1802 CLEAR_HARD_REG_SET (newpat_used_regs);
1804 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1805 code below, set I1 to be the earlier of the two insns. */
1806 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1807 temp = i1, i1 = i2, i2 = temp;
1809 added_links_insn = 0;
1811 /* First check for one important special-case that the code below will
1812 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1813 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1814 we may be able to replace that destination with the destination of I3.
1815 This occurs in the common code where we compute both a quotient and
1816 remainder into a structure, in which case we want to do the computation
1817 directly into the structure to avoid register-register copies.
1819 Note that this case handles both multiple sets in I2 and also
1820 cases where I2 has a number of CLOBBER or PARALLELs.
1822 We make very conservative checks below and only try to handle the
1823 most common cases of this. For example, we only handle the case
1824 where I2 and I3 are adjacent to avoid making difficult register
1827 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
1828 && REG_P (SET_SRC (PATTERN (i3)))
1829 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1830 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1831 && GET_CODE (PATTERN (i2)) == PARALLEL
1832 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1833 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1834 below would need to check what is inside (and reg_overlap_mentioned_p
1835 doesn't support those codes anyway). Don't allow those destinations;
1836 the resulting insn isn't likely to be recognized anyway. */
1837 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1838 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1839 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1840 SET_DEST (PATTERN (i3)))
1841 && next_real_insn (i2) == i3)
1843 rtx p2 = PATTERN (i2);
1845 /* Make sure that the destination of I3,
1846 which we are going to substitute into one output of I2,
1847 is not used within another output of I2. We must avoid making this:
1848 (parallel [(set (mem (reg 69)) ...)
1849 (set (reg 69) ...)])
1850 which is not well-defined as to order of actions.
1851 (Besides, reload can't handle output reloads for this.)
1853 The problem can also happen if the dest of I3 is a memory ref,
1854 if another dest in I2 is an indirect memory ref. */
1855 for (i = 0; i < XVECLEN (p2, 0); i++)
1856 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1857 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1858 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1859 SET_DEST (XVECEXP (p2, 0, i))))
1862 if (i == XVECLEN (p2, 0))
1863 for (i = 0; i < XVECLEN (p2, 0); i++)
1864 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1865 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1866 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1871 subst_low_cuid = INSN_CUID (i2);
1873 added_sets_2 = added_sets_1 = 0;
1874 i2dest = SET_SRC (PATTERN (i3));
1875 i2dest_killed = dead_or_set_p (i2, i2dest);
1877 /* Replace the dest in I2 with our dest and make the resulting
1878 insn the new pattern for I3. Then skip to where we
1879 validate the pattern. Everything was set up above. */
1880 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1881 SET_DEST (PATTERN (i3)));
1884 i3_subst_into_i2 = 1;
1885 goto validate_replacement;
1889 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1890 one of those words to another constant, merge them by making a new
1893 && (temp = single_set (i2)) != 0
1894 && (GET_CODE (SET_SRC (temp)) == CONST_INT
1895 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1896 && REG_P (SET_DEST (temp))
1897 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
1898 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
1899 && GET_CODE (PATTERN (i3)) == SET
1900 && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG
1901 && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp)
1902 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT
1903 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD
1904 && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT)
1906 HOST_WIDE_INT lo, hi;
1908 if (GET_CODE (SET_SRC (temp)) == CONST_INT)
1909 lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0;
1912 lo = CONST_DOUBLE_LOW (SET_SRC (temp));
1913 hi = CONST_DOUBLE_HIGH (SET_SRC (temp));
1916 if (subreg_lowpart_p (SET_DEST (PATTERN (i3))))
1918 /* We don't handle the case of the target word being wider
1919 than a host wide int. */
1920 gcc_assert (HOST_BITS_PER_WIDE_INT >= BITS_PER_WORD);
1922 lo &= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1923 lo |= (INTVAL (SET_SRC (PATTERN (i3)))
1924 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1926 else if (HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
1927 hi = INTVAL (SET_SRC (PATTERN (i3)));
1928 else if (HOST_BITS_PER_WIDE_INT >= 2 * BITS_PER_WORD)
1930 int sign = -(int) ((unsigned HOST_WIDE_INT) lo
1931 >> (HOST_BITS_PER_WIDE_INT - 1));
1933 lo &= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1934 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1935 lo |= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1936 (INTVAL (SET_SRC (PATTERN (i3)))));
1938 hi = lo < 0 ? -1 : 0;
1941 /* We don't handle the case of the higher word not fitting
1942 entirely in either hi or lo. */
1947 subst_low_cuid = INSN_CUID (i2);
1948 added_sets_2 = added_sets_1 = 0;
1949 i2dest = SET_DEST (temp);
1950 i2dest_killed = dead_or_set_p (i2, i2dest);
1952 SUBST (SET_SRC (temp),
1953 immed_double_const (lo, hi, GET_MODE (SET_DEST (temp))));
1955 newpat = PATTERN (i2);
1956 goto validate_replacement;
1960 /* If we have no I1 and I2 looks like:
1961 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1963 make up a dummy I1 that is
1966 (set (reg:CC X) (compare:CC Y (const_int 0)))
1968 (We can ignore any trailing CLOBBERs.)
1970 This undoes a previous combination and allows us to match a branch-and-
1973 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1974 && XVECLEN (PATTERN (i2), 0) >= 2
1975 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1976 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1978 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1979 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1980 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1981 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
1982 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1983 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1985 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1986 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1991 /* We make I1 with the same INSN_UID as I2. This gives it
1992 the same INSN_CUID for value tracking. Our fake I1 will
1993 never appear in the insn stream so giving it the same INSN_UID
1994 as I2 will not cause a problem. */
1996 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1997 BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
1998 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
2001 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2002 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2003 SET_DEST (PATTERN (i1)));
2008 /* Verify that I2 and I1 are valid for combining. */
2009 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
2010 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
2016 /* Record whether I2DEST is used in I2SRC and similarly for the other
2017 cases. Knowing this will help in register status updating below. */
2018 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2019 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2020 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2021 i2dest_killed = dead_or_set_p (i2, i2dest);
2022 i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2024 /* See if I1 directly feeds into I3. It does if I1DEST is not used
2026 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
2028 /* Ensure that I3's pattern can be the destination of combines. */
2029 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
2030 i1 && i2dest_in_i1src && i1_feeds_i3,
2037 /* See if any of the insns is a MULT operation. Unless one is, we will
2038 reject a combination that is, since it must be slower. Be conservative
2040 if (GET_CODE (i2src) == MULT
2041 || (i1 != 0 && GET_CODE (i1src) == MULT)
2042 || (GET_CODE (PATTERN (i3)) == SET
2043 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2046 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2047 We used to do this EXCEPT in one case: I3 has a post-inc in an
2048 output operand. However, that exception can give rise to insns like
2050 which is a famous insn on the PDP-11 where the value of r3 used as the
2051 source was model-dependent. Avoid this sort of thing. */
2054 if (!(GET_CODE (PATTERN (i3)) == SET
2055 && REG_P (SET_SRC (PATTERN (i3)))
2056 && MEM_P (SET_DEST (PATTERN (i3)))
2057 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2058 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2059 /* It's not the exception. */
2062 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2063 if (REG_NOTE_KIND (link) == REG_INC
2064 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2066 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2073 /* See if the SETs in I1 or I2 need to be kept around in the merged
2074 instruction: whenever the value set there is still needed past I3.
2075 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2077 For the SET in I1, we have two cases: If I1 and I2 independently
2078 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2079 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2080 in I1 needs to be kept around unless I1DEST dies or is set in either
2081 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
2082 I1DEST. If so, we know I1 feeds into I2. */
2084 added_sets_2 = ! dead_or_set_p (i3, i2dest);
2087 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
2088 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
2090 /* If the set in I2 needs to be kept around, we must make a copy of
2091 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2092 PATTERN (I2), we are only substituting for the original I1DEST, not into
2093 an already-substituted copy. This also prevents making self-referential
2094 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2099 if (GET_CODE (PATTERN (i2)) == PARALLEL)
2100 i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
2102 i2pat = copy_rtx (PATTERN (i2));
2107 if (GET_CODE (PATTERN (i1)) == PARALLEL)
2108 i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
2110 i1pat = copy_rtx (PATTERN (i1));
2115 /* Substitute in the latest insn for the regs set by the earlier ones. */
2117 maxreg = max_reg_num ();
2121 /* It is possible that the source of I2 or I1 may be performing an
2122 unneeded operation, such as a ZERO_EXTEND of something that is known
2123 to have the high part zero. Handle that case by letting subst look at
2124 the innermost one of them.
2126 Another way to do this would be to have a function that tries to
2127 simplify a single insn instead of merging two or more insns. We don't
2128 do this because of the potential of infinite loops and because
2129 of the potential extra memory required. However, doing it the way
2130 we are is a bit of a kludge and doesn't catch all cases.
2132 But only do this if -fexpensive-optimizations since it slows things down
2133 and doesn't usually win. */
2135 if (flag_expensive_optimizations)
2137 /* Pass pc_rtx so no substitutions are done, just simplifications. */
2140 subst_low_cuid = INSN_CUID (i1);
2141 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
2145 subst_low_cuid = INSN_CUID (i2);
2146 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
2151 /* Many machines that don't use CC0 have insns that can both perform an
2152 arithmetic operation and set the condition code. These operations will
2153 be represented as a PARALLEL with the first element of the vector
2154 being a COMPARE of an arithmetic operation with the constant zero.
2155 The second element of the vector will set some pseudo to the result
2156 of the same arithmetic operation. If we simplify the COMPARE, we won't
2157 match such a pattern and so will generate an extra insn. Here we test
2158 for this case, where both the comparison and the operation result are
2159 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2160 I2SRC. Later we will make the PARALLEL that contains I2. */
2162 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2163 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2164 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
2165 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2167 #ifdef SELECT_CC_MODE
2169 enum machine_mode compare_mode;
2172 newpat = PATTERN (i3);
2173 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
2177 #ifdef SELECT_CC_MODE
2178 /* See if a COMPARE with the operand we substituted in should be done
2179 with the mode that is currently being used. If not, do the same
2180 processing we do in `subst' for a SET; namely, if the destination
2181 is used only once, try to replace it with a register of the proper
2182 mode and also replace the COMPARE. */
2183 if (undobuf.other_insn == 0
2184 && (cc_use = find_single_use (SET_DEST (newpat), i3,
2185 &undobuf.other_insn))
2186 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
2188 != GET_MODE (SET_DEST (newpat))))
2190 if (can_change_dest_mode(SET_DEST (newpat), added_sets_2,
2193 unsigned int regno = REGNO (SET_DEST (newpat));
2194 rtx new_dest = gen_rtx_REG (compare_mode, regno);
2196 if (regno >= FIRST_PSEUDO_REGISTER)
2197 SUBST (regno_reg_rtx[regno], new_dest);
2199 SUBST (SET_DEST (newpat), new_dest);
2200 SUBST (XEXP (*cc_use, 0), new_dest);
2201 SUBST (SET_SRC (newpat),
2202 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
2205 undobuf.other_insn = 0;
2212 n_occurrences = 0; /* `subst' counts here */
2214 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2215 need to make a unique copy of I2SRC each time we substitute it
2216 to avoid self-referential rtl. */
2218 subst_low_cuid = INSN_CUID (i2);
2219 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
2220 ! i1_feeds_i3 && i1dest_in_i1src);
2223 /* Record whether i2's body now appears within i3's body. */
2224 i2_is_used = n_occurrences;
2227 /* If we already got a failure, don't try to do more. Otherwise,
2228 try to substitute in I1 if we have it. */
2230 if (i1 && GET_CODE (newpat) != CLOBBER)
2232 /* Before we can do this substitution, we must redo the test done
2233 above (see detailed comments there) that ensures that I1DEST
2234 isn't mentioned in any SETs in NEWPAT that are field assignments. */
2236 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
2244 subst_low_cuid = INSN_CUID (i1);
2245 newpat = subst (newpat, i1dest, i1src, 0, 0);
2249 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2250 to count all the ways that I2SRC and I1SRC can be used. */
2251 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2252 && i2_is_used + added_sets_2 > 1)
2253 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2254 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2256 /* Fail if we tried to make a new register. */
2257 || max_reg_num () != maxreg
2258 /* Fail if we couldn't do something and have a CLOBBER. */
2259 || GET_CODE (newpat) == CLOBBER
2260 /* Fail if this new pattern is a MULT and we didn't have one before
2261 at the outer level. */
2262 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2269 /* If the actions of the earlier insns must be kept
2270 in addition to substituting them into the latest one,
2271 we must make a new PARALLEL for the latest insn
2272 to hold additional the SETs. */
2274 if (added_sets_1 || added_sets_2)
2278 if (GET_CODE (newpat) == PARALLEL)
2280 rtvec old = XVEC (newpat, 0);
2281 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2282 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2283 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2284 sizeof (old->elem[0]) * old->num_elem);
2289 total_sets = 1 + added_sets_1 + added_sets_2;
2290 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2291 XVECEXP (newpat, 0, 0) = old;
2295 XVECEXP (newpat, 0, --total_sets) = i1pat;
2299 /* If there is no I1, use I2's body as is. We used to also not do
2300 the subst call below if I2 was substituted into I3,
2301 but that could lose a simplification. */
2303 XVECEXP (newpat, 0, --total_sets) = i2pat;
2305 /* See comment where i2pat is assigned. */
2306 XVECEXP (newpat, 0, --total_sets)
2307 = subst (i2pat, i1dest, i1src, 0, 0);
2311 /* We come here when we are replacing a destination in I2 with the
2312 destination of I3. */
2313 validate_replacement:
2315 /* Note which hard regs this insn has as inputs. */
2316 mark_used_regs_combine (newpat);
2318 /* If recog_for_combine fails, it strips existing clobbers. If we'll
2319 consider splitting this pattern, we might need these clobbers. */
2320 if (i1 && GET_CODE (newpat) == PARALLEL
2321 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
2323 int len = XVECLEN (newpat, 0);
2325 newpat_vec_with_clobbers = rtvec_alloc (len);
2326 for (i = 0; i < len; i++)
2327 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
2330 /* Is the result of combination a valid instruction? */
2331 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2333 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2334 the second SET's destination is a register that is unused and isn't
2335 marked as an instruction that might trap in an EH region. In that case,
2336 we just need the first SET. This can occur when simplifying a divmod
2337 insn. We *must* test for this case here because the code below that
2338 splits two independent SETs doesn't handle this case correctly when it
2339 updates the register status.
2341 It's pointless doing this if we originally had two sets, one from
2342 i3, and one from i2. Combining then splitting the parallel results
2343 in the original i2 again plus an invalid insn (which we delete).
2344 The net effect is only to move instructions around, which makes
2345 debug info less accurate.
2347 Also check the case where the first SET's destination is unused.
2348 That would not cause incorrect code, but does cause an unneeded
2351 if (insn_code_number < 0
2352 && !(added_sets_2 && i1 == 0)
2353 && GET_CODE (newpat) == PARALLEL
2354 && XVECLEN (newpat, 0) == 2
2355 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2356 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2357 && asm_noperands (newpat) < 0)
2359 rtx set0 = XVECEXP (newpat, 0, 0);
2360 rtx set1 = XVECEXP (newpat, 0, 1);
2363 if (((REG_P (SET_DEST (set1))
2364 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
2365 || (GET_CODE (SET_DEST (set1)) == SUBREG
2366 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
2367 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2368 || INTVAL (XEXP (note, 0)) <= 0)
2369 && ! side_effects_p (SET_SRC (set1)))
2372 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2375 else if (((REG_P (SET_DEST (set0))
2376 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
2377 || (GET_CODE (SET_DEST (set0)) == SUBREG
2378 && find_reg_note (i3, REG_UNUSED,
2379 SUBREG_REG (SET_DEST (set0)))))
2380 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2381 || INTVAL (XEXP (note, 0)) <= 0)
2382 && ! side_effects_p (SET_SRC (set0)))
2385 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2387 if (insn_code_number >= 0)
2389 /* If we will be able to accept this, we have made a
2390 change to the destination of I3. This requires us to
2391 do a few adjustments. */
2393 PATTERN (i3) = newpat;
2394 adjust_for_new_dest (i3);
2399 /* If we were combining three insns and the result is a simple SET
2400 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2401 insns. There are two ways to do this. It can be split using a
2402 machine-specific method (like when you have an addition of a large
2403 constant) or by combine in the function find_split_point. */
2405 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2406 && asm_noperands (newpat) < 0)
2408 rtx m_split, *split;
2409 rtx ni2dest = i2dest;
2411 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2412 use I2DEST as a scratch register will help. In the latter case,
2413 convert I2DEST to the mode of the source of NEWPAT if we can. */
2415 m_split = split_insns (newpat, i3);
2417 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2418 inputs of NEWPAT. */
2420 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2421 possible to try that as a scratch reg. This would require adding
2422 more code to make it work though. */
2424 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
2426 enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
2427 /* If I2DEST is a hard register or the only use of a pseudo,
2428 we can change its mode. */
2429 if (new_mode != GET_MODE (i2dest)
2430 && new_mode != VOIDmode
2431 && can_change_dest_mode (i2dest, added_sets_2, new_mode))
2432 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
2435 m_split = split_insns (gen_rtx_PARALLEL
2437 gen_rtvec (2, newpat,
2438 gen_rtx_CLOBBER (VOIDmode,
2441 /* If the split with the mode-changed register didn't work, try
2442 the original register. */
2443 if (! m_split && ni2dest != i2dest)
2446 m_split = split_insns (gen_rtx_PARALLEL
2448 gen_rtvec (2, newpat,
2449 gen_rtx_CLOBBER (VOIDmode,
2455 /* If recog_for_combine has discarded clobbers, try to use them
2456 again for the split. */
2457 if (m_split == 0 && newpat_vec_with_clobbers)
2459 = split_insns (gen_rtx_PARALLEL (VOIDmode,
2460 newpat_vec_with_clobbers), i3);
2462 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
2464 m_split = PATTERN (m_split);
2465 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2466 if (insn_code_number >= 0)
2469 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
2470 && (next_real_insn (i2) == i3
2471 || ! use_crosses_set_p (PATTERN (m_split), INSN_CUID (i2))))
2474 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
2475 newi2pat = PATTERN (m_split);
2477 i3set = single_set (NEXT_INSN (m_split));
2478 i2set = single_set (m_split);
2480 /* In case we changed the mode of I2DEST, replace it in the
2481 pseudo-register table here. We can't do it above in case this
2482 code doesn't get executed and we do a split the other way. */
2484 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2485 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
2487 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2489 /* If I2 or I3 has multiple SETs, we won't know how to track
2490 register status, so don't use these insns. If I2's destination
2491 is used between I2 and I3, we also can't use these insns. */
2493 if (i2_code_number >= 0 && i2set && i3set
2494 && (next_real_insn (i2) == i3
2495 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2496 insn_code_number = recog_for_combine (&newi3pat, i3,
2498 if (insn_code_number >= 0)
2501 /* It is possible that both insns now set the destination of I3.
2502 If so, we must show an extra use of it. */
2504 if (insn_code_number >= 0)
2506 rtx new_i3_dest = SET_DEST (i3set);
2507 rtx new_i2_dest = SET_DEST (i2set);
2509 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2510 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2511 || GET_CODE (new_i3_dest) == SUBREG)
2512 new_i3_dest = XEXP (new_i3_dest, 0);
2514 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2515 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2516 || GET_CODE (new_i2_dest) == SUBREG)
2517 new_i2_dest = XEXP (new_i2_dest, 0);
2519 if (REG_P (new_i3_dest)
2520 && REG_P (new_i2_dest)
2521 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2522 REG_N_SETS (REGNO (new_i2_dest))++;
2526 /* If we can split it and use I2DEST, go ahead and see if that
2527 helps things be recognized. Verify that none of the registers
2528 are set between I2 and I3. */
2529 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2533 /* We need I2DEST in the proper mode. If it is a hard register
2534 or the only use of a pseudo, we can change its mode.
2535 Make sure we don't change a hard register to have a mode that
2536 isn't valid for it, or change the number of registers. */
2537 && (GET_MODE (*split) == GET_MODE (i2dest)
2538 || GET_MODE (*split) == VOIDmode
2539 || can_change_dest_mode (i2dest, added_sets_2,
2541 && (next_real_insn (i2) == i3
2542 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2543 /* We can't overwrite I2DEST if its value is still used by
2545 && ! reg_referenced_p (i2dest, newpat))
2547 rtx newdest = i2dest;
2548 enum rtx_code split_code = GET_CODE (*split);
2549 enum machine_mode split_mode = GET_MODE (*split);
2551 /* Get NEWDEST as a register in the proper mode. We have already
2552 validated that we can do this. */
2553 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2555 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2557 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2558 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2561 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2562 an ASHIFT. This can occur if it was inside a PLUS and hence
2563 appeared to be a memory address. This is a kludge. */
2564 if (split_code == MULT
2565 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2566 && INTVAL (XEXP (*split, 1)) > 0
2567 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2569 SUBST (*split, gen_rtx_ASHIFT (split_mode,
2570 XEXP (*split, 0), GEN_INT (i)));
2571 /* Update split_code because we may not have a multiply
2573 split_code = GET_CODE (*split);
2576 #ifdef INSN_SCHEDULING
2577 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2578 be written as a ZERO_EXTEND. */
2579 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
2581 #ifdef LOAD_EXTEND_OP
2582 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2583 what it really is. */
2584 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
2586 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
2587 SUBREG_REG (*split)));
2590 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2591 SUBREG_REG (*split)));
2595 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2596 SUBST (*split, newdest);
2597 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2599 /* recog_for_combine might have added CLOBBERs to newi2pat.
2600 Make sure NEWPAT does not depend on the clobbered regs. */
2601 if (GET_CODE (newi2pat) == PARALLEL)
2602 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
2603 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
2605 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
2606 if (reg_overlap_mentioned_p (reg, newpat))
2613 /* If the split point was a MULT and we didn't have one before,
2614 don't use one now. */
2615 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2616 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2620 /* Check for a case where we loaded from memory in a narrow mode and
2621 then sign extended it, but we need both registers. In that case,
2622 we have a PARALLEL with both loads from the same memory location.
2623 We can split this into a load from memory followed by a register-register
2624 copy. This saves at least one insn, more if register allocation can
2627 We cannot do this if the destination of the first assignment is a
2628 condition code register or cc0. We eliminate this case by making sure
2629 the SET_DEST and SET_SRC have the same mode.
2631 We cannot do this if the destination of the second assignment is
2632 a register that we have already assumed is zero-extended. Similarly
2633 for a SUBREG of such a register. */
2635 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2636 && GET_CODE (newpat) == PARALLEL
2637 && XVECLEN (newpat, 0) == 2
2638 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2639 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2640 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
2641 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
2642 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2643 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2644 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2645 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2647 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2648 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2649 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2651 && reg_stat[REGNO (temp)].nonzero_bits != 0
2652 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2653 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2654 && (reg_stat[REGNO (temp)].nonzero_bits
2655 != GET_MODE_MASK (word_mode))))
2656 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2657 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2659 && reg_stat[REGNO (temp)].nonzero_bits != 0
2660 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2661 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2662 && (reg_stat[REGNO (temp)].nonzero_bits
2663 != GET_MODE_MASK (word_mode)))))
2664 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2665 SET_SRC (XVECEXP (newpat, 0, 1)))
2666 && ! find_reg_note (i3, REG_UNUSED,
2667 SET_DEST (XVECEXP (newpat, 0, 0))))
2671 newi2pat = XVECEXP (newpat, 0, 0);
2672 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2673 newpat = XVECEXP (newpat, 0, 1);
2674 SUBST (SET_SRC (newpat),
2675 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
2676 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2678 if (i2_code_number >= 0)
2679 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2681 if (insn_code_number >= 0)
2685 /* Similarly, check for a case where we have a PARALLEL of two independent
2686 SETs but we started with three insns. In this case, we can do the sets
2687 as two separate insns. This case occurs when some SET allows two
2688 other insns to combine, but the destination of that SET is still live. */
2690 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2691 && GET_CODE (newpat) == PARALLEL
2692 && XVECLEN (newpat, 0) == 2
2693 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2694 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2695 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2696 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2697 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2698 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2699 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2701 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2702 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2703 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2704 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2705 XVECEXP (newpat, 0, 0))
2706 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2707 XVECEXP (newpat, 0, 1))
2708 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2709 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2711 /* Normally, it doesn't matter which of the two is done first,
2712 but it does if one references cc0. In that case, it has to
2715 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2717 newi2pat = XVECEXP (newpat, 0, 0);
2718 newpat = XVECEXP (newpat, 0, 1);
2723 newi2pat = XVECEXP (newpat, 0, 1);
2724 newpat = XVECEXP (newpat, 0, 0);
2727 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2729 if (i2_code_number >= 0)
2730 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2733 /* If it still isn't recognized, fail and change things back the way they
2735 if ((insn_code_number < 0
2736 /* Is the result a reasonable ASM_OPERANDS? */
2737 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2743 /* If we had to change another insn, make sure it is valid also. */
2744 if (undobuf.other_insn)
2746 rtx other_pat = PATTERN (undobuf.other_insn);
2747 rtx new_other_notes;
2750 CLEAR_HARD_REG_SET (newpat_used_regs);
2752 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2755 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2761 PATTERN (undobuf.other_insn) = other_pat;
2763 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2764 are still valid. Then add any non-duplicate notes added by
2765 recog_for_combine. */
2766 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2768 next = XEXP (note, 1);
2770 if (REG_NOTE_KIND (note) == REG_UNUSED
2771 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2773 if (REG_P (XEXP (note, 0)))
2774 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2776 remove_note (undobuf.other_insn, note);
2780 for (note = new_other_notes; note; note = XEXP (note, 1))
2781 if (REG_P (XEXP (note, 0)))
2782 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2784 distribute_notes (new_other_notes, undobuf.other_insn,
2785 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2788 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
2789 they are adjacent to each other or not. */
2791 rtx p = prev_nonnote_insn (i3);
2792 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
2793 && sets_cc0_p (newi2pat))
2801 /* Only allow this combination if insn_rtx_costs reports that the
2802 replacement instructions are cheaper than the originals. */
2803 if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat))
2809 /* We now know that we can do this combination. Merge the insns and
2810 update the status of registers and LOG_LINKS. */
2818 /* I3 now uses what used to be its destination and which is now
2819 I2's destination. This requires us to do a few adjustments. */
2820 PATTERN (i3) = newpat;
2821 adjust_for_new_dest (i3);
2823 /* We need a LOG_LINK from I3 to I2. But we used to have one,
2826 However, some later insn might be using I2's dest and have
2827 a LOG_LINK pointing at I3. We must remove this link.
2828 The simplest way to remove the link is to point it at I1,
2829 which we know will be a NOTE. */
2831 /* newi2pat is usually a SET here; however, recog_for_combine might
2832 have added some clobbers. */
2833 if (GET_CODE (newi2pat) == PARALLEL)
2834 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
2836 ni2dest = SET_DEST (newi2pat);
2838 for (insn = NEXT_INSN (i3);
2839 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2840 || insn != BB_HEAD (this_basic_block->next_bb));
2841 insn = NEXT_INSN (insn))
2843 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
2845 for (link = LOG_LINKS (insn); link;
2846 link = XEXP (link, 1))
2847 if (XEXP (link, 0) == i3)
2848 XEXP (link, 0) = i1;
2856 rtx i3notes, i2notes, i1notes = 0;
2857 rtx i3links, i2links, i1links = 0;
2860 /* Compute which registers we expect to eliminate. newi2pat may be setting
2861 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2862 same as i3dest, in which case newi2pat may be setting i1dest. */
2863 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
2864 || i2dest_in_i2src || i2dest_in_i1src
2867 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
2868 || (newi2pat && reg_set_p (i1dest, newi2pat))
2872 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2874 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2875 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2877 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2879 /* Ensure that we do not have something that should not be shared but
2880 occurs multiple times in the new insns. Check this by first
2881 resetting all the `used' flags and then copying anything is shared. */
2883 reset_used_flags (i3notes);
2884 reset_used_flags (i2notes);
2885 reset_used_flags (i1notes);
2886 reset_used_flags (newpat);
2887 reset_used_flags (newi2pat);
2888 if (undobuf.other_insn)
2889 reset_used_flags (PATTERN (undobuf.other_insn));
2891 i3notes = copy_rtx_if_shared (i3notes);
2892 i2notes = copy_rtx_if_shared (i2notes);
2893 i1notes = copy_rtx_if_shared (i1notes);
2894 newpat = copy_rtx_if_shared (newpat);
2895 newi2pat = copy_rtx_if_shared (newi2pat);
2896 if (undobuf.other_insn)
2897 reset_used_flags (PATTERN (undobuf.other_insn));
2899 INSN_CODE (i3) = insn_code_number;
2900 PATTERN (i3) = newpat;
2902 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
2904 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
2906 reset_used_flags (call_usage);
2907 call_usage = copy_rtx (call_usage);
2910 replace_rtx (call_usage, i2dest, i2src);
2913 replace_rtx (call_usage, i1dest, i1src);
2915 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
2918 if (undobuf.other_insn)
2919 INSN_CODE (undobuf.other_insn) = other_code_number;
2921 /* We had one special case above where I2 had more than one set and
2922 we replaced a destination of one of those sets with the destination
2923 of I3. In that case, we have to update LOG_LINKS of insns later
2924 in this basic block. Note that this (expensive) case is rare.
2926 Also, in this case, we must pretend that all REG_NOTEs for I2
2927 actually came from I3, so that REG_UNUSED notes from I2 will be
2928 properly handled. */
2930 if (i3_subst_into_i2)
2932 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2933 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE
2934 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
2935 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2936 && ! find_reg_note (i2, REG_UNUSED,
2937 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2938 for (temp = NEXT_INSN (i2);
2939 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2940 || BB_HEAD (this_basic_block) != temp);
2941 temp = NEXT_INSN (temp))
2942 if (temp != i3 && INSN_P (temp))
2943 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2944 if (XEXP (link, 0) == i2)
2945 XEXP (link, 0) = i3;
2950 while (XEXP (link, 1))
2951 link = XEXP (link, 1);
2952 XEXP (link, 1) = i2notes;
2966 INSN_CODE (i2) = i2_code_number;
2967 PATTERN (i2) = newi2pat;
2970 SET_INSN_DELETED (i2);
2976 SET_INSN_DELETED (i1);
2979 /* Get death notes for everything that is now used in either I3 or
2980 I2 and used to die in a previous insn. If we built two new
2981 patterns, move from I1 to I2 then I2 to I3 so that we get the
2982 proper movement on registers that I2 modifies. */
2986 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2987 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2990 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2993 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2995 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2998 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
3001 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
3004 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3007 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
3008 know these are REG_UNUSED and want them to go to the desired insn,
3009 so we always pass it as i3. We have not counted the notes in
3010 reg_n_deaths yet, so we need to do so now. */
3012 if (newi2pat && new_i2_notes)
3014 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
3015 if (REG_P (XEXP (temp, 0)))
3016 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
3018 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3023 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
3024 if (REG_P (XEXP (temp, 0)))
3025 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
3027 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
3030 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
3031 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
3032 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
3033 in that case, it might delete I2. Similarly for I2 and I1.
3034 Show an additional death due to the REG_DEAD note we make here. If
3035 we discard it in distribute_notes, we will decrement it again. */
3039 if (REG_P (i3dest_killed))
3040 REG_N_DEATHS (REGNO (i3dest_killed))++;
3042 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
3043 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3045 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
3047 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3049 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3053 if (i2dest_in_i2src)
3056 REG_N_DEATHS (REGNO (i2dest))++;
3058 if (newi2pat && reg_set_p (i2dest, newi2pat))
3059 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3060 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3062 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3063 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3064 NULL_RTX, NULL_RTX);
3067 if (i1dest_in_i1src)
3070 REG_N_DEATHS (REGNO (i1dest))++;
3072 if (newi2pat && reg_set_p (i1dest, newi2pat))
3073 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3074 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3076 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3077 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3078 NULL_RTX, NULL_RTX);
3081 distribute_links (i3links);
3082 distribute_links (i2links);
3083 distribute_links (i1links);
3088 rtx i2_insn = 0, i2_val = 0, set;
3090 /* The insn that used to set this register doesn't exist, and
3091 this life of the register may not exist either. See if one of
3092 I3's links points to an insn that sets I2DEST. If it does,
3093 that is now the last known value for I2DEST. If we don't update
3094 this and I2 set the register to a value that depended on its old
3095 contents, we will get confused. If this insn is used, thing
3096 will be set correctly in combine_instructions. */
3098 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3099 if ((set = single_set (XEXP (link, 0))) != 0
3100 && rtx_equal_p (i2dest, SET_DEST (set)))
3101 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
3103 record_value_for_reg (i2dest, i2_insn, i2_val);
3105 /* If the reg formerly set in I2 died only once and that was in I3,
3106 zero its use count so it won't make `reload' do any work. */
3108 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
3109 && ! i2dest_in_i2src)
3111 regno = REGNO (i2dest);
3112 REG_N_SETS (regno)--;
3116 if (i1 && REG_P (i1dest))
3119 rtx i1_insn = 0, i1_val = 0, set;
3121 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3122 if ((set = single_set (XEXP (link, 0))) != 0
3123 && rtx_equal_p (i1dest, SET_DEST (set)))
3124 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
3126 record_value_for_reg (i1dest, i1_insn, i1_val);
3128 regno = REGNO (i1dest);
3129 if (! added_sets_1 && ! i1dest_in_i1src)
3130 REG_N_SETS (regno)--;
3133 /* Update reg_stat[].nonzero_bits et al for any changes that may have
3134 been made to this insn. The order of
3135 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
3136 can affect nonzero_bits of newpat */
3138 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
3139 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
3141 /* Set new_direct_jump_p if a new return or simple jump instruction
3144 If I3 is now an unconditional jump, ensure that it has a
3145 BARRIER following it since it may have initially been a
3146 conditional jump. It may also be the last nonnote insn. */
3148 if (returnjump_p (i3) || any_uncondjump_p (i3))
3150 *new_direct_jump_p = 1;
3151 mark_jump_label (PATTERN (i3), i3, 0);
3153 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
3154 || !BARRIER_P (temp))
3155 emit_barrier_after (i3);
3158 if (undobuf.other_insn != NULL_RTX
3159 && (returnjump_p (undobuf.other_insn)
3160 || any_uncondjump_p (undobuf.other_insn)))
3162 *new_direct_jump_p = 1;
3164 if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX
3165 || !BARRIER_P (temp))
3166 emit_barrier_after (undobuf.other_insn);
3169 /* An NOOP jump does not need barrier, but it does need cleaning up
3171 if (GET_CODE (newpat) == SET
3172 && SET_SRC (newpat) == pc_rtx
3173 && SET_DEST (newpat) == pc_rtx)
3174 *new_direct_jump_p = 1;
3177 combine_successes++;
3180 if (added_links_insn
3181 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
3182 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
3183 return added_links_insn;
3185 return newi2pat ? i2 : i3;
3188 /* Undo all the modifications recorded in undobuf. */
3193 struct undo *undo, *next;
3195 for (undo = undobuf.undos; undo; undo = next)
3199 *undo->where.i = undo->old_contents.i;
3201 *undo->where.r = undo->old_contents.r;
3203 undo->next = undobuf.frees;
3204 undobuf.frees = undo;
3210 /* We've committed to accepting the changes we made. Move all
3211 of the undos to the free list. */
3216 struct undo *undo, *next;
3218 for (undo = undobuf.undos; undo; undo = next)
3221 undo->next = undobuf.frees;
3222 undobuf.frees = undo;
3228 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
3229 where we have an arithmetic expression and return that point. LOC will
3232 try_combine will call this function to see if an insn can be split into
3236 find_split_point (rtx *loc, rtx insn)
3239 enum rtx_code code = GET_CODE (x);
3241 unsigned HOST_WIDE_INT len = 0;
3242 HOST_WIDE_INT pos = 0;
3244 rtx inner = NULL_RTX;
3246 /* First special-case some codes. */
3250 #ifdef INSN_SCHEDULING
3251 /* If we are making a paradoxical SUBREG invalid, it becomes a split
3253 if (MEM_P (SUBREG_REG (x)))
3256 return find_split_point (&SUBREG_REG (x), insn);
3260 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3261 using LO_SUM and HIGH. */
3262 if (GET_CODE (XEXP (x, 0)) == CONST
3263 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
3266 gen_rtx_LO_SUM (Pmode,
3267 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
3269 return &XEXP (XEXP (x, 0), 0);
3273 /* If we have a PLUS whose second operand is a constant and the
3274 address is not valid, perhaps will can split it up using
3275 the machine-specific way to split large constants. We use
3276 the first pseudo-reg (one of the virtual regs) as a placeholder;
3277 it will not remain in the result. */
3278 if (GET_CODE (XEXP (x, 0)) == PLUS
3279 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3280 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
3282 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
3283 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
3286 /* This should have produced two insns, each of which sets our
3287 placeholder. If the source of the second is a valid address,
3288 we can make put both sources together and make a split point
3292 && NEXT_INSN (seq) != NULL_RTX
3293 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
3294 && NONJUMP_INSN_P (seq)
3295 && GET_CODE (PATTERN (seq)) == SET
3296 && SET_DEST (PATTERN (seq)) == reg
3297 && ! reg_mentioned_p (reg,
3298 SET_SRC (PATTERN (seq)))
3299 && NONJUMP_INSN_P (NEXT_INSN (seq))
3300 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
3301 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
3302 && memory_address_p (GET_MODE (x),
3303 SET_SRC (PATTERN (NEXT_INSN (seq)))))
3305 rtx src1 = SET_SRC (PATTERN (seq));
3306 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
3308 /* Replace the placeholder in SRC2 with SRC1. If we can
3309 find where in SRC2 it was placed, that can become our
3310 split point and we can replace this address with SRC2.
3311 Just try two obvious places. */
3313 src2 = replace_rtx (src2, reg, src1);
3315 if (XEXP (src2, 0) == src1)
3316 split = &XEXP (src2, 0);
3317 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
3318 && XEXP (XEXP (src2, 0), 0) == src1)
3319 split = &XEXP (XEXP (src2, 0), 0);
3323 SUBST (XEXP (x, 0), src2);
3328 /* If that didn't work, perhaps the first operand is complex and
3329 needs to be computed separately, so make a split point there.
3330 This will occur on machines that just support REG + CONST
3331 and have a constant moved through some previous computation. */
3333 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
3334 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3335 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
3336 return &XEXP (XEXP (x, 0), 0);
3342 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3343 ZERO_EXTRACT, the most likely reason why this doesn't match is that
3344 we need to put the operand into a register. So split at that
3347 if (SET_DEST (x) == cc0_rtx
3348 && GET_CODE (SET_SRC (x)) != COMPARE
3349 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
3350 && !OBJECT_P (SET_SRC (x))
3351 && ! (GET_CODE (SET_SRC (x)) == SUBREG
3352 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
3353 return &SET_SRC (x);
3356 /* See if we can split SET_SRC as it stands. */
3357 split = find_split_point (&SET_SRC (x), insn);
3358 if (split && split != &SET_SRC (x))
3361 /* See if we can split SET_DEST as it stands. */
3362 split = find_split_point (&SET_DEST (x), insn);
3363 if (split && split != &SET_DEST (x))
3366 /* See if this is a bitfield assignment with everything constant. If
3367 so, this is an IOR of an AND, so split it into that. */
3368 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3369 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
3370 <= HOST_BITS_PER_WIDE_INT)
3371 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
3372 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
3373 && GET_CODE (SET_SRC (x)) == CONST_INT
3374 && ((INTVAL (XEXP (SET_DEST (x), 1))
3375 + INTVAL (XEXP (SET_DEST (x), 2)))
3376 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
3377 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
3379 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
3380 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
3381 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
3382 rtx dest = XEXP (SET_DEST (x), 0);
3383 enum machine_mode mode = GET_MODE (dest);
3384 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3387 if (BITS_BIG_ENDIAN)
3388 pos = GET_MODE_BITSIZE (mode) - len - pos;
3390 or_mask = gen_int_mode (src << pos, mode);
3393 simplify_gen_binary (IOR, mode, dest, or_mask));
3396 rtx negmask = gen_int_mode (~(mask << pos), mode);
3398 simplify_gen_binary (IOR, mode,
3399 simplify_gen_binary (AND, mode,
3404 SUBST (SET_DEST (x), dest);
3406 split = find_split_point (&SET_SRC (x), insn);
3407 if (split && split != &SET_SRC (x))
3411 /* Otherwise, see if this is an operation that we can split into two.
3412 If so, try to split that. */
3413 code = GET_CODE (SET_SRC (x));
3418 /* If we are AND'ing with a large constant that is only a single
3419 bit and the result is only being used in a context where we
3420 need to know if it is zero or nonzero, replace it with a bit
3421 extraction. This will avoid the large constant, which might
3422 have taken more than one insn to make. If the constant were
3423 not a valid argument to the AND but took only one insn to make,
3424 this is no worse, but if it took more than one insn, it will
3427 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3428 && REG_P (XEXP (SET_SRC (x), 0))
3429 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3430 && REG_P (SET_DEST (x))
3431 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
3432 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3433 && XEXP (*split, 0) == SET_DEST (x)
3434 && XEXP (*split, 1) == const0_rtx)
3436 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3437 XEXP (SET_SRC (x), 0),
3438 pos, NULL_RTX, 1, 1, 0, 0);
3439 if (extraction != 0)
3441 SUBST (SET_SRC (x), extraction);
3442 return find_split_point (loc, insn);
3448 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3449 is known to be on, this can be converted into a NEG of a shift. */
3450 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3451 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3452 && 1 <= (pos = exact_log2
3453 (nonzero_bits (XEXP (SET_SRC (x), 0),
3454 GET_MODE (XEXP (SET_SRC (x), 0))))))
3456 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3460 gen_rtx_LSHIFTRT (mode,
3461 XEXP (SET_SRC (x), 0),
3464 split = find_split_point (&SET_SRC (x), insn);
3465 if (split && split != &SET_SRC (x))
3471 inner = XEXP (SET_SRC (x), 0);
3473 /* We can't optimize if either mode is a partial integer
3474 mode as we don't know how many bits are significant
3476 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3477 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3481 len = GET_MODE_BITSIZE (GET_MODE (inner));
3487 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3488 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3490 inner = XEXP (SET_SRC (x), 0);
3491 len = INTVAL (XEXP (SET_SRC (x), 1));
3492 pos = INTVAL (XEXP (SET_SRC (x), 2));
3494 if (BITS_BIG_ENDIAN)
3495 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3496 unsignedp = (code == ZERO_EXTRACT);
3504 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3506 enum machine_mode mode = GET_MODE (SET_SRC (x));
3508 /* For unsigned, we have a choice of a shift followed by an
3509 AND or two shifts. Use two shifts for field sizes where the
3510 constant might be too large. We assume here that we can
3511 always at least get 8-bit constants in an AND insn, which is
3512 true for every current RISC. */
3514 if (unsignedp && len <= 8)
3519 (mode, gen_lowpart (mode, inner),
3521 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3523 split = find_split_point (&SET_SRC (x), insn);
3524 if (split && split != &SET_SRC (x))
3531 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3532 gen_rtx_ASHIFT (mode,
3533 gen_lowpart (mode, inner),
3534 GEN_INT (GET_MODE_BITSIZE (mode)
3536 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3538 split = find_split_point (&SET_SRC (x), insn);
3539 if (split && split != &SET_SRC (x))
3544 /* See if this is a simple operation with a constant as the second
3545 operand. It might be that this constant is out of range and hence
3546 could be used as a split point. */
3547 if (BINARY_P (SET_SRC (x))
3548 && CONSTANT_P (XEXP (SET_SRC (x), 1))
3549 && (OBJECT_P (XEXP (SET_SRC (x), 0))
3550 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3551 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
3552 return &XEXP (SET_SRC (x), 1);
3554 /* Finally, see if this is a simple operation with its first operand
3555 not in a register. The operation might require this operand in a
3556 register, so return it as a split point. We can always do this
3557 because if the first operand were another operation, we would have
3558 already found it as a split point. */
3559 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
3560 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3561 return &XEXP (SET_SRC (x), 0);
3567 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3568 it is better to write this as (not (ior A B)) so we can split it.
3569 Similarly for IOR. */
3570 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3573 gen_rtx_NOT (GET_MODE (x),
3574 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3576 XEXP (XEXP (x, 0), 0),
3577 XEXP (XEXP (x, 1), 0))));
3578 return find_split_point (loc, insn);
3581 /* Many RISC machines have a large set of logical insns. If the
3582 second operand is a NOT, put it first so we will try to split the
3583 other operand first. */
3584 if (GET_CODE (XEXP (x, 1)) == NOT)
3586 rtx tem = XEXP (x, 0);
3587 SUBST (XEXP (x, 0), XEXP (x, 1));
3588 SUBST (XEXP (x, 1), tem);
3596 /* Otherwise, select our actions depending on our rtx class. */
3597 switch (GET_RTX_CLASS (code))
3599 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3601 split = find_split_point (&XEXP (x, 2), insn);
3604 /* ... fall through ... */
3606 case RTX_COMM_ARITH:
3608 case RTX_COMM_COMPARE:
3609 split = find_split_point (&XEXP (x, 1), insn);
3612 /* ... fall through ... */
3614 /* Some machines have (and (shift ...) ...) insns. If X is not
3615 an AND, but XEXP (X, 0) is, use it as our split point. */
3616 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3617 return &XEXP (x, 0);
3619 split = find_split_point (&XEXP (x, 0), insn);
3625 /* Otherwise, we don't have a split point. */
3630 /* Throughout X, replace FROM with TO, and return the result.
3631 The result is TO if X is FROM;
3632 otherwise the result is X, but its contents may have been modified.
3633 If they were modified, a record was made in undobuf so that
3634 undo_all will (among other things) return X to its original state.
3636 If the number of changes necessary is too much to record to undo,
3637 the excess changes are not made, so the result is invalid.
3638 The changes already made can still be undone.
3639 undobuf.num_undo is incremented for such changes, so by testing that
3640 the caller can tell whether the result is valid.
3642 `n_occurrences' is incremented each time FROM is replaced.
3644 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3646 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3647 by copying if `n_occurrences' is nonzero. */
3650 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
3652 enum rtx_code code = GET_CODE (x);
3653 enum machine_mode op0_mode = VOIDmode;
3658 /* Two expressions are equal if they are identical copies of a shared
3659 RTX or if they are both registers with the same register number
3662 #define COMBINE_RTX_EQUAL_P(X,Y) \
3664 || (REG_P (X) && REG_P (Y) \
3665 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3667 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3670 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3673 /* If X and FROM are the same register but different modes, they will
3674 not have been seen as equal above. However, flow.c will make a
3675 LOG_LINKS entry for that case. If we do nothing, we will try to
3676 rerecognize our original insn and, when it succeeds, we will
3677 delete the feeding insn, which is incorrect.
3679 So force this insn not to match in this (rare) case. */
3680 if (! in_dest && code == REG && REG_P (from)
3681 && REGNO (x) == REGNO (from))
3682 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3684 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3685 of which may contain things that can be combined. */
3686 if (code != MEM && code != LO_SUM && OBJECT_P (x))
3689 /* It is possible to have a subexpression appear twice in the insn.
3690 Suppose that FROM is a register that appears within TO.
3691 Then, after that subexpression has been scanned once by `subst',
3692 the second time it is scanned, TO may be found. If we were
3693 to scan TO here, we would find FROM within it and create a
3694 self-referent rtl structure which is completely wrong. */
3695 if (COMBINE_RTX_EQUAL_P (x, to))
3698 /* Parallel asm_operands need special attention because all of the
3699 inputs are shared across the arms. Furthermore, unsharing the
3700 rtl results in recognition failures. Failure to handle this case
3701 specially can result in circular rtl.
3703 Solve this by doing a normal pass across the first entry of the
3704 parallel, and only processing the SET_DESTs of the subsequent
3707 if (code == PARALLEL
3708 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3709 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3711 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3713 /* If this substitution failed, this whole thing fails. */
3714 if (GET_CODE (new) == CLOBBER
3715 && XEXP (new, 0) == const0_rtx)
3718 SUBST (XVECEXP (x, 0, 0), new);
3720 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3722 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3725 && GET_CODE (dest) != CC0
3726 && GET_CODE (dest) != PC)
3728 new = subst (dest, from, to, 0, unique_copy);
3730 /* If this substitution failed, this whole thing fails. */
3731 if (GET_CODE (new) == CLOBBER
3732 && XEXP (new, 0) == const0_rtx)
3735 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3741 len = GET_RTX_LENGTH (code);
3742 fmt = GET_RTX_FORMAT (code);
3744 /* We don't need to process a SET_DEST that is a register, CC0,
3745 or PC, so set up to skip this common case. All other cases
3746 where we want to suppress replacing something inside a
3747 SET_SRC are handled via the IN_DEST operand. */
3749 && (REG_P (SET_DEST (x))
3750 || GET_CODE (SET_DEST (x)) == CC0
3751 || GET_CODE (SET_DEST (x)) == PC))
3754 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3757 op0_mode = GET_MODE (XEXP (x, 0));
3759 for (i = 0; i < len; i++)
3764 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3766 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3768 new = (unique_copy && n_occurrences
3769 ? copy_rtx (to) : to);
3774 new = subst (XVECEXP (x, i, j), from, to, 0,
3777 /* If this substitution failed, this whole thing
3779 if (GET_CODE (new) == CLOBBER
3780 && XEXP (new, 0) == const0_rtx)
3784 SUBST (XVECEXP (x, i, j), new);
3787 else if (fmt[i] == 'e')
3789 /* If this is a register being set, ignore it. */
3793 && (((code == SUBREG || code == ZERO_EXTRACT)
3795 || code == STRICT_LOW_PART))
3798 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3800 /* In general, don't install a subreg involving two
3801 modes not tieable. It can worsen register
3802 allocation, and can even make invalid reload
3803 insns, since the reg inside may need to be copied
3804 from in the outside mode, and that may be invalid
3805 if it is an fp reg copied in integer mode.
3807 We allow two exceptions to this: It is valid if
3808 it is inside another SUBREG and the mode of that
3809 SUBREG and the mode of the inside of TO is
3810 tieable and it is valid if X is a SET that copies
3813 if (GET_CODE (to) == SUBREG
3814 && ! MODES_TIEABLE_P (GET_MODE (to),
3815 GET_MODE (SUBREG_REG (to)))
3816 && ! (code == SUBREG
3817 && MODES_TIEABLE_P (GET_MODE (x),
3818 GET_MODE (SUBREG_REG (to))))
3820 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3823 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3825 #ifdef CANNOT_CHANGE_MODE_CLASS
3828 && REGNO (to) < FIRST_PSEUDO_REGISTER
3829 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
3832 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3835 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3839 /* If we are in a SET_DEST, suppress most cases unless we
3840 have gone inside a MEM, in which case we want to
3841 simplify the address. We assume here that things that
3842 are actually part of the destination have their inner
3843 parts in the first expression. This is true for SUBREG,
3844 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3845 things aside from REG and MEM that should appear in a
3847 new = subst (XEXP (x, i), from, to,
3849 && (code == SUBREG || code == STRICT_LOW_PART
3850 || code == ZERO_EXTRACT))
3852 && i == 0), unique_copy);
3854 /* If we found that we will have to reject this combination,
3855 indicate that by returning the CLOBBER ourselves, rather than
3856 an expression containing it. This will speed things up as
3857 well as prevent accidents where two CLOBBERs are considered
3858 to be equal, thus producing an incorrect simplification. */
3860 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3863 if (GET_CODE (x) == SUBREG
3864 && (GET_CODE (new) == CONST_INT
3865 || GET_CODE (new) == CONST_DOUBLE))
3867 enum machine_mode mode = GET_MODE (x);
3869 x = simplify_subreg (GET_MODE (x), new,
3870 GET_MODE (SUBREG_REG (x)),
3873 x = gen_rtx_CLOBBER (mode, const0_rtx);
3875 else if (GET_CODE (new) == CONST_INT
3876 && GET_CODE (x) == ZERO_EXTEND)
3878 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
3879 new, GET_MODE (XEXP (x, 0)));
3883 SUBST (XEXP (x, i), new);
3888 /* Try to simplify X. If the simplification changed the code, it is likely
3889 that further simplification will help, so loop, but limit the number
3890 of repetitions that will be performed. */
3892 for (i = 0; i < 4; i++)
3894 /* If X is sufficiently simple, don't bother trying to do anything
3896 if (code != CONST_INT && code != REG && code != CLOBBER)
3897 x = combine_simplify_rtx (x, op0_mode, in_dest);
3899 if (GET_CODE (x) == code)
3902 code = GET_CODE (x);
3904 /* We no longer know the original mode of operand 0 since we
3905 have changed the form of X) */
3906 op0_mode = VOIDmode;
3912 /* Simplify X, a piece of RTL. We just operate on the expression at the
3913 outer level; call `subst' to simplify recursively. Return the new
3916 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
3917 if we are inside a SET_DEST. */
3920 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
3922 enum rtx_code code = GET_CODE (x);
3923 enum machine_mode mode = GET_MODE (x);
3928 /* If this is a commutative operation, put a constant last and a complex
3929 expression first. We don't need to do this for comparisons here. */
3930 if (COMMUTATIVE_ARITH_P (x)
3931 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
3934 SUBST (XEXP (x, 0), XEXP (x, 1));
3935 SUBST (XEXP (x, 1), temp);
3938 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3939 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3940 things. Check for cases where both arms are testing the same
3943 Don't do anything if all operands are very simple. */
3946 && ((!OBJECT_P (XEXP (x, 0))
3947 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3948 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
3949 || (!OBJECT_P (XEXP (x, 1))
3950 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3951 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
3953 && (!OBJECT_P (XEXP (x, 0))
3954 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3955 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
3957 rtx cond, true_rtx, false_rtx;
3959 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
3961 /* If everything is a comparison, what we have is highly unlikely
3962 to be simpler, so don't use it. */
3963 && ! (COMPARISON_P (x)
3964 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
3966 rtx cop1 = const0_rtx;
3967 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3969 if (cond_code == NE && COMPARISON_P (cond))
3972 /* Simplify the alternative arms; this may collapse the true and
3973 false arms to store-flag values. Be careful to use copy_rtx
3974 here since true_rtx or false_rtx might share RTL with x as a
3975 result of the if_then_else_cond call above. */
3976 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
3977 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
3979 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3980 is unlikely to be simpler. */
3981 if (general_operand (true_rtx, VOIDmode)
3982 && general_operand (false_rtx, VOIDmode))
3984 enum rtx_code reversed;
3986 /* Restarting if we generate a store-flag expression will cause
3987 us to loop. Just drop through in this case. */
3989 /* If the result values are STORE_FLAG_VALUE and zero, we can
3990 just make the comparison operation. */
3991 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
3992 x = simplify_gen_relational (cond_code, mode, VOIDmode,
3994 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
3995 && ((reversed = reversed_comparison_code_parts
3996 (cond_code, cond, cop1, NULL))
3998 x = simplify_gen_relational (reversed, mode, VOIDmode,
4001 /* Likewise, we can make the negate of a comparison operation
4002 if the result values are - STORE_FLAG_VALUE and zero. */
4003 else if (GET_CODE (true_rtx) == CONST_INT
4004 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
4005 && false_rtx == const0_rtx)
4006 x = simplify_gen_unary (NEG, mode,
4007 simplify_gen_relational (cond_code,
4011 else if (GET_CODE (false_rtx) == CONST_INT
4012 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
4013 && true_rtx == const0_rtx
4014 && ((reversed = reversed_comparison_code_parts
4015 (cond_code, cond, cop1, NULL))
4017 x = simplify_gen_unary (NEG, mode,
4018 simplify_gen_relational (reversed,
4023 return gen_rtx_IF_THEN_ELSE (mode,
4024 simplify_gen_relational (cond_code,
4029 true_rtx, false_rtx);
4031 code = GET_CODE (x);
4032 op0_mode = VOIDmode;
4037 /* Try to fold this expression in case we have constants that weren't
4040 switch (GET_RTX_CLASS (code))
4043 if (op0_mode == VOIDmode)
4044 op0_mode = GET_MODE (XEXP (x, 0));
4045 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
4048 case RTX_COMM_COMPARE:
4050 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
4051 if (cmp_mode == VOIDmode)
4053 cmp_mode = GET_MODE (XEXP (x, 1));
4054 if (cmp_mode == VOIDmode)
4055 cmp_mode = op0_mode;
4057 temp = simplify_relational_operation (code, mode, cmp_mode,
4058 XEXP (x, 0), XEXP (x, 1));
4061 case RTX_COMM_ARITH:
4063 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
4065 case RTX_BITFIELD_OPS:
4067 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
4068 XEXP (x, 1), XEXP (x, 2));
4077 code = GET_CODE (temp);
4078 op0_mode = VOIDmode;
4079 mode = GET_MODE (temp);
4082 /* First see if we can apply the inverse distributive law. */
4083 if (code == PLUS || code == MINUS
4084 || code == AND || code == IOR || code == XOR)
4086 x = apply_distributive_law (x);
4087 code = GET_CODE (x);
4088 op0_mode = VOIDmode;
4091 /* If CODE is an associative operation not otherwise handled, see if we
4092 can associate some operands. This can win if they are constants or
4093 if they are logically related (i.e. (a & b) & a). */
4094 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
4095 || code == AND || code == IOR || code == XOR
4096 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
4097 && ((INTEGRAL_MODE_P (mode) && code != DIV)
4098 || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
4100 if (GET_CODE (XEXP (x, 0)) == code)
4102 rtx other = XEXP (XEXP (x, 0), 0);
4103 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
4104 rtx inner_op1 = XEXP (x, 1);
4107 /* Make sure we pass the constant operand if any as the second
4108 one if this is a commutative operation. */
4109 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
4111 rtx tem = inner_op0;
4112 inner_op0 = inner_op1;
4115 inner = simplify_binary_operation (code == MINUS ? PLUS
4116 : code == DIV ? MULT
4118 mode, inner_op0, inner_op1);
4120 /* For commutative operations, try the other pair if that one
4122 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
4124 other = XEXP (XEXP (x, 0), 1);
4125 inner = simplify_binary_operation (code, mode,
4126 XEXP (XEXP (x, 0), 0),
4131 return simplify_gen_binary (code, mode, other, inner);
4135 /* A little bit of algebraic simplification here. */
4139 /* Ensure that our address has any ASHIFTs converted to MULT in case
4140 address-recognizing predicates are called later. */
4141 temp = make_compound_operation (XEXP (x, 0), MEM);
4142 SUBST (XEXP (x, 0), temp);
4146 if (op0_mode == VOIDmode)
4147 op0_mode = GET_MODE (SUBREG_REG (x));
4149 /* See if this can be moved to simplify_subreg. */
4150 if (CONSTANT_P (SUBREG_REG (x))
4151 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
4152 /* Don't call gen_lowpart if the inner mode
4153 is VOIDmode and we cannot simplify it, as SUBREG without
4154 inner mode is invalid. */
4155 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
4156 || gen_lowpart_common (mode, SUBREG_REG (x))))
4157 return gen_lowpart (mode, SUBREG_REG (x));
4159 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
4163 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
4169 /* Don't change the mode of the MEM if that would change the meaning
4171 if (MEM_P (SUBREG_REG (x))
4172 && (MEM_VOLATILE_P (SUBREG_REG (x))
4173 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
4174 return gen_rtx_CLOBBER (mode, const0_rtx);
4176 /* Note that we cannot do any narrowing for non-constants since
4177 we might have been counting on using the fact that some bits were
4178 zero. We now do this in the SET. */
4183 if (GET_CODE (XEXP (x, 0)) == SUBREG
4184 && subreg_lowpart_p (XEXP (x, 0))
4185 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
4186 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
4187 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
4188 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
4190 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
4192 x = gen_rtx_ROTATE (inner_mode,
4193 simplify_gen_unary (NOT, inner_mode, const1_rtx,
4195 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
4196 return gen_lowpart (mode, x);
4199 /* Apply De Morgan's laws to reduce number of patterns for machines
4200 with negating logical insns (and-not, nand, etc.). If result has
4201 only one NOT, put it first, since that is how the patterns are
4204 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
4206 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
4207 enum machine_mode op_mode;
4209 op_mode = GET_MODE (in1);
4210 in1 = simplify_gen_unary (NOT, op_mode, in1, op_mode);
4212 op_mode = GET_MODE (in2);
4213 if (op_mode == VOIDmode)
4215 in2 = simplify_gen_unary (NOT, op_mode, in2, op_mode);
4217 if (GET_CODE (in2) == NOT && GET_CODE (in1) != NOT)
4220 in2 = in1; in1 = tem;
4223 return gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
4229 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
4230 if (GET_CODE (XEXP (x, 0)) == XOR
4231 && XEXP (XEXP (x, 0), 1) == const1_rtx
4232 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
4233 return simplify_gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
4236 temp = expand_compound_operation (XEXP (x, 0));
4238 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4239 replaced by (lshiftrt X C). This will convert
4240 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4242 if (GET_CODE (temp) == ASHIFTRT
4243 && GET_CODE (XEXP (temp, 1)) == CONST_INT
4244 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4245 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
4246 INTVAL (XEXP (temp, 1)));
4248 /* If X has only a single bit that might be nonzero, say, bit I, convert
4249 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4250 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4251 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4252 or a SUBREG of one since we'd be making the expression more
4253 complex if it was just a register. */
4256 && ! (GET_CODE (temp) == SUBREG
4257 && REG_P (SUBREG_REG (temp)))
4258 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4260 rtx temp1 = simplify_shift_const
4261 (NULL_RTX, ASHIFTRT, mode,
4262 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4263 GET_MODE_BITSIZE (mode) - 1 - i),
4264 GET_MODE_BITSIZE (mode) - 1 - i);
4266 /* If all we did was surround TEMP with the two shifts, we
4267 haven't improved anything, so don't use it. Otherwise,
4268 we are better off with TEMP1. */
4269 if (GET_CODE (temp1) != ASHIFTRT
4270 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4271 || XEXP (XEXP (temp1, 0), 0) != temp)
4277 /* We can't handle truncation to a partial integer mode here
4278 because we don't know the real bitsize of the partial
4280 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4283 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4284 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4285 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4287 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4288 GET_MODE_MASK (mode), NULL_RTX, 0));
4290 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4291 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4292 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4293 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4294 return XEXP (XEXP (x, 0), 0);
4296 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4297 (OP:SI foo:SI) if OP is NEG or ABS. */
4298 if ((GET_CODE (XEXP (x, 0)) == ABS
4299 || GET_CODE (XEXP (x, 0)) == NEG)
4300 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
4301 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
4302 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4303 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4304 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4306 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4308 if (GET_CODE (XEXP (x, 0)) == SUBREG
4309 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
4310 && subreg_lowpart_p (XEXP (x, 0)))
4311 return SUBREG_REG (XEXP (x, 0));
4313 /* If we know that the value is already truncated, we can
4314 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4315 is nonzero for the corresponding modes. But don't do this
4316 for an (LSHIFTRT (MULT ...)) since this will cause problems
4317 with the umulXi3_highpart patterns. */
4318 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4319 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4320 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4321 >= (unsigned int) (GET_MODE_BITSIZE (mode) + 1)
4322 && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT
4323 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT))
4324 return gen_lowpart (mode, XEXP (x, 0));
4326 /* A truncate of a comparison can be replaced with a subreg if
4327 STORE_FLAG_VALUE permits. This is like the previous test,
4328 but it works even if the comparison is done in a mode larger
4329 than HOST_BITS_PER_WIDE_INT. */
4330 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4331 && COMPARISON_P (XEXP (x, 0))
4332 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0)
4333 return gen_lowpart (mode, XEXP (x, 0));
4335 /* Similarly, a truncate of a register whose value is a
4336 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4338 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4339 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4340 && (temp = get_last_value (XEXP (x, 0)))
4341 && COMPARISON_P (temp))
4342 return gen_lowpart (mode, XEXP (x, 0));
4346 case FLOAT_TRUNCATE:
4347 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4348 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4349 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4350 return XEXP (XEXP (x, 0), 0);
4352 /* (float_truncate:SF (float_truncate:DF foo:XF))
4353 = (float_truncate:SF foo:XF).
4354 This may eliminate double rounding, so it is unsafe.
4356 (float_truncate:SF (float_extend:XF foo:DF))
4357 = (float_truncate:SF foo:DF).
4359 (float_truncate:DF (float_extend:XF foo:SF))
4360 = (float_extend:SF foo:DF). */
4361 if ((GET_CODE (XEXP (x, 0)) == FLOAT_TRUNCATE
4362 && flag_unsafe_math_optimizations)
4363 || GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND)
4364 return simplify_gen_unary (GET_MODE_SIZE (GET_MODE (XEXP (XEXP (x, 0),
4366 > GET_MODE_SIZE (mode)
4367 ? FLOAT_TRUNCATE : FLOAT_EXTEND,
4369 XEXP (XEXP (x, 0), 0), mode);
4371 /* (float_truncate (float x)) is (float x) */
4372 if (GET_CODE (XEXP (x, 0)) == FLOAT
4373 && (flag_unsafe_math_optimizations
4374 || ((unsigned)significand_size (GET_MODE (XEXP (x, 0)))
4375 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x, 0), 0)))
4376 - num_sign_bit_copies (XEXP (XEXP (x, 0), 0),
4377 GET_MODE (XEXP (XEXP (x, 0), 0)))))))
4378 return simplify_gen_unary (FLOAT, mode,
4379 XEXP (XEXP (x, 0), 0),
4380 GET_MODE (XEXP (XEXP (x, 0), 0)));
4382 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4383 (OP:SF foo:SF) if OP is NEG or ABS. */
4384 if ((GET_CODE (XEXP (x, 0)) == ABS
4385 || GET_CODE (XEXP (x, 0)) == NEG)
4386 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
4387 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4388 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4389 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4391 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4392 is (float_truncate:SF x). */
4393 if (GET_CODE (XEXP (x, 0)) == SUBREG
4394 && subreg_lowpart_p (XEXP (x, 0))
4395 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
4396 return SUBREG_REG (XEXP (x, 0));
4399 /* (float_extend (float_extend x)) is (float_extend x)
4401 (float_extend (float x)) is (float x) assuming that double
4402 rounding can't happen.
4404 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4405 || (GET_CODE (XEXP (x, 0)) == FLOAT
4406 && ((unsigned)significand_size (GET_MODE (XEXP (x, 0)))
4407 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x, 0), 0)))
4408 - num_sign_bit_copies (XEXP (XEXP (x, 0), 0),
4409 GET_MODE (XEXP (XEXP (x, 0), 0)))))))
4410 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4411 XEXP (XEXP (x, 0), 0),
4412 GET_MODE (XEXP (XEXP (x, 0), 0)));
4417 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4418 using cc0, in which case we want to leave it as a COMPARE
4419 so we can distinguish it from a register-register-copy. */
4420 if (XEXP (x, 1) == const0_rtx)
4423 /* x - 0 is the same as x unless x's mode has signed zeros and
4424 allows rounding towards -infinity. Under those conditions,
4426 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4427 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4428 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4434 /* (const (const X)) can become (const X). Do it this way rather than
4435 returning the inner CONST since CONST can be shared with a
4437 if (GET_CODE (XEXP (x, 0)) == CONST)
4438 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4443 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4444 can add in an offset. find_split_point will split this address up
4445 again if it doesn't match. */
4446 if (GET_CODE (XEXP (x, 0)) == HIGH
4447 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4453 /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)).
4455 if (GET_CODE (XEXP (x, 0)) == MULT
4456 && GET_CODE (XEXP (XEXP (x, 0), 0)) == NEG)
4460 in1 = XEXP (XEXP (XEXP (x, 0), 0), 0);
4461 in2 = XEXP (XEXP (x, 0), 1);
4462 return simplify_gen_binary (MINUS, mode, XEXP (x, 1),
4463 simplify_gen_binary (MULT, mode,
4467 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4468 outermost. That's because that's the way indexed addresses are
4469 supposed to appear. This code used to check many more cases, but
4470 they are now checked elsewhere. */
4471 if (GET_CODE (XEXP (x, 0)) == PLUS
4472 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
4473 return simplify_gen_binary (PLUS, mode,
4474 simplify_gen_binary (PLUS, mode,
4475 XEXP (XEXP (x, 0), 0),
4477 XEXP (XEXP (x, 0), 1));
4479 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4480 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4481 bit-field and can be replaced by either a sign_extend or a
4482 sign_extract. The `and' may be a zero_extend and the two
4483 <c>, -<c> constants may be reversed. */
4484 if (GET_CODE (XEXP (x, 0)) == XOR
4485 && GET_CODE (XEXP (x, 1)) == CONST_INT
4486 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4487 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4488 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4489 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4490 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4491 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4492 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4493 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4494 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4495 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4496 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4497 == (unsigned int) i + 1))))
4498 return simplify_shift_const
4499 (NULL_RTX, ASHIFTRT, mode,
4500 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4501 XEXP (XEXP (XEXP (x, 0), 0), 0),
4502 GET_MODE_BITSIZE (mode) - (i + 1)),
4503 GET_MODE_BITSIZE (mode) - (i + 1));
4505 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4506 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4507 is 1. This produces better code than the alternative immediately
4509 if (COMPARISON_P (XEXP (x, 0))
4510 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
4511 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx))
4512 && (reversed = reversed_comparison (XEXP (x, 0), mode)))
4514 simplify_gen_unary (NEG, mode, reversed, mode);
4516 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4517 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4518 the bitsize of the mode - 1. This allows simplification of
4519 "a = (b & 8) == 0;" */
4520 if (XEXP (x, 1) == constm1_rtx
4521 && !REG_P (XEXP (x, 0))
4522 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4523 && REG_P (SUBREG_REG (XEXP (x, 0))))
4524 && nonzero_bits (XEXP (x, 0), mode) == 1)
4525 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4526 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4527 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4528 GET_MODE_BITSIZE (mode) - 1),
4529 GET_MODE_BITSIZE (mode) - 1);
4531 /* If we are adding two things that have no bits in common, convert
4532 the addition into an IOR. This will often be further simplified,
4533 for example in cases like ((a & 1) + (a & 2)), which can
4536 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4537 && (nonzero_bits (XEXP (x, 0), mode)
4538 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4540 /* Try to simplify the expression further. */
4541 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4542 temp = combine_simplify_rtx (tor, mode, in_dest);
4544 /* If we could, great. If not, do not go ahead with the IOR
4545 replacement, since PLUS appears in many special purpose
4546 address arithmetic instructions. */
4547 if (GET_CODE (temp) != CLOBBER && temp != tor)
4553 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4554 by reversing the comparison code if valid. */
4555 if (STORE_FLAG_VALUE == 1
4556 && XEXP (x, 0) == const1_rtx
4557 && COMPARISON_P (XEXP (x, 1))
4558 && (reversed = reversed_comparison (XEXP (x, 1), mode)))
4561 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4562 (and <foo> (const_int pow2-1)) */
4563 if (GET_CODE (XEXP (x, 1)) == AND
4564 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4565 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4566 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4567 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4568 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4570 /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A).
4572 if (GET_CODE (XEXP (x, 1)) == MULT
4573 && GET_CODE (XEXP (XEXP (x, 1), 0)) == NEG)
4577 in1 = XEXP (XEXP (XEXP (x, 1), 0), 0);
4578 in2 = XEXP (XEXP (x, 1), 1);
4579 return simplify_gen_binary (PLUS, mode,
4580 simplify_gen_binary (MULT, mode,
4585 /* Canonicalize (minus (neg A) (mult B C)) to
4586 (minus (mult (neg B) C) A). */
4587 if (GET_CODE (XEXP (x, 1)) == MULT
4588 && GET_CODE (XEXP (x, 0)) == NEG)
4592 in1 = simplify_gen_unary (NEG, mode, XEXP (XEXP (x, 1), 0), mode);
4593 in2 = XEXP (XEXP (x, 1), 1);
4594 return simplify_gen_binary (MINUS, mode,
4595 simplify_gen_binary (MULT, mode,
4597 XEXP (XEXP (x, 0), 0));
4600 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4602 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
4603 return simplify_gen_binary (MINUS, mode,
4604 simplify_gen_binary (MINUS, mode,
4606 XEXP (XEXP (x, 1), 0)),
4607 XEXP (XEXP (x, 1), 1));
4611 /* If we have (mult (plus A B) C), apply the distributive law and then
4612 the inverse distributive law to see if things simplify. This
4613 occurs mostly in addresses, often when unrolling loops. */
4615 if (GET_CODE (XEXP (x, 0)) == PLUS)
4617 rtx result = distribute_and_simplify_rtx (x, 0);
4622 /* Try simplify a*(b/c) as (a*b)/c. */
4623 if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4624 && GET_CODE (XEXP (x, 0)) == DIV)
4626 rtx tem = simplify_binary_operation (MULT, mode,
4627 XEXP (XEXP (x, 0), 0),
4630 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4635 /* If this is a divide by a power of two, treat it as a shift if
4636 its first operand is a shift. */
4637 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4638 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4639 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4640 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4641 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4642 || GET_CODE (XEXP (x, 0)) == ROTATE
4643 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4644 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4648 case GT: case GTU: case GE: case GEU:
4649 case LT: case LTU: case LE: case LEU:
4650 case UNEQ: case LTGT:
4651 case UNGT: case UNGE:
4652 case UNLT: case UNLE:
4653 case UNORDERED: case ORDERED:
4654 /* If the first operand is a condition code, we can't do anything
4656 if (GET_CODE (XEXP (x, 0)) == COMPARE
4657 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4658 && ! CC0_P (XEXP (x, 0))))
4660 rtx op0 = XEXP (x, 0);
4661 rtx op1 = XEXP (x, 1);
4662 enum rtx_code new_code;
4664 if (GET_CODE (op0) == COMPARE)
4665 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4667 /* Simplify our comparison, if possible. */
4668 new_code = simplify_comparison (code, &op0, &op1);
4670 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4671 if only the low-order bit is possibly nonzero in X (such as when
4672 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4673 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4674 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4677 Remove any ZERO_EXTRACT we made when thinking this was a
4678 comparison. It may now be simpler to use, e.g., an AND. If a
4679 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4680 the call to make_compound_operation in the SET case. */
4682 if (STORE_FLAG_VALUE == 1
4683 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4684 && op1 == const0_rtx
4685 && mode == GET_MODE (op0)
4686 && nonzero_bits (op0, mode) == 1)
4687 return gen_lowpart (mode,
4688 expand_compound_operation (op0));
4690 else if (STORE_FLAG_VALUE == 1
4691 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4692 && op1 == const0_rtx
4693 && mode == GET_MODE (op0)
4694 && (num_sign_bit_copies (op0, mode)
4695 == GET_MODE_BITSIZE (mode)))
4697 op0 = expand_compound_operation (op0);
4698 return simplify_gen_unary (NEG, mode,
4699 gen_lowpart (mode, op0),
4703 else if (STORE_FLAG_VALUE == 1
4704 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4705 && op1 == const0_rtx
4706 && mode == GET_MODE (op0)
4707 && nonzero_bits (op0, mode) == 1)
4709 op0 = expand_compound_operation (op0);
4710 return simplify_gen_binary (XOR, mode,
4711 gen_lowpart (mode, op0),
4715 else if (STORE_FLAG_VALUE == 1
4716 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4717 && op1 == const0_rtx
4718 && mode == GET_MODE (op0)
4719 && (num_sign_bit_copies (op0, mode)
4720 == GET_MODE_BITSIZE (mode)))
4722 op0 = expand_compound_operation (op0);
4723 return plus_constant (gen_lowpart (mode, op0), 1);
4726 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4728 if (STORE_FLAG_VALUE == -1
4729 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4730 && op1 == const0_rtx
4731 && (num_sign_bit_copies (op0, mode)
4732 == GET_MODE_BITSIZE (mode)))
4733 return gen_lowpart (mode,
4734 expand_compound_operation (op0));
4736 else if (STORE_FLAG_VALUE == -1
4737 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4738 && op1 == const0_rtx
4739 && mode == GET_MODE (op0)
4740 && nonzero_bits (op0, mode) == 1)
4742 op0 = expand_compound_operation (op0);
4743 return simplify_gen_unary (NEG, mode,
4744 gen_lowpart (mode, op0),
4748 else if (STORE_FLAG_VALUE == -1
4749 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4750 && op1 == const0_rtx
4751 && mode == GET_MODE (op0)
4752 && (num_sign_bit_copies (op0, mode)
4753 == GET_MODE_BITSIZE (mode)))
4755 op0 = expand_compound_operation (op0);
4756 return simplify_gen_unary (NOT, mode,
4757 gen_lowpart (mode, op0),
4761 /* If X is 0/1, (eq X 0) is X-1. */
4762 else if (STORE_FLAG_VALUE == -1
4763 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4764 && op1 == const0_rtx
4765 && mode == GET_MODE (op0)
4766 && nonzero_bits (op0, mode) == 1)
4768 op0 = expand_compound_operation (op0);
4769 return plus_constant (gen_lowpart (mode, op0), -1);
4772 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4773 one bit that might be nonzero, we can convert (ne x 0) to
4774 (ashift x c) where C puts the bit in the sign bit. Remove any
4775 AND with STORE_FLAG_VALUE when we are done, since we are only
4776 going to test the sign bit. */
4777 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4778 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4779 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4780 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4781 && op1 == const0_rtx
4782 && mode == GET_MODE (op0)
4783 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4785 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4786 expand_compound_operation (op0),
4787 GET_MODE_BITSIZE (mode) - 1 - i);
4788 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4794 /* If the code changed, return a whole new comparison. */
4795 if (new_code != code)
4796 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4798 /* Otherwise, keep this operation, but maybe change its operands.
4799 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4800 SUBST (XEXP (x, 0), op0);
4801 SUBST (XEXP (x, 1), op1);
4806 return simplify_if_then_else (x);
4812 /* If we are processing SET_DEST, we are done. */
4816 return expand_compound_operation (x);
4819 return simplify_set (x);
4824 return simplify_logical (x);
4827 /* (abs (neg <foo>)) -> (abs <foo>) */
4828 if (GET_CODE (XEXP (x, 0)) == NEG)
4829 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4831 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4833 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4836 /* If operand is something known to be positive, ignore the ABS. */
4837 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4838 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4839 <= HOST_BITS_PER_WIDE_INT)
4840 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4841 & ((HOST_WIDE_INT) 1
4842 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4846 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4847 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4848 return gen_rtx_NEG (mode, XEXP (x, 0));
4853 /* (ffs (*_extend <X>)) = (ffs <X>) */
4854 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4855 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4856 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4861 /* (pop* (zero_extend <X>)) = (pop* <X>) */
4862 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4863 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4867 /* (float (sign_extend <X>)) = (float <X>). */
4868 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4869 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4877 /* If this is a shift by a constant amount, simplify it. */
4878 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4879 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4880 INTVAL (XEXP (x, 1)));
4882 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
4884 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
4886 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4893 rtx op0 = XEXP (x, 0);
4894 rtx op1 = XEXP (x, 1);
4897 gcc_assert (GET_CODE (op1) == PARALLEL);
4898 len = XVECLEN (op1, 0);
4900 && GET_CODE (XVECEXP (op1, 0, 0)) == CONST_INT
4901 && GET_CODE (op0) == VEC_CONCAT)
4903 int offset = INTVAL (XVECEXP (op1, 0, 0)) * GET_MODE_SIZE (GET_MODE (x));
4905 /* Try to find the element in the VEC_CONCAT. */
4908 if (GET_MODE (op0) == GET_MODE (x))
4910 if (GET_CODE (op0) == VEC_CONCAT)
4912 HOST_WIDE_INT op0_size = GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)));
4913 if (offset < op0_size)
4914 op0 = XEXP (op0, 0);
4918 op0 = XEXP (op0, 1);
4936 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4939 simplify_if_then_else (rtx x)
4941 enum machine_mode mode = GET_MODE (x);
4942 rtx cond = XEXP (x, 0);
4943 rtx true_rtx = XEXP (x, 1);
4944 rtx false_rtx = XEXP (x, 2);
4945 enum rtx_code true_code = GET_CODE (cond);
4946 int comparison_p = COMPARISON_P (cond);
4949 enum rtx_code false_code;
4952 /* Simplify storing of the truth value. */
4953 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4954 return simplify_gen_relational (true_code, mode, VOIDmode,
4955 XEXP (cond, 0), XEXP (cond, 1));
4957 /* Also when the truth value has to be reversed. */
4959 && true_rtx == const0_rtx && false_rtx == const_true_rtx
4960 && (reversed = reversed_comparison (cond, mode)))
4963 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4964 in it is being compared against certain values. Get the true and false
4965 comparisons and see if that says anything about the value of each arm. */
4968 && ((false_code = reversed_comparison_code (cond, NULL))
4970 && REG_P (XEXP (cond, 0)))
4973 rtx from = XEXP (cond, 0);
4974 rtx true_val = XEXP (cond, 1);
4975 rtx false_val = true_val;
4978 /* If FALSE_CODE is EQ, swap the codes and arms. */
4980 if (false_code == EQ)
4982 swapped = 1, true_code = EQ, false_code = NE;
4983 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4986 /* If we are comparing against zero and the expression being tested has
4987 only a single bit that might be nonzero, that is its value when it is
4988 not equal to zero. Similarly if it is known to be -1 or 0. */
4990 if (true_code == EQ && true_val == const0_rtx
4991 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4992 false_code = EQ, false_val = GEN_INT (nzb);
4993 else if (true_code == EQ && true_val == const0_rtx
4994 && (num_sign_bit_copies (from, GET_MODE (from))
4995 == GET_MODE_BITSIZE (GET_MODE (from))))
4996 false_code = EQ, false_val = constm1_rtx;
4998 /* Now simplify an arm if we know the value of the register in the
4999 branch and it is used in the arm. Be careful due to the potential
5000 of locally-shared RTL. */
5002 if (reg_mentioned_p (from, true_rtx))
5003 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
5005 pc_rtx, pc_rtx, 0, 0);
5006 if (reg_mentioned_p (from, false_rtx))
5007 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
5009 pc_rtx, pc_rtx, 0, 0);
5011 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
5012 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
5014 true_rtx = XEXP (x, 1);
5015 false_rtx = XEXP (x, 2);
5016 true_code = GET_CODE (cond);
5019 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5020 reversed, do so to avoid needing two sets of patterns for
5021 subtract-and-branch insns. Similarly if we have a constant in the true
5022 arm, the false arm is the same as the first operand of the comparison, or
5023 the false arm is more complicated than the true arm. */
5026 && reversed_comparison_code (cond, NULL) != UNKNOWN
5027 && (true_rtx == pc_rtx
5028 || (CONSTANT_P (true_rtx)
5029 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
5030 || true_rtx == const0_rtx
5031 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
5032 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
5033 && !OBJECT_P (false_rtx))
5034 || reg_mentioned_p (true_rtx, false_rtx)
5035 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
5037 true_code = reversed_comparison_code (cond, NULL);
5038 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
5039 SUBST (XEXP (x, 1), false_rtx);
5040 SUBST (XEXP (x, 2), true_rtx);
5042 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5045 /* It is possible that the conditional has been simplified out. */
5046 true_code = GET_CODE (cond);
5047 comparison_p = COMPARISON_P (cond);
5050 /* If the two arms are identical, we don't need the comparison. */
5052 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
5055 /* Convert a == b ? b : a to "a". */
5056 if (true_code == EQ && ! side_effects_p (cond)
5057 && !HONOR_NANS (mode)
5058 && rtx_equal_p (XEXP (cond, 0), false_rtx)
5059 && rtx_equal_p (XEXP (cond, 1), true_rtx))
5061 else if (true_code == NE && ! side_effects_p (cond)
5062 && !HONOR_NANS (mode)
5063 && rtx_equal_p (XEXP (cond, 0), true_rtx)
5064 && rtx_equal_p (XEXP (cond, 1), false_rtx))
5067 /* Look for cases where we have (abs x) or (neg (abs X)). */
5069 if (GET_MODE_CLASS (mode) == MODE_INT
5070 && GET_CODE (false_rtx) == NEG
5071 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
5073 && rtx_equal_p (true_rtx, XEXP (cond, 0))
5074 && ! side_effects_p (true_rtx))
5079 return simplify_gen_unary (ABS, mode, true_rtx, mode);
5083 simplify_gen_unary (NEG, mode,
5084 simplify_gen_unary (ABS, mode, true_rtx, mode),
5090 /* Look for MIN or MAX. */
5092 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
5094 && rtx_equal_p (XEXP (cond, 0), true_rtx)
5095 && rtx_equal_p (XEXP (cond, 1), false_rtx)
5096 && ! side_effects_p (cond))
5101 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
5104 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
5107 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
5110 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
5115 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
5116 second operand is zero, this can be done as (OP Z (mult COND C2)) where
5117 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
5118 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
5119 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
5120 neither 1 or -1, but it isn't worth checking for. */
5122 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
5124 && GET_MODE_CLASS (mode) == MODE_INT
5125 && ! side_effects_p (x))
5127 rtx t = make_compound_operation (true_rtx, SET);
5128 rtx f = make_compound_operation (false_rtx, SET);
5129 rtx cond_op0 = XEXP (cond, 0);
5130 rtx cond_op1 = XEXP (cond, 1);
5131 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
5132 enum machine_mode m = mode;
5133 rtx z = 0, c1 = NULL_RTX;
5135 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
5136 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
5137 || GET_CODE (t) == ASHIFT
5138 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
5139 && rtx_equal_p (XEXP (t, 0), f))
5140 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
5142 /* If an identity-zero op is commutative, check whether there
5143 would be a match if we swapped the operands. */
5144 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
5145 || GET_CODE (t) == XOR)
5146 && rtx_equal_p (XEXP (t, 1), f))
5147 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
5148 else if (GET_CODE (t) == SIGN_EXTEND
5149 && (GET_CODE (XEXP (t, 0)) == PLUS
5150 || GET_CODE (XEXP (t, 0)) == MINUS
5151 || GET_CODE (XEXP (t, 0)) == IOR
5152 || GET_CODE (XEXP (t, 0)) == XOR
5153 || GET_CODE (XEXP (t, 0)) == ASHIFT
5154 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5155 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5156 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5157 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5158 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5159 && (num_sign_bit_copies (f, GET_MODE (f))
5161 (GET_MODE_BITSIZE (mode)
5162 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
5164 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5165 extend_op = SIGN_EXTEND;
5166 m = GET_MODE (XEXP (t, 0));
5168 else if (GET_CODE (t) == SIGN_EXTEND
5169 && (GET_CODE (XEXP (t, 0)) == PLUS
5170 || GET_CODE (XEXP (t, 0)) == IOR
5171 || GET_CODE (XEXP (t, 0)) == XOR)
5172 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5173 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5174 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5175 && (num_sign_bit_copies (f, GET_MODE (f))
5177 (GET_MODE_BITSIZE (mode)
5178 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
5180 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5181 extend_op = SIGN_EXTEND;
5182 m = GET_MODE (XEXP (t, 0));
5184 else if (GET_CODE (t) == ZERO_EXTEND
5185 && (GET_CODE (XEXP (t, 0)) == PLUS
5186 || GET_CODE (XEXP (t, 0)) == MINUS
5187 || GET_CODE (XEXP (t, 0)) == IOR
5188 || GET_CODE (XEXP (t, 0)) == XOR
5189 || GET_CODE (XEXP (t, 0)) == ASHIFT
5190 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5191 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5192 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5193 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5194 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5195 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5196 && ((nonzero_bits (f, GET_MODE (f))
5197 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
5200 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5201 extend_op = ZERO_EXTEND;
5202 m = GET_MODE (XEXP (t, 0));
5204 else if (GET_CODE (t) == ZERO_EXTEND
5205 && (GET_CODE (XEXP (t, 0)) == PLUS
5206 || GET_CODE (XEXP (t, 0)) == IOR
5207 || GET_CODE (XEXP (t, 0)) == XOR)
5208 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5209 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5210 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5211 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5212 && ((nonzero_bits (f, GET_MODE (f))
5213 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5216 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5217 extend_op = ZERO_EXTEND;
5218 m = GET_MODE (XEXP (t, 0));
5223 temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
5224 cond_op0, cond_op1),
5225 pc_rtx, pc_rtx, 0, 0);
5226 temp = simplify_gen_binary (MULT, m, temp,
5227 simplify_gen_binary (MULT, m, c1,
5229 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5230 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
5232 if (extend_op != UNKNOWN)
5233 temp = simplify_gen_unary (extend_op, mode, temp, m);
5239 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5240 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5241 negation of a single bit, we can convert this operation to a shift. We
5242 can actually do this more generally, but it doesn't seem worth it. */
5244 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5245 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5246 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5247 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5248 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5249 == GET_MODE_BITSIZE (mode))
5250 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5252 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5253 gen_lowpart (mode, XEXP (cond, 0)), i);
5255 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
5256 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5257 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5258 && GET_MODE (XEXP (cond, 0)) == mode
5259 && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
5260 == nonzero_bits (XEXP (cond, 0), mode)
5261 && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
5262 return XEXP (cond, 0);
5267 /* Simplify X, a SET expression. Return the new expression. */
5270 simplify_set (rtx x)
5272 rtx src = SET_SRC (x);
5273 rtx dest = SET_DEST (x);
5274 enum machine_mode mode
5275 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5279 /* (set (pc) (return)) gets written as (return). */
5280 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5283 /* Now that we know for sure which bits of SRC we are using, see if we can
5284 simplify the expression for the object knowing that we only need the
5287 if (GET_MODE_CLASS (mode) == MODE_INT
5288 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5290 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
5291 SUBST (SET_SRC (x), src);
5294 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5295 the comparison result and try to simplify it unless we already have used
5296 undobuf.other_insn. */
5297 if ((GET_MODE_CLASS (mode) == MODE_CC
5298 || GET_CODE (src) == COMPARE
5300 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5301 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5302 && COMPARISON_P (*cc_use)
5303 && rtx_equal_p (XEXP (*cc_use, 0), dest))
5305 enum rtx_code old_code = GET_CODE (*cc_use);
5306 enum rtx_code new_code;
5308 int other_changed = 0;
5309 enum machine_mode compare_mode = GET_MODE (dest);
5311 if (GET_CODE (src) == COMPARE)
5312 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5314 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
5316 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
5319 new_code = old_code;
5320 else if (!CONSTANT_P (tmp))
5322 new_code = GET_CODE (tmp);
5323 op0 = XEXP (tmp, 0);
5324 op1 = XEXP (tmp, 1);
5328 rtx pat = PATTERN (other_insn);
5329 undobuf.other_insn = other_insn;
5330 SUBST (*cc_use, tmp);
5332 /* Attempt to simplify CC user. */
5333 if (GET_CODE (pat) == SET)
5335 rtx new = simplify_rtx (SET_SRC (pat));
5336 if (new != NULL_RTX)
5337 SUBST (SET_SRC (pat), new);
5340 /* Convert X into a no-op move. */
5341 SUBST (SET_DEST (x), pc_rtx);
5342 SUBST (SET_SRC (x), pc_rtx);
5346 /* Simplify our comparison, if possible. */
5347 new_code = simplify_comparison (new_code, &op0, &op1);
5349 #ifdef SELECT_CC_MODE
5350 /* If this machine has CC modes other than CCmode, check to see if we
5351 need to use a different CC mode here. */
5352 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
5353 compare_mode = GET_MODE (op0);
5355 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5358 /* If the mode changed, we have to change SET_DEST, the mode in the
5359 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5360 a hard register, just build new versions with the proper mode. If it
5361 is a pseudo, we lose unless it is only time we set the pseudo, in
5362 which case we can safely change its mode. */
5363 if (compare_mode != GET_MODE (dest))
5365 if (can_change_dest_mode (dest, 0, compare_mode))
5367 unsigned int regno = REGNO (dest);
5368 rtx new_dest = gen_rtx_REG (compare_mode, regno);
5370 if (regno >= FIRST_PSEUDO_REGISTER)
5371 SUBST (regno_reg_rtx[regno], new_dest);
5373 SUBST (SET_DEST (x), new_dest);
5374 SUBST (XEXP (*cc_use, 0), new_dest);
5381 #endif /* SELECT_CC_MODE */
5383 /* If the code changed, we have to build a new comparison in
5384 undobuf.other_insn. */
5385 if (new_code != old_code)
5387 int other_changed_previously = other_changed;
5388 unsigned HOST_WIDE_INT mask;
5390 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5394 /* If the only change we made was to change an EQ into an NE or
5395 vice versa, OP0 has only one bit that might be nonzero, and OP1
5396 is zero, check if changing the user of the condition code will
5397 produce a valid insn. If it won't, we can keep the original code
5398 in that insn by surrounding our operation with an XOR. */
5400 if (((old_code == NE && new_code == EQ)
5401 || (old_code == EQ && new_code == NE))
5402 && ! other_changed_previously && op1 == const0_rtx
5403 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5404 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5406 rtx pat = PATTERN (other_insn), note = 0;
5408 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5409 && ! check_asm_operands (pat)))
5411 PUT_CODE (*cc_use, old_code);
5414 op0 = simplify_gen_binary (XOR, GET_MODE (op0),
5415 op0, GEN_INT (mask));
5421 undobuf.other_insn = other_insn;
5424 /* If we are now comparing against zero, change our source if
5425 needed. If we do not use cc0, we always have a COMPARE. */
5426 if (op1 == const0_rtx && dest == cc0_rtx)
5428 SUBST (SET_SRC (x), op0);
5434 /* Otherwise, if we didn't previously have a COMPARE in the
5435 correct mode, we need one. */
5436 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5438 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5441 else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
5443 SUBST(SET_SRC (x), op0);
5448 /* Otherwise, update the COMPARE if needed. */
5449 SUBST (XEXP (src, 0), op0);
5450 SUBST (XEXP (src, 1), op1);
5455 /* Get SET_SRC in a form where we have placed back any
5456 compound expressions. Then do the checks below. */
5457 src = make_compound_operation (src, SET);
5458 SUBST (SET_SRC (x), src);
5461 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5462 and X being a REG or (subreg (reg)), we may be able to convert this to
5463 (set (subreg:m2 x) (op)).
5465 We can always do this if M1 is narrower than M2 because that means that
5466 we only care about the low bits of the result.
5468 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5469 perform a narrower operation than requested since the high-order bits will
5470 be undefined. On machine where it is defined, this transformation is safe
5471 as long as M1 and M2 have the same number of words. */
5473 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5474 && !OBJECT_P (SUBREG_REG (src))
5475 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5477 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5478 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5479 #ifndef WORD_REGISTER_OPERATIONS
5480 && (GET_MODE_SIZE (GET_MODE (src))
5481 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5483 #ifdef CANNOT_CHANGE_MODE_CLASS
5484 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
5485 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5486 GET_MODE (SUBREG_REG (src)),
5490 || (GET_CODE (dest) == SUBREG
5491 && REG_P (SUBREG_REG (dest)))))
5493 SUBST (SET_DEST (x),
5494 gen_lowpart (GET_MODE (SUBREG_REG (src)),
5496 SUBST (SET_SRC (x), SUBREG_REG (src));
5498 src = SET_SRC (x), dest = SET_DEST (x);
5502 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5505 && GET_CODE (src) == SUBREG
5506 && subreg_lowpart_p (src)
5507 && (GET_MODE_BITSIZE (GET_MODE (src))
5508 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5510 rtx inner = SUBREG_REG (src);
5511 enum machine_mode inner_mode = GET_MODE (inner);
5513 /* Here we make sure that we don't have a sign bit on. */
5514 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5515 && (nonzero_bits (inner, inner_mode)
5516 < ((unsigned HOST_WIDE_INT) 1
5517 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5519 SUBST (SET_SRC (x), inner);
5525 #ifdef LOAD_EXTEND_OP
5526 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5527 would require a paradoxical subreg. Replace the subreg with a
5528 zero_extend to avoid the reload that would otherwise be required. */
5530 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5531 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
5532 && SUBREG_BYTE (src) == 0
5533 && (GET_MODE_SIZE (GET_MODE (src))
5534 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5535 && MEM_P (SUBREG_REG (src)))
5538 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5539 GET_MODE (src), SUBREG_REG (src)));
5545 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5546 are comparing an item known to be 0 or -1 against 0, use a logical
5547 operation instead. Check for one of the arms being an IOR of the other
5548 arm with some value. We compute three terms to be IOR'ed together. In
5549 practice, at most two will be nonzero. Then we do the IOR's. */
5551 if (GET_CODE (dest) != PC
5552 && GET_CODE (src) == IF_THEN_ELSE
5553 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5554 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5555 && XEXP (XEXP (src, 0), 1) == const0_rtx
5556 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5557 #ifdef HAVE_conditional_move
5558 && ! can_conditionally_move_p (GET_MODE (src))
5560 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5561 GET_MODE (XEXP (XEXP (src, 0), 0)))
5562 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5563 && ! side_effects_p (src))
5565 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5566 ? XEXP (src, 1) : XEXP (src, 2));
5567 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5568 ? XEXP (src, 2) : XEXP (src, 1));
5569 rtx term1 = const0_rtx, term2, term3;
5571 if (GET_CODE (true_rtx) == IOR
5572 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5573 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
5574 else if (GET_CODE (true_rtx) == IOR
5575 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5576 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
5577 else if (GET_CODE (false_rtx) == IOR
5578 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5579 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
5580 else if (GET_CODE (false_rtx) == IOR
5581 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5582 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
5584 term2 = simplify_gen_binary (AND, GET_MODE (src),
5585 XEXP (XEXP (src, 0), 0), true_rtx);
5586 term3 = simplify_gen_binary (AND, GET_MODE (src),
5587 simplify_gen_unary (NOT, GET_MODE (src),
5588 XEXP (XEXP (src, 0), 0),
5593 simplify_gen_binary (IOR, GET_MODE (src),
5594 simplify_gen_binary (IOR, GET_MODE (src),
5601 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5602 whole thing fail. */
5603 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5605 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5608 /* Convert this into a field assignment operation, if possible. */
5609 return make_field_assignment (x);
5612 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5616 simplify_logical (rtx x)
5618 enum machine_mode mode = GET_MODE (x);
5619 rtx op0 = XEXP (x, 0);
5620 rtx op1 = XEXP (x, 1);
5623 switch (GET_CODE (x))
5626 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5627 insn (and may simplify more). */
5628 if (GET_CODE (op0) == XOR
5629 && rtx_equal_p (XEXP (op0, 0), op1)
5630 && ! side_effects_p (op1))
5631 x = simplify_gen_binary (AND, mode,
5632 simplify_gen_unary (NOT, mode,
5633 XEXP (op0, 1), mode),
5636 if (GET_CODE (op0) == XOR
5637 && rtx_equal_p (XEXP (op0, 1), op1)
5638 && ! side_effects_p (op1))
5639 x = simplify_gen_binary (AND, mode,
5640 simplify_gen_unary (NOT, mode,
5641 XEXP (op0, 0), mode),
5644 /* Similarly for (~(A ^ B)) & A. */
5645 if (GET_CODE (op0) == NOT
5646 && GET_CODE (XEXP (op0, 0)) == XOR
5647 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
5648 && ! side_effects_p (op1))
5649 x = simplify_gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
5651 if (GET_CODE (op0) == NOT
5652 && GET_CODE (XEXP (op0, 0)) == XOR
5653 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
5654 && ! side_effects_p (op1))
5655 x = simplify_gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
5657 /* We can call simplify_and_const_int only if we don't lose
5658 any (sign) bits when converting INTVAL (op1) to
5659 "unsigned HOST_WIDE_INT". */
5660 if (GET_CODE (op1) == CONST_INT
5661 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5662 || INTVAL (op1) > 0))
5664 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5666 /* If we have (ior (and (X C1) C2)) and the next restart would be
5667 the last, simplify this by making C1 as small as possible
5668 and then exit. Only do this if C1 actually changes: for now
5669 this only saves memory but, should this transformation be
5670 moved to simplify-rtx.c, we'd risk unbounded recursion there. */
5671 if (GET_CODE (x) == IOR && GET_CODE (op0) == AND
5672 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5673 && GET_CODE (op1) == CONST_INT
5674 && (INTVAL (XEXP (op0, 1)) & INTVAL (op1)) != 0)
5675 return simplify_gen_binary (IOR, mode,
5677 (AND, mode, XEXP (op0, 0),
5678 GEN_INT (INTVAL (XEXP (op0, 1))
5679 & ~INTVAL (op1))), op1);
5681 if (GET_CODE (x) != AND)
5688 /* Convert (A | B) & A to A. */
5689 if (GET_CODE (op0) == IOR
5690 && (rtx_equal_p (XEXP (op0, 0), op1)
5691 || rtx_equal_p (XEXP (op0, 1), op1))
5692 && ! side_effects_p (XEXP (op0, 0))
5693 && ! side_effects_p (XEXP (op0, 1)))
5696 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
5697 apply the distributive law and then the inverse distributive
5698 law to see if things simplify. */
5699 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5701 rtx result = distribute_and_simplify_rtx (x, 0);
5705 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5707 rtx result = distribute_and_simplify_rtx (x, 1);
5714 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5715 if (GET_CODE (op1) == CONST_INT
5716 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5717 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
5720 /* Convert (A & B) | A to A. */
5721 if (GET_CODE (op0) == AND
5722 && (rtx_equal_p (XEXP (op0, 0), op1)
5723 || rtx_equal_p (XEXP (op0, 1), op1))
5724 && ! side_effects_p (XEXP (op0, 0))
5725 && ! side_effects_p (XEXP (op0, 1)))
5728 /* If we have (ior (and A B) C), apply the distributive law and then
5729 the inverse distributive law to see if things simplify. */
5731 if (GET_CODE (op0) == AND)
5733 rtx result = distribute_and_simplify_rtx (x, 0);
5738 if (GET_CODE (op1) == AND)
5740 rtx result = distribute_and_simplify_rtx (x, 1);
5745 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5746 mode size to (rotate A CX). */
5748 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5749 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5750 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5751 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5752 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5753 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5754 == GET_MODE_BITSIZE (mode)))
5755 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5756 (GET_CODE (op0) == ASHIFT
5757 ? XEXP (op0, 1) : XEXP (op1, 1)));
5759 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5760 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5761 does not affect any of the bits in OP1, it can really be done
5762 as a PLUS and we can associate. We do this by seeing if OP1
5763 can be safely shifted left C bits. */
5764 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5765 && GET_CODE (XEXP (op0, 0)) == PLUS
5766 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5767 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5768 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5770 int count = INTVAL (XEXP (op0, 1));
5771 HOST_WIDE_INT mask = INTVAL (op1) << count;
5773 if (mask >> count == INTVAL (op1)
5774 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5776 SUBST (XEXP (XEXP (op0, 0), 1),
5777 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5784 /* If we are XORing two things that have no bits in common,
5785 convert them into an IOR. This helps to detect rotation encoded
5786 using those methods and possibly other simplifications. */
5788 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5789 && (nonzero_bits (op0, mode)
5790 & nonzero_bits (op1, mode)) == 0)
5791 return (simplify_gen_binary (IOR, mode, op0, op1));
5793 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5794 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5797 int num_negated = 0;
5799 if (GET_CODE (op0) == NOT)
5800 num_negated++, op0 = XEXP (op0, 0);
5801 if (GET_CODE (op1) == NOT)
5802 num_negated++, op1 = XEXP (op1, 0);
5804 if (num_negated == 2)
5806 SUBST (XEXP (x, 0), op0);
5807 SUBST (XEXP (x, 1), op1);
5809 else if (num_negated == 1)
5811 simplify_gen_unary (NOT, mode,
5812 simplify_gen_binary (XOR, mode, op0, op1),
5816 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5817 correspond to a machine insn or result in further simplifications
5818 if B is a constant. */
5820 if (GET_CODE (op0) == AND
5821 && rtx_equal_p (XEXP (op0, 1), op1)
5822 && ! side_effects_p (op1))
5823 return simplify_gen_binary (AND, mode,
5824 simplify_gen_unary (NOT, mode,
5825 XEXP (op0, 0), mode),
5828 else if (GET_CODE (op0) == AND
5829 && rtx_equal_p (XEXP (op0, 0), op1)
5830 && ! side_effects_p (op1))
5831 return simplify_gen_binary (AND, mode,
5832 simplify_gen_unary (NOT, mode,
5833 XEXP (op0, 1), mode),
5836 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5837 comparison if STORE_FLAG_VALUE is 1. */
5838 if (STORE_FLAG_VALUE == 1
5839 && op1 == const1_rtx
5840 && COMPARISON_P (op0)
5841 && (reversed = reversed_comparison (op0, mode)))
5844 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5845 is (lt foo (const_int 0)), so we can perform the above
5846 simplification if STORE_FLAG_VALUE is 1. */
5848 if (STORE_FLAG_VALUE == 1
5849 && op1 == const1_rtx
5850 && GET_CODE (op0) == LSHIFTRT
5851 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5852 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5853 return gen_rtx_GE (mode, XEXP (op0, 0), const0_rtx);
5855 /* (xor (comparison foo bar) (const_int sign-bit))
5856 when STORE_FLAG_VALUE is the sign bit. */
5857 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5858 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5859 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5860 && op1 == const_true_rtx
5861 && COMPARISON_P (op0)
5862 && (reversed = reversed_comparison (op0, mode)))
5874 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5875 operations" because they can be replaced with two more basic operations.
5876 ZERO_EXTEND is also considered "compound" because it can be replaced with
5877 an AND operation, which is simpler, though only one operation.
5879 The function expand_compound_operation is called with an rtx expression
5880 and will convert it to the appropriate shifts and AND operations,
5881 simplifying at each stage.
5883 The function make_compound_operation is called to convert an expression
5884 consisting of shifts and ANDs into the equivalent compound expression.
5885 It is the inverse of this function, loosely speaking. */
5888 expand_compound_operation (rtx x)
5890 unsigned HOST_WIDE_INT pos = 0, len;
5892 unsigned int modewidth;
5895 switch (GET_CODE (x))
5900 /* We can't necessarily use a const_int for a multiword mode;
5901 it depends on implicitly extending the value.
5902 Since we don't know the right way to extend it,
5903 we can't tell whether the implicit way is right.
5905 Even for a mode that is no wider than a const_int,
5906 we can't win, because we need to sign extend one of its bits through
5907 the rest of it, and we don't know which bit. */
5908 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5911 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5912 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5913 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5914 reloaded. If not for that, MEM's would very rarely be safe.
5916 Reject MODEs bigger than a word, because we might not be able
5917 to reference a two-register group starting with an arbitrary register
5918 (and currently gen_lowpart might crash for a SUBREG). */
5920 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5923 /* Reject MODEs that aren't scalar integers because turning vector
5924 or complex modes into shifts causes problems. */
5926 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5929 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5930 /* If the inner object has VOIDmode (the only way this can happen
5931 is if it is an ASM_OPERANDS), we can't do anything since we don't
5932 know how much masking to do. */
5941 /* ... fall through ... */
5944 /* If the operand is a CLOBBER, just return it. */
5945 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5948 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5949 || GET_CODE (XEXP (x, 2)) != CONST_INT
5950 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5953 /* Reject MODEs that aren't scalar integers because turning vector
5954 or complex modes into shifts causes problems. */
5956 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5959 len = INTVAL (XEXP (x, 1));
5960 pos = INTVAL (XEXP (x, 2));
5962 /* If this goes outside the object being extracted, replace the object
5963 with a (use (mem ...)) construct that only combine understands
5964 and is used only for this purpose. */
5965 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5966 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5968 if (BITS_BIG_ENDIAN)
5969 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5976 /* Convert sign extension to zero extension, if we know that the high
5977 bit is not set, as this is easier to optimize. It will be converted
5978 back to cheaper alternative in make_extraction. */
5979 if (GET_CODE (x) == SIGN_EXTEND
5980 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5981 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5982 & ~(((unsigned HOST_WIDE_INT)
5983 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5987 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5988 rtx temp2 = expand_compound_operation (temp);
5990 /* Make sure this is a profitable operation. */
5991 if (rtx_cost (x, SET) > rtx_cost (temp2, SET))
5993 else if (rtx_cost (x, SET) > rtx_cost (temp, SET))
5999 /* We can optimize some special cases of ZERO_EXTEND. */
6000 if (GET_CODE (x) == ZERO_EXTEND)
6002 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6003 know that the last value didn't have any inappropriate bits
6005 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6006 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6007 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6008 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
6009 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6010 return XEXP (XEXP (x, 0), 0);
6012 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6013 if (GET_CODE (XEXP (x, 0)) == SUBREG
6014 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6015 && subreg_lowpart_p (XEXP (x, 0))
6016 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6017 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
6018 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6019 return SUBREG_REG (XEXP (x, 0));
6021 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6022 is a comparison and STORE_FLAG_VALUE permits. This is like
6023 the first case, but it works even when GET_MODE (x) is larger
6024 than HOST_WIDE_INT. */
6025 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6026 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6027 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
6028 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6029 <= HOST_BITS_PER_WIDE_INT)
6030 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6031 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6032 return XEXP (XEXP (x, 0), 0);
6034 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6035 if (GET_CODE (XEXP (x, 0)) == SUBREG
6036 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6037 && subreg_lowpart_p (XEXP (x, 0))
6038 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
6039 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6040 <= HOST_BITS_PER_WIDE_INT)
6041 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6042 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6043 return SUBREG_REG (XEXP (x, 0));
6047 /* If we reach here, we want to return a pair of shifts. The inner
6048 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6049 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6050 logical depending on the value of UNSIGNEDP.
6052 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6053 converted into an AND of a shift.
6055 We must check for the case where the left shift would have a negative
6056 count. This can happen in a case like (x >> 31) & 255 on machines
6057 that can't shift by a constant. On those machines, we would first
6058 combine the shift with the AND to produce a variable-position
6059 extraction. Then the constant of 31 would be substituted in to produce
6060 a such a position. */
6062 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
6063 if (modewidth + len >= pos)
6064 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
6066 simplify_shift_const (NULL_RTX, ASHIFT,
6069 modewidth - pos - len),
6072 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
6073 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
6074 simplify_shift_const (NULL_RTX, LSHIFTRT,
6077 ((HOST_WIDE_INT) 1 << len) - 1);
6079 /* Any other cases we can't handle. */
6082 /* If we couldn't do this for some reason, return the original
6084 if (GET_CODE (tem) == CLOBBER)
6090 /* X is a SET which contains an assignment of one object into
6091 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6092 or certain SUBREGS). If possible, convert it into a series of
6095 We half-heartedly support variable positions, but do not at all
6096 support variable lengths. */
6099 expand_field_assignment (rtx x)
6102 rtx pos; /* Always counts from low bit. */
6104 rtx mask, cleared, masked;
6105 enum machine_mode compute_mode;
6107 /* Loop until we find something we can't simplify. */
6110 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
6111 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
6113 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
6114 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
6115 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
6117 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
6118 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
6120 inner = XEXP (SET_DEST (x), 0);
6121 len = INTVAL (XEXP (SET_DEST (x), 1));
6122 pos = XEXP (SET_DEST (x), 2);
6124 /* If the position is constant and spans the width of INNER,
6125 surround INNER with a USE to indicate this. */
6126 if (GET_CODE (pos) == CONST_INT
6127 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
6128 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
6130 if (BITS_BIG_ENDIAN)
6132 if (GET_CODE (pos) == CONST_INT)
6133 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
6135 else if (GET_CODE (pos) == MINUS
6136 && GET_CODE (XEXP (pos, 1)) == CONST_INT
6137 && (INTVAL (XEXP (pos, 1))
6138 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
6139 /* If position is ADJUST - X, new position is X. */
6140 pos = XEXP (pos, 0);
6142 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
6143 GEN_INT (GET_MODE_BITSIZE (
6150 /* A SUBREG between two modes that occupy the same numbers of words
6151 can be done by moving the SUBREG to the source. */
6152 else if (GET_CODE (SET_DEST (x)) == SUBREG
6153 /* We need SUBREGs to compute nonzero_bits properly. */
6154 && nonzero_sign_valid
6155 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6156 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6157 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6158 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6160 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6162 (GET_MODE (SUBREG_REG (SET_DEST (x))),
6169 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6170 inner = SUBREG_REG (inner);
6172 compute_mode = GET_MODE (inner);
6174 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6175 if (! SCALAR_INT_MODE_P (compute_mode))
6177 enum machine_mode imode;
6179 /* Don't do anything for vector or complex integral types. */
6180 if (! FLOAT_MODE_P (compute_mode))
6183 /* Try to find an integral mode to pun with. */
6184 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6185 if (imode == BLKmode)
6188 compute_mode = imode;
6189 inner = gen_lowpart (imode, inner);
6192 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6193 if (len >= HOST_BITS_PER_WIDE_INT)
6196 /* Now compute the equivalent expression. Make a copy of INNER
6197 for the SET_DEST in case it is a MEM into which we will substitute;
6198 we don't want shared RTL in that case. */
6199 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
6200 cleared = simplify_gen_binary (AND, compute_mode,
6201 simplify_gen_unary (NOT, compute_mode,
6202 simplify_gen_binary (ASHIFT,
6207 masked = simplify_gen_binary (ASHIFT, compute_mode,
6208 simplify_gen_binary (
6210 gen_lowpart (compute_mode, SET_SRC (x)),
6214 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
6215 simplify_gen_binary (IOR, compute_mode,
6222 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6223 it is an RTX that represents a variable starting position; otherwise,
6224 POS is the (constant) starting bit position (counted from the LSB).
6226 INNER may be a USE. This will occur when we started with a bitfield
6227 that went outside the boundary of the object in memory, which is
6228 allowed on most machines. To isolate this case, we produce a USE
6229 whose mode is wide enough and surround the MEM with it. The only
6230 code that understands the USE is this routine. If it is not removed,
6231 it will cause the resulting insn not to match.
6233 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6236 IN_DEST is nonzero if this is a reference in the destination of a
6237 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6238 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6241 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6242 ZERO_EXTRACT should be built even for bits starting at bit 0.
6244 MODE is the desired mode of the result (if IN_DEST == 0).
6246 The result is an RTX for the extraction or NULL_RTX if the target
6250 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
6251 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
6252 int in_dest, int in_compare)
6254 /* This mode describes the size of the storage area
6255 to fetch the overall value from. Within that, we
6256 ignore the POS lowest bits, etc. */
6257 enum machine_mode is_mode = GET_MODE (inner);
6258 enum machine_mode inner_mode;
6259 enum machine_mode wanted_inner_mode = byte_mode;
6260 enum machine_mode wanted_inner_reg_mode = word_mode;
6261 enum machine_mode pos_mode = word_mode;
6262 enum machine_mode extraction_mode = word_mode;
6263 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
6266 rtx orig_pos_rtx = pos_rtx;
6267 HOST_WIDE_INT orig_pos;
6269 /* Get some information about INNER and get the innermost object. */
6270 if (GET_CODE (inner) == USE)
6271 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
6272 /* We don't need to adjust the position because we set up the USE
6273 to pretend that it was a full-word object. */
6274 spans_byte = 1, inner = XEXP (inner, 0);
6275 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6277 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6278 consider just the QI as the memory to extract from.
6279 The subreg adds or removes high bits; its mode is
6280 irrelevant to the meaning of this extraction,
6281 since POS and LEN count from the lsb. */
6282 if (MEM_P (SUBREG_REG (inner)))
6283 is_mode = GET_MODE (SUBREG_REG (inner));
6284 inner = SUBREG_REG (inner);
6286 else if (GET_CODE (inner) == ASHIFT
6287 && GET_CODE (XEXP (inner, 1)) == CONST_INT
6288 && pos_rtx == 0 && pos == 0
6289 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
6291 /* We're extracting the least significant bits of an rtx
6292 (ashift X (const_int C)), where LEN > C. Extract the
6293 least significant (LEN - C) bits of X, giving an rtx
6294 whose mode is MODE, then shift it left C times. */
6295 new = make_extraction (mode, XEXP (inner, 0),
6296 0, 0, len - INTVAL (XEXP (inner, 1)),
6297 unsignedp, in_dest, in_compare);
6299 return gen_rtx_ASHIFT (mode, new, XEXP (inner, 1));
6302 inner_mode = GET_MODE (inner);
6304 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
6305 pos = INTVAL (pos_rtx), pos_rtx = 0;
6307 /* See if this can be done without an extraction. We never can if the
6308 width of the field is not the same as that of some integer mode. For
6309 registers, we can only avoid the extraction if the position is at the
6310 low-order bit and this is either not in the destination or we have the
6311 appropriate STRICT_LOW_PART operation available.
6313 For MEM, we can avoid an extract if the field starts on an appropriate
6314 boundary and we can change the mode of the memory reference. However,
6315 we cannot directly access the MEM if we have a USE and the underlying
6316 MEM is not TMODE. This combination means that MEM was being used in a
6317 context where bits outside its mode were being referenced; that is only
6318 valid in bit-field insns. */
6320 if (tmode != BLKmode
6321 && ! (spans_byte && inner_mode != tmode)
6322 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6326 && have_insn_for (STRICT_LOW_PART, tmode))))
6327 || (MEM_P (inner) && pos_rtx == 0
6329 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6330 : BITS_PER_UNIT)) == 0
6331 /* We can't do this if we are widening INNER_MODE (it
6332 may not be aligned, for one thing). */
6333 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6334 && (inner_mode == tmode
6335 || (! mode_dependent_address_p (XEXP (inner, 0))
6336 && ! MEM_VOLATILE_P (inner))))))
6338 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6339 field. If the original and current mode are the same, we need not
6340 adjust the offset. Otherwise, we do if bytes big endian.
6342 If INNER is not a MEM, get a piece consisting of just the field
6343 of interest (in this case POS % BITS_PER_WORD must be 0). */
6347 HOST_WIDE_INT offset;
6349 /* POS counts from lsb, but make OFFSET count in memory order. */
6350 if (BYTES_BIG_ENDIAN)
6351 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6353 offset = pos / BITS_PER_UNIT;
6355 new = adjust_address_nv (inner, tmode, offset);
6357 else if (REG_P (inner))
6359 if (tmode != inner_mode)
6361 /* We can't call gen_lowpart in a DEST since we
6362 always want a SUBREG (see below) and it would sometimes
6363 return a new hard register. */
6366 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6368 if (WORDS_BIG_ENDIAN
6369 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6370 final_word = ((GET_MODE_SIZE (inner_mode)
6371 - GET_MODE_SIZE (tmode))
6372 / UNITS_PER_WORD) - final_word;
6374 final_word *= UNITS_PER_WORD;
6375 if (BYTES_BIG_ENDIAN &&
6376 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6377 final_word += (GET_MODE_SIZE (inner_mode)
6378 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6380 /* Avoid creating invalid subregs, for example when
6381 simplifying (x>>32)&255. */
6382 if (!validate_subreg (tmode, inner_mode, inner, final_word))
6385 new = gen_rtx_SUBREG (tmode, inner, final_word);
6388 new = gen_lowpart (tmode, inner);
6394 new = force_to_mode (inner, tmode,
6395 len >= HOST_BITS_PER_WIDE_INT
6396 ? ~(unsigned HOST_WIDE_INT) 0
6397 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6400 /* If this extraction is going into the destination of a SET,
6401 make a STRICT_LOW_PART unless we made a MEM. */
6404 return (MEM_P (new) ? new
6405 : (GET_CODE (new) != SUBREG
6406 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6407 : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
6412 if (GET_CODE (new) == CONST_INT)
6413 return gen_int_mode (INTVAL (new), mode);
6415 /* If we know that no extraneous bits are set, and that the high
6416 bit is not set, convert the extraction to the cheaper of
6417 sign and zero extension, that are equivalent in these cases. */
6418 if (flag_expensive_optimizations
6419 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6420 && ((nonzero_bits (new, tmode)
6421 & ~(((unsigned HOST_WIDE_INT)
6422 GET_MODE_MASK (tmode))
6426 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6427 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6429 /* Prefer ZERO_EXTENSION, since it gives more information to
6431 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6436 /* Otherwise, sign- or zero-extend unless we already are in the
6439 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6443 /* Unless this is a COMPARE or we have a funny memory reference,
6444 don't do anything with zero-extending field extracts starting at
6445 the low-order bit since they are simple AND operations. */
6446 if (pos_rtx == 0 && pos == 0 && ! in_dest
6447 && ! in_compare && ! spans_byte && unsignedp)
6450 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6451 we would be spanning bytes or if the position is not a constant and the
6452 length is not 1. In all other cases, we would only be going outside
6453 our object in cases when an original shift would have been
6455 if (! spans_byte && MEM_P (inner)
6456 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6457 || (pos_rtx != 0 && len != 1)))
6460 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6461 and the mode for the result. */
6462 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6464 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6465 pos_mode = mode_for_extraction (EP_insv, 2);
6466 extraction_mode = mode_for_extraction (EP_insv, 3);
6469 if (! in_dest && unsignedp
6470 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6472 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6473 pos_mode = mode_for_extraction (EP_extzv, 3);
6474 extraction_mode = mode_for_extraction (EP_extzv, 0);
6477 if (! in_dest && ! unsignedp
6478 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6480 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6481 pos_mode = mode_for_extraction (EP_extv, 3);
6482 extraction_mode = mode_for_extraction (EP_extv, 0);
6485 /* Never narrow an object, since that might not be safe. */
6487 if (mode != VOIDmode
6488 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6489 extraction_mode = mode;
6491 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6492 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6493 pos_mode = GET_MODE (pos_rtx);
6495 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6496 if we have to change the mode of memory and cannot, the desired mode is
6499 wanted_inner_mode = wanted_inner_reg_mode;
6500 else if (inner_mode != wanted_inner_mode
6501 && (mode_dependent_address_p (XEXP (inner, 0))
6502 || MEM_VOLATILE_P (inner)))
6503 wanted_inner_mode = extraction_mode;
6507 if (BITS_BIG_ENDIAN)
6509 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6510 BITS_BIG_ENDIAN style. If position is constant, compute new
6511 position. Otherwise, build subtraction.
6512 Note that POS is relative to the mode of the original argument.
6513 If it's a MEM we need to recompute POS relative to that.
6514 However, if we're extracting from (or inserting into) a register,
6515 we want to recompute POS relative to wanted_inner_mode. */
6516 int width = (MEM_P (inner)
6517 ? GET_MODE_BITSIZE (is_mode)
6518 : GET_MODE_BITSIZE (wanted_inner_mode));
6521 pos = width - len - pos;
6524 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6525 /* POS may be less than 0 now, but we check for that below.
6526 Note that it can only be less than 0 if !MEM_P (inner). */
6529 /* If INNER has a wider mode, make it smaller. If this is a constant
6530 extract, try to adjust the byte to point to the byte containing
6532 if (wanted_inner_mode != VOIDmode
6533 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6535 && (inner_mode == wanted_inner_mode
6536 || (! mode_dependent_address_p (XEXP (inner, 0))
6537 && ! MEM_VOLATILE_P (inner))))))
6541 /* The computations below will be correct if the machine is big
6542 endian in both bits and bytes or little endian in bits and bytes.
6543 If it is mixed, we must adjust. */
6545 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6546 adjust OFFSET to compensate. */
6547 if (BYTES_BIG_ENDIAN
6549 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6550 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6552 /* If this is a constant position, we can move to the desired byte.
6553 Be careful not to go beyond the original object and maintain the
6554 natural alignment of the memory. */
6557 enum machine_mode bfmode = smallest_mode_for_size (len, MODE_INT);
6558 offset += (pos / GET_MODE_BITSIZE (bfmode)) * GET_MODE_SIZE (bfmode);
6559 pos %= GET_MODE_BITSIZE (bfmode);
6562 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6564 && is_mode != wanted_inner_mode)
6565 offset = (GET_MODE_SIZE (is_mode)
6566 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6568 if (offset != 0 || inner_mode != wanted_inner_mode)
6569 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6572 /* If INNER is not memory, we can always get it into the proper mode. If we
6573 are changing its mode, POS must be a constant and smaller than the size
6575 else if (!MEM_P (inner))
6577 if (GET_MODE (inner) != wanted_inner_mode
6579 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6585 inner = force_to_mode (inner, wanted_inner_mode,
6587 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6588 ? ~(unsigned HOST_WIDE_INT) 0
6589 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6594 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6595 have to zero extend. Otherwise, we can just use a SUBREG. */
6597 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6599 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6601 /* If we know that no extraneous bits are set, and that the high
6602 bit is not set, convert extraction to cheaper one - either
6603 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6605 if (flag_expensive_optimizations
6606 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6607 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6608 & ~(((unsigned HOST_WIDE_INT)
6609 GET_MODE_MASK (GET_MODE (pos_rtx)))
6613 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6615 /* Prefer ZERO_EXTENSION, since it gives more information to
6617 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6622 else if (pos_rtx != 0
6623 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6624 pos_rtx = gen_lowpart (pos_mode, pos_rtx);
6626 /* Make POS_RTX unless we already have it and it is correct. If we don't
6627 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6629 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6630 pos_rtx = orig_pos_rtx;
6632 else if (pos_rtx == 0)
6633 pos_rtx = GEN_INT (pos);
6635 /* Make the required operation. See if we can use existing rtx. */
6636 new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6637 extraction_mode, inner, GEN_INT (len), pos_rtx);
6639 new = gen_lowpart (mode, new);
6644 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6645 with any other operations in X. Return X without that shift if so. */
6648 extract_left_shift (rtx x, int count)
6650 enum rtx_code code = GET_CODE (x);
6651 enum machine_mode mode = GET_MODE (x);
6657 /* This is the shift itself. If it is wide enough, we will return
6658 either the value being shifted if the shift count is equal to
6659 COUNT or a shift for the difference. */
6660 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6661 && INTVAL (XEXP (x, 1)) >= count)
6662 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6663 INTVAL (XEXP (x, 1)) - count);
6667 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6668 return simplify_gen_unary (code, mode, tem, mode);
6672 case PLUS: case IOR: case XOR: case AND:
6673 /* If we can safely shift this constant and we find the inner shift,
6674 make a new operation. */
6675 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6676 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6677 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6678 return simplify_gen_binary (code, mode, tem,
6679 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6690 /* Look at the expression rooted at X. Look for expressions
6691 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6692 Form these expressions.
6694 Return the new rtx, usually just X.
6696 Also, for machines like the VAX that don't have logical shift insns,
6697 try to convert logical to arithmetic shift operations in cases where
6698 they are equivalent. This undoes the canonicalizations to logical
6699 shifts done elsewhere.
6701 We try, as much as possible, to re-use rtl expressions to save memory.
6703 IN_CODE says what kind of expression we are processing. Normally, it is
6704 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6705 being kludges), it is MEM. When processing the arguments of a comparison
6706 or a COMPARE against zero, it is COMPARE. */
6709 make_compound_operation (rtx x, enum rtx_code in_code)
6711 enum rtx_code code = GET_CODE (x);
6712 enum machine_mode mode = GET_MODE (x);
6713 int mode_width = GET_MODE_BITSIZE (mode);
6715 enum rtx_code next_code;
6721 /* Select the code to be used in recursive calls. Once we are inside an
6722 address, we stay there. If we have a comparison, set to COMPARE,
6723 but once inside, go back to our default of SET. */
6725 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6726 : ((code == COMPARE || COMPARISON_P (x))
6727 && XEXP (x, 1) == const0_rtx) ? COMPARE
6728 : in_code == COMPARE ? SET : in_code);
6730 /* Process depending on the code of this operation. If NEW is set
6731 nonzero, it will be returned. */
6736 /* Convert shifts by constants into multiplications if inside
6738 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6739 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6740 && INTVAL (XEXP (x, 1)) >= 0)
6742 new = make_compound_operation (XEXP (x, 0), next_code);
6743 new = gen_rtx_MULT (mode, new,
6744 GEN_INT ((HOST_WIDE_INT) 1
6745 << INTVAL (XEXP (x, 1))));
6750 /* If the second operand is not a constant, we can't do anything
6752 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6755 /* If the constant is a power of two minus one and the first operand
6756 is a logical right shift, make an extraction. */
6757 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6758 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6760 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6761 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6762 0, in_code == COMPARE);
6765 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6766 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6767 && subreg_lowpart_p (XEXP (x, 0))
6768 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6769 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6771 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6773 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6774 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6775 0, in_code == COMPARE);
6777 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6778 else if ((GET_CODE (XEXP (x, 0)) == XOR
6779 || GET_CODE (XEXP (x, 0)) == IOR)
6780 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6781 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6782 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6784 /* Apply the distributive law, and then try to make extractions. */
6785 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6786 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6788 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6790 new = make_compound_operation (new, in_code);
6793 /* If we are have (and (rotate X C) M) and C is larger than the number
6794 of bits in M, this is an extraction. */
6796 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6797 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6798 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6799 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6801 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6802 new = make_extraction (mode, new,
6803 (GET_MODE_BITSIZE (mode)
6804 - INTVAL (XEXP (XEXP (x, 0), 1))),
6805 NULL_RTX, i, 1, 0, in_code == COMPARE);
6808 /* On machines without logical shifts, if the operand of the AND is
6809 a logical shift and our mask turns off all the propagated sign
6810 bits, we can replace the logical shift with an arithmetic shift. */
6811 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6812 && !have_insn_for (LSHIFTRT, mode)
6813 && have_insn_for (ASHIFTRT, mode)
6814 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6815 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6816 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6817 && mode_width <= HOST_BITS_PER_WIDE_INT)
6819 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6821 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6822 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6824 gen_rtx_ASHIFTRT (mode,
6825 make_compound_operation
6826 (XEXP (XEXP (x, 0), 0), next_code),
6827 XEXP (XEXP (x, 0), 1)));
6830 /* If the constant is one less than a power of two, this might be
6831 representable by an extraction even if no shift is present.
6832 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6833 we are in a COMPARE. */
6834 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6835 new = make_extraction (mode,
6836 make_compound_operation (XEXP (x, 0),
6838 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6840 /* If we are in a comparison and this is an AND with a power of two,
6841 convert this into the appropriate bit extract. */
6842 else if (in_code == COMPARE
6843 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6844 new = make_extraction (mode,
6845 make_compound_operation (XEXP (x, 0),
6847 i, NULL_RTX, 1, 1, 0, 1);
6852 /* If the sign bit is known to be zero, replace this with an
6853 arithmetic shift. */
6854 if (have_insn_for (ASHIFTRT, mode)
6855 && ! have_insn_for (LSHIFTRT, mode)
6856 && mode_width <= HOST_BITS_PER_WIDE_INT
6857 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6859 new = gen_rtx_ASHIFTRT (mode,
6860 make_compound_operation (XEXP (x, 0),
6866 /* ... fall through ... */
6872 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6873 this is a SIGN_EXTRACT. */
6874 if (GET_CODE (rhs) == CONST_INT
6875 && GET_CODE (lhs) == ASHIFT
6876 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6877 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6879 new = make_compound_operation (XEXP (lhs, 0), next_code);
6880 new = make_extraction (mode, new,
6881 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6882 NULL_RTX, mode_width - INTVAL (rhs),
6883 code == LSHIFTRT, 0, in_code == COMPARE);
6887 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6888 If so, try to merge the shifts into a SIGN_EXTEND. We could
6889 also do this for some cases of SIGN_EXTRACT, but it doesn't
6890 seem worth the effort; the case checked for occurs on Alpha. */
6893 && ! (GET_CODE (lhs) == SUBREG
6894 && (OBJECT_P (SUBREG_REG (lhs))))
6895 && GET_CODE (rhs) == CONST_INT
6896 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6897 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6898 new = make_extraction (mode, make_compound_operation (new, next_code),
6899 0, NULL_RTX, mode_width - INTVAL (rhs),
6900 code == LSHIFTRT, 0, in_code == COMPARE);
6905 /* Call ourselves recursively on the inner expression. If we are
6906 narrowing the object and it has a different RTL code from
6907 what it originally did, do this SUBREG as a force_to_mode. */
6909 tem = make_compound_operation (SUBREG_REG (x), in_code);
6913 simplified = simplify_subreg (GET_MODE (x), tem, GET_MODE (tem),
6919 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6920 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6921 && subreg_lowpart_p (x))
6923 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6926 /* If we have something other than a SUBREG, we might have
6927 done an expansion, so rerun ourselves. */
6928 if (GET_CODE (newer) != SUBREG)
6929 newer = make_compound_operation (newer, in_code);
6945 x = gen_lowpart (mode, new);
6946 code = GET_CODE (x);
6949 /* Now recursively process each operand of this operation. */
6950 fmt = GET_RTX_FORMAT (code);
6951 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6954 new = make_compound_operation (XEXP (x, i), next_code);
6955 SUBST (XEXP (x, i), new);
6961 /* Given M see if it is a value that would select a field of bits
6962 within an item, but not the entire word. Return -1 if not.
6963 Otherwise, return the starting position of the field, where 0 is the
6966 *PLEN is set to the length of the field. */
6969 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
6971 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6972 int pos = exact_log2 (m & -m);
6976 /* Now shift off the low-order zero bits and see if we have a
6977 power of two minus 1. */
6978 len = exact_log2 ((m >> pos) + 1);
6987 /* See if X can be simplified knowing that we will only refer to it in
6988 MODE and will only refer to those bits that are nonzero in MASK.
6989 If other bits are being computed or if masking operations are done
6990 that select a superset of the bits in MASK, they can sometimes be
6993 Return a possibly simplified expression, but always convert X to
6994 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6996 Also, if REG is nonzero and X is a register equal in value to REG,
6999 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
7000 are all off in X. This is used when X will be complemented, by either
7001 NOT, NEG, or XOR. */
7004 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
7005 rtx reg, int just_select)
7007 enum rtx_code code = GET_CODE (x);
7008 int next_select = just_select || code == XOR || code == NOT || code == NEG;
7009 enum machine_mode op_mode;
7010 unsigned HOST_WIDE_INT fuller_mask, nonzero;
7013 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
7014 code below will do the wrong thing since the mode of such an
7015 expression is VOIDmode.
7017 Also do nothing if X is a CLOBBER; this can happen if X was
7018 the return value from a call to gen_lowpart. */
7019 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
7022 /* We want to perform the operation is its present mode unless we know
7023 that the operation is valid in MODE, in which case we do the operation
7025 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
7026 && have_insn_for (code, mode))
7027 ? mode : GET_MODE (x));
7029 /* It is not valid to do a right-shift in a narrower mode
7030 than the one it came in with. */
7031 if ((code == LSHIFTRT || code == ASHIFTRT)
7032 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
7033 op_mode = GET_MODE (x);
7035 /* Truncate MASK to fit OP_MODE. */
7037 mask &= GET_MODE_MASK (op_mode);
7039 /* When we have an arithmetic operation, or a shift whose count we
7040 do not know, we need to assume that all bits up to the highest-order
7041 bit in MASK will be needed. This is how we form such a mask. */
7042 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
7043 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
7045 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
7048 /* Determine what bits of X are guaranteed to be (non)zero. */
7049 nonzero = nonzero_bits (x, mode);
7051 /* If none of the bits in X are needed, return a zero. */
7052 if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
7055 /* If X is a CONST_INT, return a new one. Do this here since the
7056 test below will fail. */
7057 if (GET_CODE (x) == CONST_INT)
7059 if (SCALAR_INT_MODE_P (mode))
7060 return gen_int_mode (INTVAL (x) & mask, mode);
7063 x = GEN_INT (INTVAL (x) & mask);
7064 return gen_lowpart_common (mode, x);
7068 /* If X is narrower than MODE and we want all the bits in X's mode, just
7069 get X in the proper mode. */
7070 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
7071 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
7072 return gen_lowpart (mode, x);
7077 /* If X is a (clobber (const_int)), return it since we know we are
7078 generating something that won't match. */
7082 /* X is a (use (mem ..)) that was made from a bit-field extraction that
7083 spanned the boundary of the MEM. If we are now masking so it is
7084 within that boundary, we don't need the USE any more. */
7085 if (! BITS_BIG_ENDIAN
7086 && (mask & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
7087 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7094 x = expand_compound_operation (x);
7095 if (GET_CODE (x) != code)
7096 return force_to_mode (x, mode, mask, reg, next_select);
7100 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
7101 || rtx_equal_p (reg, get_last_value (x))))
7106 if (subreg_lowpart_p (x)
7107 /* We can ignore the effect of this SUBREG if it narrows the mode or
7108 if the constant masks to zero all the bits the mode doesn't
7110 && ((GET_MODE_SIZE (GET_MODE (x))
7111 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7113 & GET_MODE_MASK (GET_MODE (x))
7114 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
7115 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
7119 /* If this is an AND with a constant, convert it into an AND
7120 whose constant is the AND of that constant with MASK. If it
7121 remains an AND of MASK, delete it since it is redundant. */
7123 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
7125 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
7126 mask & INTVAL (XEXP (x, 1)));
7128 /* If X is still an AND, see if it is an AND with a mask that
7129 is just some low-order bits. If so, and it is MASK, we don't
7132 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
7133 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
7137 /* If it remains an AND, try making another AND with the bits
7138 in the mode mask that aren't in MASK turned on. If the
7139 constant in the AND is wide enough, this might make a
7140 cheaper constant. */
7142 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
7143 && GET_MODE_MASK (GET_MODE (x)) != mask
7144 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
7146 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
7147 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
7148 int width = GET_MODE_BITSIZE (GET_MODE (x));
7151 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
7152 number, sign extend it. */
7153 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
7154 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7155 cval |= (HOST_WIDE_INT) -1 << width;
7157 y = simplify_gen_binary (AND, GET_MODE (x),
7158 XEXP (x, 0), GEN_INT (cval));
7159 if (rtx_cost (y, SET) < rtx_cost (x, SET))
7169 /* In (and (plus FOO C1) M), if M is a mask that just turns off
7170 low-order bits (as in an alignment operation) and FOO is already
7171 aligned to that boundary, mask C1 to that boundary as well.
7172 This may eliminate that PLUS and, later, the AND. */
7175 unsigned int width = GET_MODE_BITSIZE (mode);
7176 unsigned HOST_WIDE_INT smask = mask;
7178 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
7179 number, sign extend it. */
7181 if (width < HOST_BITS_PER_WIDE_INT
7182 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7183 smask |= (HOST_WIDE_INT) -1 << width;
7185 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7186 && exact_log2 (- smask) >= 0
7187 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
7188 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
7189 return force_to_mode (plus_constant (XEXP (x, 0),
7190 (INTVAL (XEXP (x, 1)) & smask)),
7191 mode, smask, reg, next_select);
7194 /* ... fall through ... */
7197 /* For PLUS, MINUS and MULT, we need any bits less significant than the
7198 most significant bit in MASK since carries from those bits will
7199 affect the bits we are interested in. */
7204 /* If X is (minus C Y) where C's least set bit is larger than any bit
7205 in the mask, then we may replace with (neg Y). */
7206 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7207 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
7208 & -INTVAL (XEXP (x, 0))))
7211 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
7213 return force_to_mode (x, mode, mask, reg, next_select);
7216 /* Similarly, if C contains every bit in the fuller_mask, then we may
7217 replace with (not Y). */
7218 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7219 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
7220 == INTVAL (XEXP (x, 0))))
7222 x = simplify_gen_unary (NOT, GET_MODE (x),
7223 XEXP (x, 1), GET_MODE (x));
7224 return force_to_mode (x, mode, mask, reg, next_select);
7232 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7233 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7234 operation which may be a bitfield extraction. Ensure that the
7235 constant we form is not wider than the mode of X. */
7237 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7238 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7239 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7240 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7241 && GET_CODE (XEXP (x, 1)) == CONST_INT
7242 && ((INTVAL (XEXP (XEXP (x, 0), 1))
7243 + floor_log2 (INTVAL (XEXP (x, 1))))
7244 < GET_MODE_BITSIZE (GET_MODE (x)))
7245 && (INTVAL (XEXP (x, 1))
7246 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7248 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7249 << INTVAL (XEXP (XEXP (x, 0), 1)));
7250 temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
7251 XEXP (XEXP (x, 0), 0), temp);
7252 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
7253 XEXP (XEXP (x, 0), 1));
7254 return force_to_mode (x, mode, mask, reg, next_select);
7258 /* For most binary operations, just propagate into the operation and
7259 change the mode if we have an operation of that mode. */
7261 op0 = gen_lowpart (op_mode,
7262 force_to_mode (XEXP (x, 0), mode, mask,
7264 op1 = gen_lowpart (op_mode,
7265 force_to_mode (XEXP (x, 1), mode, mask,
7268 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7269 x = simplify_gen_binary (code, op_mode, op0, op1);
7273 /* For left shifts, do the same, but just for the first operand.
7274 However, we cannot do anything with shifts where we cannot
7275 guarantee that the counts are smaller than the size of the mode
7276 because such a count will have a different meaning in a
7279 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
7280 && INTVAL (XEXP (x, 1)) >= 0
7281 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7282 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7283 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7284 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7287 /* If the shift count is a constant and we can do arithmetic in
7288 the mode of the shift, refine which bits we need. Otherwise, use the
7289 conservative form of the mask. */
7290 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7291 && INTVAL (XEXP (x, 1)) >= 0
7292 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7293 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7294 mask >>= INTVAL (XEXP (x, 1));
7298 op0 = gen_lowpart (op_mode,
7299 force_to_mode (XEXP (x, 0), op_mode,
7300 mask, reg, next_select));
7302 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7303 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
7307 /* Here we can only do something if the shift count is a constant,
7308 this shift constant is valid for the host, and we can do arithmetic
7311 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7312 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7313 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7315 rtx inner = XEXP (x, 0);
7316 unsigned HOST_WIDE_INT inner_mask;
7318 /* Select the mask of the bits we need for the shift operand. */
7319 inner_mask = mask << INTVAL (XEXP (x, 1));
7321 /* We can only change the mode of the shift if we can do arithmetic
7322 in the mode of the shift and INNER_MASK is no wider than the
7323 width of X's mode. */
7324 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
7325 op_mode = GET_MODE (x);
7327 inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select);
7329 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7330 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7333 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7334 shift and AND produces only copies of the sign bit (C2 is one less
7335 than a power of two), we can do this with just a shift. */
7337 if (GET_CODE (x) == LSHIFTRT
7338 && GET_CODE (XEXP (x, 1)) == CONST_INT
7339 /* The shift puts one of the sign bit copies in the least significant
7341 && ((INTVAL (XEXP (x, 1))
7342 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7343 >= GET_MODE_BITSIZE (GET_MODE (x)))
7344 && exact_log2 (mask + 1) >= 0
7345 /* Number of bits left after the shift must be more than the mask
7347 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7348 <= GET_MODE_BITSIZE (GET_MODE (x)))
7349 /* Must be more sign bit copies than the mask needs. */
7350 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7351 >= exact_log2 (mask + 1)))
7352 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7353 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7354 - exact_log2 (mask + 1)));
7359 /* If we are just looking for the sign bit, we don't need this shift at
7360 all, even if it has a variable count. */
7361 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7362 && (mask == ((unsigned HOST_WIDE_INT) 1
7363 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7364 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7366 /* If this is a shift by a constant, get a mask that contains those bits
7367 that are not copies of the sign bit. We then have two cases: If
7368 MASK only includes those bits, this can be a logical shift, which may
7369 allow simplifications. If MASK is a single-bit field not within
7370 those bits, we are requesting a copy of the sign bit and hence can
7371 shift the sign bit to the appropriate location. */
7373 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7374 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7378 /* If the considered data is wider than HOST_WIDE_INT, we can't
7379 represent a mask for all its bits in a single scalar.
7380 But we only care about the lower bits, so calculate these. */
7382 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7384 nonzero = ~(HOST_WIDE_INT) 0;
7386 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7387 is the number of bits a full-width mask would have set.
7388 We need only shift if these are fewer than nonzero can
7389 hold. If not, we must keep all bits set in nonzero. */
7391 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7392 < HOST_BITS_PER_WIDE_INT)
7393 nonzero >>= INTVAL (XEXP (x, 1))
7394 + HOST_BITS_PER_WIDE_INT
7395 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7399 nonzero = GET_MODE_MASK (GET_MODE (x));
7400 nonzero >>= INTVAL (XEXP (x, 1));
7403 if ((mask & ~nonzero) == 0
7404 || (i = exact_log2 (mask)) >= 0)
7406 x = simplify_shift_const
7407 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7408 i < 0 ? INTVAL (XEXP (x, 1))
7409 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7411 if (GET_CODE (x) != ASHIFTRT)
7412 return force_to_mode (x, mode, mask, reg, next_select);
7416 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7417 even if the shift count isn't a constant. */
7419 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7420 XEXP (x, 0), XEXP (x, 1));
7424 /* If this is a zero- or sign-extension operation that just affects bits
7425 we don't care about, remove it. Be sure the call above returned
7426 something that is still a shift. */
7428 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7429 && GET_CODE (XEXP (x, 1)) == CONST_INT
7430 && INTVAL (XEXP (x, 1)) >= 0
7431 && (INTVAL (XEXP (x, 1))
7432 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7433 && GET_CODE (XEXP (x, 0)) == ASHIFT
7434 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7435 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7442 /* If the shift count is constant and we can do computations
7443 in the mode of X, compute where the bits we care about are.
7444 Otherwise, we can't do anything. Don't change the mode of
7445 the shift or propagate MODE into the shift, though. */
7446 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7447 && INTVAL (XEXP (x, 1)) >= 0)
7449 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7450 GET_MODE (x), GEN_INT (mask),
7452 if (temp && GET_CODE (temp) == CONST_INT)
7454 force_to_mode (XEXP (x, 0), GET_MODE (x),
7455 INTVAL (temp), reg, next_select));
7460 /* If we just want the low-order bit, the NEG isn't needed since it
7461 won't change the low-order bit. */
7463 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
7465 /* We need any bits less significant than the most significant bit in
7466 MASK since carries from those bits will affect the bits we are
7472 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7473 same as the XOR case above. Ensure that the constant we form is not
7474 wider than the mode of X. */
7476 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7477 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7478 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7479 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7480 < GET_MODE_BITSIZE (GET_MODE (x)))
7481 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7483 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
7485 temp = simplify_gen_binary (XOR, GET_MODE (x),
7486 XEXP (XEXP (x, 0), 0), temp);
7487 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7488 temp, XEXP (XEXP (x, 0), 1));
7490 return force_to_mode (x, mode, mask, reg, next_select);
7493 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7494 use the full mask inside the NOT. */
7498 op0 = gen_lowpart (op_mode,
7499 force_to_mode (XEXP (x, 0), mode, mask,
7501 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7502 x = simplify_gen_unary (code, op_mode, op0, op_mode);
7506 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7507 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7508 which is equal to STORE_FLAG_VALUE. */
7509 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7510 && GET_MODE (XEXP (x, 0)) == mode
7511 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7512 && (nonzero_bits (XEXP (x, 0), mode)
7513 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
7514 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7519 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7520 written in a narrower mode. We play it safe and do not do so. */
7523 gen_lowpart (GET_MODE (x),
7524 force_to_mode (XEXP (x, 1), mode,
7525 mask, reg, next_select)));
7527 gen_lowpart (GET_MODE (x),
7528 force_to_mode (XEXP (x, 2), mode,
7529 mask, reg, next_select)));
7536 /* Ensure we return a value of the proper mode. */
7537 return gen_lowpart (mode, x);
7540 /* Return nonzero if X is an expression that has one of two values depending on
7541 whether some other value is zero or nonzero. In that case, we return the
7542 value that is being tested, *PTRUE is set to the value if the rtx being
7543 returned has a nonzero value, and *PFALSE is set to the other alternative.
7545 If we return zero, we set *PTRUE and *PFALSE to X. */
7548 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
7550 enum machine_mode mode = GET_MODE (x);
7551 enum rtx_code code = GET_CODE (x);
7552 rtx cond0, cond1, true0, true1, false0, false1;
7553 unsigned HOST_WIDE_INT nz;
7555 /* If we are comparing a value against zero, we are done. */
7556 if ((code == NE || code == EQ)
7557 && XEXP (x, 1) == const0_rtx)
7559 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7560 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7564 /* If this is a unary operation whose operand has one of two values, apply
7565 our opcode to compute those values. */
7566 else if (UNARY_P (x)
7567 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7569 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7570 *pfalse = simplify_gen_unary (code, mode, false0,
7571 GET_MODE (XEXP (x, 0)));
7575 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7576 make can't possibly match and would suppress other optimizations. */
7577 else if (code == COMPARE)
7580 /* If this is a binary operation, see if either side has only one of two
7581 values. If either one does or if both do and they are conditional on
7582 the same value, compute the new true and false values. */
7583 else if (BINARY_P (x))
7585 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7586 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7588 if ((cond0 != 0 || cond1 != 0)
7589 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7591 /* If if_then_else_cond returned zero, then true/false are the
7592 same rtl. We must copy one of them to prevent invalid rtl
7595 true0 = copy_rtx (true0);
7596 else if (cond1 == 0)
7597 true1 = copy_rtx (true1);
7599 if (COMPARISON_P (x))
7601 *ptrue = simplify_gen_relational (code, mode, VOIDmode,
7603 *pfalse = simplify_gen_relational (code, mode, VOIDmode,
7608 *ptrue = simplify_gen_binary (code, mode, true0, true1);
7609 *pfalse = simplify_gen_binary (code, mode, false0, false1);
7612 return cond0 ? cond0 : cond1;
7615 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7616 operands is zero when the other is nonzero, and vice-versa,
7617 and STORE_FLAG_VALUE is 1 or -1. */
7619 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7620 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7622 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7624 rtx op0 = XEXP (XEXP (x, 0), 1);
7625 rtx op1 = XEXP (XEXP (x, 1), 1);
7627 cond0 = XEXP (XEXP (x, 0), 0);
7628 cond1 = XEXP (XEXP (x, 1), 0);
7630 if (COMPARISON_P (cond0)
7631 && COMPARISON_P (cond1)
7632 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7633 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7634 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7635 || ((swap_condition (GET_CODE (cond0))
7636 == reversed_comparison_code (cond1, NULL))
7637 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7638 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7639 && ! side_effects_p (x))
7641 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
7642 *pfalse = simplify_gen_binary (MULT, mode,
7644 ? simplify_gen_unary (NEG, mode,
7652 /* Similarly for MULT, AND and UMIN, except that for these the result
7654 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7655 && (code == MULT || code == AND || code == UMIN)
7656 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7658 cond0 = XEXP (XEXP (x, 0), 0);
7659 cond1 = XEXP (XEXP (x, 1), 0);
7661 if (COMPARISON_P (cond0)
7662 && COMPARISON_P (cond1)
7663 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7664 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7665 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7666 || ((swap_condition (GET_CODE (cond0))
7667 == reversed_comparison_code (cond1, NULL))
7668 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7669 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7670 && ! side_effects_p (x))
7672 *ptrue = *pfalse = const0_rtx;
7678 else if (code == IF_THEN_ELSE)
7680 /* If we have IF_THEN_ELSE already, extract the condition and
7681 canonicalize it if it is NE or EQ. */
7682 cond0 = XEXP (x, 0);
7683 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7684 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7685 return XEXP (cond0, 0);
7686 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7688 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7689 return XEXP (cond0, 0);
7695 /* If X is a SUBREG, we can narrow both the true and false values
7696 if the inner expression, if there is a condition. */
7697 else if (code == SUBREG
7698 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7701 true0 = simplify_gen_subreg (mode, true0,
7702 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7703 false0 = simplify_gen_subreg (mode, false0,
7704 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7705 if (true0 && false0)
7713 /* If X is a constant, this isn't special and will cause confusions
7714 if we treat it as such. Likewise if it is equivalent to a constant. */
7715 else if (CONSTANT_P (x)
7716 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7719 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7720 will be least confusing to the rest of the compiler. */
7721 else if (mode == BImode)
7723 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7727 /* If X is known to be either 0 or -1, those are the true and
7728 false values when testing X. */
7729 else if (x == constm1_rtx || x == const0_rtx
7730 || (mode != VOIDmode
7731 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7733 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7737 /* Likewise for 0 or a single bit. */
7738 else if (SCALAR_INT_MODE_P (mode)
7739 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7740 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7742 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7746 /* Otherwise fail; show no condition with true and false values the same. */
7747 *ptrue = *pfalse = x;
7751 /* Return the value of expression X given the fact that condition COND
7752 is known to be true when applied to REG as its first operand and VAL
7753 as its second. X is known to not be shared and so can be modified in
7756 We only handle the simplest cases, and specifically those cases that
7757 arise with IF_THEN_ELSE expressions. */
7760 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
7762 enum rtx_code code = GET_CODE (x);
7767 if (side_effects_p (x))
7770 /* If either operand of the condition is a floating point value,
7771 then we have to avoid collapsing an EQ comparison. */
7773 && rtx_equal_p (x, reg)
7774 && ! FLOAT_MODE_P (GET_MODE (x))
7775 && ! FLOAT_MODE_P (GET_MODE (val)))
7778 if (cond == UNEQ && rtx_equal_p (x, reg))
7781 /* If X is (abs REG) and we know something about REG's relationship
7782 with zero, we may be able to simplify this. */
7784 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7787 case GE: case GT: case EQ:
7790 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7792 GET_MODE (XEXP (x, 0)));
7797 /* The only other cases we handle are MIN, MAX, and comparisons if the
7798 operands are the same as REG and VAL. */
7800 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
7802 if (rtx_equal_p (XEXP (x, 0), val))
7803 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7805 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7807 if (COMPARISON_P (x))
7809 if (comparison_dominates_p (cond, code))
7810 return const_true_rtx;
7812 code = reversed_comparison_code (x, NULL);
7814 && comparison_dominates_p (cond, code))
7819 else if (code == SMAX || code == SMIN
7820 || code == UMIN || code == UMAX)
7822 int unsignedp = (code == UMIN || code == UMAX);
7824 /* Do not reverse the condition when it is NE or EQ.
7825 This is because we cannot conclude anything about
7826 the value of 'SMAX (x, y)' when x is not equal to y,
7827 but we can when x equals y. */
7828 if ((code == SMAX || code == UMAX)
7829 && ! (cond == EQ || cond == NE))
7830 cond = reverse_condition (cond);
7835 return unsignedp ? x : XEXP (x, 1);
7837 return unsignedp ? x : XEXP (x, 0);
7839 return unsignedp ? XEXP (x, 1) : x;
7841 return unsignedp ? XEXP (x, 0) : x;
7848 else if (code == SUBREG)
7850 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
7851 rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
7853 if (SUBREG_REG (x) != r)
7855 /* We must simplify subreg here, before we lose track of the
7856 original inner_mode. */
7857 new = simplify_subreg (GET_MODE (x), r,
7858 inner_mode, SUBREG_BYTE (x));
7862 SUBST (SUBREG_REG (x), r);
7867 /* We don't have to handle SIGN_EXTEND here, because even in the
7868 case of replacing something with a modeless CONST_INT, a
7869 CONST_INT is already (supposed to be) a valid sign extension for
7870 its narrower mode, which implies it's already properly
7871 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7872 story is different. */
7873 else if (code == ZERO_EXTEND)
7875 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
7876 rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
7878 if (XEXP (x, 0) != r)
7880 /* We must simplify the zero_extend here, before we lose
7881 track of the original inner_mode. */
7882 new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
7887 SUBST (XEXP (x, 0), r);
7893 fmt = GET_RTX_FORMAT (code);
7894 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7897 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7898 else if (fmt[i] == 'E')
7899 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7900 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7907 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7908 assignment as a field assignment. */
7911 rtx_equal_for_field_assignment_p (rtx x, rtx y)
7913 if (x == y || rtx_equal_p (x, y))
7916 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7919 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7920 Note that all SUBREGs of MEM are paradoxical; otherwise they
7921 would have been rewritten. */
7922 if (MEM_P (x) && GET_CODE (y) == SUBREG
7923 && MEM_P (SUBREG_REG (y))
7924 && rtx_equal_p (SUBREG_REG (y),
7925 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
7928 if (MEM_P (y) && GET_CODE (x) == SUBREG
7929 && MEM_P (SUBREG_REG (x))
7930 && rtx_equal_p (SUBREG_REG (x),
7931 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
7934 /* We used to see if get_last_value of X and Y were the same but that's
7935 not correct. In one direction, we'll cause the assignment to have
7936 the wrong destination and in the case, we'll import a register into this
7937 insn that might have already have been dead. So fail if none of the
7938 above cases are true. */
7942 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7943 Return that assignment if so.
7945 We only handle the most common cases. */
7948 make_field_assignment (rtx x)
7950 rtx dest = SET_DEST (x);
7951 rtx src = SET_SRC (x);
7956 unsigned HOST_WIDE_INT len;
7958 enum machine_mode mode;
7960 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7961 a clear of a one-bit field. We will have changed it to
7962 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7965 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7966 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7967 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7968 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7970 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7973 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7977 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7978 && subreg_lowpart_p (XEXP (src, 0))
7979 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7980 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7981 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7982 && GET_CODE (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == CONST_INT
7983 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7984 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7986 assign = make_extraction (VOIDmode, dest, 0,
7987 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7990 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7994 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7996 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7997 && XEXP (XEXP (src, 0), 0) == const1_rtx
7998 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8000 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8003 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
8007 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
8008 SRC is an AND with all bits of that field set, then we can discard
8010 if (GET_CODE (dest) == ZERO_EXTRACT
8011 && GET_CODE (XEXP (dest, 1)) == CONST_INT
8012 && GET_CODE (src) == AND
8013 && GET_CODE (XEXP (src, 1)) == CONST_INT)
8015 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
8016 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
8017 unsigned HOST_WIDE_INT ze_mask;
8019 if (width >= HOST_BITS_PER_WIDE_INT)
8022 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
8024 /* Complete overlap. We can remove the source AND. */
8025 if ((and_mask & ze_mask) == ze_mask)
8026 return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
8028 /* Partial overlap. We can reduce the source AND. */
8029 if ((and_mask & ze_mask) != and_mask)
8031 mode = GET_MODE (src);
8032 src = gen_rtx_AND (mode, XEXP (src, 0),
8033 gen_int_mode (and_mask & ze_mask, mode));
8034 return gen_rtx_SET (VOIDmode, dest, src);
8038 /* The other case we handle is assignments into a constant-position
8039 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
8040 a mask that has all one bits except for a group of zero bits and
8041 OTHER is known to have zeros where C1 has ones, this is such an
8042 assignment. Compute the position and length from C1. Shift OTHER
8043 to the appropriate position, force it to the required mode, and
8044 make the extraction. Check for the AND in both operands. */
8046 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
8049 rhs = expand_compound_operation (XEXP (src, 0));
8050 lhs = expand_compound_operation (XEXP (src, 1));
8052 if (GET_CODE (rhs) == AND
8053 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
8054 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
8055 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
8056 else if (GET_CODE (lhs) == AND
8057 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
8058 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
8059 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
8063 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
8064 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
8065 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
8066 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
8069 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
8073 /* The mode to use for the source is the mode of the assignment, or of
8074 what is inside a possible STRICT_LOW_PART. */
8075 mode = (GET_CODE (assign) == STRICT_LOW_PART
8076 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
8078 /* Shift OTHER right POS places and make it the source, restricting it
8079 to the proper length and mode. */
8081 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
8082 GET_MODE (src), other, pos),
8084 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
8085 ? ~(unsigned HOST_WIDE_INT) 0
8086 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
8089 /* If SRC is masked by an AND that does not make a difference in
8090 the value being stored, strip it. */
8091 if (GET_CODE (assign) == ZERO_EXTRACT
8092 && GET_CODE (XEXP (assign, 1)) == CONST_INT
8093 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
8094 && GET_CODE (src) == AND
8095 && GET_CODE (XEXP (src, 1)) == CONST_INT
8096 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
8097 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
8098 src = XEXP (src, 0);
8100 return gen_rtx_SET (VOIDmode, assign, src);
8103 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
8107 apply_distributive_law (rtx x)
8109 enum rtx_code code = GET_CODE (x);
8110 enum rtx_code inner_code;
8111 rtx lhs, rhs, other;
8114 /* Distributivity is not true for floating point as it can change the
8115 value. So we don't do it unless -funsafe-math-optimizations. */
8116 if (FLOAT_MODE_P (GET_MODE (x))
8117 && ! flag_unsafe_math_optimizations)
8120 /* The outer operation can only be one of the following: */
8121 if (code != IOR && code != AND && code != XOR
8122 && code != PLUS && code != MINUS)
8128 /* If either operand is a primitive we can't do anything, so get out
8130 if (OBJECT_P (lhs) || OBJECT_P (rhs))
8133 lhs = expand_compound_operation (lhs);
8134 rhs = expand_compound_operation (rhs);
8135 inner_code = GET_CODE (lhs);
8136 if (inner_code != GET_CODE (rhs))
8139 /* See if the inner and outer operations distribute. */
8146 /* These all distribute except over PLUS. */
8147 if (code == PLUS || code == MINUS)
8152 if (code != PLUS && code != MINUS)
8157 /* This is also a multiply, so it distributes over everything. */
8161 /* Non-paradoxical SUBREGs distributes over all operations,
8162 provided the inner modes and byte offsets are the same, this
8163 is an extraction of a low-order part, we don't convert an fp
8164 operation to int or vice versa, this is not a vector mode,
8165 and we would not be converting a single-word operation into a
8166 multi-word operation. The latter test is not required, but
8167 it prevents generating unneeded multi-word operations. Some
8168 of the previous tests are redundant given the latter test,
8169 but are retained because they are required for correctness.
8171 We produce the result slightly differently in this case. */
8173 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
8174 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
8175 || ! subreg_lowpart_p (lhs)
8176 || (GET_MODE_CLASS (GET_MODE (lhs))
8177 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
8178 || (GET_MODE_SIZE (GET_MODE (lhs))
8179 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
8180 || VECTOR_MODE_P (GET_MODE (lhs))
8181 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
8184 tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
8185 SUBREG_REG (lhs), SUBREG_REG (rhs));
8186 return gen_lowpart (GET_MODE (x), tem);
8192 /* Set LHS and RHS to the inner operands (A and B in the example
8193 above) and set OTHER to the common operand (C in the example).
8194 There is only one way to do this unless the inner operation is
8196 if (COMMUTATIVE_ARITH_P (lhs)
8197 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
8198 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
8199 else if (COMMUTATIVE_ARITH_P (lhs)
8200 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
8201 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
8202 else if (COMMUTATIVE_ARITH_P (lhs)
8203 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
8204 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
8205 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
8206 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
8210 /* Form the new inner operation, seeing if it simplifies first. */
8211 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
8213 /* There is one exception to the general way of distributing:
8214 (a | c) ^ (b | c) -> (a ^ b) & ~c */
8215 if (code == XOR && inner_code == IOR)
8218 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
8221 /* We may be able to continuing distributing the result, so call
8222 ourselves recursively on the inner operation before forming the
8223 outer operation, which we return. */
8224 return simplify_gen_binary (inner_code, GET_MODE (x),
8225 apply_distributive_law (tem), other);
8228 /* See if X is of the form (* (+ A B) C), and if so convert to
8229 (+ (* A C) (* B C)) and try to simplify.
8231 Most of the time, this results in no change. However, if some of
8232 the operands are the same or inverses of each other, simplifications
8235 For example, (and (ior A B) (not B)) can occur as the result of
8236 expanding a bit field assignment. When we apply the distributive
8237 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8238 which then simplifies to (and (A (not B))).
8240 Note that no checks happen on the validity of applying the inverse
8241 distributive law. This is pointless since we can do it in the
8242 few places where this routine is called.
8244 N is the index of the term that is decomposed (the arithmetic operation,
8245 i.e. (+ A B) in the first example above). !N is the index of the term that
8246 is distributed, i.e. of C in the first example above. */
8248 distribute_and_simplify_rtx (rtx x, int n)
8250 enum machine_mode mode;
8251 enum rtx_code outer_code, inner_code;
8252 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
8254 decomposed = XEXP (x, n);
8255 if (!ARITHMETIC_P (decomposed))
8258 mode = GET_MODE (x);
8259 outer_code = GET_CODE (x);
8260 distributed = XEXP (x, !n);
8262 inner_code = GET_CODE (decomposed);
8263 inner_op0 = XEXP (decomposed, 0);
8264 inner_op1 = XEXP (decomposed, 1);
8266 /* Special case (and (xor B C) (not A)), which is equivalent to
8267 (xor (ior A B) (ior A C)) */
8268 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
8270 distributed = XEXP (distributed, 0);
8276 /* Distribute the second term. */
8277 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
8278 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
8282 /* Distribute the first term. */
8283 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
8284 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
8287 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
8289 if (GET_CODE (tmp) != outer_code
8290 && rtx_cost (tmp, SET) < rtx_cost (x, SET))
8296 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8299 Return an equivalent form, if different from X. Otherwise, return X. If
8300 X is zero, we are to always construct the equivalent form. */
8303 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
8304 unsigned HOST_WIDE_INT constop)
8306 unsigned HOST_WIDE_INT nonzero;
8309 /* Simplify VAROP knowing that we will be only looking at some of the
8312 Note by passing in CONSTOP, we guarantee that the bits not set in
8313 CONSTOP are not significant and will never be examined. We must
8314 ensure that is the case by explicitly masking out those bits
8315 before returning. */
8316 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
8318 /* If VAROP is a CLOBBER, we will fail so return it. */
8319 if (GET_CODE (varop) == CLOBBER)
8322 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8323 to VAROP and return the new constant. */
8324 if (GET_CODE (varop) == CONST_INT)
8325 return gen_int_mode (INTVAL (varop) & constop, mode);
8327 /* See what bits may be nonzero in VAROP. Unlike the general case of
8328 a call to nonzero_bits, here we don't care about bits outside
8331 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8333 /* Turn off all bits in the constant that are known to already be zero.
8334 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8335 which is tested below. */
8339 /* If we don't have any bits left, return zero. */
8343 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8344 a power of two, we can replace this with an ASHIFT. */
8345 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8346 && (i = exact_log2 (constop)) >= 0)
8347 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8349 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8350 or XOR, then try to apply the distributive law. This may eliminate
8351 operations if either branch can be simplified because of the AND.
8352 It may also make some cases more complex, but those cases probably
8353 won't match a pattern either with or without this. */
8355 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8359 apply_distributive_law
8360 (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
8361 simplify_and_const_int (NULL_RTX,
8365 simplify_and_const_int (NULL_RTX,
8370 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
8371 the AND and see if one of the operands simplifies to zero. If so, we
8372 may eliminate it. */
8374 if (GET_CODE (varop) == PLUS
8375 && exact_log2 (constop + 1) >= 0)
8379 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8380 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8381 if (o0 == const0_rtx)
8383 if (o1 == const0_rtx)
8387 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
8388 if we already had one (just check for the simplest cases). */
8389 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
8390 && GET_MODE (XEXP (x, 0)) == mode
8391 && SUBREG_REG (XEXP (x, 0)) == varop)
8392 varop = XEXP (x, 0);
8394 varop = gen_lowpart (mode, varop);
8396 /* If we can't make the SUBREG, try to return what we were given. */
8397 if (GET_CODE (varop) == CLOBBER)
8398 return x ? x : varop;
8400 /* If we are only masking insignificant bits, return VAROP. */
8401 if (constop == nonzero)
8405 /* Otherwise, return an AND. */
8406 constop = trunc_int_for_mode (constop, mode);
8407 /* See how much, if any, of X we can use. */
8408 if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
8409 x = simplify_gen_binary (AND, mode, varop, GEN_INT (constop));
8413 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8414 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
8415 SUBST (XEXP (x, 1), GEN_INT (constop));
8417 SUBST (XEXP (x, 0), varop);
8424 /* Given a REG, X, compute which bits in X can be nonzero.
8425 We don't care about bits outside of those defined in MODE.
8427 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8428 a shift, AND, or zero_extract, we can do better. */
8431 reg_nonzero_bits_for_combine (rtx x, enum machine_mode mode,
8432 rtx known_x ATTRIBUTE_UNUSED,
8433 enum machine_mode known_mode ATTRIBUTE_UNUSED,
8434 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
8435 unsigned HOST_WIDE_INT *nonzero)
8439 /* If X is a register whose nonzero bits value is current, use it.
8440 Otherwise, if X is a register whose value we can find, use that
8441 value. Otherwise, use the previously-computed global nonzero bits
8442 for this register. */
8444 if (reg_stat[REGNO (x)].last_set_value != 0
8445 && (reg_stat[REGNO (x)].last_set_mode == mode
8446 || (GET_MODE_CLASS (reg_stat[REGNO (x)].last_set_mode) == MODE_INT
8447 && GET_MODE_CLASS (mode) == MODE_INT))
8448 && (reg_stat[REGNO (x)].last_set_label == label_tick
8449 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8450 && REG_N_SETS (REGNO (x)) == 1
8451 && ! REGNO_REG_SET_P
8452 (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
8454 && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8456 *nonzero &= reg_stat[REGNO (x)].last_set_nonzero_bits;
8460 tem = get_last_value (x);
8464 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8465 /* If X is narrower than MODE and TEM is a non-negative
8466 constant that would appear negative in the mode of X,
8467 sign-extend it for use in reg_nonzero_bits because some
8468 machines (maybe most) will actually do the sign-extension
8469 and this is the conservative approach.
8471 ??? For 2.5, try to tighten up the MD files in this regard
8472 instead of this kludge. */
8474 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
8475 && GET_CODE (tem) == CONST_INT
8477 && 0 != (INTVAL (tem)
8478 & ((HOST_WIDE_INT) 1
8479 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8480 tem = GEN_INT (INTVAL (tem)
8481 | ((HOST_WIDE_INT) (-1)
8482 << GET_MODE_BITSIZE (GET_MODE (x))));
8486 else if (nonzero_sign_valid && reg_stat[REGNO (x)].nonzero_bits)
8488 unsigned HOST_WIDE_INT mask = reg_stat[REGNO (x)].nonzero_bits;
8490 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
8491 /* We don't know anything about the upper bits. */
8492 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8499 /* Return the number of bits at the high-order end of X that are known to
8500 be equal to the sign bit. X will be used in mode MODE; if MODE is
8501 VOIDmode, X will be used in its own mode. The returned value will always
8502 be between 1 and the number of bits in MODE. */
8505 reg_num_sign_bit_copies_for_combine (rtx x, enum machine_mode mode,
8506 rtx known_x ATTRIBUTE_UNUSED,
8507 enum machine_mode known_mode
8509 unsigned int known_ret ATTRIBUTE_UNUSED,
8510 unsigned int *result)
8514 if (reg_stat[REGNO (x)].last_set_value != 0
8515 && reg_stat[REGNO (x)].last_set_mode == mode
8516 && (reg_stat[REGNO (x)].last_set_label == label_tick
8517 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8518 && REG_N_SETS (REGNO (x)) == 1
8519 && ! REGNO_REG_SET_P
8520 (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
8522 && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8524 *result = reg_stat[REGNO (x)].last_set_sign_bit_copies;
8528 tem = get_last_value (x);
8532 if (nonzero_sign_valid && reg_stat[REGNO (x)].sign_bit_copies != 0
8533 && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
8534 *result = reg_stat[REGNO (x)].sign_bit_copies;
8539 /* Return the number of "extended" bits there are in X, when interpreted
8540 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8541 unsigned quantities, this is the number of high-order zero bits.
8542 For signed quantities, this is the number of copies of the sign bit
8543 minus 1. In both case, this function returns the number of "spare"
8544 bits. For example, if two quantities for which this function returns
8545 at least 1 are added, the addition is known not to overflow.
8547 This function will always return 0 unless called during combine, which
8548 implies that it must be called from a define_split. */
8551 extended_count (rtx x, enum machine_mode mode, int unsignedp)
8553 if (nonzero_sign_valid == 0)
8557 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8558 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
8559 - floor_log2 (nonzero_bits (x, mode)))
8561 : num_sign_bit_copies (x, mode) - 1);
8564 /* This function is called from `simplify_shift_const' to merge two
8565 outer operations. Specifically, we have already found that we need
8566 to perform operation *POP0 with constant *PCONST0 at the outermost
8567 position. We would now like to also perform OP1 with constant CONST1
8568 (with *POP0 being done last).
8570 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8571 the resulting operation. *PCOMP_P is set to 1 if we would need to
8572 complement the innermost operand, otherwise it is unchanged.
8574 MODE is the mode in which the operation will be done. No bits outside
8575 the width of this mode matter. It is assumed that the width of this mode
8576 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8578 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
8579 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8580 result is simply *PCONST0.
8582 If the resulting operation cannot be expressed as one operation, we
8583 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8586 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
8588 enum rtx_code op0 = *pop0;
8589 HOST_WIDE_INT const0 = *pconst0;
8591 const0 &= GET_MODE_MASK (mode);
8592 const1 &= GET_MODE_MASK (mode);
8594 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8598 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
8601 if (op1 == UNKNOWN || op0 == SET)
8604 else if (op0 == UNKNOWN)
8605 op0 = op1, const0 = const1;
8607 else if (op0 == op1)
8631 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8632 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8635 /* If the two constants aren't the same, we can't do anything. The
8636 remaining six cases can all be done. */
8637 else if (const0 != const1)
8645 /* (a & b) | b == b */
8647 else /* op1 == XOR */
8648 /* (a ^ b) | b == a | b */
8654 /* (a & b) ^ b == (~a) & b */
8655 op0 = AND, *pcomp_p = 1;
8656 else /* op1 == IOR */
8657 /* (a | b) ^ b == a & ~b */
8658 op0 = AND, const0 = ~const0;
8663 /* (a | b) & b == b */
8665 else /* op1 == XOR */
8666 /* (a ^ b) & b) == (~a) & b */
8673 /* Check for NO-OP cases. */
8674 const0 &= GET_MODE_MASK (mode);
8676 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8678 else if (const0 == 0 && op0 == AND)
8680 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8684 /* ??? Slightly redundant with the above mask, but not entirely.
8685 Moving this above means we'd have to sign-extend the mode mask
8686 for the final test. */
8687 const0 = trunc_int_for_mode (const0, mode);
8695 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8696 The result of the shift is RESULT_MODE. X, if nonzero, is an expression
8697 that we started with.
8699 The shift is normally computed in the widest mode we find in VAROP, as
8700 long as it isn't a different number of words than RESULT_MODE. Exceptions
8701 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8704 simplify_shift_const (rtx x, enum rtx_code code,
8705 enum machine_mode result_mode, rtx varop,
8708 enum rtx_code orig_code = code;
8711 enum machine_mode mode = result_mode;
8712 enum machine_mode shift_mode, tmode;
8713 unsigned int mode_words
8714 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8715 /* We form (outer_op (code varop count) (outer_const)). */
8716 enum rtx_code outer_op = UNKNOWN;
8717 HOST_WIDE_INT outer_const = 0;
8719 int complement_p = 0;
8722 /* Make sure and truncate the "natural" shift on the way in. We don't
8723 want to do this inside the loop as it makes it more difficult to
8725 if (SHIFT_COUNT_TRUNCATED)
8726 orig_count &= GET_MODE_BITSIZE (mode) - 1;
8728 /* If we were given an invalid count, don't do anything except exactly
8729 what was requested. */
8731 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
8736 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (orig_count));
8741 /* Unless one of the branches of the `if' in this loop does a `continue',
8742 we will `break' the loop after the `if'. */
8746 /* If we have an operand of (clobber (const_int 0)), just return that
8748 if (GET_CODE (varop) == CLOBBER)
8751 /* If we discovered we had to complement VAROP, leave. Making a NOT
8752 here would cause an infinite loop. */
8756 /* Convert ROTATERT to ROTATE. */
8757 if (code == ROTATERT)
8759 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
8761 if (VECTOR_MODE_P (result_mode))
8762 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
8764 count = bitsize - count;
8767 /* We need to determine what mode we will do the shift in. If the
8768 shift is a right shift or a ROTATE, we must always do it in the mode
8769 it was originally done in. Otherwise, we can do it in MODE, the
8770 widest mode encountered. */
8772 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8773 ? result_mode : mode);
8775 /* Handle cases where the count is greater than the size of the mode
8776 minus 1. For ASHIFT, use the size minus one as the count (this can
8777 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8778 take the count modulo the size. For other shifts, the result is
8781 Since these shifts are being produced by the compiler by combining
8782 multiple operations, each of which are defined, we know what the
8783 result is supposed to be. */
8785 if (count > (unsigned int) (GET_MODE_BITSIZE (shift_mode) - 1))
8787 if (code == ASHIFTRT)
8788 count = GET_MODE_BITSIZE (shift_mode) - 1;
8789 else if (code == ROTATE || code == ROTATERT)
8790 count %= GET_MODE_BITSIZE (shift_mode);
8793 /* We can't simply return zero because there may be an
8801 /* An arithmetic right shift of a quantity known to be -1 or 0
8803 if (code == ASHIFTRT
8804 && (num_sign_bit_copies (varop, shift_mode)
8805 == GET_MODE_BITSIZE (shift_mode)))
8811 /* If we are doing an arithmetic right shift and discarding all but
8812 the sign bit copies, this is equivalent to doing a shift by the
8813 bitsize minus one. Convert it into that shift because it will often
8814 allow other simplifications. */
8816 if (code == ASHIFTRT
8817 && (count + num_sign_bit_copies (varop, shift_mode)
8818 >= GET_MODE_BITSIZE (shift_mode)))
8819 count = GET_MODE_BITSIZE (shift_mode) - 1;
8821 /* We simplify the tests below and elsewhere by converting
8822 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8823 `make_compound_operation' will convert it to an ASHIFTRT for
8824 those machines (such as VAX) that don't have an LSHIFTRT. */
8825 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8827 && ((nonzero_bits (varop, shift_mode)
8828 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8832 if (((code == LSHIFTRT
8833 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8834 && !(nonzero_bits (varop, shift_mode) >> count))
8836 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8837 && !((nonzero_bits (varop, shift_mode) << count)
8838 & GET_MODE_MASK (shift_mode))))
8839 && !side_effects_p (varop))
8842 switch (GET_CODE (varop))
8848 new = expand_compound_operation (varop);
8857 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8858 minus the width of a smaller mode, we can do this with a
8859 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8860 if ((code == ASHIFTRT || code == LSHIFTRT)
8861 && ! mode_dependent_address_p (XEXP (varop, 0))
8862 && ! MEM_VOLATILE_P (varop)
8863 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8864 MODE_INT, 1)) != BLKmode)
8866 new = adjust_address_nv (varop, tmode,
8867 BYTES_BIG_ENDIAN ? 0
8868 : count / BITS_PER_UNIT);
8870 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
8871 : ZERO_EXTEND, mode, new);
8878 /* Similar to the case above, except that we can only do this if
8879 the resulting mode is the same as that of the underlying
8880 MEM and adjust the address depending on the *bits* endianness
8881 because of the way that bit-field extract insns are defined. */
8882 if ((code == ASHIFTRT || code == LSHIFTRT)
8883 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8884 MODE_INT, 1)) != BLKmode
8885 && tmode == GET_MODE (XEXP (varop, 0)))
8887 if (BITS_BIG_ENDIAN)
8888 new = XEXP (varop, 0);
8891 new = copy_rtx (XEXP (varop, 0));
8892 SUBST (XEXP (new, 0),
8893 plus_constant (XEXP (new, 0),
8894 count / BITS_PER_UNIT));
8897 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
8898 : ZERO_EXTEND, mode, new);
8905 /* If VAROP is a SUBREG, strip it as long as the inner operand has
8906 the same number of words as what we've seen so far. Then store
8907 the widest mode in MODE. */
8908 if (subreg_lowpart_p (varop)
8909 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8910 > GET_MODE_SIZE (GET_MODE (varop)))
8911 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8912 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8915 varop = SUBREG_REG (varop);
8916 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8917 mode = GET_MODE (varop);
8923 /* Some machines use MULT instead of ASHIFT because MULT
8924 is cheaper. But it is still better on those machines to
8925 merge two shifts into one. */
8926 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8927 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8930 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
8932 GEN_INT (exact_log2 (
8933 INTVAL (XEXP (varop, 1)))));
8939 /* Similar, for when divides are cheaper. */
8940 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8941 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8944 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
8946 GEN_INT (exact_log2 (
8947 INTVAL (XEXP (varop, 1)))));
8953 /* If we are extracting just the sign bit of an arithmetic
8954 right shift, that shift is not needed. However, the sign
8955 bit of a wider mode may be different from what would be
8956 interpreted as the sign bit in a narrower mode, so, if
8957 the result is narrower, don't discard the shift. */
8958 if (code == LSHIFTRT
8959 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
8960 && (GET_MODE_BITSIZE (result_mode)
8961 >= GET_MODE_BITSIZE (GET_MODE (varop))))
8963 varop = XEXP (varop, 0);
8967 /* ... fall through ... */
8972 /* Here we have two nested shifts. The result is usually the
8973 AND of a new shift with a mask. We compute the result below. */
8974 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8975 && INTVAL (XEXP (varop, 1)) >= 0
8976 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
8977 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8978 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8979 && !VECTOR_MODE_P (result_mode))
8981 enum rtx_code first_code = GET_CODE (varop);
8982 unsigned int first_count = INTVAL (XEXP (varop, 1));
8983 unsigned HOST_WIDE_INT mask;
8986 /* We have one common special case. We can't do any merging if
8987 the inner code is an ASHIFTRT of a smaller mode. However, if
8988 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8989 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8990 we can convert it to
8991 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8992 This simplifies certain SIGN_EXTEND operations. */
8993 if (code == ASHIFT && first_code == ASHIFTRT
8994 && count == (unsigned int)
8995 (GET_MODE_BITSIZE (result_mode)
8996 - GET_MODE_BITSIZE (GET_MODE (varop))))
8998 /* C3 has the low-order C1 bits zero. */
9000 mask = (GET_MODE_MASK (mode)
9001 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9003 varop = simplify_and_const_int (NULL_RTX, result_mode,
9004 XEXP (varop, 0), mask);
9005 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9007 count = first_count;
9012 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9013 than C1 high-order bits equal to the sign bit, we can convert
9014 this to either an ASHIFT or an ASHIFTRT depending on the
9017 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9019 if (code == ASHIFTRT && first_code == ASHIFT
9020 && GET_MODE (varop) == shift_mode
9021 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9024 varop = XEXP (varop, 0);
9026 signed_count = count - first_count;
9027 if (signed_count < 0)
9028 count = -signed_count, code = ASHIFT;
9030 count = signed_count;
9035 /* There are some cases we can't do. If CODE is ASHIFTRT,
9036 we can only do this if FIRST_CODE is also ASHIFTRT.
9038 We can't do the case when CODE is ROTATE and FIRST_CODE is
9041 If the mode of this shift is not the mode of the outer shift,
9042 we can't do this if either shift is a right shift or ROTATE.
9044 Finally, we can't do any of these if the mode is too wide
9045 unless the codes are the same.
9047 Handle the case where the shift codes are the same
9050 if (code == first_code)
9052 if (GET_MODE (varop) != result_mode
9053 && (code == ASHIFTRT || code == LSHIFTRT
9057 count += first_count;
9058 varop = XEXP (varop, 0);
9062 if (code == ASHIFTRT
9063 || (code == ROTATE && first_code == ASHIFTRT)
9064 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9065 || (GET_MODE (varop) != result_mode
9066 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9067 || first_code == ROTATE
9068 || code == ROTATE)))
9071 /* To compute the mask to apply after the shift, shift the
9072 nonzero bits of the inner shift the same way the
9073 outer shift will. */
9075 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9078 = simplify_binary_operation (code, result_mode, mask_rtx,
9081 /* Give up if we can't compute an outer operation to use. */
9083 || GET_CODE (mask_rtx) != CONST_INT
9084 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9086 result_mode, &complement_p))
9089 /* If the shifts are in the same direction, we add the
9090 counts. Otherwise, we subtract them. */
9091 signed_count = count;
9092 if ((code == ASHIFTRT || code == LSHIFTRT)
9093 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9094 signed_count += first_count;
9096 signed_count -= first_count;
9098 /* If COUNT is positive, the new shift is usually CODE,
9099 except for the two exceptions below, in which case it is
9100 FIRST_CODE. If the count is negative, FIRST_CODE should
9102 if (signed_count > 0
9103 && ((first_code == ROTATE && code == ASHIFT)
9104 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9105 code = first_code, count = signed_count;
9106 else if (signed_count < 0)
9107 code = first_code, count = -signed_count;
9109 count = signed_count;
9111 varop = XEXP (varop, 0);
9115 /* If we have (A << B << C) for any shift, we can convert this to
9116 (A << C << B). This wins if A is a constant. Only try this if
9117 B is not a constant. */
9119 else if (GET_CODE (varop) == code
9120 && GET_CODE (XEXP (varop, 1)) != CONST_INT
9122 = simplify_binary_operation (code, mode,
9126 varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
9133 /* Make this fit the case below. */
9134 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
9135 GEN_INT (GET_MODE_MASK (mode)));
9141 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9142 with C the size of VAROP - 1 and the shift is logical if
9143 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9144 we have an (le X 0) operation. If we have an arithmetic shift
9145 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9146 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9148 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9149 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9150 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9151 && (code == LSHIFTRT || code == ASHIFTRT)
9152 && count == (unsigned int)
9153 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9154 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9157 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
9160 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9161 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9166 /* If we have (shift (logical)), move the logical to the outside
9167 to allow it to possibly combine with another logical and the
9168 shift to combine with another shift. This also canonicalizes to
9169 what a ZERO_EXTRACT looks like. Also, some machines have
9170 (and (shift)) insns. */
9172 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9173 /* We can't do this if we have (ashiftrt (xor)) and the
9174 constant has its sign bit set in shift_mode. */
9175 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9176 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9178 && (new = simplify_binary_operation (code, result_mode,
9180 GEN_INT (count))) != 0
9181 && GET_CODE (new) == CONST_INT
9182 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9183 INTVAL (new), result_mode, &complement_p))
9185 varop = XEXP (varop, 0);
9189 /* If we can't do that, try to simplify the shift in each arm of the
9190 logical expression, make a new logical expression, and apply
9191 the inverse distributive law. This also can't be done
9192 for some (ashiftrt (xor)). */
9193 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9194 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9195 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9198 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9199 XEXP (varop, 0), count);
9200 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9201 XEXP (varop, 1), count);
9203 varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
9205 varop = apply_distributive_law (varop);
9213 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9214 says that the sign bit can be tested, FOO has mode MODE, C is
9215 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9216 that may be nonzero. */
9217 if (code == LSHIFTRT
9218 && XEXP (varop, 1) == const0_rtx
9219 && GET_MODE (XEXP (varop, 0)) == result_mode
9220 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9221 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9222 && ((STORE_FLAG_VALUE
9223 & ((HOST_WIDE_INT) 1
9224 < (GET_MODE_BITSIZE (result_mode) - 1))))
9225 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9226 && merge_outer_ops (&outer_op, &outer_const, XOR,
9227 (HOST_WIDE_INT) 1, result_mode,
9230 varop = XEXP (varop, 0);
9237 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9238 than the number of bits in the mode is equivalent to A. */
9239 if (code == LSHIFTRT
9240 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9241 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9243 varop = XEXP (varop, 0);
9248 /* NEG commutes with ASHIFT since it is multiplication. Move the
9249 NEG outside to allow shifts to combine. */
9251 && merge_outer_ops (&outer_op, &outer_const, NEG,
9252 (HOST_WIDE_INT) 0, result_mode,
9255 varop = XEXP (varop, 0);
9261 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9262 is one less than the number of bits in the mode is
9263 equivalent to (xor A 1). */
9264 if (code == LSHIFTRT
9265 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9266 && XEXP (varop, 1) == constm1_rtx
9267 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9268 && merge_outer_ops (&outer_op, &outer_const, XOR,
9269 (HOST_WIDE_INT) 1, result_mode,
9273 varop = XEXP (varop, 0);
9277 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9278 that might be nonzero in BAR are those being shifted out and those
9279 bits are known zero in FOO, we can replace the PLUS with FOO.
9280 Similarly in the other operand order. This code occurs when
9281 we are computing the size of a variable-size array. */
9283 if ((code == ASHIFTRT || code == LSHIFTRT)
9284 && count < HOST_BITS_PER_WIDE_INT
9285 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9286 && (nonzero_bits (XEXP (varop, 1), result_mode)
9287 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9289 varop = XEXP (varop, 0);
9292 else if ((code == ASHIFTRT || code == LSHIFTRT)
9293 && count < HOST_BITS_PER_WIDE_INT
9294 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9295 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9297 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9298 & nonzero_bits (XEXP (varop, 1),
9301 varop = XEXP (varop, 1);
9305 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9307 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9308 && (new = simplify_binary_operation (ASHIFT, result_mode,
9310 GEN_INT (count))) != 0
9311 && GET_CODE (new) == CONST_INT
9312 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9313 INTVAL (new), result_mode, &complement_p))
9315 varop = XEXP (varop, 0);
9319 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9320 signbit', and attempt to change the PLUS to an XOR and move it to
9321 the outer operation as is done above in the AND/IOR/XOR case
9322 leg for shift(logical). See details in logical handling above
9323 for reasoning in doing so. */
9324 if (code == LSHIFTRT
9325 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9326 && mode_signbit_p (result_mode, XEXP (varop, 1))
9327 && (new = simplify_binary_operation (code, result_mode,
9329 GEN_INT (count))) != 0
9330 && GET_CODE (new) == CONST_INT
9331 && merge_outer_ops (&outer_op, &outer_const, XOR,
9332 INTVAL (new), result_mode, &complement_p))
9334 varop = XEXP (varop, 0);
9341 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9342 with C the size of VAROP - 1 and the shift is logical if
9343 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9344 we have a (gt X 0) operation. If the shift is arithmetic with
9345 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9346 we have a (neg (gt X 0)) operation. */
9348 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9349 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9350 && count == (unsigned int)
9351 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9352 && (code == LSHIFTRT || code == ASHIFTRT)
9353 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9354 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (varop, 0), 1))
9356 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9359 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9362 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9363 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9370 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9371 if the truncate does not affect the value. */
9372 if (code == LSHIFTRT
9373 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9374 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9375 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9376 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9377 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9379 rtx varop_inner = XEXP (varop, 0);
9382 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9383 XEXP (varop_inner, 0),
9385 (count + INTVAL (XEXP (varop_inner, 1))));
9386 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9399 /* We need to determine what mode to do the shift in. If the shift is
9400 a right shift or ROTATE, we must always do it in the mode it was
9401 originally done in. Otherwise, we can do it in MODE, the widest mode
9402 encountered. The code we care about is that of the shift that will
9403 actually be done, not the shift that was originally requested. */
9405 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9406 ? result_mode : mode);
9408 /* We have now finished analyzing the shift. The result should be
9409 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9410 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9411 to the result of the shift. OUTER_CONST is the relevant constant,
9412 but we must turn off all bits turned off in the shift.
9414 If we were passed a value for X, see if we can use any pieces of
9415 it. If not, make new rtx. */
9417 if (x && GET_RTX_CLASS (GET_CODE (x)) == RTX_BIN_ARITH
9418 && GET_CODE (XEXP (x, 1)) == CONST_INT
9419 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == count)
9420 const_rtx = XEXP (x, 1);
9422 const_rtx = GEN_INT (count);
9424 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
9425 && GET_MODE (XEXP (x, 0)) == shift_mode
9426 && SUBREG_REG (XEXP (x, 0)) == varop)
9427 varop = XEXP (x, 0);
9428 else if (GET_MODE (varop) != shift_mode)
9429 varop = gen_lowpart (shift_mode, varop);
9431 /* If we can't make the SUBREG, try to return what we were given. */
9432 if (GET_CODE (varop) == CLOBBER)
9433 return x ? x : varop;
9435 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9439 x = gen_rtx_fmt_ee (code, shift_mode, varop, const_rtx);
9441 /* If we have an outer operation and we just made a shift, it is
9442 possible that we could have simplified the shift were it not
9443 for the outer operation. So try to do the simplification
9446 if (outer_op != UNKNOWN && GET_CODE (x) == code
9447 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9448 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9449 INTVAL (XEXP (x, 1)));
9451 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9452 turn off all the bits that the shift would have turned off. */
9453 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9454 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9455 GET_MODE_MASK (result_mode) >> orig_count);
9457 /* Do the remainder of the processing in RESULT_MODE. */
9458 x = gen_lowpart (result_mode, x);
9460 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9463 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
9465 if (outer_op != UNKNOWN)
9467 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9468 outer_const = trunc_int_for_mode (outer_const, result_mode);
9470 if (outer_op == AND)
9471 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9472 else if (outer_op == SET)
9474 /* This means that we have determined that the result is
9475 equivalent to a constant. This should be rare. */
9476 if (!side_effects_p (x))
9477 x = GEN_INT (outer_const);
9479 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
9480 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9482 x = simplify_gen_binary (outer_op, result_mode, x,
9483 GEN_INT (outer_const));
9489 /* Like recog, but we receive the address of a pointer to a new pattern.
9490 We try to match the rtx that the pointer points to.
9491 If that fails, we may try to modify or replace the pattern,
9492 storing the replacement into the same pointer object.
9494 Modifications include deletion or addition of CLOBBERs.
9496 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9497 the CLOBBERs are placed.
9499 The value is the final insn code from the pattern ultimately matched,
9503 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
9506 int insn_code_number;
9507 int num_clobbers_to_add = 0;
9510 rtx old_notes, old_pat;
9512 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9513 we use to indicate that something didn't match. If we find such a
9514 thing, force rejection. */
9515 if (GET_CODE (pat) == PARALLEL)
9516 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9517 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9518 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9521 old_pat = PATTERN (insn);
9522 old_notes = REG_NOTES (insn);
9523 PATTERN (insn) = pat;
9524 REG_NOTES (insn) = 0;
9526 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9528 /* If it isn't, there is the possibility that we previously had an insn
9529 that clobbered some register as a side effect, but the combined
9530 insn doesn't need to do that. So try once more without the clobbers
9531 unless this represents an ASM insn. */
9533 if (insn_code_number < 0 && ! check_asm_operands (pat)
9534 && GET_CODE (pat) == PARALLEL)
9538 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9539 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9542 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9546 SUBST_INT (XVECLEN (pat, 0), pos);
9549 pat = XVECEXP (pat, 0, 0);
9551 PATTERN (insn) = pat;
9552 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9554 PATTERN (insn) = old_pat;
9555 REG_NOTES (insn) = old_notes;
9557 /* Recognize all noop sets, these will be killed by followup pass. */
9558 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9559 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9561 /* If we had any clobbers to add, make a new pattern than contains
9562 them. Then check to make sure that all of them are dead. */
9563 if (num_clobbers_to_add)
9565 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9566 rtvec_alloc (GET_CODE (pat) == PARALLEL
9568 + num_clobbers_to_add)
9569 : num_clobbers_to_add + 1));
9571 if (GET_CODE (pat) == PARALLEL)
9572 for (i = 0; i < XVECLEN (pat, 0); i++)
9573 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9575 XVECEXP (newpat, 0, 0) = pat;
9577 add_clobbers (newpat, insn_code_number);
9579 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9580 i < XVECLEN (newpat, 0); i++)
9582 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
9583 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9585 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9586 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9594 return insn_code_number;
9597 /* Like gen_lowpart_general but for use by combine. In combine it
9598 is not possible to create any new pseudoregs. However, it is
9599 safe to create invalid memory addresses, because combine will
9600 try to recognize them and all they will do is make the combine
9603 If for some reason this cannot do its job, an rtx
9604 (clobber (const_int 0)) is returned.
9605 An insn containing that will not be recognized. */
9608 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
9610 enum machine_mode imode = GET_MODE (x);
9611 unsigned int osize = GET_MODE_SIZE (omode);
9612 unsigned int isize = GET_MODE_SIZE (imode);
9618 /* Return identity if this is a CONST or symbolic reference. */
9620 && (GET_CODE (x) == CONST
9621 || GET_CODE (x) == SYMBOL_REF
9622 || GET_CODE (x) == LABEL_REF))
9625 /* We can only support MODE being wider than a word if X is a
9626 constant integer or has a mode the same size. */
9627 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
9628 && ! ((imode == VOIDmode
9629 && (GET_CODE (x) == CONST_INT
9630 || GET_CODE (x) == CONST_DOUBLE))
9634 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9635 won't know what to do. So we will strip off the SUBREG here and
9636 process normally. */
9637 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
9641 /* For use in case we fall down into the address adjustments
9642 further below, we need to adjust the known mode and size of
9643 x; imode and isize, since we just adjusted x. */
9644 imode = GET_MODE (x);
9649 isize = GET_MODE_SIZE (imode);
9652 result = gen_lowpart_common (omode, x);
9654 #ifdef CANNOT_CHANGE_MODE_CLASS
9655 if (result != 0 && GET_CODE (result) == SUBREG)
9656 record_subregs_of_mode (result);
9666 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9668 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9671 /* If we want to refer to something bigger than the original memref,
9672 generate a paradoxical subreg instead. That will force a reload
9673 of the original memref X. */
9675 return gen_rtx_SUBREG (omode, x, 0);
9677 if (WORDS_BIG_ENDIAN)
9678 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
9680 /* Adjust the address so that the address-after-the-data is
9682 if (BYTES_BIG_ENDIAN)
9683 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
9685 return adjust_address_nv (x, omode, offset);
9688 /* If X is a comparison operator, rewrite it in a new mode. This
9689 probably won't match, but may allow further simplifications. */
9690 else if (COMPARISON_P (x))
9691 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
9693 /* If we couldn't simplify X any other way, just enclose it in a
9694 SUBREG. Normally, this SUBREG won't match, but some patterns may
9695 include an explicit SUBREG or we may simplify it further in combine. */
9701 offset = subreg_lowpart_offset (omode, imode);
9702 if (imode == VOIDmode)
9704 imode = int_mode_for_mode (omode);
9705 x = gen_lowpart_common (imode, x);
9709 res = simplify_gen_subreg (omode, x, imode, offset);
9715 return gen_rtx_CLOBBER (imode, const0_rtx);
9718 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9719 comparison code that will be tested.
9721 The result is a possibly different comparison code to use. *POP0 and
9722 *POP1 may be updated.
9724 It is possible that we might detect that a comparison is either always
9725 true or always false. However, we do not perform general constant
9726 folding in combine, so this knowledge isn't useful. Such tautologies
9727 should have been detected earlier. Hence we ignore all such cases. */
9729 static enum rtx_code
9730 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
9736 enum machine_mode mode, tmode;
9738 /* Try a few ways of applying the same transformation to both operands. */
9741 #ifndef WORD_REGISTER_OPERATIONS
9742 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9743 so check specially. */
9744 if (code != GTU && code != GEU && code != LTU && code != LEU
9745 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9746 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9747 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9748 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9749 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9750 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9751 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9752 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9753 && XEXP (op0, 1) == XEXP (op1, 1)
9754 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
9755 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
9756 && (INTVAL (XEXP (op0, 1))
9757 == (GET_MODE_BITSIZE (GET_MODE (op0))
9759 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9761 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9762 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9766 /* If both operands are the same constant shift, see if we can ignore the
9767 shift. We can if the shift is a rotate or if the bits shifted out of
9768 this shift are known to be zero for both inputs and if the type of
9769 comparison is compatible with the shift. */
9770 if (GET_CODE (op0) == GET_CODE (op1)
9771 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9772 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9773 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9774 && (code != GT && code != LT && code != GE && code != LE))
9775 || (GET_CODE (op0) == ASHIFTRT
9776 && (code != GTU && code != LTU
9777 && code != GEU && code != LEU)))
9778 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9779 && INTVAL (XEXP (op0, 1)) >= 0
9780 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9781 && XEXP (op0, 1) == XEXP (op1, 1))
9783 enum machine_mode mode = GET_MODE (op0);
9784 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9785 int shift_count = INTVAL (XEXP (op0, 1));
9787 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9788 mask &= (mask >> shift_count) << shift_count;
9789 else if (GET_CODE (op0) == ASHIFT)
9790 mask = (mask & (mask << shift_count)) >> shift_count;
9792 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
9793 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
9794 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9799 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9800 SUBREGs are of the same mode, and, in both cases, the AND would
9801 be redundant if the comparison was done in the narrower mode,
9802 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9803 and the operand's possibly nonzero bits are 0xffffff01; in that case
9804 if we only care about QImode, we don't need the AND). This case
9805 occurs if the output mode of an scc insn is not SImode and
9806 STORE_FLAG_VALUE == 1 (e.g., the 386).
9808 Similarly, check for a case where the AND's are ZERO_EXTEND
9809 operations from some narrower mode even though a SUBREG is not
9812 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9813 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9814 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
9816 rtx inner_op0 = XEXP (op0, 0);
9817 rtx inner_op1 = XEXP (op1, 0);
9818 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9819 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9822 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9823 && (GET_MODE_SIZE (GET_MODE (inner_op0))
9824 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9825 && (GET_MODE (SUBREG_REG (inner_op0))
9826 == GET_MODE (SUBREG_REG (inner_op1)))
9827 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
9828 <= HOST_BITS_PER_WIDE_INT)
9829 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9830 GET_MODE (SUBREG_REG (inner_op0)))))
9831 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9832 GET_MODE (SUBREG_REG (inner_op1))))))
9834 op0 = SUBREG_REG (inner_op0);
9835 op1 = SUBREG_REG (inner_op1);
9837 /* The resulting comparison is always unsigned since we masked
9838 off the original sign bit. */
9839 code = unsigned_condition (code);
9845 for (tmode = GET_CLASS_NARROWEST_MODE
9846 (GET_MODE_CLASS (GET_MODE (op0)));
9847 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9848 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
9850 op0 = gen_lowpart (tmode, inner_op0);
9851 op1 = gen_lowpart (tmode, inner_op1);
9852 code = unsigned_condition (code);
9861 /* If both operands are NOT, we can strip off the outer operation
9862 and adjust the comparison code for swapped operands; similarly for
9863 NEG, except that this must be an equality comparison. */
9864 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9865 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9866 && (code == EQ || code == NE)))
9867 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
9873 /* If the first operand is a constant, swap the operands and adjust the
9874 comparison code appropriately, but don't do this if the second operand
9875 is already a constant integer. */
9876 if (swap_commutative_operands_p (op0, op1))
9878 tem = op0, op0 = op1, op1 = tem;
9879 code = swap_condition (code);
9882 /* We now enter a loop during which we will try to simplify the comparison.
9883 For the most part, we only are concerned with comparisons with zero,
9884 but some things may really be comparisons with zero but not start
9885 out looking that way. */
9887 while (GET_CODE (op1) == CONST_INT)
9889 enum machine_mode mode = GET_MODE (op0);
9890 unsigned int mode_width = GET_MODE_BITSIZE (mode);
9891 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9892 int equality_comparison_p;
9893 int sign_bit_comparison_p;
9894 int unsigned_comparison_p;
9895 HOST_WIDE_INT const_op;
9897 /* We only want to handle integral modes. This catches VOIDmode,
9898 CCmode, and the floating-point modes. An exception is that we
9899 can handle VOIDmode if OP0 is a COMPARE or a comparison
9902 if (GET_MODE_CLASS (mode) != MODE_INT
9903 && ! (mode == VOIDmode
9904 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
9907 /* Get the constant we are comparing against and turn off all bits
9908 not on in our mode. */
9909 const_op = INTVAL (op1);
9910 if (mode != VOIDmode)
9911 const_op = trunc_int_for_mode (const_op, mode);
9912 op1 = GEN_INT (const_op);
9914 /* If we are comparing against a constant power of two and the value
9915 being compared can only have that single bit nonzero (e.g., it was
9916 `and'ed with that bit), we can replace this with a comparison
9919 && (code == EQ || code == NE || code == GE || code == GEU
9920 || code == LT || code == LTU)
9921 && mode_width <= HOST_BITS_PER_WIDE_INT
9922 && exact_log2 (const_op) >= 0
9923 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
9925 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9926 op1 = const0_rtx, const_op = 0;
9929 /* Similarly, if we are comparing a value known to be either -1 or
9930 0 with -1, change it to the opposite comparison against zero. */
9933 && (code == EQ || code == NE || code == GT || code == LE
9934 || code == GEU || code == LTU)
9935 && num_sign_bit_copies (op0, mode) == mode_width)
9937 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9938 op1 = const0_rtx, const_op = 0;
9941 /* Do some canonicalizations based on the comparison code. We prefer
9942 comparisons against zero and then prefer equality comparisons.
9943 If we can reduce the size of a constant, we will do that too. */
9948 /* < C is equivalent to <= (C - 1) */
9952 op1 = GEN_INT (const_op);
9954 /* ... fall through to LE case below. */
9960 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
9964 op1 = GEN_INT (const_op);
9968 /* If we are doing a <= 0 comparison on a value known to have
9969 a zero sign bit, we can replace this with == 0. */
9970 else if (const_op == 0
9971 && mode_width <= HOST_BITS_PER_WIDE_INT
9972 && (nonzero_bits (op0, mode)
9973 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9978 /* >= C is equivalent to > (C - 1). */
9982 op1 = GEN_INT (const_op);
9984 /* ... fall through to GT below. */
9990 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
9994 op1 = GEN_INT (const_op);
9998 /* If we are doing a > 0 comparison on a value known to have
9999 a zero sign bit, we can replace this with != 0. */
10000 else if (const_op == 0
10001 && mode_width <= HOST_BITS_PER_WIDE_INT
10002 && (nonzero_bits (op0, mode)
10003 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10008 /* < C is equivalent to <= (C - 1). */
10012 op1 = GEN_INT (const_op);
10014 /* ... fall through ... */
10017 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10018 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10019 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10021 const_op = 0, op1 = const0_rtx;
10029 /* unsigned <= 0 is equivalent to == 0 */
10033 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10034 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10035 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10037 const_op = 0, op1 = const0_rtx;
10043 /* >= C is equivalent to > (C - 1). */
10047 op1 = GEN_INT (const_op);
10049 /* ... fall through ... */
10052 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10053 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10054 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10056 const_op = 0, op1 = const0_rtx;
10064 /* unsigned > 0 is equivalent to != 0 */
10068 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10069 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10070 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10072 const_op = 0, op1 = const0_rtx;
10081 /* Compute some predicates to simplify code below. */
10083 equality_comparison_p = (code == EQ || code == NE);
10084 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10085 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10088 /* If this is a sign bit comparison and we can do arithmetic in
10089 MODE, say that we will only be needing the sign bit of OP0. */
10090 if (sign_bit_comparison_p
10091 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10092 op0 = force_to_mode (op0, mode,
10094 << (GET_MODE_BITSIZE (mode) - 1)),
10097 /* Now try cases based on the opcode of OP0. If none of the cases
10098 does a "continue", we exit this loop immediately after the
10101 switch (GET_CODE (op0))
10104 /* If we are extracting a single bit from a variable position in
10105 a constant that has only a single bit set and are comparing it
10106 with zero, we can convert this into an equality comparison
10107 between the position and the location of the single bit. */
10108 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
10109 have already reduced the shift count modulo the word size. */
10110 if (!SHIFT_COUNT_TRUNCATED
10111 && GET_CODE (XEXP (op0, 0)) == CONST_INT
10112 && XEXP (op0, 1) == const1_rtx
10113 && equality_comparison_p && const_op == 0
10114 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10116 if (BITS_BIG_ENDIAN)
10118 enum machine_mode new_mode
10119 = mode_for_extraction (EP_extzv, 1);
10120 if (new_mode == MAX_MACHINE_MODE)
10121 i = BITS_PER_WORD - 1 - i;
10125 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10129 op0 = XEXP (op0, 2);
10133 /* Result is nonzero iff shift count is equal to I. */
10134 code = reverse_condition (code);
10138 /* ... fall through ... */
10141 tem = expand_compound_operation (op0);
10150 /* If testing for equality, we can take the NOT of the constant. */
10151 if (equality_comparison_p
10152 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10154 op0 = XEXP (op0, 0);
10159 /* If just looking at the sign bit, reverse the sense of the
10161 if (sign_bit_comparison_p)
10163 op0 = XEXP (op0, 0);
10164 code = (code == GE ? LT : GE);
10170 /* If testing for equality, we can take the NEG of the constant. */
10171 if (equality_comparison_p
10172 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10174 op0 = XEXP (op0, 0);
10179 /* The remaining cases only apply to comparisons with zero. */
10183 /* When X is ABS or is known positive,
10184 (neg X) is < 0 if and only if X != 0. */
10186 if (sign_bit_comparison_p
10187 && (GET_CODE (XEXP (op0, 0)) == ABS
10188 || (mode_width <= HOST_BITS_PER_WIDE_INT
10189 && (nonzero_bits (XEXP (op0, 0), mode)
10190 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10192 op0 = XEXP (op0, 0);
10193 code = (code == LT ? NE : EQ);
10197 /* If we have NEG of something whose two high-order bits are the
10198 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10199 if (num_sign_bit_copies (op0, mode) >= 2)
10201 op0 = XEXP (op0, 0);
10202 code = swap_condition (code);
10208 /* If we are testing equality and our count is a constant, we
10209 can perform the inverse operation on our RHS. */
10210 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10211 && (tem = simplify_binary_operation (ROTATERT, mode,
10212 op1, XEXP (op0, 1))) != 0)
10214 op0 = XEXP (op0, 0);
10219 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10220 a particular bit. Convert it to an AND of a constant of that
10221 bit. This will be converted into a ZERO_EXTRACT. */
10222 if (const_op == 0 && sign_bit_comparison_p
10223 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10224 && mode_width <= HOST_BITS_PER_WIDE_INT)
10226 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10229 - INTVAL (XEXP (op0, 1)))));
10230 code = (code == LT ? NE : EQ);
10234 /* Fall through. */
10237 /* ABS is ignorable inside an equality comparison with zero. */
10238 if (const_op == 0 && equality_comparison_p)
10240 op0 = XEXP (op0, 0);
10246 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10247 (compare FOO CONST) if CONST fits in FOO's mode and we
10248 are either testing inequality or have an unsigned
10249 comparison with ZERO_EXTEND or a signed comparison with
10250 SIGN_EXTEND. But don't do it if we don't have a compare
10251 insn of the given mode, since we'd have to revert it
10252 later on, and then we wouldn't know whether to sign- or
10254 mode = GET_MODE (XEXP (op0, 0));
10255 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10256 && ! unsigned_comparison_p
10257 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10258 && ((unsigned HOST_WIDE_INT) const_op
10259 < (((unsigned HOST_WIDE_INT) 1
10260 << (GET_MODE_BITSIZE (mode) - 1))))
10261 && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
10263 op0 = XEXP (op0, 0);
10269 /* Check for the case where we are comparing A - C1 with C2, that is
10271 (subreg:MODE (plus (A) (-C1))) op (C2)
10273 with C1 a constant, and try to lift the SUBREG, i.e. to do the
10274 comparison in the wider mode. One of the following two conditions
10275 must be true in order for this to be valid:
10277 1. The mode extension results in the same bit pattern being added
10278 on both sides and the comparison is equality or unsigned. As
10279 C2 has been truncated to fit in MODE, the pattern can only be
10282 2. The mode extension results in the sign bit being copied on
10285 The difficulty here is that we have predicates for A but not for
10286 (A - C1) so we need to check that C1 is within proper bounds so
10287 as to perturbate A as little as possible. */
10289 if (mode_width <= HOST_BITS_PER_WIDE_INT
10290 && subreg_lowpart_p (op0)
10291 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
10292 && GET_CODE (SUBREG_REG (op0)) == PLUS
10293 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT)
10295 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
10296 rtx a = XEXP (SUBREG_REG (op0), 0);
10297 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
10300 && (unsigned HOST_WIDE_INT) c1
10301 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
10302 && (equality_comparison_p || unsigned_comparison_p)
10303 /* (A - C1) zero-extends if it is positive and sign-extends
10304 if it is negative, C2 both zero- and sign-extends. */
10305 && ((0 == (nonzero_bits (a, inner_mode)
10306 & ~GET_MODE_MASK (mode))
10308 /* (A - C1) sign-extends if it is positive and 1-extends
10309 if it is negative, C2 both sign- and 1-extends. */
10310 || (num_sign_bit_copies (a, inner_mode)
10311 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10314 || ((unsigned HOST_WIDE_INT) c1
10315 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
10316 /* (A - C1) always sign-extends, like C2. */
10317 && num_sign_bit_copies (a, inner_mode)
10318 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10319 - (mode_width - 1))))
10321 op0 = SUBREG_REG (op0);
10326 /* If the inner mode is narrower and we are extracting the low part,
10327 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10328 if (subreg_lowpart_p (op0)
10329 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10330 /* Fall through */ ;
10334 /* ... fall through ... */
10337 mode = GET_MODE (XEXP (op0, 0));
10338 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10339 && (unsigned_comparison_p || equality_comparison_p)
10340 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10341 && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
10342 && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
10344 op0 = XEXP (op0, 0);
10350 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10351 this for equality comparisons due to pathological cases involving
10353 if (equality_comparison_p
10354 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10355 op1, XEXP (op0, 1))))
10357 op0 = XEXP (op0, 0);
10362 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10363 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10364 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10366 op0 = XEXP (XEXP (op0, 0), 0);
10367 code = (code == LT ? EQ : NE);
10373 /* We used to optimize signed comparisons against zero, but that
10374 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10375 arrive here as equality comparisons, or (GEU, LTU) are
10376 optimized away. No need to special-case them. */
10378 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10379 (eq B (minus A C)), whichever simplifies. We can only do
10380 this for equality comparisons due to pathological cases involving
10382 if (equality_comparison_p
10383 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10384 XEXP (op0, 1), op1)))
10386 op0 = XEXP (op0, 0);
10391 if (equality_comparison_p
10392 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10393 XEXP (op0, 0), op1)))
10395 op0 = XEXP (op0, 1);
10400 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10401 of bits in X minus 1, is one iff X > 0. */
10402 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10403 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10404 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10406 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10408 op0 = XEXP (op0, 1);
10409 code = (code == GE ? LE : GT);
10415 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10416 if C is zero or B is a constant. */
10417 if (equality_comparison_p
10418 && 0 != (tem = simplify_binary_operation (XOR, mode,
10419 XEXP (op0, 1), op1)))
10421 op0 = XEXP (op0, 0);
10428 case UNEQ: case LTGT:
10429 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10430 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10431 case UNORDERED: case ORDERED:
10432 /* We can't do anything if OP0 is a condition code value, rather
10433 than an actual data value. */
10435 || CC0_P (XEXP (op0, 0))
10436 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10439 /* Get the two operands being compared. */
10440 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10441 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10443 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10445 /* Check for the cases where we simply want the result of the
10446 earlier test or the opposite of that result. */
10447 if (code == NE || code == EQ
10448 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10449 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10450 && (STORE_FLAG_VALUE
10451 & (((HOST_WIDE_INT) 1
10452 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10453 && (code == LT || code == GE)))
10455 enum rtx_code new_code;
10456 if (code == LT || code == NE)
10457 new_code = GET_CODE (op0);
10459 new_code = reversed_comparison_code (op0, NULL);
10461 if (new_code != UNKNOWN)
10472 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10474 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10475 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10476 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10478 op0 = XEXP (op0, 1);
10479 code = (code == GE ? GT : LE);
10485 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10486 will be converted to a ZERO_EXTRACT later. */
10487 if (const_op == 0 && equality_comparison_p
10488 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10489 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10491 op0 = simplify_and_const_int
10492 (op0, mode, gen_rtx_LSHIFTRT (mode,
10494 XEXP (XEXP (op0, 0), 1)),
10495 (HOST_WIDE_INT) 1);
10499 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10500 zero and X is a comparison and C1 and C2 describe only bits set
10501 in STORE_FLAG_VALUE, we can compare with X. */
10502 if (const_op == 0 && equality_comparison_p
10503 && mode_width <= HOST_BITS_PER_WIDE_INT
10504 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10505 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10506 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10507 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10508 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10510 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10511 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10512 if ((~STORE_FLAG_VALUE & mask) == 0
10513 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
10514 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10515 && COMPARISON_P (tem))))
10517 op0 = XEXP (XEXP (op0, 0), 0);
10522 /* If we are doing an equality comparison of an AND of a bit equal
10523 to the sign bit, replace this with a LT or GE comparison of
10524 the underlying value. */
10525 if (equality_comparison_p
10527 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10528 && mode_width <= HOST_BITS_PER_WIDE_INT
10529 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10530 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10532 op0 = XEXP (op0, 0);
10533 code = (code == EQ ? GE : LT);
10537 /* If this AND operation is really a ZERO_EXTEND from a narrower
10538 mode, the constant fits within that mode, and this is either an
10539 equality or unsigned comparison, try to do this comparison in
10540 the narrower mode. */
10541 if ((equality_comparison_p || unsigned_comparison_p)
10542 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10543 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10544 & GET_MODE_MASK (mode))
10546 && const_op >> i == 0
10547 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10549 op0 = gen_lowpart (tmode, XEXP (op0, 0));
10553 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10554 fits in both M1 and M2 and the SUBREG is either paradoxical
10555 or represents the low part, permute the SUBREG and the AND
10557 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
10559 unsigned HOST_WIDE_INT c1;
10560 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
10561 /* Require an integral mode, to avoid creating something like
10563 if (SCALAR_INT_MODE_P (tmode)
10564 /* It is unsafe to commute the AND into the SUBREG if the
10565 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10566 not defined. As originally written the upper bits
10567 have a defined value due to the AND operation.
10568 However, if we commute the AND inside the SUBREG then
10569 they no longer have defined values and the meaning of
10570 the code has been changed. */
10572 #ifdef WORD_REGISTER_OPERATIONS
10573 || (mode_width > GET_MODE_BITSIZE (tmode)
10574 && mode_width <= BITS_PER_WORD)
10576 || (mode_width <= GET_MODE_BITSIZE (tmode)
10577 && subreg_lowpart_p (XEXP (op0, 0))))
10578 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10579 && mode_width <= HOST_BITS_PER_WIDE_INT
10580 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
10581 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
10582 && (c1 & ~GET_MODE_MASK (tmode)) == 0
10584 && c1 != GET_MODE_MASK (tmode))
10586 op0 = simplify_gen_binary (AND, tmode,
10587 SUBREG_REG (XEXP (op0, 0)),
10588 gen_int_mode (c1, tmode));
10589 op0 = gen_lowpart (mode, op0);
10594 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
10595 if (const_op == 0 && equality_comparison_p
10596 && XEXP (op0, 1) == const1_rtx
10597 && GET_CODE (XEXP (op0, 0)) == NOT)
10599 op0 = simplify_and_const_int
10600 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
10601 code = (code == NE ? EQ : NE);
10605 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10606 (eq (and (lshiftrt X) 1) 0).
10607 Also handle the case where (not X) is expressed using xor. */
10608 if (const_op == 0 && equality_comparison_p
10609 && XEXP (op0, 1) == const1_rtx
10610 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
10612 rtx shift_op = XEXP (XEXP (op0, 0), 0);
10613 rtx shift_count = XEXP (XEXP (op0, 0), 1);
10615 if (GET_CODE (shift_op) == NOT
10616 || (GET_CODE (shift_op) == XOR
10617 && GET_CODE (XEXP (shift_op, 1)) == CONST_INT
10618 && GET_CODE (shift_count) == CONST_INT
10619 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10620 && (INTVAL (XEXP (shift_op, 1))
10621 == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
10623 op0 = simplify_and_const_int
10625 gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
10626 (HOST_WIDE_INT) 1);
10627 code = (code == NE ? EQ : NE);
10634 /* If we have (compare (ashift FOO N) (const_int C)) and
10635 the high order N bits of FOO (N+1 if an inequality comparison)
10636 are known to be zero, we can do this by comparing FOO with C
10637 shifted right N bits so long as the low-order N bits of C are
10639 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10640 && INTVAL (XEXP (op0, 1)) >= 0
10641 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10642 < HOST_BITS_PER_WIDE_INT)
10644 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10645 && mode_width <= HOST_BITS_PER_WIDE_INT
10646 && (nonzero_bits (XEXP (op0, 0), mode)
10647 & ~(mask >> (INTVAL (XEXP (op0, 1))
10648 + ! equality_comparison_p))) == 0)
10650 /* We must perform a logical shift, not an arithmetic one,
10651 as we want the top N bits of C to be zero. */
10652 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10654 temp >>= INTVAL (XEXP (op0, 1));
10655 op1 = gen_int_mode (temp, mode);
10656 op0 = XEXP (op0, 0);
10660 /* If we are doing a sign bit comparison, it means we are testing
10661 a particular bit. Convert it to the appropriate AND. */
10662 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10663 && mode_width <= HOST_BITS_PER_WIDE_INT)
10665 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10668 - INTVAL (XEXP (op0, 1)))));
10669 code = (code == LT ? NE : EQ);
10673 /* If this an equality comparison with zero and we are shifting
10674 the low bit to the sign bit, we can convert this to an AND of the
10676 if (const_op == 0 && equality_comparison_p
10677 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10678 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10681 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10682 (HOST_WIDE_INT) 1);
10688 /* If this is an equality comparison with zero, we can do this
10689 as a logical shift, which might be much simpler. */
10690 if (equality_comparison_p && const_op == 0
10691 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10693 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10695 INTVAL (XEXP (op0, 1)));
10699 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10700 do the comparison in a narrower mode. */
10701 if (! unsigned_comparison_p
10702 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10703 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10704 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10705 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10706 MODE_INT, 1)) != BLKmode
10707 && (((unsigned HOST_WIDE_INT) const_op
10708 + (GET_MODE_MASK (tmode) >> 1) + 1)
10709 <= GET_MODE_MASK (tmode)))
10711 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
10715 /* Likewise if OP0 is a PLUS of a sign extension with a
10716 constant, which is usually represented with the PLUS
10717 between the shifts. */
10718 if (! unsigned_comparison_p
10719 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10720 && GET_CODE (XEXP (op0, 0)) == PLUS
10721 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10722 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10723 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10724 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10725 MODE_INT, 1)) != BLKmode
10726 && (((unsigned HOST_WIDE_INT) const_op
10727 + (GET_MODE_MASK (tmode) >> 1) + 1)
10728 <= GET_MODE_MASK (tmode)))
10730 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10731 rtx add_const = XEXP (XEXP (op0, 0), 1);
10732 rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
10733 add_const, XEXP (op0, 1));
10735 op0 = simplify_gen_binary (PLUS, tmode,
10736 gen_lowpart (tmode, inner),
10741 /* ... fall through ... */
10743 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10744 the low order N bits of FOO are known to be zero, we can do this
10745 by comparing FOO with C shifted left N bits so long as no
10746 overflow occurs. */
10747 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10748 && INTVAL (XEXP (op0, 1)) >= 0
10749 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10750 && mode_width <= HOST_BITS_PER_WIDE_INT
10751 && (nonzero_bits (XEXP (op0, 0), mode)
10752 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10753 && (((unsigned HOST_WIDE_INT) const_op
10754 + (GET_CODE (op0) != LSHIFTRT
10755 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
10758 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
10760 /* If the shift was logical, then we must make the condition
10762 if (GET_CODE (op0) == LSHIFTRT)
10763 code = unsigned_condition (code);
10765 const_op <<= INTVAL (XEXP (op0, 1));
10766 op1 = GEN_INT (const_op);
10767 op0 = XEXP (op0, 0);
10771 /* If we are using this shift to extract just the sign bit, we
10772 can replace this with an LT or GE comparison. */
10774 && (equality_comparison_p || sign_bit_comparison_p)
10775 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10776 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10779 op0 = XEXP (op0, 0);
10780 code = (code == NE || code == GT ? LT : GE);
10792 /* Now make any compound operations involved in this comparison. Then,
10793 check for an outmost SUBREG on OP0 that is not doing anything or is
10794 paradoxical. The latter transformation must only be performed when
10795 it is known that the "extra" bits will be the same in op0 and op1 or
10796 that they don't matter. There are three cases to consider:
10798 1. SUBREG_REG (op0) is a register. In this case the bits are don't
10799 care bits and we can assume they have any convenient value. So
10800 making the transformation is safe.
10802 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
10803 In this case the upper bits of op0 are undefined. We should not make
10804 the simplification in that case as we do not know the contents of
10807 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
10808 UNKNOWN. In that case we know those bits are zeros or ones. We must
10809 also be sure that they are the same as the upper bits of op1.
10811 We can never remove a SUBREG for a non-equality comparison because
10812 the sign bit is in a different place in the underlying object. */
10814 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10815 op1 = make_compound_operation (op1, SET);
10817 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10818 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10819 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
10820 && (code == NE || code == EQ))
10822 if (GET_MODE_SIZE (GET_MODE (op0))
10823 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
10825 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
10827 if (REG_P (SUBREG_REG (op0)))
10829 op0 = SUBREG_REG (op0);
10830 op1 = gen_lowpart (GET_MODE (op0), op1);
10833 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10834 <= HOST_BITS_PER_WIDE_INT)
10835 && (nonzero_bits (SUBREG_REG (op0),
10836 GET_MODE (SUBREG_REG (op0)))
10837 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10839 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
10841 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10842 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10843 op0 = SUBREG_REG (op0), op1 = tem;
10847 /* We now do the opposite procedure: Some machines don't have compare
10848 insns in all modes. If OP0's mode is an integer mode smaller than a
10849 word and we can't do a compare in that mode, see if there is a larger
10850 mode for which we can do the compare. There are a number of cases in
10851 which we can use the wider mode. */
10853 mode = GET_MODE (op0);
10854 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10855 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10856 && ! have_insn_for (COMPARE, mode))
10857 for (tmode = GET_MODE_WIDER_MODE (mode);
10859 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10860 tmode = GET_MODE_WIDER_MODE (tmode))
10861 if (have_insn_for (COMPARE, tmode))
10865 /* If the only nonzero bits in OP0 and OP1 are those in the
10866 narrower mode and this is an equality or unsigned comparison,
10867 we can use the wider mode. Similarly for sign-extended
10868 values, in which case it is true for all comparisons. */
10869 zero_extended = ((code == EQ || code == NE
10870 || code == GEU || code == GTU
10871 || code == LEU || code == LTU)
10872 && (nonzero_bits (op0, tmode)
10873 & ~GET_MODE_MASK (mode)) == 0
10874 && ((GET_CODE (op1) == CONST_INT
10875 || (nonzero_bits (op1, tmode)
10876 & ~GET_MODE_MASK (mode)) == 0)));
10879 || ((num_sign_bit_copies (op0, tmode)
10880 > (unsigned int) (GET_MODE_BITSIZE (tmode)
10881 - GET_MODE_BITSIZE (mode)))
10882 && (num_sign_bit_copies (op1, tmode)
10883 > (unsigned int) (GET_MODE_BITSIZE (tmode)
10884 - GET_MODE_BITSIZE (mode)))))
10886 /* If OP0 is an AND and we don't have an AND in MODE either,
10887 make a new AND in the proper mode. */
10888 if (GET_CODE (op0) == AND
10889 && !have_insn_for (AND, mode))
10890 op0 = simplify_gen_binary (AND, tmode,
10891 gen_lowpart (tmode,
10893 gen_lowpart (tmode,
10896 op0 = gen_lowpart (tmode, op0);
10897 if (zero_extended && GET_CODE (op1) == CONST_INT)
10898 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
10899 op1 = gen_lowpart (tmode, op1);
10903 /* If this is a test for negative, we can make an explicit
10904 test of the sign bit. */
10906 if (op1 == const0_rtx && (code == LT || code == GE)
10907 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10909 op0 = simplify_gen_binary (AND, tmode,
10910 gen_lowpart (tmode, op0),
10911 GEN_INT ((HOST_WIDE_INT) 1
10912 << (GET_MODE_BITSIZE (mode)
10914 code = (code == LT) ? NE : EQ;
10919 #ifdef CANONICALIZE_COMPARISON
10920 /* If this machine only supports a subset of valid comparisons, see if we
10921 can convert an unsupported one into a supported one. */
10922 CANONICALIZE_COMPARISON (code, op0, op1);
10931 /* Utility function for record_value_for_reg. Count number of
10936 enum rtx_code code = GET_CODE (x);
10940 if (GET_RTX_CLASS (code) == '2'
10941 || GET_RTX_CLASS (code) == 'c')
10943 rtx x0 = XEXP (x, 0);
10944 rtx x1 = XEXP (x, 1);
10947 return 1 + 2 * count_rtxs (x0);
10949 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
10950 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
10951 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
10952 return 2 + 2 * count_rtxs (x0)
10953 + count_rtxs (x == XEXP (x1, 0)
10954 ? XEXP (x1, 1) : XEXP (x1, 0));
10956 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
10957 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
10958 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
10959 return 2 + 2 * count_rtxs (x1)
10960 + count_rtxs (x == XEXP (x0, 0)
10961 ? XEXP (x0, 1) : XEXP (x0, 0));
10964 fmt = GET_RTX_FORMAT (code);
10965 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10967 ret += count_rtxs (XEXP (x, i));
10972 /* Utility function for following routine. Called when X is part of a value
10973 being stored into last_set_value. Sets last_set_table_tick
10974 for each register mentioned. Similar to mention_regs in cse.c */
10977 update_table_tick (rtx x)
10979 enum rtx_code code = GET_CODE (x);
10980 const char *fmt = GET_RTX_FORMAT (code);
10985 unsigned int regno = REGNO (x);
10986 unsigned int endregno
10987 = regno + (regno < FIRST_PSEUDO_REGISTER
10988 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
10991 for (r = regno; r < endregno; r++)
10992 reg_stat[r].last_set_table_tick = label_tick;
10997 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10998 /* Note that we can't have an "E" in values stored; see
10999 get_last_value_validate. */
11002 /* Check for identical subexpressions. If x contains
11003 identical subexpression we only have to traverse one of
11005 if (i == 0 && ARITHMETIC_P (x))
11007 /* Note that at this point x1 has already been
11009 rtx x0 = XEXP (x, 0);
11010 rtx x1 = XEXP (x, 1);
11012 /* If x0 and x1 are identical then there is no need to
11017 /* If x0 is identical to a subexpression of x1 then while
11018 processing x1, x0 has already been processed. Thus we
11019 are done with x. */
11020 if (ARITHMETIC_P (x1)
11021 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11024 /* If x1 is identical to a subexpression of x0 then we
11025 still have to process the rest of x0. */
11026 if (ARITHMETIC_P (x0)
11027 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11029 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
11034 update_table_tick (XEXP (x, i));
11038 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11039 are saying that the register is clobbered and we no longer know its
11040 value. If INSN is zero, don't update reg_stat[].last_set; this is
11041 only permitted with VALUE also zero and is used to invalidate the
11045 record_value_for_reg (rtx reg, rtx insn, rtx value)
11047 unsigned int regno = REGNO (reg);
11048 unsigned int endregno
11049 = regno + (regno < FIRST_PSEUDO_REGISTER
11050 ? hard_regno_nregs[regno][GET_MODE (reg)] : 1);
11053 /* If VALUE contains REG and we have a previous value for REG, substitute
11054 the previous value. */
11055 if (value && insn && reg_overlap_mentioned_p (reg, value))
11059 /* Set things up so get_last_value is allowed to see anything set up to
11061 subst_low_cuid = INSN_CUID (insn);
11062 tem = get_last_value (reg);
11064 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11065 it isn't going to be useful and will take a lot of time to process,
11066 so just use the CLOBBER. */
11070 if (ARITHMETIC_P (tem)
11071 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11072 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11073 tem = XEXP (tem, 0);
11074 else if (count_occurrences (value, reg, 1) >= 2)
11076 /* If there are two or more occurrences of REG in VALUE,
11077 prevent the value from growing too much. */
11078 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
11079 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
11082 value = replace_rtx (copy_rtx (value), reg, tem);
11086 /* For each register modified, show we don't know its value, that
11087 we don't know about its bitwise content, that its value has been
11088 updated, and that we don't know the location of the death of the
11090 for (i = regno; i < endregno; i++)
11093 reg_stat[i].last_set = insn;
11095 reg_stat[i].last_set_value = 0;
11096 reg_stat[i].last_set_mode = 0;
11097 reg_stat[i].last_set_nonzero_bits = 0;
11098 reg_stat[i].last_set_sign_bit_copies = 0;
11099 reg_stat[i].last_death = 0;
11102 /* Mark registers that are being referenced in this value. */
11104 update_table_tick (value);
11106 /* Now update the status of each register being set.
11107 If someone is using this register in this block, set this register
11108 to invalid since we will get confused between the two lives in this
11109 basic block. This makes using this register always invalid. In cse, we
11110 scan the table to invalidate all entries using this register, but this
11111 is too much work for us. */
11113 for (i = regno; i < endregno; i++)
11115 reg_stat[i].last_set_label = label_tick;
11116 if (value && reg_stat[i].last_set_table_tick == label_tick)
11117 reg_stat[i].last_set_invalid = 1;
11119 reg_stat[i].last_set_invalid = 0;
11122 /* The value being assigned might refer to X (like in "x++;"). In that
11123 case, we must replace it with (clobber (const_int 0)) to prevent
11125 if (value && ! get_last_value_validate (&value, insn,
11126 reg_stat[regno].last_set_label, 0))
11128 value = copy_rtx (value);
11129 if (! get_last_value_validate (&value, insn,
11130 reg_stat[regno].last_set_label, 1))
11134 /* For the main register being modified, update the value, the mode, the
11135 nonzero bits, and the number of sign bit copies. */
11137 reg_stat[regno].last_set_value = value;
11141 enum machine_mode mode = GET_MODE (reg);
11142 subst_low_cuid = INSN_CUID (insn);
11143 reg_stat[regno].last_set_mode = mode;
11144 if (GET_MODE_CLASS (mode) == MODE_INT
11145 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11146 mode = nonzero_bits_mode;
11147 reg_stat[regno].last_set_nonzero_bits = nonzero_bits (value, mode);
11148 reg_stat[regno].last_set_sign_bit_copies
11149 = num_sign_bit_copies (value, GET_MODE (reg));
11153 /* Called via note_stores from record_dead_and_set_regs to handle one
11154 SET or CLOBBER in an insn. DATA is the instruction in which the
11155 set is occurring. */
11158 record_dead_and_set_regs_1 (rtx dest, rtx setter, void *data)
11160 rtx record_dead_insn = (rtx) data;
11162 if (GET_CODE (dest) == SUBREG)
11163 dest = SUBREG_REG (dest);
11167 /* If we are setting the whole register, we know its value. Otherwise
11168 show that we don't know the value. We can handle SUBREG in
11170 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11171 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11172 else if (GET_CODE (setter) == SET
11173 && GET_CODE (SET_DEST (setter)) == SUBREG
11174 && SUBREG_REG (SET_DEST (setter)) == dest
11175 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11176 && subreg_lowpart_p (SET_DEST (setter)))
11177 record_value_for_reg (dest, record_dead_insn,
11178 gen_lowpart (GET_MODE (dest),
11179 SET_SRC (setter)));
11181 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11183 else if (MEM_P (dest)
11184 /* Ignore pushes, they clobber nothing. */
11185 && ! push_operand (dest, GET_MODE (dest)))
11186 mem_last_set = INSN_CUID (record_dead_insn);
11189 /* Update the records of when each REG was most recently set or killed
11190 for the things done by INSN. This is the last thing done in processing
11191 INSN in the combiner loop.
11193 We update reg_stat[], in particular fields last_set, last_set_value,
11194 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
11195 last_death, and also the similar information mem_last_set (which insn
11196 most recently modified memory) and last_call_cuid (which insn was the
11197 most recent subroutine call). */
11200 record_dead_and_set_regs (rtx insn)
11205 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11207 if (REG_NOTE_KIND (link) == REG_DEAD
11208 && REG_P (XEXP (link, 0)))
11210 unsigned int regno = REGNO (XEXP (link, 0));
11211 unsigned int endregno
11212 = regno + (regno < FIRST_PSEUDO_REGISTER
11213 ? hard_regno_nregs[regno][GET_MODE (XEXP (link, 0))]
11216 for (i = regno; i < endregno; i++)
11217 reg_stat[i].last_death = insn;
11219 else if (REG_NOTE_KIND (link) == REG_INC)
11220 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11225 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11226 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11228 reg_stat[i].last_set_value = 0;
11229 reg_stat[i].last_set_mode = 0;
11230 reg_stat[i].last_set_nonzero_bits = 0;
11231 reg_stat[i].last_set_sign_bit_copies = 0;
11232 reg_stat[i].last_death = 0;
11235 last_call_cuid = mem_last_set = INSN_CUID (insn);
11237 /* Don't bother recording what this insn does. It might set the
11238 return value register, but we can't combine into a call
11239 pattern anyway, so there's no point trying (and it may cause
11240 a crash, if e.g. we wind up asking for last_set_value of a
11241 SUBREG of the return value register). */
11245 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11248 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11249 register present in the SUBREG, so for each such SUBREG go back and
11250 adjust nonzero and sign bit information of the registers that are
11251 known to have some zero/sign bits set.
11253 This is needed because when combine blows the SUBREGs away, the
11254 information on zero/sign bits is lost and further combines can be
11255 missed because of that. */
11258 record_promoted_value (rtx insn, rtx subreg)
11261 unsigned int regno = REGNO (SUBREG_REG (subreg));
11262 enum machine_mode mode = GET_MODE (subreg);
11264 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11267 for (links = LOG_LINKS (insn); links;)
11269 insn = XEXP (links, 0);
11270 set = single_set (insn);
11272 if (! set || !REG_P (SET_DEST (set))
11273 || REGNO (SET_DEST (set)) != regno
11274 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11276 links = XEXP (links, 1);
11280 if (reg_stat[regno].last_set == insn)
11282 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11283 reg_stat[regno].last_set_nonzero_bits &= GET_MODE_MASK (mode);
11286 if (REG_P (SET_SRC (set)))
11288 regno = REGNO (SET_SRC (set));
11289 links = LOG_LINKS (insn);
11296 /* Scan X for promoted SUBREGs. For each one found,
11297 note what it implies to the registers used in it. */
11300 check_promoted_subreg (rtx insn, rtx x)
11302 if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
11303 && REG_P (SUBREG_REG (x)))
11304 record_promoted_value (insn, x);
11307 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11310 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11314 check_promoted_subreg (insn, XEXP (x, i));
11318 if (XVEC (x, i) != 0)
11319 for (j = 0; j < XVECLEN (x, i); j++)
11320 check_promoted_subreg (insn, XVECEXP (x, i, j));
11326 /* Utility routine for the following function. Verify that all the registers
11327 mentioned in *LOC are valid when *LOC was part of a value set when
11328 label_tick == TICK. Return 0 if some are not.
11330 If REPLACE is nonzero, replace the invalid reference with
11331 (clobber (const_int 0)) and return 1. This replacement is useful because
11332 we often can get useful information about the form of a value (e.g., if
11333 it was produced by a shift that always produces -1 or 0) even though
11334 we don't know exactly what registers it was produced from. */
11337 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
11340 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11341 int len = GET_RTX_LENGTH (GET_CODE (x));
11346 unsigned int regno = REGNO (x);
11347 unsigned int endregno
11348 = regno + (regno < FIRST_PSEUDO_REGISTER
11349 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11352 for (j = regno; j < endregno; j++)
11353 if (reg_stat[j].last_set_invalid
11354 /* If this is a pseudo-register that was only set once and not
11355 live at the beginning of the function, it is always valid. */
11356 || (! (regno >= FIRST_PSEUDO_REGISTER
11357 && REG_N_SETS (regno) == 1
11358 && (! REGNO_REG_SET_P
11359 (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
11361 && reg_stat[j].last_set_label > tick))
11364 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11370 /* If this is a memory reference, make sure that there were
11371 no stores after it that might have clobbered the value. We don't
11372 have alias info, so we assume any store invalidates it. */
11373 else if (MEM_P (x) && !MEM_READONLY_P (x)
11374 && INSN_CUID (insn) <= mem_last_set)
11377 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11381 for (i = 0; i < len; i++)
11385 /* Check for identical subexpressions. If x contains
11386 identical subexpression we only have to traverse one of
11388 if (i == 1 && ARITHMETIC_P (x))
11390 /* Note that at this point x0 has already been checked
11391 and found valid. */
11392 rtx x0 = XEXP (x, 0);
11393 rtx x1 = XEXP (x, 1);
11395 /* If x0 and x1 are identical then x is also valid. */
11399 /* If x1 is identical to a subexpression of x0 then
11400 while checking x0, x1 has already been checked. Thus
11401 it is valid and so as x. */
11402 if (ARITHMETIC_P (x0)
11403 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11406 /* If x0 is identical to a subexpression of x1 then x is
11407 valid iff the rest of x1 is valid. */
11408 if (ARITHMETIC_P (x1)
11409 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11411 get_last_value_validate (&XEXP (x1,
11412 x0 == XEXP (x1, 0) ? 1 : 0),
11413 insn, tick, replace);
11416 if (get_last_value_validate (&XEXP (x, i), insn, tick,
11420 /* Don't bother with these. They shouldn't occur anyway. */
11421 else if (fmt[i] == 'E')
11425 /* If we haven't found a reason for it to be invalid, it is valid. */
11429 /* Get the last value assigned to X, if known. Some registers
11430 in the value may be replaced with (clobber (const_int 0)) if their value
11431 is known longer known reliably. */
11434 get_last_value (rtx x)
11436 unsigned int regno;
11439 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11440 then convert it to the desired mode. If this is a paradoxical SUBREG,
11441 we cannot predict what values the "extra" bits might have. */
11442 if (GET_CODE (x) == SUBREG
11443 && subreg_lowpart_p (x)
11444 && (GET_MODE_SIZE (GET_MODE (x))
11445 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11446 && (value = get_last_value (SUBREG_REG (x))) != 0)
11447 return gen_lowpart (GET_MODE (x), value);
11453 value = reg_stat[regno].last_set_value;
11455 /* If we don't have a value, or if it isn't for this basic block and
11456 it's either a hard register, set more than once, or it's a live
11457 at the beginning of the function, return 0.
11459 Because if it's not live at the beginning of the function then the reg
11460 is always set before being used (is never used without being set).
11461 And, if it's set only once, and it's always set before use, then all
11462 uses must have the same last value, even if it's not from this basic
11466 || (reg_stat[regno].last_set_label != label_tick
11467 && (regno < FIRST_PSEUDO_REGISTER
11468 || REG_N_SETS (regno) != 1
11469 || (REGNO_REG_SET_P
11470 (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
11474 /* If the value was set in a later insn than the ones we are processing,
11475 we can't use it even if the register was only set once. */
11476 if (INSN_CUID (reg_stat[regno].last_set) >= subst_low_cuid)
11479 /* If the value has all its registers valid, return it. */
11480 if (get_last_value_validate (&value, reg_stat[regno].last_set,
11481 reg_stat[regno].last_set_label, 0))
11484 /* Otherwise, make a copy and replace any invalid register with
11485 (clobber (const_int 0)). If that fails for some reason, return 0. */
11487 value = copy_rtx (value);
11488 if (get_last_value_validate (&value, reg_stat[regno].last_set,
11489 reg_stat[regno].last_set_label, 1))
11495 /* Return nonzero if expression X refers to a REG or to memory
11496 that is set in an instruction more recent than FROM_CUID. */
11499 use_crosses_set_p (rtx x, int from_cuid)
11503 enum rtx_code code = GET_CODE (x);
11507 unsigned int regno = REGNO (x);
11508 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11509 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11511 #ifdef PUSH_ROUNDING
11512 /* Don't allow uses of the stack pointer to be moved,
11513 because we don't know whether the move crosses a push insn. */
11514 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11517 for (; regno < endreg; regno++)
11518 if (reg_stat[regno].last_set
11519 && INSN_CUID (reg_stat[regno].last_set) > from_cuid)
11524 if (code == MEM && mem_last_set > from_cuid)
11527 fmt = GET_RTX_FORMAT (code);
11529 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11534 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11535 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11538 else if (fmt[i] == 'e'
11539 && use_crosses_set_p (XEXP (x, i), from_cuid))
11545 /* Define three variables used for communication between the following
11548 static unsigned int reg_dead_regno, reg_dead_endregno;
11549 static int reg_dead_flag;
11551 /* Function called via note_stores from reg_dead_at_p.
11553 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11554 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11557 reg_dead_at_p_1 (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
11559 unsigned int regno, endregno;
11564 regno = REGNO (dest);
11565 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11566 ? hard_regno_nregs[regno][GET_MODE (dest)] : 1);
11568 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11569 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11572 /* Return nonzero if REG is known to be dead at INSN.
11574 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11575 referencing REG, it is dead. If we hit a SET referencing REG, it is
11576 live. Otherwise, see if it is live or dead at the start of the basic
11577 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11578 must be assumed to be always live. */
11581 reg_dead_at_p (rtx reg, rtx insn)
11586 /* Set variables for reg_dead_at_p_1. */
11587 reg_dead_regno = REGNO (reg);
11588 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11589 ? hard_regno_nregs[reg_dead_regno]
11595 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
11596 we allow the machine description to decide whether use-and-clobber
11597 patterns are OK. */
11598 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11600 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11601 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
11605 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11606 beginning of function. */
11607 for (; insn && !LABEL_P (insn) && !BARRIER_P (insn);
11608 insn = prev_nonnote_insn (insn))
11610 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11612 return reg_dead_flag == 1 ? 1 : 0;
11614 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11618 /* Get the basic block that we were in. */
11620 block = ENTRY_BLOCK_PTR->next_bb;
11623 FOR_EACH_BB (block)
11624 if (insn == BB_HEAD (block))
11627 if (block == EXIT_BLOCK_PTR)
11631 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11632 if (REGNO_REG_SET_P (block->il.rtl->global_live_at_start, i))
11638 /* Note hard registers in X that are used. This code is similar to
11639 that in flow.c, but much simpler since we don't care about pseudos. */
11642 mark_used_regs_combine (rtx x)
11644 RTX_CODE code = GET_CODE (x);
11645 unsigned int regno;
11658 case ADDR_DIFF_VEC:
11661 /* CC0 must die in the insn after it is set, so we don't need to take
11662 special note of it here. */
11668 /* If we are clobbering a MEM, mark any hard registers inside the
11669 address as used. */
11670 if (MEM_P (XEXP (x, 0)))
11671 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11676 /* A hard reg in a wide mode may really be multiple registers.
11677 If so, mark all of them just like the first. */
11678 if (regno < FIRST_PSEUDO_REGISTER)
11680 unsigned int endregno, r;
11682 /* None of this applies to the stack, frame or arg pointers. */
11683 if (regno == STACK_POINTER_REGNUM
11684 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11685 || regno == HARD_FRAME_POINTER_REGNUM
11687 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11688 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11690 || regno == FRAME_POINTER_REGNUM)
11693 endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11694 for (r = regno; r < endregno; r++)
11695 SET_HARD_REG_BIT (newpat_used_regs, r);
11701 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11703 rtx testreg = SET_DEST (x);
11705 while (GET_CODE (testreg) == SUBREG
11706 || GET_CODE (testreg) == ZERO_EXTRACT
11707 || GET_CODE (testreg) == STRICT_LOW_PART)
11708 testreg = XEXP (testreg, 0);
11710 if (MEM_P (testreg))
11711 mark_used_regs_combine (XEXP (testreg, 0));
11713 mark_used_regs_combine (SET_SRC (x));
11721 /* Recursively scan the operands of this expression. */
11724 const char *fmt = GET_RTX_FORMAT (code);
11726 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11729 mark_used_regs_combine (XEXP (x, i));
11730 else if (fmt[i] == 'E')
11734 for (j = 0; j < XVECLEN (x, i); j++)
11735 mark_used_regs_combine (XVECEXP (x, i, j));
11741 /* Remove register number REGNO from the dead registers list of INSN.
11743 Return the note used to record the death, if there was one. */
11746 remove_death (unsigned int regno, rtx insn)
11748 rtx note = find_regno_note (insn, REG_DEAD, regno);
11752 REG_N_DEATHS (regno)--;
11753 remove_note (insn, note);
11759 /* For each register (hardware or pseudo) used within expression X, if its
11760 death is in an instruction with cuid between FROM_CUID (inclusive) and
11761 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11762 list headed by PNOTES.
11764 That said, don't move registers killed by maybe_kill_insn.
11766 This is done when X is being merged by combination into TO_INSN. These
11767 notes will then be distributed as needed. */
11770 move_deaths (rtx x, rtx maybe_kill_insn, int from_cuid, rtx to_insn,
11775 enum rtx_code code = GET_CODE (x);
11779 unsigned int regno = REGNO (x);
11780 rtx where_dead = reg_stat[regno].last_death;
11781 rtx before_dead, after_dead;
11783 /* Don't move the register if it gets killed in between from and to. */
11784 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11785 && ! reg_referenced_p (x, maybe_kill_insn))
11788 /* WHERE_DEAD could be a USE insn made by combine, so first we
11789 make sure that we have insns with valid INSN_CUID values. */
11790 before_dead = where_dead;
11791 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11792 before_dead = PREV_INSN (before_dead);
11794 after_dead = where_dead;
11795 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11796 after_dead = NEXT_INSN (after_dead);
11798 if (before_dead && after_dead
11799 && INSN_CUID (before_dead) >= from_cuid
11800 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11801 || (where_dead != after_dead
11802 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11804 rtx note = remove_death (regno, where_dead);
11806 /* It is possible for the call above to return 0. This can occur
11807 when last_death points to I2 or I1 that we combined with.
11808 In that case make a new note.
11810 We must also check for the case where X is a hard register
11811 and NOTE is a death note for a range of hard registers
11812 including X. In that case, we must put REG_DEAD notes for
11813 the remaining registers in place of NOTE. */
11815 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11816 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11817 > GET_MODE_SIZE (GET_MODE (x))))
11819 unsigned int deadregno = REGNO (XEXP (note, 0));
11820 unsigned int deadend
11821 = (deadregno + hard_regno_nregs[deadregno]
11822 [GET_MODE (XEXP (note, 0))]);
11823 unsigned int ourend
11824 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11827 for (i = deadregno; i < deadend; i++)
11828 if (i < regno || i >= ourend)
11829 REG_NOTES (where_dead)
11830 = gen_rtx_EXPR_LIST (REG_DEAD,
11832 REG_NOTES (where_dead));
11835 /* If we didn't find any note, or if we found a REG_DEAD note that
11836 covers only part of the given reg, and we have a multi-reg hard
11837 register, then to be safe we must check for REG_DEAD notes
11838 for each register other than the first. They could have
11839 their own REG_DEAD notes lying around. */
11840 else if ((note == 0
11842 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11843 < GET_MODE_SIZE (GET_MODE (x)))))
11844 && regno < FIRST_PSEUDO_REGISTER
11845 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
11847 unsigned int ourend
11848 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11849 unsigned int i, offset;
11853 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
11857 for (i = regno + offset; i < ourend; i++)
11858 move_deaths (regno_reg_rtx[i],
11859 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11862 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11864 XEXP (note, 1) = *pnotes;
11868 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11870 REG_N_DEATHS (regno)++;
11876 else if (GET_CODE (x) == SET)
11878 rtx dest = SET_DEST (x);
11880 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11882 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11883 that accesses one word of a multi-word item, some
11884 piece of everything register in the expression is used by
11885 this insn, so remove any old death. */
11886 /* ??? So why do we test for equality of the sizes? */
11888 if (GET_CODE (dest) == ZERO_EXTRACT
11889 || GET_CODE (dest) == STRICT_LOW_PART
11890 || (GET_CODE (dest) == SUBREG
11891 && (((GET_MODE_SIZE (GET_MODE (dest))
11892 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11893 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11894 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11896 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
11900 /* If this is some other SUBREG, we know it replaces the entire
11901 value, so use that as the destination. */
11902 if (GET_CODE (dest) == SUBREG)
11903 dest = SUBREG_REG (dest);
11905 /* If this is a MEM, adjust deaths of anything used in the address.
11906 For a REG (the only other possibility), the entire value is
11907 being replaced so the old value is not used in this insn. */
11910 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11915 else if (GET_CODE (x) == CLOBBER)
11918 len = GET_RTX_LENGTH (code);
11919 fmt = GET_RTX_FORMAT (code);
11921 for (i = 0; i < len; i++)
11926 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11927 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11930 else if (fmt[i] == 'e')
11931 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
11935 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11936 pattern of an insn. X must be a REG. */
11939 reg_bitfield_target_p (rtx x, rtx body)
11943 if (GET_CODE (body) == SET)
11945 rtx dest = SET_DEST (body);
11947 unsigned int regno, tregno, endregno, endtregno;
11949 if (GET_CODE (dest) == ZERO_EXTRACT)
11950 target = XEXP (dest, 0);
11951 else if (GET_CODE (dest) == STRICT_LOW_PART)
11952 target = SUBREG_REG (XEXP (dest, 0));
11956 if (GET_CODE (target) == SUBREG)
11957 target = SUBREG_REG (target);
11959 if (!REG_P (target))
11962 tregno = REGNO (target), regno = REGNO (x);
11963 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11964 return target == x;
11966 endtregno = tregno + hard_regno_nregs[tregno][GET_MODE (target)];
11967 endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11969 return endregno > tregno && regno < endtregno;
11972 else if (GET_CODE (body) == PARALLEL)
11973 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
11974 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
11980 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11981 as appropriate. I3 and I2 are the insns resulting from the combination
11982 insns including FROM (I2 may be zero).
11984 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11985 not need REG_DEAD notes because they are being substituted for. This
11986 saves searching in the most common cases.
11988 Each note in the list is either ignored or placed on some insns, depending
11989 on the type of note. */
11992 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
11995 rtx note, next_note;
11998 for (note = notes; note; note = next_note)
12000 rtx place = 0, place2 = 0;
12002 /* If this NOTE references a pseudo register, ensure it references
12003 the latest copy of that register. */
12004 if (XEXP (note, 0) && REG_P (XEXP (note, 0))
12005 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
12006 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
12008 next_note = XEXP (note, 1);
12009 switch (REG_NOTE_KIND (note))
12013 /* Doesn't matter much where we put this, as long as it's somewhere.
12014 It is preferable to keep these notes on branches, which is most
12015 likely to be i3. */
12019 case REG_VALUE_PROFILE:
12020 /* Just get rid of this note, as it is unused later anyway. */
12023 case REG_NON_LOCAL_GOTO:
12028 gcc_assert (i2 && JUMP_P (i2));
12033 case REG_EH_REGION:
12034 /* These notes must remain with the call or trapping instruction. */
12037 else if (i2 && CALL_P (i2))
12041 gcc_assert (flag_non_call_exceptions);
12042 if (may_trap_p (i3))
12044 else if (i2 && may_trap_p (i2))
12046 /* ??? Otherwise assume we've combined things such that we
12047 can now prove that the instructions can't trap. Drop the
12048 note in this case. */
12054 /* These notes must remain with the call. It should not be
12055 possible for both I2 and I3 to be a call. */
12060 gcc_assert (i2 && CALL_P (i2));
12066 /* Any clobbers for i3 may still exist, and so we must process
12067 REG_UNUSED notes from that insn.
12069 Any clobbers from i2 or i1 can only exist if they were added by
12070 recog_for_combine. In that case, recog_for_combine created the
12071 necessary REG_UNUSED notes. Trying to keep any original
12072 REG_UNUSED notes from these insns can cause incorrect output
12073 if it is for the same register as the original i3 dest.
12074 In that case, we will notice that the register is set in i3,
12075 and then add a REG_UNUSED note for the destination of i3, which
12076 is wrong. However, it is possible to have REG_UNUSED notes from
12077 i2 or i1 for register which were both used and clobbered, so
12078 we keep notes from i2 or i1 if they will turn into REG_DEAD
12081 /* If this register is set or clobbered in I3, put the note there
12082 unless there is one already. */
12083 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12085 if (from_insn != i3)
12088 if (! (REG_P (XEXP (note, 0))
12089 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12090 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12093 /* Otherwise, if this register is used by I3, then this register
12094 now dies here, so we must put a REG_DEAD note here unless there
12096 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12097 && ! (REG_P (XEXP (note, 0))
12098 ? find_regno_note (i3, REG_DEAD,
12099 REGNO (XEXP (note, 0)))
12100 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12102 PUT_REG_NOTE_KIND (note, REG_DEAD);
12110 /* These notes say something about results of an insn. We can
12111 only support them if they used to be on I3 in which case they
12112 remain on I3. Otherwise they are ignored.
12114 If the note refers to an expression that is not a constant, we
12115 must also ignore the note since we cannot tell whether the
12116 equivalence is still true. It might be possible to do
12117 slightly better than this (we only have a problem if I2DEST
12118 or I1DEST is present in the expression), but it doesn't
12119 seem worth the trouble. */
12121 if (from_insn == i3
12122 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12127 case REG_NO_CONFLICT:
12128 /* These notes say something about how a register is used. They must
12129 be present on any use of the register in I2 or I3. */
12130 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12133 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12143 /* This can show up in several ways -- either directly in the
12144 pattern, or hidden off in the constant pool with (or without?)
12145 a REG_EQUAL note. */
12146 /* ??? Ignore the without-reg_equal-note problem for now. */
12147 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12148 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12149 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12150 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12154 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12155 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12156 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12157 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12165 /* Don't attach REG_LABEL note to a JUMP_INSN. Add
12166 a JUMP_LABEL instead or decrement LABEL_NUSES. */
12167 if (place && JUMP_P (place))
12169 rtx label = JUMP_LABEL (place);
12172 JUMP_LABEL (place) = XEXP (note, 0);
12175 gcc_assert (label == XEXP (note, 0));
12176 if (LABEL_P (label))
12177 LABEL_NUSES (label)--;
12181 if (place2 && JUMP_P (place2))
12183 rtx label = JUMP_LABEL (place2);
12186 JUMP_LABEL (place2) = XEXP (note, 0);
12189 gcc_assert (label == XEXP (note, 0));
12190 if (LABEL_P (label))
12191 LABEL_NUSES (label)--;
12198 /* This note says something about the value of a register prior
12199 to the execution of an insn. It is too much trouble to see
12200 if the note is still correct in all situations. It is better
12201 to simply delete it. */
12205 /* If the insn previously containing this note still exists,
12206 put it back where it was. Otherwise move it to the previous
12207 insn. Adjust the corresponding REG_LIBCALL note. */
12208 if (!NOTE_P (from_insn))
12212 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12213 place = prev_real_insn (from_insn);
12215 XEXP (tem, 0) = place;
12216 /* If we're deleting the last remaining instruction of a
12217 libcall sequence, don't add the notes. */
12218 else if (XEXP (note, 0) == from_insn)
12220 /* Don't add the dangling REG_RETVAL note. */
12227 /* This is handled similarly to REG_RETVAL. */
12228 if (!NOTE_P (from_insn))
12232 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12233 place = next_real_insn (from_insn);
12235 XEXP (tem, 0) = place;
12236 /* If we're deleting the last remaining instruction of a
12237 libcall sequence, don't add the notes. */
12238 else if (XEXP (note, 0) == from_insn)
12240 /* Don't add the dangling REG_LIBCALL note. */
12247 /* If we replaced the right hand side of FROM_INSN with a
12248 REG_EQUAL note, the original use of the dying register
12249 will not have been combined into I3 and I2. In such cases,
12250 FROM_INSN is guaranteed to be the first of the combined
12251 instructions, so we simply need to search back before
12252 FROM_INSN for the previous use or set of this register,
12253 then alter the notes there appropriately.
12255 If the register is used as an input in I3, it dies there.
12256 Similarly for I2, if it is nonzero and adjacent to I3.
12258 If the register is not used as an input in either I3 or I2
12259 and it is not one of the registers we were supposed to eliminate,
12260 there are two possibilities. We might have a non-adjacent I2
12261 or we might have somehow eliminated an additional register
12262 from a computation. For example, we might have had A & B where
12263 we discover that B will always be zero. In this case we will
12264 eliminate the reference to A.
12266 In both cases, we must search to see if we can find a previous
12267 use of A and put the death note there. */
12270 && from_insn == i2mod
12271 && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
12276 && CALL_P (from_insn)
12277 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12279 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12281 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12282 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12284 else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
12286 && reg_overlap_mentioned_p (XEXP (note, 0),
12288 || rtx_equal_p (XEXP (note, 0), elim_i1))
12295 basic_block bb = this_basic_block;
12297 for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
12299 if (! INSN_P (tem))
12301 if (tem == BB_HEAD (bb))
12306 /* If the register is being set at TEM, see if that is all
12307 TEM is doing. If so, delete TEM. Otherwise, make this
12308 into a REG_UNUSED note instead. Don't delete sets to
12309 global register vars. */
12310 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
12311 || !global_regs[REGNO (XEXP (note, 0))])
12312 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
12314 rtx set = single_set (tem);
12315 rtx inner_dest = 0;
12317 rtx cc0_setter = NULL_RTX;
12321 for (inner_dest = SET_DEST (set);
12322 (GET_CODE (inner_dest) == STRICT_LOW_PART
12323 || GET_CODE (inner_dest) == SUBREG
12324 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12325 inner_dest = XEXP (inner_dest, 0))
12328 /* Verify that it was the set, and not a clobber that
12329 modified the register.
12331 CC0 targets must be careful to maintain setter/user
12332 pairs. If we cannot delete the setter due to side
12333 effects, mark the user with an UNUSED note instead
12336 if (set != 0 && ! side_effects_p (SET_SRC (set))
12337 && rtx_equal_p (XEXP (note, 0), inner_dest)
12339 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12340 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12341 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12345 /* Move the notes and links of TEM elsewhere.
12346 This might delete other dead insns recursively.
12347 First set the pattern to something that won't use
12349 rtx old_notes = REG_NOTES (tem);
12351 PATTERN (tem) = pc_rtx;
12352 REG_NOTES (tem) = NULL;
12354 distribute_notes (old_notes, tem, tem, NULL_RTX,
12355 NULL_RTX, NULL_RTX);
12356 distribute_links (LOG_LINKS (tem));
12358 SET_INSN_DELETED (tem);
12361 /* Delete the setter too. */
12364 PATTERN (cc0_setter) = pc_rtx;
12365 old_notes = REG_NOTES (cc0_setter);
12366 REG_NOTES (cc0_setter) = NULL;
12368 distribute_notes (old_notes, cc0_setter,
12369 cc0_setter, NULL_RTX,
12370 NULL_RTX, NULL_RTX);
12371 distribute_links (LOG_LINKS (cc0_setter));
12373 SET_INSN_DELETED (cc0_setter);
12379 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12381 /* If there isn't already a REG_UNUSED note, put one
12382 here. Do not place a REG_DEAD note, even if
12383 the register is also used here; that would not
12384 match the algorithm used in lifetime analysis
12385 and can cause the consistency check in the
12386 scheduler to fail. */
12387 if (! find_regno_note (tem, REG_UNUSED,
12388 REGNO (XEXP (note, 0))))
12393 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12395 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12399 /* If we are doing a 3->2 combination, and we have a
12400 register which formerly died in i3 and was not used
12401 by i2, which now no longer dies in i3 and is used in
12402 i2 but does not die in i2, and place is between i2
12403 and i3, then we may need to move a link from place to
12405 if (i2 && INSN_UID (place) <= max_uid_cuid
12406 && INSN_CUID (place) > INSN_CUID (i2)
12408 && INSN_CUID (from_insn) > INSN_CUID (i2)
12409 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12411 rtx links = LOG_LINKS (place);
12412 LOG_LINKS (place) = 0;
12413 distribute_links (links);
12418 if (tem == BB_HEAD (bb))
12422 /* We haven't found an insn for the death note and it
12423 is still a REG_DEAD note, but we have hit the beginning
12424 of the block. If the existing life info says the reg
12425 was dead, there's nothing left to do. Otherwise, we'll
12426 need to do a global life update after combine. */
12427 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12428 && REGNO_REG_SET_P (bb->il.rtl->global_live_at_start,
12429 REGNO (XEXP (note, 0))))
12430 SET_BIT (refresh_blocks, this_basic_block->index);
12433 /* If the register is set or already dead at PLACE, we needn't do
12434 anything with this note if it is still a REG_DEAD note.
12435 We check here if it is set at all, not if is it totally replaced,
12436 which is what `dead_or_set_p' checks, so also check for it being
12439 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12441 unsigned int regno = REGNO (XEXP (note, 0));
12443 /* Similarly, if the instruction on which we want to place
12444 the note is a noop, we'll need do a global live update
12445 after we remove them in delete_noop_moves. */
12446 if (noop_move_p (place))
12447 SET_BIT (refresh_blocks, this_basic_block->index);
12449 if (dead_or_set_p (place, XEXP (note, 0))
12450 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12452 /* Unless the register previously died in PLACE, clear
12453 last_death. [I no longer understand why this is
12455 if (reg_stat[regno].last_death != place)
12456 reg_stat[regno].last_death = 0;
12460 reg_stat[regno].last_death = place;
12462 /* If this is a death note for a hard reg that is occupying
12463 multiple registers, ensure that we are still using all
12464 parts of the object. If we find a piece of the object
12465 that is unused, we must arrange for an appropriate REG_DEAD
12466 note to be added for it. However, we can't just emit a USE
12467 and tag the note to it, since the register might actually
12468 be dead; so we recourse, and the recursive call then finds
12469 the previous insn that used this register. */
12471 if (place && regno < FIRST_PSEUDO_REGISTER
12472 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
12474 unsigned int endregno
12475 = regno + hard_regno_nregs[regno]
12476 [GET_MODE (XEXP (note, 0))];
12480 for (i = regno; i < endregno; i++)
12481 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12482 && ! find_regno_fusage (place, USE, i))
12483 || dead_or_set_regno_p (place, i))
12488 /* Put only REG_DEAD notes for pieces that are
12489 not already dead or set. */
12491 for (i = regno; i < endregno;
12492 i += hard_regno_nregs[i][reg_raw_mode[i]])
12494 rtx piece = regno_reg_rtx[i];
12495 basic_block bb = this_basic_block;
12497 if (! dead_or_set_p (place, piece)
12498 && ! reg_bitfield_target_p (piece,
12502 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12504 distribute_notes (new_note, place, place,
12505 NULL_RTX, NULL_RTX, NULL_RTX);
12507 else if (! refers_to_regno_p (i, i + 1,
12508 PATTERN (place), 0)
12509 && ! find_regno_fusage (place, USE, i))
12510 for (tem = PREV_INSN (place); ;
12511 tem = PREV_INSN (tem))
12513 if (! INSN_P (tem))
12515 if (tem == BB_HEAD (bb))
12517 SET_BIT (refresh_blocks,
12518 this_basic_block->index);
12523 if (dead_or_set_p (tem, piece)
12524 || reg_bitfield_target_p (piece,
12528 = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12543 /* Any other notes should not be present at this point in the
12545 gcc_unreachable ();
12550 XEXP (note, 1) = REG_NOTES (place);
12551 REG_NOTES (place) = note;
12553 else if ((REG_NOTE_KIND (note) == REG_DEAD
12554 || REG_NOTE_KIND (note) == REG_UNUSED)
12555 && REG_P (XEXP (note, 0)))
12556 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12560 if ((REG_NOTE_KIND (note) == REG_DEAD
12561 || REG_NOTE_KIND (note) == REG_UNUSED)
12562 && REG_P (XEXP (note, 0)))
12563 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12565 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12566 REG_NOTE_KIND (note),
12568 REG_NOTES (place2));
12573 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12574 I3, I2, and I1 to new locations. This is also called to add a link
12575 pointing at I3 when I3's destination is changed. */
12578 distribute_links (rtx links)
12580 rtx link, next_link;
12582 for (link = links; link; link = next_link)
12588 next_link = XEXP (link, 1);
12590 /* If the insn that this link points to is a NOTE or isn't a single
12591 set, ignore it. In the latter case, it isn't clear what we
12592 can do other than ignore the link, since we can't tell which
12593 register it was for. Such links wouldn't be used by combine
12596 It is not possible for the destination of the target of the link to
12597 have been changed by combine. The only potential of this is if we
12598 replace I3, I2, and I1 by I3 and I2. But in that case the
12599 destination of I2 also remains unchanged. */
12601 if (NOTE_P (XEXP (link, 0))
12602 || (set = single_set (XEXP (link, 0))) == 0)
12605 reg = SET_DEST (set);
12606 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12607 || GET_CODE (reg) == STRICT_LOW_PART)
12608 reg = XEXP (reg, 0);
12610 /* A LOG_LINK is defined as being placed on the first insn that uses
12611 a register and points to the insn that sets the register. Start
12612 searching at the next insn after the target of the link and stop
12613 when we reach a set of the register or the end of the basic block.
12615 Note that this correctly handles the link that used to point from
12616 I3 to I2. Also note that not much searching is typically done here
12617 since most links don't point very far away. */
12619 for (insn = NEXT_INSN (XEXP (link, 0));
12620 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
12621 || BB_HEAD (this_basic_block->next_bb) != insn));
12622 insn = NEXT_INSN (insn))
12623 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12625 if (reg_referenced_p (reg, PATTERN (insn)))
12629 else if (CALL_P (insn)
12630 && find_reg_fusage (insn, USE, reg))
12635 else if (INSN_P (insn) && reg_set_p (reg, insn))
12638 /* If we found a place to put the link, place it there unless there
12639 is already a link to the same insn as LINK at that point. */
12645 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12646 if (XEXP (link2, 0) == XEXP (link, 0))
12651 XEXP (link, 1) = LOG_LINKS (place);
12652 LOG_LINKS (place) = link;
12654 /* Set added_links_insn to the earliest insn we added a
12656 if (added_links_insn == 0
12657 || INSN_CUID (added_links_insn) > INSN_CUID (place))
12658 added_links_insn = place;
12664 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12665 Check whether the expression pointer to by LOC is a register or
12666 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12667 Otherwise return zero. */
12670 unmentioned_reg_p_1 (rtx *loc, void *expr)
12675 && (REG_P (x) || MEM_P (x))
12676 && ! reg_mentioned_p (x, (rtx) expr))
12681 /* Check for any register or memory mentioned in EQUIV that is not
12682 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
12683 of EXPR where some registers may have been replaced by constants. */
12686 unmentioned_reg_p (rtx equiv, rtx expr)
12688 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
12691 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12694 insn_cuid (rtx insn)
12696 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12697 && NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE)
12698 insn = NEXT_INSN (insn);
12700 gcc_assert (INSN_UID (insn) <= max_uid_cuid);
12702 return INSN_CUID (insn);
12706 dump_combine_stats (FILE *file)
12710 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12711 combine_attempts, combine_merges, combine_extras, combine_successes);
12715 dump_combine_total_stats (FILE *file)
12719 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12720 total_attempts, total_merges, total_extras, total_successes);
12725 gate_handle_combine (void)
12727 return (optimize > 0);
12730 /* Try combining insns through substitution. */
12732 rest_of_handle_combine (void)
12734 int rebuild_jump_labels_after_combine
12735 = combine_instructions (get_insns (), max_reg_num ());
12737 /* Combining insns may have turned an indirect jump into a
12738 direct jump. Rebuild the JUMP_LABEL fields of jumping
12740 if (rebuild_jump_labels_after_combine)
12742 timevar_push (TV_JUMP);
12743 rebuild_jump_labels (get_insns ());
12744 timevar_pop (TV_JUMP);
12746 delete_dead_jumptables ();
12747 cleanup_cfg (CLEANUP_EXPENSIVE | CLEANUP_UPDATE_LIFE);
12751 struct tree_opt_pass pass_combine =
12753 "combine", /* name */
12754 gate_handle_combine, /* gate */
12755 rest_of_handle_combine, /* execute */
12758 0, /* static_pass_number */
12759 TV_COMBINE, /* tv_id */
12760 0, /* properties_required */
12761 0, /* properties_provided */
12762 0, /* properties_destroyed */
12763 0, /* todo_flags_start */
12765 TODO_ggc_collect, /* todo_flags_finish */
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