sys/dev/netif/bge/if_bge.c

   1 /*
   2  * Copyright (c) 2001 Wind River Systems
   3  * Copyright (c) 1997, 1998, 1999, 2001
   4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Bill Paul.
  17  * 4. Neither the name of the author nor the names of any co-contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  31  * THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.29 2003/12/01 21:06:59 ambrisko Exp $
  34  * $DragonFly: src/sys/dev/netif/bge/if_bge.c,v 1.40 2005/06/14 14:19:22 joerg Exp $
  35  *
  36  */
  37
  38 /*
  39  * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
  40  *
  41  * Written by Bill Paul <wpaul@windriver.com>
  42  * Senior Engineer, Wind River Systems
  43  */
  44
  45 /*
  46  * The Broadcom BCM5700 is based on technology originally developed by
  47  * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
  48  * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
  49  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
  50  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
  51  * frames, highly configurable RX filtering, and 16 RX and TX queues
  52  * (which, along with RX filter rules, can be used for QOS applications).
  53  * Other features, such as TCP segmentation, may be available as part
  54  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
  55  * firmware images can be stored in hardware and need not be compiled
  56  * into the driver.
  57  *
  58  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
  59  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
  60  *
  61  * The BCM5701 is a single-chip solution incorporating both the BCM5700
  62  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
  63  * does not support external SSRAM.
  64  *
  65  * Broadcom also produces a variation of the BCM5700 under the "Altima"
  66  * brand name, which is functionally similar but lacks PCI-X support.
  67  *
  68  * Without external SSRAM, you can only have at most 4 TX rings,
  69  * and the use of the mini RX ring is disabled. This seems to imply
  70  * that these features are simply not available on the BCM5701. As a
  71  * result, this driver does not implement any support for the mini RX
  72  * ring.
  73  */
  74
  75 #include <sys/param.h>
  76 #include <sys/systm.h>
  77 #include <sys/sockio.h>
  78 #include <sys/mbuf.h>
  79 #include <sys/malloc.h>
  80 #include <sys/kernel.h>
  81 #include <sys/socket.h>
  82 #include <sys/queue.h>
  83 #include <sys/thread2.h>
  84
  85 #include <net/if.h>
  86 #include <net/ifq_var.h>
  87 #include <net/if_arp.h>
  88 #include <net/ethernet.h>
  89 #include <net/if_dl.h>
  90 #include <net/if_media.h>
  91
  92 #include <net/bpf.h>
  93
  94 #include <net/if_types.h>
  95 #include <net/vlan/if_vlan_var.h>
  96
  97 #include <netinet/in_systm.h>
  98 #include <netinet/in.h>
  99 #include <netinet/ip.h>
 100
 101 #include <vm/vm.h>              /* for vtophys */
 102 #include <vm/pmap.h>            /* for vtophys */
 103 #include <machine/resource.h>
 104 #include <sys/bus.h>
 105 #include <sys/rman.h>
 106
 107 #include <dev/netif/mii_layer/mii.h>
 108 #include <dev/netif/mii_layer/miivar.h>
 109 #include <dev/netif/mii_layer/miidevs.h>
 110 #include <dev/netif/mii_layer/brgphyreg.h>
 111
 112 #include <bus/pci/pcidevs.h>
 113 #include <bus/pci/pcireg.h>
 114 #include <bus/pci/pcivar.h>
 115
 116 #include "if_bgereg.h"
 117
 118 #define BGE_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
 119
 120 /* "controller miibus0" required.  See GENERIC if you get errors here. */
 121 #include "miibus_if.h"
 122
 123 /*
 124  * Various supported device vendors/types and their names. Note: the
 125  * spec seems to indicate that the hardware still has Alteon's vendor
 126  * ID burned into it, though it will always be overriden by the vendor
 127  * ID in the EEPROM. Just to be safe, we cover all possibilities.
 128  */
 129 #define BGE_DEVDESC_MAX         64      /* Maximum device description length */
 130
 131 static struct bge_type bge_devs[] = {
 132         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
 133                 "Broadcom BCM5700 Gigabit Ethernet" },
 134         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
 135                 "Broadcom BCM5701 Gigabit Ethernet" },
 136         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700,
 137                 "Broadcom BCM5700 Gigabit Ethernet" },
 138         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701,
 139                 "Broadcom BCM5701 Gigabit Ethernet" },
 140         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X,
 141                 "Broadcom BCM5702X Gigabit Ethernet" },
 142         { PCI_VENDOR_BROADCOM, BCOM_DEVICEID_BCM5702X,
 143                 "Broadcom BCM5702X Gigabit Ethernet" },
 144         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X,
 145                 "Broadcom BCM5703X Gigabit Ethernet" },
 146         { PCI_VENDOR_BROADCOM, BCOM_DEVICEID_BCM5703X,
 147                 "Broadcom BCM5703X Gigabit Ethernet" },
 148         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C,
 149                 "Broadcom BCM5704C Dual Gigabit Ethernet" },
 150         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S,
 151                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
 152         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705,
 153                 "Broadcom BCM5705 Gigabit Ethernet" },
 154         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M,
 155                 "Broadcom BCM5705M Gigabit Ethernet" },
 156         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705_ALT,
 157                 "Broadcom BCM5705M Gigabit Ethernet" },
 158         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782,
 159                 "Broadcom BCM5782 Gigabit Ethernet" },
 160         { PCI_VENDOR_BROADCOM, BCOM_DEVICEID_BCM5788,
 161                 "Broadcom BCM5788 Gigabit Ethernet" },
 162         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901,
 163                 "Broadcom BCM5901 Fast Ethernet" },
 164         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2,
 165                 "Broadcom BCM5901A2 Fast Ethernet" },
 166         { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
 167                 "SysKonnect Gigabit Ethernet" },
 168         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000,
 169                 "Altima AC1000 Gigabit Ethernet" },
 170         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001,
 171                 "Altima AC1002 Gigabit Ethernet" },
 172         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100,
 173                 "Altima AC9100 Gigabit Ethernet" },
 174         { 0, 0, NULL }
 175 };
 176
 177 static int      bge_probe(device_t);
 178 static int      bge_attach(device_t);
 179 static int      bge_detach(device_t);
 180 static void     bge_release_resources(struct bge_softc *);
 181 static void     bge_txeof(struct bge_softc *);
 182 static void     bge_rxeof(struct bge_softc *);
 183
 184 static void     bge_tick(void *);
 185 static void     bge_stats_update(struct bge_softc *);
 186 static void     bge_stats_update_regs(struct bge_softc *);
 187 static int      bge_encap(struct bge_softc *, struct mbuf *, uint32_t *);
 188
 189 static void     bge_intr(void *);
 190 static void     bge_start(struct ifnet *);
 191 static int      bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 192 static void     bge_init(void *);
 193 static void     bge_stop(struct bge_softc *);
 194 static void     bge_watchdog(struct ifnet *);
 195 static void     bge_shutdown(device_t);
 196 static int      bge_ifmedia_upd(struct ifnet *);
 197 static void     bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 198
 199 static uint8_t  bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *);
 200 static int      bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t);
 201
 202 static void     bge_setmulti(struct bge_softc *);
 203
 204 static void     bge_handle_events(struct bge_softc *);
 205 static int      bge_alloc_jumbo_mem(struct bge_softc *);
 206 static void     bge_free_jumbo_mem(struct bge_softc *);
 207 static struct bge_jslot
 208                 *bge_jalloc(struct bge_softc *);
 209 static void     bge_jfree(void *);
 210 static void     bge_jref(void *);
 211 static int      bge_newbuf_std(struct bge_softc *, int, struct mbuf *);
 212 static int      bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *);
 213 static int      bge_init_rx_ring_std(struct bge_softc *);
 214 static void     bge_free_rx_ring_std(struct bge_softc *);
 215 static int      bge_init_rx_ring_jumbo(struct bge_softc *);
 216 static void     bge_free_rx_ring_jumbo(struct bge_softc *);
 217 static void     bge_free_tx_ring(struct bge_softc *);
 218 static int      bge_init_tx_ring(struct bge_softc *);
 219
 220 static int      bge_chipinit(struct bge_softc *);
 221 static int      bge_blockinit(struct bge_softc *);
 222
 223 #ifdef notdef
 224 static uint8_t  bge_vpd_readbyte(struct bge_softc *, uint32_t);
 225 static void     bge_vpd_read_res(struct bge_softc *, struct vpd_res *, uint32_t);
 226 static void     bge_vpd_read(struct bge_softc *);
 227 #endif
 228
 229 static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t);
 230 static void     bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t);
 231 #ifdef notdef
 232 static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t);
 233 #endif
 234 static void     bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t);
 235
 236 static int      bge_miibus_readreg(device_t, int, int);
 237 static int      bge_miibus_writereg(device_t, int, int, int);
 238 static void     bge_miibus_statchg(device_t);
 239
 240 static void     bge_reset(struct bge_softc *);
 241
 242 static device_method_t bge_methods[] = {
 243         /* Device interface */
 244         DEVMETHOD(device_probe,         bge_probe),
 245         DEVMETHOD(device_attach,        bge_attach),
 246         DEVMETHOD(device_detach,        bge_detach),
 247         DEVMETHOD(device_shutdown,      bge_shutdown),
 248
 249         /* bus interface */
 250         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 251         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 252
 253         /* MII interface */
 254         DEVMETHOD(miibus_readreg,       bge_miibus_readreg),
 255         DEVMETHOD(miibus_writereg,      bge_miibus_writereg),
 256         DEVMETHOD(miibus_statchg,       bge_miibus_statchg),
 257
 258         { 0, 0 }
 259 };
 260
 261 static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc));
 262 static devclass_t bge_devclass;
 263
 264 DECLARE_DUMMY_MODULE(if_bge);
 265 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, 0, 0);
 266 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
 267
 268 static uint32_t
 269 bge_readmem_ind(struct bge_softc *sc, uint32_t off)
 270 {
 271         device_t dev = sc->bge_dev;
 272
 273         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 274         return(pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4));
 275 }
 276
 277 static void
 278 bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
 279 {
 280         device_t dev = sc->bge_dev;
 281
 282         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 283         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
 284 }
 285
 286 #ifdef notdef
 287 static uint32_t
 288 bge_readreg_ind(struct bge_softc *sc, uin32_t off)
 289 {
 290         device_t dev = sc->bge_dev;
 291
 292         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 293         return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
 294 }
 295 #endif
 296
 297 static void
 298 bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
 299 {
 300         device_t dev = sc->bge_dev;
 301
 302         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 303         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
 304 }
 305
 306 #ifdef notdef
 307 static uint8_t
 308 bge_vpd_readbyte(struct bge_softc *sc, uint32_t addr)
 309 {
 310         device_t dev = sc->bge_dev;
 311         uint32_t val;
 312         int i;
 313
 314         pci_write_config(dev, BGE_PCI_VPD_ADDR, addr, 2);
 315         for (i = 0; i < BGE_TIMEOUT * 10; i++) {
 316                 DELAY(10);
 317                 if (pci_read_config(dev, BGE_PCI_VPD_ADDR, 2) & BGE_VPD_FLAG)
 318                         break;
 319         }
 320
 321         if (i == BGE_TIMEOUT) {
 322                 device_printf(sc->bge_dev, "VPD read timed out\n");
 323                 return(0);
 324         }
 325
 326         val = pci_read_config(dev, BGE_PCI_VPD_DATA, 4);
 327
 328         return((val >> ((addr % 4) * 8)) & 0xFF);
 329 }
 330
 331 static void
 332 bge_vpd_read_res(struct bge_softc *sc, struct vpd_res *res, uint32_t addr)
 333 {
 334         size_t i;
 335         uint8_t *ptr;
 336
 337         ptr = (uint8_t *)res;
 338         for (i = 0; i < sizeof(struct vpd_res); i++)
 339                 ptr[i] = bge_vpd_readbyte(sc, i + addr);
 340
 341         return;
 342 }
 343
 344 static void
 345 bge_vpd_read(struct bge_softc *sc)
 346 {
 347         int pos = 0, i;
 348         struct vpd_res res;
 349
 350         if (sc->bge_vpd_prodname != NULL)
 351                 free(sc->bge_vpd_prodname, M_DEVBUF);
 352         if (sc->bge_vpd_readonly != NULL)
 353                 free(sc->bge_vpd_readonly, M_DEVBUF);
 354         sc->bge_vpd_prodname = NULL;
 355         sc->bge_vpd_readonly = NULL;
 356
 357         bge_vpd_read_res(sc, &res, pos);
 358
 359         if (res.vr_id != VPD_RES_ID) {
 360                 device_printf(sc->bge_dev,
 361                               "bad VPD resource id: expected %x got %x\n",
 362                               VPD_RES_ID, res.vr_id);
 363                 return;
 364         }
 365
 366         pos += sizeof(res);
 367         sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_INTWAIT);
 368         for (i = 0; i < res.vr_len; i++)
 369                 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos);
 370         sc->bge_vpd_prodname[i] = '\0';
 371         pos += i;
 372
 373         bge_vpd_read_res(sc, &res, pos);
 374
 375         if (res.vr_id != VPD_RES_READ) {
 376                 device_printf(sc->bge_dev,
 377                               "bad VPD resource id: expected %x got %x\n",
 378                               VPD_RES_READ, res.vr_id);
 379                 return;
 380         }
 381
 382         pos += sizeof(res);
 383         sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_INTWAIT);
 384         for (i = 0; i < res.vr_len + 1; i++)
 385                 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos);
 386 }
 387 #endif
 388
 389 /*
 390  * Read a byte of data stored in the EEPROM at address 'addr.' The
 391  * BCM570x supports both the traditional bitbang interface and an
 392  * auto access interface for reading the EEPROM. We use the auto
 393  * access method.
 394  */
 395 static uint8_t
 396 bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest)
 397 {
 398         int i;
 399         uint32_t byte = 0;
 400
 401         /*
 402          * Enable use of auto EEPROM access so we can avoid
 403          * having to use the bitbang method.
 404          */
 405         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
 406
 407         /* Reset the EEPROM, load the clock period. */
 408         CSR_WRITE_4(sc, BGE_EE_ADDR,
 409             BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
 410         DELAY(20);
 411
 412         /* Issue the read EEPROM command. */
 413         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
 414
 415         /* Wait for completion */
 416         for(i = 0; i < BGE_TIMEOUT * 10; i++) {
 417                 DELAY(10);
 418                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
 419                         break;
 420         }
 421
 422         if (i == BGE_TIMEOUT) {
 423                 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
 424                 return(0);
 425         }
 426
 427         /* Get result. */
 428         byte = CSR_READ_4(sc, BGE_EE_DATA);
 429
 430         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
 431
 432         return(0);
 433 }
 434
 435 /*
 436  * Read a sequence of bytes from the EEPROM.
 437  */
 438 static int
 439 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len)
 440 {
 441         size_t i;
 442         int err;
 443         uint8_t byte;
 444
 445         for (byte = 0, err = 0, i = 0; i < len; i++) {
 446                 err = bge_eeprom_getbyte(sc, off + i, &byte);
 447                 if (err)
 448                         break;
 449                 *(dest + i) = byte;
 450         }
 451
 452         return(err ? 1 : 0);
 453 }
 454
 455 static int
 456 bge_miibus_readreg(device_t dev, int phy, int reg)
 457 {
 458         struct bge_softc *sc;
 459         struct ifnet *ifp;
 460         uint32_t val, autopoll;
 461         int i;
 462
 463         sc = device_get_softc(dev);
 464         ifp = &sc->arpcom.ac_if;
 465
 466         /*
 467          * Broadcom's own driver always assumes the internal
 468          * PHY is at GMII address 1. On some chips, the PHY responds
 469          * to accesses at all addresses, which could cause us to
 470          * bogusly attach the PHY 32 times at probe type. Always
 471          * restricting the lookup to address 1 is simpler than
 472          * trying to figure out which chips revisions should be
 473          * special-cased.
 474          */
 475         if (phy != 1)
 476                 return(0);
 477
 478         /* Reading with autopolling on may trigger PCI errors */
 479         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 480         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 481                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 482                 DELAY(40);
 483         }
 484
 485         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY|
 486             BGE_MIPHY(phy)|BGE_MIREG(reg));
 487
 488         for (i = 0; i < BGE_TIMEOUT; i++) {
 489                 val = CSR_READ_4(sc, BGE_MI_COMM);
 490                 if (!(val & BGE_MICOMM_BUSY))
 491                         break;
 492         }
 493
 494         if (i == BGE_TIMEOUT) {
 495                 if_printf(ifp, "PHY read timed out\n");
 496                 val = 0;
 497                 goto done;
 498         }
 499
 500         val = CSR_READ_4(sc, BGE_MI_COMM);
 501
 502 done:
 503         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 504                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 505                 DELAY(40);
 506         }
 507
 508         if (val & BGE_MICOMM_READFAIL)
 509                 return(0);
 510
 511         return(val & 0xFFFF);
 512 }
 513
 514 static int
 515 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
 516 {
 517         struct bge_softc *sc;
 518         uint32_t autopoll;
 519         int i;
 520
 521         sc = device_get_softc(dev);
 522
 523         /* Reading with autopolling on may trigger PCI errors */
 524         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 525         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 526                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 527                 DELAY(40);
 528         }
 529
 530         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY|
 531             BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
 532
 533         for (i = 0; i < BGE_TIMEOUT; i++) {
 534                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY))
 535                         break;
 536         }
 537
 538         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 539                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 540                 DELAY(40);
 541         }
 542
 543         if (i == BGE_TIMEOUT) {
 544                 if_printf(&sc->arpcom.ac_if, "PHY read timed out\n");
 545                 return(0);
 546         }
 547
 548         return(0);
 549 }
 550
 551 static void
 552 bge_miibus_statchg(device_t dev)
 553 {
 554         struct bge_softc *sc;
 555         struct mii_data *mii;
 556
 557         sc = device_get_softc(dev);
 558         mii = device_get_softc(sc->bge_miibus);
 559
 560         BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
 561         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
 562                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
 563         } else {
 564                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
 565         }
 566
 567         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
 568                 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 569         } else {
 570                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 571         }
 572 }
 573
 574 /*
 575  * Handle events that have triggered interrupts.
 576  */
 577 static void
 578 bge_handle_events(struct bge_softc *sc)
 579 {
 580 }
 581
 582 /*
 583  * Memory management for jumbo frames.
 584  */
 585 static int
 586 bge_alloc_jumbo_mem(struct bge_softc *sc)
 587 {
 588         struct bge_jslot *entry;
 589         caddr_t ptr;
 590         int i;
 591
 592         /* Grab a big chunk o' storage. */
 593         sc->bge_cdata.bge_jumbo_buf = contigmalloc(BGE_JMEM, M_DEVBUF,
 594                 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
 595
 596         if (sc->bge_cdata.bge_jumbo_buf == NULL) {
 597                 if_printf(&sc->arpcom.ac_if, "no memory for jumbo buffers!\n");
 598                 return(ENOBUFS);
 599         }
 600
 601         SLIST_INIT(&sc->bge_jfree_listhead);
 602
 603         /*
 604          * Now divide it up into 9K pieces and save the addresses
 605          * in an array. Note that we play an evil trick here by using
 606          * the first few bytes in the buffer to hold the the address
 607          * of the softc structure for this interface. This is because
 608          * bge_jfree() needs it, but it is called by the mbuf management
 609          * code which will not pass it to us explicitly.
 610          */
 611         ptr = sc->bge_cdata.bge_jumbo_buf;
 612         for (i = 0; i < BGE_JSLOTS; i++) {
 613                 entry = &sc->bge_cdata.bge_jslots[i];
 614                 entry->bge_sc = sc;
 615                 entry->bge_buf = ptr;
 616                 entry->bge_inuse = 0;
 617                 entry->bge_slot = i;
 618                 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
 619                 ptr += BGE_JLEN;
 620         }
 621
 622         return(0);
 623 }
 624
 625 static void
 626 bge_free_jumbo_mem(struct bge_softc *sc)
 627 {
 628         if (sc->bge_cdata.bge_jumbo_buf)
 629                 contigfree(sc->bge_cdata.bge_jumbo_buf, BGE_JMEM, M_DEVBUF);
 630 }
 631
 632 /*
 633  * Allocate a jumbo buffer.
 634  */
 635 static struct bge_jslot *
 636 bge_jalloc(struct bge_softc *sc)
 637 {
 638         struct bge_jslot *entry;
 639
 640         entry = SLIST_FIRST(&sc->bge_jfree_listhead);
 641
 642         if (entry == NULL) {
 643                 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
 644                 return(NULL);
 645         }
 646
 647         SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link);
 648         entry->bge_inuse = 1;
 649         return(entry);
 650 }
 651
 652 /*
 653  * Adjust usage count on a jumbo buffer.
 654  */
 655 static void
 656 bge_jref(void *arg)
 657 {
 658         struct bge_jslot *entry = (struct bge_jslot *)arg;
 659         struct bge_softc *sc = entry->bge_sc;
 660
 661         if (sc == NULL)
 662                 panic("bge_jref: can't find softc pointer!");
 663
 664         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry)
 665                 panic("bge_jref: asked to reference buffer "
 666                     "that we don't manage!");
 667         else if (entry->bge_inuse == 0)
 668                 panic("bge_jref: buffer already free!");
 669         else
 670                 entry->bge_inuse++;
 671 }
 672
 673 /*
 674  * Release a jumbo buffer.
 675  */
 676 static void
 677 bge_jfree(void *arg)
 678 {
 679         struct bge_jslot *entry = (struct bge_jslot *)arg;
 680         struct bge_softc *sc = entry->bge_sc;
 681
 682         if (sc == NULL)
 683                 panic("bge_jfree: can't find softc pointer!");
 684
 685         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry)
 686                 panic("bge_jfree: asked to free buffer that we don't manage!");
 687         else if (entry->bge_inuse == 0)
 688                 panic("bge_jfree: buffer already free!");
 689         else if (--entry->bge_inuse == 0)
 690                 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
 691 }
 692
 693
 694 /*
 695  * Intialize a standard receive ring descriptor.
 696  */
 697 static int
 698 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m)
 699 {
 700         struct mbuf *m_new = NULL;
 701         struct bge_rx_bd *r;
 702
 703         if (m == NULL) {
 704                 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
 705                 if (m_new == NULL)
 706                         return (ENOBUFS);
 707                 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 708         } else {
 709                 m_new = m;
 710                 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 711                 m_new->m_data = m_new->m_ext.ext_buf;
 712         }
 713
 714         if (!sc->bge_rx_alignment_bug)
 715                 m_adj(m_new, ETHER_ALIGN);
 716         sc->bge_cdata.bge_rx_std_chain[i] = m_new;
 717         r = &sc->bge_rdata->bge_rx_std_ring[i];
 718         BGE_HOSTADDR(r->bge_addr, vtophys(mtod(m_new, caddr_t)));
 719         r->bge_flags = BGE_RXBDFLAG_END;
 720         r->bge_len = m_new->m_len;
 721         r->bge_idx = i;
 722
 723         return(0);
 724 }
 725
 726 /*
 727  * Initialize a jumbo receive ring descriptor. This allocates
 728  * a jumbo buffer from the pool managed internally by the driver.
 729  */
 730 static int
 731 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m)
 732 {
 733         struct mbuf *m_new = NULL;
 734         struct bge_rx_bd *r;
 735
 736         if (m == NULL) {
 737                 struct bge_jslot *buf;
 738
 739                 /* Allocate the mbuf. */
 740                 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
 741                 if (m_new == NULL)
 742                         return(ENOBUFS);
 743
 744                 /* Allocate the jumbo buffer */
 745                 buf = bge_jalloc(sc);
 746                 if (buf == NULL) {
 747                         m_freem(m_new);
 748                         if_printf(&sc->arpcom.ac_if, "jumbo allocation failed "
 749                             "-- packet dropped!\n");
 750                         return(ENOBUFS);
 751                 }
 752
 753                 /* Attach the buffer to the mbuf. */
 754                 m_new->m_ext.ext_arg = buf;
 755                 m_new->m_ext.ext_buf = buf->bge_buf;
 756                 m_new->m_ext.ext_free = bge_jfree;
 757                 m_new->m_ext.ext_ref = bge_jref;
 758                 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
 759
 760                 m_new->m_data = m_new->m_ext.ext_buf;
 761                 m_new->m_flags |= M_EXT;
 762                 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
 763         } else {
 764                 m_new = m;
 765                 m_new->m_data = m_new->m_ext.ext_buf;
 766                 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
 767         }
 768
 769         if (!sc->bge_rx_alignment_bug)
 770                 m_adj(m_new, ETHER_ALIGN);
 771         /* Set up the descriptor. */
 772         r = &sc->bge_rdata->bge_rx_jumbo_ring[i];
 773         sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new;
 774         BGE_HOSTADDR(r->bge_addr, vtophys(mtod(m_new, caddr_t)));
 775         r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
 776         r->bge_len = m_new->m_len;
 777         r->bge_idx = i;
 778
 779         return(0);
 780 }
 781
 782 /*
 783  * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
 784  * that's 1MB or memory, which is a lot. For now, we fill only the first
 785  * 256 ring entries and hope that our CPU is fast enough to keep up with
 786  * the NIC.
 787  */
 788 static int
 789 bge_init_rx_ring_std(struct bge_softc *sc)
 790 {
 791         int i;
 792
 793         for (i = 0; i < BGE_SSLOTS; i++) {
 794                 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS)
 795                         return(ENOBUFS);
 796         };
 797
 798         sc->bge_std = i - 1;
 799         CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
 800
 801         return(0);
 802 }
 803
 804 static void
 805 bge_free_rx_ring_std(struct bge_softc *sc)
 806 {
 807         int i;
 808
 809         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
 810                 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
 811                         m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
 812                         sc->bge_cdata.bge_rx_std_chain[i] = NULL;
 813                 }
 814                 bzero(&sc->bge_rdata->bge_rx_std_ring[i],
 815                     sizeof(struct bge_rx_bd));
 816         }
 817 }
 818
 819 static int
 820 bge_init_rx_ring_jumbo(struct bge_softc *sc)
 821 {
 822         int i;
 823         struct bge_rcb *rcb;
 824
 825         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
 826                 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
 827                         return(ENOBUFS);
 828         };
 829
 830         sc->bge_jumbo = i - 1;
 831
 832         rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
 833         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
 834         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
 835
 836         CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
 837
 838         return(0);
 839 }
 840
 841 static void
 842 bge_free_rx_ring_jumbo(struct bge_softc *sc)
 843 {
 844         int i;
 845
 846         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
 847                 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
 848                         m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
 849                         sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
 850                 }
 851                 bzero(&sc->bge_rdata->bge_rx_jumbo_ring[i],
 852                     sizeof(struct bge_rx_bd));
 853         }
 854 }
 855
 856 static void
 857 bge_free_tx_ring(struct bge_softc *sc)
 858 {
 859         int i;
 860
 861         if (sc->bge_rdata->bge_tx_ring == NULL)
 862                 return;
 863
 864         for (i = 0; i < BGE_TX_RING_CNT; i++) {
 865                 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
 866                         m_freem(sc->bge_cdata.bge_tx_chain[i]);
 867                         sc->bge_cdata.bge_tx_chain[i] = NULL;
 868                 }
 869                 bzero(&sc->bge_rdata->bge_tx_ring[i],
 870                     sizeof(struct bge_tx_bd));
 871         }
 872 }
 873
 874 static int
 875 bge_init_tx_ring(struct bge_softc *sc)
 876 {
 877         sc->bge_txcnt = 0;
 878         sc->bge_tx_saved_considx = 0;
 879
 880         CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0);
 881         /* 5700 b2 errata */
 882         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
 883                 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0);
 884
 885         CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
 886         /* 5700 b2 errata */
 887         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
 888                 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
 889
 890         return(0);
 891 }
 892
 893 static void
 894 bge_setmulti(struct bge_softc *sc)
 895 {
 896         struct ifnet *ifp;
 897         struct ifmultiaddr *ifma;
 898         uint32_t hashes[4] = { 0, 0, 0, 0 };
 899         int h, i;
 900
 901         ifp = &sc->arpcom.ac_if;
 902
 903         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
 904                 for (i = 0; i < 4; i++)
 905                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
 906                 return;
 907         }
 908
 909         /* First, zot all the existing filters. */
 910         for (i = 0; i < 4; i++)
 911                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
 912
 913         /* Now program new ones. */
 914         LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
 915                 if (ifma->ifma_addr->sa_family != AF_LINK)
 916                         continue;
 917                 h = ether_crc32_le(
 918                     LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
 919                     ETHER_ADDR_LEN) & 0x7f;
 920                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
 921         }
 922
 923         for (i = 0; i < 4; i++)
 924                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
 925 }
 926
 927 /*
 928  * Do endian, PCI and DMA initialization. Also check the on-board ROM
 929  * self-test results.
 930  */
 931 static int
 932 bge_chipinit(struct bge_softc *sc)
 933 {
 934         int i;
 935         uint32_t dma_rw_ctl;
 936
 937         /* Set endianness before we access any non-PCI registers. */
 938 #if BYTE_ORDER == BIG_ENDIAN
 939         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,
 940             BGE_BIGENDIAN_INIT, 4);
 941 #else
 942         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,
 943             BGE_LITTLEENDIAN_INIT, 4);
 944 #endif
 945
 946         /*
 947          * Check the 'ROM failed' bit on the RX CPU to see if
 948          * self-tests passed.
 949          */
 950         if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) {
 951                 if_printf(&sc->arpcom.ac_if,
 952                           "RX CPU self-diagnostics failed!\n");
 953                 return(ENODEV);
 954         }
 955
 956         /* Clear the MAC control register */
 957         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
 958
 959         /*
 960          * Clear the MAC statistics block in the NIC's
 961          * internal memory.
 962          */
 963         for (i = BGE_STATS_BLOCK;
 964             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
 965                 BGE_MEMWIN_WRITE(sc, i, 0);
 966
 967         for (i = BGE_STATUS_BLOCK;
 968             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
 969                 BGE_MEMWIN_WRITE(sc, i, 0);
 970
 971         /* Set up the PCI DMA control register. */
 972         if (pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
 973             BGE_PCISTATE_PCI_BUSMODE) {
 974                 /* Conventional PCI bus */
 975                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
 976                     (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
 977                     (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
 978                     (0x0F);
 979         } else {
 980                 /* PCI-X bus */
 981                 /*
 982                  * The 5704 uses a different encoding of read/write
 983                  * watermarks.
 984                  */
 985                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
 986                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
 987                             (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
 988                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
 989                 else
 990                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
 991                             (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
 992                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
 993                             (0x0F);
 994
 995                 /*
 996                  * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
 997                  * for hardware bugs.
 998                  */
 999                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1000                     sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1001                         uint32_t tmp;
1002
1003                         tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1004                         if (tmp == 0x6 || tmp == 0x7)
1005                                 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1006                 }
1007         }
1008
1009         if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1010             sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
1011             sc->bge_asicrev == BGE_ASICREV_BCM5705)
1012                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1013         pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1014
1015         /*
1016          * Set up general mode register.
1017          */
1018         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME|
1019             BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA|
1020             BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1021             BGE_MODECTL_TX_NO_PHDR_CSUM|BGE_MODECTL_RX_NO_PHDR_CSUM);
1022
1023         /*
1024          * Disable memory write invalidate.  Apparently it is not supported
1025          * properly by these devices.
1026          */
1027         PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1028
1029         /* Set the timer prescaler (always 66Mhz) */
1030         CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1031
1032         return(0);
1033 }
1034
1035 static int
1036 bge_blockinit(struct bge_softc *sc)
1037 {
1038         struct bge_rcb *rcb;
1039         volatile struct bge_rcb *vrcb;
1040         int i;
1041
1042         /*
1043          * Initialize the memory window pointer register so that
1044          * we can access the first 32K of internal NIC RAM. This will
1045          * allow us to set up the TX send ring RCBs and the RX return
1046          * ring RCBs, plus other things which live in NIC memory.
1047          */
1048         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1049
1050         /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1051
1052         if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
1053                 /* Configure mbuf memory pool */
1054                 if (sc->bge_extram) {
1055                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR,
1056                             BGE_EXT_SSRAM);
1057                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1058                                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1059                         else
1060                                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1061                 } else {
1062                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR,
1063                             BGE_BUFFPOOL_1);
1064                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1065                                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1066                         else
1067                                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1068                 }
1069
1070                 /* Configure DMA resource pool */
1071                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1072                     BGE_DMA_DESCRIPTORS);
1073                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1074         }
1075
1076         /* Configure mbuf pool watermarks */
1077         if (sc->bge_asicrev == BGE_ASICREV_BCM5705) {
1078                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1079                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1080         } else {
1081                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1082                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1083         }
1084         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1085
1086         /* Configure DMA resource watermarks */
1087         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1088         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1089
1090         /* Enable buffer manager */
1091         if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
1092                 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1093                     BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1094
1095                 /* Poll for buffer manager start indication */
1096                 for (i = 0; i < BGE_TIMEOUT; i++) {
1097                         if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1098                                 break;
1099                         DELAY(10);
1100                 }
1101
1102                 if (i == BGE_TIMEOUT) {
1103                         if_printf(&sc->arpcom.ac_if,
1104                                   "buffer manager failed to start\n");
1105                         return(ENXIO);
1106                 }
1107         }
1108
1109         /* Enable flow-through queues */
1110         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1111         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1112
1113         /* Wait until queue initialization is complete */
1114         for (i = 0; i < BGE_TIMEOUT; i++) {
1115                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1116                         break;
1117                 DELAY(10);
1118         }
1119
1120         if (i == BGE_TIMEOUT) {
1121                 if_printf(&sc->arpcom.ac_if,
1122                           "flow-through queue init failed\n");
1123                 return(ENXIO);
1124         }
1125
1126         /* Initialize the standard RX ring control block */
1127         rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb;
1128         BGE_HOSTADDR(rcb->bge_hostaddr,
1129             vtophys(&sc->bge_rdata->bge_rx_std_ring));
1130         if (sc->bge_asicrev == BGE_ASICREV_BCM5705)
1131                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1132         else
1133                 rcb->bge_maxlen_flags =
1134                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1135         if (sc->bge_extram)
1136                 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS;
1137         else
1138                 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1139         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1140         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1141         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1142         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1143
1144         /*
1145          * Initialize the jumbo RX ring control block
1146          * We set the 'ring disabled' bit in the flags
1147          * field until we're actually ready to start
1148          * using this ring (i.e. once we set the MTU
1149          * high enough to require it).
1150          */
1151         if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
1152                 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
1153                 BGE_HOSTADDR(rcb->bge_hostaddr,
1154                     vtophys(&sc->bge_rdata->bge_rx_jumbo_ring));
1155                 rcb->bge_maxlen_flags =
1156                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
1157                     BGE_RCB_FLAG_RING_DISABLED);
1158                 if (sc->bge_extram)
1159                         rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS;
1160                 else
1161                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1162                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1163                     rcb->bge_hostaddr.bge_addr_hi);
1164                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1165                     rcb->bge_hostaddr.bge_addr_lo);
1166                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1167                     rcb->bge_maxlen_flags);
1168                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1169
1170                 /* Set up dummy disabled mini ring RCB */
1171                 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb;
1172                 rcb->bge_maxlen_flags =
1173                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1174                 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1175                     rcb->bge_maxlen_flags);
1176         }
1177
1178         /*
1179          * Set the BD ring replentish thresholds. The recommended
1180          * values are 1/8th the number of descriptors allocated to
1181          * each ring.
1182          */
1183         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8);
1184         CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
1185
1186         /*
1187          * Disable all unused send rings by setting the 'ring disabled'
1188          * bit in the flags field of all the TX send ring control blocks.
1189          * These are located in NIC memory.
1190          */
1191         vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1192             BGE_SEND_RING_RCB);
1193         for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1194                 vrcb->bge_maxlen_flags =
1195                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1196                 vrcb->bge_nicaddr = 0;
1197                 vrcb++;
1198         }
1199
1200         /* Configure TX RCB 0 (we use only the first ring) */
1201         vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1202             BGE_SEND_RING_RCB);
1203         vrcb->bge_hostaddr.bge_addr_hi = 0;
1204         BGE_HOSTADDR(vrcb->bge_hostaddr, vtophys(&sc->bge_rdata->bge_tx_ring));
1205         vrcb->bge_nicaddr = BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT);
1206         if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
1207                 vrcb->bge_maxlen_flags =
1208                     BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0);
1209
1210         /* Disable all unused RX return rings */
1211         vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1212             BGE_RX_RETURN_RING_RCB);
1213         for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1214                 vrcb->bge_hostaddr.bge_addr_hi = 0;
1215                 vrcb->bge_hostaddr.bge_addr_lo = 0;
1216                 vrcb->bge_maxlen_flags =
1217                     BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
1218                     BGE_RCB_FLAG_RING_DISABLED);
1219                 vrcb->bge_nicaddr = 0;
1220                 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO +
1221                     (i * (sizeof(uint64_t))), 0);
1222                 vrcb++;
1223         }
1224
1225         /* Initialize RX ring indexes */
1226         CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1227         CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1228         CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1229
1230         /*
1231          * Set up RX return ring 0
1232          * Note that the NIC address for RX return rings is 0x00000000.
1233          * The return rings live entirely within the host, so the
1234          * nicaddr field in the RCB isn't used.
1235          */
1236         vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1237             BGE_RX_RETURN_RING_RCB);
1238         vrcb->bge_hostaddr.bge_addr_hi = 0;
1239         BGE_HOSTADDR(vrcb->bge_hostaddr,
1240             vtophys(&sc->bge_rdata->bge_rx_return_ring));
1241         vrcb->bge_nicaddr = 0x00000000;
1242         vrcb->bge_maxlen_flags =
1243             BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0);
1244
1245         /* Set random backoff seed for TX */
1246         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1247             sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1248             sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1249             sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1250             BGE_TX_BACKOFF_SEED_MASK);
1251
1252         /* Set inter-packet gap */
1253         CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1254
1255         /*
1256          * Specify which ring to use for packets that don't match
1257          * any RX rules.
1258          */
1259         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1260
1261         /*
1262          * Configure number of RX lists. One interrupt distribution
1263          * list, sixteen active lists, one bad frames class.
1264          */
1265         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1266
1267         /* Inialize RX list placement stats mask. */
1268         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1269         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1270
1271         /* Disable host coalescing until we get it set up */
1272         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1273
1274         /* Poll to make sure it's shut down. */
1275         for (i = 0; i < BGE_TIMEOUT; i++) {
1276                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1277                         break;
1278                 DELAY(10);
1279         }
1280
1281         if (i == BGE_TIMEOUT) {
1282                 if_printf(&sc->arpcom.ac_if,
1283                           "host coalescing engine failed to idle\n");
1284                 return(ENXIO);
1285         }
1286
1287         /* Set up host coalescing defaults */
1288         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1289         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1290         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1291         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1292         if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
1293                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1294                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1295         }
1296         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0);
1297         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0);
1298
1299         /* Set up address of statistics block */
1300         if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
1301                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 0);
1302                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1303                     vtophys(&sc->bge_rdata->bge_info.bge_stats));
1304
1305                 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1306                 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1307                 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1308         }
1309
1310         /* Set up address of status block */
1311         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 0);
1312         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1313             vtophys(&sc->bge_rdata->bge_status_block));
1314
1315         sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0;
1316         sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0;
1317
1318         /* Turn on host coalescing state machine */
1319         CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
1320
1321         /* Turn on RX BD completion state machine and enable attentions */
1322         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1323             BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1324
1325         /* Turn on RX list placement state machine */
1326         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1327
1328         /* Turn on RX list selector state machine. */
1329         if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
1330                 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1331
1332         /* Turn on DMA, clear stats */
1333         CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB|
1334             BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR|
1335             BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB|
1336             BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB|
1337             (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
1338
1339         /* Set misc. local control, enable interrupts on attentions */
1340         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1341
1342 #ifdef notdef
1343         /* Assert GPIO pins for PHY reset */
1344         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1345             BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1346         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1347             BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1348 #endif
1349
1350         /* Turn on DMA completion state machine */
1351         if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
1352                 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1353
1354         /* Turn on write DMA state machine */
1355         CSR_WRITE_4(sc, BGE_WDMA_MODE,
1356             BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS);
1357
1358         /* Turn on read DMA state machine */
1359         CSR_WRITE_4(sc, BGE_RDMA_MODE,
1360             BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS);
1361
1362         /* Turn on RX data completion state machine */
1363         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1364
1365         /* Turn on RX BD initiator state machine */
1366         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1367
1368         /* Turn on RX data and RX BD initiator state machine */
1369         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1370
1371         /* Turn on Mbuf cluster free state machine */
1372         if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
1373                 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1374
1375         /* Turn on send BD completion state machine */
1376         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1377
1378         /* Turn on send data completion state machine */
1379         CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
1380
1381         /* Turn on send data initiator state machine */
1382         CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1383
1384         /* Turn on send BD initiator state machine */
1385         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1386
1387         /* Turn on send BD selector state machine */
1388         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1389
1390         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1391         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1392             BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1393
1394         /* ack/clear link change events */
1395         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1396             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1397             BGE_MACSTAT_LINK_CHANGED);
1398
1399         /* Enable PHY auto polling (for MII/GMII only) */
1400         if (sc->bge_tbi) {
1401                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1402         } else {
1403                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
1404                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700)
1405                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1406                             BGE_EVTENB_MI_INTERRUPT);
1407         }
1408
1409         /* Enable link state change attentions. */
1410         BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1411
1412         return(0);
1413 }
1414
1415 /*
1416  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1417  * against our list and return its name if we find a match. Note
1418  * that since the Broadcom controller contains VPD support, we
1419  * can get the device name string from the controller itself instead
1420  * of the compiled-in string. This is a little slow, but it guarantees
1421  * we'll always announce the right product name.
1422  */
1423 static int
1424 bge_probe(device_t dev)
1425 {
1426         struct bge_softc *sc;
1427         struct bge_type *t;
1428         char *descbuf;
1429         uint16_t product, vendor;
1430
1431         product = pci_get_device(dev);
1432         vendor = pci_get_vendor(dev);
1433
1434         for (t = bge_devs; t->bge_name != NULL; t++) {
1435                 if (vendor == t->bge_vid && product == t->bge_did)
1436                         break;
1437         }
1438
1439         if (t->bge_name == NULL)
1440                 return(ENXIO);
1441
1442         sc = device_get_softc(dev);
1443 #ifdef notdef
1444         sc->bge_dev = dev;
1445
1446         bge_vpd_read(sc);
1447         device_set_desc(dev, sc->bge_vpd_prodname);
1448 #endif
1449         descbuf = malloc(BGE_DEVDESC_MAX, M_TEMP, M_WAITOK);
1450         snprintf(descbuf, BGE_DEVDESC_MAX, "%s, ASIC rev. %#04x", t->bge_name,
1451             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 16);
1452         device_set_desc_copy(dev, descbuf);
1453         if (pci_get_subvendor(dev) == PCI_VENDOR_DELL)
1454                 sc->bge_no_3_led = 1;
1455         free(descbuf, M_TEMP);
1456         return(0);
1457 }
1458
1459 static int
1460 bge_attach(device_t dev)
1461 {
1462         struct ifnet *ifp;
1463         struct bge_softc *sc;
1464         uint32_t hwcfg = 0;
1465         uint32_t mac_addr = 0;
1466         int error = 0, rid;
1467         uint8_t ether_addr[ETHER_ADDR_LEN];
1468
1469         sc = device_get_softc(dev);
1470         sc->bge_dev = dev;
1471         callout_init(&sc->bge_stat_timer);
1472
1473         /*
1474          * Map control/status registers.
1475          */
1476         pci_enable_busmaster(dev);
1477
1478         rid = BGE_PCI_BAR0;
1479         sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1480             RF_ACTIVE);
1481
1482         if (sc->bge_res == NULL) {
1483                 device_printf(dev, "couldn't map memory\n");
1484                 error = ENXIO;
1485                 return(error);
1486         }
1487
1488         sc->bge_btag = rman_get_bustag(sc->bge_res);
1489         sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
1490         sc->bge_vhandle = (vm_offset_t)rman_get_virtual(sc->bge_res);
1491
1492         /* Allocate interrupt */
1493         rid = 0;
1494
1495         sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1496             RF_SHAREABLE | RF_ACTIVE);
1497
1498         if (sc->bge_irq == NULL) {
1499                 device_printf(dev, "couldn't map interrupt\n");
1500                 error = ENXIO;
1501                 goto fail;
1502         }
1503
1504         ifp = &sc->arpcom.ac_if;
1505         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1506
1507         /* Try to reset the chip. */
1508         bge_reset(sc);
1509
1510         if (bge_chipinit(sc)) {
1511                 device_printf(dev, "chip initialization failed\n");
1512                 error = ENXIO;
1513                 goto fail;
1514         }
1515
1516         /*
1517          * Get station address from the EEPROM.
1518          */
1519         mac_addr = bge_readmem_ind(sc, 0x0c14);
1520         if ((mac_addr >> 16) == 0x484b) {
1521                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
1522                 ether_addr[1] = (uint8_t)mac_addr;
1523                 mac_addr = bge_readmem_ind(sc, 0x0c18);
1524                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
1525                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
1526                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
1527                 ether_addr[5] = (uint8_t)mac_addr;
1528         } else if (bge_read_eeprom(sc, ether_addr,
1529             BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
1530                 device_printf(dev, "failed to read station address\n");
1531                 error = ENXIO;
1532                 goto fail;
1533         }
1534
1535         /* Allocate the general information block and ring buffers. */
1536         sc->bge_rdata = contigmalloc(sizeof(struct bge_ring_data), M_DEVBUF,
1537             M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
1538
1539         if (sc->bge_rdata == NULL) {
1540                 error = ENXIO;
1541                 device_printf(dev, "no memory for list buffers!\n");
1542                 goto fail;
1543         }
1544
1545         bzero(sc->bge_rdata, sizeof(struct bge_ring_data));
1546
1547         /* Save ASIC rev. */
1548
1549         sc->bge_chipid =
1550             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &
1551             BGE_PCIMISCCTL_ASICREV;
1552         sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
1553         sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
1554
1555         /*
1556          * Try to allocate memory for jumbo buffers.
1557          * The 5705 does not appear to support jumbo frames.
1558          */
1559         if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
1560                 if (bge_alloc_jumbo_mem(sc)) {
1561                         device_printf(dev, "jumbo buffer allocation failed\n");
1562                         error = ENXIO;
1563                         goto fail;
1564                 }
1565         }
1566
1567         /* Set default tuneable values. */
1568         sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
1569         sc->bge_rx_coal_ticks = 150;
1570         sc->bge_tx_coal_ticks = 150;
1571         sc->bge_rx_max_coal_bds = 64;
1572         sc->bge_tx_max_coal_bds = 128;
1573
1574         /* 5705 limits RX return ring to 512 entries. */
1575         if (sc->bge_asicrev == BGE_ASICREV_BCM5705)
1576                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
1577         else
1578                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
1579
1580         /* Set up ifnet structure */
1581         ifp->if_softc = sc;
1582         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1583         ifp->if_ioctl = bge_ioctl;
1584         ifp->if_start = bge_start;
1585         ifp->if_watchdog = bge_watchdog;
1586         ifp->if_init = bge_init;
1587         ifp->if_mtu = ETHERMTU;
1588         ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
1589         ifq_set_ready(&ifp->if_snd);
1590         ifp->if_hwassist = BGE_CSUM_FEATURES;
1591         ifp->if_capabilities = IFCAP_HWCSUM;
1592         ifp->if_capenable = ifp->if_capabilities;
1593
1594         /*
1595          * Figure out what sort of media we have by checking the
1596          * hardware config word in the first 32k of NIC internal memory,
1597          * or fall back to examining the EEPROM if necessary.
1598          * Note: on some BCM5700 cards, this value appears to be unset.
1599          * If that's the case, we have to rely on identifying the NIC
1600          * by its PCI subsystem ID, as we do below for the SysKonnect
1601          * SK-9D41.
1602          */
1603         if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
1604                 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
1605         else {
1606                 bge_read_eeprom(sc, (caddr_t)&hwcfg,
1607                                 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg));
1608                 hwcfg = ntohl(hwcfg);
1609         }
1610
1611         if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
1612                 sc->bge_tbi = 1;
1613
1614         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
1615         if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41)
1616                 sc->bge_tbi = 1;
1617
1618         if (sc->bge_tbi) {
1619                 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
1620                     bge_ifmedia_upd, bge_ifmedia_sts);
1621                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
1622                 ifmedia_add(&sc->bge_ifmedia,
1623                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
1624                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
1625                 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
1626         } else {
1627                 /*
1628                  * Do transceiver setup.
1629                  */
1630                 if (mii_phy_probe(dev, &sc->bge_miibus,
1631                     bge_ifmedia_upd, bge_ifmedia_sts)) {
1632                         device_printf(dev, "MII without any PHY!\n");
1633                         error = ENXIO;
1634                         goto fail;
1635                 }
1636         }
1637
1638         /*
1639          * When using the BCM5701 in PCI-X mode, data corruption has
1640          * been observed in the first few bytes of some received packets.
1641          * Aligning the packet buffer in memory eliminates the corruption.
1642          * Unfortunately, this misaligns the packet payloads.  On platforms
1643          * which do not support unaligned accesses, we will realign the
1644          * payloads by copying the received packets.
1645          */
1646         switch (sc->bge_chipid) {
1647         case BGE_CHIPID_BCM5701_A0:
1648         case BGE_CHIPID_BCM5701_B0:
1649         case BGE_CHIPID_BCM5701_B2:
1650         case BGE_CHIPID_BCM5701_B5:
1651                 /* If in PCI-X mode, work around the alignment bug. */
1652                 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &
1653                     (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) ==
1654                     BGE_PCISTATE_PCI_BUSSPEED)
1655                         sc->bge_rx_alignment_bug = 1;
1656                 break;
1657         }
1658
1659         /*
1660          * Call MI attach routine.
1661          */
1662         ether_ifattach(ifp, ether_addr);
1663
1664         error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET,
1665                                bge_intr, sc, &sc->bge_intrhand, NULL);
1666         if (error) {
1667                 ether_ifdetach(ifp);
1668                 device_printf(dev, "couldn't set up irq\n");
1669                 goto fail;
1670         }
1671
1672         return(0);
1673
1674 fail:
1675         bge_detach(dev);
1676
1677         return(error);
1678 }
1679
1680 static int
1681 bge_detach(device_t dev)
1682 {
1683         struct bge_softc *sc = device_get_softc(dev);
1684         struct ifnet *ifp = &sc->arpcom.ac_if;
1685
1686         crit_enter();
1687
1688         if (device_is_attached(dev)) {
1689                 ether_ifdetach(ifp);
1690                 bge_stop(sc);
1691                 bge_reset(sc);
1692         }
1693
1694         if (sc->bge_tbi)
1695                 ifmedia_removeall(&sc->bge_ifmedia);
1696         if (sc->bge_miibus);
1697                 device_delete_child(dev, sc->bge_miibus);
1698         bus_generic_detach(dev);
1699
1700         bge_release_resources(sc);
1701
1702         crit_exit();
1703
1704         if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
1705                 bge_free_jumbo_mem(sc);
1706
1707         return(0);
1708 }
1709
1710 static void
1711 bge_release_resources(struct bge_softc *sc)
1712 {
1713         device_t dev;
1714
1715         dev = sc->bge_dev;
1716
1717         if (sc->bge_vpd_prodname != NULL)
1718                 free(sc->bge_vpd_prodname, M_DEVBUF);
1719
1720         if (sc->bge_vpd_readonly != NULL)
1721                 free(sc->bge_vpd_readonly, M_DEVBUF);
1722
1723         if (sc->bge_intrhand != NULL)
1724                 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
1725
1726         if (sc->bge_irq != NULL)
1727                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);
1728
1729         if (sc->bge_res != NULL)
1730                 bus_release_resource(dev, SYS_RES_MEMORY,
1731                     BGE_PCI_BAR0, sc->bge_res);
1732
1733         if (sc->bge_rdata != NULL)
1734                 contigfree(sc->bge_rdata, sizeof(struct bge_ring_data),
1735                            M_DEVBUF);
1736
1737         return;
1738 }
1739
1740 static void
1741 bge_reset(struct bge_softc *sc)
1742 {
1743         device_t dev;
1744         uint32_t cachesize, command, pcistate;
1745         int i, val = 0;
1746
1747         dev = sc->bge_dev;
1748
1749         /* Save some important PCI state. */
1750         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
1751         command = pci_read_config(dev, BGE_PCI_CMD, 4);
1752         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
1753
1754         pci_write_config(dev, BGE_PCI_MISC_CTL,
1755             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
1756             BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4);
1757
1758         /* Issue global reset */
1759         bge_writereg_ind(sc, BGE_MISC_CFG,
1760                          BGE_MISCCFG_RESET_CORE_CLOCKS | (65<<1));
1761
1762         DELAY(1000);
1763
1764         /* Reset some of the PCI state that got zapped by reset */
1765         pci_write_config(dev, BGE_PCI_MISC_CTL,
1766             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
1767             BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4);
1768         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
1769         pci_write_config(dev, BGE_PCI_CMD, command, 4);
1770         bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1));
1771
1772         /*
1773          * Prevent PXE restart: write a magic number to the
1774          * general communications memory at 0xB50.
1775          */
1776         bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
1777         /*
1778          * Poll the value location we just wrote until
1779          * we see the 1's complement of the magic number.
1780          * This indicates that the firmware initialization
1781          * is complete.
1782          */
1783         for (i = 0; i < BGE_TIMEOUT; i++) {
1784                 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
1785                 if (val == ~BGE_MAGIC_NUMBER)
1786                         break;
1787                 DELAY(10);
1788         }
1789
1790         if (i == BGE_TIMEOUT) {
1791                 if_printf(&sc->arpcom.ac_if, "firmware handshake timed out\n");
1792                 return;
1793         }
1794
1795         /*
1796          * XXX Wait for the value of the PCISTATE register to
1797          * return to its original pre-reset state. This is a
1798          * fairly good indicator of reset completion. If we don't
1799          * wait for the reset to fully complete, trying to read
1800          * from the device's non-PCI registers may yield garbage
1801          * results.
1802          */
1803         for (i = 0; i < BGE_TIMEOUT; i++) {
1804                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
1805                         break;
1806                 DELAY(10);
1807         }
1808
1809         /* Enable memory arbiter. */
1810         if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
1811                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
1812
1813         /* Fix up byte swapping */
1814         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_BYTESWAP_NONFRAME|
1815             BGE_MODECTL_BYTESWAP_DATA);
1816
1817         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1818
1819         DELAY(10000);
1820
1821         return;
1822 }
1823
1824 /*
1825  * Frame reception handling. This is called if there's a frame
1826  * on the receive return list.
1827  *
1828  * Note: we have to be able to handle two possibilities here:
1829  * 1) the frame is from the jumbo recieve ring
1830  * 2) the frame is from the standard receive ring
1831  */
1832
1833 static void
1834 bge_rxeof(struct bge_softc *sc)
1835 {
1836         struct ifnet *ifp;
1837         int stdcnt = 0, jumbocnt = 0;
1838
1839         ifp = &sc->arpcom.ac_if;
1840
1841         while(sc->bge_rx_saved_considx !=
1842             sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) {
1843                 struct bge_rx_bd        *cur_rx;
1844                 uint32_t                rxidx;
1845                 struct mbuf             *m = NULL;
1846                 uint16_t                vlan_tag = 0;
1847                 int                     have_tag = 0;
1848
1849                 cur_rx =
1850             &sc->bge_rdata->bge_rx_return_ring[sc->bge_rx_saved_considx];
1851
1852                 rxidx = cur_rx->bge_idx;
1853                 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
1854
1855                 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
1856                         have_tag = 1;
1857                         vlan_tag = cur_rx->bge_vlan_tag;
1858                 }
1859
1860                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
1861                         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
1862                         m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
1863                         sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL;
1864                         jumbocnt++;
1865                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
1866                                 ifp->if_ierrors++;
1867                                 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
1868                                 continue;
1869                         }
1870                         if (bge_newbuf_jumbo(sc,
1871                             sc->bge_jumbo, NULL) == ENOBUFS) {
1872                                 ifp->if_ierrors++;
1873                                 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
1874                                 continue;
1875                         }
1876                 } else {
1877                         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
1878                         m = sc->bge_cdata.bge_rx_std_chain[rxidx];
1879                         sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL;
1880                         stdcnt++;
1881                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
1882                                 ifp->if_ierrors++;
1883                                 bge_newbuf_std(sc, sc->bge_std, m);
1884                                 continue;
1885                         }
1886                         if (bge_newbuf_std(sc, sc->bge_std,
1887                             NULL) == ENOBUFS) {
1888                                 ifp->if_ierrors++;
1889                                 bge_newbuf_std(sc, sc->bge_std, m);
1890                                 continue;
1891                         }
1892                 }
1893
1894                 ifp->if_ipackets++;
1895 #ifndef __i386__
1896                 /*
1897                  * The i386 allows unaligned accesses, but for other
1898                  * platforms we must make sure the payload is aligned.
1899                  */
1900                 if (sc->bge_rx_alignment_bug) {
1901                         bcopy(m->m_data, m->m_data + ETHER_ALIGN,
1902                             cur_rx->bge_len);
1903                         m->m_data += ETHER_ALIGN;
1904                 }
1905 #endif
1906                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
1907                 m->m_pkthdr.rcvif = ifp;
1908
1909 #if 0 /* currently broken for some packets, possibly related to TCP options */
1910                 if (ifp->if_hwassist) {
1911                         m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1912                         if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
1913                                 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1914                         if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
1915                                 m->m_pkthdr.csum_data =
1916                                     cur_rx->bge_tcp_udp_csum;
1917                                 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID;
1918                         }
1919                 }
1920 #endif
1921
1922                 /*
1923                  * If we received a packet with a vlan tag, pass it
1924                  * to vlan_input() instead of ether_input().
1925                  */
1926                 if (have_tag) {
1927                         VLAN_INPUT_TAG(m, vlan_tag);
1928                         have_tag = vlan_tag = 0;
1929                         continue;
1930                 }
1931
1932                 (*ifp->if_input)(ifp, m);
1933         }
1934
1935         CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
1936         if (stdcnt)
1937                 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
1938         if (jumbocnt)
1939                 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
1940 }
1941
1942 static void
1943 bge_txeof(struct bge_softc *sc)
1944 {
1945         struct bge_tx_bd *cur_tx = NULL;
1946         struct ifnet *ifp;
1947
1948         ifp = &sc->arpcom.ac_if;
1949
1950         /*
1951          * Go through our tx ring and free mbufs for those
1952          * frames that have been sent.
1953          */
1954         while (sc->bge_tx_saved_considx !=
1955             sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) {
1956                 uint32_t                idx = 0;
1957
1958                 idx = sc->bge_tx_saved_considx;
1959                 cur_tx = &sc->bge_rdata->bge_tx_ring[idx];
1960                 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
1961                         ifp->if_opackets++;
1962                 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
1963                         m_freem(sc->bge_cdata.bge_tx_chain[idx]);
1964                         sc->bge_cdata.bge_tx_chain[idx] = NULL;
1965                 }
1966                 sc->bge_txcnt--;
1967                 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
1968                 ifp->if_timer = 0;
1969         }
1970
1971         if (cur_tx != NULL)
1972                 ifp->if_flags &= ~IFF_OACTIVE;
1973 }
1974
1975 static void
1976 bge_intr(void *xsc)
1977 {
1978         struct bge_softc *sc = xsc;
1979         struct ifnet *ifp = &sc->arpcom.ac_if;
1980         uint32_t status;
1981
1982 #ifdef notdef
1983         /* Avoid this for now -- checking this register is expensive. */
1984         /* Make sure this is really our interrupt. */
1985         if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE))
1986                 return;
1987 #endif
1988         /* Ack interrupt and stop others from occuring. */
1989         CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
1990
1991         /*
1992          * Process link state changes.
1993          * Grrr. The link status word in the status block does
1994          * not work correctly on the BCM5700 rev AX and BX chips,
1995          * according to all available information. Hence, we have
1996          * to enable MII interrupts in order to properly obtain
1997          * async link changes. Unfortunately, this also means that
1998          * we have to read the MAC status register to detect link
1999          * changes, thereby adding an additional register access to
2000          * the interrupt handler.
2001          */
2002
2003         if (sc->bge_asicrev == BGE_ASICREV_BCM5700) {
2004                 status = CSR_READ_4(sc, BGE_MAC_STS);
2005                 if (status & BGE_MACSTAT_MI_INTERRUPT) {
2006                         sc->bge_link = 0;
2007                         callout_stop(&sc->bge_stat_timer);
2008                         bge_tick(sc);
2009                         /* Clear the interrupt */
2010                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
2011                             BGE_EVTENB_MI_INTERRUPT);
2012                         bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
2013                         bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR,
2014                             BRGPHY_INTRS);
2015                 }
2016         } else {
2017                 if ((sc->bge_rdata->bge_status_block.bge_status &
2018                     BGE_STATFLAG_UPDATED) &&
2019                     (sc->bge_rdata->bge_status_block.bge_status &
2020                     BGE_STATFLAG_LINKSTATE_CHANGED)) {
2021                         sc->bge_rdata->bge_status_block.bge_status &=
2022                                 ~(BGE_STATFLAG_UPDATED|
2023                                 BGE_STATFLAG_LINKSTATE_CHANGED);
2024                         /*
2025                          * Sometimes PCS encoding errors are detected in
2026                          * TBI mode (on fiber NICs), and for some reason
2027                          * the chip will signal them as link changes.
2028                          * If we get a link change event, but the 'PCS
2029                          * encoding error' bit in the MAC status register
2030                          * is set, don't bother doing a link check.
2031                          * This avoids spurious "gigabit link up" messages
2032                          * that sometimes appear on fiber NICs during
2033                          * periods of heavy traffic. (There should be no
2034                          * effect on copper NICs.)
2035                          */
2036                         status = CSR_READ_4(sc, BGE_MAC_STS);
2037                         if (!(status & (BGE_MACSTAT_PORT_DECODE_ERROR|
2038                             BGE_MACSTAT_MI_COMPLETE))) {
2039                                 sc->bge_link = 0;
2040                                 callout_stop(&sc->bge_stat_timer);
2041                                 bge_tick(sc);
2042                         }
2043                         sc->bge_link = 0;
2044                         callout_stop(&sc->bge_stat_timer);
2045                         bge_tick(sc);
2046                         /* Clear the interrupt */
2047                         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
2048                             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
2049                             BGE_MACSTAT_LINK_CHANGED);
2050
2051                         /* Force flush the status block cached by PCI bridge */
2052                         CSR_READ_4(sc, BGE_MBX_IRQ0_LO);
2053                 }
2054         }
2055
2056         if (ifp->if_flags & IFF_RUNNING) {
2057                 /* Check RX return ring producer/consumer */
2058                 bge_rxeof(sc);
2059
2060                 /* Check TX ring producer/consumer */
2061                 bge_txeof(sc);
2062         }
2063
2064         bge_handle_events(sc);
2065
2066         /* Re-enable interrupts. */
2067         CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
2068
2069         if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd))
2070                 (*ifp->if_start)(ifp);
2071 }
2072
2073 static void
2074 bge_tick(void *xsc)
2075 {
2076         struct bge_softc *sc = xsc;
2077         struct ifnet *ifp = &sc->arpcom.ac_if;
2078         struct mii_data *mii = NULL;
2079         struct ifmedia *ifm = NULL;
2080
2081         crit_enter();
2082
2083         if (sc->bge_asicrev == BGE_ASICREV_BCM5705)
2084                 bge_stats_update_regs(sc);
2085         else
2086                 bge_stats_update(sc);
2087
2088         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2089
2090         if (sc->bge_link) {
2091                 crit_exit();
2092                 return;
2093         }
2094
2095         if (sc->bge_tbi) {
2096                 ifm = &sc->bge_ifmedia;
2097                 if (CSR_READ_4(sc, BGE_MAC_STS) &
2098                     BGE_MACSTAT_TBI_PCS_SYNCHED) {
2099                         sc->bge_link++;
2100                         CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
2101                         if_printf(ifp, "gigabit link up\n");
2102                         if (!ifq_is_empty(&ifp->if_snd))
2103                                 (*ifp->if_start)(ifp);
2104                 }
2105                 crit_exit();
2106                 return;
2107         }
2108
2109         mii = device_get_softc(sc->bge_miibus);
2110         mii_tick(mii);
2111
2112         if (!sc->bge_link) {
2113                 mii_pollstat(mii);
2114                 if (mii->mii_media_status & IFM_ACTIVE &&
2115                     IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2116                         sc->bge_link++;
2117                         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
2118                             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
2119                                 if_printf(ifp, "gigabit link up\n");
2120                         if (!ifq_is_empty(&ifp->if_snd))
2121                                 (*ifp->if_start)(ifp);
2122                 }
2123         }
2124
2125         crit_exit();
2126 }
2127
2128 static void
2129 bge_stats_update_regs(struct bge_softc *sc)
2130 {
2131         struct ifnet *ifp = &sc->arpcom.ac_if;
2132         struct bge_mac_stats_regs stats;
2133         uint32_t *s;
2134         int i;
2135
2136         s = (uint32_t *)&stats;
2137         for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2138                 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2139                 s++;
2140         }
2141
2142         ifp->if_collisions +=
2143            (stats.dot3StatsSingleCollisionFrames +
2144            stats.dot3StatsMultipleCollisionFrames +
2145            stats.dot3StatsExcessiveCollisions +
2146            stats.dot3StatsLateCollisions) -
2147            ifp->if_collisions;
2148 }
2149
2150 static void
2151 bge_stats_update(struct bge_softc *sc)
2152 {
2153         struct ifnet *ifp = &sc->arpcom.ac_if;
2154         struct bge_stats *stats;
2155
2156         stats = (struct bge_stats *)(sc->bge_vhandle +
2157             BGE_MEMWIN_START + BGE_STATS_BLOCK);
2158
2159         ifp->if_collisions +=
2160            (stats->txstats.dot3StatsSingleCollisionFrames.bge_addr_lo +
2161            stats->txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo +
2162            stats->txstats.dot3StatsExcessiveCollisions.bge_addr_lo +
2163            stats->txstats.dot3StatsLateCollisions.bge_addr_lo) -
2164            ifp->if_collisions;
2165
2166 #ifdef notdef
2167         ifp->if_collisions +=
2168            (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
2169            sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
2170            sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
2171            sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
2172            ifp->if_collisions;
2173 #endif
2174 }
2175
2176 /*
2177  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
2178  * pointers to descriptors.
2179  */
2180 static int
2181 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx)
2182 {
2183         struct bge_tx_bd *f = NULL;
2184         struct mbuf *m;
2185         uint32_t frag, cur, cnt = 0;
2186         uint16_t csum_flags = 0;
2187         struct ifvlan *ifv = NULL;
2188
2189         if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
2190             m_head->m_pkthdr.rcvif != NULL &&
2191             m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN)
2192                 ifv = m_head->m_pkthdr.rcvif->if_softc;
2193
2194         m = m_head;
2195         cur = frag = *txidx;
2196
2197         if (m_head->m_pkthdr.csum_flags) {
2198                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2199                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2200                 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2201                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2202                 if (m_head->m_flags & M_LASTFRAG)
2203                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2204                 else if (m_head->m_flags & M_FRAG)
2205                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2206         }
2207         /*
2208          * Start packing the mbufs in this chain into
2209          * the fragment pointers. Stop when we run out
2210          * of fragments or hit the end of the mbuf chain.
2211          */
2212         for (m = m_head; m != NULL; m = m->m_next) {
2213                 if (m->m_len != 0) {
2214                         f = &sc->bge_rdata->bge_tx_ring[frag];
2215                         if (sc->bge_cdata.bge_tx_chain[frag] != NULL)
2216                                 break;
2217                         BGE_HOSTADDR(f->bge_addr,
2218                             vtophys(mtod(m, vm_offset_t)));
2219                         f->bge_len = m->m_len;
2220                         f->bge_flags = csum_flags;
2221                         if (ifv != NULL) {
2222                                 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
2223                                 f->bge_vlan_tag = ifv->ifv_tag;
2224                         } else {
2225                                 f->bge_vlan_tag = 0;
2226                         }
2227                         /*
2228                          * Sanity check: avoid coming within 16 descriptors
2229                          * of the end of the ring.
2230                          */
2231                         if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16)
2232                                 return(ENOBUFS);
2233                         cur = frag;
2234                         BGE_INC(frag, BGE_TX_RING_CNT);
2235                         cnt++;
2236                 }
2237         }
2238
2239         if (m != NULL)
2240                 return(ENOBUFS);
2241
2242         if (frag == sc->bge_tx_saved_considx)
2243                 return(ENOBUFS);
2244
2245         sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END;
2246         sc->bge_cdata.bge_tx_chain[cur] = m_head;
2247         sc->bge_txcnt += cnt;
2248
2249         *txidx = frag;
2250
2251         return(0);
2252 }
2253
2254 /*
2255  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2256  * to the mbuf data regions directly in the transmit descriptors.
2257  */
2258 static void
2259 bge_start(struct ifnet *ifp)
2260 {
2261         struct bge_softc *sc;
2262         struct mbuf *m_head = NULL;
2263         uint32_t prodidx = 0;
2264
2265         sc = ifp->if_softc;
2266
2267         if (!sc->bge_link)
2268                 return;
2269
2270         prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO);
2271
2272         while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
2273                 m_head = ifq_poll(&ifp->if_snd);
2274                 if (m_head == NULL)
2275                         break;
2276
2277                 /*
2278                  * XXX
2279                  * safety overkill.  If this is a fragmented packet chain
2280                  * with delayed TCP/UDP checksums, then only encapsulate
2281                  * it if we have enough descriptors to handle the entire
2282                  * chain at once.
2283                  * (paranoia -- may not actually be needed)
2284                  */
2285                 if (m_head->m_flags & M_FIRSTFRAG &&
2286                     m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
2287                         if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2288                             m_head->m_pkthdr.csum_data + 16) {
2289                                 ifp->if_flags |= IFF_OACTIVE;
2290                                 break;
2291                         }
2292                 }
2293
2294                 /*
2295                  * Pack the data into the transmit ring. If we
2296                  * don't have room, set the OACTIVE flag and wait
2297                  * for the NIC to drain the ring.
2298                  */
2299                 if (bge_encap(sc, m_head, &prodidx)) {
2300                         ifp->if_flags |= IFF_OACTIVE;
2301                         break;
2302                 }
2303                 m_head = ifq_dequeue(&ifp->if_snd);
2304
2305                 BPF_MTAP(ifp, m_head);
2306         }
2307
2308         /* Transmit */
2309         CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2310         /* 5700 b2 errata */
2311         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
2312                 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2313
2314         /*
2315          * Set a timeout in case the chip goes out to lunch.
2316          */
2317         ifp->if_timer = 5;
2318 }
2319
2320 static void
2321 bge_init(void *xsc)
2322 {
2323         struct bge_softc *sc = xsc;
2324         struct ifnet *ifp = &sc->arpcom.ac_if;
2325         uint16_t *m;
2326
2327         crit_enter();
2328
2329         if (ifp->if_flags & IFF_RUNNING) {
2330                 crit_exit();
2331                 return;
2332         }
2333
2334         /* Cancel pending I/O and flush buffers. */
2335         bge_stop(sc);
2336         bge_reset(sc);
2337         bge_chipinit(sc);
2338
2339         /*
2340          * Init the various state machines, ring
2341          * control blocks and firmware.
2342          */
2343         if (bge_blockinit(sc)) {
2344                 if_printf(ifp, "initialization failure\n");
2345                 crit_exit();
2346                 return;
2347         }
2348
2349         /* Specify MTU. */
2350         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
2351             ETHER_HDR_LEN + ETHER_CRC_LEN);
2352
2353         /* Load our MAC address. */
2354         m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
2355         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
2356         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
2357
2358         /* Enable or disable promiscuous mode as needed. */
2359         if (ifp->if_flags & IFF_PROMISC) {
2360                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
2361         } else {
2362                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
2363         }
2364
2365         /* Program multicast filter. */
2366         bge_setmulti(sc);
2367
2368         /* Init RX ring. */
2369         bge_init_rx_ring_std(sc);
2370
2371         /*
2372          * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
2373          * memory to insure that the chip has in fact read the first
2374          * entry of the ring.
2375          */
2376         if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
2377                 uint32_t                v, i;
2378                 for (i = 0; i < 10; i++) {
2379                         DELAY(20);
2380                         v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
2381                         if (v == (MCLBYTES - ETHER_ALIGN))
2382                                 break;
2383                 }
2384                 if (i == 10)
2385                         if_printf(ifp, "5705 A0 chip failed to load RX ring\n");
2386         }
2387
2388         /* Init jumbo RX ring. */
2389         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2390                 bge_init_rx_ring_jumbo(sc);
2391
2392         /* Init our RX return ring index */
2393         sc->bge_rx_saved_considx = 0;
2394
2395         /* Init TX ring. */
2396         bge_init_tx_ring(sc);
2397
2398         /* Turn on transmitter */
2399         BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
2400
2401         /* Turn on receiver */
2402         BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
2403
2404         /* Tell firmware we're alive. */
2405         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2406
2407         /* Enable host interrupts. */
2408         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
2409         BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
2410         CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
2411
2412         bge_ifmedia_upd(ifp);
2413
2414         ifp->if_flags |= IFF_RUNNING;
2415         ifp->if_flags &= ~IFF_OACTIVE;
2416
2417         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2418
2419         crit_exit();
2420 }
2421
2422 /*
2423  * Set media options.
2424  */
2425 static int
2426 bge_ifmedia_upd(struct ifnet *ifp)
2427 {
2428         struct bge_softc *sc = ifp->if_softc;
2429         struct ifmedia *ifm = &sc->bge_ifmedia;
2430         struct mii_data *mii;
2431
2432         /* If this is a 1000baseX NIC, enable the TBI port. */
2433         if (sc->bge_tbi) {
2434                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2435                         return(EINVAL);
2436                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
2437                 case IFM_AUTO:
2438                         break;
2439                 case IFM_1000_SX:
2440                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2441                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
2442                                     BGE_MACMODE_HALF_DUPLEX);
2443                         } else {
2444                                 BGE_SETBIT(sc, BGE_MAC_MODE,
2445                                     BGE_MACMODE_HALF_DUPLEX);
2446                         }
2447                         break;
2448                 default:
2449                         return(EINVAL);
2450                 }
2451                 return(0);
2452         }
2453
2454         mii = device_get_softc(sc->bge_miibus);
2455         sc->bge_link = 0;
2456         if (mii->mii_instance) {
2457                 struct mii_softc *miisc;
2458                 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
2459                     miisc = LIST_NEXT(miisc, mii_list))
2460                         mii_phy_reset(miisc);
2461         }
2462         mii_mediachg(mii);
2463
2464         return(0);
2465 }
2466
2467 /*
2468  * Report current media status.
2469  */
2470 static void
2471 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2472 {
2473         struct bge_softc *sc = ifp->if_softc;
2474         struct mii_data *mii;
2475
2476         if (sc->bge_tbi) {
2477                 ifmr->ifm_status = IFM_AVALID;
2478                 ifmr->ifm_active = IFM_ETHER;
2479                 if (CSR_READ_4(sc, BGE_MAC_STS) &
2480                     BGE_MACSTAT_TBI_PCS_SYNCHED)
2481                         ifmr->ifm_status |= IFM_ACTIVE;
2482                 ifmr->ifm_active |= IFM_1000_SX;
2483                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
2484                         ifmr->ifm_active |= IFM_HDX;
2485                 else
2486                         ifmr->ifm_active |= IFM_FDX;
2487                 return;
2488         }
2489
2490         mii = device_get_softc(sc->bge_miibus);
2491         mii_pollstat(mii);
2492         ifmr->ifm_active = mii->mii_media_active;
2493         ifmr->ifm_status = mii->mii_media_status;
2494 }
2495
2496 static int
2497 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2498 {
2499         struct bge_softc *sc = ifp->if_softc;
2500         struct ifreq *ifr = (struct ifreq *) data;
2501         int mask, error = 0;
2502         struct mii_data *mii;
2503
2504         crit_enter();
2505
2506         switch(command) {
2507         case SIOCSIFMTU:
2508                 /* Disallow jumbo frames on 5705. */
2509                 if ((sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2510                     ifr->ifr_mtu > ETHERMTU) || ifr->ifr_mtu > BGE_JUMBO_MTU)
2511                         error = EINVAL;
2512                 else {
2513                         ifp->if_mtu = ifr->ifr_mtu;
2514                         ifp->if_flags &= ~IFF_RUNNING;
2515                         bge_init(sc);
2516                 }
2517                 break;
2518         case SIOCSIFFLAGS:
2519                 if (ifp->if_flags & IFF_UP) {
2520                         /*
2521                          * If only the state of the PROMISC flag changed,
2522                          * then just use the 'set promisc mode' command
2523                          * instead of reinitializing the entire NIC. Doing
2524                          * a full re-init means reloading the firmware and
2525                          * waiting for it to start up, which may take a
2526                          * second or two.
2527                          */
2528                         if (ifp->if_flags & IFF_RUNNING &&
2529                             ifp->if_flags & IFF_PROMISC &&
2530                             !(sc->bge_if_flags & IFF_PROMISC)) {
2531                                 BGE_SETBIT(sc, BGE_RX_MODE,
2532                                     BGE_RXMODE_RX_PROMISC);
2533                         } else if (ifp->if_flags & IFF_RUNNING &&
2534                             !(ifp->if_flags & IFF_PROMISC) &&
2535                             sc->bge_if_flags & IFF_PROMISC) {
2536                                 BGE_CLRBIT(sc, BGE_RX_MODE,
2537                                     BGE_RXMODE_RX_PROMISC);
2538                         } else
2539                                 bge_init(sc);
2540                 } else {
2541                         if (ifp->if_flags & IFF_RUNNING) {
2542                                 bge_stop(sc);
2543                         }
2544                 }
2545                 sc->bge_if_flags = ifp->if_flags;
2546                 error = 0;
2547                 break;
2548         case SIOCADDMULTI:
2549         case SIOCDELMULTI:
2550                 if (ifp->if_flags & IFF_RUNNING) {
2551                         bge_setmulti(sc);
2552                         error = 0;
2553                 }
2554                 break;
2555         case SIOCSIFMEDIA:
2556         case SIOCGIFMEDIA:
2557                 if (sc->bge_tbi) {
2558                         error = ifmedia_ioctl(ifp, ifr,
2559                             &sc->bge_ifmedia, command);
2560                 } else {
2561                         mii = device_get_softc(sc->bge_miibus);
2562                         error = ifmedia_ioctl(ifp, ifr,
2563                             &mii->mii_media, command);
2564                 }
2565                 break;
2566         case SIOCSIFCAP:
2567                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2568                 if (mask & IFCAP_HWCSUM) {
2569                         if (IFCAP_HWCSUM & ifp->if_capenable)
2570                                 ifp->if_capenable &= ~IFCAP_HWCSUM;
2571                         else
2572                                 ifp->if_capenable |= IFCAP_HWCSUM;
2573                 }
2574                 error = 0;
2575                 break;
2576         default:
2577                 error = ether_ioctl(ifp, command, data);
2578                 break;
2579         }
2580
2581         crit_exit();
2582
2583         return(error);
2584 }
2585
2586 static void
2587 bge_watchdog(struct ifnet *ifp)
2588 {
2589         struct bge_softc *sc = ifp->if_softc;
2590
2591         if_printf(ifp, "watchdog timeout -- resetting\n");
2592
2593         ifp->if_flags &= ~IFF_RUNNING;
2594         bge_init(sc);
2595
2596         ifp->if_oerrors++;
2597 }
2598
2599 /*
2600  * Stop the adapter and free any mbufs allocated to the
2601  * RX and TX lists.
2602  */
2603 static void
2604 bge_stop(struct bge_softc *sc)
2605 {
2606         struct ifnet *ifp = &sc->arpcom.ac_if;
2607         struct ifmedia_entry *ifm;
2608         struct mii_data *mii = NULL;
2609         int mtmp, itmp;
2610
2611         if (!sc->bge_tbi)
2612                 mii = device_get_softc(sc->bge_miibus);
2613
2614         callout_stop(&sc->bge_stat_timer);
2615
2616         /*
2617          * Disable all of the receiver blocks
2618          */
2619         BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
2620         BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
2621         BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
2622         if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
2623                 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
2624         BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
2625         BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
2626         BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
2627
2628         /*
2629          * Disable all of the transmit blocks
2630          */
2631         BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
2632         BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
2633         BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
2634         BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
2635         BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
2636         if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
2637                 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
2638         BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
2639
2640         /*
2641          * Shut down all of the memory managers and related
2642          * state machines.
2643          */
2644         BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
2645         BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
2646         if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
2647                 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
2648         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
2649         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
2650         if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
2651                 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
2652                 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2653         }
2654
2655         /* Disable host interrupts. */
2656         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
2657         CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
2658
2659         /*
2660          * Tell firmware we're shutting down.
2661          */
2662         BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2663
2664         /* Free the RX lists. */
2665         bge_free_rx_ring_std(sc);
2666
2667         /* Free jumbo RX list. */
2668         if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
2669                 bge_free_rx_ring_jumbo(sc);
2670
2671         /* Free TX buffers. */
2672         bge_free_tx_ring(sc);
2673
2674         /*
2675          * Isolate/power down the PHY, but leave the media selection
2676          * unchanged so that things will be put back to normal when
2677          * we bring the interface back up.
2678          */
2679         if (!sc->bge_tbi) {
2680                 itmp = ifp->if_flags;
2681                 ifp->if_flags |= IFF_UP;
2682                 ifm = mii->mii_media.ifm_cur;
2683                 mtmp = ifm->ifm_media;
2684                 ifm->ifm_media = IFM_ETHER|IFM_NONE;
2685                 mii_mediachg(mii);
2686                 ifm->ifm_media = mtmp;
2687                 ifp->if_flags = itmp;
2688         }
2689
2690         sc->bge_link = 0;
2691
2692         sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
2693
2694         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2695 }
2696
2697 /*
2698  * Stop all chip I/O so that the kernel's probe routines don't
2699  * get confused by errant DMAs when rebooting.
2700  */
2701 static void
2702 bge_shutdown(device_t dev)
2703 {
2704         struct bge_softc *sc = device_get_softc(dev);
2705
2706         bge_stop(sc);
2707         bge_reset(sc);
2708 }