2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_tl.c,v 1.51.2.5 2001/12/16 15:46:08 luigi Exp $
33 * $DragonFly: src/sys/dev/netif/tl/if_tl.c,v 1.30 2005/06/14 14:19:22 joerg Exp $
37 * Texas Instruments ThunderLAN driver for FreeBSD 2.2.6 and 3.x.
38 * Supports many Compaq PCI NICs based on the ThunderLAN ethernet controller,
39 * the National Semiconductor DP83840A physical interface and the
40 * Microchip Technology 24Cxx series serial EEPROM.
42 * Written using the following four documents:
44 * Texas Instruments ThunderLAN Programmer's Guide (www.ti.com)
45 * National Semiconductor DP83840A data sheet (www.national.com)
46 * Microchip Technology 24C02C data sheet (www.microchip.com)
47 * Micro Linear ML6692 100BaseTX only PHY data sheet (www.microlinear.com)
49 * Written by Bill Paul <wpaul@ctr.columbia.edu>
50 * Electrical Engineering Department
51 * Columbia University, New York City
55 * Some notes about the ThunderLAN:
57 * The ThunderLAN controller is a single chip containing PCI controller
58 * logic, approximately 3K of on-board SRAM, a LAN controller, and media
59 * independent interface (MII) bus. The MII allows the ThunderLAN chip to
60 * control up to 32 different physical interfaces (PHYs). The ThunderLAN
61 * also has a built-in 10baseT PHY, allowing a single ThunderLAN controller
62 * to act as a complete ethernet interface.
64 * Other PHYs may be attached to the ThunderLAN; the Compaq 10/100 cards
65 * use a National Semiconductor DP83840A PHY that supports 10 or 100Mb/sec
66 * in full or half duplex. Some of the Compaq Deskpro machines use a
67 * Level 1 LXT970 PHY with the same capabilities. Certain Olicom adapters
68 * use a Micro Linear ML6692 100BaseTX only PHY, which can be used in
69 * concert with the ThunderLAN's internal PHY to provide full 10/100
70 * support. This is cheaper than using a standalone external PHY for both
71 * 10/100 modes and letting the ThunderLAN's internal PHY go to waste.
72 * A serial EEPROM is also attached to the ThunderLAN chip to provide
73 * power-up default register settings and for storing the adapter's
74 * station address. Although not supported by this driver, the ThunderLAN
75 * chip can also be connected to token ring PHYs.
77 * The ThunderLAN has a set of registers which can be used to issue
78 * commands, acknowledge interrupts, and to manipulate other internal
79 * registers on its DIO bus. The primary registers can be accessed
80 * using either programmed I/O (inb/outb) or via PCI memory mapping,
81 * depending on how the card is configured during the PCI probing
82 * phase. It is even possible to have both PIO and memory mapped
83 * access turned on at the same time.
85 * Frame reception and transmission with the ThunderLAN chip is done
86 * using frame 'lists.' A list structure looks more or less like this:
89 * u_int32_t fragment_address;
90 * u_int32_t fragment_size;
93 * u_int32_t forward_pointer;
95 * u_int16_t frame_size;
96 * struct tl_frag fragments[10];
99 * The forward pointer in the list header can be either a 0 or the address
100 * of another list, which allows several lists to be linked together. Each
101 * list contains up to 10 fragment descriptors. This means the chip allows
102 * ethernet frames to be broken up into up to 10 chunks for transfer to
103 * and from the SRAM. Note that the forward pointer and fragment buffer
104 * addresses are physical memory addresses, not virtual. Note also that
105 * a single ethernet frame can not span lists: if the host wants to
106 * transmit a frame and the frame data is split up over more than 10
107 * buffers, the frame has to collapsed before it can be transmitted.
109 * To receive frames, the driver sets up a number of lists and populates
110 * the fragment descriptors, then it sends an RX GO command to the chip.
111 * When a frame is received, the chip will DMA it into the memory regions
112 * specified by the fragment descriptors and then trigger an RX 'end of
113 * frame interrupt' when done. The driver may choose to use only one
114 * fragment per list; this may result is slighltly less efficient use
115 * of memory in exchange for improving performance.
117 * To transmit frames, the driver again sets up lists and fragment
118 * descriptors, only this time the buffers contain frame data that
119 * is to be DMA'ed into the chip instead of out of it. Once the chip
120 * has transfered the data into its on-board SRAM, it will trigger a
121 * TX 'end of frame' interrupt. It will also generate an 'end of channel'
122 * interrupt when it reaches the end of the list.
126 * Some notes about this driver:
128 * The ThunderLAN chip provides a couple of different ways to organize
129 * reception, transmission and interrupt handling. The simplest approach
130 * is to use one list each for transmission and reception. In this mode,
131 * the ThunderLAN will generate two interrupts for every received frame
132 * (one RX EOF and one RX EOC) and two for each transmitted frame (one
133 * TX EOF and one TX EOC). This may make the driver simpler but it hurts
134 * performance to have to handle so many interrupts.
136 * Initially I wanted to create a circular list of receive buffers so
137 * that the ThunderLAN chip would think there was an infinitely long
138 * receive channel and never deliver an RXEOC interrupt. However this
139 * doesn't work correctly under heavy load: while the manual says the
140 * chip will trigger an RXEOF interrupt each time a frame is copied into
141 * memory, you can't count on the chip waiting around for you to acknowledge
142 * the interrupt before it starts trying to DMA the next frame. The result
143 * is that the chip might traverse the entire circular list and then wrap
144 * around before you have a chance to do anything about it. Consequently,
145 * the receive list is terminated (with a 0 in the forward pointer in the
146 * last element). Each time an RXEOF interrupt arrives, the used list
147 * is shifted to the end of the list. This gives the appearance of an
148 * infinitely large RX chain so long as the driver doesn't fall behind
149 * the chip and allow all of the lists to be filled up.
151 * If all the lists are filled, the adapter will deliver an RX 'end of
152 * channel' interrupt when it hits the 0 forward pointer at the end of
153 * the chain. The RXEOC handler then cleans out the RX chain and resets
154 * the list head pointer in the ch_parm register and restarts the receiver.
156 * For frame transmission, it is possible to program the ThunderLAN's
157 * transmit interrupt threshold so that the chip can acknowledge multiple
158 * lists with only a single TX EOF interrupt. This allows the driver to
159 * queue several frames in one shot, and only have to handle a total
160 * two interrupts (one TX EOF and one TX EOC) no matter how many frames
161 * are transmitted. Frame transmission is done directly out of the
162 * mbufs passed to the tl_start() routine via the interface send queue.
163 * The driver simply sets up the fragment descriptors in the transmit
164 * lists to point to the mbuf data regions and sends a TX GO command.
166 * Note that since the RX and TX lists themselves are always used
167 * only by the driver, the are malloc()ed once at driver initialization
168 * time and never free()ed.
170 * Also, in order to remain as platform independent as possible, this
171 * driver uses memory mapped register access to manipulate the card
172 * as opposed to programmed I/O. This avoids the use of the inb/outb
173 * (and related) instructions which are specific to the i386 platform.
175 * Using these techniques, this driver achieves very high performance
176 * by minimizing the amount of interrupts generated during large
177 * transfers and by completely avoiding buffer copies. Frame transfer
178 * to and from the ThunderLAN chip is performed entirely by the chip
179 * itself thereby reducing the load on the host CPU.
182 #include <sys/param.h>
183 #include <sys/systm.h>
184 #include <sys/sockio.h>
185 #include <sys/mbuf.h>
186 #include <sys/malloc.h>
187 #include <sys/kernel.h>
188 #include <sys/socket.h>
189 #include <sys/thread2.h>
192 #include <net/ifq_var.h>
193 #include <net/if_arp.h>
194 #include <net/ethernet.h>
195 #include <net/if_dl.h>
196 #include <net/if_media.h>
200 #include <vm/vm.h> /* for vtophys */
201 #include <vm/pmap.h> /* for vtophys */
202 #include <machine/bus_memio.h>
203 #include <machine/bus_pio.h>
204 #include <machine/bus.h>
205 #include <machine/resource.h>
207 #include <sys/rman.h>
209 #include "../mii_layer/mii.h"
210 #include "../mii_layer/miivar.h"
212 #include <bus/pci/pcireg.h>
213 #include <bus/pci/pcivar.h>
216 * Default to using PIO register access mode to pacify certain
217 * laptop docking stations with built-in ThunderLAN chips that
218 * don't seem to handle memory mapped mode properly.
220 #define TL_USEIOSPACE
222 #include "if_tlreg.h"
224 /* "controller miibus0" required. See GENERIC if you get errors here. */
225 #include "miibus_if.h"
228 * Various supported device vendors/types and their names.
231 static struct tl_type tl_devs[] = {
232 { TI_VENDORID, TI_DEVICEID_THUNDERLAN,
233 "Texas Instruments ThunderLAN" },
234 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10,
235 "Compaq Netelligent 10" },
236 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100,
237 "Compaq Netelligent 10/100" },
238 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_PROLIANT,
239 "Compaq Netelligent 10/100 Proliant" },
240 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_DUAL,
241 "Compaq Netelligent 10/100 Dual Port" },
242 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED,
243 "Compaq NetFlex-3/P Integrated" },
244 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P,
245 "Compaq NetFlex-3/P" },
246 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_BNC,
247 "Compaq NetFlex 3/P w/ BNC" },
248 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED,
249 "Compaq Netelligent 10/100 TX Embedded UTP" },
250 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX,
251 "Compaq Netelligent 10 T/2 PCI UTP/Coax" },
252 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_TX_UTP,
253 "Compaq Netelligent 10/100 TX UTP" },
254 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2183,
255 "Olicom OC-2183/2185" },
256 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2325,
258 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2326,
259 "Olicom OC-2326 10/100 TX UTP" },
263 static int tl_probe (device_t);
264 static int tl_attach (device_t);
265 static int tl_detach (device_t);
266 static int tl_intvec_rxeoc (void *, u_int32_t);
267 static int tl_intvec_txeoc (void *, u_int32_t);
268 static int tl_intvec_txeof (void *, u_int32_t);
269 static int tl_intvec_rxeof (void *, u_int32_t);
270 static int tl_intvec_adchk (void *, u_int32_t);
271 static int tl_intvec_netsts (void *, u_int32_t);
273 static int tl_newbuf (struct tl_softc *,
274 struct tl_chain_onefrag *);
275 static void tl_stats_update (void *);
276 static int tl_encap (struct tl_softc *, struct tl_chain *,
279 static void tl_intr (void *);
280 static void tl_start (struct ifnet *);
281 static int tl_ioctl (struct ifnet *, u_long, caddr_t,
283 static void tl_init (void *);
284 static void tl_stop (struct tl_softc *);
285 static void tl_watchdog (struct ifnet *);
286 static void tl_shutdown (device_t);
287 static int tl_ifmedia_upd (struct ifnet *);
288 static void tl_ifmedia_sts (struct ifnet *, struct ifmediareq *);
290 static u_int8_t tl_eeprom_putbyte (struct tl_softc *, int);
291 static u_int8_t tl_eeprom_getbyte (struct tl_softc *,
293 static int tl_read_eeprom (struct tl_softc *, caddr_t, int, int);
295 static void tl_mii_sync (struct tl_softc *);
296 static void tl_mii_send (struct tl_softc *, u_int32_t, int);
297 static int tl_mii_readreg (struct tl_softc *, struct tl_mii_frame *);
298 static int tl_mii_writereg (struct tl_softc *, struct tl_mii_frame *);
299 static int tl_miibus_readreg (device_t, int, int);
300 static int tl_miibus_writereg (device_t, int, int, int);
301 static void tl_miibus_statchg (device_t);
303 static void tl_setmode (struct tl_softc *, int);
304 static int tl_calchash (caddr_t);
305 static void tl_setmulti (struct tl_softc *);
306 static void tl_setfilt (struct tl_softc *, caddr_t, int);
307 static void tl_softreset (struct tl_softc *, int);
308 static void tl_hardreset (device_t);
309 static int tl_list_rx_init (struct tl_softc *);
310 static int tl_list_tx_init (struct tl_softc *);
312 static u_int8_t tl_dio_read8 (struct tl_softc *, int);
313 static u_int16_t tl_dio_read16 (struct tl_softc *, int);
314 static u_int32_t tl_dio_read32 (struct tl_softc *, int);
315 static void tl_dio_write8 (struct tl_softc *, int, int);
316 static void tl_dio_write16 (struct tl_softc *, int, int);
317 static void tl_dio_write32 (struct tl_softc *, int, int);
318 static void tl_dio_setbit (struct tl_softc *, int, int);
319 static void tl_dio_clrbit (struct tl_softc *, int, int);
320 static void tl_dio_setbit16 (struct tl_softc *, int, int);
321 static void tl_dio_clrbit16 (struct tl_softc *, int, int);
324 #define TL_RES SYS_RES_IOPORT
325 #define TL_RID TL_PCI_LOIO
327 #define TL_RES SYS_RES_MEMORY
328 #define TL_RID TL_PCI_LOMEM
331 static device_method_t tl_methods[] = {
332 /* Device interface */
333 DEVMETHOD(device_probe, tl_probe),
334 DEVMETHOD(device_attach, tl_attach),
335 DEVMETHOD(device_detach, tl_detach),
336 DEVMETHOD(device_shutdown, tl_shutdown),
339 DEVMETHOD(bus_print_child, bus_generic_print_child),
340 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
343 DEVMETHOD(miibus_readreg, tl_miibus_readreg),
344 DEVMETHOD(miibus_writereg, tl_miibus_writereg),
345 DEVMETHOD(miibus_statchg, tl_miibus_statchg),
350 static driver_t tl_driver = {
353 sizeof(struct tl_softc)
356 static devclass_t tl_devclass;
358 DECLARE_DUMMY_MODULE(if_tl);
359 DRIVER_MODULE(if_tl, pci, tl_driver, tl_devclass, 0, 0);
360 DRIVER_MODULE(miibus, tl, miibus_driver, miibus_devclass, 0, 0);
362 static u_int8_t tl_dio_read8(sc, reg)
366 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
367 return(CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)));
370 static u_int16_t tl_dio_read16(sc, reg)
374 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
375 return(CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)));
378 static u_int32_t tl_dio_read32(sc, reg)
382 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
383 return(CSR_READ_4(sc, TL_DIO_DATA + (reg & 3)));
386 static void tl_dio_write8(sc, reg, val)
391 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
392 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), val);
396 static void tl_dio_write16(sc, reg, val)
401 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
402 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val);
406 static void tl_dio_write32(sc, reg, val)
411 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
412 CSR_WRITE_4(sc, TL_DIO_DATA + (reg & 3), val);
416 static void tl_dio_setbit(sc, reg, bit)
423 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
424 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3));
426 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f);
431 static void tl_dio_clrbit(sc, reg, bit)
438 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
439 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3));
441 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f);
446 static void tl_dio_setbit16(sc, reg, bit)
453 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
454 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3));
456 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f);
461 static void tl_dio_clrbit16(sc, reg, bit)
468 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
469 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3));
471 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f);
477 * Send an instruction or address to the EEPROM, check for ACK.
479 static u_int8_t tl_eeprom_putbyte(sc, byte)
486 * Make sure we're in TX mode.
488 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN);
491 * Feed in each bit and stobe the clock.
493 for (i = 0x80; i; i >>= 1) {
495 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA);
497 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA);
500 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
502 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
508 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN);
513 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
514 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA;
515 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
521 * Read a byte of data stored in the EEPROM at address 'addr.'
523 static u_int8_t tl_eeprom_getbyte(sc, addr, dest)
531 tl_dio_write8(sc, TL_NETSIO, 0);
536 * Send write control code to EEPROM.
538 if (tl_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
539 if_printf(&sc->arpcom.ac_if, "failed to send write command, "
540 "status: %x\n", tl_dio_read8(sc, TL_NETSIO));
545 * Send address of byte we want to read.
547 if (tl_eeprom_putbyte(sc, addr)) {
548 if_printf(&sc->arpcom.ac_if, "failed to send address, "
549 "status: %x\n", tl_dio_read8(sc, TL_NETSIO));
556 * Send read control code to EEPROM.
558 if (tl_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
559 if_printf(&sc->arpcom.ac_if, "failed to send write command, "
560 "status: %x\n", tl_dio_read8(sc, TL_NETSIO));
565 * Start reading bits from EEPROM.
567 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN);
568 for (i = 0x80; i; i >>= 1) {
569 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
571 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA)
573 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
580 * No ACK generated for read, so just return byte.
589 * Read a sequence of bytes from the EEPROM.
591 static int tl_read_eeprom(sc, dest, off, cnt)
600 for (i = 0; i < cnt; i++) {
601 err = tl_eeprom_getbyte(sc, off + i, &byte);
610 static void tl_mii_sync(sc)
615 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN);
617 for (i = 0; i < 32; i++) {
618 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
619 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
625 static void tl_mii_send(sc, bits, cnt)
632 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
633 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
635 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MDATA);
637 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MDATA);
639 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
643 static int tl_mii_readreg(sc, frame)
645 struct tl_mii_frame *frame;
656 * Set up frame for RX.
658 frame->mii_stdelim = TL_MII_STARTDELIM;
659 frame->mii_opcode = TL_MII_READOP;
660 frame->mii_turnaround = 0;
664 * Turn off MII interrupt by forcing MINTEN low.
666 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN;
668 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN);
674 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN);
677 * Send command/address info.
679 tl_mii_send(sc, frame->mii_stdelim, 2);
680 tl_mii_send(sc, frame->mii_opcode, 2);
681 tl_mii_send(sc, frame->mii_phyaddr, 5);
682 tl_mii_send(sc, frame->mii_regaddr, 5);
687 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN);
690 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
691 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
694 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
695 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA;
697 /* Complete the cycle */
698 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
701 * Now try reading data bits. If the ack failed, we still
702 * need to clock through 16 cycles to keep the PHYs in sync.
705 for(i = 0; i < 16; i++) {
706 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
707 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
712 for (i = 0x8000; i; i >>= 1) {
713 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
715 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA)
716 frame->mii_data |= i;
718 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
723 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
724 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
726 /* Reenable interrupts */
728 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN);
738 static int tl_mii_writereg(sc, frame)
740 struct tl_mii_frame *frame;
749 * Set up frame for TX.
752 frame->mii_stdelim = TL_MII_STARTDELIM;
753 frame->mii_opcode = TL_MII_WRITEOP;
754 frame->mii_turnaround = TL_MII_TURNAROUND;
757 * Turn off MII interrupt by forcing MINTEN low.
759 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN;
761 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN);
765 * Turn on data output.
767 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN);
769 tl_mii_send(sc, frame->mii_stdelim, 2);
770 tl_mii_send(sc, frame->mii_opcode, 2);
771 tl_mii_send(sc, frame->mii_phyaddr, 5);
772 tl_mii_send(sc, frame->mii_regaddr, 5);
773 tl_mii_send(sc, frame->mii_turnaround, 2);
774 tl_mii_send(sc, frame->mii_data, 16);
776 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
777 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
782 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN);
784 /* Reenable interrupts */
786 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN);
793 static int tl_miibus_readreg(dev, phy, reg)
798 struct tl_mii_frame frame;
800 sc = device_get_softc(dev);
801 bzero((char *)&frame, sizeof(frame));
803 frame.mii_phyaddr = phy;
804 frame.mii_regaddr = reg;
805 tl_mii_readreg(sc, &frame);
807 return(frame.mii_data);
810 static int tl_miibus_writereg(dev, phy, reg, data)
815 struct tl_mii_frame frame;
817 sc = device_get_softc(dev);
818 bzero((char *)&frame, sizeof(frame));
820 frame.mii_phyaddr = phy;
821 frame.mii_regaddr = reg;
822 frame.mii_data = data;
824 tl_mii_writereg(sc, &frame);
829 static void tl_miibus_statchg(dev)
833 struct mii_data *mii;
835 sc = device_get_softc(dev);
836 mii = device_get_softc(sc->tl_miibus);
838 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
839 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
841 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
848 * Set modes for bitrate devices.
850 static void tl_setmode(sc, media)
854 if (IFM_SUBTYPE(media) == IFM_10_5)
855 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD1);
856 if (IFM_SUBTYPE(media) == IFM_10_T) {
857 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD1);
858 if ((media & IFM_GMASK) == IFM_FDX) {
859 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD3);
860 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
862 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD3);
863 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
871 * Calculate the hash of a MAC address for programming the multicast hash
872 * table. This hash is simply the address split into 6-bit chunks
874 * byte: 000000|00 1111|1111 22|222222|333333|33 4444|4444 55|555555
875 * bit: 765432|10 7654|3210 76|543210|765432|10 7654|3210 76|543210
876 * Bytes 0-2 and 3-5 are symmetrical, so are folded together. Then
877 * the folded 24-bit value is split into 6-bit portions and XOR'd.
879 static int tl_calchash(addr)
884 t = (addr[0] ^ addr[3]) << 16 | (addr[1] ^ addr[4]) << 8 |
886 return ((t >> 18) ^ (t >> 12) ^ (t >> 6) ^ t) & 0x3f;
890 * The ThunderLAN has a perfect MAC address filter in addition to
891 * the multicast hash filter. The perfect filter can be programmed
892 * with up to four MAC addresses. The first one is always used to
893 * hold the station address, which leaves us free to use the other
894 * three for multicast addresses.
896 static void tl_setfilt(sc, addr, slot)
904 regaddr = TL_AREG0_B5 + (slot * ETHER_ADDR_LEN);
906 for (i = 0; i < ETHER_ADDR_LEN; i++)
907 tl_dio_write8(sc, regaddr + i, *(addr + i));
913 * XXX In FreeBSD 3.0, multicast addresses are managed using a doubly
914 * linked list. This is fine, except addresses are added from the head
915 * end of the list. We want to arrange for 224.0.0.1 (the "all hosts")
916 * group to always be in the perfect filter, but as more groups are added,
917 * the 224.0.0.1 entry (which is always added first) gets pushed down
918 * the list and ends up at the tail. So after 3 or 4 multicast groups
919 * are added, the all-hosts entry gets pushed out of the perfect filter
920 * and into the hash table.
922 * Because the multicast list is a doubly-linked list as opposed to a
923 * circular queue, we don't have the ability to just grab the tail of
924 * the list and traverse it backwards. Instead, we have to traverse
925 * the list once to find the tail, then traverse it again backwards to
926 * update the multicast filter.
928 static void tl_setmulti(sc)
932 u_int32_t hashes[2] = { 0, 0 };
934 struct ifmultiaddr *ifma;
935 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 };
936 ifp = &sc->arpcom.ac_if;
938 /* First, zot all the existing filters. */
939 for (i = 1; i < 4; i++)
940 tl_setfilt(sc, (caddr_t)&dummy, i);
941 tl_dio_write32(sc, TL_HASH1, 0);
942 tl_dio_write32(sc, TL_HASH2, 0);
944 /* Now program new ones. */
945 if (ifp->if_flags & IFF_ALLMULTI) {
946 hashes[0] = 0xFFFFFFFF;
947 hashes[1] = 0xFFFFFFFF;
950 /* First find the tail of the list. */
951 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
952 ifma = ifma->ifma_link.le_next) {
953 if (ifma->ifma_link.le_next == NULL)
956 /* Now traverse the list backwards. */
957 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs;
958 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) {
959 if (ifma->ifma_addr->sa_family != AF_LINK)
962 * Program the first three multicast groups
963 * into the perfect filter. For all others,
964 * use the hash table.
968 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i);
974 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
976 hashes[0] |= (1 << h);
978 hashes[1] |= (1 << (h - 32));
982 tl_dio_write32(sc, TL_HASH1, hashes[0]);
983 tl_dio_write32(sc, TL_HASH2, hashes[1]);
989 * This routine is recommended by the ThunderLAN manual to insure that
990 * the internal PHY is powered up correctly. It also recommends a one
991 * second pause at the end to 'wait for the clocks to start' but in my
992 * experience this isn't necessary.
994 static void tl_hardreset(dev)
1001 sc = device_get_softc(dev);
1005 flags = BMCR_LOOP|BMCR_ISO|BMCR_PDOWN;
1007 for (i = 0; i < MII_NPHY; i++)
1008 tl_miibus_writereg(dev, i, MII_BMCR, flags);
1010 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_ISO);
1012 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_LOOP|BMCR_ISO);
1014 while(tl_miibus_readreg(dev, 31, MII_BMCR) & BMCR_RESET);
1020 static void tl_softreset(sc, internal)
1021 struct tl_softc *sc;
1024 u_int32_t cmd, dummy, i;
1026 /* Assert the adapter reset bit. */
1027 CMD_SET(sc, TL_CMD_ADRST);
1029 /* Turn off interrupts */
1030 CMD_SET(sc, TL_CMD_INTSOFF);
1032 /* First, clear the stats registers. */
1033 for (i = 0; i < 5; i++)
1034 dummy = tl_dio_read32(sc, TL_TXGOODFRAMES);
1036 /* Clear Areg and Hash registers */
1037 for (i = 0; i < 8; i++)
1038 tl_dio_write32(sc, TL_AREG0_B5, 0x00000000);
1041 * Set up Netconfig register. Enable one channel and
1042 * one fragment mode.
1044 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_ONECHAN|TL_CFG_ONEFRAG);
1045 if (internal && !sc->tl_bitrate) {
1046 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN);
1048 tl_dio_clrbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN);
1051 /* Handle cards with bitrate devices. */
1053 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_BITRATE);
1056 * Load adapter irq pacing timer and tx threshold.
1057 * We make the transmit threshold 1 initially but we may
1058 * change that later.
1060 cmd = CSR_READ_4(sc, TL_HOSTCMD);
1062 cmd &= ~(TL_CMD_RT|TL_CMD_EOC|TL_CMD_ACK_MASK|TL_CMD_CHSEL_MASK);
1063 CMD_PUT(sc, cmd | (TL_CMD_LDTHR | TX_THR));
1064 CMD_PUT(sc, cmd | (TL_CMD_LDTMR | 0x00000003));
1066 /* Unreset the MII */
1067 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_NMRST);
1069 /* Take the adapter out of reset */
1070 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NRESET|TL_CMD_NWRAP);
1072 /* Wait for things to settle down a little. */
1079 * Probe for a ThunderLAN chip. Check the PCI vendor and device IDs
1080 * against our list and return its name if we find a match.
1082 static int tl_probe(dev)
1089 while(t->tl_name != NULL) {
1090 if ((pci_get_vendor(dev) == t->tl_vid) &&
1091 (pci_get_device(dev) == t->tl_did)) {
1092 device_set_desc(dev, t->tl_name);
1101 static int tl_attach(dev)
1108 struct tl_softc *sc;
1110 uint8_t eaddr[ETHER_ADDR_LEN];
1112 vid = pci_get_vendor(dev);
1113 did = pci_get_device(dev);
1114 sc = device_get_softc(dev);
1117 while(t->tl_name != NULL) {
1118 if (vid == t->tl_vid && did == t->tl_did)
1123 KKASSERT(t->tl_name != NULL);
1125 pci_enable_busmaster(dev);
1127 #ifdef TL_USEIOSPACE
1129 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
1133 * Some cards have the I/O and memory mapped address registers
1134 * reversed. Try both combinations before giving up.
1136 if (sc->tl_res == NULL) {
1138 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
1143 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1145 if (sc->tl_res == NULL) {
1147 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1152 if (sc->tl_res == NULL) {
1153 device_printf(dev, "couldn't map ports/memory\n");
1158 sc->tl_btag = rman_get_bustag(sc->tl_res);
1159 sc->tl_bhandle = rman_get_bushandle(sc->tl_res);
1163 * The ThunderLAN manual suggests jacking the PCI latency
1164 * timer all the way up to its maximum value. I'm not sure
1165 * if this is really necessary, but what the manual wants,
1168 command = pci_read_config(dev, TL_PCI_LATENCY_TIMER, 4);
1169 command |= 0x0000FF00;
1170 pci_write_config(dev, TL_PCI_LATENCY_TIMER, command, 4);
1173 /* Allocate interrupt */
1175 sc->tl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1176 RF_SHAREABLE | RF_ACTIVE);
1178 if (sc->tl_irq == NULL) {
1179 device_printf(dev, "couldn't map interrupt\n");
1185 * Now allocate memory for the TX and RX lists.
1187 sc->tl_ldata = contigmalloc(sizeof(struct tl_list_data), M_DEVBUF,
1188 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
1190 if (sc->tl_ldata == NULL) {
1191 device_printf(dev, "no memory for list buffers!\n");
1196 bzero(sc->tl_ldata, sizeof(struct tl_list_data));
1199 if (t->tl_vid == COMPAQ_VENDORID || t->tl_vid == TI_VENDORID)
1200 sc->tl_eeaddr = TL_EEPROM_EADDR;
1201 if (t->tl_vid == OLICOM_VENDORID)
1202 sc->tl_eeaddr = TL_EEPROM_EADDR_OC;
1204 /* Reset the adapter. */
1205 tl_softreset(sc, 1);
1207 tl_softreset(sc, 1);
1209 ifp = &sc->arpcom.ac_if;
1210 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1213 * Get station address from the EEPROM.
1215 if (tl_read_eeprom(sc, eaddr, sc->tl_eeaddr, ETHER_ADDR_LEN)) {
1216 device_printf(dev, "failed to read station address\n");
1222 * XXX Olicom, in its desire to be different from the
1223 * rest of the world, has done strange things with the
1224 * encoding of the station address in the EEPROM. First
1225 * of all, they store the address at offset 0xF8 rather
1226 * than at 0x83 like the ThunderLAN manual suggests.
1227 * Second, they store the address in three 16-bit words in
1228 * network byte order, as opposed to storing it sequentially
1229 * like all the other ThunderLAN cards. In order to get
1230 * the station address in a form that matches what the Olicom
1231 * diagnostic utility specifies, we have to byte-swap each
1232 * word. To make things even more confusing, neither 00:00:28
1233 * nor 00:00:24 appear in the IEEE OUI database.
1235 if (sc->tl_dinfo->tl_vid == OLICOM_VENDORID) {
1236 for (i = 0; i < ETHER_ADDR_LEN; i += 2) {
1238 p = (u_int16_t *)&eaddr[i];
1244 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1245 ifp->if_ioctl = tl_ioctl;
1246 ifp->if_start = tl_start;
1247 ifp->if_watchdog = tl_watchdog;
1248 ifp->if_init = tl_init;
1249 ifp->if_mtu = ETHERMTU;
1250 ifq_set_maxlen(&ifp->if_snd, TL_TX_LIST_CNT - 1);
1251 ifq_set_ready(&ifp->if_snd);
1252 callout_init(&sc->tl_stat_timer);
1254 /* Reset the adapter again. */
1255 tl_softreset(sc, 1);
1257 tl_softreset(sc, 1);
1260 * Do MII setup. If no PHYs are found, then this is a
1261 * bitrate ThunderLAN chip that only supports 10baseT
1264 if (mii_phy_probe(dev, &sc->tl_miibus,
1265 tl_ifmedia_upd, tl_ifmedia_sts)) {
1266 struct ifmedia *ifm;
1268 ifmedia_init(&sc->ifmedia, 0, tl_ifmedia_upd, tl_ifmedia_sts);
1269 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1270 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1271 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1272 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1273 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_10_T);
1274 /* Reset again, this time setting bitrate mode. */
1275 tl_softreset(sc, 1);
1277 ifm->ifm_media = ifm->ifm_cur->ifm_media;
1278 tl_ifmedia_upd(ifp);
1282 * Call MI attach routine.
1284 ether_ifattach(ifp, eaddr);
1286 error = bus_setup_intr(dev, sc->tl_irq, INTR_TYPE_NET,
1287 tl_intr, sc, &sc->tl_intrhand, NULL);
1290 ether_ifdetach(ifp);
1291 device_printf(dev, "couldn't set up irq\n");
1302 static int tl_detach(dev)
1305 struct tl_softc *sc = device_get_softc(dev);
1306 struct ifnet *ifp = &sc->arpcom.ac_if;
1310 if (device_is_attached(dev)) {
1312 ether_ifdetach(ifp);
1316 device_delete_child(dev, sc->tl_miibus);
1317 bus_generic_detach(dev);
1322 contigfree(sc->tl_ldata, sizeof(struct tl_list_data), M_DEVBUF);
1324 ifmedia_removeall(&sc->ifmedia);
1325 if (sc->tl_intrhand)
1326 bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand);
1328 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq);
1330 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res);
1336 * Initialize the transmit lists.
1338 static int tl_list_tx_init(sc)
1339 struct tl_softc *sc;
1341 struct tl_chain_data *cd;
1342 struct tl_list_data *ld;
1347 for (i = 0; i < TL_TX_LIST_CNT; i++) {
1348 cd->tl_tx_chain[i].tl_ptr = &ld->tl_tx_list[i];
1349 if (i == (TL_TX_LIST_CNT - 1))
1350 cd->tl_tx_chain[i].tl_next = NULL;
1352 cd->tl_tx_chain[i].tl_next = &cd->tl_tx_chain[i + 1];
1355 cd->tl_tx_free = &cd->tl_tx_chain[0];
1356 cd->tl_tx_tail = cd->tl_tx_head = NULL;
1363 * Initialize the RX lists and allocate mbufs for them.
1365 static int tl_list_rx_init(sc)
1366 struct tl_softc *sc;
1368 struct tl_chain_data *cd;
1369 struct tl_list_data *ld;
1375 for (i = 0; i < TL_RX_LIST_CNT; i++) {
1376 cd->tl_rx_chain[i].tl_ptr =
1377 (struct tl_list_onefrag *)&ld->tl_rx_list[i];
1378 if (tl_newbuf(sc, &cd->tl_rx_chain[i]) == ENOBUFS)
1380 if (i == (TL_RX_LIST_CNT - 1)) {
1381 cd->tl_rx_chain[i].tl_next = NULL;
1382 ld->tl_rx_list[i].tlist_fptr = 0;
1384 cd->tl_rx_chain[i].tl_next = &cd->tl_rx_chain[i + 1];
1385 ld->tl_rx_list[i].tlist_fptr =
1386 vtophys(&ld->tl_rx_list[i + 1]);
1390 cd->tl_rx_head = &cd->tl_rx_chain[0];
1391 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1];
1396 static int tl_newbuf(sc, c)
1397 struct tl_softc *sc;
1398 struct tl_chain_onefrag *c;
1402 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
1408 c->tl_ptr->tlist_frsize = MCLBYTES;
1409 c->tl_ptr->tlist_fptr = 0;
1410 c->tl_ptr->tl_frag.tlist_dadr = vtophys(mtod(m_new, caddr_t));
1411 c->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES;
1412 c->tl_ptr->tlist_cstat = TL_CSTAT_READY;
1417 * Interrupt handler for RX 'end of frame' condition (EOF). This
1418 * tells us that a full ethernet frame has been captured and we need
1421 * Reception is done using 'lists' which consist of a header and a
1422 * series of 10 data count/data address pairs that point to buffers.
1423 * Initially you're supposed to create a list, populate it with pointers
1424 * to buffers, then load the physical address of the list into the
1425 * ch_parm register. The adapter is then supposed to DMA the received
1426 * frame into the buffers for you.
1428 * To make things as fast as possible, we have the chip DMA directly
1429 * into mbufs. This saves us from having to do a buffer copy: we can
1430 * just hand the mbufs directly to ether_input(). Once the frame has
1431 * been sent on its way, the 'list' structure is assigned a new buffer
1432 * and moved to the end of the RX chain. As long we we stay ahead of
1433 * the chip, it will always think it has an endless receive channel.
1435 * If we happen to fall behind and the chip manages to fill up all of
1436 * the buffers, it will generate an end of channel interrupt and wait
1437 * for us to empty the chain and restart the receiver.
1439 static int tl_intvec_rxeof(xsc, type)
1443 struct tl_softc *sc;
1444 int r = 0, total_len = 0;
1445 struct ether_header *eh;
1448 struct tl_chain_onefrag *cur_rx;
1451 ifp = &sc->arpcom.ac_if;
1453 while(sc->tl_cdata.tl_rx_head != NULL) {
1454 cur_rx = sc->tl_cdata.tl_rx_head;
1455 if (!(cur_rx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP))
1458 sc->tl_cdata.tl_rx_head = cur_rx->tl_next;
1459 m = cur_rx->tl_mbuf;
1460 total_len = cur_rx->tl_ptr->tlist_frsize;
1462 if (tl_newbuf(sc, cur_rx) == ENOBUFS) {
1464 cur_rx->tl_ptr->tlist_frsize = MCLBYTES;
1465 cur_rx->tl_ptr->tlist_cstat = TL_CSTAT_READY;
1466 cur_rx->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES;
1470 sc->tl_cdata.tl_rx_tail->tl_ptr->tlist_fptr =
1471 vtophys(cur_rx->tl_ptr);
1472 sc->tl_cdata.tl_rx_tail->tl_next = cur_rx;
1473 sc->tl_cdata.tl_rx_tail = cur_rx;
1475 eh = mtod(m, struct ether_header *);
1476 m->m_pkthdr.rcvif = ifp;
1479 * Note: when the ThunderLAN chip is in 'capture all
1480 * frames' mode, it will receive its own transmissions.
1481 * We drop don't need to process our own transmissions,
1482 * so we drop them here and continue.
1484 /*if (ifp->if_flags & IFF_PROMISC && */
1485 if (!bcmp(eh->ether_shost, sc->arpcom.ac_enaddr,
1491 (*ifp->if_input)(ifp, m);
1498 * The RX-EOC condition hits when the ch_parm address hasn't been
1499 * initialized or the adapter reached a list with a forward pointer
1500 * of 0 (which indicates the end of the chain). In our case, this means
1501 * the card has hit the end of the receive buffer chain and we need to
1502 * empty out the buffers and shift the pointer back to the beginning again.
1504 static int tl_intvec_rxeoc(xsc, type)
1508 struct tl_softc *sc;
1510 struct tl_chain_data *cd;
1516 /* Flush out the receive queue and ack RXEOF interrupts. */
1517 r = tl_intvec_rxeof(xsc, type);
1518 CMD_PUT(sc, TL_CMD_ACK | r | (type & ~(0x00100000)));
1520 cd->tl_rx_head = &cd->tl_rx_chain[0];
1521 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1];
1522 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(sc->tl_cdata.tl_rx_head->tl_ptr));
1523 r |= (TL_CMD_GO|TL_CMD_RT);
1527 static int tl_intvec_txeof(xsc, type)
1531 struct tl_softc *sc;
1533 struct tl_chain *cur_tx;
1538 * Go through our tx list and free mbufs for those
1539 * frames that have been sent.
1541 while (sc->tl_cdata.tl_tx_head != NULL) {
1542 cur_tx = sc->tl_cdata.tl_tx_head;
1543 if (!(cur_tx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP))
1545 sc->tl_cdata.tl_tx_head = cur_tx->tl_next;
1548 m_freem(cur_tx->tl_mbuf);
1549 cur_tx->tl_mbuf = NULL;
1551 cur_tx->tl_next = sc->tl_cdata.tl_tx_free;
1552 sc->tl_cdata.tl_tx_free = cur_tx;
1553 if (!cur_tx->tl_ptr->tlist_fptr)
1561 * The transmit end of channel interrupt. The adapter triggers this
1562 * interrupt to tell us it hit the end of the current transmit list.
1564 * A note about this: it's possible for a condition to arise where
1565 * tl_start() may try to send frames between TXEOF and TXEOC interrupts.
1566 * You have to avoid this since the chip expects things to go in a
1567 * particular order: transmit, acknowledge TXEOF, acknowledge TXEOC.
1568 * When the TXEOF handler is called, it will free all of the transmitted
1569 * frames and reset the tx_head pointer to NULL. However, a TXEOC
1570 * interrupt should be received and acknowledged before any more frames
1571 * are queued for transmission. If tl_statrt() is called after TXEOF
1572 * resets the tx_head pointer but _before_ the TXEOC interrupt arrives,
1573 * it could attempt to issue a transmit command prematurely.
1575 * To guard against this, tl_start() will only issue transmit commands
1576 * if the tl_txeoc flag is set, and only the TXEOC interrupt handler
1577 * can set this flag once tl_start() has cleared it.
1579 static int tl_intvec_txeoc(xsc, type)
1583 struct tl_softc *sc;
1588 ifp = &sc->arpcom.ac_if;
1590 /* Clear the timeout timer. */
1593 if (sc->tl_cdata.tl_tx_head == NULL) {
1594 ifp->if_flags &= ~IFF_OACTIVE;
1595 sc->tl_cdata.tl_tx_tail = NULL;
1599 /* First we have to ack the EOC interrupt. */
1600 CMD_PUT(sc, TL_CMD_ACK | 0x00000001 | type);
1601 /* Then load the address of the next TX list. */
1602 CSR_WRITE_4(sc, TL_CH_PARM,
1603 vtophys(sc->tl_cdata.tl_tx_head->tl_ptr));
1604 /* Restart TX channel. */
1605 cmd = CSR_READ_4(sc, TL_HOSTCMD);
1607 cmd |= TL_CMD_GO|TL_CMD_INTSON;
1615 static int tl_intvec_adchk(xsc, type)
1619 struct tl_softc *sc;
1624 if_printf(&sc->arpcom.ac_if, "adapter check: %x\n",
1625 (unsigned int)CSR_READ_4(sc, TL_CH_PARM));
1628 tl_softreset(sc, 1);
1631 CMD_SET(sc, TL_CMD_INTSON);
1636 static int tl_intvec_netsts(xsc, type)
1640 struct tl_softc *sc;
1645 netsts = tl_dio_read16(sc, TL_NETSTS);
1646 tl_dio_write16(sc, TL_NETSTS, netsts);
1648 if_printf(&sc->arpcom.ac_if, "network status: %x\n", netsts);
1653 static void tl_intr(xsc)
1656 struct tl_softc *sc;
1665 /* Disable interrupts */
1666 ints = CSR_READ_2(sc, TL_HOST_INT);
1667 CSR_WRITE_2(sc, TL_HOST_INT, ints);
1668 type = (ints << 16) & 0xFFFF0000;
1669 ivec = (ints & TL_VEC_MASK) >> 5;
1670 ints = (ints & TL_INT_MASK) >> 2;
1672 ifp = &sc->arpcom.ac_if;
1675 case (TL_INTR_INVALID):
1677 if_printf(ifp, "got an invalid interrupt!\n");
1679 /* Re-enable interrupts but don't ack this one. */
1683 case (TL_INTR_TXEOF):
1684 r = tl_intvec_txeof((void *)sc, type);
1686 case (TL_INTR_TXEOC):
1687 r = tl_intvec_txeoc((void *)sc, type);
1689 case (TL_INTR_STATOFLOW):
1690 tl_stats_update(sc);
1693 case (TL_INTR_RXEOF):
1694 r = tl_intvec_rxeof((void *)sc, type);
1696 case (TL_INTR_DUMMY):
1697 if_printf(ifp, "got a dummy interrupt\n");
1700 case (TL_INTR_ADCHK):
1702 r = tl_intvec_adchk((void *)sc, type);
1704 r = tl_intvec_netsts((void *)sc, type);
1706 case (TL_INTR_RXEOC):
1707 r = tl_intvec_rxeoc((void *)sc, type);
1710 if_printf(ifp, "bogus interrupt type\n");
1714 /* Re-enable interrupts */
1716 CMD_PUT(sc, TL_CMD_ACK | r | type);
1719 if (!ifq_is_empty(&ifp->if_snd))
1725 static void tl_stats_update(xsc)
1728 struct tl_softc *sc;
1730 struct tl_stats tl_stats;
1731 struct mii_data *mii;
1736 bzero((char *)&tl_stats, sizeof(struct tl_stats));
1739 ifp = &sc->arpcom.ac_if;
1741 p = (u_int32_t *)&tl_stats;
1743 CSR_WRITE_2(sc, TL_DIO_ADDR, TL_TXGOODFRAMES|TL_DIO_ADDR_INC);
1744 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1745 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1746 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1747 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1748 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1750 ifp->if_opackets += tl_tx_goodframes(tl_stats);
1751 ifp->if_collisions += tl_stats.tl_tx_single_collision +
1752 tl_stats.tl_tx_multi_collision;
1753 ifp->if_ipackets += tl_rx_goodframes(tl_stats);
1754 ifp->if_ierrors += tl_stats.tl_crc_errors + tl_stats.tl_code_errors +
1755 tl_rx_overrun(tl_stats);
1756 ifp->if_oerrors += tl_tx_underrun(tl_stats);
1758 if (tl_tx_underrun(tl_stats)) {
1760 tx_thresh = tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_TXTHRESH;
1761 if (tx_thresh != TL_AC_TXTHRESH_WHOLEPKT) {
1764 if_printf(ifp, "tx underrun -- increasing "
1765 "tx threshold to %d bytes\n",
1766 (64 * (tx_thresh * 4)));
1767 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH);
1768 tl_dio_setbit(sc, TL_ACOMMIT, tx_thresh << 4);
1772 callout_reset(&sc->tl_stat_timer, hz, tl_stats_update, sc);
1774 if (!sc->tl_bitrate) {
1775 mii = device_get_softc(sc->tl_miibus);
1785 * Encapsulate an mbuf chain in a list by coupling the mbuf data
1786 * pointers to the fragment pointers.
1788 static int tl_encap(sc, c, m_head)
1789 struct tl_softc *sc;
1791 struct mbuf *m_head;
1794 struct tl_frag *f = NULL;
1799 * Start packing the mbufs in this chain into
1800 * the fragment pointers. Stop when we run out
1801 * of fragments or hit the end of the mbuf chain.
1806 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1807 if (m->m_len != 0) {
1808 if (frag == TL_MAXFRAGS)
1810 total_len+= m->m_len;
1811 c->tl_ptr->tl_frag[frag].tlist_dadr =
1812 vtophys(mtod(m, vm_offset_t));
1813 c->tl_ptr->tl_frag[frag].tlist_dcnt = m->m_len;
1819 * Handle special cases.
1820 * Special case #1: we used up all 10 fragments, but
1821 * we have more mbufs left in the chain. Copy the
1822 * data into an mbuf cluster. Note that we don't
1823 * bother clearing the values in the other fragment
1824 * pointers/counters; it wouldn't gain us anything,
1825 * and would waste cycles.
1830 m_new = m_getl(m_head->m_pkthdr.len, MB_DONTWAIT, MT_DATA,
1832 if (m_new == NULL) {
1833 if_printf(&sc->arpcom.ac_if, "no memory for tx list\n");
1836 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1837 mtod(m_new, caddr_t));
1838 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1841 f = &c->tl_ptr->tl_frag[0];
1842 f->tlist_dadr = vtophys(mtod(m_new, caddr_t));
1843 f->tlist_dcnt = total_len = m_new->m_len;
1848 * Special case #2: the frame is smaller than the minimum
1849 * frame size. We have to pad it to make the chip happy.
1851 if (total_len < TL_MIN_FRAMELEN) {
1852 if (frag == TL_MAXFRAGS) {
1853 if_printf(&sc->arpcom.ac_if, "all frags filled but "
1854 "frame still to small!\n");
1856 f = &c->tl_ptr->tl_frag[frag];
1857 f->tlist_dcnt = TL_MIN_FRAMELEN - total_len;
1858 f->tlist_dadr = vtophys(&sc->tl_ldata->tl_pad);
1859 total_len += f->tlist_dcnt;
1863 c->tl_mbuf = m_head;
1864 c->tl_ptr->tl_frag[frag - 1].tlist_dcnt |= TL_LAST_FRAG;
1865 c->tl_ptr->tlist_frsize = total_len;
1866 c->tl_ptr->tlist_cstat = TL_CSTAT_READY;
1867 c->tl_ptr->tlist_fptr = 0;
1873 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1874 * to the mbuf data regions directly in the transmit lists. We also save a
1875 * copy of the pointers since the transmit list fragment pointers are
1876 * physical addresses.
1878 static void tl_start(ifp)
1881 struct tl_softc *sc;
1882 struct mbuf *m_head = NULL;
1884 struct tl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
1889 * Check for an available queue slot. If there are none,
1892 if (sc->tl_cdata.tl_tx_free == NULL) {
1893 ifp->if_flags |= IFF_OACTIVE;
1897 start_tx = sc->tl_cdata.tl_tx_free;
1899 while(sc->tl_cdata.tl_tx_free != NULL) {
1900 m_head = ifq_dequeue(&ifp->if_snd);
1904 /* Pick a chain member off the free list. */
1905 cur_tx = sc->tl_cdata.tl_tx_free;
1906 sc->tl_cdata.tl_tx_free = cur_tx->tl_next;
1908 cur_tx->tl_next = NULL;
1910 /* Pack the data into the list. */
1911 tl_encap(sc, cur_tx, m_head);
1913 /* Chain it together */
1915 prev->tl_next = cur_tx;
1916 prev->tl_ptr->tlist_fptr = vtophys(cur_tx->tl_ptr);
1920 BPF_MTAP(ifp, cur_tx->tl_mbuf);
1924 * If there are no packets queued, bail.
1930 * That's all we can stands, we can't stands no more.
1931 * If there are no other transfers pending, then issue the
1932 * TX GO command to the adapter to start things moving.
1933 * Otherwise, just leave the data in the queue and let
1934 * the EOF/EOC interrupt handler send.
1936 if (sc->tl_cdata.tl_tx_head == NULL) {
1937 sc->tl_cdata.tl_tx_head = start_tx;
1938 sc->tl_cdata.tl_tx_tail = cur_tx;
1942 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(start_tx->tl_ptr));
1943 cmd = CSR_READ_4(sc, TL_HOSTCMD);
1945 cmd |= TL_CMD_GO|TL_CMD_INTSON;
1949 sc->tl_cdata.tl_tx_tail->tl_next = start_tx;
1950 sc->tl_cdata.tl_tx_tail = cur_tx;
1954 * Set a timeout in case the chip goes out to lunch.
1961 static void tl_init(xsc)
1964 struct tl_softc *sc = xsc;
1965 struct ifnet *ifp = &sc->arpcom.ac_if;
1966 struct mii_data *mii;
1971 * Cancel pending I/O.
1975 /* Initialize TX FIFO threshold */
1976 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH);
1977 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH_16LONG);
1979 /* Set PCI burst size */
1980 tl_dio_write8(sc, TL_BSIZEREG, TL_RXBURST_16LONG|TL_TXBURST_16LONG);
1983 * Set 'capture all frames' bit for promiscuous mode.
1985 if (ifp->if_flags & IFF_PROMISC)
1986 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF);
1988 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF);
1991 * Set capture broadcast bit to capture broadcast frames.
1993 if (ifp->if_flags & IFF_BROADCAST)
1994 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_NOBRX);
1996 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NOBRX);
1998 tl_dio_write16(sc, TL_MAXRX, MCLBYTES);
2000 /* Init our MAC address */
2001 tl_setfilt(sc, (caddr_t)&sc->arpcom.ac_enaddr, 0);
2003 /* Init multicast filter, if needed. */
2006 /* Init circular RX list. */
2007 if (tl_list_rx_init(sc) == ENOBUFS) {
2008 if_printf(ifp, "initialization failed: no "
2009 "memory for rx buffers\n");
2014 /* Init TX pointers. */
2015 tl_list_tx_init(sc);
2017 /* Enable PCI interrupts. */
2018 CMD_SET(sc, TL_CMD_INTSON);
2020 /* Load the address of the rx list */
2021 CMD_SET(sc, TL_CMD_RT);
2022 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(&sc->tl_ldata->tl_rx_list[0]));
2024 if (!sc->tl_bitrate) {
2025 if (sc->tl_miibus != NULL) {
2026 mii = device_get_softc(sc->tl_miibus);
2031 /* Send the RX go command */
2032 CMD_SET(sc, TL_CMD_GO|TL_CMD_NES|TL_CMD_RT);
2034 ifp->if_flags |= IFF_RUNNING;
2035 ifp->if_flags &= ~IFF_OACTIVE;
2037 /* Start the stats update counter */
2038 callout_reset(&sc->tl_stat_timer, hz, tl_stats_update, sc);
2044 * Set media options.
2046 static int tl_ifmedia_upd(ifp)
2049 struct tl_softc *sc;
2050 struct mii_data *mii = NULL;
2055 tl_setmode(sc, sc->ifmedia.ifm_media);
2057 mii = device_get_softc(sc->tl_miibus);
2065 * Report current media status.
2067 static void tl_ifmedia_sts(ifp, ifmr)
2069 struct ifmediareq *ifmr;
2071 struct tl_softc *sc;
2072 struct mii_data *mii;
2076 ifmr->ifm_active = IFM_ETHER;
2078 if (sc->tl_bitrate) {
2079 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD1)
2080 ifmr->ifm_active = IFM_ETHER|IFM_10_5;
2082 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
2083 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD3)
2084 ifmr->ifm_active |= IFM_HDX;
2086 ifmr->ifm_active |= IFM_FDX;
2089 mii = device_get_softc(sc->tl_miibus);
2091 ifmr->ifm_active = mii->mii_media_active;
2092 ifmr->ifm_status = mii->mii_media_status;
2098 static int tl_ioctl(ifp, command, data, cr)
2104 struct tl_softc *sc = ifp->if_softc;
2105 struct ifreq *ifr = (struct ifreq *) data;
2112 if (ifp->if_flags & IFF_UP) {
2113 if (ifp->if_flags & IFF_RUNNING &&
2114 ifp->if_flags & IFF_PROMISC &&
2115 !(sc->tl_if_flags & IFF_PROMISC)) {
2116 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF);
2118 } else if (ifp->if_flags & IFF_RUNNING &&
2119 !(ifp->if_flags & IFF_PROMISC) &&
2120 sc->tl_if_flags & IFF_PROMISC) {
2121 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF);
2126 if (ifp->if_flags & IFF_RUNNING) {
2130 sc->tl_if_flags = ifp->if_flags;
2141 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
2143 struct mii_data *mii;
2144 mii = device_get_softc(sc->tl_miibus);
2145 error = ifmedia_ioctl(ifp, ifr,
2146 &mii->mii_media, command);
2150 error = ether_ioctl(ifp, command, data);
2159 static void tl_watchdog(ifp)
2162 struct tl_softc *sc;
2166 if_printf(ifp, "device timeout\n");
2170 tl_softreset(sc, 1);
2177 * Stop the adapter and free any mbufs allocated to the
2180 static void tl_stop(sc)
2181 struct tl_softc *sc;
2186 ifp = &sc->arpcom.ac_if;
2188 /* Stop the stats updater. */
2189 callout_stop(&sc->tl_stat_timer);
2191 /* Stop the transmitter */
2192 CMD_CLR(sc, TL_CMD_RT);
2193 CMD_SET(sc, TL_CMD_STOP);
2194 CSR_WRITE_4(sc, TL_CH_PARM, 0);
2196 /* Stop the receiver */
2197 CMD_SET(sc, TL_CMD_RT);
2198 CMD_SET(sc, TL_CMD_STOP);
2199 CSR_WRITE_4(sc, TL_CH_PARM, 0);
2202 * Disable host interrupts.
2204 CMD_SET(sc, TL_CMD_INTSOFF);
2207 * Clear list pointer.
2209 CSR_WRITE_4(sc, TL_CH_PARM, 0);
2212 * Free the RX lists.
2214 for (i = 0; i < TL_RX_LIST_CNT; i++) {
2215 if (sc->tl_cdata.tl_rx_chain[i].tl_mbuf != NULL) {
2216 m_freem(sc->tl_cdata.tl_rx_chain[i].tl_mbuf);
2217 sc->tl_cdata.tl_rx_chain[i].tl_mbuf = NULL;
2220 bzero((char *)&sc->tl_ldata->tl_rx_list,
2221 sizeof(sc->tl_ldata->tl_rx_list));
2224 * Free the TX list buffers.
2226 for (i = 0; i < TL_TX_LIST_CNT; i++) {
2227 if (sc->tl_cdata.tl_tx_chain[i].tl_mbuf != NULL) {
2228 m_freem(sc->tl_cdata.tl_tx_chain[i].tl_mbuf);
2229 sc->tl_cdata.tl_tx_chain[i].tl_mbuf = NULL;
2232 bzero((char *)&sc->tl_ldata->tl_tx_list,
2233 sizeof(sc->tl_ldata->tl_tx_list));
2235 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2241 * Stop all chip I/O so that the kernel's probe routines don't
2242 * get confused by errant DMAs when rebooting.
2244 static void tl_shutdown(dev)
2247 struct tl_softc *sc;
2249 sc = device_get_softc(dev);