2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/dev/re/if_rereg.h,v 1.14.2.1 2001/07/19 18:33:07 wpaul Exp $
36 /*#define VERSION(_MainVer,_MinorVer) ((_MainVer)*10+(_MinorVer))*/
37 /*#define OS_VER VERSION(5,1)*/
38 #if __FreeBSD_version < 500000
39 #define VERSION(_MainVer,_MinorVer) ((_MainVer)*100000+(_MinorVer)*10000)
41 #define VERSION(_MainVer,_MinorVer) ((_MainVer)*100000+(_MinorVer)*1000)
43 #define OS_VER __FreeBSD_version
46 #define M_DONTWAIT M_NOWAIT
49 #if OS_VER>=VERSION(4,0)
50 #define RE_USE_NEW_CALLOUT_FUN 1
52 #endif /* !__DragonFly__ */
56 * RealTek RTL8110S/SB/SC register offsets
59 #define RE_TPPOLL 0x0038 /* transmit priority polling */
62 * RealTek RTL8110S/SB/SC register contents
65 /* Transmit Priority Polling --- 0x40 */
66 #define RE_HPQ 0x80 /* high priority queue polling */
67 #define RE_NPQ 0x40 /* normal priority queue polling */
68 #define RE_FSWInt 0x01 /* Forced Software Interrupt */
72 * RealTek 8129/8139 register offsets
75 #define RE_IDR0 0x0000 /* ID register 0 (station addr) */
76 #define RE_IDR1 0x0001 /* Must use 32-bit accesses (?) */
77 #define RE_IDR2 0x0002
78 #define RE_IDR3 0x0003
79 #define RE_IDR4 0x0004
80 #define RE_IDR5 0x0005
81 /* 0006-0007 reserved */
82 #define RE_MAR0 0x0008 /* Multicast hash table */
83 #define RE_MAR1 0x0009
84 #define RE_MAR2 0x000A
85 #define RE_MAR3 0x000B
86 #define RE_MAR4 0x000C
87 #define RE_MAR5 0x000D
88 #define RE_MAR6 0x000E
89 #define RE_MAR7 0x000F
91 #define RE_TXSTAT0 0x0010 /* status of TX descriptor 0 */
92 #define RE_TXSTAT1 0x0014 /* status of TX descriptor 1 */
93 #define RE_TXSTAT2 0x0018 /* status of TX descriptor 2 */
94 #define RE_CUSTOM_LED 0x0018
95 #define RE_TXSTAT3 0x001C /* status of TX descriptor 3 */
97 #define RE_TXADDR0 0x0020 /* address of TX descriptor 0 */
98 #define RE_TXADDR1 0x0024 /* address of TX descriptor 1 */
99 #define RE_TXADDR2 0x0028 /* address of TX descriptor 2 */
100 #define RE_TXADDR3 0x002C /* address of TX descriptor 3 */
102 #define RE_RXADDR 0x0030 /* RX ring start address */
103 #define RE_COMMAND 0x0037 /* command register */
104 #define RE_CURRXADDR 0x0038 /* current address of packet read */
105 #define RE_CURRXBUF 0x003A /* current RX buffer address */
106 #define RE_IMR 0x003C /* interrupt mask register */
107 #define RE_ISR 0x003E /* interrupt status register */
108 #define RE_TXCFG 0x0040 /* transmit config */
109 #define RE_RXCFG 0x0044 /* receive config */
110 #define RE_TIMERCNT 0x0048 /* timer count register */
111 #define RE_MISSEDPKT 0x004C /* missed packet counter */
112 #define RE_EECMD 0x0050 /* EEPROM command register */
113 #define RE_CFG0 0x0051 /* config register #0 */
114 #define RE_CFG1 0x0052 /* config register #1 */
115 #define RE_CFG2 0x0053 /* config register #2 */
116 #define RE_CFG3 0x0054 /* config register #3 */
117 #define RE_CFG4 0x0055 /* config register #4 */
118 #define RE_CFG5 0x0056 /* config register #5 */
119 /* 0053-0057 reserved */
120 #define RE_TDFNR 0x0057 /* Tx descriptor fetch number */
121 #define RE_MEDIASTAT 0x0058 /* media status register (8139) */
122 /* 0059-005A reserved */
123 #define RE_MII 0x005A /* 8129 chip only */
124 #define RE_HALTCLK 0x005B
125 #define RE_MULTIINTR 0x005C /* multiple interrupt */
126 #define RE_PCIREV 0x005E /* PCI revision value */
128 #define RE_PHYAR 0x0060 /* PHY register access */
129 #define RE_CSIDR 0x0064
130 #define RE_CSIAR 0x0068
131 #define RE_PHY_STATUS 0x006C /* PHY status */
132 #define RE_MACDBG 0x006D
133 #define RE_PMCH 0x006F /* 8 bits */
134 #define RE_ERIDR 0x0070
135 #define RE_ERIAR 0x0074
136 #define RE_EPHY_RXER_NUM 0x007C
137 #define RE_EPHYAR 0x0080
138 #define RE_MCUACCESS 0x00B0
139 #define RE_OCPDR 0x00B0
140 #define RE_OCPAR 0x00B4
141 #define RE_SecMAC0 0x00B4
142 #define RE_SecMAC4 0x00B8
143 #define RE_PHYOCPACCESS 0x00B8
144 #define RE_DBG_reg 0x00D1
145 #define RE_TwiCmdReg 0x00D2
146 #define RE_MCU_CMD 0x00D3
147 #define RE_RxMaxSize 0x00DA
148 #define RE_EFUSEAR 0x00DC
149 #define RE_CPlusCmd 0x00E0
150 #define RE_MTPS 0x00EC
151 #define RE_CMAC_IBCR0 0x00F8
152 #define RE_CMAC_IBCR2 0x00F9
153 #define RE_CMAC_IBIMR0 0x00FA
154 #define RE_CMAC_IBISR0 0x00FB
157 #define ERIAR_Flag 0x80000000
158 #define ERIAR_Write 0x80000000
159 #define ERIAR_Read 0x00000000
160 #define ERIAR_Addr_Align 4 /* ERI access register address must be 4 byte alignment */
161 #define ERIAR_ExGMAC 0
164 #define ERIAR_Type_shift 16
165 #define ERIAR_ByteEn 0x0f
166 #define ERIAR_ByteEn_shift 12
173 /* Direct PHY access registers only available on 8139 */
174 #define RE_BMCR 0x0062 /* PHY basic mode control */
175 #define RE_BMSR 0x0064 /* PHY basic mode status */
176 #define RE_ANAR 0x0066 /* PHY autoneg advert */
177 #define RE_LPAR 0x0068 /* PHY link partner ability */
178 #define RE_ANER 0x006A /* PHY autoneg expansion */
180 #define RE_DISCCNT 0x006C /* disconnect counter */
181 #define RE_FALSECAR 0x006E /* false carrier counter */
182 #define RE_NWAYTST 0x0070 /* NWAY test register */
183 #define RE_RX_ER 0x0072 /* RX_ER counter */
184 #define RE_CSCFG 0x0074 /* CS configuration register */
185 #define RE_LDPS 0x0082 /* Link Down Power Saving */
186 #define RE_CPCR 0x00E0
191 * TX config register bits
193 #define RE_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */
194 #define RE_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */
195 #define RE_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */
196 #define RE_TXCFG_LOOPBKTST 0x00060000 /* loopback test */
197 #define RE_TXCFG_IFG 0x03000000 /* interframe gap */
199 #define RE_TXDMA_16BYTES 0x00000000
200 #define RE_TXDMA_32BYTES 0x00000100
201 #define RE_TXDMA_64BYTES 0x00000200
202 #define RE_TXDMA_128BYTES 0x00000300
203 #define RE_TXDMA_256BYTES 0x00000400
204 #define RE_TXDMA_512BYTES 0x00000500
205 #define RE_TXDMA_1024BYTES 0x00000600
206 #define RE_TXDMA_2048BYTES 0x00000700
209 * Transmit descriptor status register bits.
211 #define RE_TXSTAT_LENMASK 0x00001FFF
212 #define RE_TXSTAT_OWN 0x00002000
213 #define RE_TXSTAT_TX_UNDERRUN 0x00004000
214 #define RE_TXSTAT_TX_OK 0x00008000
215 #define RE_TXSTAT_COLLCNT 0x0F000000
216 #define RE_TXSTAT_CARR_HBEAT 0x10000000
217 #define RE_TXSTAT_OUTOFWIN 0x20000000
218 #define RE_TXSTAT_TXABRT 0x40000000
219 #define RE_TXSTAT_CARRLOSS 0x80000000
222 * Interrupt status register bits.
224 #define RE_ISR_RX_OK 0x0001
225 #define RE_ISR_RX_ERR 0x0002
226 #define RE_ISR_TX_OK 0x0004
227 #define RE_ISR_TX_ERR 0x0008
228 #define RE_ISR_RX_OVERRUN 0x0010
229 #define RE_ISR_PKT_UNDERRUN 0x0020
230 #define RE_ISR_LINKCHG 0x0020
231 #define RE_ISR_FIFO_OFLOW 0x0040 /* 8139 only */
232 #define RE_ISR_TDU 0x0080
233 #define RE_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */
234 #define RE_ISR_SYSTEM_ERR 0x8000
238 (RE_ISR_TX_OK|RE_ISR_RX_OK|RE_ISR_RX_ERR|RE_ISR_TX_ERR| \
239 RE_ISR_RX_OVERRUN|RE_ISR_PKT_UNDERRUN|RE_ISR_FIFO_OFLOW| \
240 RE_ISR_PCS_TIMEOUT|RE_ISR_SYSTEM_ERR)
244 (RE_ISR_TX_OK|RE_ISR_RX_OK|RE_ISR_RX_ERR|RE_ISR_TX_ERR| \
245 RE_ISR_RX_OVERRUN|RE_ISR_PKT_UNDERRUN|RE_ISR_TDU| \
246 RE_ISR_PCS_TIMEOUT|RE_ISR_SYSTEM_ERR)
249 * Media status register. (8139 only)
251 #define RE_MEDIASTAT_RXPAUSE 0x01
252 #define RE_MEDIASTAT_TXPAUSE 0x02
253 #define RE_MEDIASTAT_LINK 0x04
254 #define RE_MEDIASTAT_SPEED10 0x08
255 #define RE_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */
256 #define RE_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */
259 * Receive config register.
261 #define RE_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */
262 #define RE_RXCFG_RX_INDIV 0x00000002 /* match filter */
263 #define RE_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */
264 #define RE_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */
265 #define RE_RXCFG_RX_RUNT 0x00000010
266 #define RE_RXCFG_RX_ERRPKT 0x00000020
267 #define RE_RXCFG_RX_9356SEL 0x00000040
268 #define RE_RXCFG_WRAP 0x00000080
269 #define RE_RXCFG_MAXDMA 0x00000700
270 #define RE_RXCFG_BUFSZ 0x00001800
272 #define RE_RXDMA_16BYTES 0x00000000
273 #define RE_RXDMA_32BYTES 0x00000100
274 #define RE_RXDMA_64BYTES 0x00000200
275 #define RE_RXDMA_128BYTES 0x00000300
276 #define RE_RXDMA_256BYTES 0x00000400
277 #define RE_RXDMA_512BYTES 0x00000500
278 #define RE_RXDMA_1024BYTES 0x00000600
279 #define RE_RXDMA_UNLIMITED 0x00000700
281 #define RE_RXBUF_8 0x00000000
282 #define RE_RXBUF_16 0x00000800
283 #define RE_RXBUF_32 0x00001000
284 #define RE_RXBUF_64 0x00001800
286 #define RE_RXRESVERED 0x0000E000
289 * Bits in RX status header (included with RX'ed packet
292 #define RE_RXSTAT_RXOK 0x00000001
293 #define RE_RXSTAT_ALIGNERR 0x00000002
294 #define RE_RXSTAT_CRCERR 0x00000004
295 #define RE_RXSTAT_GIANT 0x00000008
296 #define RE_RXSTAT_RUNT 0x00000010
297 #define RE_RXSTAT_BADSYM 0x00000020
298 #define RE_RXSTAT_BROAD 0x00002000
299 #define RE_RXSTAT_INDIV 0x00004000
300 #define RE_RXSTAT_MULTI 0x00008000
301 #define RE_RXSTAT_LENMASK 0xFFFF0000
303 #define RE_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */
307 #define RE_CMD_EMPTY_RXBUF 0x0001
308 #define RE_CMD_TX_ENB 0x0004
309 #define RE_CMD_RX_ENB 0x0008
310 #define RE_CMD_RESET 0x0010
313 * EEPROM control register
315 #define RE_EE_DATAOUT 0x01 /* Data out */
316 #define RE_EE_DATAIN 0x02 /* Data in */
317 #define RE_EE_CLK 0x04 /* clock */
318 #define RE_EE_SEL 0x08 /* chip select */
319 #define RE_EE_MODE (0x40|0x80)
321 #define RE_EEMODE_OFF 0x00
322 #define RE_EEMODE_AUTOLOAD 0x40
323 #define RE_EEMODE_PROGRAM 0x80
324 #define RE_EEMODE_WRITECFG (0x80|0x40)
326 /* 9346 EEPROM commands */
327 #define RE_EECMD_WRITE 0x140
328 #define RE_EECMD_READ 0x180
329 #define RE_EECMD_ERASE 0x1c0
331 #define RE_EE_ID 0x00
332 #define RE_EE_PCI_VID 0x01
333 #define RE_EE_PCI_DID 0x02
334 /* Location of station address inside EEPROM */
335 #define RE_EE_EADDR 0x07
338 * MII register (8129 only)
340 #define RE_MII_CLK 0x01
341 #define RE_MII_DATAIN 0x02
342 #define RE_MII_DATAOUT 0x04
343 #define RE_MII_DIR 0x80 /* 0 == input, 1 == output */
348 #define RE_CFG0_ROM0 0x01
349 #define RE_CFG0_ROM1 0x02
350 #define RE_CFG0_ROM2 0x04
351 #define RE_CFG0_PL0 0x08
352 #define RE_CFG0_PL1 0x10
353 #define RE_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */
354 #define RE_CFG0_PCS 0x40
355 #define RE_CFG0_SCR 0x80
360 #define RE_CFG1_PME 0x01
361 #define RE_CFG1_IOMAP 0x04
362 #define RE_CFG1_MEMMAP 0x08
363 #define RE_CFG1_RSVD 0x10
364 #define RE_CFG1_LED0 0x40
365 #define RE_CFG1_LED1 0x80
370 #define RL_CFG3_GRANTSEL 0x80
371 #define RL_CFG3_WOL_MAGIC 0x20
372 #define RL_CFG3_WOL_LINK 0x10
373 #define RL_CFG3_JUMBO_EN0 0x04 /* RTL8168C or later. */
374 #define RL_CFG3_FAST_B2B 0x01
379 #define RL_CFG4_LWPTN 0x04
380 #define RL_CFG4_LWPME 0x10
381 #define RL_CFG4_JUMBO_EN1 0x02 /* RTL8168C or later. */
382 #define RL_CFG4_CUSTOMIZED_LED 0x40
387 #define RL_CFG5_WOL_BCAST 0x40
388 #define RL_CFG5_WOL_MCAST 0x20
389 #define RL_CFG5_WOL_UCAST 0x10
390 #define RL_CFG5_WOL_LANWAKE 0x02
391 #define RL_CFG5_PME_STS 0x01
394 * PHY Status register
396 #define RL_PHY_STATUS_1000MF 0x10
397 #define RL_PHY_STATUS_100M 0x08
398 #define RL_PHY_STATUS_10M 0x04
399 #define RL_PHY_STATUS_LINK_STS 0x02
400 #define RL_PHY_STATUS_FULL_DUP 0x01
402 /* OCP GPHY access */
403 #define OCPDR_Write 0x80000000
404 #define OCPDR_Read 0x00000000
405 #define OCPDR_Reg_Mask 0xFF
406 #define OCPDR_Data_Mask 0xFFFF
407 #define OCPDR_GPHY_Reg_shift 16
408 #define OCPAR_Flag 0x80000000
409 #define OCPAR_GPHY_Write 0x8000F060
410 #define OCPAR_GPHY_Read 0x0000F060
411 #define OCPR_Write 0x80000000
412 #define OCPR_Read 0x00000000
413 #define OCPR_Addr_Reg_shift 16
414 #define OCPR_Flag 0x80000000
415 #define OCP_STD_PHY_BASE_PAGE 0x0A40
418 #define RE_NOW_IS_OOB (1 << 7)
419 #define RE_TXFIFO_EMPTY (1 << 5)
420 #define RE_RXFIFO_EMPTY (1 << 4)
423 #define OOB_CMD_RESET 0x00
424 #define OOB_CMD_DRIVER_START 0x05
425 #define OOB_CMD_DRIVER_STOP 0x06
426 #define OOB_CMD_SET_IPMAC 0x41
428 /* Ethernet PHY MDI Mode */
429 #define RE_ETH_PHY_FORCE_MDI 0
430 #define RE_ETH_PHY_FORCE_MDIX 1
431 #define RE_ETH_PHY_AUTO_MDI_MDIX 2
434 * The RealTek doesn't use a fragment-based descriptor mechanism.
435 * Instead, there are only four register sets, each or which represents
436 * one 'descriptor.' Basically, each TX descriptor is just a contiguous
437 * packet buffer (32-bit aligned!) and we place the buffer addresses in
438 * the registers so the chip knows where they are.
440 * We can sort of kludge together the same kind of buffer management
441 * used in previous drivers, but we have to do buffer copies almost all
442 * the time, so it doesn't really buy us much.
444 * For reception, there's just one large buffer where the chip stores
445 * all received packets.
447 #ifndef __NO_STRICT_ALIGNMENT
448 #define RE_FIXUP_RX 1
452 #define RE_RX_BUF_SZ RE_RXBUF_64
453 #define RE_RXBUFLEN (1 << ((RE_RX_BUF_SZ >> 11) + 13))
454 #define RE_TX_LIST_CNT 4 /* C mode Tx buffer number */
455 #define RE_TX_BUF_NUM 256 /* Tx buffer number */
456 #define RE_RX_BUF_NUM 256 /* Rx buffer number */
457 #define RE_BUF_SIZE 9216 /* Buffer size of descriptor buffer */
458 #define RE_MIN_FRAMELEN 60
459 #define RE_TXREV(x) ((x) << 11)
460 #define RE_RX_RESVERED RE_RXRESVERED
461 #define RE_RX_MAXDMA RE_RXDMA_UNLIMITED
462 #define RE_TX_MAXDMA RE_TXDMA_2048BYTES
463 #define RE_NTXSEGS 32
465 #define RE_TXCFG_CONFIG 0x03000780 //(RE_TXCFG_IFG|RE_TX_MAXDMA)
467 #define RE_DESC_ALIGN 256 /* descriptor alignment */
468 #define RE_RX_BUFFER_ALIGN 8 /* descriptor alignment */
471 #define RE_ETHER_ALIGN RE_RX_BUFFER_ALIGN
473 #define RE_ETHER_ALIGN 0
477 #ifndef ETHER_VLAN_ENCAP_LEN
478 #define ETHER_VLAN_ENCAP_LEN EVL_ENCAPLEN
481 #define Jumbo_Frame_2k ((2 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)
482 #define Jumbo_Frame_3k ((3 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)
483 #define Jumbo_Frame_4k ((4 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)
484 #define Jumbo_Frame_5k ((5 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)
485 #define Jumbo_Frame_6k ((6 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)
486 #define Jumbo_Frame_7k ((7 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)
487 #define Jumbo_Frame_8k ((8 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)
488 #define Jumbo_Frame_9k ((9 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)
490 #ifndef __DragonFly__
491 struct re_chain_data {
494 caddr_t re_rx_buf_ptr;
496 struct mbuf *re_tx_chain[RE_TX_LIST_CNT];
497 u_int8_t last_tx; /* Previous Tx OK */
498 u_int8_t cur_tx; /* Next to TX */
501 //+++ From FreeBSD 9.0 +++
503 #define RL_MSI_MESSAGES 1
505 #define RL_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF)
506 #define RL_ADDR_HI(y) ((uint64_t) (y) >> 32)
508 * RX/TX descriptor definition. When large send mode is enabled, the
509 * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and
510 * the checksum offload bits are disabled. The structure layout is
511 * the same for RX and TX descriptors
514 #define RL_TDESC_CMD_FRAGLEN 0x0000FFFF
515 #define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */
516 #define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */
517 #define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */
518 #define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */
519 #define RL_TDESC_CMD_MSSVAL_SHIFT 16 /* Large send MSS value shift */
520 #define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */
521 #define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */
522 #define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */
523 #define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */
524 #define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */
526 #define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */
527 #define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */
528 /* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */
529 #define RL_TDESC_CMD_UDPCSUMV2 0x80000000
530 #define RL_TDESC_CMD_TCPCSUMV2 0x40000000
531 #define RL_TDESC_CMD_IPCSUMV2 0x20000000
532 #define RL_TDESC_CMD_MSSVALV2 0x1FFC0000
533 #define RL_TDESC_CMD_MSSVALV2_SHIFT 18
535 #define RL_TDESC_CMD_BUFLEN 0x0000FFFF
538 * Error bits are valid only on the last descriptor of a frame
539 * (i.e. RL_TDESC_CMD_EOF == 1)
542 #define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */
543 #define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */
544 #define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */
545 #define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */
546 #define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */
547 #define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */
548 #define RL_TDESC_STAT_OWN 0x80000000
551 * RX descriptor cmd/vlan definitions
554 #define RL_RDESC_CMD_EOR 0x40000000
555 #define RL_RDESC_CMD_OWN 0x80000000
556 #define RL_RDESC_CMD_BUFLEN 0x00003FFF
558 #define RL_RDESC_STAT_OWN 0x80000000
559 #define RL_RDESC_STAT_EOR 0x40000000
560 #define RL_RDESC_STAT_SOF 0x20000000
561 #define RL_RDESC_STAT_EOF 0x10000000
562 #define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */
563 #define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */
564 #define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */
565 #define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */
566 #define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */
567 #define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */
568 #define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */
569 #define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */
570 #define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */
571 #define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */
572 #define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */
573 #define RL_RDESC_STAT_UDP 0x00020000 /* UDP, 8168C/CP, 8111C/CP */
574 #define RL_RDESC_STAT_TCP 0x00010000 /* TCP, 8168C/CP, 8111C/CP */
575 #define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */
576 #define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */
577 #define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */
578 #define RL_RDESC_STAT_GFRAGLEN RL_RDESC_CMD_BUFLEN /* RX'ed frame/frag len */
579 #define RL_RDESC_STAT_ERRS (RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \
580 RL_RDESC_STAT_CRCERR)
582 #define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available
583 (rl_vlandata valid)*/
584 #define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */
585 /* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */
586 #define RL_RDESC_IPV6 0x80000000
587 #define RL_RDESC_IPV4 0x40000000
589 #define RL_PROTOID_NONIP 0x00000000
590 #define RL_PROTOID_TCPIP 0x00010000
591 #define RL_PROTOID_UDPIP 0x00020000
592 #define RL_PROTOID_IP 0x00030000
593 #define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \
595 #define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \
598 //--- From FreeBSD 9.0---
604 #if defined(_LITTLE_ENDIAN)
605 u_int32_t Frame_Length:14;
624 u_int32_t VLAN_TAG:16;
627 #elif defined(_BIG_ENDIAN)
645 u_int32_t Frame_Length:14;
649 u_int32_t VLAN_TAG:16;
651 #error "what endian is this machine?"
655 } so0; /* symbol owner=0 */
661 #if defined(_LITTLE_ENDIAN)
662 u_int32_t Frame_Length:16;
675 u_int32_t VLAN_TAG:16;
679 #elif defined(_BIG_ENDIAN)
691 u_int32_t Frame_Length:16;
696 u_int32_t VLAN_TAG:16;
698 #error "what endian is this machine?"
702 } so1; /* symbol owner=1 */
705 struct re_descriptor {
706 u_int8_t rx_cur_index;
707 u_int8_t rx_last_index;
708 union RxDesc *rx_desc; /* 8 bits alignment */
709 struct mbuf *rx_buf[RE_RX_BUF_NUM];
711 u_int8_t tx_cur_index;
712 u_int8_t tx_last_index;
713 union TxDesc *tx_desc; /* 8 bits alignment */
714 struct mbuf *tx_buf[RE_TX_BUF_NUM];
715 bus_dma_tag_t rx_desc_tag;
716 bus_dmamap_t rx_desc_dmamap;
717 bus_dma_tag_t re_rx_mtag; /* mbuf RX mapping tag */
718 bus_dmamap_t re_rx_dmamap[RE_RX_BUF_NUM];
720 bus_dma_tag_t tx_desc_tag;
721 bus_dmamap_t tx_desc_dmamap;
722 bus_dma_tag_t re_tx_mtag; /* mbuf TX mapping tag */
723 bus_dmamap_t re_tx_dmamap[RE_TX_BUF_NUM];
726 #define RE_INC(x) (x = (x + 1) % RE_TX_LIST_CNT)
727 #define RE_CUR_TXADDR(x) ((x->re_cdata.cur_tx * 4) + RE_TXADDR0)
728 #define RE_CUR_TXSTAT(x) ((x->re_cdata.cur_tx * 4) + RE_TXSTAT0)
729 #define RE_CUR_TXMBUF(x) (x->re_cdata.re_tx_chain[x->re_cdata.cur_tx])
730 #define RE_LAST_TXADDR(x) ((x->re_cdata.last_tx * 4) + RE_TXADDR0)
731 #define RE_LAST_TXSTAT(x) ((x->re_cdata.last_tx * 4) + RE_TXSTAT0)
732 #define RE_LAST_TXMBUF(x) (x->re_cdata.re_tx_chain[x->re_cdata.last_tx])
740 struct re_mii_frame {
741 u_int8_t mii_stdelim;
743 u_int8_t mii_phyaddr;
744 u_int8_t mii_regaddr;
745 u_int8_t mii_turnaround;
748 #endif /* !__DragonFly__ */
753 #define RE_MII_STARTDELIM 0x01
754 #define RE_MII_READOP 0x02
755 #define RE_MII_WRITEOP 0x01
756 #define RE_MII_TURNAROUND 0x02
757 #define RL_TDESC_VLANCTL_TAG 0x00020000
758 #define RL_RDESC_VLANCTL_TAG 0x00010000
759 #define RL_RDESC_VLANCTL_DATA 0x0000FFFF
760 #define RL_CPLUSCMD_VLANSTRIP 0x0040
761 #define RL_FLAG_MSI 0x00000001
762 #define RL_FLAG_PHYWAKE_PM 0x00000004
763 #define RL_FLAG_DESCV2 0x00000040
764 #define RL_FLAG_MSIX 0x00000800
765 #define RL_FLAG_MAGIC_PACKET_V2 0x20000000
766 #define RL_FLAG_PCIE 0x40000000
768 #define RL_ProtoIP ((1<<17)|(1<<18))
769 //#define RL_ProtoIP ((1<<16)|(1<<17))
770 #define RL_TCPT (1<<17)
771 #define RL_UDPT (1<<18)
772 #define RL_IPF (1<<16)
773 #define RL_UDPF (1<<15)
774 #define RL_TCPF (1<<14)
775 #define RL_V4F (1<<30)
777 #define RL_IPV4CS (1<<29)
778 #define RL_TCPCS (1<<30)
779 #define RL_UDPCS (1<<31)
780 #define RL_IPV4CS1 (1<<18)
781 #define RL_TCPCS1 (1<<16)
782 #define RL_UDPCS1 (1<<17)
784 #define RL_RxChkSum (1<<5)
787 EFUSE_NOT_SUPPORT = 0,
857 //#define MAC_STYLE_1 1 /* RTL8110S/SB/SC, RTL8111B and RTL8101E */
858 //#define MAC_STYLE_2 2 /* RTL8111C/CP/D and RTL8102E */
860 #ifndef __DragonFly__
862 #if OS_VER<VERSION(6,0)
863 struct arpcom arpcom; /* interface info */
865 struct ifnet *re_ifp;
868 bus_space_handle_t re_bhandle; /* bus space handle */
869 bus_space_tag_t re_btag; /* bus space tag */
870 struct resource *re_res;
873 struct resource *re_res_pba;
874 struct resource *re_irq;
876 struct ifmedia media; /* used to instead of MII */
878 /* Variable for 8169 family */
879 u_int8_t re_8169_MacVersion;
880 u_int8_t re_8169_PhyVersion;
882 u_int8_t rx_fifo_overflow;
883 u_int8_t driver_detach;
885 u_int8_t re_unit; /* interface number */
887 u_int8_t re_stats_no_timeout;
889 u_int16_t re_device_id;
891 struct re_chain_data re_cdata; /* Tx buffer chain, Used only in ~C+ mode */
892 struct re_descriptor re_desc; /* Descriptor, Used only in C+ mode */
893 #ifdef RE_USE_NEW_CALLOUT_FUN
894 struct callout re_stat_ch;
896 struct callout_handle re_stat_ch;
898 u_int8_t re_link_chg_det;
900 bus_dma_tag_t re_parent_tag;
903 int max_jumbo_frame_size;
905 int re_rx_desc_buf_sz;
909 int suspended; /* 0 = normal 1 = suspended */
911 u_int8_t RequireAdcBiasPatch;
912 u_int16_t AdcBiasPatchIoffset;
914 u_int8_t RequireAdjustUpsTxLinkPulseTiming;
915 u_int16_t SwrCnt1msIni;
917 u_int8_t RequiredSecLanDonglePatch;
919 u_int8_t re_efuse_ver;
921 u_int16_t re_sw_ram_code_ver;
922 u_int16_t re_hw_ram_code_ver;
923 #if OS_VER>=VERSION(7,0)
924 struct task re_inttask;
928 u_int8_t re_hw_enable_msi_msix;
930 u_int8_t re_coalesce_tx_pkt;
934 u_int8_t prohibit_access_reg;
936 u_int8_t re_hw_supp_now_is_oob_ver;
938 u_int8_t HwSuppDashVer;
940 bus_space_handle_t re_mapped_cmac_handle; /* bus space tag */
941 bus_space_tag_t re_mapped_cmac_tag; /* bus space tag */
942 bus_space_handle_t re_cmac_handle; /* bus space handle */
943 bus_space_tag_t re_cmac_tag; /* bus space tag */
946 #endif /* !__DragonFly__ */
983 #ifndef __DragonFly__
984 #define RE_LOCK(_sc) mtx_lock(&(_sc)->mtx)
985 #define RE_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx)
986 #define RE_LOCK_INIT(_sc,_name) mtx_init(&(_sc)->mtx,_name,MTX_NETWORK_LOCK,MTX_DEF)
987 #define RE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx)
988 #define RE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->mtx,MA_OWNED)
991 * register space access macros
993 #if OS_VER>VERSION(5,9)
994 #define CSR_WRITE_STREAM_4(sc, reg, val) ((sc->prohibit_access_reg)?:bus_space_write_stream_4(sc->re_btag, sc->re_bhandle, reg, val))
995 #define CSR_WRITE_STREAM_2(sc, reg, val) ((sc->prohibit_access_reg)?:bus_space_write_stream_2(sc->re_btag, sc->re_bhandle, reg, val))
997 #define CSR_WRITE_4(sc, reg, val) ((sc->prohibit_access_reg)?:bus_space_write_4(sc->re_btag, sc->re_bhandle, reg, val))
998 #define CSR_WRITE_2(sc, reg, val) ((sc->prohibit_access_reg)?:bus_space_write_2(sc->re_btag, sc->re_bhandle, reg, val))
999 #define CSR_WRITE_1(sc, reg, val) ((sc->prohibit_access_reg)?:bus_space_write_1(sc->re_btag, sc->re_bhandle, reg, val))
1001 #define CSR_READ_4(sc, reg) ((sc->prohibit_access_reg)?0xFFFFFFFF:bus_space_read_4(sc->re_btag, sc->re_bhandle, reg))
1002 #define CSR_READ_2(sc, reg) ((sc->prohibit_access_reg)?0xFFFF:bus_space_read_2(sc->re_btag, sc->re_bhandle, reg))
1003 #define CSR_READ_1(sc, reg) ((sc->prohibit_access_reg)?0xFF:bus_space_read_1(sc->re_btag, sc->re_bhandle, reg))
1005 /* cmac write/read MMIO register */
1006 #define RE_CMAC_WRITE_1(sc, reg, val) ((sc->prohibit_access_reg)?:bus_space_write_1(sc->re_cmac_tag, sc->re_cmac_handle, reg, val))
1007 #define RE_CMAC_WRITE_2(sc, reg, val) ((sc->prohibit_access_reg)?:bus_space_write_2(sc->re_cmac_tag, sc->re_cmac_handle, reg, val))
1008 #define RE_CMAC_WRITE_4(sc, reg, val) ((sc->prohibit_access_reg)?:bus_space_write_4(sc->re_cmac_tag, sc->re_cmac_handle, reg, val))
1009 #define RE_CMAC_READ_1(sc, reg) ((sc->prohibit_access_reg)?0xFF:bus_space_read_1(sc->re_cmac_tag, sc->re_cmac_handle, reg))
1010 #define RE_CMAC_READ_2(sc, reg) ((sc->prohibit_access_reg)?0xFFFF:bus_space_read_2(sc->re_cmac_tag, sc->re_cmac_handle, reg))
1011 #define RE_CMAC_READ_4(sc, reg) (sc->prohibit_access_reg)?0xFFFFFFFF:bus_space_read_4(sc->re_cmac_tag, sc->re_cmac_handle, reg))
1012 #endif /* !__DragonFly__ */
1014 #define RE_TIMEOUT 1000
1017 * General constants that are fun to know.
1019 * RealTek PCI vendor ID
1021 #define RT_VENDORID 0x10EC
1024 * RealTek chip device IDs.
1026 #define RT_DEVICEID_8129 0x8129
1027 #define RT_DEVICEID_8139 0x8139
1028 #define RT_DEVICEID_8169 0x8169 /* For RTL8169 */
1029 #define RT_DEVICEID_8169SC 0x8167 /* For RTL8169SC */
1030 #define RT_DEVICEID_8168 0x8168 /* For RTL8168B */
1031 #define RT_DEVICEID_8161 0x8161 /* For RTL8168 Series add-on card */
1032 #define RT_DEVICEID_8136 0x8136 /* For RTL8101E */
1035 * Accton PCI vendor ID
1037 #define ACCTON_VENDORID 0x1113
1040 * Accton MPX 5030/5038 device ID.
1042 #define ACCTON_DEVICEID_5030 0x1211
1045 * Delta Electronics Vendor ID.
1047 #define DELTA_VENDORID 0x1500
1052 #define DELTA_DEVICEID_8139 0x1360
1055 * Addtron vendor ID.
1057 #define ADDTRON_VENDORID 0x4033
1060 * Addtron device IDs.
1062 #define ADDTRON_DEVICEID_8139 0x1360
1067 #define DLINK_VENDORID 0x1186
1070 * D-Link DFE-530TX+ device ID
1072 #define DLINK_DEVICEID_530TXPLUS 0x1300
1075 * PCI low memory base and low I/O base register, and
1076 * other PCI registers.
1079 #define RE_PCI_VENDOR_ID 0x00
1080 #define RE_PCI_DEVICE_ID 0x02
1081 #define RE_PCI_COMMAND 0x04
1082 #define RE_PCI_STATUS 0x06
1083 #define RE_PCI_REVISION_ID 0x08 /* 8 bits */
1084 #define RE_PCI_CLASSCODE 0x09
1085 #define RE_PCI_LATENCY_TIMER 0x0D
1086 #define RE_PCI_HEADER_TYPE 0x0E
1087 #define RE_PCI_BIOSROM 0x30
1088 #define RE_PCI_INTLINE 0x3C
1089 #define RE_PCI_INTPIN 0x3D
1090 #define RE_PCI_MINGNT 0x3E
1091 #define RE_PCI_MINLAT 0x0F
1092 #define RE_PCI_RESETOPT 0x48
1093 #define RE_PCI_EEPROM_DATA 0x4C
1095 #define RE_PCI_CAPID 0x50 /* 8 bits */
1096 #define RE_PCI_NEXTPTR 0x51 /* 8 bits */
1097 #define RE_PCI_PWRMGMTCAP 0x52 /* 16 bits */
1098 #define RE_PCI_PWRMGMTCTRL 0x54 /* 16 bits */
1100 #define RE_PSTATE_MASK 0x0003
1101 #define RE_PSTATE_D0 0x0000
1102 #define RE_PSTATE_D1 0x0002
1103 #define RE_PSTATE_D2 0x0002
1104 #define RE_PSTATE_D3 0x0003
1105 #define RE_PME_EN 0x0010
1106 #define RE_PME_STATUS 0x8000
1108 #define RE_WOL_LINK_SPEED_10M_FIRST ( 0 )
1109 #define RE_WOL_LINK_SPEED_100M_FIRST ( 1 )
1112 #define NIC_RAMCODE_VERSION_8168E (0x0057)
1113 #define NIC_RAMCODE_VERSION_8168EVL (0x0055)
1114 #define NIC_RAMCODE_VERSION_8168F (0x0052)
1115 #define NIC_RAMCODE_VERSION_8411 (0x0044)
1116 #define NIC_RAMCODE_VERSION_8168G (0x0042)
1117 #define NIC_RAMCODE_VERSION_8168GU (0x0001)
1118 #define NIC_RAMCODE_VERSION_8168EP (0x0019)
1119 #define NIC_RAMCODE_VERSION_8411B (0x0012)
1120 #define NIC_RAMCODE_VERSION_8168H (0x0018)
1121 #define NIC_RAMCODE_VERSION_8168FP (0x0003)
1125 #define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va)
1135 #define PHYAR_Flag 0x80000000
1136 #define RE_CPlusMode 0x20 /* In Revision ID */
1138 /* interrupt service routine loop time*/
1139 /* the minimum value is 1 */
1140 #define INTR_MAX_LOOP 1
1142 #define RE_REGS_SIZE (256)
1144 #define RTL8168FP_OOBMAC_BASE 0xBAF70000
1145 #define HW_DASH_SUPPORT_DASH(_M) ((_M)->HwSuppDashVer > 0 )
1146 #define HW_DASH_SUPPORT_TYPE_1(_M) ((_M)->HwSuppDashVer == 1 )
1147 #define HW_DASH_SUPPORT_TYPE_2(_M) ((_M)->HwSuppDashVer == 2 )
1148 #define HW_DASH_SUPPORT_TYPE_3(_M) ((_M)->HwSuppDashVer == 3 )
1153 #define DBGPRINT(_unit, _msg) printf ("re%d: %s\n", _unit,_msg)
1154 #define DBGPRINT1(_unit, _msg, _para1) \
1157 sprintf(buf,_msg,_para1); \
1158 printf ("re%d: %s\n", _unit,buf); \
1161 #define DBGPRINT(_unit, _msg)
1162 #define DBGPRINT1(_unit, _msg, _para1)
1165 #ifndef __DragonFly__
1166 #if OS_VER<VERSION(4,9)
1167 #define IFM_1000_T IFM_1000_TX
1168 #elif OS_VER<VERSION(6,0)
1169 #define RE_GET_IFNET(SC) &SC->arpcom.ac_if
1170 #define if_drv_flags if_flags
1171 #define IFF_DRV_RUNNING IFF_RUNNING
1172 #define IFF_DRV_OACTIVE IFF_OACTIVE
1174 #define RE_GET_IFNET(SC) SC->re_ifp
1177 #if OS_VER>=VERSION(10,0)
1178 #define IF_ADDR_LOCK IF_ADDR_WLOCK
1179 #define IF_ADDR_UNLOCK IF_ADDR_WUNLOCK
1182 #if OS_VER>=VERSION(7,4)
1183 #if OS_VER>=VERSION(9,2)
1184 #define RE_PCIEM_LINK_CAP_ASPM PCIEM_LINK_CAP_ASPM
1185 #define RE_PCIER_LINK_CTL PCIER_LINK_CTL
1186 #define RE_PCIER_LINK_CAP PCIER_LINK_CAP
1187 #else //OS_VER>=VERSION(9,2)
1188 #define RE_PCIEM_LINK_CAP_ASPM PCIM_LINK_CAP_ASPM
1189 #define RE_PCIER_LINK_CTL PCIR_EXPRESS_LINK_CTL
1190 #define RE_PCIER_LINK_CAP PCIR_EXPRESS_LINK_CAP
1192 #endif //OS_VER>=VERSION(7,4)
1193 #endif /* !__DragonFly__ */