1 /* $OpenBSD: if_sk.c,v 1.33 2003/08/12 05:23:06 nate Exp $ */
4 * Copyright (c) 1997, 1998, 1999, 2000
5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
34 * $FreeBSD: src/sys/pci/if_sk.c,v 1.19.2.9 2003/03/05 18:42:34 njl Exp $
35 * $DragonFly: src/sys/dev/netif/sk/if_sk.c,v 1.37 2005/09/29 12:52:51 sephe Exp $
39 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
41 * Permission to use, copy, modify, and distribute this software for any
42 * purpose with or without fee is hereby granted, provided that the above
43 * copyright notice and this permission notice appear in all copies.
45 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
46 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
47 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
48 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
49 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
50 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
51 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
55 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports
56 * the SK-984x series adapters, both single port and dual port.
58 * The XaQti XMAC II datasheet,
59 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
60 * The SysKonnect GEnesis manual, http://www.syskonnect.com
62 * Note: XaQti has been aquired by Vitesse, and Vitesse does not have the
63 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a
64 * convenience to others until Vitesse corrects this problem:
66 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
68 * Written by Bill Paul <wpaul@ee.columbia.edu>
69 * Department of Electrical Engineering
70 * Columbia University, New York City
74 * The SysKonnect gigabit ethernet adapters consist of two main
75 * components: the SysKonnect GEnesis controller chip and the XaQti Corp.
76 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC
77 * components and a PHY while the GEnesis controller provides a PCI
78 * interface with DMA support. Each card may have between 512K and
79 * 2MB of SRAM on board depending on the configuration.
81 * The SysKonnect GEnesis controller can have either one or two XMAC
82 * chips connected to it, allowing single or dual port NIC configurations.
83 * SysKonnect has the distinction of being the only vendor on the market
84 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs,
85 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the
86 * XMAC registers. This driver takes advantage of these features to allow
87 * both XMACs to operate as independent interfaces.
90 #include <sys/param.h>
91 #include <sys/systm.h>
92 #include <sys/sockio.h>
94 #include <sys/malloc.h>
95 #include <sys/kernel.h>
96 #include <sys/socket.h>
97 #include <sys/thread2.h>
98 #include <sys/queue.h>
101 #include <net/ifq_var.h>
102 #include <net/if_arp.h>
103 #include <net/ethernet.h>
104 #include <net/if_dl.h>
105 #include <net/if_media.h>
109 #include <vm/vm.h> /* for vtophys */
110 #include <vm/pmap.h> /* for vtophys */
111 #include <machine/bus.h>
112 #include <machine/resource.h>
114 #include <sys/rman.h>
116 #include <dev/netif/mii_layer/mii.h>
117 #include <dev/netif/mii_layer/miivar.h>
118 #include <dev/netif/mii_layer/brgphyreg.h>
120 #include <bus/pci/pcireg.h>
121 #include <bus/pci/pcivar.h>
124 #define SK_USEIOSPACE
127 #include "if_skreg.h"
128 #include "xmaciireg.h"
129 #include "yukonreg.h"
131 /* "controller miibus0" required. See GENERIC if you get errors here. */
132 #include "miibus_if.h"
134 static struct sk_type sk_devs[] = {
135 { VENDORID_SK, DEVICEID_SK_V1,
136 "SysKonnect Gigabit Ethernet (V1.0)" },
137 { VENDORID_SK, DEVICEID_SK_V2,
138 "SysKonnect Gigabit Ethernet (V2.0)" },
139 { VENDORID_MARVELL, DEVICEID_SK_V2,
140 "Marvell Gigabit Ethernet" },
141 { VENDORID_3COM, DEVICEID_3COM_3C940,
142 "3Com 3C940 Gigabit Ethernet" },
143 { VENDORID_LINKSYS, DEVICEID_LINKSYS_EG1032,
144 "Linksys EG1032 Gigabit Ethernet" },
145 { VENDORID_DLINK, DEVICEID_DLINK_DGE530T,
146 "D-Link DGE-530T Gigabit Ethernet" },
150 static int skc_probe(device_t);
151 static int skc_attach(device_t);
152 static int skc_detach(device_t);
153 static void skc_shutdown(device_t);
154 static int sk_probe(device_t);
155 static int sk_attach(device_t);
156 static int sk_detach(device_t);
157 static void sk_tick(void *);
158 static void sk_intr(void *);
159 static void sk_intr_bcom(struct sk_if_softc *);
160 static void sk_intr_xmac(struct sk_if_softc *);
161 static void sk_intr_yukon(struct sk_if_softc *);
162 static void sk_rxeof(struct sk_if_softc *);
163 static void sk_txeof(struct sk_if_softc *);
164 static int sk_encap(struct sk_if_softc *, struct mbuf *, uint32_t *);
165 static void sk_start(struct ifnet *);
166 static int sk_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
167 static void sk_init(void *);
168 static void sk_init_xmac(struct sk_if_softc *);
169 static void sk_init_yukon(struct sk_if_softc *);
170 static void sk_stop(struct sk_if_softc *);
171 static void sk_watchdog(struct ifnet *);
172 static int sk_ifmedia_upd(struct ifnet *);
173 static void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *);
174 static void sk_reset(struct sk_softc *);
175 static int sk_newbuf(struct sk_if_softc *, struct sk_chain *,
177 static int sk_alloc_jumbo_mem(struct sk_if_softc *);
178 static struct sk_jslot
179 *sk_jalloc(struct sk_if_softc *);
180 static void sk_jfree(void *);
181 static void sk_jref(void *);
182 static int sk_init_rx_ring(struct sk_if_softc *);
183 static void sk_init_tx_ring(struct sk_if_softc *);
184 static uint32_t sk_win_read_4(struct sk_softc *, int);
185 static uint16_t sk_win_read_2(struct sk_softc *, int);
186 static uint8_t sk_win_read_1(struct sk_softc *, int);
187 static void sk_win_write_4(struct sk_softc *, int, uint32_t);
188 static void sk_win_write_2(struct sk_softc *, int, uint32_t);
189 static void sk_win_write_1(struct sk_softc *, int, uint32_t);
190 static uint8_t sk_vpd_readbyte(struct sk_softc *, int);
191 static void sk_vpd_read_res(struct sk_softc *, struct vpd_res *, int);
192 static void sk_vpd_read(struct sk_softc *);
194 static int sk_miibus_readreg(device_t, int, int);
195 static int sk_miibus_writereg(device_t, int, int, int);
196 static void sk_miibus_statchg(device_t);
198 static int sk_xmac_miibus_readreg(struct sk_if_softc *, int, int);
199 static int sk_xmac_miibus_writereg(struct sk_if_softc *, int, int, int);
200 static void sk_xmac_miibus_statchg(struct sk_if_softc *);
202 static int sk_marv_miibus_readreg(struct sk_if_softc *, int, int);
203 static int sk_marv_miibus_writereg(struct sk_if_softc *, int, int, int);
204 static void sk_marv_miibus_statchg(struct sk_if_softc *);
206 static void sk_setfilt(struct sk_if_softc *, caddr_t, int);
207 static void sk_setmulti(struct sk_if_softc *);
208 static void sk_setpromisc(struct sk_if_softc *);
211 #define SK_RES SYS_RES_IOPORT
212 #define SK_RID SK_PCI_LOIO
214 #define SK_RES SYS_RES_MEMORY
215 #define SK_RID SK_PCI_LOMEM
219 * Note that we have newbus methods for both the GEnesis controller
220 * itself and the XMAC(s). The XMACs are children of the GEnesis, and
221 * the miibus code is a child of the XMACs. We need to do it this way
222 * so that the miibus drivers can access the PHY registers on the
223 * right PHY. It's not quite what I had in mind, but it's the only
224 * design that achieves the desired effect.
226 static device_method_t skc_methods[] = {
227 /* Device interface */
228 DEVMETHOD(device_probe, skc_probe),
229 DEVMETHOD(device_attach, skc_attach),
230 DEVMETHOD(device_detach, skc_detach),
231 DEVMETHOD(device_shutdown, skc_shutdown),
234 DEVMETHOD(bus_print_child, bus_generic_print_child),
235 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
240 static DEFINE_CLASS_0(skc, skc_driver, skc_methods, sizeof(struct sk_softc));
241 static devclass_t skc_devclass;
243 static device_method_t sk_methods[] = {
244 /* Device interface */
245 DEVMETHOD(device_probe, sk_probe),
246 DEVMETHOD(device_attach, sk_attach),
247 DEVMETHOD(device_detach, sk_detach),
248 DEVMETHOD(device_shutdown, bus_generic_shutdown),
251 DEVMETHOD(bus_print_child, bus_generic_print_child),
252 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
255 DEVMETHOD(miibus_readreg, sk_miibus_readreg),
256 DEVMETHOD(miibus_writereg, sk_miibus_writereg),
257 DEVMETHOD(miibus_statchg, sk_miibus_statchg),
262 static DEFINE_CLASS_0(sk, sk_driver, sk_methods, sizeof(struct sk_if_softc));
263 static devclass_t sk_devclass;
265 DECLARE_DUMMY_MODULE(if_sk);
266 DRIVER_MODULE(if_sk, pci, skc_driver, skc_devclass, 0, 0);
267 DRIVER_MODULE(if_sk, skc, sk_driver, sk_devclass, 0, 0);
268 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, 0, 0);
270 #define SK_SETBIT(sc, reg, x) \
271 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
273 #define SK_CLRBIT(sc, reg, x) \
274 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
276 #define SK_WIN_SETBIT_4(sc, reg, x) \
277 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x)
279 #define SK_WIN_CLRBIT_4(sc, reg, x) \
280 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x)
282 #define SK_WIN_SETBIT_2(sc, reg, x) \
283 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x)
285 #define SK_WIN_CLRBIT_2(sc, reg, x) \
286 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x)
289 sk_win_read_4(struct sk_softc *sc, int reg)
292 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
293 return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)));
295 return(CSR_READ_4(sc, reg));
300 sk_win_read_2(struct sk_softc *sc, int reg)
303 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
304 return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)));
306 return(CSR_READ_2(sc, reg));
311 sk_win_read_1(struct sk_softc *sc, int reg)
314 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
315 return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)));
317 return(CSR_READ_1(sc, reg));
322 sk_win_write_4(struct sk_softc *sc, int reg, uint32_t val)
325 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
326 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val);
328 CSR_WRITE_4(sc, reg, val);
333 sk_win_write_2(struct sk_softc *sc, int reg, uint32_t val)
336 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
337 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val);
339 CSR_WRITE_2(sc, reg, val);
344 sk_win_write_1(struct sk_softc *sc, int reg, uint32_t val)
347 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
348 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val);
350 CSR_WRITE_1(sc, reg, val);
355 * The VPD EEPROM contains Vital Product Data, as suggested in
356 * the PCI 2.1 specification. The VPD data is separared into areas
357 * denoted by resource IDs. The SysKonnect VPD contains an ID string
358 * resource (the name of the adapter), a read-only area resource
359 * containing various key/data fields and a read/write area which
360 * can be used to store asset management information or log messages.
361 * We read the ID string and read-only into buffers attached to
362 * the controller softc structure for later use. At the moment,
363 * we only use the ID string during sk_attach().
366 sk_vpd_readbyte(struct sk_softc *sc, int addr)
370 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr);
371 for (i = 0; i < SK_TIMEOUT; i++) {
373 if (sk_win_read_2(sc,
374 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG)
381 return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA)));
385 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr)
390 ptr = (uint8_t *)res;
391 for (i = 0; i < sizeof(struct vpd_res); i++)
392 ptr[i] = sk_vpd_readbyte(sc, i + addr);
396 sk_vpd_read(struct sk_softc *sc)
401 if (sc->sk_vpd_prodname != NULL)
402 free(sc->sk_vpd_prodname, M_DEVBUF);
403 if (sc->sk_vpd_readonly != NULL)
404 free(sc->sk_vpd_readonly, M_DEVBUF);
405 sc->sk_vpd_prodname = NULL;
406 sc->sk_vpd_readonly = NULL;
408 sk_vpd_read_res(sc, &res, pos);
410 if (res.vr_id != VPD_RES_ID) {
411 printf("skc%d: bad VPD resource id: expected %x got %x\n",
412 sc->sk_unit, VPD_RES_ID, res.vr_id);
417 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_INTWAIT);
418 for (i = 0; i < res.vr_len; i++)
419 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos);
420 sc->sk_vpd_prodname[i] = '\0';
423 sk_vpd_read_res(sc, &res, pos);
425 if (res.vr_id != VPD_RES_READ) {
426 printf("skc%d: bad VPD resource id: expected %x got %x\n",
427 sc->sk_unit, VPD_RES_READ, res.vr_id);
432 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_INTWAIT);
433 for (i = 0; i < res.vr_len + 1; i++)
434 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos);
438 sk_miibus_readreg(device_t dev, int phy, int reg)
440 struct sk_if_softc *sc_if = device_get_softc(dev);
442 switch(sc_if->sk_softc->sk_type) {
444 return(sk_xmac_miibus_readreg(sc_if, phy, reg));
446 return(sk_marv_miibus_readreg(sc_if, phy, reg));
453 sk_miibus_writereg(device_t dev, int phy, int reg, int val)
455 struct sk_if_softc *sc_if = device_get_softc(dev);
457 switch(sc_if->sk_softc->sk_type) {
459 return(sk_xmac_miibus_writereg(sc_if, phy, reg, val));
461 return(sk_marv_miibus_writereg(sc_if, phy, reg, val));
468 sk_miibus_statchg(device_t dev)
470 struct sk_if_softc *sc_if = device_get_softc(dev);
472 switch(sc_if->sk_softc->sk_type) {
474 sk_xmac_miibus_statchg(sc_if);
477 sk_marv_miibus_statchg(sc_if);
483 sk_xmac_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg)
487 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0)
490 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
491 SK_XM_READ_2(sc_if, XM_PHY_DATA);
492 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
493 for (i = 0; i < SK_TIMEOUT; i++) {
495 if (SK_XM_READ_2(sc_if, XM_MMUCMD) &
496 XM_MMUCMD_PHYDATARDY)
500 if (i == SK_TIMEOUT) {
501 printf("sk%d: phy failed to come ready\n",
507 return(SK_XM_READ_2(sc_if, XM_PHY_DATA));
511 sk_xmac_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val)
515 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
516 for (i = 0; i < SK_TIMEOUT; i++) {
517 if ((SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY) == 0)
521 if (i == SK_TIMEOUT) {
522 printf("sk%d: phy failed to come ready\n", sc_if->sk_unit);
526 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val);
527 for (i = 0; i < SK_TIMEOUT; i++) {
529 if ((SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY) == 0)
534 printf("sk%d: phy write timed out\n", sc_if->sk_unit);
540 sk_xmac_miibus_statchg(struct sk_if_softc *sc_if)
542 struct mii_data *mii;
544 mii = device_get_softc(sc_if->sk_miibus);
547 * If this is a GMII PHY, manually set the XMAC's
548 * duplex mode accordingly.
550 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
551 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
552 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
554 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
559 sk_marv_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg)
565 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER &&
566 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) {
570 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
571 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ);
573 for (i = 0; i < SK_TIMEOUT; i++) {
575 val = SK_YU_READ_2(sc_if, YUKON_SMICR);
576 if (val & YU_SMICR_READ_VALID)
580 if (i == SK_TIMEOUT) {
581 printf("sk%d: phy failed to come ready\n",
586 val = SK_YU_READ_2(sc_if, YUKON_SMIDR);
592 sk_marv_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val)
596 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val);
597 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
598 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE);
600 for (i = 0; i < SK_TIMEOUT; i++) {
602 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)
610 sk_marv_miibus_statchg(struct sk_if_softc *sc_if)
616 static void sk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot)
620 base = XM_RXFILT_ENTRY(slot);
622 SK_XM_WRITE_2(sc_if, base, *(uint16_t *)(&addr[0]));
623 SK_XM_WRITE_2(sc_if, base + 2, *(uint16_t *)(&addr[2]));
624 SK_XM_WRITE_2(sc_if, base + 4, *(uint16_t *)(&addr[4]));
628 sk_setmulti(struct sk_if_softc *sc_if)
630 struct sk_softc *sc = sc_if->sk_softc;
631 struct ifnet *ifp = &sc_if->arpcom.ac_if;
632 uint32_t hashes[2] = { 0, 0 };
634 struct ifmultiaddr *ifma;
635 uint8_t dummy[] = { 0, 0, 0, 0, 0 ,0 };
637 /* First, zot all the existing filters. */
638 switch(sc->sk_type) {
640 for (i = 1; i < XM_RXFILT_MAX; i++)
641 sk_setfilt(sc_if, (caddr_t)&dummy, i);
643 SK_XM_WRITE_4(sc_if, XM_MAR0, 0);
644 SK_XM_WRITE_4(sc_if, XM_MAR2, 0);
647 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0);
648 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0);
649 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0);
650 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0);
654 /* Now program new ones. */
655 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
656 hashes[0] = 0xFFFFFFFF;
657 hashes[1] = 0xFFFFFFFF;
660 /* First find the tail of the list. */
661 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
662 if (ifma->ifma_link.le_next == NULL)
665 /* Now traverse the list backwards. */
666 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs;
667 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) {
668 if (ifma->ifma_addr->sa_family != AF_LINK)
671 * Program the first XM_RXFILT_MAX multicast groups
672 * into the perfect filter. For all others,
673 * use the hash table.
675 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) {
677 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i);
682 switch(sc->sk_type) {
684 h = ~ether_crc32_le(LLADDR((struct sockaddr_dl *)
685 ifma->ifma_addr), ETHER_ADDR_LEN) &
686 ((1 << HASH_BITS) -1 );
688 hashes[0] |= (1 << h);
690 hashes[1] |= (1 << (h - 32));
694 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
695 ifma->ifma_addr), ETHER_ADDR_LEN) &
696 ((1 << HASH_BITS) -1 );
698 hashes[0] |= (1 << h);
700 hashes[1] |= (1 << (h - 32));
706 switch(sc->sk_type) {
708 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH|
709 XM_MODE_RX_USE_PERFECT);
710 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]);
711 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]);
714 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff);
715 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff);
716 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff);
717 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff);
723 sk_setpromisc(struct sk_if_softc *sc_if)
725 struct sk_softc *sc = sc_if->sk_softc;
726 struct ifnet *ifp = &sc_if->arpcom.ac_if;
728 switch(sc->sk_type) {
730 if (ifp->if_flags & IFF_PROMISC) {
731 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
733 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
737 if (ifp->if_flags & IFF_PROMISC) {
738 SK_YU_CLRBIT_2(sc_if, YUKON_RCR,
739 YU_RCR_UFLEN | YU_RCR_MUFLEN);
741 SK_YU_SETBIT_2(sc_if, YUKON_RCR,
742 YU_RCR_UFLEN | YU_RCR_MUFLEN);
749 sk_init_rx_ring(struct sk_if_softc *sc_if)
751 struct sk_chain_data *cd = &sc_if->sk_cdata;
752 struct sk_ring_data *rd = sc_if->sk_rdata;
755 bzero(rd->sk_rx_ring, sizeof(struct sk_rx_desc) * SK_RX_RING_CNT);
757 for (i = 0; i < SK_RX_RING_CNT; i++) {
758 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i];
759 if (sk_newbuf(sc_if, &cd->sk_rx_chain[i], NULL) == ENOBUFS)
761 if (i == (SK_RX_RING_CNT - 1)) {
762 cd->sk_rx_chain[i].sk_next =
764 rd->sk_rx_ring[i].sk_next =
765 vtophys(&rd->sk_rx_ring[0]);
767 cd->sk_rx_chain[i].sk_next =
768 &cd->sk_rx_chain[i + 1];
769 rd->sk_rx_ring[i].sk_next =
770 vtophys(&rd->sk_rx_ring[i + 1]);
774 sc_if->sk_cdata.sk_rx_prod = 0;
775 sc_if->sk_cdata.sk_rx_cons = 0;
781 sk_init_tx_ring(struct sk_if_softc *sc_if)
783 struct sk_chain_data *cd = &sc_if->sk_cdata;
784 struct sk_ring_data *rd = sc_if->sk_rdata;
787 bzero(sc_if->sk_rdata->sk_tx_ring,
788 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT);
790 for (i = 0; i < SK_TX_RING_CNT; i++) {
791 nexti = (i == (SK_TX_RING_CNT - 1)) ? 0 : i + 1;
792 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i];
793 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti];
794 rd->sk_tx_ring[i].sk_next = vtophys(&rd->sk_tx_ring[nexti]);
797 sc_if->sk_cdata.sk_tx_prod = 0;
798 sc_if->sk_cdata.sk_tx_cons = 0;
799 sc_if->sk_cdata.sk_tx_cnt = 0;
803 sk_newbuf(struct sk_if_softc *sc_if, struct sk_chain *c, struct mbuf *m)
805 struct mbuf *m_new = NULL;
806 struct sk_rx_desc *r;
807 struct sk_jslot *buf;
810 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
814 /* Allocate the jumbo buffer */
815 buf = sk_jalloc(sc_if);
819 printf("sk%d: jumbo allocation failed "
820 "-- packet dropped!\n", sc_if->sk_unit);
825 /* Attach the buffer to the mbuf */
826 m_new->m_ext.ext_arg = buf;
827 m_new->m_ext.ext_buf = buf->sk_buf;
828 m_new->m_ext.ext_free = sk_jfree;
829 m_new->m_ext.ext_ref = sk_jref;
830 m_new->m_ext.ext_size = SK_JUMBO_FRAMELEN;
832 m_new->m_data = m_new->m_ext.ext_buf;
833 m_new->m_flags |= M_EXT;
834 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
837 * We're re-using a previously allocated mbuf;
838 * be sure to re-init pointers and lengths to
842 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN;
843 m_new->m_data = m_new->m_ext.ext_buf;
847 * Adjust alignment so packet payload begins on a
848 * longword boundary. Mandatory for Alpha, useful on
851 m_adj(m_new, ETHER_ALIGN);
855 r->sk_data_lo = vtophys(mtod(m_new, caddr_t));
856 r->sk_ctl = m_new->m_len | SK_RXSTAT;
862 * Allocate jumbo buffer storage. The SysKonnect adapters support
863 * "jumbograms" (9K frames), although SysKonnect doesn't currently
864 * use them in their drivers. In order for us to use them, we need
865 * large 9K receive buffers, however standard mbuf clusters are only
866 * 2048 bytes in size. Consequently, we need to allocate and manage
867 * our own jumbo buffer pool. Fortunately, this does not require an
868 * excessive amount of additional code.
871 sk_alloc_jumbo_mem(struct sk_if_softc *sc_if)
875 struct sk_jslot *entry;
877 /* Grab a big chunk o' storage. */
878 sc_if->sk_cdata.sk_jumbo_buf = contigmalloc(SK_JMEM, M_DEVBUF,
879 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
881 if (sc_if->sk_cdata.sk_jumbo_buf == NULL) {
882 printf("sk%d: no memory for jumbo buffers!\n", sc_if->sk_unit);
886 SLIST_INIT(&sc_if->sk_jfree_listhead);
889 * Now divide it up into 9K pieces and save the addresses
890 * in an array. Note that we play an evil trick here by using
891 * the first few bytes in the buffer to hold the the address
892 * of the softc structure for this interface. This is because
893 * sk_jfree() needs it, but it is called by the mbuf management
894 * code which will not pass it to us explicitly.
896 ptr = sc_if->sk_cdata.sk_jumbo_buf;
897 for (i = 0; i < SK_JSLOTS; i++) {
898 entry = &sc_if->sk_cdata.sk_jslots[i];
899 entry->sk_sc = sc_if;
903 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead, entry, jslot_link);
911 * Allocate a jumbo buffer.
913 static struct sk_jslot *
914 sk_jalloc(struct sk_if_softc *sc_if)
916 struct sk_jslot *entry;
918 entry = SLIST_FIRST(&sc_if->sk_jfree_listhead);
922 printf("sk%d: no free jumbo buffers\n", sc_if->sk_unit);
927 SLIST_REMOVE_HEAD(&sc_if->sk_jfree_listhead, jslot_link);
934 * Adjust usage count on a jumbo buffer. In general this doesn't
935 * get used much because our jumbo buffers don't get passed around
936 * a lot, but it's implemented for correctness.
941 struct sk_jslot *entry = (struct sk_jslot *)arg;
942 struct sk_if_softc *sc = entry->sk_sc;
945 panic("sk_jref: can't find softc pointer!");
947 if (&sc->sk_cdata.sk_jslots[entry->sk_slot] != entry)
948 panic("sk_jref: asked to reference buffer "
949 "that we don't manage!");
950 if (entry->sk_inuse == 0)
951 panic("sk_jref: buffer already free!");
956 * Release a jumbo buffer.
961 struct sk_jslot *entry = (struct sk_jslot *)arg;
962 struct sk_if_softc *sc = entry->sk_sc;
965 panic("sk_jref: can't find softc pointer!");
967 if (&sc->sk_cdata.sk_jslots[entry->sk_slot] != entry)
968 panic("sk_jref: asked to reference buffer "
969 "that we don't manage!");
970 if (entry->sk_inuse == 0)
971 panic("sk_jref: buffer already free!");
972 if (--entry->sk_inuse == 0)
973 SLIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jslot_link);
980 sk_ifmedia_upd(struct ifnet *ifp)
982 struct sk_if_softc *sc_if = ifp->if_softc;
983 struct mii_data *mii;
985 mii = device_get_softc(sc_if->sk_miibus);
993 * Report current media status.
996 sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
998 struct sk_if_softc *sc_if;
999 struct mii_data *mii;
1001 sc_if = ifp->if_softc;
1002 mii = device_get_softc(sc_if->sk_miibus);
1005 ifmr->ifm_active = mii->mii_media_active;
1006 ifmr->ifm_status = mii->mii_media_status;
1010 sk_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1012 struct sk_if_softc *sc_if = ifp->if_softc;
1013 struct ifreq *ifr = (struct ifreq *)data;
1014 struct mii_data *mii;
1021 if (ifr->ifr_mtu > SK_JUMBO_MTU)
1024 ifp->if_mtu = ifr->ifr_mtu;
1029 if (ifp->if_flags & IFF_UP) {
1030 if (ifp->if_flags & IFF_RUNNING) {
1031 if ((ifp->if_flags ^ sc_if->sk_if_flags)
1033 sk_setpromisc(sc_if);
1039 if (ifp->if_flags & IFF_RUNNING)
1042 sc_if->sk_if_flags = ifp->if_flags;
1052 mii = device_get_softc(sc_if->sk_miibus);
1053 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1056 error = ether_ioctl(ifp, command, data);
1066 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device
1067 * IDs against our list and return a device name if we find a match.
1070 skc_probe(device_t dev)
1073 uint16_t vendor, product;
1075 vendor = pci_get_vendor(dev);
1076 product = pci_get_device(dev);
1078 for (t = sk_devs; t->sk_name != NULL; t++) {
1079 if (vendor == t->sk_vid && product == t->sk_did) {
1080 device_set_desc(dev, t->sk_name);
1089 * Force the GEnesis into reset, then bring it out of reset.
1092 sk_reset(struct sk_softc *sc)
1094 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET);
1095 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET);
1096 if (sc->sk_type == SK_YUKON)
1097 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET);
1100 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET);
1102 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET);
1103 if (sc->sk_type == SK_YUKON)
1104 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR);
1106 if (sc->sk_type == SK_GENESIS) {
1107 /* Configure packet arbiter */
1108 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET);
1109 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT);
1110 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT);
1111 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT);
1112 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT);
1115 /* Enable RAM interface */
1116 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET);
1119 * Configure interrupt moderation. The moderation timer
1120 * defers interrupts specified in the interrupt moderation
1121 * timer mask based on the timeout specified in the interrupt
1122 * moderation timer init register. Each bit in the timer
1123 * register represents 18.825ns, so to specify a timeout in
1124 * microseconds, we have to multiply by 54.
1126 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(200));
1127 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF|
1128 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF);
1129 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START);
1133 sk_probe(device_t dev)
1135 struct sk_softc *sc = device_get_softc(device_get_parent(dev));
1138 * Not much to do here. We always know there will be
1139 * at least one XMAC present, and if there are two,
1140 * skc_attach() will create a second device instance
1143 switch (sc->sk_type) {
1145 device_set_desc(dev, "XaQti Corp. XMAC II");
1148 device_set_desc(dev, "Marvell Semiconductor, Inc. Yukon");
1156 * Each XMAC chip is attached as a separate logical IP interface.
1157 * Single port cards will have only one logical interface of course.
1160 sk_attach(device_t dev)
1162 struct sk_softc *sc = device_get_softc(device_get_parent(dev));
1163 struct sk_if_softc *sc_if = device_get_softc(dev);
1167 port = *(int *)device_get_ivars(dev);
1168 free(device_get_ivars(dev), M_DEVBUF);
1169 device_set_ivars(dev, NULL);
1170 sc_if->sk_dev = dev;
1171 callout_init(&sc_if->sk_tick_timer);
1173 sc_if->sk_dev = dev;
1174 sc_if->sk_unit = device_get_unit(dev);
1175 sc_if->sk_port = port;
1176 sc_if->sk_softc = sc;
1177 sc->sk_if[port] = sc_if;
1178 if (port == SK_PORT_A)
1179 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0;
1180 if (port == SK_PORT_B)
1181 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1;
1184 * Get station address for this interface. Note that
1185 * dual port cards actually come with three station
1186 * addresses: one for each port, plus an extra. The
1187 * extra one is used by the SysKonnect driver software
1188 * as a 'virtual' station address for when both ports
1189 * are operating in failover mode. Currently we don't
1190 * use this extra address.
1192 for (i = 0; i < ETHER_ADDR_LEN; i++)
1193 sc_if->arpcom.ac_enaddr[i] =
1194 sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i);
1197 * Set up RAM buffer addresses. The NIC will have a certain
1198 * amount of SRAM on it, somewhere between 512K and 2MB. We
1199 * need to divide this up a) between the transmitter and
1200 * receiver and b) between the two XMACs, if this is a
1201 * dual port NIC. Our algotithm is to divide up the memory
1202 * evenly so that everyone gets a fair share.
1204 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) {
1205 uint32_t chunk, val;
1207 chunk = sc->sk_ramsize / 2;
1208 val = sc->sk_rboff / sizeof(uint64_t);
1209 sc_if->sk_rx_ramstart = val;
1210 val += (chunk / sizeof(uint64_t));
1211 sc_if->sk_rx_ramend = val - 1;
1212 sc_if->sk_tx_ramstart = val;
1213 val += (chunk / sizeof(uint64_t));
1214 sc_if->sk_tx_ramend = val - 1;
1216 uint32_t chunk, val;
1218 chunk = sc->sk_ramsize / 4;
1219 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) /
1221 sc_if->sk_rx_ramstart = val;
1222 val += (chunk / sizeof(uint64_t));
1223 sc_if->sk_rx_ramend = val - 1;
1224 sc_if->sk_tx_ramstart = val;
1225 val += (chunk / sizeof(uint64_t));
1226 sc_if->sk_tx_ramend = val - 1;
1229 /* Read and save PHY type and set PHY address */
1230 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF;
1231 switch(sc_if->sk_phytype) {
1232 case SK_PHYTYPE_XMAC:
1233 sc_if->sk_phyaddr = SK_PHYADDR_XMAC;
1235 case SK_PHYTYPE_BCOM:
1236 sc_if->sk_phyaddr = SK_PHYADDR_BCOM;
1238 case SK_PHYTYPE_MARV_COPPER:
1239 sc_if->sk_phyaddr = SK_PHYADDR_MARV;
1242 printf("skc%d: unsupported PHY type: %d\n",
1243 sc->sk_unit, sc_if->sk_phytype);
1247 /* Allocate the descriptor queues. */
1248 sc_if->sk_rdata = contigmalloc(sizeof(struct sk_ring_data), M_DEVBUF,
1249 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1251 if (sc_if->sk_rdata == NULL) {
1252 printf("sk%d: no memory for list buffers!\n", sc_if->sk_unit);
1253 sc->sk_if[port] = NULL;
1257 bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data));
1259 /* Try to allocate memory for jumbo buffers. */
1260 if (sk_alloc_jumbo_mem(sc_if)) {
1261 printf("sk%d: jumbo buffer allocation failed\n",
1263 contigfree(sc_if->sk_rdata,
1264 sizeof(struct sk_ring_data), M_DEVBUF);
1265 sc->sk_if[port] = NULL;
1269 ifp = &sc_if->arpcom.ac_if;
1270 ifp->if_softc = sc_if;
1271 if_initname(ifp, "sk", sc_if->sk_unit);
1272 ifp->if_mtu = ETHERMTU;
1273 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1274 ifp->if_ioctl = sk_ioctl;
1275 ifp->if_start = sk_start;
1276 ifp->if_watchdog = sk_watchdog;
1277 ifp->if_init = sk_init;
1278 ifp->if_baudrate = 1000000000;
1279 ifq_set_maxlen(&ifp->if_snd, SK_TX_RING_CNT - 1);
1280 ifq_set_ready(&ifp->if_snd);
1285 switch (sc->sk_type) {
1287 sk_init_xmac(sc_if);
1290 sk_init_yukon(sc_if);
1294 if (mii_phy_probe(dev, &sc_if->sk_miibus,
1295 sk_ifmedia_upd, sk_ifmedia_sts)) {
1296 printf("skc%d: no PHY found!\n", sc_if->sk_unit);
1297 contigfree(sc_if->sk_cdata.sk_jumbo_buf, SK_JMEM,
1299 contigfree(sc_if->sk_rdata,
1300 sizeof(struct sk_ring_data), M_DEVBUF);
1305 * Call MI attach routine.
1307 ether_ifattach(ifp, sc_if->arpcom.ac_enaddr);
1308 callout_init(&sc_if->sk_tick_timer);
1314 * Attach the interface. Allocate softc structures, do ifmedia
1315 * setup and ethernet/BPF attach.
1318 skc_attach(device_t dev)
1320 struct sk_softc *sc;
1321 int error = 0, *port, rid, unit;
1327 sc = device_get_softc(dev);
1328 unit = device_get_unit(dev);
1329 switch (pci_get_device(dev)) {
1330 case DEVICEID_SK_V1:
1331 sc->sk_type = SK_GENESIS;
1333 case DEVICEID_SK_V2:
1334 case DEVICEID_3COM_3C940:
1335 case DEVICEID_LINKSYS_EG1032:
1336 case DEVICEID_DLINK_DGE530T:
1337 sc->sk_type = SK_YUKON;
1342 * Handle power management nonsense.
1344 command = pci_read_config(dev, SK_PCI_CAPID, 4) & 0x000000FF;
1345 if (command == 0x01) {
1346 command = pci_read_config(dev, SK_PCI_PWRMGMTCTRL, 4);
1347 if (command & SK_PSTATE_MASK) {
1348 uint32_t iobase, membase, irq;
1350 /* Save important PCI config data. */
1351 iobase = pci_read_config(dev, SK_PCI_LOIO, 4);
1352 membase = pci_read_config(dev, SK_PCI_LOMEM, 4);
1353 irq = pci_read_config(dev, SK_PCI_INTLINE, 4);
1355 /* Reset the power state. */
1356 printf("skc%d: chip is in D%d power mode "
1357 "-- setting to D0\n", unit, command & SK_PSTATE_MASK);
1358 command &= 0xFFFFFFFC;
1359 pci_write_config(dev, SK_PCI_PWRMGMTCTRL, command, 4);
1361 /* Restore PCI config data. */
1362 pci_write_config(dev, SK_PCI_LOIO, iobase, 4);
1363 pci_write_config(dev, SK_PCI_LOMEM, membase, 4);
1364 pci_write_config(dev, SK_PCI_INTLINE, irq, 4);
1369 * Map control/status registers.
1371 command = pci_read_config(dev, PCIR_COMMAND, 4);
1372 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1373 pci_write_config(dev, PCIR_COMMAND, command, 4);
1374 command = pci_read_config(dev, PCIR_COMMAND, 4);
1376 #ifdef SK_USEIOSPACE
1377 if ((command & PCIM_CMD_PORTEN) == 0) {
1378 printf("skc%d: failed to enable I/O ports!\n", unit);
1383 if ((command & PCIM_CMD_MEMEN) == 0) {
1384 printf("skc%d: failed to enable memory mapping!\n", unit);
1391 sc->sk_res = bus_alloc_resource_any(dev, SK_RES, &rid, RF_ACTIVE);
1393 if (sc->sk_res == NULL) {
1394 printf("sk%d: couldn't map ports/memory\n", unit);
1399 sc->sk_btag = rman_get_bustag(sc->sk_res);
1400 sc->sk_bhandle = rman_get_bushandle(sc->sk_res);
1402 /* Allocate interrupt */
1404 sc->sk_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1405 RF_SHAREABLE | RF_ACTIVE);
1407 if (sc->sk_irq == NULL) {
1408 printf("skc%d: couldn't map interrupt\n", unit);
1409 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1414 error = bus_setup_intr(dev, sc->sk_irq, INTR_TYPE_NET,
1416 &sc->sk_intrhand, NULL);
1419 printf("skc%d: couldn't set up irq\n", unit);
1420 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1421 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq);
1425 /* Reset the adapter. */
1430 /* Read and save vital product data from EEPROM. */
1433 skrs = sk_win_read_1(sc, SK_EPROM0);
1434 if (sc->sk_type == SK_GENESIS) {
1435 /* Read and save RAM size and RAMbuffer offset */
1437 case SK_RAMSIZE_512K_64:
1438 sc->sk_ramsize = 0x80000;
1439 sc->sk_rboff = SK_RBOFF_0;
1441 case SK_RAMSIZE_1024K_64:
1442 sc->sk_ramsize = 0x100000;
1443 sc->sk_rboff = SK_RBOFF_80000;
1445 case SK_RAMSIZE_1024K_128:
1446 sc->sk_ramsize = 0x100000;
1447 sc->sk_rboff = SK_RBOFF_0;
1449 case SK_RAMSIZE_2048K_128:
1450 sc->sk_ramsize = 0x200000;
1451 sc->sk_rboff = SK_RBOFF_0;
1454 printf("skc%d: unknown ram size: %d\n",
1455 sc->sk_unit, sk_win_read_1(sc, SK_EPROM0));
1456 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand);
1457 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq);
1458 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1463 } else { /* SK_YUKON */
1465 sc->sk_ramsize = 0x20000;
1467 sc->sk_ramsize = skrs * (1<<12);
1469 sc->sk_rboff = SK_RBOFF_0;
1472 /* Read and save physical media type */
1473 switch(sk_win_read_1(sc, SK_PMDTYPE)) {
1474 case SK_PMD_1000BASESX:
1475 sc->sk_pmd = IFM_1000_SX;
1477 case SK_PMD_1000BASELX:
1478 sc->sk_pmd = IFM_1000_LX;
1480 case SK_PMD_1000BASECX:
1481 sc->sk_pmd = IFM_1000_CX;
1483 case SK_PMD_1000BASETX:
1484 sc->sk_pmd = IFM_1000_T;
1487 printf("skc%d: unknown media type: 0x%x\n",
1488 sc->sk_unit, sk_win_read_1(sc, SK_PMDTYPE));
1489 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand);
1490 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq);
1491 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1496 /* Announce the product name. */
1497 printf("skc%d: %s\n", sc->sk_unit, sc->sk_vpd_prodname);
1498 sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1);
1499 port = malloc(sizeof(int), M_DEVBUF, M_WAITOK);
1501 device_set_ivars(sc->sk_devs[SK_PORT_A], port);
1503 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) {
1504 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1);
1505 port = malloc(sizeof(int), M_DEVBUF, M_WAITOK);
1507 device_set_ivars(sc->sk_devs[SK_PORT_B], port);
1510 /* Turn on the 'driver is loaded' LED. */
1511 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
1513 bus_generic_attach(dev);
1521 sk_detach(device_t dev)
1523 struct sk_if_softc *sc_if = device_get_softc(dev);
1524 struct ifnet *ifp = &sc_if->arpcom.ac_if;
1529 ether_ifdetach(ifp);
1530 bus_generic_detach(dev);
1531 if (sc_if->sk_miibus != NULL)
1532 device_delete_child(dev, sc_if->sk_miibus);
1533 contigfree(sc_if->sk_cdata.sk_jumbo_buf, SK_JMEM, M_DEVBUF);
1534 contigfree(sc_if->sk_rdata, sizeof(struct sk_ring_data), M_DEVBUF);
1542 skc_detach(device_t dev)
1544 struct sk_softc *sc;
1548 sc = device_get_softc(dev);
1550 bus_generic_detach(dev);
1551 if (sc->sk_devs[SK_PORT_A] != NULL)
1552 device_delete_child(dev, sc->sk_devs[SK_PORT_A]);
1553 if (sc->sk_devs[SK_PORT_B] != NULL)
1554 device_delete_child(dev, sc->sk_devs[SK_PORT_B]);
1556 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand);
1557 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq);
1558 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1566 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, uint32_t *txidx)
1568 struct sk_tx_desc *f = NULL;
1570 uint32_t cnt = 0, cur, frag;
1573 cur = frag = *txidx;
1576 * Start packing the mbufs in this chain into
1577 * the fragment pointers. Stop when we run out
1578 * of fragments or hit the end of the mbuf chain.
1580 for (m = m_head; m != NULL; m = m->m_next) {
1581 if (m->m_len != 0) {
1582 if ((SK_TX_RING_CNT -
1583 (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2)
1585 f = &sc_if->sk_rdata->sk_tx_ring[frag];
1586 f->sk_data_lo = vtophys(mtod(m, vm_offset_t));
1587 f->sk_ctl = m->m_len | SK_OPCODE_DEFAULT;
1589 f->sk_ctl |= SK_TXCTL_FIRSTFRAG;
1591 f->sk_ctl |= SK_TXCTL_OWN;
1593 SK_INC(frag, SK_TX_RING_CNT);
1601 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |=
1602 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR;
1603 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head;
1604 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN;
1605 sc_if->sk_cdata.sk_tx_cnt += cnt;
1613 sk_start(struct ifnet *ifp)
1615 struct sk_if_softc *sc_if = ifp->if_softc;
1616 struct sk_softc *sc = sc_if->sk_softc;
1617 struct mbuf *m_head = NULL;
1621 idx = sc_if->sk_cdata.sk_tx_prod;
1624 while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) {
1625 m_head = ifq_poll(&ifp->if_snd);
1630 * Pack the data into the transmit ring. If we
1631 * don't have room, set the OACTIVE flag and wait
1632 * for the NIC to drain the ring.
1634 if (sk_encap(sc_if, m_head, &idx)) {
1635 ifp->if_flags |= IFF_OACTIVE;
1638 m_head = ifq_dequeue(&ifp->if_snd);
1641 BPF_MTAP(ifp, m_head);
1648 sc_if->sk_cdata.sk_tx_prod = idx;
1649 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
1651 /* Set a timeout in case the chip goes out to lunch. */
1657 sk_watchdog(struct ifnet *ifp)
1659 struct sk_if_softc *sc_if;
1661 sc_if = ifp->if_softc;
1663 printf("sk%d: watchdog timeout\n", sc_if->sk_unit);
1666 if (!ifq_is_empty(&ifp->if_snd))
1671 skc_shutdown(device_t dev)
1673 struct sk_softc *sc = device_get_softc(dev);
1675 /* Turn off the 'driver is loaded' LED. */
1676 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF);
1679 * Reset the GEnesis controller. Doing this should also
1680 * assert the resets on the attached XMAC(s).
1686 sk_rxeof(struct sk_if_softc *sc_if)
1688 struct ifnet *ifp = &sc_if->arpcom.ac_if;
1690 struct sk_chain *cur_rx;
1691 int i, total_len = 0;
1694 i = sc_if->sk_cdata.sk_rx_prod;
1695 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i];
1697 while(!(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl & SK_RXCTL_OWN)) {
1698 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i];
1699 rxstat = sc_if->sk_rdata->sk_rx_ring[i].sk_xmac_rxstat;
1700 m = cur_rx->sk_mbuf;
1701 cur_rx->sk_mbuf = NULL;
1702 total_len = SK_RXBYTES(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl);
1703 SK_INC(i, SK_RX_RING_CNT);
1705 if (rxstat & XM_RXSTAT_ERRFRAME) {
1707 sk_newbuf(sc_if, cur_rx, m);
1712 * Try to allocate a new jumbo buffer. If that
1713 * fails, copy the packet to mbufs and put the
1714 * jumbo buffer back in the ring so it can be
1715 * re-used. If allocating mbufs fails, then we
1716 * have to drop the packet.
1718 if (sk_newbuf(sc_if, cur_rx, NULL) == ENOBUFS) {
1720 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1721 total_len + ETHER_ALIGN, 0, ifp, NULL);
1722 sk_newbuf(sc_if, cur_rx, m);
1724 printf("sk%d: no receive buffers "
1725 "available -- packet dropped!\n",
1730 m_adj(m0, ETHER_ALIGN);
1733 m->m_pkthdr.rcvif = ifp;
1734 m->m_pkthdr.len = m->m_len = total_len;
1738 (*ifp->if_input)(ifp, m);
1741 sc_if->sk_cdata.sk_rx_prod = i;
1745 sk_txeof(struct sk_if_softc *sc_if)
1747 struct ifnet *ifp = &sc_if->arpcom.ac_if;
1748 struct sk_tx_desc *cur_tx = NULL;
1752 * Go through our tx ring and free mbufs for those
1753 * frames that have been sent.
1755 idx = sc_if->sk_cdata.sk_tx_cons;
1756 while(idx != sc_if->sk_cdata.sk_tx_prod) {
1757 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx];
1758 if (cur_tx->sk_ctl & SK_TXCTL_OWN)
1760 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG)
1762 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) {
1763 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf);
1764 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL;
1766 sc_if->sk_cdata.sk_tx_cnt--;
1767 SK_INC(idx, SK_TX_RING_CNT);
1771 sc_if->sk_cdata.sk_tx_cons = idx;
1774 ifp->if_flags &= ~IFF_OACTIVE;
1778 sk_tick(void *xsc_if)
1780 struct sk_if_softc *sc_if = xsc_if;
1781 struct ifnet *ifp = &sc_if->arpcom.ac_if;
1782 struct mii_data *mii = device_get_softc(sc_if->sk_miibus);
1785 if ((ifp->if_flags & IFF_UP) == 0)
1788 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
1789 sk_intr_bcom(sc_if);
1794 * According to SysKonnect, the correct way to verify that
1795 * the link has come back up is to poll bit 0 of the GPIO
1796 * register three times. This pin has the signal from the
1797 * link_sync pin connected to it; if we read the same link
1798 * state 3 times in a row, we know the link is up.
1800 for (i = 0; i < 3; i++) {
1801 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET)
1806 callout_reset(&sc_if->sk_tick_timer, hz, sk_tick, sc_if);
1810 /* Turn the GP0 interrupt back on. */
1811 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
1812 SK_XM_READ_2(sc_if, XM_ISR);
1815 callout_stop(&sc_if->sk_tick_timer);
1819 sk_intr_bcom(struct sk_if_softc *sc_if)
1821 struct ifnet *ifp = &sc_if->arpcom.ac_if;
1822 struct mii_data *mii = device_get_softc(sc_if->sk_miibus);
1825 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
1828 * Read the PHY interrupt register to make sure
1829 * we clear any pending interrupts.
1831 status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR);
1833 if ((ifp->if_flags & IFF_RUNNING) == 0) {
1834 sk_init_xmac(sc_if);
1838 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) {
1840 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM,
1843 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) {
1845 /* Turn off the link LED. */
1846 SK_IF_WRITE_1(sc_if, 0,
1847 SK_LINKLED1_CTL, SK_LINKLED_OFF);
1849 } else if (status & BRGPHY_ISR_LNK_CHG) {
1850 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
1851 BRGPHY_MII_IMR, 0xFF00);
1854 /* Turn on the link LED. */
1855 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
1856 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF|
1857 SK_LINKLED_BLINK_OFF);
1861 callout_reset(&sc_if->sk_tick_timer, hz,
1866 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
1870 sk_intr_xmac(struct sk_if_softc *sc_if)
1874 status = SK_XM_READ_2(sc_if, XM_ISR);
1877 * Link has gone down. Start MII tick timeout to
1878 * watch for link resync.
1880 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) {
1881 if (status & XM_ISR_GP0_SET) {
1882 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
1883 callout_reset(&sc_if->sk_tick_timer, hz,
1887 if (status & XM_ISR_AUTONEG_DONE) {
1888 callout_reset(&sc_if->sk_tick_timer, hz,
1893 if (status & XM_IMR_TX_UNDERRUN)
1894 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO);
1896 if (status & XM_IMR_RX_OVERRUN)
1897 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO);
1899 status = SK_XM_READ_2(sc_if, XM_ISR);
1903 sk_intr_yukon(struct sk_if_softc *sc_if)
1907 status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
1913 struct sk_softc *sc = xsc;
1914 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A];
1915 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_A];
1916 struct ifnet *ifp0 = NULL, *ifp1 = NULL;
1920 ifp0 = &sc_if0->arpcom.ac_if;
1922 ifp1 = &sc_if1->arpcom.ac_if;
1925 status = CSR_READ_4(sc, SK_ISSR);
1926 if ((status & sc->sk_intrmask) == 0)
1929 /* Handle receive interrupts first. */
1930 if (status & SK_ISR_RX1_EOF) {
1932 CSR_WRITE_4(sc, SK_BMU_RX_CSR0,
1933 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
1935 if (status & SK_ISR_RX2_EOF) {
1937 CSR_WRITE_4(sc, SK_BMU_RX_CSR1,
1938 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
1941 /* Then transmit interrupts. */
1942 if (status & SK_ISR_TX1_S_EOF) {
1944 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0,
1945 SK_TXBMU_CLR_IRQ_EOF);
1947 if (status & SK_ISR_TX2_S_EOF) {
1949 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1,
1950 SK_TXBMU_CLR_IRQ_EOF);
1953 /* Then MAC interrupts. */
1954 if (status & SK_ISR_MAC1 && ifp0->if_flags & IFF_RUNNING) {
1955 if (sc->sk_type == SK_GENESIS)
1956 sk_intr_xmac(sc_if0);
1958 sk_intr_yukon(sc_if0);
1961 if (status & SK_ISR_MAC2 && ifp1->if_flags & IFF_RUNNING) {
1962 if (sc->sk_type == SK_GENESIS)
1963 sk_intr_xmac(sc_if1);
1965 sk_intr_yukon(sc_if0);
1968 if (status & SK_ISR_EXTERNAL_REG) {
1970 sc_if0->sk_phytype == SK_PHYTYPE_BCOM)
1971 sk_intr_bcom(sc_if0);
1973 sc_if1->sk_phytype == SK_PHYTYPE_BCOM)
1974 sk_intr_bcom(sc_if1);
1978 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
1980 if (ifp0 != NULL && !ifq_is_empty(&ifp0->if_snd))
1982 if (ifp1 != NULL && !ifq_is_empty(&ifp0->if_snd))
1987 sk_init_xmac(struct sk_if_softc *sc_if)
1989 struct sk_softc *sc = sc_if->sk_softc;
1990 struct ifnet *ifp = &sc_if->arpcom.ac_if;
1991 struct sk_bcom_hack bhack[] = {
1992 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 },
1993 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 },
1994 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1997 /* Unreset the XMAC. */
1998 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET);
2001 /* Reset the XMAC's internal state. */
2002 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
2004 /* Save the XMAC II revision */
2005 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID));
2008 * Perform additional initialization for external PHYs,
2009 * namely for the 1000baseTX cards that use the XMAC's
2012 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2016 /* Take PHY out of reset. */
2017 val = sk_win_read_4(sc, SK_GPIO);
2018 if (sc_if->sk_port == SK_PORT_A)
2019 val |= SK_GPIO_DIR0|SK_GPIO_DAT0;
2021 val |= SK_GPIO_DIR2|SK_GPIO_DAT2;
2022 sk_win_write_4(sc, SK_GPIO, val);
2024 /* Enable GMII mode on the XMAC. */
2025 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE);
2027 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2028 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET);
2030 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2031 BRGPHY_MII_IMR, 0xFFF0);
2034 * Early versions of the BCM5400 apparently have
2035 * a bug that requires them to have their reserved
2036 * registers initialized to some magic values. I don't
2037 * know what the numbers do, I'm just the messenger.
2039 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03)
2041 while(bhack[i].reg) {
2042 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2043 bhack[i].reg, bhack[i].val);
2049 /* Set station address */
2050 SK_XM_WRITE_2(sc_if, XM_PAR0,
2051 *(uint16_t *)(&sc_if->arpcom.ac_enaddr[0]));
2052 SK_XM_WRITE_2(sc_if, XM_PAR1,
2053 *(uint16_t *)(&sc_if->arpcom.ac_enaddr[2]));
2054 SK_XM_WRITE_2(sc_if, XM_PAR2,
2055 *(uint16_t *)(&sc_if->arpcom.ac_enaddr[4]));
2056 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION);
2058 if (ifp->if_flags & IFF_BROADCAST)
2059 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
2061 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
2063 /* We don't need the FCS appended to the packet. */
2064 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS);
2066 /* We want short frames padded to 60 bytes. */
2067 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD);
2070 * Enable the reception of all error frames. This is is
2071 * a necessary evil due to the design of the XMAC. The
2072 * XMAC's receive FIFO is only 8K in size, however jumbo
2073 * frames can be up to 9000 bytes in length. When bad
2074 * frame filtering is enabled, the XMAC's RX FIFO operates
2075 * in 'store and forward' mode. For this to work, the
2076 * entire frame has to fit into the FIFO, but that means
2077 * that jumbo frames larger than 8192 bytes will be
2078 * truncated. Disabling all bad frame filtering causes
2079 * the RX FIFO to operate in streaming mode, in which
2080 * case the XMAC will start transfering frames out of the
2081 * RX FIFO as soon as the FIFO threshold is reached.
2083 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES|
2084 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS|
2085 XM_MODE_RX_INRANGELEN);
2087 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2088 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
2090 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
2093 * Bump up the transmit threshold. This helps hold off transmit
2094 * underruns when we're blasting traffic from both ports at once.
2096 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH);
2098 /* Set promiscuous mode */
2099 sk_setpromisc(sc_if);
2101 /* Set multicast filter */
2104 /* Clear and enable interrupts */
2105 SK_XM_READ_2(sc_if, XM_ISR);
2106 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
2107 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS);
2109 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
2111 /* Configure MAC arbiter */
2112 switch(sc_if->sk_xmac_rev) {
2113 case XM_XMAC_REV_B2:
2114 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2);
2115 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2);
2116 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2);
2117 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2);
2118 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2);
2119 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2);
2120 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2);
2121 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2);
2122 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
2124 case XM_XMAC_REV_C1:
2125 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1);
2126 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1);
2127 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1);
2128 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1);
2129 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1);
2130 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1);
2131 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1);
2132 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1);
2133 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
2138 sk_win_write_2(sc, SK_MACARB_CTL,
2139 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF);
2145 sk_init_yukon(struct sk_if_softc *sc_if)
2147 struct ifnet *ifp = &sc_if->arpcom.ac_if;
2152 /* GMAC and GPHY Reset */
2153 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET);
2154 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
2156 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR);
2157 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
2160 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP |
2161 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE;
2163 switch(sc_if->sk_softc->sk_pmd) {
2166 phy |= SK_GPHY_FIBER;
2171 phy |= SK_GPHY_COPPER;
2175 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET);
2177 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR);
2178 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF |
2179 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR);
2181 /* unused read of the interrupt source register */
2182 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
2184 reg = SK_YU_READ_2(sc_if, YUKON_PAR);
2186 /* MIB Counter Clear Mode set */
2187 reg |= YU_PAR_MIB_CLR;
2188 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
2190 /* MIB Counter Clear Mode clear */
2191 reg &= ~YU_PAR_MIB_CLR;
2192 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
2194 /* receive control reg */
2195 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR);
2197 /* transmit parameter register */
2198 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) |
2199 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) );
2201 /* serial mode register */
2202 reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e);
2203 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2204 reg |= YU_SMR_MFL_JUMBO;
2205 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg);
2207 /* Setup Yukon's address */
2208 for (i = 0; i < 3; i++) {
2209 /* Write Source Address 1 (unicast filter) */
2210 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4,
2211 sc_if->arpcom.ac_enaddr[i * 2] |
2212 sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8);
2215 for (i = 0; i < 3; i++) {
2216 reg = sk_win_read_2(sc_if->sk_softc,
2217 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8);
2218 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg);
2221 /* Set promiscuous mode */
2222 sk_setpromisc(sc_if);
2224 /* Set multicast filter */
2227 /* enable interrupt mask for counter overflows */
2228 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0);
2229 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0);
2230 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0);
2232 /* Configure RX MAC FIFO */
2233 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR);
2234 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON);
2236 /* Configure TX MAC FIFO */
2237 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR);
2238 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON);
2242 * Note that to properly initialize any part of the GEnesis chip,
2243 * you first have to take it out of reset mode.
2248 struct sk_if_softc *sc_if = xsc;
2249 struct sk_softc *sc = sc_if->sk_softc;
2250 struct ifnet *ifp = &sc_if->arpcom.ac_if;
2251 struct mii_data *mii = device_get_softc(sc_if->sk_miibus);
2256 /* Cancel pending I/O and free all RX/TX buffers. */
2259 if (sc->sk_type == SK_GENESIS) {
2260 /* Configure LINK_SYNC LED */
2261 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON);
2262 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
2263 SK_LINKLED_LINKSYNC_ON);
2265 /* Configure RX LED */
2266 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL,
2267 SK_RXLEDCTL_COUNTER_START);
2269 /* Configure TX LED */
2270 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL,
2271 SK_TXLEDCTL_COUNTER_START);
2274 /* Configure I2C registers */
2276 /* Configure XMAC(s) */
2277 switch (sc->sk_type) {
2279 sk_init_xmac(sc_if);
2282 sk_init_yukon(sc_if);
2287 if (sc->sk_type == SK_GENESIS) {
2288 /* Configure MAC FIFOs */
2289 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET);
2290 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END);
2291 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON);
2293 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET);
2294 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END);
2295 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON);
2298 /* Configure transmit arbiter(s) */
2299 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL,
2300 SK_TXARCTL_ON | SK_TXARCTL_FSYNC_ON);
2302 /* Configure RAMbuffers */
2303 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET);
2304 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart);
2305 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart);
2306 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart);
2307 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend);
2308 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON);
2310 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET);
2311 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON);
2312 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart);
2313 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart);
2314 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart);
2315 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend);
2316 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON);
2318 /* Configure BMUs */
2319 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE);
2320 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
2321 vtophys(&sc_if->sk_rdata->sk_rx_ring[0]));
2322 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0);
2324 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE);
2325 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO,
2326 vtophys(&sc_if->sk_rdata->sk_tx_ring[0]));
2327 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0);
2329 /* Init descriptors */
2330 if (sk_init_rx_ring(sc_if) == ENOBUFS) {
2331 printf("sk%d: initialization failed: no "
2332 "memory for rx buffers\n", sc_if->sk_unit);
2337 sk_init_tx_ring(sc_if);
2339 /* Configure interrupt handling */
2340 CSR_READ_4(sc, SK_ISSR);
2341 if (sc_if->sk_port == SK_PORT_A)
2342 sc->sk_intrmask |= SK_INTRS1;
2344 sc->sk_intrmask |= SK_INTRS2;
2346 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG;
2348 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2351 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START);
2353 switch(sc->sk_type) {
2355 /* Enable XMACs TX and RX state machines */
2356 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE);
2357 SK_XM_SETBIT_2(sc_if, XM_MMUCMD,
2358 XM_MMUCMD_TX_ENB | XM_MMUCMD_RX_ENB);
2361 reg = SK_YU_READ_2(sc_if, YUKON_GPCR);
2362 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN;
2363 reg &= ~(YU_GPCR_SPEED_EN | YU_GPCR_DPLX_EN);
2364 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg);
2367 ifp->if_flags |= IFF_RUNNING;
2368 ifp->if_flags &= ~IFF_OACTIVE;
2374 sk_stop(struct sk_if_softc *sc_if)
2377 struct sk_softc *sc = sc_if->sk_softc;
2378 struct ifnet *ifp = &sc_if->arpcom.ac_if;
2380 callout_stop(&sc_if->sk_tick_timer);
2382 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2385 /* Put PHY back into reset. */
2386 val = sk_win_read_4(sc, SK_GPIO);
2387 if (sc_if->sk_port == SK_PORT_A) {
2388 val |= SK_GPIO_DIR0;
2389 val &= ~SK_GPIO_DAT0;
2391 val |= SK_GPIO_DIR2;
2392 val &= ~SK_GPIO_DAT2;
2394 sk_win_write_4(sc, SK_GPIO, val);
2397 /* Turn off various components of this interface. */
2398 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
2399 switch (sc->sk_type) {
2401 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET);
2402 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET);
2405 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET);
2406 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET);
2409 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE);
2410 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET | SK_RBCTL_OFF);
2411 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE);
2412 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST,
2413 SK_RBCTL_RESET | SK_RBCTL_OFF);
2414 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF);
2415 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
2416 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
2417 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF);
2418 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF);
2420 /* Disable interrupts */
2421 if (sc_if->sk_port == SK_PORT_A)
2422 sc->sk_intrmask &= ~SK_INTRS1;
2424 sc->sk_intrmask &= ~SK_INTRS2;
2425 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2427 SK_XM_READ_2(sc_if, XM_ISR);
2428 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
2430 /* Free RX and TX mbufs still in the queues. */
2431 for (i = 0; i < SK_RX_RING_CNT; i++) {
2432 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) {
2433 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf);
2434 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL;
2438 for (i = 0; i < SK_TX_RING_CNT; i++) {
2439 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) {
2440 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf);
2441 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL;
2445 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);