1 /******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
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13 notice, this list of conditions and the following disclaimer in the
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18 this software without specific prior written permission.
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21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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32 ******************************************************************************/
35 /* 82562G 10/100 Network Connection
36 * 82562G-2 10/100 Network Connection
37 * 82562GT 10/100 Network Connection
38 * 82562GT-2 10/100 Network Connection
39 * 82562V 10/100 Network Connection
40 * 82562V-2 10/100 Network Connection
41 * 82566DC-2 Gigabit Network Connection
42 * 82566DC Gigabit Network Connection
43 * 82566DM-2 Gigabit Network Connection
44 * 82566DM Gigabit Network Connection
45 * 82566MC Gigabit Network Connection
46 * 82566MM Gigabit Network Connection
47 * 82567LM Gigabit Network Connection
48 * 82567LF Gigabit Network Connection
49 * 82567V Gigabit Network Connection
50 * 82567LM-2 Gigabit Network Connection
51 * 82567LF-2 Gigabit Network Connection
52 * 82567V-2 Gigabit Network Connection
53 * 82567LF-3 Gigabit Network Connection
54 * 82567LM-3 Gigabit Network Connection
55 * 82567LM-4 Gigabit Network Connection
56 * 82577LM Gigabit Network Connection
57 * 82577LC Gigabit Network Connection
58 * 82578DM Gigabit Network Connection
59 * 82578DC Gigabit Network Connection
60 * 82579LM Gigabit Network Connection
61 * 82579V Gigabit Network Connection
62 * Ethernet Connection I217-LM
63 * Ethernet Connection I217-V
64 * Ethernet Connection I218-V
65 * Ethernet Connection I218-LM
66 * Ethernet Connection (2) I218-LM
67 * Ethernet Connection (2) I218-V
68 * Ethernet Connection (3) I218-LM
69 * Ethernet Connection (3) I218-V
72 #include "e1000_api.h"
74 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
75 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
76 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);
77 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw);
78 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
79 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
80 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
81 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
82 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw);
83 static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
86 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
87 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
88 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
89 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
91 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
93 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
94 u16 words, u16 *data);
95 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
97 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
98 u16 words, u16 *data);
99 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
100 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
101 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw);
102 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
104 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
105 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
106 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw);
107 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw);
108 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
109 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
110 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
111 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
112 u16 *speed, u16 *duplex);
113 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
114 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
115 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
116 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
117 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
118 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
119 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
120 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
121 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
122 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
123 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
124 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
125 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
126 u32 offset, u8 *data);
127 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
129 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
131 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
132 u32 offset, u32 *data);
133 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
134 u32 offset, u32 data);
135 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
136 u32 offset, u32 dword);
137 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
138 u32 offset, u16 *data);
139 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
140 u32 offset, u8 byte);
141 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
142 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
143 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
144 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
145 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
146 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
147 static s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr);
149 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
150 /* Offset 04h HSFSTS */
151 union ich8_hws_flash_status {
153 u16 flcdone:1; /* bit 0 Flash Cycle Done */
154 u16 flcerr:1; /* bit 1 Flash Cycle Error */
155 u16 dael:1; /* bit 2 Direct Access error Log */
156 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
157 u16 flcinprog:1; /* bit 5 flash cycle in Progress */
158 u16 reserved1:2; /* bit 13:6 Reserved */
159 u16 reserved2:6; /* bit 13:6 Reserved */
160 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
161 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
166 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
167 /* Offset 06h FLCTL */
168 union ich8_hws_flash_ctrl {
169 struct ich8_hsflctl {
170 u16 flcgo:1; /* 0 Flash Cycle Go */
171 u16 flcycle:2; /* 2:1 Flash Cycle */
172 u16 reserved:5; /* 7:3 Reserved */
173 u16 fldbcount:2; /* 9:8 Flash Data Byte Count */
174 u16 flockdn:6; /* 15:10 Reserved */
179 /* ICH Flash Region Access Permissions */
180 union ich8_hws_flash_regacc {
182 u32 grra:8; /* 0:7 GbE region Read Access */
183 u32 grwa:8; /* 8:15 GbE region Write Access */
184 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
185 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
191 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
192 * @hw: pointer to the HW structure
194 * Test access to the PHY registers by reading the PHY ID registers. If
195 * the PHY ID is already known (e.g. resume path) compare it with known ID,
196 * otherwise assume the read PHY ID is correct if it is valid.
198 * Assumes the sw/fw/hw semaphore is already acquired.
200 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
208 for (retry_count = 0; retry_count < 2; retry_count++) {
209 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg);
210 if (ret_val || (phy_reg == 0xFFFF))
212 phy_id = (u32)(phy_reg << 16);
214 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg);
215 if (ret_val || (phy_reg == 0xFFFF)) {
219 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
224 if (hw->phy.id == phy_id)
228 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
232 /* In case the PHY needs to be in mdio slow mode,
233 * set slow mode and try to get the PHY id again.
235 if (hw->mac.type < e1000_pch_lpt) {
236 hw->phy.ops.release(hw);
237 ret_val = e1000_set_mdio_slow_mode_hv(hw);
239 ret_val = e1000_get_phy_id(hw);
240 hw->phy.ops.acquire(hw);
246 if ((hw->mac.type == e1000_pch_lpt) ||
247 (hw->mac.type == e1000_pch_spt)) {
248 /* Only unforce SMBus if ME is not active */
249 if (!(E1000_READ_REG(hw, E1000_FWSM) &
250 E1000_ICH_FWSM_FW_VALID)) {
251 /* Unforce SMBus mode in PHY */
252 hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg);
253 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
254 hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg);
256 /* Unforce SMBus mode in MAC */
257 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
258 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
259 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
267 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
268 * @hw: pointer to the HW structure
270 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is
271 * used to reset the PHY to a quiescent state when necessary.
273 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
277 DEBUGFUNC("e1000_toggle_lanphypc_pch_lpt");
279 /* Set Phy Config Counter to 50msec */
280 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
281 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
282 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
283 E1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg);
285 /* Toggle LANPHYPC Value bit */
286 mac_reg = E1000_READ_REG(hw, E1000_CTRL);
287 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
288 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
289 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
290 E1000_WRITE_FLUSH(hw);
292 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
293 E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
294 E1000_WRITE_FLUSH(hw);
296 if (hw->mac.type < e1000_pch_lpt) {
303 } while (!(E1000_READ_REG(hw, E1000_CTRL_EXT) &
304 E1000_CTRL_EXT_LPCD) && count--);
311 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
312 * @hw: pointer to the HW structure
314 * Workarounds/flow necessary for PHY initialization during driver load
317 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
319 u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM);
322 DEBUGFUNC("e1000_init_phy_workarounds_pchlan");
324 /* Gate automatic PHY configuration by hardware on managed and
325 * non-managed 82579 and newer adapters.
327 e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
329 /* It is not possible to be certain of the current state of ULP
330 * so forcibly disable it.
332 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
333 e1000_disable_ulp_lpt_lp(hw, TRUE);
335 ret_val = hw->phy.ops.acquire(hw);
337 DEBUGOUT("Failed to initialize PHY flow\n");
341 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is
342 * inaccessible and resetting the PHY is not blocked, toggle the
343 * LANPHYPC Value bit to force the interconnect to PCIe mode.
345 switch (hw->mac.type) {
348 if (e1000_phy_is_accessible_pchlan(hw))
351 /* Before toggling LANPHYPC, see if PHY is accessible by
352 * forcing MAC to SMBus mode first.
354 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
355 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
356 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
358 /* Wait 50 milliseconds for MAC to finish any retries
359 * that it might be trying to perform from previous
360 * attempts to acknowledge any phy read requests.
366 if (e1000_phy_is_accessible_pchlan(hw))
371 if ((hw->mac.type == e1000_pchlan) &&
372 (fwsm & E1000_ICH_FWSM_FW_VALID))
375 if (hw->phy.ops.check_reset_block(hw)) {
376 DEBUGOUT("Required LANPHYPC toggle blocked by ME\n");
377 ret_val = -E1000_ERR_PHY;
381 /* Toggle LANPHYPC Value bit */
382 e1000_toggle_lanphypc_pch_lpt(hw);
383 if (hw->mac.type >= e1000_pch_lpt) {
384 if (e1000_phy_is_accessible_pchlan(hw))
387 /* Toggling LANPHYPC brings the PHY out of SMBus mode
388 * so ensure that the MAC is also out of SMBus mode
390 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
391 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
392 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
394 if (e1000_phy_is_accessible_pchlan(hw))
397 ret_val = -E1000_ERR_PHY;
404 hw->phy.ops.release(hw);
407 /* Check to see if able to reset PHY. Print error if not */
408 if (hw->phy.ops.check_reset_block(hw)) {
409 ERROR_REPORT("Reset blocked by ME\n");
413 /* Reset the PHY before any access to it. Doing so, ensures
414 * that the PHY is in a known good state before we read/write
415 * PHY registers. The generic reset is sufficient here,
416 * because we haven't determined the PHY type yet.
418 ret_val = e1000_phy_hw_reset_generic(hw);
422 /* On a successful reset, possibly need to wait for the PHY
423 * to quiesce to an accessible state before returning control
424 * to the calling function. If the PHY does not quiesce, then
425 * return E1000E_BLK_PHY_RESET, as this is the condition that
428 ret_val = hw->phy.ops.check_reset_block(hw);
430 ERROR_REPORT("ME blocked access to PHY after reset\n");
434 /* Ungate automatic PHY configuration on non-managed 82579 */
435 if ((hw->mac.type == e1000_pch2lan) &&
436 !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
438 e1000_gate_hw_phy_config_ich8lan(hw, FALSE);
445 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
446 * @hw: pointer to the HW structure
448 * Initialize family-specific PHY parameters and function pointers.
450 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
452 struct e1000_phy_info *phy = &hw->phy;
455 DEBUGFUNC("e1000_init_phy_params_pchlan");
458 phy->reset_delay_us = 100;
460 phy->ops.acquire = e1000_acquire_swflag_ich8lan;
461 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
462 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
463 phy->ops.set_page = e1000_set_page_igp;
464 phy->ops.read_reg = e1000_read_phy_reg_hv;
465 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
466 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
467 phy->ops.release = e1000_release_swflag_ich8lan;
468 phy->ops.reset = e1000_phy_hw_reset_ich8lan;
469 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
470 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
471 phy->ops.write_reg = e1000_write_phy_reg_hv;
472 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
473 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
474 phy->ops.power_up = e1000_power_up_phy_copper;
475 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
476 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
478 phy->id = e1000_phy_unknown;
480 ret_val = e1000_init_phy_workarounds_pchlan(hw);
484 if (phy->id == e1000_phy_unknown)
485 switch (hw->mac.type) {
487 ret_val = e1000_get_phy_id(hw);
490 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
496 /* In case the PHY needs to be in mdio slow mode,
497 * set slow mode and try to get the PHY id again.
499 ret_val = e1000_set_mdio_slow_mode_hv(hw);
502 ret_val = e1000_get_phy_id(hw);
507 phy->type = e1000_get_phy_type_from_id(phy->id);
510 case e1000_phy_82577:
511 case e1000_phy_82579:
513 phy->ops.check_polarity = e1000_check_polarity_82577;
514 phy->ops.force_speed_duplex =
515 e1000_phy_force_speed_duplex_82577;
516 phy->ops.get_cable_length = e1000_get_cable_length_82577;
517 phy->ops.get_info = e1000_get_phy_info_82577;
518 phy->ops.commit = e1000_phy_sw_reset_generic;
520 case e1000_phy_82578:
521 phy->ops.check_polarity = e1000_check_polarity_m88;
522 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
523 phy->ops.get_cable_length = e1000_get_cable_length_m88;
524 phy->ops.get_info = e1000_get_phy_info_m88;
527 ret_val = -E1000_ERR_PHY;
535 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
536 * @hw: pointer to the HW structure
538 * Initialize family-specific PHY parameters and function pointers.
540 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
542 struct e1000_phy_info *phy = &hw->phy;
546 DEBUGFUNC("e1000_init_phy_params_ich8lan");
549 phy->reset_delay_us = 100;
551 phy->ops.acquire = e1000_acquire_swflag_ich8lan;
552 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
553 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
554 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
555 phy->ops.read_reg = e1000_read_phy_reg_igp;
556 phy->ops.release = e1000_release_swflag_ich8lan;
557 phy->ops.reset = e1000_phy_hw_reset_ich8lan;
558 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
559 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
560 phy->ops.write_reg = e1000_write_phy_reg_igp;
561 phy->ops.power_up = e1000_power_up_phy_copper;
562 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
564 /* We may need to do this twice - once for IGP and if that fails,
565 * we'll set BM func pointers and try again
567 ret_val = e1000_determine_phy_address(hw);
569 phy->ops.write_reg = e1000_write_phy_reg_bm;
570 phy->ops.read_reg = e1000_read_phy_reg_bm;
571 ret_val = e1000_determine_phy_address(hw);
573 DEBUGOUT("Cannot determine PHY addr. Erroring out\n");
579 while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) &&
582 ret_val = e1000_get_phy_id(hw);
589 case IGP03E1000_E_PHY_ID:
590 phy->type = e1000_phy_igp_3;
591 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
592 phy->ops.read_reg_locked = e1000_read_phy_reg_igp_locked;
593 phy->ops.write_reg_locked = e1000_write_phy_reg_igp_locked;
594 phy->ops.get_info = e1000_get_phy_info_igp;
595 phy->ops.check_polarity = e1000_check_polarity_igp;
596 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
599 case IFE_PLUS_E_PHY_ID:
601 phy->type = e1000_phy_ife;
602 phy->autoneg_mask = E1000_ALL_NOT_GIG;
603 phy->ops.get_info = e1000_get_phy_info_ife;
604 phy->ops.check_polarity = e1000_check_polarity_ife;
605 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
607 case BME1000_E_PHY_ID:
608 phy->type = e1000_phy_bm;
609 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
610 phy->ops.read_reg = e1000_read_phy_reg_bm;
611 phy->ops.write_reg = e1000_write_phy_reg_bm;
612 phy->ops.commit = e1000_phy_sw_reset_generic;
613 phy->ops.get_info = e1000_get_phy_info_m88;
614 phy->ops.check_polarity = e1000_check_polarity_m88;
615 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
618 return -E1000_ERR_PHY;
622 return E1000_SUCCESS;
626 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
627 * @hw: pointer to the HW structure
629 * Initialize family-specific NVM parameters and function
632 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
634 struct e1000_nvm_info *nvm = &hw->nvm;
635 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
636 u32 gfpreg, sector_base_addr, sector_end_addr;
640 DEBUGFUNC("e1000_init_nvm_params_ich8lan");
642 nvm->type = e1000_nvm_flash_sw;
644 if (hw->mac.type == e1000_pch_spt) {
645 /* in SPT, gfpreg doesn't exist. NVM size is taken from the
646 * STRAP register. This is because in SPT the GbE Flash region
647 * is no longer accessed through the flash registers. Instead,
648 * the mechanism has changed, and the Flash region access
649 * registers are now implemented in GbE memory space.
651 nvm->flash_base_addr = 0;
653 (((E1000_READ_REG(hw, E1000_STRAP) >> 1) & 0x1F) + 1)
654 * NVM_SIZE_MULTIPLIER;
655 nvm->flash_bank_size = nvm_size / 2;
656 /* Adjust to word count */
657 nvm->flash_bank_size /= sizeof(u16);
658 /* Set the base address for flash register access */
659 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;
661 /* Can't read flash registers if register set isn't mapped. */
662 if (!hw->flash_address) {
663 DEBUGOUT("ERROR: Flash registers not mapped\n");
664 return -E1000_ERR_CONFIG;
667 gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
669 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
670 * Add 1 to sector_end_addr since this sector is included in
673 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
674 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
676 /* flash_base_addr is byte-aligned */
677 nvm->flash_base_addr = sector_base_addr
678 << FLASH_SECTOR_ADDR_SHIFT;
680 /* find total size of the NVM, then cut in half since the total
681 * size represents two separate NVM banks.
683 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
684 << FLASH_SECTOR_ADDR_SHIFT);
685 nvm->flash_bank_size /= 2;
686 /* Adjust to word count */
687 nvm->flash_bank_size /= sizeof(u16);
690 nvm->word_size = E1000_SHADOW_RAM_WORDS;
692 /* Clear shadow ram */
693 for (i = 0; i < nvm->word_size; i++) {
694 dev_spec->shadow_ram[i].modified = FALSE;
695 dev_spec->shadow_ram[i].value = 0xFFFF;
698 /* Function Pointers */
699 nvm->ops.acquire = e1000_acquire_nvm_ich8lan;
700 nvm->ops.release = e1000_release_nvm_ich8lan;
701 if (hw->mac.type == e1000_pch_spt) {
702 nvm->ops.read = e1000_read_nvm_spt;
703 nvm->ops.update = e1000_update_nvm_checksum_spt;
705 nvm->ops.read = e1000_read_nvm_ich8lan;
706 nvm->ops.update = e1000_update_nvm_checksum_ich8lan;
708 nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
709 nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan;
710 nvm->ops.write = e1000_write_nvm_ich8lan;
712 return E1000_SUCCESS;
716 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
717 * @hw: pointer to the HW structure
719 * Initialize family-specific MAC parameters and function
722 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
724 struct e1000_mac_info *mac = &hw->mac;
726 DEBUGFUNC("e1000_init_mac_params_ich8lan");
728 /* Set media type function pointer */
729 hw->phy.media_type = e1000_media_type_copper;
731 /* Set mta register count */
732 mac->mta_reg_count = 32;
733 /* Set rar entry count */
734 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
735 if (mac->type == e1000_ich8lan)
736 mac->rar_entry_count--;
737 /* Set if part includes ASF firmware */
738 mac->asf_firmware_present = TRUE;
740 mac->has_fwsm = TRUE;
741 /* ARC subsystem not supported */
742 mac->arc_subsystem_valid = FALSE;
743 /* Adaptive IFS supported */
744 mac->adaptive_ifs = TRUE;
746 /* Function pointers */
748 /* bus type/speed/width */
749 mac->ops.get_bus_info = e1000_get_bus_info_ich8lan;
751 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
753 mac->ops.reset_hw = e1000_reset_hw_ich8lan;
754 /* hw initialization */
755 mac->ops.init_hw = e1000_init_hw_ich8lan;
757 mac->ops.setup_link = e1000_setup_link_ich8lan;
758 /* physical interface setup */
759 mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan;
761 mac->ops.check_for_link = e1000_check_for_copper_link_ich8lan;
763 mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan;
764 /* multicast address update */
765 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
766 /* clear hardware counters */
767 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan;
769 /* LED and other operations */
774 /* check management mode */
775 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
777 mac->ops.id_led_init = e1000_id_led_init_generic;
779 mac->ops.blink_led = e1000_blink_led_generic;
781 mac->ops.setup_led = e1000_setup_led_generic;
783 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
784 /* turn on/off LED */
785 mac->ops.led_on = e1000_led_on_ich8lan;
786 mac->ops.led_off = e1000_led_off_ich8lan;
789 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
790 mac->ops.rar_set = e1000_rar_set_pch2lan;
794 /* multicast address update for pch2 */
795 mac->ops.update_mc_addr_list =
796 e1000_update_mc_addr_list_pch2lan;
799 /* check management mode */
800 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
802 mac->ops.id_led_init = e1000_id_led_init_pchlan;
804 mac->ops.setup_led = e1000_setup_led_pchlan;
806 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
807 /* turn on/off LED */
808 mac->ops.led_on = e1000_led_on_pchlan;
809 mac->ops.led_off = e1000_led_off_pchlan;
815 if ((mac->type == e1000_pch_lpt) ||
816 (mac->type == e1000_pch_spt)) {
817 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
818 mac->ops.rar_set = e1000_rar_set_pch_lpt;
819 mac->ops.setup_physical_interface = e1000_setup_copper_link_pch_lpt;
820 mac->ops.set_obff_timer = e1000_set_obff_timer_pch_lpt;
823 /* Enable PCS Lock-loss workaround for ICH8 */
824 if (mac->type == e1000_ich8lan)
825 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, TRUE);
827 return E1000_SUCCESS;
831 * __e1000_access_emi_reg_locked - Read/write EMI register
832 * @hw: pointer to the HW structure
833 * @addr: EMI address to program
834 * @data: pointer to value to read/write from/to the EMI address
835 * @read: boolean flag to indicate read or write
837 * This helper function assumes the SW/FW/HW Semaphore is already acquired.
839 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
840 u16 *data, bool read)
844 DEBUGFUNC("__e1000_access_emi_reg_locked");
846 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address);
851 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA,
854 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
861 * e1000_read_emi_reg_locked - Read Extended Management Interface register
862 * @hw: pointer to the HW structure
863 * @addr: EMI address to program
864 * @data: value to be read from the EMI address
866 * Assumes the SW/FW/HW Semaphore is already acquired.
868 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
870 DEBUGFUNC("e1000_read_emi_reg_locked");
872 return __e1000_access_emi_reg_locked(hw, addr, data, TRUE);
876 * e1000_write_emi_reg_locked - Write Extended Management Interface register
877 * @hw: pointer to the HW structure
878 * @addr: EMI address to program
879 * @data: value to be written to the EMI address
881 * Assumes the SW/FW/HW Semaphore is already acquired.
883 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
885 DEBUGFUNC("e1000_read_emi_reg_locked");
887 return __e1000_access_emi_reg_locked(hw, addr, &data, FALSE);
891 * e1000_set_eee_pchlan - Enable/disable EEE support
892 * @hw: pointer to the HW structure
894 * Enable/disable EEE based on setting in dev_spec structure, the duplex of
895 * the link and the EEE capabilities of the link partner. The LPI Control
896 * register bits will remain set only if/when link is up.
898 * EEE LPI must not be asserted earlier than one second after link is up.
899 * On 82579, EEE LPI should not be enabled until such time otherwise there
900 * can be link issues with some switches. Other devices can have EEE LPI
901 * enabled immediately upon link up since they have a timer in hardware which
902 * prevents LPI from being asserted too early.
904 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
906 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
908 u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
910 DEBUGFUNC("e1000_set_eee_pchlan");
912 switch (hw->phy.type) {
913 case e1000_phy_82579:
914 lpa = I82579_EEE_LP_ABILITY;
915 pcs_status = I82579_EEE_PCS_STATUS;
916 adv_addr = I82579_EEE_ADVERTISEMENT;
919 lpa = I217_EEE_LP_ABILITY;
920 pcs_status = I217_EEE_PCS_STATUS;
921 adv_addr = I217_EEE_ADVERTISEMENT;
924 return E1000_SUCCESS;
927 ret_val = hw->phy.ops.acquire(hw);
931 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
935 /* Clear bits that enable EEE in various speeds */
936 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
938 /* Enable EEE if not disabled by user */
939 if (!dev_spec->eee_disable) {
940 /* Save off link partner's EEE ability */
941 ret_val = e1000_read_emi_reg_locked(hw, lpa,
942 &dev_spec->eee_lp_ability);
946 /* Read EEE advertisement */
947 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
951 /* Enable EEE only for speeds in which the link partner is
952 * EEE capable and for which we advertise EEE.
954 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
955 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
957 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
958 hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data);
959 if (data & NWAY_LPAR_100TX_FD_CAPS)
960 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
962 /* EEE is not supported in 100Half, so ignore
963 * partner's EEE in 100 ability if full-duplex
966 dev_spec->eee_lp_ability &=
967 ~I82579_EEE_100_SUPPORTED;
971 if (hw->phy.type == e1000_phy_82579) {
972 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
977 data &= ~I82579_LPI_100_PLL_SHUT;
978 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
982 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
983 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
987 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
989 hw->phy.ops.release(hw);
995 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
996 * @hw: pointer to the HW structure
997 * @link: link up bool flag
999 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
1000 * preventing further DMA write requests. Workaround the issue by disabling
1001 * the de-assertion of the clock request when in 1Gpbs mode.
1002 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
1003 * speeds in order to avoid Tx hangs.
1005 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
1007 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
1008 u32 status = E1000_READ_REG(hw, E1000_STATUS);
1009 s32 ret_val = E1000_SUCCESS;
1012 if (link && (status & E1000_STATUS_SPEED_1000)) {
1013 ret_val = hw->phy.ops.acquire(hw);
1018 e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
1024 e1000_write_kmrn_reg_locked(hw,
1025 E1000_KMRNCTRLSTA_K1_CONFIG,
1027 ~E1000_KMRNCTRLSTA_K1_ENABLE);
1033 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
1034 fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
1037 e1000_write_kmrn_reg_locked(hw,
1038 E1000_KMRNCTRLSTA_K1_CONFIG,
1041 hw->phy.ops.release(hw);
1043 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
1044 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
1046 if ((hw->phy.revision > 5) || !link ||
1047 ((status & E1000_STATUS_SPEED_100) &&
1048 (status & E1000_STATUS_FD)))
1049 goto update_fextnvm6;
1051 ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, ®);
1055 /* Clear link status transmit timeout */
1056 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
1058 if (status & E1000_STATUS_SPEED_100) {
1059 /* Set inband Tx timeout to 5x10us for 100Half */
1060 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1062 /* Do not extend the K1 entry latency for 100Half */
1063 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1065 /* Set inband Tx timeout to 50x10us for 10Full/Half */
1067 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1069 /* Extend the K1 entry latency for 10 Mbps */
1070 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1073 ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg);
1078 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1084 static u64 e1000_ltr2ns(u16 ltr)
1088 /* Determine the latency in nsec based on the LTR value & scale */
1089 value = ltr & E1000_LTRV_VALUE_MASK;
1090 scale = (ltr & E1000_LTRV_SCALE_MASK) >> E1000_LTRV_SCALE_SHIFT;
1092 return value * (1 << (scale * E1000_LTRV_SCALE_FACTOR));
1096 * e1000_platform_pm_pch_lpt - Set platform power management values
1097 * @hw: pointer to the HW structure
1098 * @link: bool indicating link status
1100 * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
1101 * GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
1102 * when link is up (which must not exceed the maximum latency supported
1103 * by the platform), otherwise specify there is no LTR requirement.
1104 * Unlike TRUE-PCIe devices which set the LTR maximum snoop/no-snoop
1105 * latencies in the LTR Extended Capability Structure in the PCIe Extended
1106 * Capability register set, on this device LTR is set by writing the
1107 * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
1108 * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
1109 * message to the PMC.
1111 * Use the LTR value to calculate the Optimized Buffer Flush/Fill (OBFF)
1114 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
1116 u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |
1117 link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND;
1118 u16 lat_enc = 0; /* latency encoded */
1121 DEBUGFUNC("e1000_platform_pm_pch_lpt");
1124 u16 speed, duplex, scale = 0;
1125 u16 max_snoop, max_nosnoop;
1126 u16 max_ltr_enc; /* max LTR latency encoded */
1131 if (!hw->mac.max_frame_size) {
1132 DEBUGOUT("max_frame_size not set.\n");
1133 return -E1000_ERR_CONFIG;
1136 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1138 DEBUGOUT("Speed not set.\n");
1139 return -E1000_ERR_CONFIG;
1142 /* Rx Packet Buffer Allocation size (KB) */
1143 rxa = E1000_READ_REG(hw, E1000_PBA) & E1000_PBA_RXA_MASK;
1145 /* Determine the maximum latency tolerated by the device.
1147 * Per the PCIe spec, the tolerated latencies are encoded as
1148 * a 3-bit encoded scale (only 0-5 are valid) multiplied by
1149 * a 10-bit value (0-1023) to provide a range from 1 ns to
1150 * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns,
1151 * 1=2^5ns, 2=2^10ns,...5=2^25ns.
1153 lat_ns = ((s64)rxa * 1024 -
1154 (2 * (s64)hw->mac.max_frame_size)) * 8 * 1000;
1161 while (value > E1000_LTRV_VALUE_MASK) {
1163 value = E1000_DIVIDE_ROUND_UP(value, (1 << 5));
1165 if (scale > E1000_LTRV_SCALE_MAX) {
1166 DEBUGOUT1("Invalid LTR latency scale %d\n", scale);
1167 return -E1000_ERR_CONFIG;
1169 lat_enc = (u16)((scale << E1000_LTRV_SCALE_SHIFT) | value);
1171 /* Determine the maximum latency tolerated by the platform */
1172 e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT, &max_snoop);
1173 e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop);
1174 max_ltr_enc = E1000_MAX(max_snoop, max_nosnoop);
1176 if (lat_enc > max_ltr_enc) {
1177 lat_enc = max_ltr_enc;
1178 lat_ns = e1000_ltr2ns(max_ltr_enc);
1182 lat_ns *= speed * 1000;
1184 lat_ns /= 1000000000;
1185 obff_hwm = (s32)(rxa - lat_ns);
1187 if ((obff_hwm < 0) || (obff_hwm > E1000_SVT_OFF_HWM_MASK)) {
1188 DEBUGOUT1("Invalid high water mark %d\n", obff_hwm);
1189 return -E1000_ERR_CONFIG;
1193 /* Set Snoop and No-Snoop latencies the same */
1194 reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);
1195 E1000_WRITE_REG(hw, E1000_LTRV, reg);
1197 /* Set OBFF high water mark */
1198 reg = E1000_READ_REG(hw, E1000_SVT) & ~E1000_SVT_OFF_HWM_MASK;
1200 E1000_WRITE_REG(hw, E1000_SVT, reg);
1203 reg = E1000_READ_REG(hw, E1000_SVCR);
1204 reg |= E1000_SVCR_OFF_EN;
1205 /* Always unblock interrupts to the CPU even when the system is
1206 * in OBFF mode. This ensures that small round-robin traffic
1207 * (like ping) does not get dropped or experience long latency.
1209 reg |= E1000_SVCR_OFF_MASKINT;
1210 E1000_WRITE_REG(hw, E1000_SVCR, reg);
1212 return E1000_SUCCESS;
1216 * e1000_set_obff_timer_pch_lpt - Update Optimized Buffer Flush/Fill timer
1217 * @hw: pointer to the HW structure
1218 * @itr: interrupt throttling rate
1220 * Configure OBFF with the updated interrupt rate.
1222 static s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr)
1227 DEBUGFUNC("e1000_set_obff_timer_pch_lpt");
1229 /* Convert ITR value into microseconds for OBFF timer */
1230 timer = itr & E1000_ITR_MASK;
1231 timer = (timer * E1000_ITR_MULT) / 1000;
1233 if ((timer < 0) || (timer > E1000_ITR_MASK)) {
1234 DEBUGOUT1("Invalid OBFF timer %d\n", timer);
1235 return -E1000_ERR_CONFIG;
1238 svcr = E1000_READ_REG(hw, E1000_SVCR);
1239 svcr &= ~E1000_SVCR_OFF_TIMER_MASK;
1240 svcr |= timer << E1000_SVCR_OFF_TIMER_SHIFT;
1241 E1000_WRITE_REG(hw, E1000_SVCR, svcr);
1243 return E1000_SUCCESS;
1247 * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1248 * @hw: pointer to the HW structure
1249 * @to_sx: boolean indicating a system power state transition to Sx
1251 * When link is down, configure ULP mode to significantly reduce the power
1252 * to the PHY. If on a Manageability Engine (ME) enabled system, tell the
1253 * ME firmware to start the ULP configuration. If not on an ME enabled
1254 * system, configure the ULP mode by software.
1256 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1259 s32 ret_val = E1000_SUCCESS;
1263 if ((hw->mac.type < e1000_pch_lpt) ||
1264 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1265 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1266 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1267 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1268 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1271 if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1272 /* Request ME configure ULP mode in the PHY */
1273 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1274 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1275 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1283 /* Poll up to 5 seconds for Cable Disconnected indication */
1284 while (!(E1000_READ_REG(hw, E1000_FEXT) &
1285 E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1286 /* Bail if link is re-acquired */
1287 if (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)
1288 return -E1000_ERR_PHY;
1295 DEBUGOUT2("CABLE_DISCONNECTED %s set after %dmsec\n",
1296 (E1000_READ_REG(hw, E1000_FEXT) &
1297 E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not",
1301 ret_val = hw->phy.ops.acquire(hw);
1305 /* Force SMBus mode in PHY */
1306 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1309 phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1310 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1312 /* Force SMBus mode in MAC */
1313 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1314 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1315 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1317 /* Si workaround for ULP entry flow on i127/rev6 h/w. Enable
1318 * LPLU and disable Gig speed when entering ULP
1320 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) {
1321 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
1327 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS;
1329 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1336 /* Set Inband ULP Exit, Reset to SMBus mode and
1337 * Disable SMBus Release on PERST# in PHY
1339 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1342 phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1343 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1345 if (E1000_READ_REG(hw, E1000_WUFC) & E1000_WUFC_LNKC)
1346 phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1348 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1350 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1351 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT;
1353 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1354 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP;
1355 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1357 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1359 /* Set Disable SMBus Release on PERST# in MAC */
1360 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1361 mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1362 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1364 /* Commit ULP changes in PHY by starting auto ULP configuration */
1365 phy_reg |= I218_ULP_CONFIG1_START;
1366 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1368 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&
1369 to_sx && (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1370 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1377 hw->phy.ops.release(hw);
1380 DEBUGOUT1("Error in ULP enable flow: %d\n", ret_val);
1382 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1388 * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1389 * @hw: pointer to the HW structure
1390 * @force: boolean indicating whether or not to force disabling ULP
1392 * Un-configure ULP mode when link is up, the system is transitioned from
1393 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled
1394 * system, poll for an indication from ME that ULP has been un-configured.
1395 * If not on an ME enabled system, un-configure the ULP mode by software.
1397 * During nominal operation, this function is called when link is acquired
1398 * to disable ULP mode (force=FALSE); otherwise, for example when unloading
1399 * the driver or during Sx->S0 transitions, this is called with force=TRUE
1400 * to forcibly disable ULP.
1402 s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1404 s32 ret_val = E1000_SUCCESS;
1409 if ((hw->mac.type < e1000_pch_lpt) ||
1410 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1411 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1412 (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1413 (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1414 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1417 if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1419 /* Request ME un-configure ULP mode in the PHY */
1420 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1421 mac_reg &= ~E1000_H2ME_ULP;
1422 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1423 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1426 /* Poll up to 300msec for ME to clear ULP_CFG_DONE. */
1427 while (E1000_READ_REG(hw, E1000_FWSM) &
1428 E1000_FWSM_ULP_CFG_DONE) {
1430 ret_val = -E1000_ERR_PHY;
1436 DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1439 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1440 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1441 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1443 /* Clear H2ME.ULP after ME ULP configuration */
1444 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1445 mac_reg &= ~E1000_H2ME_ULP;
1446 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1452 ret_val = hw->phy.ops.acquire(hw);
1457 /* Toggle LANPHYPC Value bit */
1458 e1000_toggle_lanphypc_pch_lpt(hw);
1460 /* Unforce SMBus mode in PHY */
1461 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1463 /* The MAC might be in PCIe mode, so temporarily force to
1464 * SMBus mode in order to access the PHY.
1466 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1467 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1468 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1472 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1477 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1478 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1480 /* Unforce SMBus mode in MAC */
1481 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1482 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1483 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1485 /* When ULP mode was previously entered, K1 was disabled by the
1486 * hardware. Re-Enable K1 in the PHY when exiting ULP.
1488 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1491 phy_reg |= HV_PM_CTRL_K1_ENABLE;
1492 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1494 /* Clear ULP enabled configuration */
1495 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1498 phy_reg &= ~(I218_ULP_CONFIG1_IND |
1499 I218_ULP_CONFIG1_STICKY_ULP |
1500 I218_ULP_CONFIG1_RESET_TO_SMBUS |
1501 I218_ULP_CONFIG1_WOL_HOST |
1502 I218_ULP_CONFIG1_INBAND_EXIT |
1503 I218_ULP_CONFIG1_EN_ULP_LANPHYPC |
1504 I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST |
1505 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1506 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1508 /* Commit ULP changes by starting auto ULP configuration */
1509 phy_reg |= I218_ULP_CONFIG1_START;
1510 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1512 /* Clear Disable SMBus Release on PERST# in MAC */
1513 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1514 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1515 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1518 hw->phy.ops.release(hw);
1520 hw->phy.ops.reset(hw);
1525 DEBUGOUT1("Error in ULP disable flow: %d\n", ret_val);
1527 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1533 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1534 * @hw: pointer to the HW structure
1536 * Checks to see of the link status of the hardware has changed. If a
1537 * change in link status has been detected, then we read the PHY registers
1538 * to get the current speed/duplex if link exists.
1540 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1542 struct e1000_mac_info *mac = &hw->mac;
1543 s32 ret_val, tipg_reg = 0;
1544 u16 emi_addr, emi_val = 0;
1548 DEBUGFUNC("e1000_check_for_copper_link_ich8lan");
1550 /* We only want to go out to the PHY registers to see if Auto-Neg
1551 * has completed and/or if our link status has changed. The
1552 * get_link_status flag is set upon receiving a Link Status
1553 * Change or Rx Sequence Error interrupt.
1555 if (!mac->get_link_status)
1556 return E1000_SUCCESS;
1558 /* First we want to see if the MII Status Register reports
1559 * link. If so, then we want to get the current speed/duplex
1562 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1566 if (hw->mac.type == e1000_pchlan) {
1567 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1572 /* When connected at 10Mbps half-duplex, some parts are excessively
1573 * aggressive resulting in many collisions. To avoid this, increase
1574 * the IPG and reduce Rx latency in the PHY.
1576 if (((hw->mac.type == e1000_pch2lan) ||
1577 (hw->mac.type == e1000_pch_lpt) ||
1578 (hw->mac.type == e1000_pch_spt)) && link) {
1581 e1000_get_speed_and_duplex_copper_generic(hw, &speed, &duplex);
1582 tipg_reg = E1000_READ_REG(hw, E1000_TIPG);
1583 tipg_reg &= ~E1000_TIPG_IPGT_MASK;
1585 if (duplex == HALF_DUPLEX && speed == SPEED_10) {
1587 /* Reduce Rx latency in analog PHY */
1589 } else if (hw->mac.type == e1000_pch_spt &&
1590 duplex == FULL_DUPLEX && speed != SPEED_1000) {
1594 /* Roll back the default values */
1599 E1000_WRITE_REG(hw, E1000_TIPG, tipg_reg);
1601 ret_val = hw->phy.ops.acquire(hw);
1605 if (hw->mac.type == e1000_pch2lan)
1606 emi_addr = I82579_RX_CONFIG;
1608 emi_addr = I217_RX_CONFIG;
1609 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
1611 if (hw->mac.type == e1000_pch_lpt ||
1612 hw->mac.type == e1000_pch_spt) {
1615 hw->phy.ops.read_reg_locked(hw, I217_PLL_CLOCK_GATE_REG,
1617 phy_reg &= ~I217_PLL_CLOCK_GATE_MASK;
1618 if (speed == SPEED_100 || speed == SPEED_10)
1622 hw->phy.ops.write_reg_locked(hw,
1623 I217_PLL_CLOCK_GATE_REG,
1626 hw->phy.ops.release(hw);
1631 if (hw->mac.type == e1000_pch_spt) {
1635 if (speed == SPEED_1000) {
1636 ret_val = hw->phy.ops.acquire(hw);
1640 ret_val = hw->phy.ops.read_reg_locked(hw,
1644 hw->phy.ops.release(hw);
1648 ptr_gap = (data & (0x3FF << 2)) >> 2;
1649 if (ptr_gap < 0x18) {
1650 data &= ~(0x3FF << 2);
1651 data |= (0x18 << 2);
1653 hw->phy.ops.write_reg_locked(hw,
1654 PHY_REG(776, 20), data);
1656 hw->phy.ops.release(hw);
1660 ret_val = hw->phy.ops.acquire(hw);
1664 ret_val = hw->phy.ops.write_reg_locked(hw,
1667 hw->phy.ops.release(hw);
1675 /* I217 Packet Loss issue:
1676 * ensure that FEXTNVM4 Beacon Duration is set correctly
1678 * Set the Beacon Duration for I217 to 8 usec
1680 if ((hw->mac.type == e1000_pch_lpt) ||
1681 (hw->mac.type == e1000_pch_spt)) {
1684 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
1685 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1686 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1687 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
1690 /* Work-around I218 hang issue */
1691 if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1692 (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1693 (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) ||
1694 (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) {
1695 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1699 if ((hw->mac.type == e1000_pch_lpt) ||
1700 (hw->mac.type == e1000_pch_spt)) {
1701 /* Set platform power management values for
1702 * Latency Tolerance Reporting (LTR)
1703 * Optimized Buffer Flush/Fill (OBFF)
1705 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1710 /* Clear link partner's EEE ability */
1711 hw->dev_spec.ich8lan.eee_lp_ability = 0;
1713 /* FEXTNVM6 K1-off workaround */
1714 if (hw->mac.type == e1000_pch_spt) {
1715 u32 pcieanacfg = E1000_READ_REG(hw, E1000_PCIEANACFG);
1716 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
1718 if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE)
1719 fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE;
1721 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1723 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1727 return E1000_SUCCESS; /* No link detected */
1729 mac->get_link_status = FALSE;
1731 switch (hw->mac.type) {
1733 ret_val = e1000_k1_workaround_lv(hw);
1738 if (hw->phy.type == e1000_phy_82578) {
1739 ret_val = e1000_link_stall_workaround_hv(hw);
1744 /* Workaround for PCHx parts in half-duplex:
1745 * Set the number of preambles removed from the packet
1746 * when it is passed from the PHY to the MAC to prevent
1747 * the MAC from misinterpreting the packet type.
1749 hw->phy.ops.read_reg(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1750 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1752 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FD) !=
1754 phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1756 hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1762 /* Check if there was DownShift, must be checked
1763 * immediately after link-up
1765 e1000_check_downshift_generic(hw);
1767 /* Enable/Disable EEE after link up */
1768 if (hw->phy.type > e1000_phy_82579) {
1769 ret_val = e1000_set_eee_pchlan(hw);
1774 /* If we are forcing speed/duplex, then we simply return since
1775 * we have already determined whether we have link or not.
1778 return -E1000_ERR_CONFIG;
1780 /* Auto-Neg is enabled. Auto Speed Detection takes care
1781 * of MAC speed/duplex configuration. So we only need to
1782 * configure Collision Distance in the MAC.
1784 mac->ops.config_collision_dist(hw);
1786 /* Configure Flow Control now that Auto-Neg has completed.
1787 * First, we need to restore the desired flow control
1788 * settings because we may have had to re-autoneg with a
1789 * different link partner.
1791 ret_val = e1000_config_fc_after_link_up_generic(hw);
1793 DEBUGOUT("Error configuring flow control\n");
1799 * e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers
1800 * @hw: pointer to the HW structure
1802 * Initialize family-specific function pointers for PHY, MAC, and NVM.
1804 void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
1806 DEBUGFUNC("e1000_init_function_pointers_ich8lan");
1808 hw->mac.ops.init_params = e1000_init_mac_params_ich8lan;
1809 hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;
1810 switch (hw->mac.type) {
1813 case e1000_ich10lan:
1814 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
1820 hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
1828 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1829 * @hw: pointer to the HW structure
1831 * Acquires the mutex for performing NVM operations.
1833 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
1835 DEBUGFUNC("e1000_acquire_nvm_ich8lan");
1836 return E1000_SUCCESS;
1840 * e1000_release_nvm_ich8lan - Release NVM mutex
1841 * @hw: pointer to the HW structure
1843 * Releases the mutex used while performing NVM operations.
1845 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
1847 DEBUGFUNC("e1000_release_nvm_ich8lan");
1852 * e1000_acquire_swflag_ich8lan - Acquire software control flag
1853 * @hw: pointer to the HW structure
1855 * Acquires the software control flag for performing PHY and select
1858 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1860 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1861 s32 ret_val = E1000_SUCCESS;
1863 DEBUGFUNC("e1000_acquire_swflag_ich8lan");
1866 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1867 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1875 DEBUGOUT("SW has already locked the resource.\n");
1876 ret_val = -E1000_ERR_CONFIG;
1880 timeout = SW_FLAG_TIMEOUT;
1882 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1883 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1886 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1887 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1895 DEBUGOUT2("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1896 E1000_READ_REG(hw, E1000_FWSM), extcnf_ctrl);
1897 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1898 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1899 ret_val = -E1000_ERR_CONFIG;
1908 * e1000_release_swflag_ich8lan - Release software control flag
1909 * @hw: pointer to the HW structure
1911 * Releases the software control flag for performing PHY and select
1914 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1918 DEBUGFUNC("e1000_release_swflag_ich8lan");
1920 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1922 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1923 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1924 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1926 DEBUGOUT("Semaphore unexpectedly released by sw/fw/hw\n");
1932 * e1000_check_mng_mode_ich8lan - Checks management mode
1933 * @hw: pointer to the HW structure
1935 * This checks if the adapter has any manageability enabled.
1936 * This is a function pointer entry point only called by read/write
1937 * routines for the PHY and NVM parts.
1939 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1943 DEBUGFUNC("e1000_check_mng_mode_ich8lan");
1945 fwsm = E1000_READ_REG(hw, E1000_FWSM);
1947 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1948 ((fwsm & E1000_FWSM_MODE_MASK) ==
1949 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1953 * e1000_check_mng_mode_pchlan - Checks management mode
1954 * @hw: pointer to the HW structure
1956 * This checks if the adapter has iAMT enabled.
1957 * This is a function pointer entry point only called by read/write
1958 * routines for the PHY and NVM parts.
1960 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1964 DEBUGFUNC("e1000_check_mng_mode_pchlan");
1966 fwsm = E1000_READ_REG(hw, E1000_FWSM);
1968 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1969 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1973 * e1000_rar_set_pch2lan - Set receive address register
1974 * @hw: pointer to the HW structure
1975 * @addr: pointer to the receive address
1976 * @index: receive address array register
1978 * Sets the receive address array register at index to the address passed
1979 * in by addr. For 82579, RAR[0] is the base address register that is to
1980 * contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1981 * Use SHRA[0-3] in place of those reserved for ME.
1983 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1985 u32 rar_low, rar_high;
1987 DEBUGFUNC("e1000_rar_set_pch2lan");
1989 /* HW expects these in little endian so we reverse the byte order
1990 * from network order (big endian) to little endian
1992 rar_low = ((u32) addr[0] |
1993 ((u32) addr[1] << 8) |
1994 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
1996 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
1998 /* If MAC address zero, no need to set the AV bit */
1999 if (rar_low || rar_high)
2000 rar_high |= E1000_RAH_AV;
2003 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
2004 E1000_WRITE_FLUSH(hw);
2005 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
2006 E1000_WRITE_FLUSH(hw);
2007 return E1000_SUCCESS;
2010 /* RAR[1-6] are owned by manageability. Skip those and program the
2011 * next address into the SHRA register array.
2013 if (index < (u32) (hw->mac.rar_entry_count)) {
2016 ret_val = e1000_acquire_swflag_ich8lan(hw);
2020 E1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low);
2021 E1000_WRITE_FLUSH(hw);
2022 E1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high);
2023 E1000_WRITE_FLUSH(hw);
2025 e1000_release_swflag_ich8lan(hw);
2027 /* verify the register updates */
2028 if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) &&
2029 (E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high))
2030 return E1000_SUCCESS;
2032 DEBUGOUT2("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
2033 (index - 1), E1000_READ_REG(hw, E1000_FWSM));
2037 DEBUGOUT1("Failed to write receive address at index %d\n", index);
2038 return -E1000_ERR_CONFIG;
2042 * e1000_rar_set_pch_lpt - Set receive address registers
2043 * @hw: pointer to the HW structure
2044 * @addr: pointer to the receive address
2045 * @index: receive address array register
2047 * Sets the receive address register array at index to the address passed
2048 * in by addr. For LPT, RAR[0] is the base address register that is to
2049 * contain the MAC address. SHRA[0-10] are the shared receive address
2050 * registers that are shared between the Host and manageability engine (ME).
2052 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
2054 u32 rar_low, rar_high;
2057 DEBUGFUNC("e1000_rar_set_pch_lpt");
2059 /* HW expects these in little endian so we reverse the byte order
2060 * from network order (big endian) to little endian
2062 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
2063 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
2065 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
2067 /* If MAC address zero, no need to set the AV bit */
2068 if (rar_low || rar_high)
2069 rar_high |= E1000_RAH_AV;
2072 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
2073 E1000_WRITE_FLUSH(hw);
2074 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
2075 E1000_WRITE_FLUSH(hw);
2076 return E1000_SUCCESS;
2079 /* The manageability engine (ME) can lock certain SHRAR registers that
2080 * it is using - those registers are unavailable for use.
2082 if (index < hw->mac.rar_entry_count) {
2083 wlock_mac = E1000_READ_REG(hw, E1000_FWSM) &
2084 E1000_FWSM_WLOCK_MAC_MASK;
2085 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
2087 /* Check if all SHRAR registers are locked */
2091 if ((wlock_mac == 0) || (index <= wlock_mac)) {
2094 ret_val = e1000_acquire_swflag_ich8lan(hw);
2099 E1000_WRITE_REG(hw, E1000_SHRAL_PCH_LPT(index - 1),
2101 E1000_WRITE_FLUSH(hw);
2102 E1000_WRITE_REG(hw, E1000_SHRAH_PCH_LPT(index - 1),
2104 E1000_WRITE_FLUSH(hw);
2106 e1000_release_swflag_ich8lan(hw);
2108 /* verify the register updates */
2109 if ((E1000_READ_REG(hw, E1000_SHRAL_PCH_LPT(index - 1)) == rar_low) &&
2110 (E1000_READ_REG(hw, E1000_SHRAH_PCH_LPT(index - 1)) == rar_high))
2111 return E1000_SUCCESS;
2116 DEBUGOUT1("Failed to write receive address at index %d\n", index);
2117 return -E1000_ERR_CONFIG;
2121 * e1000_update_mc_addr_list_pch2lan - Update Multicast addresses
2122 * @hw: pointer to the HW structure
2123 * @mc_addr_list: array of multicast addresses to program
2124 * @mc_addr_count: number of multicast addresses to program
2126 * Updates entire Multicast Table Array of the PCH2 MAC and PHY.
2127 * The caller must have a packed mc_addr_list of multicast addresses.
2129 static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
2137 DEBUGFUNC("e1000_update_mc_addr_list_pch2lan");
2139 e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count);
2141 ret_val = hw->phy.ops.acquire(hw);
2145 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2149 for (i = 0; i < hw->mac.mta_reg_count; i++) {
2150 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
2151 (u16)(hw->mac.mta_shadow[i] &
2153 hw->phy.ops.write_reg_page(hw, (BM_MTA(i) + 1),
2154 (u16)((hw->mac.mta_shadow[i] >> 16) &
2158 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2161 hw->phy.ops.release(hw);
2165 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
2166 * @hw: pointer to the HW structure
2168 * Checks if firmware is blocking the reset of the PHY.
2169 * This is a function pointer entry point only called by
2172 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
2175 bool blocked = FALSE;
2178 DEBUGFUNC("e1000_check_reset_block_ich8lan");
2181 fwsm = E1000_READ_REG(hw, E1000_FWSM);
2182 if (!(fwsm & E1000_ICH_FWSM_RSPCIPHY)) {
2188 } while (blocked && (i++ < 30));
2189 return blocked ? E1000_BLK_PHY_RESET : E1000_SUCCESS;
2193 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2194 * @hw: pointer to the HW structure
2196 * Assumes semaphore already acquired.
2199 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
2202 u32 strap = E1000_READ_REG(hw, E1000_STRAP);
2203 u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
2204 E1000_STRAP_SMT_FREQ_SHIFT;
2207 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
2209 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2213 phy_data &= ~HV_SMB_ADDR_MASK;
2214 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
2215 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
2217 if (hw->phy.type == e1000_phy_i217) {
2218 /* Restore SMBus frequency */
2220 phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
2221 phy_data |= (freq & (1 << 0)) <<
2222 HV_SMB_ADDR_FREQ_LOW_SHIFT;
2223 phy_data |= (freq & (1 << 1)) <<
2224 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
2226 DEBUGOUT("Unsupported SMB frequency in PHY\n");
2230 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
2234 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2235 * @hw: pointer to the HW structure
2237 * SW should configure the LCD from the NVM extended configuration region
2238 * as a workaround for certain parts.
2240 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2242 struct e1000_phy_info *phy = &hw->phy;
2243 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
2244 s32 ret_val = E1000_SUCCESS;
2245 u16 word_addr, reg_data, reg_addr, phy_page = 0;
2247 DEBUGFUNC("e1000_sw_lcd_config_ich8lan");
2249 /* Initialize the PHY from the NVM on ICH platforms. This
2250 * is needed due to an issue where the NVM configuration is
2251 * not properly autoloaded after power transitions.
2252 * Therefore, after each PHY reset, we will load the
2253 * configuration data out of the NVM manually.
2255 switch (hw->mac.type) {
2257 if (phy->type != e1000_phy_igp_3)
2260 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_AMT) ||
2261 (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) {
2262 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2270 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2276 ret_val = hw->phy.ops.acquire(hw);
2280 data = E1000_READ_REG(hw, E1000_FEXTNVM);
2281 if (!(data & sw_cfg_mask))
2284 /* Make sure HW does not configure LCD from PHY
2285 * extended configuration before SW configuration
2287 data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2288 if ((hw->mac.type < e1000_pch2lan) &&
2289 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2292 cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE);
2293 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2294 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2298 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2299 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2301 if (((hw->mac.type == e1000_pchlan) &&
2302 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2303 (hw->mac.type > e1000_pchlan)) {
2304 /* HW configures the SMBus address and LEDs when the
2305 * OEM and LCD Write Enable bits are set in the NVM.
2306 * When both NVM bits are cleared, SW will configure
2309 ret_val = e1000_write_smbus_addr(hw);
2313 data = E1000_READ_REG(hw, E1000_LEDCTL);
2314 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2320 /* Configure LCD from extended configuration region. */
2322 /* cnf_base_addr is in DWORD */
2323 word_addr = (u16)(cnf_base_addr << 1);
2325 for (i = 0; i < cnf_size; i++) {
2326 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
2331 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
2336 /* Save off the PHY page for future writes. */
2337 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2338 phy_page = reg_data;
2342 reg_addr &= PHY_REG_MASK;
2343 reg_addr |= phy_page;
2345 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
2352 hw->phy.ops.release(hw);
2357 * e1000_k1_gig_workaround_hv - K1 Si workaround
2358 * @hw: pointer to the HW structure
2359 * @link: link up bool flag
2361 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2362 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
2363 * If link is down, the function will restore the default K1 setting located
2366 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2368 s32 ret_val = E1000_SUCCESS;
2370 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2372 DEBUGFUNC("e1000_k1_gig_workaround_hv");
2374 if (hw->mac.type != e1000_pchlan)
2375 return E1000_SUCCESS;
2377 /* Wrap the whole flow with the sw flag */
2378 ret_val = hw->phy.ops.acquire(hw);
2382 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2384 if (hw->phy.type == e1000_phy_82578) {
2385 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
2390 status_reg &= (BM_CS_STATUS_LINK_UP |
2391 BM_CS_STATUS_RESOLVED |
2392 BM_CS_STATUS_SPEED_MASK);
2394 if (status_reg == (BM_CS_STATUS_LINK_UP |
2395 BM_CS_STATUS_RESOLVED |
2396 BM_CS_STATUS_SPEED_1000))
2400 if (hw->phy.type == e1000_phy_82577) {
2401 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
2406 status_reg &= (HV_M_STATUS_LINK_UP |
2407 HV_M_STATUS_AUTONEG_COMPLETE |
2408 HV_M_STATUS_SPEED_MASK);
2410 if (status_reg == (HV_M_STATUS_LINK_UP |
2411 HV_M_STATUS_AUTONEG_COMPLETE |
2412 HV_M_STATUS_SPEED_1000))
2416 /* Link stall fix for link up */
2417 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2423 /* Link stall fix for link down */
2424 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2430 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2433 hw->phy.ops.release(hw);
2439 * e1000_configure_k1_ich8lan - Configure K1 power state
2440 * @hw: pointer to the HW structure
2441 * @enable: K1 state to configure
2443 * Configure the K1 power state based on the provided parameter.
2444 * Assumes semaphore already acquired.
2446 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2448 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2456 DEBUGFUNC("e1000_configure_k1_ich8lan");
2458 ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2464 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2466 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2468 ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2474 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2475 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
2477 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2478 reg |= E1000_CTRL_FRCSPD;
2479 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2481 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2482 E1000_WRITE_FLUSH(hw);
2484 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
2485 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
2486 E1000_WRITE_FLUSH(hw);
2489 return E1000_SUCCESS;
2493 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2494 * @hw: pointer to the HW structure
2495 * @d0_state: boolean if entering d0 or d3 device state
2497 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2498 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
2499 * in NVM determines whether HW should configure LPLU and Gbe Disable.
2501 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2507 DEBUGFUNC("e1000_oem_bits_config_ich8lan");
2509 if (hw->mac.type < e1000_pchlan)
2512 ret_val = hw->phy.ops.acquire(hw);
2516 if (hw->mac.type == e1000_pchlan) {
2517 mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2518 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2522 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM);
2523 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2526 mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
2528 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
2532 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2535 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2536 oem_reg |= HV_OEM_BITS_GBE_DIS;
2538 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2539 oem_reg |= HV_OEM_BITS_LPLU;
2541 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2542 E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2543 oem_reg |= HV_OEM_BITS_GBE_DIS;
2545 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2546 E1000_PHY_CTRL_NOND0A_LPLU))
2547 oem_reg |= HV_OEM_BITS_LPLU;
2550 /* Set Restart auto-neg to activate the bits */
2551 if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2552 !hw->phy.ops.check_reset_block(hw))
2553 oem_reg |= HV_OEM_BITS_RESTART_AN;
2555 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
2558 hw->phy.ops.release(hw);
2565 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2566 * @hw: pointer to the HW structure
2568 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2573 DEBUGFUNC("e1000_set_mdio_slow_mode_hv");
2575 ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data);
2579 data |= HV_KMRN_MDIO_SLOW;
2581 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data);
2587 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2588 * done after every PHY reset.
2590 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2592 s32 ret_val = E1000_SUCCESS;
2595 DEBUGFUNC("e1000_hv_phy_workarounds_ich8lan");
2597 if (hw->mac.type != e1000_pchlan)
2598 return E1000_SUCCESS;
2600 /* Set MDIO slow mode before any other MDIO access */
2601 if (hw->phy.type == e1000_phy_82577) {
2602 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2607 if (((hw->phy.type == e1000_phy_82577) &&
2608 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2609 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2610 /* Disable generation of early preamble */
2611 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
2615 /* Preamble tuning for SSC */
2616 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA,
2622 if (hw->phy.type == e1000_phy_82578) {
2623 /* Return registers to default by doing a soft reset then
2624 * writing 0x3140 to the control register.
2626 if (hw->phy.revision < 2) {
2627 e1000_phy_sw_reset_generic(hw);
2628 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,
2634 ret_val = hw->phy.ops.acquire(hw);
2639 ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2640 hw->phy.ops.release(hw);
2644 /* Configure the K1 Si workaround during phy reset assuming there is
2645 * link so that it disables K1 if link is in 1Gbps.
2647 ret_val = e1000_k1_gig_workaround_hv(hw, TRUE);
2651 /* Workaround for link disconnects on a busy hub in half duplex */
2652 ret_val = hw->phy.ops.acquire(hw);
2655 ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2658 ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
2663 /* set MSE higher to enable link to stay up when noise is high */
2664 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2666 hw->phy.ops.release(hw);
2672 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2673 * @hw: pointer to the HW structure
2675 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2681 DEBUGFUNC("e1000_copy_rx_addrs_to_phy_ich8lan");
2683 ret_val = hw->phy.ops.acquire(hw);
2686 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2690 /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2691 for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2692 mac_reg = E1000_READ_REG(hw, E1000_RAL(i));
2693 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2694 (u16)(mac_reg & 0xFFFF));
2695 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2696 (u16)((mac_reg >> 16) & 0xFFFF));
2698 mac_reg = E1000_READ_REG(hw, E1000_RAH(i));
2699 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2700 (u16)(mac_reg & 0xFFFF));
2701 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2702 (u16)((mac_reg & E1000_RAH_AV)
2706 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2709 hw->phy.ops.release(hw);
2712 static u32 e1000_calc_rx_da_crc(u8 mac[])
2714 u32 poly = 0xEDB88320; /* Polynomial for 802.3 CRC calculation */
2715 u32 i, j, mask, crc;
2717 DEBUGFUNC("e1000_calc_rx_da_crc");
2720 for (i = 0; i < 6; i++) {
2722 for (j = 8; j > 0; j--) {
2723 mask = (crc & 1) * (-1);
2724 crc = (crc >> 1) ^ (poly & mask);
2731 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2733 * @hw: pointer to the HW structure
2734 * @enable: flag to enable/disable workaround when enabling/disabling jumbos
2736 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2738 s32 ret_val = E1000_SUCCESS;
2743 DEBUGFUNC("e1000_lv_jumbo_workaround_ich8lan");
2745 if (hw->mac.type < e1000_pch2lan)
2746 return E1000_SUCCESS;
2748 /* disable Rx path while enabling/disabling workaround */
2749 hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg);
2750 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20),
2751 phy_reg | (1 << 14));
2756 /* Write Rx addresses (rar_entry_count for RAL/H, and
2757 * SHRAL/H) and initial CRC values to the MAC
2759 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2760 u8 mac_addr[ETH_ADDR_LEN] = {0};
2761 u32 addr_high, addr_low;
2763 addr_high = E1000_READ_REG(hw, E1000_RAH(i));
2764 if (!(addr_high & E1000_RAH_AV))
2766 addr_low = E1000_READ_REG(hw, E1000_RAL(i));
2767 mac_addr[0] = (addr_low & 0xFF);
2768 mac_addr[1] = ((addr_low >> 8) & 0xFF);
2769 mac_addr[2] = ((addr_low >> 16) & 0xFF);
2770 mac_addr[3] = ((addr_low >> 24) & 0xFF);
2771 mac_addr[4] = (addr_high & 0xFF);
2772 mac_addr[5] = ((addr_high >> 8) & 0xFF);
2774 E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
2775 e1000_calc_rx_da_crc(mac_addr));
2778 /* Write Rx addresses to the PHY */
2779 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2781 /* Enable jumbo frame workaround in the MAC */
2782 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2783 mac_reg &= ~(1 << 14);
2784 mac_reg |= (7 << 15);
2785 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2787 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2788 mac_reg |= E1000_RCTL_SECRC;
2789 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2791 ret_val = e1000_read_kmrn_reg_generic(hw,
2792 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2796 ret_val = e1000_write_kmrn_reg_generic(hw,
2797 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2801 ret_val = e1000_read_kmrn_reg_generic(hw,
2802 E1000_KMRNCTRLSTA_HD_CTRL,
2806 data &= ~(0xF << 8);
2808 ret_val = e1000_write_kmrn_reg_generic(hw,
2809 E1000_KMRNCTRLSTA_HD_CTRL,
2814 /* Enable jumbo frame workaround in the PHY */
2815 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2816 data &= ~(0x7F << 5);
2817 data |= (0x37 << 5);
2818 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2821 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2823 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2826 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2827 data &= ~(0x3FF << 2);
2828 data |= (E1000_TX_PTR_GAP << 2);
2829 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2832 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100);
2835 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2836 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data |
2841 /* Write MAC register values back to h/w defaults */
2842 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2843 mac_reg &= ~(0xF << 14);
2844 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2846 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2847 mac_reg &= ~E1000_RCTL_SECRC;
2848 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2850 ret_val = e1000_read_kmrn_reg_generic(hw,
2851 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2855 ret_val = e1000_write_kmrn_reg_generic(hw,
2856 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2860 ret_val = e1000_read_kmrn_reg_generic(hw,
2861 E1000_KMRNCTRLSTA_HD_CTRL,
2865 data &= ~(0xF << 8);
2867 ret_val = e1000_write_kmrn_reg_generic(hw,
2868 E1000_KMRNCTRLSTA_HD_CTRL,
2873 /* Write PHY register values back to h/w defaults */
2874 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2875 data &= ~(0x7F << 5);
2876 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2879 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2881 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2884 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2885 data &= ~(0x3FF << 2);
2887 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2890 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00);
2893 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2894 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data &
2900 /* re-enable Rx path after enabling/disabling workaround */
2901 return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg &
2906 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2907 * done after every PHY reset.
2909 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2911 s32 ret_val = E1000_SUCCESS;
2913 DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan");
2915 if (hw->mac.type != e1000_pch2lan)
2916 return E1000_SUCCESS;
2918 /* Set MDIO slow mode before any other MDIO access */
2919 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2923 ret_val = hw->phy.ops.acquire(hw);
2926 /* set MSE higher to enable link to stay up when noise is high */
2927 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2930 /* drop link after 5 times MSE threshold was reached */
2931 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2933 hw->phy.ops.release(hw);
2939 * e1000_k1_gig_workaround_lv - K1 Si workaround
2940 * @hw: pointer to the HW structure
2942 * Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2943 * Disable K1 for 1000 and 100 speeds
2945 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2947 s32 ret_val = E1000_SUCCESS;
2950 DEBUGFUNC("e1000_k1_workaround_lv");
2952 if (hw->mac.type != e1000_pch2lan)
2953 return E1000_SUCCESS;
2955 /* Set K1 beacon duration based on 10Mbs speed */
2956 ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg);
2960 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2961 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2963 (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
2966 /* LV 1G/100 Packet drop issue wa */
2967 ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL,
2971 pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
2972 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL,
2978 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
2979 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2980 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2981 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
2989 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2990 * @hw: pointer to the HW structure
2991 * @gate: boolean set to TRUE to gate, FALSE to ungate
2993 * Gate/ungate the automatic PHY configuration via hardware; perform
2994 * the configuration via software instead.
2996 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
3000 DEBUGFUNC("e1000_gate_hw_phy_config_ich8lan");
3002 if (hw->mac.type < e1000_pch2lan)
3005 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
3008 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
3010 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
3012 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
3016 * e1000_lan_init_done_ich8lan - Check for PHY config completion
3017 * @hw: pointer to the HW structure
3019 * Check the appropriate indication the MAC has finished configuring the
3020 * PHY after a software reset.
3022 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
3024 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
3026 DEBUGFUNC("e1000_lan_init_done_ich8lan");
3028 /* Wait for basic configuration completes before proceeding */
3030 data = E1000_READ_REG(hw, E1000_STATUS);
3031 data &= E1000_STATUS_LAN_INIT_DONE;
3033 } while ((!data) && --loop);
3035 /* If basic configuration is incomplete before the above loop
3036 * count reaches 0, loading the configuration from NVM will
3037 * leave the PHY in a bad state possibly resulting in no link.
3040 DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n");
3042 /* Clear the Init Done bit for the next init event */
3043 data = E1000_READ_REG(hw, E1000_STATUS);
3044 data &= ~E1000_STATUS_LAN_INIT_DONE;
3045 E1000_WRITE_REG(hw, E1000_STATUS, data);
3049 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
3050 * @hw: pointer to the HW structure
3052 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
3054 s32 ret_val = E1000_SUCCESS;
3057 DEBUGFUNC("e1000_post_phy_reset_ich8lan");
3059 if (hw->phy.ops.check_reset_block(hw))
3060 return E1000_SUCCESS;
3062 /* Allow time for h/w to get to quiescent state after reset */
3065 /* Perform any necessary post-reset workarounds */
3066 switch (hw->mac.type) {
3068 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
3073 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
3081 /* Clear the host wakeup bit after lcd reset */
3082 if (hw->mac.type >= e1000_pchlan) {
3083 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, ®);
3084 reg &= ~BM_WUC_HOST_WU_BIT;
3085 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg);
3088 /* Configure the LCD with the extended configuration region in NVM */
3089 ret_val = e1000_sw_lcd_config_ich8lan(hw);
3093 /* Configure the LCD with the OEM bits in NVM */
3094 ret_val = e1000_oem_bits_config_ich8lan(hw, TRUE);
3096 if (hw->mac.type == e1000_pch2lan) {
3097 /* Ungate automatic PHY configuration on non-managed 82579 */
3098 if (!(E1000_READ_REG(hw, E1000_FWSM) &
3099 E1000_ICH_FWSM_FW_VALID)) {
3101 e1000_gate_hw_phy_config_ich8lan(hw, FALSE);
3104 /* Set EEE LPI Update Timer to 200usec */
3105 ret_val = hw->phy.ops.acquire(hw);
3108 ret_val = e1000_write_emi_reg_locked(hw,
3109 I82579_LPI_UPDATE_TIMER,
3111 hw->phy.ops.release(hw);
3118 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
3119 * @hw: pointer to the HW structure
3122 * This is a function pointer entry point called by drivers
3123 * or other shared routines.
3125 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
3127 s32 ret_val = E1000_SUCCESS;
3129 DEBUGFUNC("e1000_phy_hw_reset_ich8lan");
3131 /* Gate automatic PHY configuration by hardware on non-managed 82579 */
3132 if ((hw->mac.type == e1000_pch2lan) &&
3133 !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
3134 e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
3136 ret_val = e1000_phy_hw_reset_generic(hw);
3140 return e1000_post_phy_reset_ich8lan(hw);
3144 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
3145 * @hw: pointer to the HW structure
3146 * @active: TRUE to enable LPLU, FALSE to disable
3148 * Sets the LPLU state according to the active flag. For PCH, if OEM write
3149 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
3150 * the phy speed. This function will manually set the LPLU bit and restart
3151 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
3152 * since it configures the same bit.
3154 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
3159 DEBUGFUNC("e1000_set_lplu_state_pchlan");
3160 ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg);
3165 oem_reg |= HV_OEM_BITS_LPLU;
3167 oem_reg &= ~HV_OEM_BITS_LPLU;
3169 if (!hw->phy.ops.check_reset_block(hw))
3170 oem_reg |= HV_OEM_BITS_RESTART_AN;
3172 return hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg);
3176 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
3177 * @hw: pointer to the HW structure
3178 * @active: TRUE to enable LPLU, FALSE to disable
3180 * Sets the LPLU D0 state according to the active flag. When
3181 * activating LPLU this function also disables smart speed
3182 * and vice versa. LPLU will not be activated unless the
3183 * device autonegotiation advertisement meets standards of
3184 * either 10 or 10/100 or 10/100/1000 at all duplexes.
3185 * This is a function pointer entry point only called by
3186 * PHY setup routines.
3188 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3190 struct e1000_phy_info *phy = &hw->phy;
3192 s32 ret_val = E1000_SUCCESS;
3195 DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan");
3197 if (phy->type == e1000_phy_ife)
3198 return E1000_SUCCESS;
3200 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3203 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
3204 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3206 if (phy->type != e1000_phy_igp_3)
3207 return E1000_SUCCESS;
3209 /* Call gig speed drop workaround on LPLU before accessing
3212 if (hw->mac.type == e1000_ich8lan)
3213 e1000_gig_downshift_workaround_ich8lan(hw);
3215 /* When LPLU is enabled, we should disable SmartSpeed */
3216 ret_val = phy->ops.read_reg(hw,
3217 IGP01E1000_PHY_PORT_CONFIG,
3221 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3222 ret_val = phy->ops.write_reg(hw,
3223 IGP01E1000_PHY_PORT_CONFIG,
3228 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
3229 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3231 if (phy->type != e1000_phy_igp_3)
3232 return E1000_SUCCESS;
3234 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3235 * during Dx states where the power conservation is most
3236 * important. During driver activity we should enable
3237 * SmartSpeed, so performance is maintained.
3239 if (phy->smart_speed == e1000_smart_speed_on) {
3240 ret_val = phy->ops.read_reg(hw,
3241 IGP01E1000_PHY_PORT_CONFIG,
3246 data |= IGP01E1000_PSCFR_SMART_SPEED;
3247 ret_val = phy->ops.write_reg(hw,
3248 IGP01E1000_PHY_PORT_CONFIG,
3252 } else if (phy->smart_speed == e1000_smart_speed_off) {
3253 ret_val = phy->ops.read_reg(hw,
3254 IGP01E1000_PHY_PORT_CONFIG,
3259 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3260 ret_val = phy->ops.write_reg(hw,
3261 IGP01E1000_PHY_PORT_CONFIG,
3268 return E1000_SUCCESS;
3272 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3273 * @hw: pointer to the HW structure
3274 * @active: TRUE to enable LPLU, FALSE to disable
3276 * Sets the LPLU D3 state according to the active flag. When
3277 * activating LPLU this function also disables smart speed
3278 * and vice versa. LPLU will not be activated unless the
3279 * device autonegotiation advertisement meets standards of
3280 * either 10 or 10/100 or 10/100/1000 at all duplexes.
3281 * This is a function pointer entry point only called by
3282 * PHY setup routines.
3284 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3286 struct e1000_phy_info *phy = &hw->phy;
3288 s32 ret_val = E1000_SUCCESS;
3291 DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan");
3293 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3296 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3297 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3299 if (phy->type != e1000_phy_igp_3)
3300 return E1000_SUCCESS;
3302 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3303 * during Dx states where the power conservation is most
3304 * important. During driver activity we should enable
3305 * SmartSpeed, so performance is maintained.
3307 if (phy->smart_speed == e1000_smart_speed_on) {
3308 ret_val = phy->ops.read_reg(hw,
3309 IGP01E1000_PHY_PORT_CONFIG,
3314 data |= IGP01E1000_PSCFR_SMART_SPEED;
3315 ret_val = phy->ops.write_reg(hw,
3316 IGP01E1000_PHY_PORT_CONFIG,
3320 } else if (phy->smart_speed == e1000_smart_speed_off) {
3321 ret_val = phy->ops.read_reg(hw,
3322 IGP01E1000_PHY_PORT_CONFIG,
3327 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3328 ret_val = phy->ops.write_reg(hw,
3329 IGP01E1000_PHY_PORT_CONFIG,
3334 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3335 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3336 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3337 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3338 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3340 if (phy->type != e1000_phy_igp_3)
3341 return E1000_SUCCESS;
3343 /* Call gig speed drop workaround on LPLU before accessing
3346 if (hw->mac.type == e1000_ich8lan)
3347 e1000_gig_downshift_workaround_ich8lan(hw);
3349 /* When LPLU is enabled, we should disable SmartSpeed */
3350 ret_val = phy->ops.read_reg(hw,
3351 IGP01E1000_PHY_PORT_CONFIG,
3356 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3357 ret_val = phy->ops.write_reg(hw,
3358 IGP01E1000_PHY_PORT_CONFIG,
3366 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3367 * @hw: pointer to the HW structure
3368 * @bank: pointer to the variable that returns the active bank
3370 * Reads signature byte from the NVM using the flash access registers.
3371 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3373 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3376 struct e1000_nvm_info *nvm = &hw->nvm;
3377 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3378 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3383 DEBUGFUNC("e1000_valid_nvm_bank_detect_ich8lan");
3385 switch (hw->mac.type) {
3387 bank1_offset = nvm->flash_bank_size;
3388 act_offset = E1000_ICH_NVM_SIG_WORD;
3390 /* set bank to 0 in case flash read fails */
3394 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,
3398 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3399 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3400 E1000_ICH_NVM_SIG_VALUE) {
3402 return E1000_SUCCESS;
3406 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset +
3411 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3412 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3413 E1000_ICH_NVM_SIG_VALUE) {
3415 return E1000_SUCCESS;
3418 DEBUGOUT("ERROR: No valid NVM bank present\n");
3419 return -E1000_ERR_NVM;
3422 eecd = E1000_READ_REG(hw, E1000_EECD);
3423 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3424 E1000_EECD_SEC1VAL_VALID_MASK) {
3425 if (eecd & E1000_EECD_SEC1VAL)
3430 return E1000_SUCCESS;
3432 DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3435 /* set bank to 0 in case flash read fails */
3439 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3443 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3444 E1000_ICH_NVM_SIG_VALUE) {
3446 return E1000_SUCCESS;
3450 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3455 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3456 E1000_ICH_NVM_SIG_VALUE) {
3458 return E1000_SUCCESS;
3461 DEBUGOUT("ERROR: No valid NVM bank present\n");
3462 return -E1000_ERR_NVM;
3467 * e1000_read_nvm_spt - NVM access for SPT
3468 * @hw: pointer to the HW structure
3469 * @offset: The offset (in bytes) of the word(s) to read.
3470 * @words: Size of data to read in words.
3471 * @data: pointer to the word(s) to read at offset.
3473 * Reads a word(s) from the NVM
3475 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
3478 struct e1000_nvm_info *nvm = &hw->nvm;
3479 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3481 s32 ret_val = E1000_SUCCESS;
3487 DEBUGFUNC("e1000_read_nvm_spt");
3489 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3491 DEBUGOUT("nvm parameter(s) out of bounds\n");
3492 ret_val = -E1000_ERR_NVM;
3496 nvm->ops.acquire(hw);
3498 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3499 if (ret_val != E1000_SUCCESS) {
3500 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3504 act_offset = (bank) ? nvm->flash_bank_size : 0;
3505 act_offset += offset;
3507 ret_val = E1000_SUCCESS;
3509 for (i = 0; i < words; i += 2) {
3510 if (words - i == 1) {
3511 if (dev_spec->shadow_ram[offset+i].modified) {
3512 data[i] = dev_spec->shadow_ram[offset+i].value;
3514 offset_to_read = act_offset + i -
3515 ((act_offset + i) % 2);
3517 e1000_read_flash_dword_ich8lan(hw,
3522 if ((act_offset + i) % 2 == 0)
3523 data[i] = (u16)(dword & 0xFFFF);
3525 data[i] = (u16)((dword >> 16) & 0xFFFF);
3528 offset_to_read = act_offset + i;
3529 if (!(dev_spec->shadow_ram[offset+i].modified) ||
3530 !(dev_spec->shadow_ram[offset+i+1].modified)) {
3532 e1000_read_flash_dword_ich8lan(hw,
3538 if (dev_spec->shadow_ram[offset+i].modified)
3539 data[i] = dev_spec->shadow_ram[offset+i].value;
3541 data[i] = (u16) (dword & 0xFFFF);
3542 if (dev_spec->shadow_ram[offset+i].modified)
3544 dev_spec->shadow_ram[offset+i+1].value;
3546 data[i+1] = (u16) (dword >> 16 & 0xFFFF);
3550 nvm->ops.release(hw);
3554 DEBUGOUT1("NVM read error: %d\n", ret_val);
3560 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
3561 * @hw: pointer to the HW structure
3562 * @offset: The offset (in bytes) of the word(s) to read.
3563 * @words: Size of data to read in words
3564 * @data: Pointer to the word(s) to read at offset.
3566 * Reads a word(s) from the NVM using the flash access registers.
3568 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3571 struct e1000_nvm_info *nvm = &hw->nvm;
3572 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3574 s32 ret_val = E1000_SUCCESS;
3578 DEBUGFUNC("e1000_read_nvm_ich8lan");
3580 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3582 DEBUGOUT("nvm parameter(s) out of bounds\n");
3583 ret_val = -E1000_ERR_NVM;
3587 nvm->ops.acquire(hw);
3589 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3590 if (ret_val != E1000_SUCCESS) {
3591 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3595 act_offset = (bank) ? nvm->flash_bank_size : 0;
3596 act_offset += offset;
3598 ret_val = E1000_SUCCESS;
3599 for (i = 0; i < words; i++) {
3600 if (dev_spec->shadow_ram[offset+i].modified) {
3601 data[i] = dev_spec->shadow_ram[offset+i].value;
3603 ret_val = e1000_read_flash_word_ich8lan(hw,
3612 nvm->ops.release(hw);
3616 DEBUGOUT1("NVM read error: %d\n", ret_val);
3622 * e1000_flash_cycle_init_ich8lan - Initialize flash
3623 * @hw: pointer to the HW structure
3625 * This function does initial flash setup so that a new read/write/erase cycle
3628 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3630 union ich8_hws_flash_status hsfsts;
3631 s32 ret_val = -E1000_ERR_NVM;
3633 DEBUGFUNC("e1000_flash_cycle_init_ich8lan");
3635 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3637 /* Check if the flash descriptor is valid */
3638 if (!hsfsts.hsf_status.fldesvalid) {
3639 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.\n");
3640 return -E1000_ERR_NVM;
3643 /* Clear FCERR and DAEL in hw status by writing 1 */
3644 hsfsts.hsf_status.flcerr = 1;
3645 hsfsts.hsf_status.dael = 1;
3646 if (hw->mac.type == e1000_pch_spt)
3647 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3648 hsfsts.regval & 0xFFFF);
3650 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3652 /* Either we should have a hardware SPI cycle in progress
3653 * bit to check against, in order to start a new cycle or
3654 * FDONE bit should be changed in the hardware so that it
3655 * is 1 after hardware reset, which can then be used as an
3656 * indication whether a cycle is in progress or has been
3660 if (!hsfsts.hsf_status.flcinprog) {
3661 /* There is no cycle running at present,
3662 * so we can start a cycle.
3663 * Begin by setting Flash Cycle Done.
3665 hsfsts.hsf_status.flcdone = 1;
3666 if (hw->mac.type == e1000_pch_spt)
3667 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3668 hsfsts.regval & 0xFFFF);
3670 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3672 ret_val = E1000_SUCCESS;
3676 /* Otherwise poll for sometime so the current
3677 * cycle has a chance to end before giving up.
3679 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3680 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3682 if (!hsfsts.hsf_status.flcinprog) {
3683 ret_val = E1000_SUCCESS;
3688 if (ret_val == E1000_SUCCESS) {
3689 /* Successful in waiting for previous cycle to timeout,
3690 * now set the Flash Cycle Done.
3692 hsfsts.hsf_status.flcdone = 1;
3693 if (hw->mac.type == e1000_pch_spt)
3694 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3695 hsfsts.regval & 0xFFFF);
3697 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3700 DEBUGOUT("Flash controller busy, cannot get access\n");
3708 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3709 * @hw: pointer to the HW structure
3710 * @timeout: maximum time to wait for completion
3712 * This function starts a flash cycle and waits for its completion.
3714 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3716 union ich8_hws_flash_ctrl hsflctl;
3717 union ich8_hws_flash_status hsfsts;
3720 DEBUGFUNC("e1000_flash_cycle_ich8lan");
3722 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3723 if (hw->mac.type == e1000_pch_spt)
3724 hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
3726 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3727 hsflctl.hsf_ctrl.flcgo = 1;
3729 if (hw->mac.type == e1000_pch_spt)
3730 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3731 hsflctl.regval << 16);
3733 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3735 /* wait till FDONE bit is set to 1 */
3737 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3738 if (hsfsts.hsf_status.flcdone)
3741 } while (i++ < timeout);
3743 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3744 return E1000_SUCCESS;
3746 return -E1000_ERR_NVM;
3750 * e1000_read_flash_dword_ich8lan - Read dword from flash
3751 * @hw: pointer to the HW structure
3752 * @offset: offset to data location
3753 * @data: pointer to the location for storing the data
3755 * Reads the flash dword at offset into data. Offset is converted
3756 * to bytes before read.
3758 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset,
3761 DEBUGFUNC("e1000_read_flash_dword_ich8lan");
3764 return -E1000_ERR_NVM;
3766 /* Must convert word offset into bytes. */
3769 return e1000_read_flash_data32_ich8lan(hw, offset, data);
3773 * e1000_read_flash_word_ich8lan - Read word from flash
3774 * @hw: pointer to the HW structure
3775 * @offset: offset to data location
3776 * @data: pointer to the location for storing the data
3778 * Reads the flash word at offset into data. Offset is converted
3779 * to bytes before read.
3781 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3784 DEBUGFUNC("e1000_read_flash_word_ich8lan");
3787 return -E1000_ERR_NVM;
3789 /* Must convert offset into bytes. */
3792 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3796 * e1000_read_flash_byte_ich8lan - Read byte from flash
3797 * @hw: pointer to the HW structure
3798 * @offset: The offset of the byte to read.
3799 * @data: Pointer to a byte to store the value read.
3801 * Reads a single byte from the NVM using the flash access registers.
3803 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3809 /* In SPT, only 32 bits access is supported,
3810 * so this function should not be called.
3812 if (hw->mac.type == e1000_pch_spt)
3813 return -E1000_ERR_NVM;
3815 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3822 return E1000_SUCCESS;
3826 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
3827 * @hw: pointer to the HW structure
3828 * @offset: The offset (in bytes) of the byte or word to read.
3829 * @size: Size of data to read, 1=byte 2=word
3830 * @data: Pointer to the word to store the value read.
3832 * Reads a byte or word from the NVM using the flash access registers.
3834 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3837 union ich8_hws_flash_status hsfsts;
3838 union ich8_hws_flash_ctrl hsflctl;
3839 u32 flash_linear_addr;
3841 s32 ret_val = -E1000_ERR_NVM;
3844 DEBUGFUNC("e1000_read_flash_data_ich8lan");
3846 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3847 return -E1000_ERR_NVM;
3848 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3849 hw->nvm.flash_base_addr);
3854 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3855 if (ret_val != E1000_SUCCESS)
3857 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3859 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3860 hsflctl.hsf_ctrl.fldbcount = size - 1;
3861 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3862 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3863 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3865 ret_val = e1000_flash_cycle_ich8lan(hw,
3866 ICH_FLASH_READ_COMMAND_TIMEOUT);
3868 /* Check if FCERR is set to 1, if set to 1, clear it
3869 * and try the whole sequence a few more times, else
3870 * read in (shift in) the Flash Data0, the order is
3871 * least significant byte first msb to lsb
3873 if (ret_val == E1000_SUCCESS) {
3874 flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
3876 *data = (u8)(flash_data & 0x000000FF);
3878 *data = (u16)(flash_data & 0x0000FFFF);
3881 /* If we've gotten here, then things are probably
3882 * completely hosed, but if the error condition is
3883 * detected, it won't hurt to give it another try...
3884 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3886 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3888 if (hsfsts.hsf_status.flcerr) {
3889 /* Repeat for some time before giving up. */
3891 } else if (!hsfsts.hsf_status.flcdone) {
3892 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3896 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3902 * e1000_read_flash_data32_ich8lan - Read dword from NVM
3903 * @hw: pointer to the HW structure
3904 * @offset: The offset (in bytes) of the dword to read.
3905 * @data: Pointer to the dword to store the value read.
3907 * Reads a byte or word from the NVM using the flash access registers.
3909 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
3912 union ich8_hws_flash_status hsfsts;
3913 union ich8_hws_flash_ctrl hsflctl;
3914 u32 flash_linear_addr;
3915 s32 ret_val = -E1000_ERR_NVM;
3918 DEBUGFUNC("e1000_read_flash_data_ich8lan");
3920 if (offset > ICH_FLASH_LINEAR_ADDR_MASK ||
3921 hw->mac.type != e1000_pch_spt)
3922 return -E1000_ERR_NVM;
3923 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3924 hw->nvm.flash_base_addr);
3929 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3930 if (ret_val != E1000_SUCCESS)
3932 /* In SPT, This register is in Lan memory space, not flash.
3933 * Therefore, only 32 bit access is supported
3935 hsflctl.regval = E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
3937 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3938 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
3939 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3940 /* In SPT, This register is in Lan memory space, not flash.
3941 * Therefore, only 32 bit access is supported
3943 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
3944 (u32)hsflctl.regval << 16);
3945 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3947 ret_val = e1000_flash_cycle_ich8lan(hw,
3948 ICH_FLASH_READ_COMMAND_TIMEOUT);
3950 /* Check if FCERR is set to 1, if set to 1, clear it
3951 * and try the whole sequence a few more times, else
3952 * read in (shift in) the Flash Data0, the order is
3953 * least significant byte first msb to lsb
3955 if (ret_val == E1000_SUCCESS) {
3956 *data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
3959 /* If we've gotten here, then things are probably
3960 * completely hosed, but if the error condition is
3961 * detected, it won't hurt to give it another try...
3962 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3964 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3966 if (hsfsts.hsf_status.flcerr) {
3967 /* Repeat for some time before giving up. */
3969 } else if (!hsfsts.hsf_status.flcdone) {
3970 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3974 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3980 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
3981 * @hw: pointer to the HW structure
3982 * @offset: The offset (in bytes) of the word(s) to write.
3983 * @words: Size of data to write in words
3984 * @data: Pointer to the word(s) to write at offset.
3986 * Writes a byte or word to the NVM using the flash access registers.
3988 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3991 struct e1000_nvm_info *nvm = &hw->nvm;
3992 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3995 DEBUGFUNC("e1000_write_nvm_ich8lan");
3997 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3999 DEBUGOUT("nvm parameter(s) out of bounds\n");
4000 return -E1000_ERR_NVM;
4003 nvm->ops.acquire(hw);
4005 for (i = 0; i < words; i++) {
4006 dev_spec->shadow_ram[offset+i].modified = TRUE;
4007 dev_spec->shadow_ram[offset+i].value = data[i];
4010 nvm->ops.release(hw);
4012 return E1000_SUCCESS;
4016 * e1000_update_nvm_checksum_spt - Update the checksum for NVM
4017 * @hw: pointer to the HW structure
4019 * The NVM checksum is updated by calling the generic update_nvm_checksum,
4020 * which writes the checksum to the shadow ram. The changes in the shadow
4021 * ram are then committed to the EEPROM by processing each bank at a time
4022 * checking for the modified bit and writing only the pending changes.
4023 * After a successful commit, the shadow ram is cleared and is ready for
4026 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)
4028 struct e1000_nvm_info *nvm = &hw->nvm;
4029 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4030 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
4034 DEBUGFUNC("e1000_update_nvm_checksum_spt");
4036 ret_val = e1000_update_nvm_checksum_generic(hw);
4040 if (nvm->type != e1000_nvm_flash_sw)
4043 nvm->ops.acquire(hw);
4045 /* We're writing to the opposite bank so if we're on bank 1,
4046 * write to bank 0 etc. We also need to erase the segment that
4047 * is going to be written
4049 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
4050 if (ret_val != E1000_SUCCESS) {
4051 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
4056 new_bank_offset = nvm->flash_bank_size;
4057 old_bank_offset = 0;
4058 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
4062 old_bank_offset = nvm->flash_bank_size;
4063 new_bank_offset = 0;
4064 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
4068 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i += 2) {
4069 /* Determine whether to write the value stored
4070 * in the other NVM bank or a modified value stored
4073 ret_val = e1000_read_flash_dword_ich8lan(hw,
4074 i + old_bank_offset,
4077 if (dev_spec->shadow_ram[i].modified) {
4078 dword &= 0xffff0000;
4079 dword |= (dev_spec->shadow_ram[i].value & 0xffff);
4081 if (dev_spec->shadow_ram[i + 1].modified) {
4082 dword &= 0x0000ffff;
4083 dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff)
4089 /* If the word is 0x13, then make sure the signature bits
4090 * (15:14) are 11b until the commit has completed.
4091 * This will allow us to write 10b which indicates the
4092 * signature is valid. We want to do this after the write
4093 * has completed so that we don't mark the segment valid
4094 * while the write is still in progress
4096 if (i == E1000_ICH_NVM_SIG_WORD - 1)
4097 dword |= E1000_ICH_NVM_SIG_MASK << 16;
4099 /* Convert offset to bytes. */
4100 act_offset = (i + new_bank_offset) << 1;
4104 /* Write the data to the new bank. Offset in words*/
4105 act_offset = i + new_bank_offset;
4106 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,
4112 /* Don't bother writing the segment valid bits if sector
4113 * programming failed.
4116 DEBUGOUT("Flash commit failed.\n");
4120 /* Finally validate the new segment by setting bit 15:14
4121 * to 10b in word 0x13 , this can be done without an
4122 * erase as well since these bits are 11 to start with
4123 * and we need to change bit 14 to 0b
4125 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4127 /*offset in words but we read dword*/
4129 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
4134 dword &= 0xBFFFFFFF;
4135 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
4140 /* And invalidate the previously valid segment by setting
4141 * its signature word (0x13) high_byte to 0b. This can be
4142 * done without an erase because flash erase sets all bits
4143 * to 1's. We can write 1's to 0's without an erase
4145 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
4147 /* offset in words but we read dword*/
4148 act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1;
4149 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
4154 dword &= 0x00FFFFFF;
4155 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
4160 /* Great! Everything worked, we can now clear the cached entries. */
4161 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4162 dev_spec->shadow_ram[i].modified = FALSE;
4163 dev_spec->shadow_ram[i].value = 0xFFFF;
4167 nvm->ops.release(hw);
4169 /* Reload the EEPROM, or else modifications will not appear
4170 * until after the next adapter reset.
4173 nvm->ops.reload(hw);
4179 DEBUGOUT1("NVM update error: %d\n", ret_val);
4185 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
4186 * @hw: pointer to the HW structure
4188 * The NVM checksum is updated by calling the generic update_nvm_checksum,
4189 * which writes the checksum to the shadow ram. The changes in the shadow
4190 * ram are then committed to the EEPROM by processing each bank at a time
4191 * checking for the modified bit and writing only the pending changes.
4192 * After a successful commit, the shadow ram is cleared and is ready for
4195 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
4197 struct e1000_nvm_info *nvm = &hw->nvm;
4198 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4199 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
4203 DEBUGFUNC("e1000_update_nvm_checksum_ich8lan");
4205 ret_val = e1000_update_nvm_checksum_generic(hw);
4209 if (nvm->type != e1000_nvm_flash_sw)
4212 nvm->ops.acquire(hw);
4214 /* We're writing to the opposite bank so if we're on bank 1,
4215 * write to bank 0 etc. We also need to erase the segment that
4216 * is going to be written
4218 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
4219 if (ret_val != E1000_SUCCESS) {
4220 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
4225 new_bank_offset = nvm->flash_bank_size;
4226 old_bank_offset = 0;
4227 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
4231 old_bank_offset = nvm->flash_bank_size;
4232 new_bank_offset = 0;
4233 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
4237 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4238 if (dev_spec->shadow_ram[i].modified) {
4239 data = dev_spec->shadow_ram[i].value;
4241 ret_val = e1000_read_flash_word_ich8lan(hw, i +
4247 /* If the word is 0x13, then make sure the signature bits
4248 * (15:14) are 11b until the commit has completed.
4249 * This will allow us to write 10b which indicates the
4250 * signature is valid. We want to do this after the write
4251 * has completed so that we don't mark the segment valid
4252 * while the write is still in progress
4254 if (i == E1000_ICH_NVM_SIG_WORD)
4255 data |= E1000_ICH_NVM_SIG_MASK;
4257 /* Convert offset to bytes. */
4258 act_offset = (i + new_bank_offset) << 1;
4262 /* Write the bytes to the new bank. */
4263 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4270 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4277 /* Don't bother writing the segment valid bits if sector
4278 * programming failed.
4281 DEBUGOUT("Flash commit failed.\n");
4285 /* Finally validate the new segment by setting bit 15:14
4286 * to 10b in word 0x13 , this can be done without an
4287 * erase as well since these bits are 11 to start with
4288 * and we need to change bit 14 to 0b
4290 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4291 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
4296 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset * 2 + 1,
4301 /* And invalidate the previously valid segment by setting
4302 * its signature word (0x13) high_byte to 0b. This can be
4303 * done without an erase because flash erase sets all bits
4304 * to 1's. We can write 1's to 0's without an erase
4306 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
4308 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
4313 /* Great! Everything worked, we can now clear the cached entries. */
4314 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4315 dev_spec->shadow_ram[i].modified = FALSE;
4316 dev_spec->shadow_ram[i].value = 0xFFFF;
4320 nvm->ops.release(hw);
4322 /* Reload the EEPROM, or else modifications will not appear
4323 * until after the next adapter reset.
4326 nvm->ops.reload(hw);
4332 DEBUGOUT1("NVM update error: %d\n", ret_val);
4338 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
4339 * @hw: pointer to the HW structure
4341 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
4342 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
4343 * calculated, in which case we need to calculate the checksum and set bit 6.
4345 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
4350 u16 valid_csum_mask;
4352 DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan");
4354 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0,
4355 * the checksum needs to be fixed. This bit is an indication that
4356 * the NVM was prepared by OEM software and did not calculate
4357 * the checksum...a likely scenario.
4359 switch (hw->mac.type) {
4363 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
4366 word = NVM_FUTURE_INIT_WORD1;
4367 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
4371 ret_val = hw->nvm.ops.read(hw, word, 1, &data);
4375 if (!(data & valid_csum_mask)) {
4376 data |= valid_csum_mask;
4377 ret_val = hw->nvm.ops.write(hw, word, 1, &data);
4380 ret_val = hw->nvm.ops.update(hw);
4385 return e1000_validate_nvm_checksum_generic(hw);
4389 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
4390 * @hw: pointer to the HW structure
4391 * @offset: The offset (in bytes) of the byte/word to read.
4392 * @size: Size of data to read, 1=byte 2=word
4393 * @data: The byte(s) to write to the NVM.
4395 * Writes one/two bytes to the NVM using the flash access registers.
4397 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
4400 union ich8_hws_flash_status hsfsts;
4401 union ich8_hws_flash_ctrl hsflctl;
4402 u32 flash_linear_addr;
4407 DEBUGFUNC("e1000_write_ich8_data");
4409 if (hw->mac.type == e1000_pch_spt) {
4410 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4411 return -E1000_ERR_NVM;
4413 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4414 return -E1000_ERR_NVM;
4417 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4418 hw->nvm.flash_base_addr);
4423 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4424 if (ret_val != E1000_SUCCESS)
4426 /* In SPT, This register is in Lan memory space, not
4427 * flash. Therefore, only 32 bit access is supported
4429 if (hw->mac.type == e1000_pch_spt)
4431 E1000_READ_FLASH_REG(hw, ICH_FLASH_HSFSTS)>>16;
4434 E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
4436 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
4437 hsflctl.hsf_ctrl.fldbcount = size - 1;
4438 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4439 /* In SPT, This register is in Lan memory space,
4440 * not flash. Therefore, only 32 bit access is
4443 if (hw->mac.type == e1000_pch_spt)
4444 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4445 hsflctl.regval << 16);
4447 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4450 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
4453 flash_data = (u32)data & 0x00FF;
4455 flash_data = (u32)data;
4457 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
4459 /* check if FCERR is set to 1 , if set to 1, clear it
4460 * and try the whole sequence a few more times else done
4463 e1000_flash_cycle_ich8lan(hw,
4464 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4465 if (ret_val == E1000_SUCCESS)
4468 /* If we're here, then things are most likely
4469 * completely hosed, but if the error condition
4470 * is detected, it won't hurt to give it another
4471 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4473 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4474 if (hsfsts.hsf_status.flcerr)
4475 /* Repeat for some time before giving up. */
4477 if (!hsfsts.hsf_status.flcdone) {
4478 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
4481 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4487 * e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM
4488 * @hw: pointer to the HW structure
4489 * @offset: The offset (in bytes) of the dwords to read.
4490 * @data: The 4 bytes to write to the NVM.
4492 * Writes one/two/four bytes to the NVM using the flash access registers.
4494 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
4497 union ich8_hws_flash_status hsfsts;
4498 union ich8_hws_flash_ctrl hsflctl;
4499 u32 flash_linear_addr;
4503 DEBUGFUNC("e1000_write_flash_data32_ich8lan");
4505 if (hw->mac.type == e1000_pch_spt) {
4506 if (offset > ICH_FLASH_LINEAR_ADDR_MASK)
4507 return -E1000_ERR_NVM;
4509 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4510 hw->nvm.flash_base_addr);
4514 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4515 if (ret_val != E1000_SUCCESS)
4518 /* In SPT, This register is in Lan memory space, not
4519 * flash. Therefore, only 32 bit access is supported
4521 if (hw->mac.type == e1000_pch_spt)
4522 hsflctl.regval = E1000_READ_FLASH_REG(hw,
4526 hsflctl.regval = E1000_READ_FLASH_REG16(hw,
4529 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
4530 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4532 /* In SPT, This register is in Lan memory space,
4533 * not flash. Therefore, only 32 bit access is
4536 if (hw->mac.type == e1000_pch_spt)
4537 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4538 hsflctl.regval << 16);
4540 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4543 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
4545 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, data);
4547 /* check if FCERR is set to 1 , if set to 1, clear it
4548 * and try the whole sequence a few more times else done
4550 ret_val = e1000_flash_cycle_ich8lan(hw,
4551 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4553 if (ret_val == E1000_SUCCESS)
4556 /* If we're here, then things are most likely
4557 * completely hosed, but if the error condition
4558 * is detected, it won't hurt to give it another
4559 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4561 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4563 if (hsfsts.hsf_status.flcerr)
4564 /* Repeat for some time before giving up. */
4566 if (!hsfsts.hsf_status.flcdone) {
4567 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
4570 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4576 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
4577 * @hw: pointer to the HW structure
4578 * @offset: The index of the byte to read.
4579 * @data: The byte to write to the NVM.
4581 * Writes a single byte to the NVM using the flash access registers.
4583 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
4586 u16 word = (u16)data;
4588 DEBUGFUNC("e1000_write_flash_byte_ich8lan");
4590 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
4594 * e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM
4595 * @hw: pointer to the HW structure
4596 * @offset: The offset of the word to write.
4597 * @dword: The dword to write to the NVM.
4599 * Writes a single dword to the NVM using the flash access registers.
4600 * Goes through a retry algorithm before giving up.
4602 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
4603 u32 offset, u32 dword)
4606 u16 program_retries;
4608 DEBUGFUNC("e1000_retry_write_flash_dword_ich8lan");
4610 /* Must convert word offset into bytes. */
4613 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4617 for (program_retries = 0; program_retries < 100; program_retries++) {
4618 DEBUGOUT2("Retrying Byte %8.8X at offset %u\n", dword, offset);
4620 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4621 if (ret_val == E1000_SUCCESS)
4624 if (program_retries == 100)
4625 return -E1000_ERR_NVM;
4627 return E1000_SUCCESS;
4631 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
4632 * @hw: pointer to the HW structure
4633 * @offset: The offset of the byte to write.
4634 * @byte: The byte to write to the NVM.
4636 * Writes a single byte to the NVM using the flash access registers.
4637 * Goes through a retry algorithm before giving up.
4639 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
4640 u32 offset, u8 byte)
4643 u16 program_retries;
4645 DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan");
4647 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4651 for (program_retries = 0; program_retries < 100; program_retries++) {
4652 DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset);
4654 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4655 if (ret_val == E1000_SUCCESS)
4658 if (program_retries == 100)
4659 return -E1000_ERR_NVM;
4661 return E1000_SUCCESS;
4665 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
4666 * @hw: pointer to the HW structure
4667 * @bank: 0 for first bank, 1 for second bank, etc.
4669 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
4670 * bank N is 4096 * N + flash_reg_addr.
4672 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
4674 struct e1000_nvm_info *nvm = &hw->nvm;
4675 union ich8_hws_flash_status hsfsts;
4676 union ich8_hws_flash_ctrl hsflctl;
4677 u32 flash_linear_addr;
4678 /* bank size is in 16bit words - adjust to bytes */
4679 u32 flash_bank_size = nvm->flash_bank_size * 2;
4682 s32 j, iteration, sector_size;
4684 DEBUGFUNC("e1000_erase_flash_bank_ich8lan");
4686 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
4688 /* Determine HW Sector size: Read BERASE bits of hw flash status
4690 * 00: The Hw sector is 256 bytes, hence we need to erase 16
4691 * consecutive sectors. The start index for the nth Hw sector
4692 * can be calculated as = bank * 4096 + n * 256
4693 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
4694 * The start index for the nth Hw sector can be calculated
4696 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
4697 * (ich9 only, otherwise error condition)
4698 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
4700 switch (hsfsts.hsf_status.berasesz) {
4702 /* Hw sector size 256 */
4703 sector_size = ICH_FLASH_SEG_SIZE_256;
4704 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
4707 sector_size = ICH_FLASH_SEG_SIZE_4K;
4711 sector_size = ICH_FLASH_SEG_SIZE_8K;
4715 sector_size = ICH_FLASH_SEG_SIZE_64K;
4719 return -E1000_ERR_NVM;
4722 /* Start with the base address, then add the sector offset. */
4723 flash_linear_addr = hw->nvm.flash_base_addr;
4724 flash_linear_addr += (bank) ? flash_bank_size : 0;
4726 for (j = 0; j < iteration; j++) {
4728 u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
4731 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4735 /* Write a value 11 (block Erase) in Flash
4736 * Cycle field in hw flash control
4738 if (hw->mac.type == e1000_pch_spt)
4740 E1000_READ_FLASH_REG(hw,
4741 ICH_FLASH_HSFSTS)>>16;
4744 E1000_READ_FLASH_REG16(hw,
4747 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
4748 if (hw->mac.type == e1000_pch_spt)
4749 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_HSFSTS,
4750 hsflctl.regval << 16);
4752 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4755 /* Write the last 24 bits of an index within the
4756 * block into Flash Linear address field in Flash
4759 flash_linear_addr += (j * sector_size);
4760 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR,
4763 ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4764 if (ret_val == E1000_SUCCESS)
4767 /* Check if FCERR is set to 1. If 1,
4768 * clear it and try the whole sequence
4769 * a few more times else Done
4771 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
4773 if (hsfsts.hsf_status.flcerr)
4774 /* repeat for some time before giving up */
4776 else if (!hsfsts.hsf_status.flcdone)
4778 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
4781 return E1000_SUCCESS;
4785 * e1000_valid_led_default_ich8lan - Set the default LED settings
4786 * @hw: pointer to the HW structure
4787 * @data: Pointer to the LED settings
4789 * Reads the LED default settings from the NVM to data. If the NVM LED
4790 * settings is all 0's or F's, set the LED default to a valid LED default
4793 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
4797 DEBUGFUNC("e1000_valid_led_default_ich8lan");
4799 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
4801 DEBUGOUT("NVM Read Error\n");
4805 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
4806 *data = ID_LED_DEFAULT_ICH8LAN;
4808 return E1000_SUCCESS;
4812 * e1000_id_led_init_pchlan - store LED configurations
4813 * @hw: pointer to the HW structure
4815 * PCH does not control LEDs via the LEDCTL register, rather it uses
4816 * the PHY LED configuration register.
4818 * PCH also does not have an "always on" or "always off" mode which
4819 * complicates the ID feature. Instead of using the "on" mode to indicate
4820 * in ledctl_mode2 the LEDs to use for ID (see e1000_id_led_init_generic()),
4821 * use "link_up" mode. The LEDs will still ID on request if there is no
4822 * link based on logic in e1000_led_[on|off]_pchlan().
4824 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4826 struct e1000_mac_info *mac = &hw->mac;
4828 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
4829 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
4830 u16 data, i, temp, shift;
4832 DEBUGFUNC("e1000_id_led_init_pchlan");
4834 /* Get default ID LED modes */
4835 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4839 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
4840 mac->ledctl_mode1 = mac->ledctl_default;
4841 mac->ledctl_mode2 = mac->ledctl_default;
4843 for (i = 0; i < 4; i++) {
4844 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
4847 case ID_LED_ON1_DEF2:
4848 case ID_LED_ON1_ON2:
4849 case ID_LED_ON1_OFF2:
4850 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4851 mac->ledctl_mode1 |= (ledctl_on << shift);
4853 case ID_LED_OFF1_DEF2:
4854 case ID_LED_OFF1_ON2:
4855 case ID_LED_OFF1_OFF2:
4856 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4857 mac->ledctl_mode1 |= (ledctl_off << shift);
4864 case ID_LED_DEF1_ON2:
4865 case ID_LED_ON1_ON2:
4866 case ID_LED_OFF1_ON2:
4867 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4868 mac->ledctl_mode2 |= (ledctl_on << shift);
4870 case ID_LED_DEF1_OFF2:
4871 case ID_LED_ON1_OFF2:
4872 case ID_LED_OFF1_OFF2:
4873 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4874 mac->ledctl_mode2 |= (ledctl_off << shift);
4882 return E1000_SUCCESS;
4886 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4887 * @hw: pointer to the HW structure
4889 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4890 * register, so the the bus width is hard coded.
4892 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4894 struct e1000_bus_info *bus = &hw->bus;
4897 DEBUGFUNC("e1000_get_bus_info_ich8lan");
4899 ret_val = e1000_get_bus_info_pcie_generic(hw);
4901 /* ICH devices are "PCI Express"-ish. They have
4902 * a configuration space, but do not contain
4903 * PCI Express Capability registers, so bus width
4904 * must be hardcoded.
4906 if (bus->width == e1000_bus_width_unknown)
4907 bus->width = e1000_bus_width_pcie_x1;
4913 * e1000_reset_hw_ich8lan - Reset the hardware
4914 * @hw: pointer to the HW structure
4916 * Does a full reset of the hardware which includes a reset of the PHY and
4919 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4921 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4926 DEBUGFUNC("e1000_reset_hw_ich8lan");
4928 /* Prevent the PCI-E bus from sticking if there is no TLP connection
4929 * on the last TLP read/write transaction when MAC is reset.
4931 ret_val = e1000_disable_pcie_master_generic(hw);
4933 DEBUGOUT("PCI-E Master disable polling has failed.\n");
4935 DEBUGOUT("Masking off all interrupts\n");
4936 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
4938 /* Disable the Transmit and Receive units. Then delay to allow
4939 * any pending transactions to complete before we hit the MAC
4940 * with the global reset.
4942 E1000_WRITE_REG(hw, E1000_RCTL, 0);
4943 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
4944 E1000_WRITE_FLUSH(hw);
4948 /* Workaround for ICH8 bit corruption issue in FIFO memory */
4949 if (hw->mac.type == e1000_ich8lan) {
4950 /* Set Tx and Rx buffer allocation to 8k apiece. */
4951 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K);
4952 /* Set Packet Buffer Size to 16k. */
4953 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K);
4956 if (hw->mac.type == e1000_pchlan) {
4957 /* Save the NVM K1 bit setting*/
4958 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
4962 if (kum_cfg & E1000_NVM_K1_ENABLE)
4963 dev_spec->nvm_k1_enabled = TRUE;
4965 dev_spec->nvm_k1_enabled = FALSE;
4968 ctrl = E1000_READ_REG(hw, E1000_CTRL);
4970 if (!hw->phy.ops.check_reset_block(hw)) {
4971 /* Full-chip reset requires MAC and PHY reset at the same
4972 * time to make sure the interface between MAC and the
4973 * external PHY is reset.
4975 ctrl |= E1000_CTRL_PHY_RST;
4977 /* Gate automatic PHY configuration by hardware on
4980 if ((hw->mac.type == e1000_pch2lan) &&
4981 !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
4982 e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
4984 ret_val = e1000_acquire_swflag_ich8lan(hw);
4985 DEBUGOUT("Issuing a global reset to ich8lan\n");
4986 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
4987 /* cannot issue a flush here because it hangs the hardware */
4990 /* Set Phy Config Counter to 50msec */
4991 if (hw->mac.type == e1000_pch2lan) {
4992 reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
4993 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
4994 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
4995 E1000_WRITE_REG(hw, E1000_FEXTNVM3, reg);
4998 if (ctrl & E1000_CTRL_PHY_RST) {
4999 ret_val = hw->phy.ops.get_cfg_done(hw);
5003 ret_val = e1000_post_phy_reset_ich8lan(hw);
5008 /* For PCH, this write will make sure that any noise
5009 * will be detected as a CRC error and be dropped rather than show up
5010 * as a bad packet to the DMA engine.
5012 if (hw->mac.type == e1000_pchlan)
5013 E1000_WRITE_REG(hw, E1000_CRC_OFFSET, 0x65656565);
5015 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
5016 E1000_READ_REG(hw, E1000_ICR);
5018 reg = E1000_READ_REG(hw, E1000_KABGTXD);
5019 reg |= E1000_KABGTXD_BGSQLBIAS;
5020 E1000_WRITE_REG(hw, E1000_KABGTXD, reg);
5022 return E1000_SUCCESS;
5026 * e1000_init_hw_ich8lan - Initialize the hardware
5027 * @hw: pointer to the HW structure
5029 * Prepares the hardware for transmit and receive by doing the following:
5030 * - initialize hardware bits
5031 * - initialize LED identification
5032 * - setup receive address registers
5033 * - setup flow control
5034 * - setup transmit descriptors
5035 * - clear statistics
5037 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
5039 struct e1000_mac_info *mac = &hw->mac;
5040 u32 ctrl_ext, txdctl, snoop;
5044 DEBUGFUNC("e1000_init_hw_ich8lan");
5046 e1000_initialize_hw_bits_ich8lan(hw);
5048 /* Initialize identification LED */
5049 ret_val = mac->ops.id_led_init(hw);
5050 /* An error is not fatal and we should not stop init due to this */
5052 DEBUGOUT("Error initializing identification LED\n");
5054 /* Setup the receive address. */
5055 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
5057 /* Zero out the Multicast HASH table */
5058 DEBUGOUT("Zeroing the MTA\n");
5059 for (i = 0; i < mac->mta_reg_count; i++)
5060 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
5062 /* The 82578 Rx buffer will stall if wakeup is enabled in host and
5063 * the ME. Disable wakeup by clearing the host wakeup bit.
5064 * Reset the phy after disabling host wakeup to reset the Rx buffer.
5066 if (hw->phy.type == e1000_phy_82578) {
5067 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &i);
5068 i &= ~BM_WUC_HOST_WU_BIT;
5069 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, i);
5070 ret_val = e1000_phy_hw_reset_ich8lan(hw);
5075 /* Setup link and flow control */
5076 ret_val = mac->ops.setup_link(hw);
5078 /* Set the transmit descriptor write-back policy for both queues */
5079 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
5080 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
5081 E1000_TXDCTL_FULL_TX_DESC_WB);
5082 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
5083 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
5084 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
5085 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1));
5086 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
5087 E1000_TXDCTL_FULL_TX_DESC_WB);
5088 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
5089 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
5090 E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl);
5092 /* ICH8 has opposite polarity of no_snoop bits.
5093 * By default, we should use snoop behavior.
5095 if (mac->type == e1000_ich8lan)
5096 snoop = PCIE_ICH8_SNOOP_ALL;
5098 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
5099 e1000_set_pcie_no_snoop_generic(hw, snoop);
5101 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
5102 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
5103 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
5105 /* Clear all of the statistics registers (clear on read). It is
5106 * important that we do this after we have tried to establish link
5107 * because the symbol error count will increment wildly if there
5110 e1000_clear_hw_cntrs_ich8lan(hw);
5116 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
5117 * @hw: pointer to the HW structure
5119 * Sets/Clears required hardware bits necessary for correctly setting up the
5120 * hardware for transmit and receive.
5122 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
5126 DEBUGFUNC("e1000_initialize_hw_bits_ich8lan");
5128 /* Extended Device Control */
5129 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
5131 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
5132 if (hw->mac.type >= e1000_pchlan)
5133 reg |= E1000_CTRL_EXT_PHYPDEN;
5134 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
5136 /* Transmit Descriptor Control 0 */
5137 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
5139 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
5141 /* Transmit Descriptor Control 1 */
5142 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
5144 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
5146 /* Transmit Arbitration Control 0 */
5147 reg = E1000_READ_REG(hw, E1000_TARC(0));
5148 if (hw->mac.type == e1000_ich8lan)
5149 reg |= (1 << 28) | (1 << 29);
5150 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
5151 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
5153 /* Transmit Arbitration Control 1 */
5154 reg = E1000_READ_REG(hw, E1000_TARC(1));
5155 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
5159 reg |= (1 << 24) | (1 << 26) | (1 << 30);
5160 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
5163 if (hw->mac.type == e1000_ich8lan) {
5164 reg = E1000_READ_REG(hw, E1000_STATUS);
5166 E1000_WRITE_REG(hw, E1000_STATUS, reg);
5169 /* work-around descriptor data corruption issue during nfs v2 udp
5170 * traffic, just disable the nfs filtering capability
5172 reg = E1000_READ_REG(hw, E1000_RFCTL);
5173 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
5175 /* Disable IPv6 extension header parsing because some malformed
5176 * IPv6 headers can hang the Rx.
5178 if (hw->mac.type == e1000_ich8lan)
5179 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
5180 E1000_WRITE_REG(hw, E1000_RFCTL, reg);
5182 /* Enable ECC on Lynxpoint */
5183 if ((hw->mac.type == e1000_pch_lpt) ||
5184 (hw->mac.type == e1000_pch_spt)) {
5185 reg = E1000_READ_REG(hw, E1000_PBECCSTS);
5186 reg |= E1000_PBECCSTS_ECC_ENABLE;
5187 E1000_WRITE_REG(hw, E1000_PBECCSTS, reg);
5189 reg = E1000_READ_REG(hw, E1000_CTRL);
5190 reg |= E1000_CTRL_MEHE;
5191 E1000_WRITE_REG(hw, E1000_CTRL, reg);
5198 * e1000_setup_link_ich8lan - Setup flow control and link settings
5199 * @hw: pointer to the HW structure
5201 * Determines which flow control settings to use, then configures flow
5202 * control. Calls the appropriate media-specific link configuration
5203 * function. Assuming the adapter has a valid link partner, a valid link
5204 * should be established. Assumes the hardware has previously been reset
5205 * and the transmitter and receiver are not enabled.
5207 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
5211 DEBUGFUNC("e1000_setup_link_ich8lan");
5213 if (hw->phy.ops.check_reset_block(hw))
5214 return E1000_SUCCESS;
5216 /* ICH parts do not have a word in the NVM to determine
5217 * the default flow control setting, so we explicitly
5220 if (hw->fc.requested_mode == e1000_fc_default)
5221 hw->fc.requested_mode = e1000_fc_full;
5223 /* Save off the requested flow control mode for use later. Depending
5224 * on the link partner's capabilities, we may or may not use this mode.
5226 hw->fc.current_mode = hw->fc.requested_mode;
5228 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
5229 hw->fc.current_mode);
5231 /* Continue to configure the copper link. */
5232 ret_val = hw->mac.ops.setup_physical_interface(hw);
5236 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
5237 if ((hw->phy.type == e1000_phy_82578) ||
5238 (hw->phy.type == e1000_phy_82579) ||
5239 (hw->phy.type == e1000_phy_i217) ||
5240 (hw->phy.type == e1000_phy_82577)) {
5241 E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time);
5243 ret_val = hw->phy.ops.write_reg(hw,
5244 PHY_REG(BM_PORT_CTRL_PAGE, 27),
5250 return e1000_set_fc_watermarks_generic(hw);
5254 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
5255 * @hw: pointer to the HW structure
5257 * Configures the kumeran interface to the PHY to wait the appropriate time
5258 * when polling the PHY, then call the generic setup_copper_link to finish
5259 * configuring the copper link.
5261 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
5267 DEBUGFUNC("e1000_setup_copper_link_ich8lan");
5269 ctrl = E1000_READ_REG(hw, E1000_CTRL);
5270 ctrl |= E1000_CTRL_SLU;
5271 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5272 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5274 /* Set the mac to wait the maximum time between each iteration
5275 * and increase the max iterations when polling the phy;
5276 * this fixes erroneous timeouts at 10Mbps.
5278 ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS,
5282 ret_val = e1000_read_kmrn_reg_generic(hw,
5283 E1000_KMRNCTRLSTA_INBAND_PARAM,
5288 ret_val = e1000_write_kmrn_reg_generic(hw,
5289 E1000_KMRNCTRLSTA_INBAND_PARAM,
5294 switch (hw->phy.type) {
5295 case e1000_phy_igp_3:
5296 ret_val = e1000_copper_link_setup_igp(hw);
5301 case e1000_phy_82578:
5302 ret_val = e1000_copper_link_setup_m88(hw);
5306 case e1000_phy_82577:
5307 case e1000_phy_82579:
5308 ret_val = e1000_copper_link_setup_82577(hw);
5313 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
5318 reg_data &= ~IFE_PMC_AUTO_MDIX;
5320 switch (hw->phy.mdix) {
5322 reg_data &= ~IFE_PMC_FORCE_MDIX;
5325 reg_data |= IFE_PMC_FORCE_MDIX;
5329 reg_data |= IFE_PMC_AUTO_MDIX;
5332 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
5341 return e1000_setup_copper_link_generic(hw);
5345 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
5346 * @hw: pointer to the HW structure
5348 * Calls the PHY specific link setup function and then calls the
5349 * generic setup_copper_link to finish configuring the link for
5350 * Lynxpoint PCH devices
5352 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
5357 DEBUGFUNC("e1000_setup_copper_link_pch_lpt");
5359 ctrl = E1000_READ_REG(hw, E1000_CTRL);
5360 ctrl |= E1000_CTRL_SLU;
5361 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5362 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
5364 ret_val = e1000_copper_link_setup_82577(hw);
5368 return e1000_setup_copper_link_generic(hw);
5372 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
5373 * @hw: pointer to the HW structure
5374 * @speed: pointer to store current link speed
5375 * @duplex: pointer to store the current link duplex
5377 * Calls the generic get_speed_and_duplex to retrieve the current link
5378 * information and then calls the Kumeran lock loss workaround for links at
5381 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
5386 DEBUGFUNC("e1000_get_link_up_info_ich8lan");
5388 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
5392 if ((hw->mac.type == e1000_ich8lan) &&
5393 (hw->phy.type == e1000_phy_igp_3) &&
5394 (*speed == SPEED_1000)) {
5395 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
5402 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
5403 * @hw: pointer to the HW structure
5405 * Work-around for 82566 Kumeran PCS lock loss:
5406 * On link status change (i.e. PCI reset, speed change) and link is up and
5408 * 0) if workaround is optionally disabled do nothing
5409 * 1) wait 1ms for Kumeran link to come up
5410 * 2) check Kumeran Diagnostic register PCS lock loss bit
5411 * 3) if not set the link is locked (all is good), otherwise...
5413 * 5) repeat up to 10 times
5414 * Note: this is only called for IGP3 copper when speed is 1gb.
5416 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
5418 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5424 DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan");
5426 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
5427 return E1000_SUCCESS;
5429 /* Make sure link is up before proceeding. If not just return.
5430 * Attempting this while link is negotiating fouled up link
5433 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
5435 return E1000_SUCCESS;
5437 for (i = 0; i < 10; i++) {
5438 /* read once to clear */
5439 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
5442 /* and again to get new status */
5443 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
5447 /* check for PCS lock */
5448 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
5449 return E1000_SUCCESS;
5451 /* Issue PHY reset */
5452 hw->phy.ops.reset(hw);
5455 /* Disable GigE link negotiation */
5456 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
5457 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
5458 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5459 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
5461 /* Call gig speed drop workaround on Gig disable before accessing
5464 e1000_gig_downshift_workaround_ich8lan(hw);
5466 /* unable to acquire PCS lock */
5467 return -E1000_ERR_PHY;
5471 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
5472 * @hw: pointer to the HW structure
5473 * @state: boolean value used to set the current Kumeran workaround state
5475 * If ICH8, set the current Kumeran workaround state (enabled - TRUE
5476 * /disabled - FALSE).
5478 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
5481 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5483 DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan");
5485 if (hw->mac.type != e1000_ich8lan) {
5486 DEBUGOUT("Workaround applies to ICH8 only.\n");
5490 dev_spec->kmrn_lock_loss_workaround_enabled = state;
5496 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
5497 * @hw: pointer to the HW structure
5499 * Workaround for 82566 power-down on D3 entry:
5500 * 1) disable gigabit link
5501 * 2) write VR power-down enable
5503 * Continue if successful, else issue LCD reset and repeat
5505 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
5511 DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan");
5513 if (hw->phy.type != e1000_phy_igp_3)
5516 /* Try the workaround twice (if needed) */
5519 reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
5520 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
5521 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5522 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);
5524 /* Call gig speed drop workaround on Gig disable before
5525 * accessing any PHY registers
5527 if (hw->mac.type == e1000_ich8lan)
5528 e1000_gig_downshift_workaround_ich8lan(hw);
5530 /* Write VR power-down enable */
5531 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
5532 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5533 hw->phy.ops.write_reg(hw, IGP3_VR_CTRL,
5534 data | IGP3_VR_CTRL_MODE_SHUTDOWN);
5536 /* Read it back and test */
5537 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
5538 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5539 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
5542 /* Issue PHY reset and repeat at most one more time */
5543 reg = E1000_READ_REG(hw, E1000_CTRL);
5544 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST);
5550 * e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working
5551 * @hw: pointer to the HW structure
5553 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
5554 * LPLU, Gig disable, MDIC PHY reset):
5555 * 1) Set Kumeran Near-end loopback
5556 * 2) Clear Kumeran Near-end loopback
5557 * Should only be called for ICH8[m] devices with any 1G Phy.
5559 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
5564 DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan");
5566 if ((hw->mac.type != e1000_ich8lan) ||
5567 (hw->phy.type == e1000_phy_ife))
5570 ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5574 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
5575 ret_val = e1000_write_kmrn_reg_generic(hw,
5576 E1000_KMRNCTRLSTA_DIAG_OFFSET,
5580 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
5581 e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5586 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
5587 * @hw: pointer to the HW structure
5589 * During S0 to Sx transition, it is possible the link remains at gig
5590 * instead of negotiating to a lower speed. Before going to Sx, set
5591 * 'Gig Disable' to force link speed negotiation to a lower speed based on
5592 * the LPLU setting in the NVM or custom setting. For PCH and newer parts,
5593 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
5594 * needs to be written.
5595 * Parts that support (and are linked to a partner which support) EEE in
5596 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
5597 * than 10Mbps w/o EEE.
5599 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
5601 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5605 DEBUGFUNC("e1000_suspend_workarounds_ich8lan");
5607 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
5608 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
5610 if (hw->phy.type == e1000_phy_i217) {
5611 u16 phy_reg, device_id = hw->device_id;
5613 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
5614 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
5615 (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
5616 (device_id == E1000_DEV_ID_PCH_I218_V3) ||
5617 (hw->mac.type == e1000_pch_spt)) {
5618 u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
5620 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
5621 fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
5624 ret_val = hw->phy.ops.acquire(hw);
5628 if (!dev_spec->eee_disable) {
5632 e1000_read_emi_reg_locked(hw,
5633 I217_EEE_ADVERTISEMENT,
5638 /* Disable LPLU if both link partners support 100BaseT
5639 * EEE and 100Full is advertised on both ends of the
5640 * link, and enable Auto Enable LPI since there will
5641 * be no driver to enable LPI while in Sx.
5643 if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
5644 (dev_spec->eee_lp_ability &
5645 I82579_EEE_100_SUPPORTED) &&
5646 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
5647 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
5648 E1000_PHY_CTRL_NOND0A_LPLU);
5650 /* Set Auto Enable LPI after link up */
5651 hw->phy.ops.read_reg_locked(hw,
5654 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5655 hw->phy.ops.write_reg_locked(hw,
5661 /* For i217 Intel Rapid Start Technology support,
5662 * when the system is going into Sx and no manageability engine
5663 * is present, the driver must configure proxy to reset only on
5664 * power good. LPI (Low Power Idle) state must also reset only
5665 * on power good, as well as the MTA (Multicast table array).
5666 * The SMBus release must also be disabled on LCD reset.
5668 if (!(E1000_READ_REG(hw, E1000_FWSM) &
5669 E1000_ICH_FWSM_FW_VALID)) {
5670 /* Enable proxy to reset only on power good. */
5671 hw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL,
5673 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
5674 hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL,
5677 /* Set bit enable LPI (EEE) to reset only on
5680 hw->phy.ops.read_reg_locked(hw, I217_SxCTRL, &phy_reg);
5681 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
5682 hw->phy.ops.write_reg_locked(hw, I217_SxCTRL, phy_reg);
5684 /* Disable the SMB release on LCD reset. */
5685 hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, &phy_reg);
5686 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
5687 hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
5690 /* Enable MTA to reset for Intel Rapid Start Technology
5693 hw->phy.ops.read_reg_locked(hw, I217_CGFREG, &phy_reg);
5694 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
5695 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
5698 hw->phy.ops.release(hw);
5701 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
5703 if (hw->mac.type == e1000_ich8lan)
5704 e1000_gig_downshift_workaround_ich8lan(hw);
5706 if (hw->mac.type >= e1000_pchlan) {
5707 e1000_oem_bits_config_ich8lan(hw, FALSE);
5709 /* Reset PHY to activate OEM bits on 82577/8 */
5710 if (hw->mac.type == e1000_pchlan)
5711 e1000_phy_hw_reset_generic(hw);
5713 ret_val = hw->phy.ops.acquire(hw);
5716 e1000_write_smbus_addr(hw);
5717 hw->phy.ops.release(hw);
5724 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
5725 * @hw: pointer to the HW structure
5727 * During Sx to S0 transitions on non-managed devices or managed devices
5728 * on which PHY resets are not blocked, if the PHY registers cannot be
5729 * accessed properly by the s/w toggle the LANPHYPC value to power cycle
5731 * On i217, setup Intel Rapid Start Technology.
5733 u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
5737 DEBUGFUNC("e1000_resume_workarounds_pchlan");
5738 if (hw->mac.type < e1000_pch2lan)
5739 return E1000_SUCCESS;
5741 ret_val = e1000_init_phy_workarounds_pchlan(hw);
5743 DEBUGOUT1("Failed to init PHY flow ret_val=%d\n", ret_val);
5747 /* For i217 Intel Rapid Start Technology support when the system
5748 * is transitioning from Sx and no manageability engine is present
5749 * configure SMBus to restore on reset, disable proxy, and enable
5750 * the reset on MTA (Multicast table array).
5752 if (hw->phy.type == e1000_phy_i217) {
5755 ret_val = hw->phy.ops.acquire(hw);
5757 DEBUGOUT("Failed to setup iRST\n");
5761 /* Clear Auto Enable LPI after link up */
5762 hw->phy.ops.read_reg_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5763 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5764 hw->phy.ops.write_reg_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5766 if (!(E1000_READ_REG(hw, E1000_FWSM) &
5767 E1000_ICH_FWSM_FW_VALID)) {
5768 /* Restore clear on SMB if no manageability engine
5771 ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR,
5775 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
5776 hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
5779 hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 0);
5781 /* Enable reset on MTA */
5782 ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG,
5786 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
5787 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
5790 DEBUGOUT1("Error %d in resume workarounds\n", ret_val);
5791 hw->phy.ops.release(hw);
5794 return E1000_SUCCESS;
5798 * e1000_cleanup_led_ich8lan - Restore the default LED operation
5799 * @hw: pointer to the HW structure
5801 * Return the LED back to the default configuration.
5803 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
5805 DEBUGFUNC("e1000_cleanup_led_ich8lan");
5807 if (hw->phy.type == e1000_phy_ife)
5808 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5811 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
5812 return E1000_SUCCESS;
5816 * e1000_led_on_ich8lan - Turn LEDs on
5817 * @hw: pointer to the HW structure
5821 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5823 DEBUGFUNC("e1000_led_on_ich8lan");
5825 if (hw->phy.type == e1000_phy_ife)
5826 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5827 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
5829 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
5830 return E1000_SUCCESS;
5834 * e1000_led_off_ich8lan - Turn LEDs off
5835 * @hw: pointer to the HW structure
5837 * Turn off the LEDs.
5839 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5841 DEBUGFUNC("e1000_led_off_ich8lan");
5843 if (hw->phy.type == e1000_phy_ife)
5844 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5845 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
5847 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
5848 return E1000_SUCCESS;
5852 * e1000_setup_led_pchlan - Configures SW controllable LED
5853 * @hw: pointer to the HW structure
5855 * This prepares the SW controllable LED for use.
5857 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5859 DEBUGFUNC("e1000_setup_led_pchlan");
5861 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5862 (u16)hw->mac.ledctl_mode1);
5866 * e1000_cleanup_led_pchlan - Restore the default LED operation
5867 * @hw: pointer to the HW structure
5869 * Return the LED back to the default configuration.
5871 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5873 DEBUGFUNC("e1000_cleanup_led_pchlan");
5875 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5876 (u16)hw->mac.ledctl_default);
5880 * e1000_led_on_pchlan - Turn LEDs on
5881 * @hw: pointer to the HW structure
5885 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5887 u16 data = (u16)hw->mac.ledctl_mode2;
5890 DEBUGFUNC("e1000_led_on_pchlan");
5892 /* If no link, then turn LED on by setting the invert bit
5893 * for each LED that's mode is "link_up" in ledctl_mode2.
5895 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5896 for (i = 0; i < 3; i++) {
5897 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5898 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5899 E1000_LEDCTL_MODE_LINK_UP)
5901 if (led & E1000_PHY_LED0_IVRT)
5902 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5904 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5908 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5912 * e1000_led_off_pchlan - Turn LEDs off
5913 * @hw: pointer to the HW structure
5915 * Turn off the LEDs.
5917 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5919 u16 data = (u16)hw->mac.ledctl_mode1;
5922 DEBUGFUNC("e1000_led_off_pchlan");
5924 /* If no link, then turn LED off by clearing the invert bit
5925 * for each LED that's mode is "link_up" in ledctl_mode1.
5927 if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5928 for (i = 0; i < 3; i++) {
5929 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5930 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5931 E1000_LEDCTL_MODE_LINK_UP)
5933 if (led & E1000_PHY_LED0_IVRT)
5934 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5936 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5940 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5944 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5945 * @hw: pointer to the HW structure
5947 * Read appropriate register for the config done bit for completion status
5948 * and configure the PHY through s/w for EEPROM-less parts.
5950 * NOTE: some silicon which is EEPROM-less will fail trying to read the
5951 * config done bit, so only an error is logged and continues. If we were
5952 * to return with error, EEPROM-less silicon would not be able to be reset
5955 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
5957 s32 ret_val = E1000_SUCCESS;
5961 DEBUGFUNC("e1000_get_cfg_done_ich8lan");
5963 e1000_get_cfg_done_generic(hw);
5965 /* Wait for indication from h/w that it has completed basic config */
5966 if (hw->mac.type >= e1000_ich10lan) {
5967 e1000_lan_init_done_ich8lan(hw);
5969 ret_val = e1000_get_auto_rd_done_generic(hw);
5971 /* When auto config read does not complete, do not
5972 * return with an error. This can happen in situations
5973 * where there is no eeprom and prevents getting link.
5975 DEBUGOUT("Auto Read Done did not complete\n");
5976 ret_val = E1000_SUCCESS;
5980 /* Clear PHY Reset Asserted bit */
5981 status = E1000_READ_REG(hw, E1000_STATUS);
5982 if (status & E1000_STATUS_PHYRA)
5983 E1000_WRITE_REG(hw, E1000_STATUS, status & ~E1000_STATUS_PHYRA);
5985 DEBUGOUT("PHY Reset Asserted not set - needs delay\n");
5987 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
5988 if (hw->mac.type <= e1000_ich9lan) {
5989 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
5990 (hw->phy.type == e1000_phy_igp_3)) {
5991 e1000_phy_init_script_igp3(hw);
5994 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
5995 /* Maybe we should do a basic PHY config */
5996 DEBUGOUT("EEPROM not present\n");
5997 ret_val = -E1000_ERR_CONFIG;
6005 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
6006 * @hw: pointer to the HW structure
6008 * In the case of a PHY power down to save power, or to turn off link during a
6009 * driver unload, or wake on lan is not enabled, remove the link.
6011 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
6013 /* If the management interface is not enabled, then power down */
6014 if (!(hw->mac.ops.check_mng_mode(hw) ||
6015 hw->phy.ops.check_reset_block(hw)))
6016 e1000_power_down_phy_copper(hw);
6022 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
6023 * @hw: pointer to the HW structure
6025 * Clears hardware counters specific to the silicon family and calls
6026 * clear_hw_cntrs_generic to clear all general purpose counters.
6028 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
6033 DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan");
6035 e1000_clear_hw_cntrs_base_generic(hw);
6037 E1000_READ_REG(hw, E1000_ALGNERRC);
6038 E1000_READ_REG(hw, E1000_RXERRC);
6039 E1000_READ_REG(hw, E1000_TNCRS);
6040 E1000_READ_REG(hw, E1000_CEXTERR);
6041 E1000_READ_REG(hw, E1000_TSCTC);
6042 E1000_READ_REG(hw, E1000_TSCTFC);
6044 E1000_READ_REG(hw, E1000_MGTPRC);
6045 E1000_READ_REG(hw, E1000_MGTPDC);
6046 E1000_READ_REG(hw, E1000_MGTPTC);
6048 E1000_READ_REG(hw, E1000_IAC);
6049 E1000_READ_REG(hw, E1000_ICRXOC);
6051 /* Clear PHY statistics registers */
6052 if ((hw->phy.type == e1000_phy_82578) ||
6053 (hw->phy.type == e1000_phy_82579) ||
6054 (hw->phy.type == e1000_phy_i217) ||
6055 (hw->phy.type == e1000_phy_82577)) {
6056 ret_val = hw->phy.ops.acquire(hw);
6059 ret_val = hw->phy.ops.set_page(hw,
6060 HV_STATS_PAGE << IGP_PAGE_SHIFT);
6063 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
6064 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
6065 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
6066 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
6067 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
6068 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
6069 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
6070 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
6071 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
6072 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
6073 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
6074 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
6075 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
6076 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
6078 hw->phy.ops.release(hw);