2 * Copyright (c) 2007 The DragonFly Project. All rights reserved.
4 * This code is derived from software contributed to The DragonFly Project
5 * by Sepherosa Ziehau <sepherosa@gmail.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * $DragonFly: src/sys/dev/netif/bwi/if_bwivar.h,v 1.9 2007/10/03 04:53:19 sephe Exp $
40 #define BWI_ALIGN 0x1000
41 #define BWI_RING_ALIGN BWI_ALIGN
42 #define BWI_BUS_SPACE_MAXADDR 0x3fffffff
44 #define BWI_TX_NRING 6
45 #define BWI_TXRX_NRING 6
46 #define BWI_TX_NDESC 128
47 #define BWI_RX_NDESC 64
48 #define BWI_TXSTATS_NDESC 64
49 #define BWI_TX_NSPRDESC 2
50 #define BWI_TX_DATA_RING 1
52 /* XXX Onoe/Sample/AMRR probably need different configuration */
55 #define BWI_SHRETRY_FB 3
56 #define BWI_LGRETRY_FB 2
58 #define BWI_NOISE_FLOOR -95 /* TODO: noise floor calc */
59 #define BWI_FRAME_MIN_LEN(hdr) \
60 ((hdr) + sizeof(struct ieee80211_frame_ack) + IEEE80211_CRC_LEN)
62 #define CSR_READ_4(sc, reg) \
63 bus_space_read_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg))
64 #define CSR_READ_2(sc, reg) \
65 bus_space_read_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg))
67 #define CSR_WRITE_4(sc, reg, val) \
68 bus_space_write_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))
69 #define CSR_WRITE_2(sc, reg, val) \
70 bus_space_write_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))
72 #define CSR_SETBITS_4(sc, reg, bits) \
73 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) | (bits))
74 #define CSR_SETBITS_2(sc, reg, bits) \
75 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (bits))
77 #define CSR_FILT_SETBITS_4(sc, reg, filt, bits) \
78 CSR_WRITE_4((sc), (reg), (CSR_READ_4((sc), (reg)) & (filt)) | (bits))
79 #define CSR_FILT_SETBITS_2(sc, reg, filt, bits) \
80 CSR_WRITE_2((sc), (reg), (CSR_READ_2((sc), (reg)) & (filt)) | (bits))
82 #define CSR_CLRBITS_4(sc, reg, bits) \
83 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) & ~(bits))
84 #define CSR_CLRBITS_2(sc, reg, bits) \
85 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(bits))
90 #define DPRINTF(sc, dbg, fmt, ...) \
92 if ((sc)->sc_debug & (dbg)) \
93 if_printf(&(sc)->sc_ic.ic_if, fmt, __VA_ARGS__); \
96 #define _DPRINTF(sc, dbg, fmt, ...) \
98 if ((sc)->sc_debug & (dbg)) \
99 kprintf(fmt, __VA_ARGS__); \
102 #else /* !BWI_DEBUG */
104 #define DPRINTF(sc, dbg, fmt, ...) ((void)0)
105 #define _DPRINTF(sc, dbg, fmt, ...) ((void)0)
107 #endif /* BWI_DEBUG */
112 uint32_t addr; /* BWI_DESC32_A_ */
115 #define BWI_DESC32_A_FUNC_TXRX 0x1
116 #define BWI_DESC32_A_FUNC_MASK __BITS(31, 30)
117 #define BWI_DESC32_A_ADDR_MASK __BITS(29, 0)
119 #define BWI_DESC32_C_BUFLEN_MASK __BITS(12, 0)
120 #define BWI_DESC32_C_ADDRHI_MASK __BITS(17, 16)
121 #define BWI_DESC32_C_EOR __BIT(28)
122 #define BWI_DESC32_C_INTR __BIT(29)
123 #define BWI_DESC32_C_FRAME_END __BIT(30)
124 #define BWI_DESC32_C_FRAME_START __BIT(31)
134 struct bwi_rxbuf_hdr {
136 uint16_t rxh_buflen; /* exclude bwi_rxbuf_hdr */
138 uint16_t rxh_flags1; /* BWI_RXH_F1_ */
141 uint16_t rxh_phyinfo; /* BWI_RXH_PHYINFO_ */
142 uint16_t rxh_flags3; /* BWI_RXH_F3_ */
143 uint16_t rxh_flags2; /* BWI_RXH_F2_ */
145 uint8_t rxh_pad3[14]; /* Padded to 30bytes */
148 #define BWI_RXH_F1_BCM2053_RSSI __BIT(14)
149 #define BWI_RXH_F1_SHPREAMBLE __BIT(7)
150 #define BWI_RXH_F1_OFDM __BIT(0)
152 #define BWI_RXH_F2_TYPE2FRAME __BIT(2)
154 #define BWI_RXH_F3_BCM2050_RSSI __BIT(10)
156 #define BWI_RXH_PHYINFO_LNAGAIN __BITS(15, 14)
158 struct bwi_txbuf_hdr {
160 uint32_t txh_mac_ctrl; /* BWI_TXH_MAC_C_ */
162 uint16_t txh_unknown1;
163 uint16_t txh_phy_ctrl; /* BWI_TXH_PHY_C_ */
165 uint8_t txh_addr1[IEEE80211_ADDR_LEN];
166 uint16_t txh_unknown2;
167 uint8_t txh_rts_fb_plcp[4];
168 uint16_t txh_rts_fb_duration;
169 uint8_t txh_fb_plcp[4];
170 uint16_t txh_fb_duration;
172 uint16_t txh_id; /* BWI_TXH_ID_ */
173 uint16_t txh_unknown3;
174 uint8_t txh_rts_plcp[6];
175 uint8_t txh_rts_fc[2];
176 uint16_t txh_rts_duration;
177 uint8_t txh_rts_ra[IEEE80211_ADDR_LEN];
178 uint8_t txh_rts_ta[IEEE80211_ADDR_LEN];
183 #define BWI_TXH_ID_RING_MASK __BITS(15, 13)
184 #define BWI_TXH_ID_IDX_MASK __BITS(12, 0)
186 #define BWI_TXH_PHY_C_OFDM __BIT(0)
187 #define BWI_TXH_PHY_C_SHPREAMBLE __BIT(4)
188 #define BWI_TXH_PHY_C_ANTMODE_MASK __BITS(9, 8)
190 #define BWI_TXH_MAC_C_ACK __BIT(0)
191 #define BWI_TXH_MAC_C_FIRST_FRAG __BIT(3)
192 #define BWI_TXH_MAC_C_HWSEQ __BIT(4)
193 #define BWI_TXH_MAC_C_FB_OFDM __BIT(8)
199 uint8_t txs_flags; /* BWI_TXS_F_ */
200 uint8_t txs_txcnt; /* BWI_TXS_TXCNT_ */
203 uint16_t txs_unknown;
204 uint8_t txs_pad3[2]; /* Padded to 16bytes */
207 #define BWI_TXS_TXCNT_DATA __BITS(7, 4)
209 #define BWI_TXS_F_ACKED __BIT(0)
210 #define BWI_TXS_F_PENDING __BIT(5)
212 struct bwi_ring_data {
213 uint32_t rdata_txrx_ctrl;
214 bus_dmamap_t rdata_dmap;
215 bus_addr_t rdata_paddr;
220 struct mbuf *tb_mbuf;
221 bus_dmamap_t tb_dmap;
223 struct ieee80211_node *tb_ni;
225 #define BWI_NTXRATE 2
227 int tb_rateidx[BWI_NTXRATE];
230 struct bwi_txbuf_data {
231 struct bwi_txbuf tbd_buf[BWI_TX_NDESC];
237 struct mbuf *rb_mbuf;
239 bus_dmamap_t rb_dmap;
242 struct bwi_rxbuf_data {
243 struct bwi_rxbuf rbd_buf[BWI_RX_NDESC];
244 bus_dmamap_t rbd_tmp_dmap;
248 struct bwi_txstats_data {
249 bus_dma_tag_t stats_ring_dtag;
250 bus_dmamap_t stats_ring_dmap;
251 bus_addr_t stats_ring_paddr;
254 bus_dma_tag_t stats_dtag;
255 bus_dmamap_t stats_dmap;
256 bus_addr_t stats_paddr;
257 struct bwi_txstats *stats;
259 uint32_t stats_ctrl_base;
265 uint8_t fw_type; /* BWI_FW_T_ */
266 uint8_t fw_gen; /* BWI_FW_GEN */
269 #define fw_iv_cnt fw_size
272 #define BWI_FWHDR_SZ sizeof(struct bwi_fwhdr)
274 #define BWI_FW_T_UCODE 'u'
275 #define BWI_FW_T_PCM 'p'
276 #define BWI_FW_T_IV 'i'
278 #define BWI_FW_GEN_1 1
280 #define BWI_FW_VERSION3 3
281 #define BWI_FW_VERSION4 4
282 #define BWI_FW_VERSION3_REVMAX 0x128
284 #define BWI_FW_PATH "bwi/v%d/"
285 #define BWI_FW_UCODE_PATH BWI_FW_PATH "ucode%d.fw"
286 #define BWI_FW_PCM_PATH BWI_FW_PATH "pcm%d.fw"
287 #define BWI_FW_IV_PATH BWI_FW_PATH "b0g0initvals%d.fw"
288 #define BWI_FW_IV_EXT_PATH BWI_FW_PATH "b0g0bsinitvals%d.fw"
299 #define BWI_FW_IV_OFS_MASK __BITS(14, 0)
300 #define BWI_FW_IV_IS_32BIT __BIT(15)
302 enum bwi_clock_mode {
309 uint32_t rw_flags; /* BWI_REGWIN_F_ */
310 uint16_t rw_type; /* BWI_REGWIN_T_ */
315 #define BWI_REGWIN_F_EXIST 0x1
317 #define BWI_CREATE_REGWIN(rw, id, type, rev) \
319 (rw)->rw_flags = BWI_REGWIN_F_EXIST; \
320 (rw)->rw_type = (type); \
321 (rw)->rw_id = (id); \
322 (rw)->rw_rev = (rev); \
325 #define BWI_REGWIN_EXIST(rw) ((rw)->rw_flags & BWI_REGWIN_F_EXIST)
326 #define BWI_GPIO_REGWIN(sc) \
327 (BWI_REGWIN_EXIST(&(sc)->sc_com_regwin) ? \
328 &(sc)->sc_com_regwin : &(sc)->sc_bus_regwin)
333 enum ieee80211_phymode phy_mode;
337 uint32_t phy_flags; /* BWI_PHY_F_ */
338 uint16_t phy_tbl_ctrl;
339 uint16_t phy_tbl_data_lo;
340 uint16_t phy_tbl_data_hi;
342 void (*phy_init)(struct bwi_mac *);
345 #define BWI_PHY_F_CALIBRATED 0x1
346 #define BWI_PHY_F_LINKED 0x2
347 #define BWI_CLEAR_PHY_FLAGS (BWI_PHY_F_CALIBRATED)
349 /* TX power control */
351 uint16_t bbp_atten; /* BBP attenuation: 4bits */
352 uint16_t rf_atten; /* RF attenuation */
353 uint16_t tp_ctrl1; /* ??: 3bits */
354 uint16_t tp_ctrl2; /* ??: 4bits */
357 #define BWI_RF_ATTEN_FACTOR 4
358 #define BWI_RF_ATTEN_MAX0 9
359 #define BWI_RF_ATTEN_MAX1 31
360 #define BWI_BBP_ATTEN_MAX 11
361 #define BWI_TPCTL1_MAX 7
369 uint16_t rf_type; /* BWI_RF_T_ */
373 uint32_t rf_flags; /* BWI_RF_F_ */
375 #define BWI_RFLO_MAX 56
376 struct bwi_rf_lo rf_lo[BWI_RFLO_MAX];
377 uint8_t rf_lo_used[8];
379 #define BWI_INVALID_NRSSI -1000
380 int16_t rf_nrssi[2]; /* Narrow RSSI */
381 int32_t rf_nrssi_slope;
383 #define BWI_NRSSI_TBLSZ 64
384 int8_t rf_nrssi_table[BWI_NRSSI_TBLSZ];
386 uint16_t rf_lo_gain; /* loopback gain */
387 uint16_t rf_rx_gain; /* TRSW RX gain */
389 uint16_t rf_calib; /* RF calibration value */
390 u_int rf_curchan; /* current channel */
394 void (*rf_off)(struct bwi_mac *);
395 void (*rf_on)(struct bwi_mac *);
397 void (*rf_set_nrssi_thr)(struct bwi_mac *);
398 void (*rf_calc_nrssi_slope)(struct bwi_mac *);
401 const struct bwi_rxbuf_hdr *);
403 void (*rf_lo_update)(struct bwi_mac *);
405 #define BWI_TSSI_MAX 64
406 int8_t rf_txpower_map0[BWI_TSSI_MAX];
407 /* Indexed by TSSI */
410 int8_t rf_txpower_map[BWI_TSSI_MAX];
415 int rf_txpower_max; /* dBm */
417 int rf_ant_mode; /* BWI_ANT_MODE_ */
420 #define BWI_RF_F_INITED 0x1
421 #define BWI_RF_F_ON 0x2
422 #define BWI_RF_CLEAR_FLAGS (BWI_RF_F_INITED)
424 #define BWI_ANT_MODE_0 0
425 #define BWI_ANT_MODE_1 1
426 #define BWI_ANT_MODE_UNKN 2
427 #define BWI_ANT_MODE_AUTO 3
433 struct bwi_regwin mac_regwin; /* MUST be first field */
434 #define mac_rw_flags mac_regwin.rw_flags
435 #define mac_type mac_regwin.rw_type
436 #define mac_id mac_regwin.rw_id
437 #define mac_rev mac_regwin.rw_rev
439 struct bwi_softc *mac_sc;
441 struct bwi_phy mac_phy; /* PHY I/F */
442 struct bwi_rf mac_rf; /* RF I/F */
444 struct bwi_tpctl mac_tpctl; /* TX power control */
445 uint32_t mac_flags; /* BWI_MAC_F_ */
447 struct fw_image *mac_ucode;
448 struct fw_image *mac_pcm;
449 struct fw_image *mac_iv;
450 struct fw_image *mac_iv_ext;
453 #define BWI_MAC_F_BSWAP 0x1
454 #define BWI_MAC_F_TPCTL_INITED 0x2
455 #define BWI_MAC_F_HAS_TXSTATS 0x4
456 #define BWI_MAC_F_INITED 0x8
457 #define BWI_MAC_F_ENABLED 0x10
458 #define BWI_MAC_F_LOCKED 0x20 /* for debug */
459 #define BWI_MAC_F_TPCTL_ERROR 0x40
461 #define BWI_CREATE_MAC(mac, sc, id, rev) \
463 BWI_CREATE_REGWIN(&(mac)->mac_regwin, \
467 (mac)->mac_sc = (sc); \
470 #define BWI_MAC_MAX 2
473 BWI_BUS_SPACE_30BIT = 1,
478 #define BWI_TX_RADIOTAP_PRESENT \
479 ((1 << IEEE80211_RADIOTAP_FLAGS) | \
480 (1 << IEEE80211_RADIOTAP_RATE) | \
481 (1 << IEEE80211_RADIOTAP_CHANNEL))
483 struct bwi_tx_radiotap_hdr {
484 struct ieee80211_radiotap_header wt_ihdr;
487 uint16_t wt_chan_freq;
488 uint16_t wt_chan_flags;
491 #define BWI_RX_RADIOTAP_PRESENT \
492 ((1 << IEEE80211_RADIOTAP_TSFT) | \
493 (1 << IEEE80211_RADIOTAP_FLAGS) | \
494 (1 << IEEE80211_RADIOTAP_RATE) | \
495 (1 << IEEE80211_RADIOTAP_CHANNEL) | \
496 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | \
497 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE))
499 struct bwi_rx_radiotap_hdr {
500 struct ieee80211_radiotap_header wr_ihdr;
504 uint16_t wr_chan_freq;
505 uint16_t wr_chan_flags;
512 struct ieee80211com sc_ic;
513 uint32_t sc_flags; /* BWI_F_ */
516 uint32_t sc_cap; /* BWI_CAP_ */
517 uint16_t sc_bbp_id; /* BWI_BBPID_ */
521 uint8_t sc_pci_revid;
522 uint16_t sc_pci_subvid;
523 uint16_t sc_pci_subdid;
525 uint16_t sc_card_flags; /* BWI_CARD_F_ */
526 uint16_t sc_pwron_delay;
530 struct resource *sc_irq_res;
534 struct resource *sc_mem_res;
535 bus_space_tag_t sc_mem_bt;
536 bus_space_handle_t sc_mem_bh;
538 struct callout sc_scan_ch;
539 struct callout sc_calib_ch;
541 struct bwi_regwin *sc_cur_regwin;
542 struct bwi_regwin sc_com_regwin;
543 struct bwi_regwin sc_bus_regwin;
546 struct bwi_mac sc_mac[BWI_MAC_MAX];
548 enum bwi_bus_space sc_bus_space;
549 bus_dma_tag_t sc_parent_dtag;
551 bus_dma_tag_t sc_buf_dtag;
552 struct bwi_txbuf_data sc_tx_bdata[BWI_TX_NRING];
553 struct bwi_rxbuf_data sc_rx_bdata;
555 bus_dma_tag_t sc_txring_dtag;
556 struct bwi_ring_data sc_tx_rdata[BWI_TX_NRING];
557 bus_dma_tag_t sc_rxring_dtag;
558 struct bwi_ring_data sc_rx_rdata;
560 struct bwi_txstats_data *sc_txstats;
564 struct bpf_if *sc_drvbpf;
567 struct bwi_tx_radiotap_hdr u_tx_th;
568 uint8_t u_pad[IEEE80211_RADIOTAP_HDRLEN];
570 #define sc_tx_th sc_u_tx_th.u_tx_th
574 struct bwi_rx_radiotap_hdr u_rx_th;
575 uint8_t u_pad[IEEE80211_RADIOTAP_HDRLEN];
577 #define sc_rx_th sc_u_rx_th.u_rx_th
581 (struct ieee80211com *,
582 enum ieee80211_state, int);
584 int (*sc_init_tx_ring)(struct bwi_softc *, int);
585 void (*sc_free_tx_ring)(struct bwi_softc *, int);
587 int (*sc_init_rx_ring)(struct bwi_softc *);
588 void (*sc_free_rx_ring)(struct bwi_softc *);
590 int (*sc_init_txstats)(struct bwi_softc *);
591 void (*sc_free_txstats)(struct bwi_softc *);
593 void (*sc_setup_rxdesc)
594 (struct bwi_softc *, int, bus_addr_t, int);
595 void (*sc_rxeof)(struct bwi_softc *);
597 void (*sc_setup_txdesc)
598 (struct bwi_softc *, struct bwi_ring_data *,
599 int, bus_addr_t, int);
601 (struct bwi_softc *, uint32_t, int);
603 void (*sc_txeof_status)(struct bwi_softc *);
605 struct sysctl_ctx_list sc_sysctl_ctx;
606 struct sysctl_oid *sc_sysctl_tree;
611 int sc_fw_version; /* BWI_FW_VERSION[34] */
612 int sc_dwell_time; /* milliseconds */
613 uint32_t sc_debug; /* BWI_DBG_ */
616 #define BWI_F_BUS_INITED 0x1
617 #define BWI_F_PROMISC 0x2
619 #define BWI_DBG_MAC 0x00000001
620 #define BWI_DBG_RF 0x00000002
621 #define BWI_DBG_PHY 0x00000004
622 #define BWI_DBG_MISC 0x00000008
624 #define BWI_DBG_ATTACH 0x00000010
625 #define BWI_DBG_INIT 0x00000020
626 #define BWI_DBG_FIRMWARE 0x00000040
627 #define BWI_DBG_80211 0x00000080
628 #define BWI_DBG_TXPOWER 0x00000100
629 #define BWI_DBG_INTR 0x00000200
630 #define BWI_DBG_RX 0x00000400
631 #define BWI_DBG_TX 0x00000800
632 #define BWI_DBG_TXEOF 0x00001000
634 uint16_t bwi_read_sprom(struct bwi_softc *, uint16_t);
635 int bwi_regwin_switch(struct bwi_softc *, struct bwi_regwin *,
636 struct bwi_regwin **);
637 int bwi_regwin_is_enabled(struct bwi_softc *, struct bwi_regwin *);
638 void bwi_regwin_enable(struct bwi_softc *, struct bwi_regwin *,
640 void bwi_regwin_disable(struct bwi_softc *, struct bwi_regwin *,
642 int bwi_bus_init(struct bwi_softc *, struct bwi_mac *);
643 uint8_t bwi_rate2plcp(uint8_t); /* XXX belongs to 802.11 */
645 #define abs(a) __builtin_abs(a)
647 #endif /* !_IF_BWIVAR_H */