sys/dev/netif/wx/if_wx.c

   1 /* $FreeBSD: src/sys/pci/if_wx.c,v 1.5.2.12 2003/03/05 18:42:34 njl Exp $ */
   2 /* $DragonFly: src/sys/dev/netif/wx/Attic/if_wx.c,v 1.12 2004/09/15 01:19:13 joerg Exp $ */
   3 /*
   4  * Principal Author: Matthew Jacob <mjacob@feral.com>
   5  * Copyright (c) 1999, 2001 by Traakan Software
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice unmodified, this list of conditions, and the following
  13  *    disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  28  * SUCH DAMAGE.
  29  *
  30  * Additional Copyright (c) 2001 by Parag Patel
  31  * under same licence for MII PHY code.
  32  */
  33
  34 /*
  35  * Intel Gigabit Ethernet (82452/82453) Driver.
  36  * Inspired by fxp driver by David Greenman for FreeBSD, and by
  37  * Bill Paul's work in other FreeBSD network drivers.
  38  */
  39
  40 /*
  41  * Many bug fixes gratefully acknowledged from:
  42  *
  43  *      The folks at Sitara Networks
  44  */
  45
  46 /*
  47  * Options
  48  */
  49
  50 /*
  51  * Use only every other 16 byte receive descriptor, leaving the ones
  52  * in between empty. This card is most efficient at reading/writing
  53  * 32 byte cache lines, so avoid all the (not working for early rev
  54  * cards) MWI and/or READ/MODIFY/WRITE cycles updating one descriptor
  55  * would have you do.
  56  *
  57  * This isn't debugged yet.
  58  */
  59 /* #define      PADDED_CELL     1 */
  60
  61 /*
  62  * Since the includes are a mess, they'll all be in if_wxvar.h
  63  */
  64
  65 #include "if_wxvar.h"
  66
  67 #ifdef __alpha__
  68 #undef vtophys
  69 #define vtophys(va)     alpha_XXX_dmamap((vm_offset_t)(va))
  70 #endif /* __alpha__ */
  71
  72 /*
  73  * Function Prototpes, yadda yadda...
  74  */
  75
  76 static int wx_intr(void *);
  77 static void wx_handle_link_intr(wx_softc_t *);
  78 static void wx_check_link(wx_softc_t *);
  79 static void wx_handle_rxint(wx_softc_t *);
  80 static void wx_gc(wx_softc_t *);
  81 static void wx_start(struct ifnet *);
  82 static int wx_ioctl(struct ifnet *, IOCTL_CMD_TYPE, caddr_t, struct ucred *);
  83 static int wx_ifmedia_upd(struct ifnet *);
  84 static void wx_ifmedia_sts(struct ifnet *, struct ifmediareq *);
  85 static int wx_init(void *);
  86 static void wx_hw_stop(wx_softc_t *);
  87 static void wx_set_addr(wx_softc_t *, int, u_int8_t *);
  88 static int wx_hw_initialize(wx_softc_t *);
  89 static void wx_stop(wx_softc_t *);
  90 static void wx_txwatchdog(struct ifnet *);
  91 static int wx_get_rbuf(wx_softc_t *, rxpkt_t *);
  92 static void wx_rxdma_map(wx_softc_t *, rxpkt_t *, struct mbuf *);
  93
  94 static INLINE void wx_eeprom_raise_clk(wx_softc_t *, u_int32_t);
  95 static INLINE void wx_eeprom_lower_clk(wx_softc_t *, u_int32_t);
  96 static INLINE void wx_eeprom_sobits(wx_softc_t *, u_int16_t, u_int16_t);
  97 static INLINE u_int16_t wx_eeprom_sibits(wx_softc_t *);
  98 static INLINE void wx_eeprom_cleanup(wx_softc_t *);
  99 static INLINE u_int16_t wx_read_eeprom_word(wx_softc_t *, int);
 100 static void wx_read_eeprom(wx_softc_t *, u_int16_t *, int, int);
 101
 102 static int wx_attach_common(wx_softc_t *);
 103 static void wx_watchdog(void *);
 104
 105 static INLINE void wx_mwi_whackon(wx_softc_t *);
 106 static INLINE void wx_mwi_unwhack(wx_softc_t *);
 107 static int wx_dring_setup(wx_softc_t *);
 108 static void wx_dring_teardown(wx_softc_t *);
 109
 110 static int wx_attach_phy(wx_softc_t *);
 111 static int wx_miibus_readreg(void *, int, int);
 112 static int wx_miibus_writereg(void *, int, int, int);
 113 static void wx_miibus_statchg(void *);
 114 static void wx_miibus_mediainit(void *);
 115
 116 static u_int32_t wx_mii_shift_in(wx_softc_t *);
 117 static void wx_mii_shift_out(wx_softc_t *, u_int32_t, u_int32_t);
 118
 119 #define WX_DISABLE_INT(sc)      WRITE_CSR(sc, WXREG_IMCLR, WXDISABLE)
 120 #define WX_ENABLE_INT(sc)       WRITE_CSR(sc, WXREG_IMASK, sc->wx_ienable)
 121
 122 /*
 123  * Until we do a bit more work, we can get no bigger than MCLBYTES
 124  */
 125 #if     0
 126 #define WX_MAXMTU       (WX_MAX_PKT_SIZE_JUMBO - sizeof (struct ether_header))
 127 #else
 128 #define WX_MAXMTU       (MCLBYTES - sizeof (struct ether_header))
 129 #endif
 130
 131 #define DPRINTF(sc, x)  if (sc->wx_debug) printf x
 132 #define IPRINTF(sc, x)  if (sc->wx_verbose) printf x
 133
 134 static const char ldn[] = "%s: link down\n";
 135 static const char lup[] = "%s: link up\n";
 136 static const char sqe[] = "%s: receive sequence error\n";
 137 static const char ane[] = "%s: /C/ ordered sets seen- enabling ANE\n";
 138 static const char inane[] = "%s: no /C/ ordered sets seen- disabling ANE\n";
 139
 140 static int wx_txint_delay = 5000;       /* ~5ms */
 141 TUNABLE_INT("hw.wx.txint_delay", &wx_txint_delay);
 142
 143 SYSCTL_NODE(_hw, OID_AUTO, wx, CTLFLAG_RD, 0, "WX driver parameters");
 144 SYSCTL_INT(_hw_wx, OID_AUTO, txint_delay, CTLFLAG_RW,
 145         &wx_txint_delay, 0, "");
 146 static int wx_dump_stats = -1;
 147 SYSCTL_INT(_hw_wx, OID_AUTO, dump_stats, CTLFLAG_RW,
 148         &wx_dump_stats, 0, "");
 149 static int wx_clr_stats = -1;
 150 SYSCTL_INT(_hw_wx, OID_AUTO, clear_stats, CTLFLAG_RW,
 151         &wx_clr_stats, 0, "");
 152
 153 /*
 154  * Program multicast addresses.
 155  *
 156  * This function must be called at splimp, but it may sleep.
 157  */
 158 static int
 159 wx_mc_setup(wx_softc_t *sc)
 160 {
 161         struct ifnet *ifp = &sc->wx_if;
 162         struct ifmultiaddr *ifma;
 163
 164         /*
 165          * XXX: drain TX queue
 166          */
 167         if (sc->tactive) {
 168                 return (EBUSY);
 169         }
 170
 171         wx_stop(sc);
 172
 173         if ((ifp->if_flags & IFF_ALLMULTI) || (ifp->if_flags & IFF_PROMISC)) {
 174                 sc->all_mcasts = 1;
 175                 return (wx_init(sc));
 176         }
 177
 178         sc->wx_nmca = 0;
 179         for (ifma = ifp->if_multiaddrs.lh_first, sc->wx_nmca = 0;
 180             ifma != NULL; ifma = ifma->ifma_link.le_next) {
 181
 182                 if (ifma->ifma_addr->sa_family != AF_LINK) {
 183                         continue;
 184                 }
 185                 if (sc->wx_nmca >= WX_RAL_TAB_SIZE-1) {
 186                         sc->wx_nmca = 0;
 187                         sc->all_mcasts = 1;
 188                         break;
 189                 }
 190                 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
 191                     (void *) &sc->wx_mcaddr[sc->wx_nmca++][0], 6);
 192         }
 193         return (wx_init(sc));
 194 }
 195
 196 /*
 197  * Return identification string if this is device is ours.
 198  */
 199 static int
 200 wx_probe(device_t dev)
 201 {
 202         if (pci_get_vendor(dev) != WX_VENDOR_INTEL) {
 203                 return (ENXIO);
 204         }
 205         switch (pci_get_device(dev)) {
 206         case WX_PRODUCT_82452:
 207                 device_set_desc(dev, "Intel PRO/1000 Gigabit (WISEMAN)");
 208                 break;
 209         case WX_PRODUCT_LIVENGOOD:
 210                 device_set_desc(dev, "Intel PRO/1000 (LIVENGOOD)");
 211                 break;
 212         case WX_PRODUCT_82452_SC:
 213                 device_set_desc(dev, "Intel PRO/1000 F Gigabit Ethernet");
 214                 break;
 215         case WX_PRODUCT_82543:
 216                 device_set_desc(dev, "Intel PRO/1000 T Gigabit Ethernet");
 217                 break;
 218         default:
 219                 return (ENXIO);
 220         }
 221         return (0);
 222 }
 223
 224 static int
 225 wx_attach(device_t dev)
 226 {
 227         int error = 0;
 228         wx_softc_t *sc = device_get_softc(dev);
 229         struct ifnet *ifp;
 230         u_int32_t val;
 231         int rid;
 232
 233         bzero(sc, sizeof (wx_softc_t));
 234
 235         callout_init(&sc->watchdog_timer);
 236         sc->w.dev = dev;
 237
 238         if (bootverbose)
 239                 sc->wx_verbose = 1;
 240
 241         if (getenv_int ("wx_debug", &rid)) {
 242                 if (rid & (1 << device_get_unit(dev))) {
 243                         sc->wx_debug = 1;
 244                 }
 245         }
 246
 247         if (getenv_int("wx_no_ilos", &rid)) {
 248                 if (rid & (1 << device_get_unit(dev))) {
 249                         sc->wx_no_ilos = 1;
 250                 }
 251         }
 252
 253         if (getenv_int("wx_ilos", &rid)) {
 254                 if (rid & (1 << device_get_unit(dev))) {
 255                         sc->wx_ilos = 1;
 256                 }
 257         }
 258
 259         if (getenv_int("wx_no_flow", &rid)) {
 260                 if (rid & (1 << device_get_unit(dev))) {
 261                         sc->wx_no_flow = 1;
 262                 }
 263         }
 264
 265 #ifdef  SMPNG
 266         mtx_init(&sc->wx_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE);
 267 #endif
 268         WX_LOCK(sc);
 269         /*
 270          * get revision && id...
 271          */
 272         sc->wx_idnrev = (pci_get_device(dev) << 16) | (pci_get_revid(dev));
 273
 274         /*
 275          * Enable bus mastering, make sure that the cache line size is right.
 276          */
 277         pci_enable_busmaster(dev);
 278         pci_enable_io(dev, SYS_RES_MEMORY);
 279         val = pci_read_config(dev, PCIR_COMMAND, 4);
 280         if ((val & PCIM_CMD_MEMEN) == 0) {
 281                 device_printf(dev, "failed to enable memory mapping\n");
 282                 error = ENXIO;
 283                 goto out;
 284         }
 285
 286         /*
 287          * Let the BIOS do it's job- but check for sanity.
 288          */
 289         val = pci_read_config(dev, PCIR_CACHELNSZ, 1);
 290         if (val < 4 || val > 32) {
 291                 pci_write_config(dev, PCIR_CACHELNSZ, 8, 1);
 292         }
 293
 294         /*
 295          * Map control/status registers.
 296          */
 297         rid = WX_MMBA;
 298         sc->w.mem = bus_alloc_resource(dev, SYS_RES_MEMORY,
 299             &rid, 0, ~0, 1, RF_ACTIVE);
 300         if (!sc->w.mem) {
 301                 device_printf(dev, "could not map memory\n");
 302                 error = ENXIO;
 303                 goto out;
 304         }
 305         sc->w.st = rman_get_bustag(sc->w.mem);
 306         sc->w.sh = rman_get_bushandle(sc->w.mem);
 307
 308         rid = 0;
 309         sc->w.irq = bus_alloc_resource(dev, SYS_RES_IRQ,
 310             &rid, 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE);
 311         if (sc->w.irq == NULL) {
 312                 device_printf(dev, "could not map interrupt\n");
 313                 error = ENXIO;
 314                 goto out;
 315         }
 316         error = bus_setup_intr(dev, sc->w.irq, INTR_TYPE_NET,
 317             (void (*)(void *))wx_intr, sc, &sc->w.ih);
 318         if (error) {
 319                 device_printf(dev, "could not setup irq\n");
 320                 goto out;
 321         }
 322         (void) snprintf(sc->wx_name, sizeof (sc->wx_name) - 1, "wx%d",
 323             device_get_unit(dev));
 324         if (wx_attach_common(sc)) {
 325                 bus_teardown_intr(dev, sc->w.irq, sc->w.ih);
 326                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->w.irq);
 327                 bus_release_resource(dev, SYS_RES_MEMORY, WX_MMBA, sc->w.mem);
 328                 error = ENXIO;
 329                 goto out;
 330         }
 331
 332         ifp = &sc->w.arpcom.ac_if;
 333         if_initname(ifp, "wx", device_get_unit(dev));
 334         ifp->if_mtu = ETHERMTU; /* we always start at ETHERMTU size */
 335         ifp->if_baudrate = 1000000000;
 336         ifp->if_init = (void (*)(void *))wx_init;
 337         ifp->if_softc = sc;
 338         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 339         ifp->if_ioctl = wx_ioctl;
 340         ifp->if_start = wx_start;
 341         ifp->if_watchdog = wx_txwatchdog;
 342         ifp->if_snd.ifq_maxlen = WX_MAX_TDESC - 1;
 343         ether_ifattach(ifp, sc->w.arpcom.ac_enaddr);
 344 out:
 345         WX_UNLOCK(sc);
 346         return (error);
 347 }
 348
 349 static int
 350 wx_attach_phy(wx_softc_t *sc)
 351 {
 352         if (mii_phy_probe(sc->w.dev, &sc->w.miibus, wx_ifmedia_upd,
 353             wx_ifmedia_sts)) {
 354                 printf("%s: no PHY probed!\n", sc->wx_name);
 355                 return (-1);
 356         }
 357         sc->wx_mii = 1;
 358         return 0;
 359 }
 360
 361 static int
 362 wx_detach(device_t dev)
 363 {
 364         wx_softc_t *sc = device_get_softc(dev);
 365
 366         WX_LOCK(sc);
 367         wx_stop(sc);
 368
 369         ether_ifdetach(&sc->w.arpcom.ac_if);
 370         if (sc->w.miibus) {
 371                 bus_generic_detach(dev);
 372                 device_delete_child(dev, sc->w.miibus);
 373         } else {
 374                 ifmedia_removeall(&sc->wx_media);
 375         }
 376         bus_teardown_intr(dev, sc->w.irq, sc->w.ih);
 377         bus_release_resource(dev, SYS_RES_IRQ, 0, sc->w.irq);
 378         bus_release_resource(dev, SYS_RES_MEMORY, WX_MMBA, sc->w.mem);
 379
 380         wx_dring_teardown(sc);
 381         if (sc->rbase) {
 382                 WXFREE(sc->rbase);
 383                 sc->rbase = NULL;
 384         }
 385         if (sc->tbase) {
 386                 WXFREE(sc->tbase);
 387                 sc->tbase = NULL;
 388         }
 389         WX_UNLOCK(sc);
 390 #ifdef  SMPNG
 391         mtx_destroy(&sc->wx_mtx);
 392 #endif
 393         return (0);
 394 }
 395
 396 static int
 397 wx_shutdown(device_t dev)
 398 {
 399         wx_hw_stop((wx_softc_t *) device_get_softc(dev));
 400         return (0);
 401 }
 402
 403 static INLINE void
 404 wx_mwi_whackon(wx_softc_t *sc)
 405 {
 406         sc->wx_cmdw = pci_read_config(sc->w.dev, PCIR_COMMAND, 2);
 407         pci_write_config(sc->w.dev, PCIR_COMMAND, sc->wx_cmdw & ~MWI, 2);
 408 }
 409
 410 static INLINE void
 411 wx_mwi_unwhack(wx_softc_t *sc)
 412 {
 413         if (sc->wx_cmdw & MWI) {
 414                 pci_write_config(sc->w.dev, PCIR_COMMAND, sc->wx_cmdw, 2);
 415         }
 416 }
 417
 418 static int
 419 wx_dring_setup(wx_softc_t *sc)
 420 {
 421         size_t len;
 422
 423         len = sizeof (wxrd_t) * WX_MAX_RDESC;
 424         sc->rdescriptors = (wxrd_t *)
 425             contigmalloc(len, M_DEVBUF, M_NOWAIT, 0, ~0, 4096, 0);
 426         if (sc->rdescriptors == NULL) {
 427                 printf("%s: could not allocate rcv descriptors\n", sc->wx_name);
 428                 return (-1);
 429         }
 430         if (((intptr_t)sc->rdescriptors) & 0xfff) {
 431                 contigfree(sc->rdescriptors, len, M_DEVBUF);
 432                 sc->rdescriptors = NULL;
 433                 printf("%s: rcv descriptors not 4KB aligned\n", sc->wx_name);
 434                 return (-1);
 435         }
 436         bzero(sc->rdescriptors, len);
 437
 438         len = sizeof (wxtd_t) * WX_MAX_TDESC;
 439         sc->tdescriptors = (wxtd_t *)
 440             contigmalloc(len, M_DEVBUF, M_NOWAIT, 0, ~0, 4096, 0);
 441         if (sc->tdescriptors == NULL) {
 442                 contigfree(sc->rdescriptors,
 443                     sizeof (wxrd_t) * WX_MAX_RDESC, M_DEVBUF);
 444                 sc->rdescriptors = NULL;
 445                 printf("%s: could not allocate xmt descriptors\n", sc->wx_name);
 446                 return (-1);
 447         }
 448         if (((intptr_t)sc->tdescriptors) & 0xfff) {
 449                 contigfree(sc->rdescriptors,
 450                     sizeof (wxrd_t) * WX_MAX_RDESC, M_DEVBUF);
 451                 contigfree(sc->tdescriptors, len, M_DEVBUF);
 452                 sc->rdescriptors = NULL;
 453                 sc->tdescriptors = NULL;
 454                 printf("%s: xmt descriptors not 4KB aligned\n", sc->wx_name);
 455                 return (-1);
 456         }
 457         bzero(sc->tdescriptors, len);
 458         return (0);
 459 }
 460
 461 static void
 462 wx_dring_teardown(wx_softc_t *sc)
 463 {
 464         if (sc->rdescriptors) {
 465                 contigfree(sc->rdescriptors,
 466                     sizeof (wxrd_t) * WX_MAX_RDESC, M_DEVBUF);
 467                 sc->rdescriptors = NULL;
 468         }
 469         if (sc->tdescriptors) {
 470                 contigfree(sc->tdescriptors,
 471                     sizeof (wxtd_t) * WX_MAX_TDESC, M_DEVBUF);
 472                 sc->tdescriptors = NULL;
 473         }
 474 }
 475
 476 static device_method_t wx_methods[] = {
 477         /* Device interface */
 478         DEVMETHOD(device_probe,         wx_probe),
 479         DEVMETHOD(device_attach,        wx_attach),
 480         DEVMETHOD(device_detach,        wx_detach),
 481         DEVMETHOD(device_shutdown,      wx_shutdown),
 482
 483         /* bus interface */
 484         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 485         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 486
 487         /* MII interface */
 488         DEVMETHOD(miibus_readreg,       wx_miibus_readreg),
 489         DEVMETHOD(miibus_writereg,      wx_miibus_writereg),
 490         DEVMETHOD(miibus_statchg,       wx_miibus_statchg),
 491         DEVMETHOD(miibus_mediainit,     wx_miibus_mediainit),
 492
 493         { 0, 0 }
 494 };
 495
 496 static driver_t wx_driver = {
 497         "wx", wx_methods, sizeof(wx_softc_t),
 498 };
 499 static devclass_t wx_devclass;
 500
 501 DECLARE_DUMMY_MODULE(if_wx);
 502 MODULE_DEPEND(if_wx, miibus, 1, 1, 1);
 503 DRIVER_MODULE(if_wx, pci, wx_driver, wx_devclass, 0, 0);
 504 DRIVER_MODULE(miibus, wx, miibus_driver, miibus_devclass, 0, 0);
 505
 506 /*
 507  * Do generic parts of attach. Our registers have been mapped
 508  * and our interrupt registered.
 509  */
 510 static int
 511 wx_attach_common(wx_softc_t *sc)
 512 {
 513         size_t len;
 514         u_int32_t tmp;
 515         int ll = 0;
 516
 517         /*
 518          * First, check for revision support.
 519          */
 520         if (sc->wx_idnrev < WX_WISEMAN_2_0) {
 521                 printf("%s: cannot support ID 0x%x, revision %d chips\n",
 522                     sc->wx_name, sc->wx_idnrev >> 16, sc->wx_idnrev & 0xffff);
 523                 return (ENXIO);
 524         }
 525
 526         /*
 527          * Second, reset the chip.
 528          */
 529         wx_hw_stop(sc);
 530
 531         /*
 532          * Third, validate our EEPROM.
 533          */
 534
 535         /* TBD */
 536
 537         /*
 538          * Fourth, read eeprom for our MAC address and other things.
 539          */
 540         wx_read_eeprom(sc, (u_int16_t *)sc->wx_enaddr, WX_EEPROM_MAC_OFF, 3);
 541
 542         /*
 543          * Fifth, establish some adapter parameters.
 544          */
 545         sc->wx_dcr = 0;
 546
 547         if (IS_LIVENGOOD_CU(sc)) {
 548
 549                 /* settings to talk to PHY */
 550                 sc->wx_dcr |= WXDCR_FRCSPD | WXDCR_FRCDPX | WXDCR_SLU;
 551                 WRITE_CSR(sc, WXREG_DCR, sc->wx_dcr);
 552
 553                 /*
 554                  * Raise the PHY's reset line to make it operational.
 555                  */
 556                 tmp = READ_CSR(sc, WXREG_EXCT);
 557                 tmp |= WXPHY_RESET_DIR4;
 558                 WRITE_CSR(sc, WXREG_EXCT, tmp);
 559                 DELAY(20*1000);
 560
 561                 tmp = READ_CSR(sc, WXREG_EXCT);
 562                 tmp &= ~WXPHY_RESET4;
 563                 WRITE_CSR(sc, WXREG_EXCT, tmp);
 564                 DELAY(20*1000);
 565
 566                 tmp = READ_CSR(sc, WXREG_EXCT);
 567                 tmp |= WXPHY_RESET4;
 568                 WRITE_CSR(sc, WXREG_EXCT, tmp);
 569                 DELAY(20*1000);
 570
 571                 if (wx_attach_phy(sc)) {
 572                         goto fail;
 573                 }
 574         } else {
 575                 ifmedia_init(&sc->wx_media, IFM_IMASK,
 576                     wx_ifmedia_upd, wx_ifmedia_sts);
 577
 578                 ifmedia_add(&sc->wx_media, IFM_ETHER|IFM_1000_SX, 0, NULL);
 579                 ifmedia_add(&sc->wx_media,
 580                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
 581                 ifmedia_set(&sc->wx_media, IFM_ETHER|IFM_1000_SX|IFM_FDX);
 582
 583                 sc->wx_media.ifm_media = sc->wx_media.ifm_cur->ifm_media;
 584         }
 585
 586         /*
 587          * Sixth, establish a default device control register word.
 588          */
 589         ll += 1;
 590         if (sc->wx_cfg1 & WX_EEPROM_CTLR1_FD)
 591                 sc->wx_dcr |= WXDCR_FD;
 592         if (sc->wx_cfg1 & WX_EEPROM_CTLR1_ILOS)
 593                 sc->wx_dcr |= WXDCR_ILOS;
 594
 595         tmp = (sc->wx_cfg1 >> WX_EEPROM_CTLR1_SWDPIO_SHIFT) & WXDCR_SWDPIO_MASK;
 596         sc->wx_dcr |= (tmp << WXDCR_SWDPIO_SHIFT);
 597
 598         if (sc->wx_no_ilos)
 599                 sc->wx_dcr &= ~WXDCR_ILOS;
 600         if (sc->wx_ilos)
 601                 sc->wx_dcr |= WXDCR_ILOS;
 602         if (sc->wx_no_flow == 0)
 603                 sc->wx_dcr |= WXDCR_RFCE | WXDCR_TFCE;
 604
 605         /*
 606          * Seventh, allocate various sw structures...
 607          */
 608         len = sizeof (rxpkt_t) * WX_MAX_RDESC;
 609         sc->rbase = (rxpkt_t *) WXMALLOC(len);
 610         if (sc->rbase == NULL) {
 611                 goto fail;
 612         }
 613         bzero(sc->rbase, len);
 614         ll += 1;
 615
 616         len = sizeof (txpkt_t) * WX_MAX_TDESC;
 617         sc->tbase = (txpkt_t *) WXMALLOC(len);
 618         if (sc->tbase == NULL) {
 619                 goto fail;
 620         }
 621         bzero(sc->tbase, len);
 622         ll += 1;
 623
 624         /*
 625          * Eighth, allocate and dma map (platform dependent) descriptor rings.
 626          * They have to be aligned on a 4KB boundary.
 627          */
 628         if (wx_dring_setup(sc) == 0) {
 629                 return (0);
 630         }
 631
 632 fail:
 633         printf("%s: failed to do common attach (%d)\n", sc->wx_name, ll);
 634         wx_dring_teardown(sc);
 635         if (sc->rbase) {
 636                 WXFREE(sc->rbase);
 637                 sc->rbase = NULL;
 638         }
 639         if (sc->tbase) {
 640                 WXFREE(sc->tbase);
 641                 sc->tbase = NULL;
 642         }
 643         return (ENOMEM);
 644 }
 645
 646 /*
 647  * EEPROM functions.
 648  */
 649
 650 static INLINE void
 651 wx_eeprom_raise_clk(wx_softc_t *sc, u_int32_t regval)
 652 {
 653         WRITE_CSR(sc, WXREG_EECDR, regval | WXEECD_SK);
 654         DELAY(50);
 655 }
 656
 657 static INLINE void
 658 wx_eeprom_lower_clk(wx_softc_t *sc, u_int32_t regval)
 659 {
 660         WRITE_CSR(sc, WXREG_EECDR, regval & ~WXEECD_SK);
 661         DELAY(50);
 662 }
 663
 664 static INLINE void
 665 wx_eeprom_sobits(wx_softc_t *sc, u_int16_t data, u_int16_t count)
 666 {
 667         u_int32_t regval, mask;
 668
 669         mask = 1 << (count - 1);
 670         regval = READ_CSR(sc, WXREG_EECDR) & ~(WXEECD_DI|WXEECD_DO);
 671
 672         do {
 673                 if (data & mask)
 674                         regval |= WXEECD_DI;
 675                 else
 676                         regval &= ~WXEECD_DI;
 677                 WRITE_CSR(sc, WXREG_EECDR, regval); DELAY(50);
 678                 wx_eeprom_raise_clk(sc, regval);
 679                 wx_eeprom_lower_clk(sc, regval);
 680                 mask >>= 1;
 681         } while (mask != 0);
 682         WRITE_CSR(sc, WXREG_EECDR, regval & ~WXEECD_DI);
 683 }
 684
 685 static INLINE u_int16_t
 686 wx_eeprom_sibits(wx_softc_t *sc)
 687 {
 688         unsigned int regval, i;
 689         u_int16_t data;
 690
 691         data = 0;
 692         regval = READ_CSR(sc, WXREG_EECDR) & ~(WXEECD_DI|WXEECD_DO);
 693         for (i = 0; i != 16; i++) {
 694                 data <<= 1;
 695                 wx_eeprom_raise_clk(sc, regval);
 696                 regval = READ_CSR(sc, WXREG_EECDR) & ~WXEECD_DI;
 697                 if (regval & WXEECD_DO) {
 698                         data |= 1;
 699                 }
 700                 wx_eeprom_lower_clk(sc, regval);
 701         }
 702         return (data);
 703 }
 704
 705 static INLINE void
 706 wx_eeprom_cleanup(wx_softc_t *sc)
 707 {
 708         u_int32_t regval;
 709         regval = READ_CSR(sc, WXREG_EECDR) & ~(WXEECD_DI|WXEECD_CS);
 710         WRITE_CSR(sc, WXREG_EECDR, regval); DELAY(50);
 711         wx_eeprom_raise_clk(sc, regval);
 712         wx_eeprom_lower_clk(sc, regval);
 713 }
 714
 715 static u_int16_t INLINE
 716 wx_read_eeprom_word(wx_softc_t *sc, int offset)
 717 {
 718         u_int16_t       data;
 719         WRITE_CSR(sc, WXREG_EECDR, WXEECD_CS);
 720         wx_eeprom_sobits(sc, EEPROM_READ_OPCODE, 3);
 721         wx_eeprom_sobits(sc, offset, 6);
 722         data = wx_eeprom_sibits(sc);
 723         wx_eeprom_cleanup(sc);
 724         return (data);
 725 }
 726
 727 static void
 728 wx_read_eeprom(wx_softc_t *sc, u_int16_t *data, int offset, int words)
 729 {
 730         int i;
 731         for (i = 0; i < words; i++) {
 732                 *data++ = wx_read_eeprom_word(sc, offset++);
 733         }
 734         sc->wx_cfg1 = wx_read_eeprom_word(sc, WX_EEPROM_CTLR1_OFF);
 735 }
 736
 737 /*
 738  * Start packet transmission on the interface.
 739  */
 740
 741 static void
 742 wx_start(struct ifnet *ifp)
 743 {
 744         wx_softc_t *sc = SOFTC_IFP(ifp);
 745         u_int16_t widx = WX_MAX_TDESC, cidx, nactv;
 746
 747         WX_LOCK(sc);
 748         DPRINTF(sc, ("%s: wx_start\n", sc->wx_name));
 749         nactv = sc->tactive;
 750         while (nactv < WX_MAX_TDESC - 1) {
 751                 int ndesc, plen;
 752                 int gctried = 0;
 753                 struct mbuf *m, *mb_head;
 754
 755                 IF_DEQUEUE(&ifp->if_snd, mb_head);
 756                 if (mb_head == NULL) {
 757                         break;
 758                 }
 759                 sc->wx_xmitwanted++;
 760
 761                 /*
 762                  * If we have a packet less than ethermin, pad it out.
 763                  */
 764                 if (mb_head->m_pkthdr.len < WX_MIN_RPKT_SIZE) {
 765                         if (mb_head->m_next == NULL) {
 766                                 mb_head->m_len = WX_MIN_RPKT_SIZE;
 767                         } else {
 768                                 MGETHDR(m, MB_DONTWAIT, MT_DATA);
 769                                 if (m == NULL) {
 770                                         m_freem(mb_head);
 771                                         break;
 772                                 }
 773                                 m_copydata(mb_head, 0, mb_head->m_pkthdr.len,
 774                                     mtod(m, caddr_t));
 775                                 m->m_pkthdr.len = m->m_len = WX_MIN_RPKT_SIZE;
 776                                 bzero(mtod(m, char *) + mb_head->m_pkthdr.len,
 777                                      WX_MIN_RPKT_SIZE - mb_head->m_pkthdr.len);
 778                                 sc->wx_xmitpullup++;
 779                                 m_freem(mb_head);
 780                                 mb_head = m;
 781                         }
 782                 }
 783         again:
 784                 cidx = sc->tnxtfree;
 785                 nactv = sc->tactive;
 786
 787
 788                 /*
 789                  * Go through each of the mbufs in the chain and initialize
 790                  * the transmit buffer descriptors with the physical address
 791                  * and size of that mbuf. If we have a length less than our
 792                  * minimum transmit size, we bail (to do a pullup). If we run
 793                  * out of descriptors, we also bail and try and do a pullup.
 794                  */
 795                 for (plen = ndesc = 0, m = mb_head; m != NULL; m = m->m_next) {
 796                         vm_offset_t vptr;
 797                         wxtd_t *td;
 798
 799                         /*
 800                          * If this mbuf has no data, skip it.
 801                          */
 802                         if (m->m_len == 0) {
 803                                 continue;
 804                         }
 805
 806                         /*
 807                          * This appears to be a bogus check the PRO1000T.
 808                          * I think they meant that the minimum packet size
 809                          * is in fact WX_MIN_XPKT_SIZE (all data loaded)
 810                          */
 811 #if     0
 812                         /*
 813                          * If this mbuf is too small for the chip's minimum,
 814                          * break out to cluster it.
 815                          */
 816                         if (m->m_len < WX_MIN_XPKT_SIZE) {
 817                                 sc->wx_xmitrunt++;
 818                                 break;
 819                         }
 820 #endif
 821
 822                         /*
 823                          * Do we have a descriptor available for this mbuf?
 824                          */
 825                         if (++nactv == WX_MAX_TDESC) {
 826                                 if (gctried++ == 0) {
 827                                         sc->wx_xmitgc++;
 828                                         wx_gc(sc);
 829                                         goto again;
 830                                 }
 831                                 break;
 832                         }
 833                         sc->tbase[cidx].dptr = m;
 834                         td = &sc->tdescriptors[cidx];
 835                         td->length = m->m_len;
 836                         plen += m->m_len;
 837
 838                         vptr = mtod(m, vm_offset_t);
 839                         td->address.highpart = 0;
 840                         td->address.lowpart = vtophys(vptr);
 841
 842                         td->cso = 0;
 843                         td->status = 0;
 844                         td->special = 0;
 845                         td->cmd = 0;
 846                         td->css = 0;
 847
 848                         if (sc->wx_debug) {
 849                                 printf("%s: XMIT[%d] %p vptr %lx (length %d "
 850                                     "DMA addr %x) idx %d\n", sc->wx_name,
 851                                     ndesc, m, (long) vptr, td->length,
 852                                     td->address.lowpart, cidx);
 853                         }
 854                         ndesc++;
 855                         cidx = T_NXT_IDX(cidx);
 856                 }
 857
 858                 /*
 859                  * If we get here and m is NULL, we can send
 860                  * the the packet chain described by mb_head.
 861                  */
 862                 if (m == NULL) {
 863                         /*
 864                          * Mark the last descriptor with EOP and tell the
 865                          * chip to insert a final checksum.
 866                          */
 867                         wxtd_t *td = &sc->tdescriptors[T_PREV_IDX(cidx)];
 868                         td->cmd = TXCMD_EOP|TXCMD_IFCS;
 869                         /*
 870                          * Set up a delayed interrupt when this packet
 871                          * is sent and the descriptor written back.
 872                          * Additional packets completing will cause
 873                          * interrupt to be delayed further. Therefore,
 874                          * after the *last* packet is sent, after the delay
 875                          * period in TIDV, an interrupt will be generated
 876                          * which will cause us to garbage collect.
 877                          */
 878                         td->cmd |= TXCMD_IDE|TXCMD_RPS;
 879
 880                         /*
 881                          * Don't xmit odd length packets.
 882                          * We're okay with bumping things
 883                          * up as long as our mbuf allocation
 884                          * is always larger than our MTU
 885                          * by a comfortable amount.
 886                          *
 887                          * Yes, it's a hole to run past the end
 888                          * of a packet.
 889                          */
 890                         if (plen & 0x1) {
 891                                 sc->wx_oddpkt++;
 892                                 td->length++;
 893                         }
 894
 895                         sc->tbase[sc->tnxtfree].sidx = sc->tnxtfree;
 896                         sc->tbase[sc->tnxtfree].eidx = cidx;
 897                         sc->tbase[sc->tnxtfree].next = NULL;
 898                         if (sc->tbsyf) {
 899                                 sc->tbsyl->next = &sc->tbase[sc->tnxtfree];
 900                         } else {
 901                                 sc->tbsyf = &sc->tbase[sc->tnxtfree];
 902                         }
 903                         sc->tbsyl = &sc->tbase[sc->tnxtfree];
 904                         sc->tnxtfree = cidx;
 905                         sc->tactive = nactv;
 906                         ifp->if_timer = 10;
 907                         if (ifp->if_bpf)
 908                                 bpf_mtap(WX_BPFTAP_ARG(ifp), mb_head);
 909                         /* defer xmit until we've got them all */
 910                         widx = cidx;
 911                         continue;
 912                 }
 913
 914                 /*
 915                  * Otherwise, we couldn't send this packet for some reason.
 916                  *
 917                  * If don't have a descriptor available, and this is a
 918                  * single mbuf packet, freeze output so that later we
 919                  * can restart when we have more room. Otherwise, we'll
 920                  * try and cluster the request. We've already tried to
 921                  * garbage collect completed descriptors.
 922                  */
 923                 if (nactv == WX_MAX_TDESC && mb_head->m_next == NULL) {
 924                         sc->wx_xmitputback++;
 925                         ifp->if_flags |= IFF_OACTIVE;
 926                         IF_PREPEND(&ifp->if_snd, mb_head);
 927                         break;
 928                 }
 929
 930                 /*
 931                  * Otherwise, it's either a fragment length somewhere in the
 932                  * chain that isn't at least WX_MIN_XPKT_SIZE in length or
 933                  * the number of fragments exceeds the number of descriptors
 934                  * available.
 935                  *
 936                  * We could try a variety of strategies here- if this is
 937                  * a length problem for single mbuf packet or a length problem
 938                  * for the last mbuf in a chain (we could just try and adjust
 939                  * it), but it's just simpler to try and cluster it.
 940                  */
 941                 MGETHDR(m, MB_DONTWAIT, MT_DATA);
 942                 if (m == NULL) {
 943                         m_freem(mb_head);
 944                         break;
 945                 }
 946                 MCLGET(m, MB_DONTWAIT);
 947                 if ((m->m_flags & M_EXT) == 0) {
 948                         m_freem(m);
 949                         m_freem(mb_head);
 950                         break;
 951                 }
 952                 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, mtod(m, caddr_t));
 953                 m->m_pkthdr.len = m->m_len = mb_head->m_pkthdr.len;
 954                 m_freem(mb_head);
 955                 mb_head = m;
 956                 sc->wx_xmitcluster++;
 957                 goto again;
 958         }
 959
 960         if (widx < WX_MAX_TDESC) {
 961                 if (IS_WISEMAN(sc)) {
 962                         WRITE_CSR(sc, WXREG_TDT, widx);
 963                 } else {
 964                         WRITE_CSR(sc, WXREG_TDT_LIVENGOOD, widx);
 965                 }
 966         }
 967
 968         if (sc->tactive == WX_MAX_TDESC - 1) {
 969                 sc->wx_xmitgc++;
 970                 wx_gc(sc);
 971                 if (sc->tactive >= WX_MAX_TDESC - 1) {
 972                         sc->wx_xmitblocked++;
 973                         ifp->if_flags |= IFF_OACTIVE;
 974                 }
 975         }
 976
 977         /* used SW LED to indicate transmission active */
 978         if (sc->tactive > 0 && sc->wx_mii) {
 979                 WRITE_CSR(sc, WXREG_DCR,
 980                     READ_CSR(sc, WXREG_DCR) | (WXDCR_SWDPIO0|WXDCR_SWDPIN0));
 981         }
 982         WX_UNLOCK(sc);
 983 }
 984
 985 /*
 986  * Process interface interrupts.
 987  */
 988 static int
 989 wx_intr(void *arg)
 990 {
 991         wx_softc_t *sc = arg;
 992         int claimed = 0;
 993
 994         WX_ILOCK(sc);
 995         /*
 996          * Read interrupt cause register. Reading it clears bits.
 997          */
 998         sc->wx_icr = READ_CSR(sc, WXREG_ICR);
 999         if (sc->wx_icr) {
1000                 claimed++;
1001                 WX_DISABLE_INT(sc);
1002                 sc->wx_intr++;
1003                 if (sc->wx_icr & (WXISR_LSC|WXISR_RXSEQ|WXISR_GPI_EN1)) {
1004                         sc->wx_linkintr++;
1005                         wx_handle_link_intr(sc);
1006                 }
1007                 wx_handle_rxint(sc);
1008                 if (sc->wx_icr & WXISR_TXDW) {
1009                         sc->wx_txqe++;
1010                         wx_gc(sc);
1011                 }
1012 #if     0
1013                 if (sc->wx_icr & WXISR_TXQE) {
1014                         sc->wx_txqe++;
1015                         wx_gc(sc);
1016                 }
1017 #endif
1018                 if (sc->wx_if.if_snd.ifq_head != NULL) {
1019                         wx_start(&sc->wx_if);
1020                 }
1021                 WX_ENABLE_INT(sc);
1022         }
1023         WX_IUNLK(sc);
1024         return (claimed);
1025 }
1026
1027 static void
1028 wx_handle_link_intr(wx_softc_t *sc)
1029 {
1030         u_int32_t txcw, rxcw, dcr, dsr;
1031
1032
1033         dcr = READ_CSR(sc, WXREG_DCR);
1034         DPRINTF(sc, ("%s: handle_link_intr: icr=%#x dcr=%#x\n",
1035             sc->wx_name, sc->wx_icr, dcr));
1036         if (sc->wx_mii) {
1037                 mii_data_t *mii = WX_MII_FROM_SOFTC(sc);
1038                 mii_pollstat(mii);
1039                 if (mii->mii_media_status & IFM_ACTIVE) {
1040                         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE) {
1041                                 IPRINTF(sc, (ldn, sc->wx_name));
1042                                 sc->linkup = 0;
1043                         } else {
1044                                 IPRINTF(sc, (lup, sc->wx_name));
1045                                 sc->linkup = 1;
1046                         }
1047                         WRITE_CSR(sc, WXREG_DCR, sc->wx_dcr);
1048                 } else if (sc->wx_icr & WXISR_RXSEQ) {
1049                         DPRINTF(sc, (sqe, sc->wx_name));
1050                 }
1051                 return;
1052         }
1053
1054         txcw = READ_CSR(sc, WXREG_XMIT_CFGW);
1055         rxcw = READ_CSR(sc, WXREG_RECV_CFGW);
1056         dsr = READ_CSR(sc, WXREG_DSR);
1057
1058         /*
1059          * If we have LOS or are now receiving Ordered Sets and are not
1060          * doing auto-negotiation, restore autonegotiation.
1061          */
1062
1063         if (((dcr & WXDCR_SWDPIN1) || (rxcw & WXRXCW_C)) &&
1064             ((txcw & WXTXCW_ANE) == 0)) {
1065                 DPRINTF(sc, (ane, sc->wx_name));
1066                 WRITE_CSR(sc, WXREG_XMIT_CFGW, WXTXCW_DEFAULT);
1067                 sc->wx_dcr &= ~WXDCR_SLU;
1068                 WRITE_CSR(sc, WXREG_DCR, sc->wx_dcr);
1069                 sc->ane_failed = 0;
1070         }
1071
1072         if (sc->wx_icr & WXISR_LSC) {
1073                 if (READ_CSR(sc, WXREG_DSR) & WXDSR_LU) {
1074                         IPRINTF(sc, (lup, sc->wx_name));
1075                         sc->linkup = 1;
1076                         sc->wx_dcr |= (WXDCR_SWDPIO0|WXDCR_SWDPIN0);
1077                 } else {
1078                         IPRINTF(sc, (ldn, sc->wx_name));
1079                         sc->linkup = 0;
1080                         sc->wx_dcr &= ~(WXDCR_SWDPIO0|WXDCR_SWDPIN0);
1081                 }
1082                 WRITE_CSR(sc, WXREG_DCR, sc->wx_dcr);
1083         } else {
1084                 DPRINTF(sc, (sqe, sc->wx_name));
1085         }
1086 }
1087
1088 static void
1089 wx_check_link(wx_softc_t *sc)
1090 {
1091         u_int32_t rxcw, dcr, dsr;
1092
1093         if (sc->wx_mii) {
1094                 mii_pollstat(WX_MII_FROM_SOFTC(sc));
1095                 return;
1096         }
1097
1098         rxcw = READ_CSR(sc, WXREG_RECV_CFGW);
1099         dcr = READ_CSR(sc, WXREG_DCR);
1100         dsr = READ_CSR(sc, WXREG_DSR);
1101
1102         if ((dsr & WXDSR_LU) == 0 && (dcr & WXDCR_SWDPIN1) == 0 &&
1103             (rxcw & WXRXCW_C) == 0) {
1104                 if (sc->ane_failed == 0) {
1105                         sc->ane_failed = 1;
1106                         return;
1107                 }
1108                 DPRINTF(sc, (inane, sc->wx_name));
1109                 WRITE_CSR(sc, WXREG_XMIT_CFGW, WXTXCW_DEFAULT & ~WXTXCW_ANE);
1110                 if (sc->wx_idnrev < WX_WISEMAN_2_1)
1111                         sc->wx_dcr &= ~WXDCR_TFCE;
1112                 sc->wx_dcr |= WXDCR_SLU;
1113                 WRITE_CSR(sc, WXREG_DCR, sc->wx_dcr);
1114         } else if ((rxcw & WXRXCW_C) != 0 && (dcr & WXDCR_SLU) != 0) {
1115                 DPRINTF(sc, (ane, sc->wx_name));
1116                 WRITE_CSR(sc, WXREG_XMIT_CFGW, WXTXCW_DEFAULT);
1117                 sc->wx_dcr &= ~WXDCR_SLU;
1118                 WRITE_CSR(sc, WXREG_DCR, sc->wx_dcr);
1119         }
1120 }
1121
1122 static void
1123 wx_handle_rxint(wx_softc_t *sc)
1124 {
1125         struct mbuf *m0, *mb, *pending[WX_MAX_RDESC];
1126         struct ifnet *ifp = &sc->wx_if;
1127         int npkts, ndesc, lidx, idx, tlen;
1128
1129         DPRINTF(sc, ("%s: wx_handle_rxint\n", sc->wx_name));
1130
1131         for (m0 = sc->rpending, tlen = ndesc = npkts = 0, idx = sc->rnxt,
1132             lidx = R_PREV_IDX(idx); ndesc < WX_MAX_RDESC;
1133             ndesc++, lidx = idx, idx = R_NXT_IDX(idx)) {
1134                 wxrd_t *rd;
1135                 rxpkt_t *rxpkt;
1136                 int length, offset, lastframe;
1137
1138                 rd = &sc->rdescriptors[idx];
1139                 /*
1140                  * XXX: DMA Flush descriptor
1141                  */
1142                 if ((rd->status & RDSTAT_DD) == 0) {
1143                         if (m0) {
1144                                 if (sc->rpending == NULL) {
1145                                         m0->m_pkthdr.len = tlen;
1146                                         sc->rpending = m0;
1147                                 } else {
1148                                         m_freem(m0);
1149                                 }
1150                                 m0 = NULL;
1151                         }
1152                         DPRINTF(sc, ("%s: WXRX: ndesc %d idx %d lidx %d\n",
1153                             sc->wx_name, ndesc, idx, lidx));
1154                         break;
1155                 }
1156
1157                 if (rd->errors != 0) {
1158                         printf("%s: packet with errors (%x)\n",
1159                             sc->wx_name, rd->errors);
1160                         rd->status = 0;
1161                         ifp->if_ierrors++;
1162                         if (m0) {
1163                                 m_freem(m0);
1164                                 m0 = NULL;
1165                                 if (sc->rpending) {
1166                                         m_freem(sc->rpending);
1167                                         sc->rpending = NULL;
1168                                 }
1169                         }
1170                         continue;
1171                 }
1172
1173
1174                 rxpkt = &sc->rbase[idx];
1175                 mb = rxpkt->dptr;
1176                 if (mb == NULL) {
1177                         printf("%s: receive descriptor with no mbuf\n",
1178                             sc->wx_name);
1179                         (void) wx_get_rbuf(sc, rxpkt);
1180                         rd->status = 0;
1181                         ifp->if_ierrors++;
1182                         if (m0) {
1183                                 m_freem(m0);
1184                                 m0 = NULL;
1185                                 if (sc->rpending) {
1186                                         m_freem(sc->rpending);
1187                                         sc->rpending = NULL;
1188                                 }
1189                         }
1190                         continue;
1191                 }
1192
1193                 /* XXX: Flush DMA for rxpkt */
1194
1195                 if (wx_get_rbuf(sc, rxpkt)) {
1196                         sc->wx_rxnobuf++;
1197                         wx_rxdma_map(sc, rxpkt, mb);
1198                         ifp->if_ierrors++;
1199                         rd->status = 0;
1200                         if (m0) {
1201                                 m_freem(m0);
1202                                 m0 = NULL;
1203                                 if (sc->rpending) {
1204                                         m_freem(sc->rpending);
1205                                         sc->rpending = NULL;
1206                                 }
1207                         }
1208                         continue;
1209                 }
1210
1211                 /*
1212                  * Save the completing packet's offset value and length
1213                  * and install the new one into the descriptor.
1214                  */
1215                 lastframe = (rd->status & RDSTAT_EOP) != 0;
1216                 length = rd->length;
1217                 offset = rd->address.lowpart & 0xff;
1218                 bzero (rd, sizeof (*rd));
1219                 rd->address.lowpart = rxpkt->dma_addr + WX_RX_OFFSET_VALUE;
1220
1221                 mb->m_len = length;
1222                 mb->m_data += offset;
1223                 mb->m_next = NULL;
1224                 if (m0 == NULL) {
1225                         m0 = mb;
1226                         tlen = length;
1227                 } else if (m0 == sc->rpending) {
1228                         /*
1229                          * Pick up where we left off before. If
1230                          * we have an offset (we're assuming the
1231                          * first frame has an offset), then we've
1232                          * lost sync somewhere along the line.
1233                          */
1234                         if (offset) {
1235                                 printf("%s: lost sync with partial packet\n",
1236                                     sc->wx_name);
1237                                 m_freem(sc->rpending);
1238                                 sc->rpending = NULL;
1239                                 m0 = mb;
1240                                 tlen = length;
1241                         } else {
1242                                 sc->rpending = NULL;
1243                                 tlen = m0->m_pkthdr.len;
1244                         }
1245                 } else {
1246                         tlen += length;
1247                 }
1248
1249                 DPRINTF(sc, ("%s: RDESC[%d] len %d off %d lastframe %d\n",
1250                     sc->wx_name, idx, mb->m_len, offset, lastframe));
1251                 if (m0 != mb)
1252                         m_cat(m0, mb);
1253                 if (lastframe == 0) {
1254                         continue;
1255                 }
1256                 m0->m_pkthdr.rcvif = ifp;
1257                 m0->m_pkthdr.len = tlen - WX_CRC_LENGTH;
1258                 mb->m_len -= WX_CRC_LENGTH;
1259
1260                 /*
1261                  * No need to check for promiscous mode since
1262                  * the decision to keep or drop the packet is
1263                  * handled by ether_input()
1264                  */
1265                 pending[npkts++] = m0;
1266                 m0 = NULL;
1267                 tlen = 0;
1268         }
1269
1270         if (ndesc) {
1271                 if (IS_WISEMAN(sc)) {
1272                         WRITE_CSR(sc, WXREG_RDT0, lidx);
1273                 } else {
1274                         WRITE_CSR(sc, WXREG_RDT0_LIVENGOOD, lidx);
1275                 }
1276                 sc->rnxt = idx;
1277         }
1278
1279         if (npkts) {
1280                 sc->wx_rxintr++;
1281         }
1282
1283         for (idx = 0; idx < npkts; idx++) {
1284                 mb = pending[idx];
1285                 if (ifp->if_bpf) {
1286                         bpf_mtap(WX_BPFTAP_ARG(ifp), mb);
1287                 }
1288                 ifp->if_ipackets++;
1289                 DPRINTF(sc, ("%s: RECV packet length %d\n",
1290                     sc->wx_name, mb->m_pkthdr.len));
1291                 (*ifp->if_input)(ifp,  mb);
1292         }
1293 }
1294
1295 static void
1296 wx_gc(wx_softc_t *sc)
1297 {
1298         struct ifnet *ifp = &sc->wx_if;
1299         txpkt_t *txpkt;
1300         u_int32_t tdh;
1301
1302         WX_LOCK(sc);
1303         txpkt = sc->tbsyf;
1304         if (IS_WISEMAN(sc)) {
1305                 tdh = READ_CSR(sc, WXREG_TDH);
1306         } else {
1307                 tdh = READ_CSR(sc, WXREG_TDH_LIVENGOOD);
1308         }
1309         while (txpkt != NULL) {
1310                 u_int32_t end = txpkt->eidx, cidx = tdh;
1311
1312                 /*
1313                  * Normalize start..end indices to 2 *
1314                  * WX_MAX_TDESC range to eliminate wrap.
1315                  */
1316                 if (txpkt->eidx < txpkt->sidx) {
1317                         end += WX_MAX_TDESC;
1318                 }
1319
1320                 /*
1321                  * Normalize current chip index to 2 *
1322                  * WX_MAX_TDESC range to eliminate wrap.
1323                  */
1324                 if (cidx < txpkt->sidx) {
1325                         cidx += WX_MAX_TDESC;
1326                 }
1327
1328                 /*
1329                  * If the current chip index is between low and
1330                  * high indices for this packet, it's not finished
1331                  * transmitting yet. Because transmits are done FIFO,
1332                  * this means we're done garbage collecting too.
1333                  */
1334
1335                 if (txpkt->sidx <= cidx && cidx < txpkt->eidx) {
1336                         DPRINTF(sc, ("%s: TXGC %d..%d TDH %d\n", sc->wx_name,
1337                             txpkt->sidx, txpkt->eidx, tdh));
1338                         break;
1339                 }
1340                 ifp->if_opackets++;
1341
1342                 if (txpkt->dptr) {
1343                         (void) m_freem(txpkt->dptr);
1344                 } else {
1345                         printf("%s: null mbuf in gc\n", sc->wx_name);
1346                 }
1347
1348                 for (cidx = txpkt->sidx; cidx != txpkt->eidx;
1349                     cidx = T_NXT_IDX(cidx)) {
1350                         txpkt_t *tmp;
1351                         wxtd_t *td;
1352
1353                         td = &sc->tdescriptors[cidx];
1354                         if (td->status & TXSTS_EC) {
1355                                 IPRINTF(sc, ("%s: excess collisions\n",
1356                                     sc->wx_name));
1357                                 ifp->if_collisions++;
1358                                 ifp->if_oerrors++;
1359                         }
1360                         if (td->status & TXSTS_LC) {
1361                                 IPRINTF(sc,
1362                                     ("%s: lost carrier\n", sc->wx_name));
1363                                 ifp->if_oerrors++;
1364                         }
1365                         tmp = &sc->tbase[cidx];
1366                         DPRINTF(sc, ("%s: TXGC[%d] %p %d..%d done nact %d "
1367                             "TDH %d\n", sc->wx_name, cidx, tmp->dptr,
1368                             txpkt->sidx, txpkt->eidx, sc->tactive, tdh));
1369                         tmp->dptr = NULL;
1370                         if (sc->tactive == 0) {
1371                                 printf("%s: nactive < 0?\n", sc->wx_name);
1372                         } else {
1373                                 sc->tactive -= 1;
1374                         }
1375                         bzero(td, sizeof (*td));
1376                 }
1377                 sc->tbsyf = txpkt->next;
1378                 txpkt = sc->tbsyf;
1379         }
1380         if (sc->tactive < WX_MAX_TDESC - 1) {
1381                 ifp->if_timer = 0;
1382                 ifp->if_flags &= ~IFF_OACTIVE;
1383         }
1384
1385         /* used SW LED to indicate transmission not active */
1386         if (sc->tactive == 0 && sc->wx_mii) {
1387                 WRITE_CSR(sc, WXREG_DCR,
1388                     READ_CSR(sc, WXREG_DCR) & ~(WXDCR_SWDPIO0|WXDCR_SWDPIN0));
1389         }
1390         WX_UNLOCK(sc);
1391 }
1392
1393 /*
1394  * Periodic timer to update packet in/out/collision statistics,
1395  * and, more importantly, garbage collect completed transmissions
1396  * and to handle link status changes.
1397  */
1398 #define WX_PRT_STATS(sc, y)     printf("\t" # y " = %u\n", ((sc)->y))
1399 #define WX_CLR_STATS(sc, y)     ((sc)->y  = 0)
1400
1401 static void
1402 wx_watchdog(void *arg)
1403 {
1404         wx_softc_t *sc = arg;
1405
1406         WX_LOCK(sc);
1407         if (sc->wx_needreinit) {
1408                 WX_UNLOCK(sc);
1409                 if (wx_init(sc) == 0) {
1410                         WX_LOCK(sc);
1411                         sc->wx_needreinit = 0;
1412                 } else {
1413                         WX_LOCK(sc);
1414                 }
1415         } else {
1416                 wx_gc(sc);
1417                 wx_check_link(sc);
1418         }
1419         if (wx_dump_stats == device_get_unit(sc->w.dev)) {
1420                 printf("%s: current statistics\n", sc->wx_name);
1421                 WX_PRT_STATS(sc, wx_intr);
1422                 WX_PRT_STATS(sc, wx_linkintr);
1423                 WX_PRT_STATS(sc, wx_rxintr);
1424                 WX_PRT_STATS(sc, wx_txqe);
1425                 WX_PRT_STATS(sc, wx_xmitgc);
1426                 WX_PRT_STATS(sc, wx_xmitpullup);
1427                 WX_PRT_STATS(sc, wx_xmitcluster);
1428                 WX_PRT_STATS(sc, wx_xmitputback);
1429                 WX_PRT_STATS(sc, wx_xmitwanted);
1430                 WX_PRT_STATS(sc, wx_xmitblocked);
1431                 WX_PRT_STATS(sc, wx_xmitrunt);
1432                 WX_PRT_STATS(sc, wx_rxnobuf);
1433                 WX_PRT_STATS(sc, wx_oddpkt);
1434                 wx_dump_stats = -1;
1435         }
1436         if (wx_clr_stats == device_get_unit(sc->w.dev)) {
1437                 printf("%s: statistics cleared\n", sc->wx_name);
1438                 WX_CLR_STATS(sc, wx_intr);
1439                 WX_CLR_STATS(sc, wx_linkintr);
1440                 WX_CLR_STATS(sc, wx_rxintr);
1441                 WX_CLR_STATS(sc, wx_txqe);
1442                 WX_CLR_STATS(sc, wx_xmitgc);
1443                 WX_CLR_STATS(sc, wx_xmitpullup);
1444                 WX_CLR_STATS(sc, wx_xmitcluster);
1445                 WX_CLR_STATS(sc, wx_xmitputback);
1446                 WX_CLR_STATS(sc, wx_xmitwanted);
1447                 WX_CLR_STATS(sc, wx_xmitblocked);
1448                 WX_CLR_STATS(sc, wx_xmitrunt);
1449                 WX_CLR_STATS(sc, wx_rxnobuf);
1450                 WX_CLR_STATS(sc, wx_oddpkt);
1451                 wx_clr_stats = -1;
1452         }
1453         WX_UNLOCK(sc);
1454
1455         /*
1456          * Schedule another timeout one second from now.
1457          */
1458         callout_reset(&sc->watchdog_timer, hz, wx_watchdog, sc);
1459 }
1460
1461 /*
1462  * Stop and reinitialize the hardware
1463  */
1464 static void
1465 wx_hw_stop(wx_softc_t *sc)
1466 {
1467         u_int32_t icr;
1468         DPRINTF(sc, ("%s: wx_hw_stop\n", sc->wx_name));
1469         WX_DISABLE_INT(sc);
1470         if (sc->wx_idnrev < WX_WISEMAN_2_1) {
1471                 wx_mwi_whackon(sc);
1472         }
1473         WRITE_CSR(sc, WXREG_DCR, WXDCR_RST);
1474         DELAY(20 * 1000);
1475         icr = READ_CSR(sc, WXREG_ICR);
1476         if (sc->wx_idnrev < WX_WISEMAN_2_1) {
1477                 wx_mwi_unwhack(sc);
1478         }
1479 }
1480
1481 static void
1482 wx_set_addr(wx_softc_t *sc, int idx, u_int8_t *mac)
1483 {
1484         u_int32_t t0, t1;
1485         DPRINTF(sc, ("%s: wx_set_addr\n", sc->wx_name));
1486         t0 = (mac[0]) | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
1487         t1 = (mac[4] << 0) | (mac[5] << 8);
1488         t1 |= WX_RAL_AV;
1489         WRITE_CSR(sc, WXREG_RAL_LO(idx), t0);
1490         WRITE_CSR(sc, WXREG_RAL_HI(idx), t1);
1491 }
1492
1493 static int
1494 wx_hw_initialize(wx_softc_t *sc)
1495 {
1496         int i;
1497
1498         DPRINTF(sc, ("%s: wx_hw_initialize\n", sc->wx_name));
1499
1500         WRITE_CSR(sc, WXREG_VET, 0);
1501         for (i = 0; i < (WX_VLAN_TAB_SIZE << 2); i += 4) {
1502                 WRITE_CSR(sc, (WXREG_VFTA + i), 0);
1503         }
1504         if (sc->wx_idnrev < WX_WISEMAN_2_1) {
1505                 wx_mwi_whackon(sc);
1506                 WRITE_CSR(sc, WXREG_RCTL, WXRCTL_RST);
1507                 DELAY(5 * 1000);
1508         }
1509         /*
1510          * Load the first receiver address with our MAC address,
1511          * and load as many multicast addresses as can fit into
1512          * the receive address array.
1513          */
1514         wx_set_addr(sc, 0, sc->wx_enaddr);
1515         for (i = 1; i <= sc->wx_nmca; i++) {
1516                 if (i >= WX_RAL_TAB_SIZE) {
1517                         break;
1518                 } else {
1519                         wx_set_addr(sc, i, sc->wx_mcaddr[i-1]);
1520                 }
1521         }
1522
1523         while (i < WX_RAL_TAB_SIZE) {
1524                 WRITE_CSR(sc, WXREG_RAL_LO(i), 0);
1525                 WRITE_CSR(sc, WXREG_RAL_HI(i), 0);
1526                 i++;
1527         }
1528
1529         if (sc->wx_idnrev < WX_WISEMAN_2_1) {
1530                 WRITE_CSR(sc, WXREG_RCTL, 0);
1531                 DELAY(1 * 1000);
1532                 wx_mwi_unwhack(sc);
1533         }
1534
1535         /*
1536          * Clear out the hashed multicast table array.
1537          */
1538         for (i = 0; i < WX_MC_TAB_SIZE; i++) {
1539                 WRITE_CSR(sc, WXREG_MTA + (sizeof (u_int32_t) * 4), 0);
1540         }
1541
1542         if (IS_LIVENGOOD_CU(sc)) {
1543                 /*
1544                  * has a PHY - raise its reset line to make it operational
1545                  */
1546                 u_int32_t tmp = READ_CSR(sc, WXREG_EXCT);
1547                 tmp |= WXPHY_RESET_DIR4;
1548                 WRITE_CSR(sc, WXREG_EXCT, tmp);
1549                 DELAY(20*1000);
1550
1551                 tmp = READ_CSR(sc, WXREG_EXCT);
1552                 tmp &= ~WXPHY_RESET4;
1553                 WRITE_CSR(sc, WXREG_EXCT, tmp);
1554                 DELAY(20*1000);
1555
1556                 tmp = READ_CSR(sc, WXREG_EXCT);
1557                 tmp |= WXPHY_RESET4;
1558                 WRITE_CSR(sc, WXREG_EXCT, tmp);
1559                 DELAY(20*1000);
1560         } else if (IS_LIVENGOOD(sc)) {
1561                 u_int16_t tew;
1562
1563                 /*
1564                  * Handle link control
1565                  */
1566                 WRITE_CSR(sc, WXREG_DCR, sc->wx_dcr | WXDCR_LRST);
1567                 DELAY(50 * 1000);
1568
1569                 wx_read_eeprom(sc, &tew, WX_EEPROM_CTLR2_OFF, 1);
1570                 tew = (tew & WX_EEPROM_CTLR2_SWDPIO) << WX_EEPROM_EXT_SHIFT;
1571                 WRITE_CSR(sc, WXREG_EXCT, (u_int32_t)tew);
1572         }
1573
1574         if (sc->wx_dcr & (WXDCR_RFCE|WXDCR_TFCE)) {
1575                 WRITE_CSR(sc, WXREG_FCAL, FC_FRM_CONST_LO);
1576                 WRITE_CSR(sc, WXREG_FCAH, FC_FRM_CONST_HI);
1577                 WRITE_CSR(sc, WXREG_FCT, FC_TYP_CONST);
1578         } else {
1579                 WRITE_CSR(sc, WXREG_FCAL, 0);
1580                 WRITE_CSR(sc, WXREG_FCAH, 0);
1581                 WRITE_CSR(sc, WXREG_FCT, 0);
1582         }
1583         WRITE_CSR(sc, WXREG_FLOW_XTIMER, WX_XTIMER_DFLT);
1584
1585         if (IS_WISEMAN(sc)) {
1586                 if (sc->wx_idnrev < WX_WISEMAN_2_1) {
1587                         WRITE_CSR(sc, WXREG_FLOW_RCV_HI, 0);
1588                         WRITE_CSR(sc, WXREG_FLOW_RCV_LO, 0);
1589                         sc->wx_dcr &= ~(WXDCR_RFCE|WXDCR_TFCE);
1590                 } else {
1591                         WRITE_CSR(sc, WXREG_FLOW_RCV_HI, WX_RCV_FLOW_HI_DFLT);
1592                         WRITE_CSR(sc, WXREG_FLOW_RCV_LO, WX_RCV_FLOW_LO_DFLT);
1593                 }
1594         } else {
1595                 WRITE_CSR(sc, WXREG_FLOW_RCV_HI_LIVENGOOD, WX_RCV_FLOW_HI_DFLT);
1596                 WRITE_CSR(sc, WXREG_FLOW_RCV_LO_LIVENGOOD, WX_RCV_FLOW_LO_DFLT);
1597         }
1598
1599         if (!IS_LIVENGOOD_CU(sc))
1600                 WRITE_CSR(sc, WXREG_XMIT_CFGW, WXTXCW_DEFAULT);
1601
1602         WRITE_CSR(sc, WXREG_DCR, sc->wx_dcr);
1603         DELAY(50 * 1000);
1604
1605         if (!IS_LIVENGOOD_CU(sc)) {
1606                 /*
1607                  * The pin stuff is all FM from the Linux driver.
1608                  */
1609                 if ((READ_CSR(sc, WXREG_DCR) & WXDCR_SWDPIN1) == 0) {
1610                         for (i = 0; i < (WX_LINK_UP_TIMEOUT/10); i++) {
1611                                 DELAY(10 * 1000);
1612                                 if (READ_CSR(sc, WXREG_DSR) & WXDSR_LU) {
1613                                         sc->linkup = 1;
1614                                         break;
1615                                 }
1616                         }
1617                         if (sc->linkup == 0) {
1618                                 sc->ane_failed = 1;
1619                                 wx_check_link(sc);
1620                         }
1621                         sc->ane_failed = 0;
1622                 } else {
1623                         printf("%s: SWDPIO1 did not clear- check for reversed "
1624                                 "or disconnected cable\n", sc->wx_name);
1625                         /* but return okay anyway */
1626                 }
1627         }
1628
1629         sc->wx_ienable = WXIENABLE_DEFAULT;
1630         return (0);
1631 }
1632
1633 /*
1634  * Stop the interface. Cancels the statistics updater and resets the interface.
1635  */
1636 static void
1637 wx_stop(wx_softc_t *sc)
1638 {
1639         txpkt_t *txp;
1640         rxpkt_t *rxp;
1641         struct ifnet *ifp = &sc->wx_if;
1642
1643         DPRINTF(sc, ("%s: wx_stop\n", sc->wx_name));
1644         /*
1645          * Cancel stats updater.
1646          */
1647         callout_stop(&sc->watchdog_timer);
1648
1649         /*
1650          * Reset the chip
1651          */
1652         wx_hw_stop(sc);
1653
1654         /*
1655          * Release any xmit buffers.
1656          */
1657         for (txp = sc->tbase; txp && txp < &sc->tbase[WX_MAX_TDESC]; txp++) {
1658                 if (txp->dptr) {
1659                         m_free(txp->dptr);
1660                         txp->dptr = NULL;
1661                 }
1662         }
1663
1664         /*
1665          * Free all the receive buffers.
1666          */
1667         for (rxp = sc->rbase; rxp && rxp < &sc->rbase[WX_MAX_RDESC]; rxp++) {
1668                 if (rxp->dptr) {
1669                         m_free(rxp->dptr);
1670                         rxp->dptr = NULL;
1671                 }
1672         }
1673
1674         if (sc->rpending) {
1675                 m_freem(sc->rpending);
1676                 sc->rpending = NULL;
1677         }
1678
1679         /*
1680          * And we're outta here...
1681          */
1682
1683         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1684         ifp->if_timer = 0;
1685 }
1686
1687 /*
1688  * Transmit Watchdog
1689  */
1690 static void
1691 wx_txwatchdog(struct ifnet *ifp)
1692 {
1693         wx_softc_t *sc = SOFTC_IFP(ifp);
1694         printf("%s: device timeout\n", sc->wx_name);
1695         ifp->if_oerrors++;
1696         if (wx_init(sc)) {
1697                 printf("%s: could not re-init device\n", sc->wx_name);
1698                 sc->wx_needreinit = 1;
1699         }
1700 }
1701
1702 static int
1703 wx_init(void *xsc)
1704 {
1705         struct ifmedia *ifm;
1706         wx_softc_t *sc = xsc;
1707         struct ifnet *ifp = &sc->wx_if;
1708         rxpkt_t *rxpkt;
1709         wxrd_t *rd;
1710         size_t len;
1711         int i, bflags;
1712
1713         DPRINTF(sc, ("%s: wx_init\n", sc->wx_name));
1714         WX_LOCK(sc);
1715
1716         /*
1717          * Cancel any pending I/O by resetting things.
1718          * wx_stop will free any allocated mbufs.
1719          */
1720         wx_stop(sc);
1721
1722         /*
1723          * Reset the hardware. All network addresses loaded here, but
1724          * neither the receiver nor the transmitter are enabled.
1725          */
1726
1727         if (wx_hw_initialize(sc)) {
1728                 DPRINTF(sc, ("%s: wx_hw_initialize failed\n", sc->wx_name));
1729                 WX_UNLOCK(sc);
1730                 return (EIO);
1731         }
1732
1733         /*
1734          * Set up the receive ring stuff.
1735          */
1736         len = sizeof (wxrd_t) * WX_MAX_RDESC;
1737         bzero(sc->rdescriptors, len);
1738         for (rxpkt = sc->rbase, i = 0; rxpkt != NULL && i < WX_MAX_RDESC;
1739             i += RXINCR, rxpkt++) {
1740                 rd = &sc->rdescriptors[i];
1741                 if (wx_get_rbuf(sc, rxpkt)) {
1742                         break;
1743                 }
1744                 rd->address.lowpart = rxpkt->dma_addr + WX_RX_OFFSET_VALUE;
1745         }
1746         if (i != WX_MAX_RDESC) {
1747                 printf("%s: could not set up rbufs\n", sc->wx_name);
1748                 wx_stop(sc);
1749                 WX_UNLOCK(sc);
1750                 return (ENOMEM);
1751         }
1752
1753         /*
1754          * Set up transmit parameters and enable the transmitter.
1755          */
1756         sc->tnxtfree = sc->tactive = 0;
1757         sc->tbsyf = sc->tbsyl = NULL;
1758         WRITE_CSR(sc, WXREG_TCTL, 0);
1759         DELAY(5 * 1000);
1760         if (IS_WISEMAN(sc)) {
1761                 WRITE_CSR(sc, WXREG_TDBA_LO,
1762                         vtophys((vm_offset_t)&sc->tdescriptors[0]));
1763                 WRITE_CSR(sc, WXREG_TDBA_HI, 0);
1764                 WRITE_CSR(sc, WXREG_TDLEN, WX_MAX_TDESC * sizeof (wxtd_t));
1765                 WRITE_CSR(sc, WXREG_TDH, 0);
1766                 WRITE_CSR(sc, WXREG_TDT, 0);
1767                 WRITE_CSR(sc, WXREG_TQSA_HI, 0);
1768                 WRITE_CSR(sc, WXREG_TQSA_LO, 0);
1769                 WRITE_CSR(sc, WXREG_TIPG, WX_WISEMAN_TIPG_DFLT);
1770                 WRITE_CSR(sc, WXREG_TIDV, wx_txint_delay);
1771         } else {
1772                 WRITE_CSR(sc, WXREG_TDBA_LO_LIVENGOOD,
1773                         vtophys((vm_offset_t)&sc->tdescriptors[0]));
1774                 WRITE_CSR(sc, WXREG_TDBA_HI_LIVENGOOD, 0);
1775                 WRITE_CSR(sc, WXREG_TDLEN_LIVENGOOD,
1776                         WX_MAX_TDESC * sizeof (wxtd_t));
1777                 WRITE_CSR(sc, WXREG_TDH_LIVENGOOD, 0);
1778                 WRITE_CSR(sc, WXREG_TDT_LIVENGOOD, 0);
1779                 WRITE_CSR(sc, WXREG_TQSA_HI, 0);
1780                 WRITE_CSR(sc, WXREG_TQSA_LO, 0);
1781                 WRITE_CSR(sc, WXREG_TIPG, WX_LIVENGOOD_TIPG_DFLT);
1782                 WRITE_CSR(sc, WXREG_TIDV_LIVENGOOD, wx_txint_delay);
1783         }
1784         WRITE_CSR(sc, WXREG_TCTL, (WXTCTL_CT(WX_COLLISION_THRESHOLD) |
1785             WXTCTL_COLD(WX_FDX_COLLISION_DX) | WXTCTL_EN));
1786         /*
1787          * Set up receive parameters and enable the receiver.
1788          */
1789
1790         sc->rnxt = 0;
1791         WRITE_CSR(sc, WXREG_RCTL, 0);
1792         DELAY(5 * 1000);
1793         if (IS_WISEMAN(sc)) {
1794                 WRITE_CSR(sc, WXREG_RDTR0, WXRDTR_FPD);
1795                 WRITE_CSR(sc, WXREG_RDBA0_LO,
1796                     vtophys((vm_offset_t)&sc->rdescriptors[0]));
1797                 WRITE_CSR(sc, WXREG_RDBA0_HI, 0);
1798                 WRITE_CSR(sc, WXREG_RDLEN0, WX_MAX_RDESC * sizeof (wxrd_t));
1799                 WRITE_CSR(sc, WXREG_RDH0, 0);
1800                 WRITE_CSR(sc, WXREG_RDT0, (WX_MAX_RDESC - RXINCR));
1801         } else {
1802                 /*
1803                  * The delay should yield ~10us receive interrupt delay
1804                  */
1805                 WRITE_CSR(sc, WXREG_RDTR0_LIVENGOOD, WXRDTR_FPD | 0x40);
1806                 WRITE_CSR(sc, WXREG_RDBA0_LO_LIVENGOOD,
1807                     vtophys((vm_offset_t)&sc->rdescriptors[0]));
1808                 WRITE_CSR(sc, WXREG_RDBA0_HI_LIVENGOOD, 0);
1809                 WRITE_CSR(sc, WXREG_RDLEN0_LIVENGOOD,
1810                     WX_MAX_RDESC * sizeof (wxrd_t));
1811                 WRITE_CSR(sc, WXREG_RDH0_LIVENGOOD, 0);
1812                 WRITE_CSR(sc, WXREG_RDT0_LIVENGOOD, (WX_MAX_RDESC - RXINCR));
1813         }
1814         WRITE_CSR(sc, WXREG_RDTR1, 0);
1815         WRITE_CSR(sc, WXREG_RDBA1_LO, 0);
1816         WRITE_CSR(sc, WXREG_RDBA1_HI, 0);
1817         WRITE_CSR(sc, WXREG_RDLEN1, 0);
1818         WRITE_CSR(sc, WXREG_RDH1, 0);
1819         WRITE_CSR(sc, WXREG_RDT1, 0);
1820
1821         if (ifp->if_mtu > ETHERMTU) {
1822                 bflags = WXRCTL_EN | WXRCTL_LPE | WXRCTL_2KRBUF;
1823         } else {
1824                 bflags = WXRCTL_EN | WXRCTL_2KRBUF;
1825         }
1826
1827         WRITE_CSR(sc, WXREG_RCTL, bflags |
1828             ((ifp->if_flags & IFF_BROADCAST) ? WXRCTL_BAM : 0) |
1829             ((ifp->if_flags & IFF_PROMISC) ? WXRCTL_UPE : 0) |
1830             ((sc->all_mcasts) ? WXRCTL_MPE : 0));
1831
1832         /*
1833          * Enable Interrupts
1834          */
1835         WX_ENABLE_INT(sc);
1836
1837         if (sc->wx_mii) {
1838                 mii_mediachg(WX_MII_FROM_SOFTC(sc));
1839         } else {
1840                 ifm = &sc->wx_media;
1841                 i = ifm->ifm_media;
1842                 ifm->ifm_media = ifm->ifm_cur->ifm_media;
1843                 wx_ifmedia_upd(ifp);
1844                 ifm->ifm_media = i;
1845         }
1846
1847         /*
1848          * Mark that we're up and running...
1849          */
1850         ifp->if_flags |= IFF_RUNNING;
1851         ifp->if_flags &= ~IFF_OACTIVE;
1852
1853
1854         /*
1855          * Start stats updater.
1856          */
1857         callout_reset(&sc->watchdog_timer, hz, wx_watchdog, sc);
1858
1859         WX_UNLOCK(sc);
1860         /*
1861          * And we're outta here...
1862          */
1863         return (0);
1864 }
1865
1866 /*
1867  * Get a receive buffer for our use (and dma map the data area).
1868  *
1869  * The Wiseman chip can have buffers be 256, 512, 1024 or 2048 bytes in size.
1870  * The LIVENGOOD chip can go higher (up to 16K), but what's the point as
1871  * we aren't doing non-MCLGET memory management.
1872  *
1873  * It wants them aligned on 256 byte boundaries, but can actually cope
1874  * with an offset in the first 255 bytes of the head of a receive frame.
1875  *
1876  * We'll allocate a MCLBYTE sized cluster but *not* adjust the data pointer
1877  * by any alignment value. Instead, we'll tell the chip to offset by any
1878  * alignment and we'll catch the alignment on the backend at interrupt time.
1879  */
1880 static void
1881 wx_rxdma_map(wx_softc_t *sc, rxpkt_t *rxpkt, struct mbuf *mb)
1882 {
1883         rxpkt->dptr = mb;
1884         rxpkt->dma_addr = vtophys(mtod(mb, vm_offset_t));
1885 }
1886
1887 static int
1888 wx_get_rbuf(wx_softc_t *sc, rxpkt_t *rxpkt)
1889 {
1890         struct mbuf *mb;
1891         MGETHDR(mb, MB_DONTWAIT, MT_DATA);
1892         if (mb == NULL) {
1893                 rxpkt->dptr = NULL;
1894                 return (-1);
1895         }
1896         MCLGET(mb, MB_DONTWAIT);
1897         if ((mb->m_flags & M_EXT) == 0) {
1898                 m_freem(mb);
1899                 rxpkt->dptr = NULL;
1900                 return (-1);
1901         }
1902         wx_rxdma_map(sc, rxpkt, mb);
1903         return (0);
1904 }
1905
1906 static int
1907 wx_ioctl(struct ifnet *ifp, IOCTL_CMD_TYPE command, caddr_t data,
1908     struct ucred *cr)
1909 {
1910         wx_softc_t *sc = SOFTC_IFP(ifp);
1911         struct ifreq *ifr = (struct ifreq *) data;
1912         int error = 0;
1913
1914         WX_LOCK(sc);
1915         switch (command) {
1916         case SIOCSIFADDR:
1917         case SIOCGIFADDR:
1918                 error = ether_ioctl(ifp, command, data);
1919                 break;
1920         case SIOCSIFMTU:
1921                 if (ifr->ifr_mtu > WX_MAXMTU || ifr->ifr_mtu < ETHERMIN) {
1922                         error = EINVAL;
1923                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
1924                         ifp->if_mtu = ifr->ifr_mtu;
1925                         error = wx_init(sc);
1926                 }
1927                 break;
1928         case SIOCSIFFLAGS:
1929                 sc->all_mcasts = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0;
1930
1931                 /*
1932                  * If interface is marked up and not running, then start it.
1933                  * If it is marked down and running, stop it.
1934                  * If it's up then re-initialize it. This is so flags
1935                  * such as IFF_PROMISC are handled.
1936                  */
1937                 if (ifp->if_flags & IFF_UP) {
1938                         if ((ifp->if_flags & IFF_RUNNING) == 0) {
1939                                 error = wx_init(sc);
1940                         }
1941                 } else {
1942                         if (ifp->if_flags & IFF_RUNNING) {
1943                                 wx_stop(sc);
1944                         }
1945                 }
1946                 break;
1947
1948         case SIOCADDMULTI:
1949         case SIOCDELMULTI:
1950                 sc->all_mcasts = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0;
1951                 error = wx_mc_setup(sc);
1952                 break;
1953         case SIOCGIFMEDIA:
1954         case SIOCSIFMEDIA:
1955                 DPRINTF(sc, ("%s: ioctl SIOC[GS]IFMEDIA: command=%#lx\n",
1956                     sc->wx_name, command));
1957                 if (sc->wx_mii) {
1958                         mii_data_t *mii = WX_MII_FROM_SOFTC(sc);
1959                         error = ifmedia_ioctl(ifp, ifr,
1960                             &mii->mii_media, command);
1961                 } else {
1962                         error = ifmedia_ioctl(ifp, ifr, &sc->wx_media, command);
1963                 }
1964
1965                 break;
1966         default:
1967                 error = EINVAL;
1968         }
1969
1970         WX_UNLOCK(sc);
1971         return (error);
1972 }
1973
1974 static int
1975 wx_ifmedia_upd(struct ifnet *ifp)
1976 {
1977         struct wx_softc *sc = SOFTC_IFP(ifp);
1978         struct ifmedia *ifm;
1979
1980         DPRINTF(sc, ("%s: ifmedia_upd\n", sc->wx_name));
1981
1982         if (sc->wx_mii) {
1983                 mii_mediachg(WX_MII_FROM_SOFTC(sc));
1984                 return 0;
1985         }
1986
1987         ifm = &sc->wx_media;
1988
1989         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) {
1990                 return (EINVAL);
1991         }
1992
1993         return (0);
1994 }
1995
1996 static void
1997 wx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1998 {
1999         u_int32_t dsr;
2000         struct wx_softc *sc = SOFTC_IFP(ifp);
2001
2002         DPRINTF(sc, ("%s: ifmedia_sts: ", sc->wx_name));
2003
2004         if (sc->wx_mii) {
2005                 mii_data_t *mii = WX_MII_FROM_SOFTC(sc);
2006                 mii_pollstat(mii);
2007                 ifmr->ifm_active = mii->mii_media_active;
2008                 ifmr->ifm_status = mii->mii_media_status;
2009                 DPRINTF(sc, ("active=%#x status=%#x\n",
2010                     ifmr->ifm_active, ifmr->ifm_status));
2011                 return;
2012         }
2013
2014         DPRINTF(sc, ("\n"));
2015         ifmr->ifm_status = IFM_AVALID;
2016         ifmr->ifm_active = IFM_ETHER;
2017
2018         if (sc->linkup == 0)
2019                 return;
2020
2021         ifmr->ifm_status |= IFM_ACTIVE;
2022         dsr = READ_CSR(sc, WXREG_DSR);
2023         if (IS_LIVENGOOD(sc)) {
2024                 if (dsr &  WXDSR_1000BT) {
2025                         if (IS_LIVENGOOD_CU(sc)) {
2026                                 ifmr->ifm_status |= IFM_1000_TX;
2027                         }
2028                         else {
2029                                 ifmr->ifm_status |= IFM_1000_SX;
2030                         }
2031                 } else if (dsr & WXDSR_100BT) {
2032                         ifmr->ifm_status |= IFM_100_FX; /* ?? */
2033                 } else {
2034                         ifmr->ifm_status |= IFM_10_T;   /* ?? */
2035                 }
2036         } else {
2037                 ifmr->ifm_status |= IFM_1000_SX;
2038         }
2039         if (dsr & WXDSR_FD) {
2040                 ifmr->ifm_active |= IFM_FDX;
2041         }
2042 }
2043
2044
2045 #define RAISE_CLOCK(sc, dcr)    \
2046                 WRITE_CSR(sc, WXREG_DCR, (dcr) | WXPHY_MDC), DELAY(2)
2047
2048 #define LOWER_CLOCK(sc, dcr)    \
2049                 WRITE_CSR(sc, WXREG_DCR, (dcr) & ~WXPHY_MDC), DELAY(2)
2050
2051 static u_int32_t
2052 wx_mii_shift_in(wx_softc_t *sc)
2053 {
2054         u_int32_t dcr, i;
2055         u_int32_t data = 0;
2056
2057         dcr = READ_CSR(sc, WXREG_DCR);
2058         dcr &= ~(WXPHY_MDIO_DIR | WXPHY_MDIO);
2059         WRITE_CSR(sc, WXREG_DCR, dcr);
2060         RAISE_CLOCK(sc, dcr);
2061         LOWER_CLOCK(sc, dcr);
2062
2063         for (i = 0; i < 16; i++) {
2064                 data <<= 1;
2065                 RAISE_CLOCK(sc, dcr);
2066                 dcr = READ_CSR(sc, WXREG_DCR);
2067
2068                 if (dcr & WXPHY_MDIO)
2069                         data |= 1;
2070
2071                 LOWER_CLOCK(sc, dcr);
2072         }
2073
2074         RAISE_CLOCK(sc, dcr);
2075         LOWER_CLOCK(sc, dcr);
2076         return (data);
2077 }
2078
2079 static void
2080 wx_mii_shift_out(wx_softc_t *sc, u_int32_t data, u_int32_t count)
2081 {
2082         u_int32_t dcr, mask;
2083
2084         dcr = READ_CSR(sc, WXREG_DCR);
2085         dcr |= WXPHY_MDIO_DIR | WXPHY_MDC_DIR;
2086
2087         for (mask = (1 << (count - 1)); mask; mask >>= 1) {
2088                 if (data & mask)
2089                         dcr |= WXPHY_MDIO;
2090                 else
2091                         dcr &= ~WXPHY_MDIO;
2092
2093                 WRITE_CSR(sc, WXREG_DCR, dcr);
2094                 DELAY(2);
2095                 RAISE_CLOCK(sc, dcr);
2096                 LOWER_CLOCK(sc, dcr);
2097         }
2098 }
2099
2100 static int
2101 wx_miibus_readreg(void *arg, int phy, int reg)
2102 {
2103         wx_softc_t *sc = WX_SOFTC_FROM_MII_ARG(arg);
2104         unsigned int data = 0;
2105
2106         if (!IS_LIVENGOOD_CU(sc)) {
2107                 return 0;
2108         }
2109         wx_mii_shift_out(sc, WXPHYC_PREAMBLE, WXPHYC_PREAMBLE_LEN);
2110         wx_mii_shift_out(sc, reg | (phy << 5) | (WXPHYC_READ << 10) |
2111             (WXPHYC_SOF << 12), 14);
2112         data = wx_mii_shift_in(sc);
2113         return (data & WXMDIC_DATA_MASK);
2114 }
2115
2116 static int
2117 wx_miibus_writereg(void *arg, int phy, int reg, int data)
2118 {
2119         wx_softc_t *sc = WX_SOFTC_FROM_MII_ARG(arg);
2120         if (!IS_LIVENGOOD_CU(sc)) {
2121                 return 0;
2122         }
2123         wx_mii_shift_out(sc, WXPHYC_PREAMBLE, WXPHYC_PREAMBLE_LEN);
2124         wx_mii_shift_out(sc, (u_int32_t)data | (WXPHYC_TURNAROUND << 16) |
2125             (reg << 18) | (phy << 23) | (WXPHYC_WRITE << 28) |
2126             (WXPHYC_SOF << 30), 32);
2127         return (0);
2128 }
2129
2130 static void
2131 wx_miibus_statchg(void *arg)
2132 {
2133         wx_softc_t *sc = WX_SOFTC_FROM_MII_ARG(arg);
2134         mii_data_t *mii = WX_MII_FROM_SOFTC(sc);
2135         u_int32_t dcr, tctl;
2136
2137         if (mii == NULL)
2138                 return;
2139
2140         dcr = sc->wx_dcr;
2141         tctl = READ_CSR(sc, WXREG_TCTL);
2142         DPRINTF(sc, ("%s: statchg dcr=%#x tctl=%#x", sc->wx_name, dcr, tctl));
2143
2144         dcr |= WXDCR_FRCSPD | WXDCR_FRCDPX | WXDCR_SLU;
2145         dcr &= ~(WXDCR_SPEED_MASK | WXDCR_ASDE /* | WXDCR_ILOS */);
2146
2147         if (mii->mii_media_status & IFM_ACTIVE) {
2148                 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE) {
2149                         DPRINTF(sc, (" link-down\n"));
2150                         sc->linkup = 0;
2151                         return;
2152                 }
2153
2154                 sc->linkup = 1;
2155         }
2156
2157         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX) {
2158                 DPRINTF(sc, (" 1000TX"));
2159                 dcr |= WXDCR_1000BT;
2160         } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
2161                 DPRINTF(sc, (" 100TX"));
2162                 dcr |= WXDCR_100BT;
2163         } else  /* assume IFM_10_TX */ {
2164                 DPRINTF(sc, (" 10TX"));
2165                 dcr |= WXDCR_10BT;
2166         }
2167
2168         if (mii->mii_media_active & IFM_FDX) {
2169                 DPRINTF(sc, ("-FD"));
2170                 tctl = WXTCTL_CT(WX_COLLISION_THRESHOLD) |
2171                     WXTCTL_COLD(WX_FDX_COLLISION_DX) | WXTCTL_EN;
2172                 dcr |= WXDCR_FD;
2173         } else {
2174                 DPRINTF(sc, ("-HD"));
2175                 tctl = WXTCTL_CT(WX_COLLISION_THRESHOLD) |
2176                     WXTCTL_COLD(WX_HDX_COLLISION_DX) | WXTCTL_EN;
2177                 dcr &= ~WXDCR_FD;
2178         }
2179
2180         /* FLAG0==rx-flow-control FLAG1==tx-flow-control */
2181         if (mii->mii_media_active & IFM_FLAG0) {
2182                 dcr |= WXDCR_RFCE;
2183         } else {
2184                 dcr &= ~WXDCR_RFCE;
2185         }
2186
2187         if (mii->mii_media_active & IFM_FLAG1) {
2188                 dcr |= WXDCR_TFCE;
2189         } else {
2190                 dcr &= ~WXDCR_TFCE;
2191         }
2192
2193         if (dcr & (WXDCR_RFCE|WXDCR_TFCE)) {
2194                 WRITE_CSR(sc, WXREG_FCAL, FC_FRM_CONST_LO);
2195                 WRITE_CSR(sc, WXREG_FCAH, FC_FRM_CONST_HI);
2196                 WRITE_CSR(sc, WXREG_FCT, FC_TYP_CONST);
2197         } else {
2198                 WRITE_CSR(sc, WXREG_FCAL, 0);
2199                 WRITE_CSR(sc, WXREG_FCAH, 0);
2200                 WRITE_CSR(sc, WXREG_FCT, 0);
2201         }
2202
2203         DPRINTF(sc, (" dcr=%#x tctl=%#x\n", dcr, tctl));
2204         WRITE_CSR(sc, WXREG_TCTL, tctl);
2205         sc->wx_dcr = dcr;
2206         WRITE_CSR(sc, WXREG_DCR, dcr);
2207 }
2208
2209 static void
2210 wx_miibus_mediainit(void *arg)
2211 {
2212 }