2 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
3 * Copyright (c) 1992 Terrence R. Lambert.
4 * Copyright (c) 2003 Peter Wemm.
5 * Copyright (c) 2008 The DragonFly Project.
8 * This code is derived from software contributed to Berkeley by
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the University of
22 * California, Berkeley and its contributors.
23 * 4. Neither the name of the University nor the names of its contributors
24 * may be used to endorse or promote products derived from this software
25 * without specific prior written permission.
27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
40 * $FreeBSD: src/sys/i386/i386/machdep.c,v 1.385.2.30 2003/05/31 08:48:05 alc Exp $
43 //#include "use_npx.h"
45 #include "opt_compat.h"
48 #include "opt_directio.h"
51 #include "opt_msgbuf.h"
54 #include <sys/param.h>
55 #include <sys/systm.h>
56 #include <sys/sysproto.h>
57 #include <sys/signalvar.h>
58 #include <sys/kernel.h>
59 #include <sys/linker.h>
60 #include <sys/malloc.h>
64 #include <sys/reboot.h>
66 #include <sys/msgbuf.h>
67 #include <sys/sysent.h>
68 #include <sys/sysctl.h>
69 #include <sys/vmmeter.h>
71 #include <sys/usched.h>
74 #include <sys/ctype.h>
75 #include <sys/serialize.h>
76 #include <sys/systimer.h>
79 #include <vm/vm_param.h>
81 #include <vm/vm_kern.h>
82 #include <vm/vm_object.h>
83 #include <vm/vm_page.h>
84 #include <vm/vm_map.h>
85 #include <vm/vm_pager.h>
86 #include <vm/vm_extern.h>
88 #include <sys/thread2.h>
89 #include <sys/mplock2.h>
90 #include <sys/mutex2.h>
98 #include <machine/cpu.h>
99 #include <machine/clock.h>
100 #include <machine/specialreg.h>
102 #include <machine/bootinfo.h>
104 #include <machine/md_var.h>
105 #include <machine/metadata.h>
106 #include <machine/pc/bios.h>
107 #include <machine/pcb_ext.h> /* pcb.h included via sys/user.h */
108 #include <machine/globaldata.h> /* CPU_prvspace */
109 #include <machine/smp.h>
111 #include <machine/perfmon.h>
113 #include <machine/cputypes.h>
114 #include <machine/intr_machdep.h>
117 #include <bus/isa/isa_device.h>
119 #include <machine_base/isa/isa_intr.h>
120 #include <bus/isa/rtc.h>
121 #include <sys/random.h>
122 #include <sys/ptrace.h>
123 #include <machine/sigframe.h>
125 #include <sys/machintr.h>
126 #include <machine_base/icu/icu_abi.h>
127 #include <machine_base/icu/elcr_var.h>
128 #include <machine_base/apic/lapic.h>
129 #include <machine_base/apic/ioapic.h>
130 #include <machine_base/apic/ioapic_abi.h>
131 #include <machine/mptable.h>
133 #define PHYSMAP_ENTRIES 10
135 extern u_int64_t hammer_time(u_int64_t, u_int64_t);
137 extern void printcpuinfo(void); /* XXX header file */
138 extern void identify_cpu(void);
140 extern void finishidentcpu(void);
142 extern void panicifcpuunsupported(void);
144 static void cpu_startup(void *);
145 static void pic_finish(void *);
146 static void cpu_finish(void *);
148 #ifndef CPU_DISABLE_SSE
149 static void set_fpregs_xmm(struct save87 *, struct savexmm *);
150 static void fill_fpregs_xmm(struct savexmm *, struct save87 *);
151 #endif /* CPU_DISABLE_SSE */
153 extern void ffs_rawread_setup(void);
154 #endif /* DIRECTIO */
155 static void init_locks(void);
157 SYSINIT(cpu, SI_BOOT2_START_CPU, SI_ORDER_FIRST, cpu_startup, NULL)
158 SYSINIT(pic_finish, SI_BOOT2_FINISH_PIC, SI_ORDER_FIRST, pic_finish, NULL)
159 SYSINIT(cpu_finish, SI_BOOT2_FINISH_CPU, SI_ORDER_FIRST, cpu_finish, NULL)
162 extern vm_offset_t ksym_start, ksym_end;
165 struct privatespace CPU_prvspace[MAXCPU] __aligned(4096); /* XXX */
167 int _udatasel, _ucodesel, _ucode32sel;
169 int64_t tsc_offsets[MAXCPU];
171 static int cpu_mwait_halt; /* MWAIT hint (EAX) or CPU_MWAIT_HINT_ */
173 #if defined(SWTCH_OPTIM_STATS)
174 extern int swtch_optim_stats;
175 SYSCTL_INT(_debug, OID_AUTO, swtch_optim_stats,
176 CTLFLAG_RD, &swtch_optim_stats, 0, "");
177 SYSCTL_INT(_debug, OID_AUTO, tlb_flush_count,
178 CTLFLAG_RD, &tlb_flush_count, 0, "");
180 SYSCTL_INT(_hw, OID_AUTO, cpu_mwait_halt,
181 CTLFLAG_RD, &cpu_mwait_halt, 0, "");
182 SYSCTL_INT(_hw, OID_AUTO, cpu_mwait_spin, CTLFLAG_RD, &cpu_mwait_spin, 0,
183 "monitor/mwait target state");
185 #define CPU_MWAIT_C1 1
186 #define CPU_MWAIT_C2 2
187 #define CPU_MWAIT_C3 3
188 #define CPU_MWAIT_CX_MAX 8
190 #define CPU_MWAIT_HINT_AUTO -1 /* C1 and C2 */
191 #define CPU_MWAIT_HINT_AUTODEEP -2 /* C3+ */
193 SYSCTL_NODE(_machdep, 0, mwait, CTLFLAG_RW, 0, "MWAIT features");
194 SYSCTL_NODE(_machdep_mwait, 0, CX, CTLFLAG_RW, 0, "MWAIT Cx settings");
196 struct cpu_mwait_cx {
199 struct sysctl_ctx_list sysctl_ctx;
200 struct sysctl_oid *sysctl_tree;
202 static struct cpu_mwait_cx cpu_mwait_cx_info[CPU_MWAIT_CX_MAX];
203 static char cpu_mwait_cx_supported[256];
205 static int cpu_mwait_c1_hints_cnt;
206 static int cpu_mwait_hints_cnt;
207 static int *cpu_mwait_hints;
209 static int cpu_mwait_deep_hints_cnt;
210 static int *cpu_mwait_deep_hints;
212 #define CPU_IDLE_REPEAT_DEFAULT 750
214 static u_int cpu_idle_repeat = CPU_IDLE_REPEAT_DEFAULT;
215 static u_long cpu_idle_repeat_max = CPU_IDLE_REPEAT_DEFAULT;
216 static u_int cpu_mwait_repeat_shift = 1;
218 #define CPU_MWAIT_C3_PREAMBLE_BM_ARB 0x1
219 #define CPU_MWAIT_C3_PREAMBLE_BM_STS 0x2
221 static int cpu_mwait_c3_preamble =
222 CPU_MWAIT_C3_PREAMBLE_BM_ARB |
223 CPU_MWAIT_C3_PREAMBLE_BM_STS;
225 SYSCTL_STRING(_machdep_mwait_CX, OID_AUTO, supported, CTLFLAG_RD,
226 cpu_mwait_cx_supported, 0, "MWAIT supported C states");
228 static struct lwkt_serialize cpu_mwait_cx_slize = LWKT_SERIALIZE_INITIALIZER;
229 static int cpu_mwait_cx_select_sysctl(SYSCTL_HANDLER_ARGS,
231 static int cpu_mwait_cx_idle_sysctl(SYSCTL_HANDLER_ARGS);
232 static int cpu_mwait_cx_spin_sysctl(SYSCTL_HANDLER_ARGS);
234 SYSCTL_PROC(_machdep_mwait_CX, OID_AUTO, idle, CTLTYPE_STRING|CTLFLAG_RW,
235 NULL, 0, cpu_mwait_cx_idle_sysctl, "A", "");
236 SYSCTL_PROC(_machdep_mwait_CX, OID_AUTO, spin, CTLTYPE_STRING|CTLFLAG_RW,
237 NULL, 0, cpu_mwait_cx_spin_sysctl, "A", "");
238 SYSCTL_UINT(_machdep_mwait_CX, OID_AUTO, repeat_shift, CTLFLAG_RW,
239 &cpu_mwait_repeat_shift, 0, "");
243 u_long ebda_addr = 0;
245 int imcr_present = 0;
247 int naps = 0; /* # of Applications processors */
250 struct mtx dt_lock; /* lock for GDT and LDT */
253 sysctl_hw_physmem(SYSCTL_HANDLER_ARGS)
255 u_long pmem = ctob(physmem);
257 int error = sysctl_handle_long(oidp, &pmem, 0, req);
261 SYSCTL_PROC(_hw, HW_PHYSMEM, physmem, CTLTYPE_ULONG|CTLFLAG_RD,
262 0, 0, sysctl_hw_physmem, "LU", "Total system memory in bytes (number of pages * page size)");
265 sysctl_hw_usermem(SYSCTL_HANDLER_ARGS)
267 int error = sysctl_handle_int(oidp, 0,
268 ctob(physmem - vmstats.v_wire_count), req);
272 SYSCTL_PROC(_hw, HW_USERMEM, usermem, CTLTYPE_INT|CTLFLAG_RD,
273 0, 0, sysctl_hw_usermem, "IU", "");
276 sysctl_hw_availpages(SYSCTL_HANDLER_ARGS)
278 int error = sysctl_handle_int(oidp, 0,
279 x86_64_btop(avail_end - avail_start), req);
283 SYSCTL_PROC(_hw, OID_AUTO, availpages, CTLTYPE_INT|CTLFLAG_RD,
284 0, 0, sysctl_hw_availpages, "I", "");
290 * The number of PHYSMAP entries must be one less than the number of
291 * PHYSSEG entries because the PHYSMAP entry that spans the largest
292 * physical address that is accessible by ISA DMA is split into two
295 #define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1))
297 vm_paddr_t phys_avail[PHYSMAP_SIZE + 2];
298 vm_paddr_t dump_avail[PHYSMAP_SIZE + 2];
300 /* must be 2 less so 0 0 can signal end of chunks */
301 #define PHYS_AVAIL_ARRAY_END (NELEM(phys_avail) - 2)
302 #define DUMP_AVAIL_ARRAY_END (NELEM(dump_avail) - 2)
304 static vm_offset_t buffer_sva, buffer_eva;
305 vm_offset_t clean_sva, clean_eva;
306 static vm_offset_t pager_sva, pager_eva;
307 static struct trapframe proc0_tf;
310 cpu_startup(void *dummy)
314 vm_offset_t firstaddr;
317 * Good {morning,afternoon,evening,night}.
319 kprintf("%s", version);
322 panicifcpuunsupported();
326 kprintf("real memory = %ju (%ju MB)\n",
328 (intmax_t)Realmem / 1024 / 1024);
330 * Display any holes after the first chunk of extended memory.
335 kprintf("Physical memory chunk(s):\n");
336 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) {
337 vm_paddr_t size1 = phys_avail[indx + 1] - phys_avail[indx];
339 kprintf("0x%08jx - 0x%08jx, %ju bytes (%ju pages)\n",
340 (intmax_t)phys_avail[indx],
341 (intmax_t)phys_avail[indx + 1] - 1,
343 (intmax_t)(size1 / PAGE_SIZE));
348 * Allocate space for system data structures.
349 * The first available kernel virtual address is in "v".
350 * As pages of kernel virtual memory are allocated, "v" is incremented.
351 * As pages of memory are allocated and cleared,
352 * "firstaddr" is incremented.
353 * An index into the kernel page table corresponding to the
354 * virtual memory address maintained in "v" is kept in "mapaddr".
358 * Make two passes. The first pass calculates how much memory is
359 * needed and allocates it. The second pass assigns virtual
360 * addresses to the various data structures.
364 v = (caddr_t)firstaddr;
366 #define valloc(name, type, num) \
367 (name) = (type *)v; v = (caddr_t)((name)+(num))
368 #define valloclim(name, type, num, lim) \
369 (name) = (type *)v; v = (caddr_t)((lim) = ((name)+(num)))
372 * The nominal buffer size (and minimum KVA allocation) is BKVASIZE.
373 * For the first 64MB of ram nominally allocate sufficient buffers to
374 * cover 1/4 of our ram. Beyond the first 64MB allocate additional
375 * buffers to cover 1/20 of our ram over 64MB. When auto-sizing
376 * the buffer cache we limit the eventual kva reservation to
379 * factor represents the 1/4 x ram conversion.
382 long factor = 4 * BKVASIZE / 1024;
383 long kbytes = physmem * (PAGE_SIZE / 1024);
387 nbuf += min((kbytes - 4096) / factor, 65536 / factor);
389 nbuf += (kbytes - 65536) * 2 / (factor * 5);
390 if (maxbcache && nbuf > maxbcache / BKVASIZE)
391 nbuf = maxbcache / BKVASIZE;
395 * Do not allow the buffer_map to be more then 1/2 the size of the
398 if (nbuf > (virtual_end - virtual_start +
399 virtual2_end - virtual2_start) / (BKVASIZE * 2)) {
400 nbuf = (virtual_end - virtual_start +
401 virtual2_end - virtual2_start) / (BKVASIZE * 2);
402 kprintf("Warning: nbufs capped at %ld due to kvm\n", nbuf);
406 * Do not allow the buffer_map to use more than 50% of available
407 * physical-equivalent memory. Since the VM pages which back
408 * individual buffers are typically wired, having too many bufs
409 * can prevent the system from paging properly.
411 if (nbuf > physmem * PAGE_SIZE / (BKVASIZE * 2)) {
412 nbuf = physmem * PAGE_SIZE / (BKVASIZE * 2);
413 kprintf("Warning: nbufs capped at %ld due to physmem\n", nbuf);
417 * Do not allow the sizeof(struct buf) * nbuf to exceed half of
418 * the valloc space which is just the virtual_end - virtual_start
419 * section. We use valloc() to allocate the buf header array.
421 if (nbuf > (virtual_end - virtual_start) / sizeof(struct buf) / 2) {
422 nbuf = (virtual_end - virtual_start) /
423 sizeof(struct buf) / 2;
424 kprintf("Warning: nbufs capped at %ld due to valloc "
425 "considerations", nbuf);
428 nswbuf = lmax(lmin(nbuf / 4, 256), 16);
430 if (nswbuf < NSWBUF_MIN)
437 valloc(swbuf, struct buf, nswbuf);
438 valloc(buf, struct buf, nbuf);
441 * End of first pass, size has been calculated so allocate memory
443 if (firstaddr == 0) {
444 size = (vm_size_t)(v - firstaddr);
445 firstaddr = kmem_alloc(&kernel_map, round_page(size));
447 panic("startup: no room for tables");
452 * End of second pass, addresses have been assigned
454 * nbuf is an int, make sure we don't overflow the field.
456 * On 64-bit systems we always reserve maximal allocations for
457 * buffer cache buffers and there are no fragmentation issues,
458 * so the KVA segment does not have to be excessively oversized.
460 if ((vm_size_t)(v - firstaddr) != size)
461 panic("startup: table size inconsistency");
463 kmem_suballoc(&kernel_map, &clean_map, &clean_sva, &clean_eva,
464 ((vm_offset_t)(nbuf + 16) * BKVASIZE) +
465 (nswbuf * MAXPHYS) + pager_map_size);
466 kmem_suballoc(&clean_map, &buffer_map, &buffer_sva, &buffer_eva,
467 ((vm_offset_t)(nbuf + 16) * BKVASIZE));
468 buffer_map.system_map = 1;
469 kmem_suballoc(&clean_map, &pager_map, &pager_sva, &pager_eva,
470 ((vm_offset_t)nswbuf * MAXPHYS) + pager_map_size);
471 pager_map.system_map = 1;
473 #if defined(USERCONFIG)
475 cninit(); /* the preferred console may have changed */
478 kprintf("avail memory = %ju (%ju MB)\n",
479 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages),
480 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages) /
484 struct cpu_idle_stat {
490 u_long mwait_cx[CPU_MWAIT_CX_MAX];
493 #define CPU_IDLE_STAT_HALT -1
494 #define CPU_IDLE_STAT_SPIN -2
496 static struct cpu_idle_stat cpu_idle_stats[MAXCPU];
499 sysctl_cpu_idle_cnt(SYSCTL_HANDLER_ARGS)
501 int idx = arg2, cpu, error;
504 if (idx == CPU_IDLE_STAT_HALT) {
505 for (cpu = 0; cpu < ncpus; ++cpu)
506 val += cpu_idle_stats[cpu].halt;
507 } else if (idx == CPU_IDLE_STAT_SPIN) {
508 for (cpu = 0; cpu < ncpus; ++cpu)
509 val += cpu_idle_stats[cpu].spin;
511 KASSERT(idx >= 0 && idx < CPU_MWAIT_CX_MAX,
512 ("invalid index %d", idx));
513 for (cpu = 0; cpu < ncpus; ++cpu)
514 val += cpu_idle_stats[cpu].mwait_cx[idx];
517 error = sysctl_handle_quad(oidp, &val, 0, req);
518 if (error || req->newptr == NULL)
521 if (idx == CPU_IDLE_STAT_HALT) {
522 for (cpu = 0; cpu < ncpus; ++cpu)
523 cpu_idle_stats[cpu].halt = 0;
524 cpu_idle_stats[0].halt = val;
525 } else if (idx == CPU_IDLE_STAT_SPIN) {
526 for (cpu = 0; cpu < ncpus; ++cpu)
527 cpu_idle_stats[cpu].spin = 0;
528 cpu_idle_stats[0].spin = val;
530 KASSERT(idx >= 0 && idx < CPU_MWAIT_CX_MAX,
531 ("invalid index %d", idx));
532 for (cpu = 0; cpu < ncpus; ++cpu)
533 cpu_idle_stats[cpu].mwait_cx[idx] = 0;
534 cpu_idle_stats[0].mwait_cx[idx] = val;
540 cpu_mwait_attach(void)
545 if ((cpu_feature2 & CPUID2_MON) == 0 ||
546 (cpu_mwait_feature & CPUID_MWAIT_EXT) == 0)
549 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
550 (CPUID_TO_FAMILY(cpu_id) > 0xf ||
551 (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
552 CPUID_TO_MODEL(cpu_id) >= 0xf))) {
553 atomic_clear_int(&cpu_mwait_c3_preamble,
554 CPU_MWAIT_C3_PREAMBLE_BM_ARB);
557 sbuf_new(&sb, cpu_mwait_cx_supported,
558 sizeof(cpu_mwait_cx_supported), SBUF_FIXEDLEN);
560 for (i = 0; i < CPU_MWAIT_CX_MAX; ++i) {
561 struct cpu_mwait_cx *cx = &cpu_mwait_cx_info[i];
564 ksnprintf(cx->name, sizeof(cx->name), "C%d", i);
566 sysctl_ctx_init(&cx->sysctl_ctx);
567 cx->sysctl_tree = SYSCTL_ADD_NODE(&cx->sysctl_ctx,
568 SYSCTL_STATIC_CHILDREN(_machdep_mwait), OID_AUTO,
569 cx->name, CTLFLAG_RW, NULL, "Cx control/info");
570 if (cx->sysctl_tree == NULL)
573 cx->subcnt = CPUID_MWAIT_CX_SUBCNT(cpu_mwait_extemu, i);
574 SYSCTL_ADD_INT(&cx->sysctl_ctx,
575 SYSCTL_CHILDREN(cx->sysctl_tree), OID_AUTO,
576 "subcnt", CTLFLAG_RD, &cx->subcnt, 0,
578 SYSCTL_ADD_PROC(&cx->sysctl_ctx,
579 SYSCTL_CHILDREN(cx->sysctl_tree), OID_AUTO,
580 "entered", (CTLTYPE_QUAD | CTLFLAG_RW), 0,
581 i, sysctl_cpu_idle_cnt, "Q", "# of times entered");
583 for (sub = 0; sub < cx->subcnt; ++sub)
584 sbuf_printf(&sb, "C%d/%d ", i, sub);
592 cpu_mwait_c1_hints_cnt = cpu_mwait_cx_info[CPU_MWAIT_C1].subcnt;
593 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_C3; ++i)
594 cpu_mwait_hints_cnt += cpu_mwait_cx_info[i].subcnt;
595 cpu_mwait_hints = kmalloc(sizeof(int) * cpu_mwait_hints_cnt,
599 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_C3; ++i) {
602 subcnt = cpu_mwait_cx_info[i].subcnt;
603 for (j = 0; j < subcnt; ++j) {
604 KASSERT(hint_idx < cpu_mwait_hints_cnt,
605 ("invalid mwait hint index %d", hint_idx));
606 cpu_mwait_hints[hint_idx] = MWAIT_EAX_HINT(i, j);
610 KASSERT(hint_idx == cpu_mwait_hints_cnt,
611 ("mwait hint count %d != index %d",
612 cpu_mwait_hints_cnt, hint_idx));
615 kprintf("MWAIT hints (%d C1 hints):\n", cpu_mwait_c1_hints_cnt);
616 for (i = 0; i < cpu_mwait_hints_cnt; ++i) {
617 int hint = cpu_mwait_hints[i];
619 kprintf(" C%d/%d hint 0x%04x\n",
620 MWAIT_EAX_TO_CX(hint), MWAIT_EAX_TO_CX_SUB(hint),
628 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_CX_MAX; ++i)
629 cpu_mwait_deep_hints_cnt += cpu_mwait_cx_info[i].subcnt;
630 cpu_mwait_deep_hints = kmalloc(sizeof(int) * cpu_mwait_deep_hints_cnt,
634 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_CX_MAX; ++i) {
637 subcnt = cpu_mwait_cx_info[i].subcnt;
638 for (j = 0; j < subcnt; ++j) {
639 KASSERT(hint_idx < cpu_mwait_deep_hints_cnt,
640 ("invalid mwait deep hint index %d", hint_idx));
641 cpu_mwait_deep_hints[hint_idx] = MWAIT_EAX_HINT(i, j);
645 KASSERT(hint_idx == cpu_mwait_deep_hints_cnt,
646 ("mwait deep hint count %d != index %d",
647 cpu_mwait_deep_hints_cnt, hint_idx));
650 kprintf("MWAIT deep hints:\n");
651 for (i = 0; i < cpu_mwait_deep_hints_cnt; ++i) {
652 int hint = cpu_mwait_deep_hints[i];
654 kprintf(" C%d/%d hint 0x%04x\n",
655 MWAIT_EAX_TO_CX(hint), MWAIT_EAX_TO_CX_SUB(hint),
659 cpu_idle_repeat_max = 256 * cpu_mwait_deep_hints_cnt;
663 cpu_finish(void *dummy __unused)
670 pic_finish(void *dummy __unused)
672 /* Log ELCR information */
675 /* Log MPTABLE information */
676 mptable_pci_int_dump();
679 MachIntrABI.finalize();
683 * Send an interrupt to process.
685 * Stack is set up to allow sigcode stored
686 * at top to call routine, followed by kcall
687 * to sigreturn routine below. After sigreturn
688 * resets the signal mask, the stack, and the
689 * frame pointer, it returns to the user
693 sendsig(sig_t catcher, int sig, sigset_t *mask, u_long code)
695 struct lwp *lp = curthread->td_lwp;
696 struct proc *p = lp->lwp_proc;
697 struct trapframe *regs;
698 struct sigacts *psp = p->p_sigacts;
699 struct sigframe sf, *sfp;
703 regs = lp->lwp_md.md_regs;
704 oonstack = (lp->lwp_sigstk.ss_flags & SS_ONSTACK) ? 1 : 0;
706 /* Save user context */
707 bzero(&sf, sizeof(struct sigframe));
708 sf.sf_uc.uc_sigmask = *mask;
709 sf.sf_uc.uc_stack = lp->lwp_sigstk;
710 sf.sf_uc.uc_mcontext.mc_onstack = oonstack;
711 KKASSERT(__offsetof(struct trapframe, tf_rdi) == 0);
712 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(struct trapframe));
714 /* Make the size of the saved context visible to userland */
715 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext);
717 /* Allocate and validate space for the signal handler context. */
718 if ((lp->lwp_flags & LWP_ALTSTACK) != 0 && !oonstack &&
719 SIGISMEMBER(psp->ps_sigonstack, sig)) {
720 sp = (char *)(lp->lwp_sigstk.ss_sp + lp->lwp_sigstk.ss_size -
721 sizeof(struct sigframe));
722 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
724 /* We take red zone into account */
725 sp = (char *)regs->tf_rsp - sizeof(struct sigframe) - 128;
729 * XXX AVX needs 64-byte alignment but sigframe has other fields and
730 * the embedded ucontext is not at the front, so aligning this won't
731 * help us. Fortunately we bcopy in/out of the sigframe, so the
734 * The problem though is if userland winds up trying to use the
737 sfp = (struct sigframe *)((intptr_t)sp & ~(intptr_t)0xF);
739 /* Translate the signal is appropriate */
740 if (p->p_sysent->sv_sigtbl) {
741 if (sig <= p->p_sysent->sv_sigsize)
742 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)];
746 * Build the argument list for the signal handler.
748 * Arguments are in registers (%rdi, %rsi, %rdx, %rcx)
750 regs->tf_rdi = sig; /* argument 1 */
751 regs->tf_rdx = (register_t)&sfp->sf_uc; /* argument 3 */
753 if (SIGISMEMBER(psp->ps_siginfo, sig)) {
755 * Signal handler installed with SA_SIGINFO.
757 * action(signo, siginfo, ucontext)
759 regs->tf_rsi = (register_t)&sfp->sf_si; /* argument 2 */
760 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */
761 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher;
763 /* fill siginfo structure */
764 sf.sf_si.si_signo = sig;
765 sf.sf_si.si_code = code;
766 sf.sf_si.si_addr = (void *)regs->tf_addr;
769 * Old FreeBSD-style arguments.
771 * handler (signo, code, [uc], addr)
773 regs->tf_rsi = (register_t)code; /* argument 2 */
774 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */
775 sf.sf_ahu.sf_handler = catcher;
779 * If we're a vm86 process, we want to save the segment registers.
780 * We also change eflags to be our emulated eflags, not the actual
784 if (regs->tf_eflags & PSL_VM) {
785 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
786 struct vm86_kernel *vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
788 sf.sf_uc.uc_mcontext.mc_gs = tf->tf_vm86_gs;
789 sf.sf_uc.uc_mcontext.mc_fs = tf->tf_vm86_fs;
790 sf.sf_uc.uc_mcontext.mc_es = tf->tf_vm86_es;
791 sf.sf_uc.uc_mcontext.mc_ds = tf->tf_vm86_ds;
793 if (vm86->vm86_has_vme == 0)
794 sf.sf_uc.uc_mcontext.mc_eflags =
795 (tf->tf_eflags & ~(PSL_VIF | PSL_VIP)) |
796 (vm86->vm86_eflags & (PSL_VIF | PSL_VIP));
799 * Clear PSL_NT to inhibit T_TSSFLT faults on return from
800 * syscalls made by the signal handler. This just avoids
801 * wasting time for our lazy fixup of such faults. PSL_NT
802 * does nothing in vm86 mode, but vm86 programs can set it
803 * almost legitimately in probes for old cpu types.
805 tf->tf_eflags &= ~(PSL_VM | PSL_NT | PSL_VIF | PSL_VIP);
810 * Save the FPU state and reinit the FP unit
812 npxpush(&sf.sf_uc.uc_mcontext);
815 * Copy the sigframe out to the user's stack.
817 if (copyout(&sf, sfp, sizeof(struct sigframe)) != 0) {
819 * Something is wrong with the stack pointer.
820 * ...Kill the process.
825 regs->tf_rsp = (register_t)sfp;
826 regs->tf_rip = PS_STRINGS - *(p->p_sysent->sv_szsigcode);
829 * i386 abi specifies that the direction flag must be cleared
832 regs->tf_rflags &= ~(PSL_T|PSL_D);
835 * 64 bit mode has a code and stack selector but
836 * no data or extra selector. %fs and %gs are not
839 regs->tf_cs = _ucodesel;
840 regs->tf_ss = _udatasel;
845 * Sanitize the trapframe for a virtual kernel passing control to a custom
846 * VM context. Remove any items that would otherwise create a privilage
849 * XXX at the moment we allow userland to set the resume flag. Is this a
853 cpu_sanitize_frame(struct trapframe *frame)
855 frame->tf_cs = _ucodesel;
856 frame->tf_ss = _udatasel;
857 /* XXX VM (8086) mode not supported? */
858 frame->tf_rflags &= (PSL_RF | PSL_USERCHANGE | PSL_VM_UNSUPP);
859 frame->tf_rflags |= PSL_RESERVED_DEFAULT | PSL_I;
865 * Sanitize the tls so loading the descriptor does not blow up
866 * on us. For x86_64 we don't have to do anything.
869 cpu_sanitize_tls(struct savetls *tls)
875 * sigreturn(ucontext_t *sigcntxp)
877 * System call to cleanup state after a signal
878 * has been taken. Reset signal mask and
879 * stack state from context left by sendsig (above).
880 * Return to previous pc and psl as specified by
881 * context left by sendsig. Check carefully to
882 * make sure that the user has not modified the
883 * state to gain improper privileges.
887 #define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0)
888 #define CS_SECURE(cs) (ISPL(cs) == SEL_UPL)
891 sys_sigreturn(struct sigreturn_args *uap)
893 struct lwp *lp = curthread->td_lwp;
894 struct trapframe *regs;
902 * We have to copy the information into kernel space so userland
903 * can't modify it while we are sniffing it.
905 regs = lp->lwp_md.md_regs;
906 error = copyin(uap->sigcntxp, &uc, sizeof(uc));
910 rflags = ucp->uc_mcontext.mc_rflags;
912 /* VM (8086) mode not supported */
913 rflags &= ~PSL_VM_UNSUPP;
916 if (eflags & PSL_VM) {
917 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
918 struct vm86_kernel *vm86;
921 * if pcb_ext == 0 or vm86_inited == 0, the user hasn't
922 * set up the vm86 area, and we can't enter vm86 mode.
924 if (lp->lwp_thread->td_pcb->pcb_ext == 0)
926 vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
927 if (vm86->vm86_inited == 0)
930 /* go back to user mode if both flags are set */
931 if ((eflags & PSL_VIP) && (eflags & PSL_VIF))
932 trapsignal(lp, SIGBUS, 0);
934 if (vm86->vm86_has_vme) {
935 eflags = (tf->tf_eflags & ~VME_USERCHANGE) |
936 (eflags & VME_USERCHANGE) | PSL_VM;
938 vm86->vm86_eflags = eflags; /* save VIF, VIP */
939 eflags = (tf->tf_eflags & ~VM_USERCHANGE) |
940 (eflags & VM_USERCHANGE) | PSL_VM;
942 bcopy(&ucp->uc_mcontext.mc_gs, tf, sizeof(struct trapframe));
943 tf->tf_eflags = eflags;
944 tf->tf_vm86_ds = tf->tf_ds;
945 tf->tf_vm86_es = tf->tf_es;
946 tf->tf_vm86_fs = tf->tf_fs;
947 tf->tf_vm86_gs = tf->tf_gs;
948 tf->tf_ds = _udatasel;
949 tf->tf_es = _udatasel;
950 tf->tf_fs = _udatasel;
951 tf->tf_gs = _udatasel;
956 * Don't allow users to change privileged or reserved flags.
959 * XXX do allow users to change the privileged flag PSL_RF.
960 * The cpu sets PSL_RF in tf_eflags for faults. Debuggers
961 * should sometimes set it there too. tf_eflags is kept in
962 * the signal context during signal handling and there is no
963 * other place to remember it, so the PSL_RF bit may be
964 * corrupted by the signal handler without us knowing.
965 * Corruption of the PSL_RF bit at worst causes one more or
966 * one less debugger trap, so allowing it is fairly harmless.
968 if (!EFL_SECURE(rflags & ~PSL_RF, regs->tf_rflags & ~PSL_RF)) {
969 kprintf("sigreturn: rflags = 0x%lx\n", (long)rflags);
974 * Don't allow users to load a valid privileged %cs. Let the
975 * hardware check for invalid selectors, excess privilege in
976 * other selectors, invalid %eip's and invalid %esp's.
978 cs = ucp->uc_mcontext.mc_cs;
979 if (!CS_SECURE(cs)) {
980 kprintf("sigreturn: cs = 0x%x\n", cs);
981 trapsignal(lp, SIGBUS, T_PROTFLT);
984 bcopy(&ucp->uc_mcontext.mc_rdi, regs, sizeof(struct trapframe));
988 * Restore the FPU state from the frame
991 npxpop(&ucp->uc_mcontext);
993 if (ucp->uc_mcontext.mc_onstack & 1)
994 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
996 lp->lwp_sigstk.ss_flags &= ~SS_ONSTACK;
998 lp->lwp_sigmask = ucp->uc_sigmask;
999 SIG_CANTMASK(lp->lwp_sigmask);
1002 return(EJUSTRETURN);
1006 * Machine dependent boot() routine
1008 * I haven't seen anything to put here yet
1009 * Possibly some stuff might be grafted back here from boot()
1017 * Shutdown the CPU as much as possible
1023 __asm__ __volatile("hlt");
1027 * cpu_idle() represents the idle LWKT. You cannot return from this function
1028 * (unless you want to blow things up!). Instead we look for runnable threads
1029 * and loop or halt as appropriate. Giant is not held on entry to the thread.
1031 * The main loop is entered with a critical section held, we must release
1032 * the critical section before doing anything else. lwkt_switch() will
1033 * check for pending interrupts due to entering and exiting its own
1036 * NOTE: On an SMP system we rely on a scheduler IPI to wake a HLTed cpu up.
1037 * However, there are cases where the idlethread will be entered with
1038 * the possibility that no IPI will occur and in such cases
1039 * lwkt_switch() sets TDF_IDLE_NOHLT.
1041 * NOTE: cpu_idle_repeat determines how many entries into the idle thread
1042 * must occur before it starts using ACPI halt.
1044 static int cpu_idle_hlt = 2;
1045 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hlt, CTLFLAG_RW,
1046 &cpu_idle_hlt, 0, "Idle loop HLT enable");
1047 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_repeat, CTLFLAG_RW,
1048 &cpu_idle_repeat, 0, "Idle entries before acpi hlt");
1050 SYSCTL_PROC(_machdep, OID_AUTO, cpu_idle_hltcnt, (CTLTYPE_QUAD | CTLFLAG_RW),
1051 0, CPU_IDLE_STAT_HALT, sysctl_cpu_idle_cnt, "Q", "Idle loop entry halts");
1052 SYSCTL_PROC(_machdep, OID_AUTO, cpu_idle_spincnt, (CTLTYPE_QUAD | CTLFLAG_RW),
1053 0, CPU_IDLE_STAT_SPIN, sysctl_cpu_idle_cnt, "Q", "Idle loop entry spins");
1056 cpu_idle_default_hook(void)
1059 * We must guarentee that hlt is exactly the instruction
1060 * following the sti.
1062 __asm __volatile("sti; hlt");
1065 /* Other subsystems (e.g., ACPI) can hook this later. */
1066 void (*cpu_idle_hook)(void) = cpu_idle_default_hook;
1069 cpu_mwait_cx_hint(struct cpu_idle_stat *stat)
1074 if (cpu_mwait_halt >= 0) {
1075 hint = cpu_mwait_halt;
1079 idx = (stat->repeat + stat->repeat_last + stat->repeat_delta) >>
1080 cpu_mwait_repeat_shift;
1081 if (idx >= cpu_mwait_c1_hints_cnt) {
1082 /* Step up faster, once we walked through all C1 states */
1083 stat->repeat_delta += 1 << (cpu_mwait_repeat_shift + 1);
1085 if (cpu_mwait_halt == CPU_MWAIT_HINT_AUTODEEP) {
1086 if (idx >= cpu_mwait_deep_hints_cnt)
1087 idx = cpu_mwait_deep_hints_cnt - 1;
1088 hint = cpu_mwait_deep_hints[idx];
1090 if (idx >= cpu_mwait_hints_cnt)
1091 idx = cpu_mwait_hints_cnt - 1;
1092 hint = cpu_mwait_hints[idx];
1095 cx_idx = MWAIT_EAX_TO_CX(hint);
1096 if (cx_idx >= 0 && cx_idx < CPU_MWAIT_CX_MAX)
1097 stat->mwait_cx[cx_idx]++;
1104 globaldata_t gd = mycpu;
1105 struct cpu_idle_stat *stat = &cpu_idle_stats[gd->gd_cpuid];
1106 struct thread *td __debugvar = gd->gd_curthread;
1110 stat->repeat = stat->repeat_last = cpu_idle_repeat_max;
1113 KKASSERT(td->td_critcount == 0);
1116 * See if there are any LWKTs ready to go.
1121 * When halting inside a cli we must check for reqflags
1122 * races, particularly [re]schedule requests. Running
1123 * splz() does the job.
1126 * 0 Never halt, just spin
1128 * 1 Always use HLT (or MONITOR/MWAIT if avail).
1129 * This typically eats more power than the
1132 * 2 Use HLT/MONITOR/MWAIT up to a point and then
1133 * use the ACPI halt (default). This is a hybrid
1134 * approach. See machdep.cpu_idle_repeat.
1136 * 3 Always use the ACPI halt. This typically
1137 * eats the least amount of power but the cpu
1138 * will be slow waking up. Slows down e.g.
1139 * compiles and other pipe/event oriented stuff.
1141 * NOTE: Interrupts are enabled and we are not in a critical
1144 * NOTE: Preemptions do not reset gd_idle_repeat. Also we
1145 * don't bother capping gd_idle_repeat, it is ok if
1148 if (gd->gd_idle_repeat == 0) {
1149 stat->repeat = (stat->repeat + stat->repeat_last) >> 1;
1150 if (stat->repeat > cpu_idle_repeat_max)
1151 stat->repeat = cpu_idle_repeat_max;
1152 stat->repeat_last = 0;
1153 stat->repeat_delta = 0;
1155 ++stat->repeat_last;
1157 ++gd->gd_idle_repeat;
1158 reqflags = gd->gd_reqflags;
1159 quick = (cpu_idle_hlt == 1) ||
1160 (cpu_idle_hlt < 3 &&
1161 gd->gd_idle_repeat < cpu_idle_repeat);
1163 if (quick && (cpu_mi_feature & CPU_MI_MONITOR) &&
1164 (reqflags & RQF_IDLECHECK_WK_MASK) == 0) {
1166 cpu_mmw_pause_int(&gd->gd_reqflags, reqflags,
1167 cpu_mwait_cx_hint(stat), 0);
1169 } else if (cpu_idle_hlt) {
1170 __asm __volatile("cli");
1172 if ((gd->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) {
1174 cpu_idle_default_hook();
1178 __asm __volatile("sti");
1182 __asm __volatile("sti");
1189 * This routine is called if a spinlock has been held through the
1190 * exponential backoff period and is seriously contested. On a real cpu
1194 cpu_spinlock_contested(void)
1200 * Clear registers on exec
1203 exec_setregs(u_long entry, u_long stack, u_long ps_strings)
1205 struct thread *td = curthread;
1206 struct lwp *lp = td->td_lwp;
1207 struct pcb *pcb = td->td_pcb;
1208 struct trapframe *regs = lp->lwp_md.md_regs;
1210 /* was i386_user_cleanup() in NetBSD */
1214 bzero((char *)regs, sizeof(struct trapframe));
1215 regs->tf_rip = entry;
1216 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8; /* align the stack */
1217 regs->tf_rdi = stack; /* argv */
1218 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T);
1219 regs->tf_ss = _udatasel;
1220 regs->tf_cs = _ucodesel;
1221 regs->tf_rbx = ps_strings;
1224 * Reset the hardware debug registers if they were in use.
1225 * They won't have any meaning for the newly exec'd process.
1227 if (pcb->pcb_flags & PCB_DBREGS) {
1233 pcb->pcb_dr7 = 0; /* JG set bit 10? */
1234 if (pcb == td->td_pcb) {
1236 * Clear the debug registers on the running
1237 * CPU, otherwise they will end up affecting
1238 * the next process we switch to.
1242 pcb->pcb_flags &= ~PCB_DBREGS;
1246 * Initialize the math emulator (if any) for the current process.
1247 * Actually, just clear the bit that says that the emulator has
1248 * been initialized. Initialization is delayed until the process
1249 * traps to the emulator (if it is done at all) mainly because
1250 * emulators don't provide an entry point for initialization.
1252 pcb->pcb_flags &= ~FP_SOFTFP;
1255 * NOTE: do not set CR0_TS here. npxinit() must do it after clearing
1256 * gd_npxthread. Otherwise a preemptive interrupt thread
1257 * may panic in npxdna().
1260 load_cr0(rcr0() | CR0_MP);
1263 * NOTE: The MSR values must be correct so we can return to
1264 * userland. gd_user_fs/gs must be correct so the switch
1265 * code knows what the current MSR values are.
1267 pcb->pcb_fsbase = 0; /* Values loaded from PCB on switch */
1268 pcb->pcb_gsbase = 0;
1269 mdcpu->gd_user_fs = 0; /* Cache of current MSR values */
1270 mdcpu->gd_user_gs = 0;
1271 wrmsr(MSR_FSBASE, 0); /* Set MSR values for return to userland */
1272 wrmsr(MSR_KGSBASE, 0);
1274 /* Initialize the npx (if any) for the current process. */
1275 npxinit(__INITIAL_FPUCW__);
1278 pcb->pcb_ds = _udatasel;
1279 pcb->pcb_es = _udatasel;
1280 pcb->pcb_fs = _udatasel;
1281 pcb->pcb_gs = _udatasel;
1290 cr0 |= CR0_NE; /* Done by npxinit() */
1291 cr0 |= CR0_MP | CR0_TS; /* Done at every execve() too. */
1292 cr0 |= CR0_WP | CR0_AM;
1298 sysctl_machdep_adjkerntz(SYSCTL_HANDLER_ARGS)
1301 error = sysctl_handle_int(oidp, oidp->oid_arg1, oidp->oid_arg2,
1303 if (!error && req->newptr)
1308 SYSCTL_PROC(_machdep, CPU_ADJKERNTZ, adjkerntz, CTLTYPE_INT|CTLFLAG_RW,
1309 &adjkerntz, 0, sysctl_machdep_adjkerntz, "I", "");
1311 SYSCTL_INT(_machdep, CPU_DISRTCSET, disable_rtc_set,
1312 CTLFLAG_RW, &disable_rtc_set, 0, "");
1315 SYSCTL_STRUCT(_machdep, CPU_BOOTINFO, bootinfo,
1316 CTLFLAG_RD, &bootinfo, bootinfo, "");
1319 SYSCTL_INT(_machdep, CPU_WALLCLOCK, wall_cmos_clock,
1320 CTLFLAG_RW, &wall_cmos_clock, 0, "");
1322 extern u_long bootdev; /* not a cdev_t - encoding is different */
1323 SYSCTL_ULONG(_machdep, OID_AUTO, guessed_bootdev,
1324 CTLFLAG_RD, &bootdev, 0, "Boot device (not in cdev_t format)");
1327 * Initialize 386 and configure to run kernel
1331 * Initialize segments & interrupt table
1335 struct user_segment_descriptor gdt[NGDT * MAXCPU]; /* global descriptor table */
1336 struct gate_descriptor idt_arr[MAXCPU][NIDT];
1338 union descriptor ldt[NLDT]; /* local descriptor table */
1341 /* table descriptors - used to load tables by cpu */
1342 struct region_descriptor r_gdt;
1343 struct region_descriptor r_idt_arr[MAXCPU];
1345 /* JG proc0paddr is a virtual address */
1348 char proc0paddr_buff[LWKT_THREAD_STACK];
1351 /* software prototypes -- in more palatable form */
1352 struct soft_segment_descriptor gdt_segs[] = {
1353 /* GNULL_SEL 0 Null Descriptor */
1354 { 0x0, /* segment base address */
1356 0, /* segment type */
1357 0, /* segment descriptor priority level */
1358 0, /* segment descriptor present */
1360 0, /* default 32 vs 16 bit size */
1361 0 /* limit granularity (byte/page units)*/ },
1362 /* GCODE_SEL 1 Code Descriptor for kernel */
1363 { 0x0, /* segment base address */
1364 0xfffff, /* length - all address space */
1365 SDT_MEMERA, /* segment type */
1366 SEL_KPL, /* segment descriptor priority level */
1367 1, /* segment descriptor present */
1369 0, /* default 32 vs 16 bit size */
1370 1 /* limit granularity (byte/page units)*/ },
1371 /* GDATA_SEL 2 Data Descriptor for kernel */
1372 { 0x0, /* segment base address */
1373 0xfffff, /* length - all address space */
1374 SDT_MEMRWA, /* segment type */
1375 SEL_KPL, /* segment descriptor priority level */
1376 1, /* segment descriptor present */
1378 0, /* default 32 vs 16 bit size */
1379 1 /* limit granularity (byte/page units)*/ },
1380 /* GUCODE32_SEL 3 32 bit Code Descriptor for user */
1381 { 0x0, /* segment base address */
1382 0xfffff, /* length - all address space */
1383 SDT_MEMERA, /* segment type */
1384 SEL_UPL, /* segment descriptor priority level */
1385 1, /* segment descriptor present */
1387 1, /* default 32 vs 16 bit size */
1388 1 /* limit granularity (byte/page units)*/ },
1389 /* GUDATA_SEL 4 32/64 bit Data Descriptor for user */
1390 { 0x0, /* segment base address */
1391 0xfffff, /* length - all address space */
1392 SDT_MEMRWA, /* segment type */
1393 SEL_UPL, /* segment descriptor priority level */
1394 1, /* segment descriptor present */
1396 1, /* default 32 vs 16 bit size */
1397 1 /* limit granularity (byte/page units)*/ },
1398 /* GUCODE_SEL 5 64 bit Code Descriptor for user */
1399 { 0x0, /* segment base address */
1400 0xfffff, /* length - all address space */
1401 SDT_MEMERA, /* segment type */
1402 SEL_UPL, /* segment descriptor priority level */
1403 1, /* segment descriptor present */
1405 0, /* default 32 vs 16 bit size */
1406 1 /* limit granularity (byte/page units)*/ },
1407 /* GPROC0_SEL 6 Proc 0 Tss Descriptor */
1409 0x0, /* segment base address */
1410 sizeof(struct x86_64tss)-1,/* length - all address space */
1411 SDT_SYSTSS, /* segment type */
1412 SEL_KPL, /* segment descriptor priority level */
1413 1, /* segment descriptor present */
1415 0, /* unused - default 32 vs 16 bit size */
1416 0 /* limit granularity (byte/page units)*/ },
1417 /* Actually, the TSS is a system descriptor which is double size */
1418 { 0x0, /* segment base address */
1420 0, /* segment type */
1421 0, /* segment descriptor priority level */
1422 0, /* segment descriptor present */
1424 0, /* default 32 vs 16 bit size */
1425 0 /* limit granularity (byte/page units)*/ },
1426 /* GUGS32_SEL 8 32 bit GS Descriptor for user */
1427 { 0x0, /* segment base address */
1428 0xfffff, /* length - all address space */
1429 SDT_MEMRWA, /* segment type */
1430 SEL_UPL, /* segment descriptor priority level */
1431 1, /* segment descriptor present */
1433 1, /* default 32 vs 16 bit size */
1434 1 /* limit granularity (byte/page units)*/ },
1438 setidt_global(int idx, inthand_t *func, int typ, int dpl, int ist)
1442 for (cpu = 0; cpu < MAXCPU; ++cpu) {
1443 struct gate_descriptor *ip = &idt_arr[cpu][idx];
1445 ip->gd_looffset = (uintptr_t)func;
1446 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL);
1452 ip->gd_hioffset = ((uintptr_t)func)>>16 ;
1457 setidt(int idx, inthand_t *func, int typ, int dpl, int ist, int cpu)
1459 struct gate_descriptor *ip;
1461 KASSERT(cpu >= 0 && cpu < ncpus, ("invalid cpu %d", cpu));
1463 ip = &idt_arr[cpu][idx];
1464 ip->gd_looffset = (uintptr_t)func;
1465 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL);
1471 ip->gd_hioffset = ((uintptr_t)func)>>16 ;
1474 #define IDTVEC(name) __CONCAT(X,name)
1477 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl),
1478 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm),
1479 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot),
1480 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align),
1481 IDTVEC(xmm), IDTVEC(dblfault),
1482 IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
1484 #ifdef DEBUG_INTERRUPTS
1485 extern inthand_t *Xrsvdary[256];
1489 sdtossd(struct user_segment_descriptor *sd, struct soft_segment_descriptor *ssd)
1491 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase;
1492 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit;
1493 ssd->ssd_type = sd->sd_type;
1494 ssd->ssd_dpl = sd->sd_dpl;
1495 ssd->ssd_p = sd->sd_p;
1496 ssd->ssd_def32 = sd->sd_def32;
1497 ssd->ssd_gran = sd->sd_gran;
1501 ssdtosd(struct soft_segment_descriptor *ssd, struct user_segment_descriptor *sd)
1504 sd->sd_lobase = (ssd->ssd_base) & 0xffffff;
1505 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff;
1506 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff;
1507 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf;
1508 sd->sd_type = ssd->ssd_type;
1509 sd->sd_dpl = ssd->ssd_dpl;
1510 sd->sd_p = ssd->ssd_p;
1511 sd->sd_long = ssd->ssd_long;
1512 sd->sd_def32 = ssd->ssd_def32;
1513 sd->sd_gran = ssd->ssd_gran;
1517 ssdtosyssd(struct soft_segment_descriptor *ssd,
1518 struct system_segment_descriptor *sd)
1521 sd->sd_lobase = (ssd->ssd_base) & 0xffffff;
1522 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful;
1523 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff;
1524 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf;
1525 sd->sd_type = ssd->ssd_type;
1526 sd->sd_dpl = ssd->ssd_dpl;
1527 sd->sd_p = ssd->ssd_p;
1528 sd->sd_gran = ssd->ssd_gran;
1532 * Populate the (physmap) array with base/bound pairs describing the
1533 * available physical memory in the system, then test this memory and
1534 * build the phys_avail array describing the actually-available memory.
1536 * If we cannot accurately determine the physical memory map, then use
1537 * value from the 0xE801 call, and failing that, the RTC.
1539 * Total memory size may be set by the kernel environment variable
1540 * hw.physmem or the compile-time define MAXMEM.
1542 * Memory is aligned to PHYSMAP_ALIGN which must be a multiple
1543 * of PAGE_SIZE. This also greatly reduces the memory test time
1544 * which would otherwise be excessive on machines with > 8G of ram.
1546 * XXX first should be vm_paddr_t.
1549 #define PHYSMAP_ALIGN (vm_paddr_t)(128 * 1024)
1550 #define PHYSMAP_ALIGN_MASK (vm_paddr_t)(PHYSMAP_ALIGN - 1)
1553 getmemsize(caddr_t kmdp, u_int64_t first)
1555 int off, physmap_idx, pa_indx, da_indx;
1557 vm_paddr_t physmap[PHYSMAP_SIZE];
1559 vm_paddr_t msgbuf_size;
1560 u_long physmem_tunable;
1562 struct bios_smap *smapbase, *smap, *smapend;
1564 quad_t dcons_addr, dcons_size;
1566 bzero(physmap, sizeof(physmap));
1570 * get memory map from INT 15:E820, kindly supplied by the loader.
1572 * subr_module.c says:
1573 * "Consumer may safely assume that size value precedes data."
1574 * ie: an int32_t immediately precedes smap.
1576 smapbase = (struct bios_smap *)preload_search_info(kmdp,
1577 MODINFO_METADATA | MODINFOMD_SMAP);
1578 if (smapbase == NULL)
1579 panic("No BIOS smap info from loader!");
1581 smapsize = *((u_int32_t *)smapbase - 1);
1582 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize);
1584 for (smap = smapbase; smap < smapend; smap++) {
1585 if (boothowto & RB_VERBOSE)
1586 kprintf("SMAP type=%02x base=%016lx len=%016lx\n",
1587 smap->type, smap->base, smap->length);
1589 if (smap->type != SMAP_TYPE_MEMORY)
1592 if (smap->length == 0)
1595 for (i = 0; i <= physmap_idx; i += 2) {
1596 if (smap->base < physmap[i + 1]) {
1597 if (boothowto & RB_VERBOSE) {
1598 kprintf("Overlapping or non-monotonic "
1599 "memory region, ignoring "
1605 if (i <= physmap_idx)
1608 Realmem += smap->length;
1610 if (smap->base == physmap[physmap_idx + 1]) {
1611 physmap[physmap_idx + 1] += smap->length;
1616 if (physmap_idx == PHYSMAP_SIZE) {
1617 kprintf("Too many segments in the physical "
1618 "address map, giving up\n");
1621 physmap[physmap_idx] = smap->base;
1622 physmap[physmap_idx + 1] = smap->base + smap->length;
1625 base_memory = physmap[1] / 1024;
1626 /* make hole for AP bootstrap code */
1627 physmap[1] = mp_bootaddress(base_memory);
1629 /* Save EBDA address, if any */
1630 ebda_addr = (u_long)(*(u_short *)(KERNBASE + 0x40e));
1634 * Maxmem isn't the "maximum memory", it's one larger than the
1635 * highest page of the physical address space. It should be
1636 * called something like "Maxphyspage". We may adjust this
1637 * based on ``hw.physmem'' and the results of the memory test.
1639 Maxmem = atop(physmap[physmap_idx + 1]);
1642 Maxmem = MAXMEM / 4;
1645 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable))
1646 Maxmem = atop(physmem_tunable);
1649 * Don't allow MAXMEM or hw.physmem to extend the amount of memory
1652 if (Maxmem > atop(physmap[physmap_idx + 1]))
1653 Maxmem = atop(physmap[physmap_idx + 1]);
1656 * Blowing out the DMAP will blow up the system.
1658 if (Maxmem > atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS)) {
1659 kprintf("Limiting Maxmem due to DMAP size\n");
1660 Maxmem = atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS);
1663 if (atop(physmap[physmap_idx + 1]) != Maxmem &&
1664 (boothowto & RB_VERBOSE)) {
1665 kprintf("Physical memory use set to %ldK\n", Maxmem * 4);
1669 * Call pmap initialization to make new kernel address space
1673 pmap_bootstrap(&first);
1674 physmap[0] = PAGE_SIZE;
1677 * Align the physmap to PHYSMAP_ALIGN and cut out anything
1680 for (i = j = 0; i <= physmap_idx; i += 2) {
1681 if (physmap[i+1] > ptoa(Maxmem))
1682 physmap[i+1] = ptoa(Maxmem);
1683 physmap[i] = (physmap[i] + PHYSMAP_ALIGN_MASK) &
1684 ~PHYSMAP_ALIGN_MASK;
1685 physmap[i+1] = physmap[i+1] & ~PHYSMAP_ALIGN_MASK;
1687 physmap[j] = physmap[i];
1688 physmap[j+1] = physmap[i+1];
1690 if (physmap[i] < physmap[i+1])
1693 physmap_idx = j - 2;
1696 * Align anything else used in the validation loop.
1698 first = (first + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK;
1701 * Size up each available chunk of physical memory.
1705 phys_avail[pa_indx++] = physmap[0];
1706 phys_avail[pa_indx] = physmap[0];
1707 dump_avail[da_indx] = physmap[0];
1711 * Get dcons buffer address
1713 if (kgetenv_quad("dcons.addr", &dcons_addr) == 0 ||
1714 kgetenv_quad("dcons.size", &dcons_size) == 0)
1718 * Validate the physical memory. The physical memory segments
1719 * have already been aligned to PHYSMAP_ALIGN which is a multiple
1722 for (i = 0; i <= physmap_idx; i += 2) {
1725 end = physmap[i + 1];
1727 for (pa = physmap[i]; pa < end; pa += PHYSMAP_ALIGN) {
1728 int tmp, page_bad, full;
1729 int *ptr = (int *)CADDR1;
1733 * block out kernel memory as not available.
1735 if (pa >= 0x200000 && pa < first)
1739 * block out dcons buffer
1742 && pa >= trunc_page(dcons_addr)
1743 && pa < dcons_addr + dcons_size) {
1750 * map page into kernel: valid, read/write,non-cacheable
1753 kernel_pmap.pmap_bits[PG_V_IDX] |
1754 kernel_pmap.pmap_bits[PG_RW_IDX] |
1755 kernel_pmap.pmap_bits[PG_N_IDX];
1760 * Test for alternating 1's and 0's
1762 *(volatile int *)ptr = 0xaaaaaaaa;
1764 if (*(volatile int *)ptr != 0xaaaaaaaa)
1767 * Test for alternating 0's and 1's
1769 *(volatile int *)ptr = 0x55555555;
1771 if (*(volatile int *)ptr != 0x55555555)
1776 *(volatile int *)ptr = 0xffffffff;
1778 if (*(volatile int *)ptr != 0xffffffff)
1783 *(volatile int *)ptr = 0x0;
1785 if (*(volatile int *)ptr != 0x0)
1788 * Restore original value.
1793 * Adjust array of valid/good pages.
1795 if (page_bad == TRUE)
1798 * If this good page is a continuation of the
1799 * previous set of good pages, then just increase
1800 * the end pointer. Otherwise start a new chunk.
1801 * Note that "end" points one higher than end,
1802 * making the range >= start and < end.
1803 * If we're also doing a speculative memory
1804 * test and we at or past the end, bump up Maxmem
1805 * so that we keep going. The first bad page
1806 * will terminate the loop.
1808 if (phys_avail[pa_indx] == pa) {
1809 phys_avail[pa_indx] += PHYSMAP_ALIGN;
1812 if (pa_indx == PHYS_AVAIL_ARRAY_END) {
1814 "Too many holes in the physical address space, giving up\n");
1819 phys_avail[pa_indx++] = pa;
1820 phys_avail[pa_indx] = pa + PHYSMAP_ALIGN;
1822 physmem += PHYSMAP_ALIGN / PAGE_SIZE;
1824 if (dump_avail[da_indx] == pa) {
1825 dump_avail[da_indx] += PHYSMAP_ALIGN;
1828 if (da_indx == DUMP_AVAIL_ARRAY_END) {
1832 dump_avail[da_indx++] = pa;
1833 dump_avail[da_indx] = pa + PHYSMAP_ALIGN;
1844 * The last chunk must contain at least one page plus the message
1845 * buffer to avoid complicating other code (message buffer address
1846 * calculation, etc.).
1848 msgbuf_size = (MSGBUF_SIZE + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK;
1850 while (phys_avail[pa_indx - 1] + PHYSMAP_ALIGN +
1851 msgbuf_size >= phys_avail[pa_indx]) {
1852 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]);
1853 phys_avail[pa_indx--] = 0;
1854 phys_avail[pa_indx--] = 0;
1857 Maxmem = atop(phys_avail[pa_indx]);
1859 /* Trim off space for the message buffer. */
1860 phys_avail[pa_indx] -= msgbuf_size;
1862 avail_end = phys_avail[pa_indx];
1864 /* Map the message buffer. */
1865 for (off = 0; off < msgbuf_size; off += PAGE_SIZE) {
1866 pmap_kenter((vm_offset_t)msgbufp + off,
1867 phys_avail[pa_indx] + off);
1871 struct machintr_abi MachIntrABI;
1882 * 7 Device Not Available (x87)
1884 * 9 Coprocessor Segment overrun (unsupported, reserved)
1886 * 11 Segment not present
1888 * 13 General Protection
1891 * 16 x87 FP Exception pending
1892 * 17 Alignment Check
1894 * 19 SIMD floating point
1896 * 32-255 INTn/external sources
1899 hammer_time(u_int64_t modulep, u_int64_t physfree)
1902 int gsel_tss, x, cpu;
1904 int metadata_missing, off;
1906 struct mdglobaldata *gd;
1910 * Prevent lowering of the ipl if we call tsleep() early.
1912 gd = &CPU_prvspace[0].mdglobaldata;
1913 bzero(gd, sizeof(*gd));
1916 * Note: on both UP and SMP curthread must be set non-NULL
1917 * early in the boot sequence because the system assumes
1918 * that 'curthread' is never NULL.
1921 gd->mi.gd_curthread = &thread0;
1922 thread0.td_gd = &gd->mi;
1924 atdevbase = ISA_HOLE_START + PTOV_OFFSET;
1927 metadata_missing = 0;
1928 if (bootinfo.bi_modulep) {
1929 preload_metadata = (caddr_t)bootinfo.bi_modulep + KERNBASE;
1930 preload_bootstrap_relocate(KERNBASE);
1932 metadata_missing = 1;
1934 if (bootinfo.bi_envp)
1935 kern_envp = (caddr_t)bootinfo.bi_envp + KERNBASE;
1938 preload_metadata = (caddr_t)(uintptr_t)(modulep + PTOV_OFFSET);
1939 preload_bootstrap_relocate(PTOV_OFFSET);
1940 kmdp = preload_search_by_type("elf kernel");
1942 kmdp = preload_search_by_type("elf64 kernel");
1943 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int);
1944 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + PTOV_OFFSET;
1946 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t);
1947 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t);
1950 if (boothowto & RB_VERBOSE)
1954 * Default MachIntrABI to ICU
1956 MachIntrABI = MachIntrABI_ICU;
1959 * start with one cpu. Note: with one cpu, ncpus2_shift, ncpus2_mask,
1960 * and ncpus_fit_mask remain 0.
1965 /* Init basic tunables, hz etc */
1969 * make gdt memory segments
1971 gdt_segs[GPROC0_SEL].ssd_base =
1972 (uintptr_t) &CPU_prvspace[0].mdglobaldata.gd_common_tss;
1974 gd->mi.gd_prvspace = &CPU_prvspace[0];
1976 for (x = 0; x < NGDT; x++) {
1977 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
1978 ssdtosd(&gdt_segs[x], &gdt[x]);
1980 ssdtosyssd(&gdt_segs[GPROC0_SEL],
1981 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]);
1983 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
1984 r_gdt.rd_base = (long) gdt;
1987 wrmsr(MSR_FSBASE, 0); /* User value */
1988 wrmsr(MSR_GSBASE, (u_int64_t)&gd->mi);
1989 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */
1991 mi_gdinit(&gd->mi, 0);
1993 proc0paddr = proc0paddr_buff;
1994 mi_proc0init(&gd->mi, proc0paddr);
1995 safepri = TDPRI_MAX;
1997 /* spinlocks and the BGL */
2001 for (x = 0; x < NIDT; x++)
2002 setidt_global(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0);
2003 setidt_global(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0);
2004 setidt_global(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 0);
2005 setidt_global(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 1);
2006 setidt_global(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0);
2007 setidt_global(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0);
2008 setidt_global(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0);
2009 setidt_global(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0);
2010 setidt_global(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0);
2011 setidt_global(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1);
2012 setidt_global(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0);
2013 setidt_global(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0);
2014 setidt_global(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0);
2015 setidt_global(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0);
2016 setidt_global(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0);
2017 setidt_global(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0);
2018 setidt_global(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0);
2019 setidt_global(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0);
2020 setidt_global(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0);
2021 setidt_global(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0);
2023 for (cpu = 0; cpu < MAXCPU; ++cpu) {
2024 r_idt_arr[cpu].rd_limit = sizeof(idt_arr[cpu]) - 1;
2025 r_idt_arr[cpu].rd_base = (long) &idt_arr[cpu][0];
2028 lidt(&r_idt_arr[0]);
2031 * Initialize the console before we print anything out.
2036 if (metadata_missing)
2037 kprintf("WARNING: loader(8) metadata is missing!\n");
2047 * Initialize IRQ mapping
2050 * SHOULD be after elcr_probe()
2052 MachIntrABI_ICU.initmap();
2053 MachIntrABI_IOAPIC.initmap();
2057 if (boothowto & RB_KDB)
2058 Debugger("Boot flags requested debugger");
2062 finishidentcpu(); /* Final stage of CPU initialization */
2063 setidt(6, &IDTVEC(ill), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2064 setidt(13, &IDTVEC(prot), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2066 identify_cpu(); /* Final stage of CPU initialization */
2067 initializecpu(0); /* Initialize CPU registers */
2069 TUNABLE_INT_FETCH("hw.apic_io_enable", &ioapic_enable); /* for compat */
2070 TUNABLE_INT_FETCH("hw.ioapic_enable", &ioapic_enable);
2071 TUNABLE_INT_FETCH("hw.lapic_enable", &lapic_enable);
2074 * Some of the virtual machines do not work w/ I/O APIC
2075 * enabled. If the user does not explicitly enable or
2076 * disable the I/O APIC (ioapic_enable < 0), then we
2077 * disable I/O APIC on all virtual machines.
2080 * This must be done after identify_cpu(), which sets
2083 if (ioapic_enable < 0) {
2084 if (cpu_feature2 & CPUID2_VMM)
2090 /* make an initial tss so cpu can get interrupt stack on syscall! */
2091 gd->gd_common_tss.tss_rsp0 =
2092 (register_t)(thread0.td_kstack +
2093 KSTACK_PAGES * PAGE_SIZE - sizeof(struct pcb));
2094 /* Ensure the stack is aligned to 16 bytes */
2095 gd->gd_common_tss.tss_rsp0 &= ~(register_t)0xF;
2097 /* double fault stack */
2098 gd->gd_common_tss.tss_ist1 =
2099 (long)&gd->mi.gd_prvspace->idlestack[
2100 sizeof(gd->mi.gd_prvspace->idlestack)];
2102 /* Set the IO permission bitmap (empty due to tss seg limit) */
2103 gd->gd_common_tss.tss_iobase = sizeof(struct x86_64tss);
2105 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
2106 gd->gd_tss_gdt = &gdt[GPROC0_SEL];
2107 gd->gd_common_tssd = *gd->gd_tss_gdt;
2110 /* Set up the fast syscall stuff */
2111 msr = rdmsr(MSR_EFER) | EFER_SCE;
2112 wrmsr(MSR_EFER, msr);
2113 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
2114 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
2115 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
2116 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
2117 wrmsr(MSR_STAR, msr);
2118 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D|PSL_IOPL);
2120 getmemsize(kmdp, physfree);
2121 init_param2(physmem);
2123 /* now running on new page tables, configured,and u/iom is accessible */
2125 /* Map the message buffer. */
2127 for (off = 0; off < round_page(MSGBUF_SIZE); off += PAGE_SIZE)
2128 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off);
2131 msgbufinit(msgbufp, MSGBUF_SIZE);
2134 /* transfer to user mode */
2136 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL);
2137 _udatasel = GSEL(GUDATA_SEL, SEL_UPL);
2138 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL);
2144 /* setup proc 0's pcb */
2145 thread0.td_pcb->pcb_flags = 0;
2146 thread0.td_pcb->pcb_cr3 = KPML4phys;
2147 thread0.td_pcb->pcb_ext = NULL;
2148 lwp0.lwp_md.md_regs = &proc0_tf; /* XXX needed? */
2150 /* Location of kernel stack for locore */
2151 return ((u_int64_t)thread0.td_pcb);
2155 * Initialize machine-dependant portions of the global data structure.
2156 * Note that the global data area and cpu0's idlestack in the private
2157 * data space were allocated in locore.
2159 * Note: the idlethread's cpl is 0
2161 * WARNING! Called from early boot, 'mycpu' may not work yet.
2164 cpu_gdinit(struct mdglobaldata *gd, int cpu)
2167 gd->mi.gd_curthread = &gd->mi.gd_idlethread;
2169 lwkt_init_thread(&gd->mi.gd_idlethread,
2170 gd->mi.gd_prvspace->idlestack,
2171 sizeof(gd->mi.gd_prvspace->idlestack),
2173 lwkt_set_comm(&gd->mi.gd_idlethread, "idle_%d", cpu);
2174 gd->mi.gd_idlethread.td_switch = cpu_lwkt_switch;
2175 gd->mi.gd_idlethread.td_sp -= sizeof(void *);
2176 *(void **)gd->mi.gd_idlethread.td_sp = cpu_idle_restore;
2180 is_globaldata_space(vm_offset_t saddr, vm_offset_t eaddr)
2182 if (saddr >= (vm_offset_t)&CPU_prvspace[0] &&
2183 eaddr <= (vm_offset_t)&CPU_prvspace[MAXCPU]) {
2186 if (saddr >= DMAP_MIN_ADDRESS && eaddr <= DMAP_MAX_ADDRESS)
2192 globaldata_find(int cpu)
2194 KKASSERT(cpu >= 0 && cpu < ncpus);
2195 return(&CPU_prvspace[cpu].mdglobaldata.mi);
2199 ptrace_set_pc(struct lwp *lp, unsigned long addr)
2201 lp->lwp_md.md_regs->tf_rip = addr;
2206 ptrace_single_step(struct lwp *lp)
2208 lp->lwp_md.md_regs->tf_rflags |= PSL_T;
2213 fill_regs(struct lwp *lp, struct reg *regs)
2215 struct trapframe *tp;
2217 if ((tp = lp->lwp_md.md_regs) == NULL)
2219 bcopy(&tp->tf_rdi, ®s->r_rdi, sizeof(*regs));
2224 set_regs(struct lwp *lp, struct reg *regs)
2226 struct trapframe *tp;
2228 tp = lp->lwp_md.md_regs;
2229 if (!EFL_SECURE(regs->r_rflags, tp->tf_rflags) ||
2230 !CS_SECURE(regs->r_cs))
2232 bcopy(®s->r_rdi, &tp->tf_rdi, sizeof(*regs));
2237 #ifndef CPU_DISABLE_SSE
2239 fill_fpregs_xmm(struct savexmm *sv_xmm, struct save87 *sv_87)
2241 struct env87 *penv_87 = &sv_87->sv_env;
2242 struct envxmm *penv_xmm = &sv_xmm->sv_env;
2245 /* FPU control/status */
2246 penv_87->en_cw = penv_xmm->en_cw;
2247 penv_87->en_sw = penv_xmm->en_sw;
2248 penv_87->en_tw = penv_xmm->en_tw;
2249 penv_87->en_fip = penv_xmm->en_fip;
2250 penv_87->en_fcs = penv_xmm->en_fcs;
2251 penv_87->en_opcode = penv_xmm->en_opcode;
2252 penv_87->en_foo = penv_xmm->en_foo;
2253 penv_87->en_fos = penv_xmm->en_fos;
2256 for (i = 0; i < 8; ++i)
2257 sv_87->sv_ac[i] = sv_xmm->sv_fp[i].fp_acc;
2261 set_fpregs_xmm(struct save87 *sv_87, struct savexmm *sv_xmm)
2263 struct env87 *penv_87 = &sv_87->sv_env;
2264 struct envxmm *penv_xmm = &sv_xmm->sv_env;
2267 /* FPU control/status */
2268 penv_xmm->en_cw = penv_87->en_cw;
2269 penv_xmm->en_sw = penv_87->en_sw;
2270 penv_xmm->en_tw = penv_87->en_tw;
2271 penv_xmm->en_fip = penv_87->en_fip;
2272 penv_xmm->en_fcs = penv_87->en_fcs;
2273 penv_xmm->en_opcode = penv_87->en_opcode;
2274 penv_xmm->en_foo = penv_87->en_foo;
2275 penv_xmm->en_fos = penv_87->en_fos;
2278 for (i = 0; i < 8; ++i)
2279 sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i];
2281 #endif /* CPU_DISABLE_SSE */
2284 fill_fpregs(struct lwp *lp, struct fpreg *fpregs)
2286 if (lp->lwp_thread == NULL || lp->lwp_thread->td_pcb == NULL)
2288 #ifndef CPU_DISABLE_SSE
2290 fill_fpregs_xmm(&lp->lwp_thread->td_pcb->pcb_save.sv_xmm,
2291 (struct save87 *)fpregs);
2294 #endif /* CPU_DISABLE_SSE */
2295 bcopy(&lp->lwp_thread->td_pcb->pcb_save.sv_87, fpregs, sizeof *fpregs);
2300 set_fpregs(struct lwp *lp, struct fpreg *fpregs)
2302 #ifndef CPU_DISABLE_SSE
2304 set_fpregs_xmm((struct save87 *)fpregs,
2305 &lp->lwp_thread->td_pcb->pcb_save.sv_xmm);
2308 #endif /* CPU_DISABLE_SSE */
2309 bcopy(fpregs, &lp->lwp_thread->td_pcb->pcb_save.sv_87, sizeof *fpregs);
2314 fill_dbregs(struct lwp *lp, struct dbreg *dbregs)
2319 dbregs->dr[0] = rdr0();
2320 dbregs->dr[1] = rdr1();
2321 dbregs->dr[2] = rdr2();
2322 dbregs->dr[3] = rdr3();
2323 dbregs->dr[4] = rdr4();
2324 dbregs->dr[5] = rdr5();
2325 dbregs->dr[6] = rdr6();
2326 dbregs->dr[7] = rdr7();
2329 if (lp->lwp_thread == NULL || (pcb = lp->lwp_thread->td_pcb) == NULL)
2331 dbregs->dr[0] = pcb->pcb_dr0;
2332 dbregs->dr[1] = pcb->pcb_dr1;
2333 dbregs->dr[2] = pcb->pcb_dr2;
2334 dbregs->dr[3] = pcb->pcb_dr3;
2337 dbregs->dr[6] = pcb->pcb_dr6;
2338 dbregs->dr[7] = pcb->pcb_dr7;
2343 set_dbregs(struct lwp *lp, struct dbreg *dbregs)
2346 load_dr0(dbregs->dr[0]);
2347 load_dr1(dbregs->dr[1]);
2348 load_dr2(dbregs->dr[2]);
2349 load_dr3(dbregs->dr[3]);
2350 load_dr4(dbregs->dr[4]);
2351 load_dr5(dbregs->dr[5]);
2352 load_dr6(dbregs->dr[6]);
2353 load_dr7(dbregs->dr[7]);
2356 struct ucred *ucred;
2358 uint64_t mask1, mask2;
2361 * Don't let an illegal value for dr7 get set. Specifically,
2362 * check for undefined settings. Setting these bit patterns
2363 * result in undefined behaviour and can lead to an unexpected
2366 /* JG this loop looks unreadable */
2367 /* Check 4 2-bit fields for invalid patterns.
2368 * These fields are R/Wi, for i = 0..3
2370 /* Is 10 in LENi allowed when running in compatibility mode? */
2371 /* Pattern 10 in R/Wi might be used to indicate
2372 * breakpoint on I/O. Further analysis should be
2373 * carried to decide if it is safe and useful to
2374 * provide access to that capability
2376 for (i = 0, mask1 = 0x3<<16, mask2 = 0x2<<16; i < 4;
2377 i++, mask1 <<= 4, mask2 <<= 4)
2378 if ((dbregs->dr[7] & mask1) == mask2)
2381 pcb = lp->lwp_thread->td_pcb;
2382 ucred = lp->lwp_proc->p_ucred;
2385 * Don't let a process set a breakpoint that is not within the
2386 * process's address space. If a process could do this, it
2387 * could halt the system by setting a breakpoint in the kernel
2388 * (if ddb was enabled). Thus, we need to check to make sure
2389 * that no breakpoints are being enabled for addresses outside
2390 * process's address space, unless, perhaps, we were called by
2393 * XXX - what about when the watched area of the user's
2394 * address space is written into from within the kernel
2395 * ... wouldn't that still cause a breakpoint to be generated
2396 * from within kernel mode?
2399 if (priv_check_cred(ucred, PRIV_ROOT, 0) != 0) {
2400 if (dbregs->dr[7] & 0x3) {
2401 /* dr0 is enabled */
2402 if (dbregs->dr[0] >= VM_MAX_USER_ADDRESS)
2406 if (dbregs->dr[7] & (0x3<<2)) {
2407 /* dr1 is enabled */
2408 if (dbregs->dr[1] >= VM_MAX_USER_ADDRESS)
2412 if (dbregs->dr[7] & (0x3<<4)) {
2413 /* dr2 is enabled */
2414 if (dbregs->dr[2] >= VM_MAX_USER_ADDRESS)
2418 if (dbregs->dr[7] & (0x3<<6)) {
2419 /* dr3 is enabled */
2420 if (dbregs->dr[3] >= VM_MAX_USER_ADDRESS)
2425 pcb->pcb_dr0 = dbregs->dr[0];
2426 pcb->pcb_dr1 = dbregs->dr[1];
2427 pcb->pcb_dr2 = dbregs->dr[2];
2428 pcb->pcb_dr3 = dbregs->dr[3];
2429 pcb->pcb_dr6 = dbregs->dr[6];
2430 pcb->pcb_dr7 = dbregs->dr[7];
2432 pcb->pcb_flags |= PCB_DBREGS;
2439 * Return > 0 if a hardware breakpoint has been hit, and the
2440 * breakpoint was in user space. Return 0, otherwise.
2443 user_dbreg_trap(void)
2445 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */
2446 u_int64_t bp; /* breakpoint bits extracted from dr6 */
2447 int nbp; /* number of breakpoints that triggered */
2448 caddr_t addr[4]; /* breakpoint addresses */
2452 if ((dr7 & 0xff) == 0) {
2454 * all GE and LE bits in the dr7 register are zero,
2455 * thus the trap couldn't have been caused by the
2456 * hardware debug registers
2467 * None of the breakpoint bits are set meaning this
2468 * trap was not caused by any of the debug registers
2474 * at least one of the breakpoints were hit, check to see
2475 * which ones and if any of them are user space addresses
2479 addr[nbp++] = (caddr_t)rdr0();
2482 addr[nbp++] = (caddr_t)rdr1();
2485 addr[nbp++] = (caddr_t)rdr2();
2488 addr[nbp++] = (caddr_t)rdr3();
2491 for (i=0; i<nbp; i++) {
2493 (caddr_t)VM_MAX_USER_ADDRESS) {
2495 * addr[i] is in user space
2502 * None of the breakpoints are in user space.
2510 Debugger(const char *msg)
2512 kprintf("Debugger(\"%s\") called.\n", msg);
2519 * Provide inb() and outb() as functions. They are normally only
2520 * available as macros calling inlined functions, thus cannot be
2521 * called inside DDB.
2523 * The actual code is stolen from <machine/cpufunc.h>, and de-inlined.
2529 /* silence compiler warnings */
2531 void outb(u_int, u_char);
2538 * We use %%dx and not %1 here because i/o is done at %dx and not at
2539 * %edx, while gcc generates inferior code (movw instead of movl)
2540 * if we tell it to load (u_short) port.
2542 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port));
2547 outb(u_int port, u_char data)
2551 * Use an unnecessary assignment to help gcc's register allocator.
2552 * This make a large difference for gcc-1.40 and a tiny difference
2553 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for
2554 * best results. gcc-2.6.0 can't handle this.
2557 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port));
2565 * initialize all the SMP locks
2568 /* critical region when masking or unmasking interupts */
2569 struct spinlock_deprecated imen_spinlock;
2571 /* critical region for old style disable_intr/enable_intr */
2572 struct spinlock_deprecated mpintr_spinlock;
2574 /* critical region around INTR() routines */
2575 struct spinlock_deprecated intr_spinlock;
2577 /* lock region used by kernel profiling */
2578 struct spinlock_deprecated mcount_spinlock;
2580 /* locks com (tty) data/hardware accesses: a FASTINTR() */
2581 struct spinlock_deprecated com_spinlock;
2583 /* lock regions around the clock hardware */
2584 struct spinlock_deprecated clock_spinlock;
2590 * Get the initial mplock with a count of 1 for the BSP.
2591 * This uses a LOGICAL cpu ID, ie BSP == 0.
2593 cpu_get_initial_mplock();
2595 spin_lock_init(&mcount_spinlock);
2596 spin_lock_init(&intr_spinlock);
2597 spin_lock_init(&mpintr_spinlock);
2598 spin_lock_init(&imen_spinlock);
2599 spin_lock_init(&com_spinlock);
2600 spin_lock_init(&clock_spinlock);
2602 /* our token pool needs to work early */
2603 lwkt_token_pool_init();
2607 cpu_mwait_hint_valid(uint32_t hint)
2611 cx_idx = MWAIT_EAX_TO_CX(hint);
2612 if (cx_idx >= CPU_MWAIT_CX_MAX)
2615 sub = MWAIT_EAX_TO_CX_SUB(hint);
2616 if (sub >= cpu_mwait_cx_info[cx_idx].subcnt)
2623 cpu_mwait_cx_no_bmsts(void)
2625 atomic_clear_int(&cpu_mwait_c3_preamble, CPU_MWAIT_C3_PREAMBLE_BM_STS);
2629 cpu_mwait_cx_select_sysctl(SYSCTL_HANDLER_ARGS, int *hint0,
2630 boolean_t allow_auto)
2632 int error, cx_idx, old_cx_idx, sub = 0, hint;
2633 char name[16], *ptr, *start;
2637 old_cx_idx = MWAIT_EAX_TO_CX(hint);
2638 sub = MWAIT_EAX_TO_CX_SUB(hint);
2639 } else if (hint == CPU_MWAIT_HINT_AUTO) {
2640 old_cx_idx = allow_auto ? CPU_MWAIT_C2 : CPU_MWAIT_CX_MAX;
2641 } else if (hint == CPU_MWAIT_HINT_AUTODEEP) {
2642 old_cx_idx = allow_auto ? CPU_MWAIT_C3 : CPU_MWAIT_CX_MAX;
2644 old_cx_idx = CPU_MWAIT_CX_MAX;
2647 if ((cpu_feature2 & CPUID2_MON) == 0 ||
2648 (cpu_mwait_feature & CPUID_MWAIT_EXT) == 0)
2649 strlcpy(name, "NONE", sizeof(name));
2650 else if (allow_auto && hint == CPU_MWAIT_HINT_AUTO)
2651 strlcpy(name, "AUTO", sizeof(name));
2652 else if (allow_auto && hint == CPU_MWAIT_HINT_AUTODEEP)
2653 strlcpy(name, "AUTODEEP", sizeof(name));
2654 else if (old_cx_idx >= CPU_MWAIT_CX_MAX ||
2655 sub >= cpu_mwait_cx_info[old_cx_idx].subcnt)
2656 strlcpy(name, "INVALID", sizeof(name));
2658 ksnprintf(name, sizeof(name), "C%d/%d", old_cx_idx, sub);
2660 error = sysctl_handle_string(oidp, name, sizeof(name), req);
2661 if (error != 0 || req->newptr == NULL)
2664 if ((cpu_feature2 & CPUID2_MON) == 0 ||
2665 (cpu_mwait_feature & CPUID_MWAIT_EXT) == 0)
2668 if (allow_auto && strcmp(name, "AUTO") == 0) {
2669 hint = CPU_MWAIT_HINT_AUTO;
2670 cx_idx = CPU_MWAIT_C2;
2673 if (allow_auto && strcmp(name, "AUTODEEP") == 0) {
2674 hint = CPU_MWAIT_HINT_AUTODEEP;
2675 cx_idx = CPU_MWAIT_C3;
2679 if (strlen(name) < 4 || toupper(name[0]) != 'C')
2684 cx_idx = strtol(start, &ptr, 10);
2685 if (ptr == start || *ptr != '/')
2687 if (cx_idx < 0 || cx_idx >= CPU_MWAIT_CX_MAX)
2693 sub = strtol(start, &ptr, 10);
2696 if (sub < 0 || sub >= cpu_mwait_cx_info[cx_idx].subcnt)
2699 hint = MWAIT_EAX_HINT(cx_idx, sub);
2701 if (cx_idx >= CPU_MWAIT_C3 && cpu_mwait_c3_preamble)
2703 if (old_cx_idx < CPU_MWAIT_C3 && cx_idx >= CPU_MWAIT_C3) {
2704 error = cputimer_intr_powersave_addreq();
2707 } else if (old_cx_idx >= CPU_MWAIT_C3 && cx_idx < CPU_MWAIT_C3) {
2708 cputimer_intr_powersave_remreq();
2716 cpu_mwait_cx_idle_sysctl(SYSCTL_HANDLER_ARGS)
2720 lwkt_serialize_enter(&cpu_mwait_cx_slize);
2721 error = cpu_mwait_cx_select_sysctl(oidp, arg1, arg2, req,
2722 &cpu_mwait_halt, TRUE);
2723 lwkt_serialize_exit(&cpu_mwait_cx_slize);
2728 cpu_mwait_cx_spin_sysctl(SYSCTL_HANDLER_ARGS)
2732 lwkt_serialize_enter(&cpu_mwait_cx_slize);
2733 error = cpu_mwait_cx_select_sysctl(oidp, arg1, arg2, req,
2734 &cpu_mwait_spin, FALSE);
2735 lwkt_serialize_exit(&cpu_mwait_cx_slize);