aic79xx.c:
[dragonfly.git] / sys / dev / disk / aic7xxx / aic7xxx.c
1 /*
2  * Core routines and tables shareable across OS platforms.
3  *
4  * Copyright (c) 1994-2002 Justin T. Gibbs.
5  * Copyright (c) 2000-2002 Adaptec Inc.
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions, and the following disclaimer,
13  *    without modification.
14  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15  *    substantially similar to the "NO WARRANTY" disclaimer below
16  *    ("Disclaimer") and any redistribution must be conditioned upon
17  *    including a substantially similar Disclaimer requirement for further
18  *    binary redistribution.
19  * 3. Neither the names of the above-listed copyright holders nor the names
20  *    of any contributors may be used to endorse or promote products derived
21  *    from this software without specific prior written permission.
22  *
23  * Alternatively, this software may be distributed under the terms of the
24  * GNU General Public License ("GPL") version 2 as published by the Free
25  * Software Foundation.
26  *
27  * NO WARRANTY
28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
37  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38  * POSSIBILITY OF SUCH DAMAGES.
39  *
40  * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.c#147 $
41  *
42  * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx.c,v 1.98 2003/12/19 18:10:59 gibbs Exp $
43  * $DragonFly: src/sys/dev/disk/aic7xxx/aic7xxx.c,v 1.15 2007/07/06 00:01:16 pavalos Exp $
44  */
45
46 #include "aic7xxx_osm.h"
47 #include "aic7xxx_inline.h"
48 #include "aicasm/aicasm_insformat.h"
49
50 /****************************** Softc Data ************************************/
51 struct ahc_softc_tailq ahc_tailq = TAILQ_HEAD_INITIALIZER(ahc_tailq);
52
53 /***************************** Lookup Tables **********************************/
54 char *ahc_chip_names[] =
55 {
56         "NONE",
57         "aic7770",
58         "aic7850",
59         "aic7855",
60         "aic7859",
61         "aic7860",
62         "aic7870",
63         "aic7880",
64         "aic7895",
65         "aic7895C",
66         "aic7890/91",
67         "aic7896/97",
68         "aic7892",
69         "aic7899"
70 };
71 static const u_int num_chip_names = NUM_ELEMENTS(ahc_chip_names);
72
73 /*
74  * Hardware error codes.
75  */
76 struct ahc_hard_error_entry {
77         uint8_t error;
78         char *errmesg;
79 };
80
81 static struct ahc_hard_error_entry ahc_hard_errors[] = {
82         { ILLHADDR,     "Illegal Host Access" },
83         { ILLSADDR,     "Illegal Sequencer Address referenced" },
84         { ILLOPCODE,    "Illegal Opcode in sequencer program" },
85         { SQPARERR,     "Sequencer Parity Error" },
86         { DPARERR,      "Data-path Parity Error" },
87         { MPARERR,      "Scratch or SCB Memory Parity Error" },
88         { PCIERRSTAT,   "PCI Error detected" },
89         { CIOPARERR,    "CIOBUS Parity Error" },
90 };
91 static const u_int num_errors = NUM_ELEMENTS(ahc_hard_errors);
92
93 static struct ahc_phase_table_entry ahc_phase_table[] =
94 {
95         { P_DATAOUT,    MSG_NOOP,               "in Data-out phase"     },
96         { P_DATAIN,     MSG_INITIATOR_DET_ERR,  "in Data-in phase"      },
97         { P_DATAOUT_DT, MSG_NOOP,               "in DT Data-out phase"  },
98         { P_DATAIN_DT,  MSG_INITIATOR_DET_ERR,  "in DT Data-in phase"   },
99         { P_COMMAND,    MSG_NOOP,               "in Command phase"      },
100         { P_MESGOUT,    MSG_NOOP,               "in Message-out phase"  },
101         { P_STATUS,     MSG_INITIATOR_DET_ERR,  "in Status phase"       },
102         { P_MESGIN,     MSG_PARITY_ERROR,       "in Message-in phase"   },
103         { P_BUSFREE,    MSG_NOOP,               "while idle"            },
104         { 0,            MSG_NOOP,               "in unknown phase"      }
105 };
106
107 /*
108  * In most cases we only wish to itterate over real phases, so
109  * exclude the last element from the count.
110  */
111 static const u_int num_phases = NUM_ELEMENTS(ahc_phase_table) - 1;
112
113 /*
114  * Valid SCSIRATE values.  (p. 3-17)
115  * Provides a mapping of tranfer periods in ns to the proper value to
116  * stick in the scsixfer reg.
117  */
118 static struct ahc_syncrate ahc_syncrates[] =
119 {
120       /* ultra2    fast/ultra  period     rate */
121         { 0x42,      0x000,      9,      "80.0" },
122         { 0x03,      0x000,     10,      "40.0" },
123         { 0x04,      0x000,     11,      "33.0" },
124         { 0x05,      0x100,     12,      "20.0" },
125         { 0x06,      0x110,     15,      "16.0" },
126         { 0x07,      0x120,     18,      "13.4" },
127         { 0x08,      0x000,     25,      "10.0" },
128         { 0x19,      0x010,     31,      "8.0"  },
129         { 0x1a,      0x020,     37,      "6.67" },
130         { 0x1b,      0x030,     43,      "5.7"  },
131         { 0x1c,      0x040,     50,      "5.0"  },
132         { 0x00,      0x050,     56,      "4.4"  },
133         { 0x00,      0x060,     62,      "4.0"  },
134         { 0x00,      0x070,     68,      "3.6"  },
135         { 0x00,      0x000,      0,      NULL   }
136 };
137
138 /* Our Sequencer Program */
139 #include "aic7xxx_seq.h"
140
141 /**************************** Function Declarations ***************************/
142 static void             ahc_force_renegotiation(struct ahc_softc *ahc,
143                                                 struct ahc_devinfo *devinfo);
144 static struct ahc_tmode_tstate*
145                         ahc_alloc_tstate(struct ahc_softc *ahc,
146                                          u_int scsi_id, char channel);
147 #ifdef AHC_TARGET_MODE
148 static void             ahc_free_tstate(struct ahc_softc *ahc,
149                                         u_int scsi_id, char channel, int force);
150 #endif
151 static struct ahc_syncrate*
152                         ahc_devlimited_syncrate(struct ahc_softc *ahc,
153                                                 struct ahc_initiator_tinfo *,
154                                                 u_int *period,
155                                                 u_int *ppr_options,
156                                                 role_t role);
157 static void             ahc_update_pending_scbs(struct ahc_softc *ahc);
158 static void             ahc_fetch_devinfo(struct ahc_softc *ahc,
159                                           struct ahc_devinfo *devinfo);
160 static void             ahc_scb_devinfo(struct ahc_softc *ahc,
161                                         struct ahc_devinfo *devinfo,
162                                         struct scb *scb);
163 static void             ahc_assert_atn(struct ahc_softc *ahc);
164 static void             ahc_setup_initiator_msgout(struct ahc_softc *ahc,
165                                                    struct ahc_devinfo *devinfo,
166                                                    struct scb *scb);
167 static void             ahc_build_transfer_msg(struct ahc_softc *ahc,
168                                                struct ahc_devinfo *devinfo);
169 static void             ahc_construct_sdtr(struct ahc_softc *ahc,
170                                            struct ahc_devinfo *devinfo,
171                                            u_int period, u_int offset);
172 static void             ahc_construct_wdtr(struct ahc_softc *ahc,
173                                            struct ahc_devinfo *devinfo,
174                                            u_int bus_width);
175 static void             ahc_construct_ppr(struct ahc_softc *ahc,
176                                           struct ahc_devinfo *devinfo,
177                                           u_int period, u_int offset,
178                                           u_int bus_width, u_int ppr_options);
179 static void             ahc_clear_msg_state(struct ahc_softc *ahc);
180 static void             ahc_handle_proto_violation(struct ahc_softc *ahc);
181 static void             ahc_handle_message_phase(struct ahc_softc *ahc);
182 typedef enum {
183         AHCMSG_1B,
184         AHCMSG_2B,
185         AHCMSG_EXT
186 } ahc_msgtype;
187 static int              ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type,
188                                      u_int msgval, int full);
189 static int              ahc_parse_msg(struct ahc_softc *ahc,
190                                       struct ahc_devinfo *devinfo);
191 static int              ahc_handle_msg_reject(struct ahc_softc *ahc,
192                                               struct ahc_devinfo *devinfo);
193 static void             ahc_handle_ign_wide_residue(struct ahc_softc *ahc,
194                                                 struct ahc_devinfo *devinfo);
195 static void             ahc_reinitialize_dataptrs(struct ahc_softc *ahc);
196 static void             ahc_handle_devreset(struct ahc_softc *ahc,
197                                             struct ahc_devinfo *devinfo,
198                                             cam_status status, char *message,
199                                             int verbose_level);
200 #ifdef AHC_TARGET_MODE
201 static void             ahc_setup_target_msgin(struct ahc_softc *ahc,
202                                                struct ahc_devinfo *devinfo,
203                                                struct scb *scb);
204 #endif
205
206 static bus_dmamap_callback_t    ahc_dmamap_cb; 
207 static void                     ahc_build_free_scb_list(struct ahc_softc *ahc);
208 static int                      ahc_init_scbdata(struct ahc_softc *ahc);
209 static void                     ahc_fini_scbdata(struct ahc_softc *ahc);
210 static void             ahc_qinfifo_requeue(struct ahc_softc *ahc,
211                                             struct scb *prev_scb,
212                                             struct scb *scb);
213 static int              ahc_qinfifo_count(struct ahc_softc *ahc);
214 static u_int            ahc_rem_scb_from_disc_list(struct ahc_softc *ahc,
215                                                    u_int prev, u_int scbptr);
216 static void             ahc_add_curscb_to_free_list(struct ahc_softc *ahc);
217 static u_int            ahc_rem_wscb(struct ahc_softc *ahc,
218                                      u_int scbpos, u_int prev);
219 static void             ahc_reset_current_bus(struct ahc_softc *ahc);
220 #ifdef AHC_DUMP_SEQ
221 static void             ahc_dumpseq(struct ahc_softc *ahc);
222 #endif
223 static int              ahc_loadseq(struct ahc_softc *ahc);
224 static int              ahc_check_patch(struct ahc_softc *ahc,
225                                         struct patch **start_patch,
226                                         u_int start_instr, u_int *skip_addr);
227 static void             ahc_download_instr(struct ahc_softc *ahc,
228                                            u_int instrptr, uint8_t *dconsts);
229 #ifdef AHC_TARGET_MODE
230 static void             ahc_queue_lstate_event(struct ahc_softc *ahc,
231                                                struct ahc_tmode_lstate *lstate,
232                                                u_int initiator_id,
233                                                u_int event_type,
234                                                u_int event_arg);
235 static void             ahc_update_scsiid(struct ahc_softc *ahc,
236                                           u_int targid_mask);
237 static int              ahc_handle_target_cmd(struct ahc_softc *ahc,
238                                               struct target_cmd *cmd);
239 #endif
240 /************************* Sequencer Execution Control ************************/
241 /*
242  * Restart the sequencer program from address zero
243  */
244 void
245 ahc_restart(struct ahc_softc *ahc)
246 {
247
248         ahc_pause(ahc);
249
250         /* No more pending messages. */
251         ahc_clear_msg_state(ahc);
252
253         ahc_outb(ahc, SCSISIGO, 0);             /* De-assert BSY */
254         ahc_outb(ahc, MSG_OUT, MSG_NOOP);       /* No message to send */
255         ahc_outb(ahc, SXFRCTL1, ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET);
256         ahc_outb(ahc, LASTPHASE, P_BUSFREE);
257         ahc_outb(ahc, SAVED_SCSIID, 0xFF);
258         ahc_outb(ahc, SAVED_LUN, 0xFF);
259
260         /*
261          * Ensure that the sequencer's idea of TQINPOS
262          * matches our own.  The sequencer increments TQINPOS
263          * only after it sees a DMA complete and a reset could
264          * occur before the increment leaving the kernel to believe
265          * the command arrived but the sequencer to not.
266          */
267         ahc_outb(ahc, TQINPOS, ahc->tqinfifonext);
268
269         /* Always allow reselection */
270         ahc_outb(ahc, SCSISEQ,
271                  ahc_inb(ahc, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP));
272         if ((ahc->features & AHC_CMD_CHAN) != 0) {
273                 /* Ensure that no DMA operations are in progress */
274                 ahc_outb(ahc, CCSCBCNT, 0);
275                 ahc_outb(ahc, CCSGCTL, 0);
276                 ahc_outb(ahc, CCSCBCTL, 0);
277         }
278         /*
279          * If we were in the process of DMA'ing SCB data into
280          * an SCB, replace that SCB on the free list.  This prevents
281          * an SCB leak.
282          */
283         if ((ahc_inb(ahc, SEQ_FLAGS2) & SCB_DMA) != 0) {
284                 ahc_add_curscb_to_free_list(ahc);
285                 ahc_outb(ahc, SEQ_FLAGS2,
286                          ahc_inb(ahc, SEQ_FLAGS2) & ~SCB_DMA);
287         }
288         ahc_outb(ahc, MWI_RESIDUAL, 0);
289         ahc_outb(ahc, SEQCTL, ahc->seqctl);
290         ahc_outb(ahc, SEQADDR0, 0);
291         ahc_outb(ahc, SEQADDR1, 0);
292         ahc_unpause(ahc);
293 }
294
295 /************************* Input/Output Queues ********************************/
296 void
297 ahc_run_qoutfifo(struct ahc_softc *ahc)
298 {
299         struct scb *scb;
300         u_int  scb_index;
301
302         ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD);
303         while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) {
304
305                 scb_index = ahc->qoutfifo[ahc->qoutfifonext];
306                 if ((ahc->qoutfifonext & 0x03) == 0x03) {
307                         u_int modnext;
308
309                         /*
310                          * Clear 32bits of QOUTFIFO at a time
311                          * so that we don't clobber an incoming
312                          * byte DMA to the array on architectures
313                          * that only support 32bit load and store
314                          * operations.
315                          */
316                         modnext = ahc->qoutfifonext & ~0x3;
317                         *((uint32_t *)(&ahc->qoutfifo[modnext])) = 0xFFFFFFFFUL;
318                         aic_dmamap_sync(ahc, ahc->shared_data_dmat,
319                                         ahc->shared_data_dmamap,
320                                         /*offset*/modnext, /*len*/4,
321                                         BUS_DMASYNC_PREREAD);
322                 }
323                 ahc->qoutfifonext++;
324
325                 scb = ahc_lookup_scb(ahc, scb_index);
326                 if (scb == NULL) {
327                         kprintf("%s: WARNING no command for scb %d "
328                                "(cmdcmplt)\nQOUTPOS = %d\n",
329                                ahc_name(ahc), scb_index,
330                                (ahc->qoutfifonext - 1) & 0xFF);
331                         continue;
332                 }
333
334                 /*
335                  * Save off the residual
336                  * if there is one.
337                  */
338                 ahc_update_residual(ahc, scb);
339                 ahc_done(ahc, scb);
340         }
341 }
342
343 void
344 ahc_run_untagged_queues(struct ahc_softc *ahc)
345 {
346         int i;
347
348         for (i = 0; i < 16; i++)
349                 ahc_run_untagged_queue(ahc, &ahc->untagged_queues[i]);
350 }
351
352 void
353 ahc_run_untagged_queue(struct ahc_softc *ahc, struct scb_tailq *queue)
354 {
355         struct scb *scb;
356
357         if (ahc->untagged_queue_lock != 0)
358                 return;
359
360         if ((scb = TAILQ_FIRST(queue)) != NULL
361          && (scb->flags & SCB_ACTIVE) == 0) {
362                 scb->flags |= SCB_ACTIVE;
363                 ahc_queue_scb(ahc, scb);
364         }
365 }
366
367 /************************* Interrupt Handling *********************************/
368 void
369 ahc_handle_brkadrint(struct ahc_softc *ahc)
370 {
371         /*
372          * We upset the sequencer :-(
373          * Lookup the error message
374          */
375         int i;
376         int error;
377
378         error = ahc_inb(ahc, ERROR);
379         for (i = 0; error != 1 && i < num_errors; i++)
380                 error >>= 1;
381         kprintf("%s: brkadrint, %s at seqaddr = 0x%x\n",
382                ahc_name(ahc), ahc_hard_errors[i].errmesg,
383                ahc_inb(ahc, SEQADDR0) |
384                (ahc_inb(ahc, SEQADDR1) << 8));
385
386         ahc_dump_card_state(ahc);
387
388         /* Tell everyone that this HBA is no longer available */
389         ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, ALL_CHANNELS,
390                        CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN,
391                        CAM_NO_HBA);
392
393         /* Disable all interrupt sources by resetting the controller */
394         ahc_shutdown(ahc);
395 }
396
397 void
398 ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat)
399 {
400         struct scb *scb;
401         struct ahc_devinfo devinfo;
402         
403         ahc_fetch_devinfo(ahc, &devinfo);
404
405         /*
406          * Clear the upper byte that holds SEQINT status
407          * codes and clear the SEQINT bit. We will unpause
408          * the sequencer, if appropriate, after servicing
409          * the request.
410          */
411         ahc_outb(ahc, CLRINT, CLRSEQINT);
412         switch (intstat & SEQINT_MASK) {
413         case BAD_STATUS:
414         {
415                 u_int  scb_index;
416                 struct hardware_scb *hscb;
417
418                 /*
419                  * Set the default return value to 0 (don't
420                  * send sense).  The sense code will change
421                  * this if needed.
422                  */
423                 ahc_outb(ahc, RETURN_1, 0);
424
425                 /*
426                  * The sequencer will notify us when a command
427                  * has an error that would be of interest to
428                  * the kernel.  This allows us to leave the sequencer
429                  * running in the common case of command completes
430                  * without error.  The sequencer will already have
431                  * dma'd the SCB back up to us, so we can reference
432                  * the in kernel copy directly.
433                  */
434                 scb_index = ahc_inb(ahc, SCB_TAG);
435                 scb = ahc_lookup_scb(ahc, scb_index);
436                 if (scb == NULL) {
437                         ahc_print_devinfo(ahc, &devinfo);
438                         kprintf("ahc_intr - referenced scb "
439                                "not valid during seqint 0x%x scb(%d)\n",
440                                intstat, scb_index);
441                         ahc_dump_card_state(ahc);
442                         panic("for safety");
443                         goto unpause;
444                 }
445
446                 hscb = scb->hscb; 
447
448                 /* Don't want to clobber the original sense code */
449                 if ((scb->flags & SCB_SENSE) != 0) {
450                         /*
451                          * Clear the SCB_SENSE Flag and have
452                          * the sequencer do a normal command
453                          * complete.
454                          */
455                         scb->flags &= ~SCB_SENSE;
456                         aic_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
457                         break;
458                 }
459                 aic_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR);
460                 /* Freeze the queue until the client sees the error. */
461                 ahc_freeze_devq(ahc, scb);
462                 aic_freeze_scb(scb);
463                 aic_set_scsi_status(scb, hscb->shared_data.status.scsi_status);
464                 switch (hscb->shared_data.status.scsi_status) {
465                 case SCSI_STATUS_OK:
466                         kprintf("%s: Interrupted for staus of 0???\n",
467                                ahc_name(ahc));
468                         break;
469                 case SCSI_STATUS_CMD_TERMINATED:
470                 case SCSI_STATUS_CHECK_COND:
471                 {
472                         struct ahc_dma_seg *sg;
473                         struct scsi_sense *sc;
474                         struct ahc_initiator_tinfo *targ_info;
475                         struct ahc_tmode_tstate *tstate;
476                         struct ahc_transinfo *tinfo;
477 #ifdef AHC_DEBUG
478                         if (ahc_debug & AHC_SHOW_SENSE) {
479                                 ahc_print_path(ahc, scb);
480                                 kprintf("SCB %d: requests Check Status\n",
481                                        scb->hscb->tag);
482                         }
483 #endif
484
485                         if (aic_perform_autosense(scb) == 0)
486                                 break;
487
488                         targ_info = ahc_fetch_transinfo(ahc,
489                                                         devinfo.channel,
490                                                         devinfo.our_scsiid,
491                                                         devinfo.target,
492                                                         &tstate);
493                         tinfo = &targ_info->curr;
494                         sg = scb->sg_list;
495                         sc = (struct scsi_sense *)(&hscb->shared_data.cdb); 
496                         /*
497                          * Save off the residual if there is one.
498                          */
499                         ahc_update_residual(ahc, scb);
500 #ifdef AHC_DEBUG
501                         if (ahc_debug & AHC_SHOW_SENSE) {
502                                 ahc_print_path(ahc, scb);
503                                 kprintf("Sending Sense\n");
504                         }
505 #endif
506                         sg->addr = ahc_get_sense_bufaddr(ahc, scb);
507                         sg->len = aic_get_sense_bufsize(ahc, scb);
508                         sg->len |= AHC_DMA_LAST_SEG;
509
510                         /* Fixup byte order */
511                         sg->addr = aic_htole32(sg->addr);
512                         sg->len = aic_htole32(sg->len);
513
514                         sc->opcode = REQUEST_SENSE;
515                         sc->byte2 = 0;
516                         if (tinfo->protocol_version <= SCSI_REV_2
517                          && SCB_GET_LUN(scb) < 8)
518                                 sc->byte2 = SCB_GET_LUN(scb) << 5;
519                         sc->unused[0] = 0;
520                         sc->unused[1] = 0;
521                         sc->length = sg->len;
522                         sc->control = 0;
523
524                         /*
525                          * We can't allow the target to disconnect.
526                          * This will be an untagged transaction and
527                          * having the target disconnect will make this
528                          * transaction indestinguishable from outstanding
529                          * tagged transactions.
530                          */
531                         hscb->control = 0;
532
533                         /*
534                          * This request sense could be because the
535                          * the device lost power or in some other
536                          * way has lost our transfer negotiations.
537                          * Renegotiate if appropriate.  Unit attention
538                          * errors will be reported before any data
539                          * phases occur.
540                          */
541                         if (aic_get_residual(scb) 
542                          == aic_get_transfer_length(scb)) {
543                                 ahc_update_neg_request(ahc, &devinfo,
544                                                        tstate, targ_info,
545                                                        AHC_NEG_IF_NON_ASYNC);
546                         }
547                         if (tstate->auto_negotiate & devinfo.target_mask) {
548                                 hscb->control |= MK_MESSAGE;
549                                 scb->flags &= ~SCB_NEGOTIATE;
550                                 scb->flags |= SCB_AUTO_NEGOTIATE;
551                         }
552                         hscb->cdb_len = sizeof(*sc);
553                         hscb->dataptr = sg->addr; 
554                         hscb->datacnt = sg->len;
555                         hscb->sgptr = scb->sg_list_phys | SG_FULL_RESID;
556                         hscb->sgptr = aic_htole32(hscb->sgptr);
557                         scb->sg_count = 1;
558                         scb->flags |= SCB_SENSE;
559                         ahc_qinfifo_requeue_tail(ahc, scb);
560                         ahc_outb(ahc, RETURN_1, SEND_SENSE);
561                         /*
562                          * Ensure we have enough time to actually
563                          * retrieve the sense.
564                          */
565                         aic_scb_timer_reset(scb, 5 * 1000000);
566                         break;
567                 }
568                 default:
569                         break;
570                 }
571                 break;
572         }
573         case NO_MATCH:
574         {
575                 /* Ensure we don't leave the selection hardware on */
576                 ahc_outb(ahc, SCSISEQ,
577                          ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
578
579                 kprintf("%s:%c:%d: no active SCB for reconnecting "
580                        "target - issuing BUS DEVICE RESET\n",
581                        ahc_name(ahc), devinfo.channel, devinfo.target);
582                 kprintf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
583                        "ARG_1 == 0x%x ACCUM = 0x%x\n",
584                        ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN),
585                        ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM));
586                 kprintf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
587                        "SINDEX == 0x%x\n",
588                        ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR),
589                        ahc_index_busy_tcl(ahc,
590                             BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),
591                                       ahc_inb(ahc, SAVED_LUN))),
592                        ahc_inb(ahc, SINDEX));
593                 kprintf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
594                        "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
595                        ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID),
596                        ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG),
597                        ahc_inb(ahc, SCB_CONTROL));
598                 kprintf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
599                        ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI));
600                 kprintf("SXFRCTL0 == 0x%x\n", ahc_inb(ahc, SXFRCTL0));
601                 kprintf("SEQCTL == 0x%x\n", ahc_inb(ahc, SEQCTL));
602                 ahc_dump_card_state(ahc);
603                 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET;
604                 ahc->msgout_len = 1;
605                 ahc->msgout_index = 0;
606                 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
607                 ahc_outb(ahc, MSG_OUT, HOST_MSG);
608                 ahc_assert_atn(ahc);
609                 break;
610         }
611         case SEND_REJECT: 
612         {
613                 u_int rejbyte = ahc_inb(ahc, ACCUM);
614                 kprintf("%s:%c:%d: Warning - unknown message received from "
615                        "target (0x%x).  Rejecting\n", 
616                        ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte);
617                 break; 
618         }
619         case PROTO_VIOLATION:
620         {
621                 ahc_handle_proto_violation(ahc);
622                 break;
623         }
624         case IGN_WIDE_RES:
625                 ahc_handle_ign_wide_residue(ahc, &devinfo);
626                 break;
627         case PDATA_REINIT:
628                 ahc_reinitialize_dataptrs(ahc);
629                 break;
630         case BAD_PHASE:
631         {
632                 u_int lastphase;
633
634                 lastphase = ahc_inb(ahc, LASTPHASE);
635                 kprintf("%s:%c:%d: unknown scsi bus phase %x, "
636                        "lastphase = 0x%x.  Attempting to continue\n",
637                        ahc_name(ahc), devinfo.channel, devinfo.target,
638                        lastphase, ahc_inb(ahc, SCSISIGI));
639                 break;
640         }
641         case MISSED_BUSFREE:
642         {
643                 u_int lastphase;
644
645                 lastphase = ahc_inb(ahc, LASTPHASE);
646                 kprintf("%s:%c:%d: Missed busfree. "
647                        "Lastphase = 0x%x, Curphase = 0x%x\n",
648                        ahc_name(ahc), devinfo.channel, devinfo.target,
649                        lastphase, ahc_inb(ahc, SCSISIGI));
650                 ahc_restart(ahc);
651                 return;
652         }
653         case HOST_MSG_LOOP:
654         {
655                 /*
656                  * The sequencer has encountered a message phase
657                  * that requires host assistance for completion.
658                  * While handling the message phase(s), we will be
659                  * notified by the sequencer after each byte is
660                  * transfered so we can track bus phase changes.
661                  *
662                  * If this is the first time we've seen a HOST_MSG_LOOP
663                  * interrupt, initialize the state of the host message
664                  * loop.
665                  */
666                 if (ahc->msg_type == MSG_TYPE_NONE) {
667                         struct scb *scb;
668                         u_int scb_index;
669                         u_int bus_phase;
670
671                         bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
672                         if (bus_phase != P_MESGIN
673                          && bus_phase != P_MESGOUT) {
674                                 kprintf("ahc_intr: HOST_MSG_LOOP bad "
675                                        "phase 0x%x\n",
676                                       bus_phase);
677                                 /*
678                                  * Probably transitioned to bus free before
679                                  * we got here.  Just punt the message.
680                                  */
681                                 ahc_clear_intstat(ahc);
682                                 ahc_restart(ahc);
683                                 return;
684                         }
685
686                         scb_index = ahc_inb(ahc, SCB_TAG);
687                         scb = ahc_lookup_scb(ahc, scb_index);
688                         if (devinfo.role == ROLE_INITIATOR) {
689                                 if (scb == NULL)
690                                         panic("HOST_MSG_LOOP with "
691                                               "invalid SCB %x\n", scb_index);
692
693                                 if (bus_phase == P_MESGOUT)
694                                         ahc_setup_initiator_msgout(ahc,
695                                                                    &devinfo,
696                                                                    scb);
697                                 else {
698                                         ahc->msg_type =
699                                             MSG_TYPE_INITIATOR_MSGIN;
700                                         ahc->msgin_index = 0;
701                                 }
702                         }
703 #ifdef AHC_TARGET_MODE
704                         else {
705                                 if (bus_phase == P_MESGOUT) {
706                                         ahc->msg_type =
707                                             MSG_TYPE_TARGET_MSGOUT;
708                                         ahc->msgin_index = 0;
709                                 }
710                                 else 
711                                         ahc_setup_target_msgin(ahc,
712                                                                &devinfo,
713                                                                scb);
714                         }
715 #endif
716                 }
717
718                 ahc_handle_message_phase(ahc);
719                 break;
720         }
721         case PERR_DETECTED:
722         {
723                 /*
724                  * If we've cleared the parity error interrupt
725                  * but the sequencer still believes that SCSIPERR
726                  * is true, it must be that the parity error is
727                  * for the currently presented byte on the bus,
728                  * and we are not in a phase (data-in) where we will
729                  * eventually ack this byte.  Ack the byte and
730                  * throw it away in the hope that the target will
731                  * take us to message out to deliver the appropriate
732                  * error message.
733                  */
734                 if ((intstat & SCSIINT) == 0
735                  && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) {
736
737                         if ((ahc->features & AHC_DT) == 0) {
738                                 u_int curphase;
739
740                                 /*
741                                  * The hardware will only let you ack bytes
742                                  * if the expected phase in SCSISIGO matches
743                                  * the current phase.  Make sure this is
744                                  * currently the case.
745                                  */
746                                 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
747                                 ahc_outb(ahc, LASTPHASE, curphase);
748                                 ahc_outb(ahc, SCSISIGO, curphase);
749                         }
750                         if ((ahc_inb(ahc, SCSISIGI) & (CDI|MSGI)) == 0) {
751                                 int wait;
752
753                                 /*
754                                  * In a data phase.  Faster to bitbucket
755                                  * the data than to individually ack each
756                                  * byte.  This is also the only strategy
757                                  * that will work with AUTOACK enabled.
758                                  */
759                                 ahc_outb(ahc, SXFRCTL1,
760                                          ahc_inb(ahc, SXFRCTL1) | BITBUCKET);
761                                 wait = 5000;
762                                 while (--wait != 0) {
763                                         if ((ahc_inb(ahc, SCSISIGI)
764                                           & (CDI|MSGI)) != 0)
765                                                 break;
766                                         aic_delay(100);
767                                 }
768                                 ahc_outb(ahc, SXFRCTL1,
769                                          ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET);
770                                 if (wait == 0) {
771                                         struct  scb *scb;
772                                         u_int   scb_index;
773
774                                         ahc_print_devinfo(ahc, &devinfo);
775                                         kprintf("Unable to clear parity error.  "
776                                                "Resetting bus.\n");
777                                         scb_index = ahc_inb(ahc, SCB_TAG);
778                                         scb = ahc_lookup_scb(ahc, scb_index);
779                                         if (scb != NULL)
780                                                 aic_set_transaction_status(scb,
781                                                     CAM_UNCOR_PARITY);
782                                         ahc_reset_channel(ahc, devinfo.channel, 
783                                                           /*init reset*/TRUE);
784                                 }
785                         } else {
786                                 ahc_inb(ahc, SCSIDATL);
787                         }
788                 }
789                 break;
790         }
791         case DATA_OVERRUN:
792         {
793                 /*
794                  * When the sequencer detects an overrun, it
795                  * places the controller in "BITBUCKET" mode
796                  * and allows the target to complete its transfer.
797                  * Unfortunately, none of the counters get updated
798                  * when the controller is in this mode, so we have
799                  * no way of knowing how large the overrun was.
800                  */
801                 u_int scbindex = ahc_inb(ahc, SCB_TAG);
802                 u_int lastphase = ahc_inb(ahc, LASTPHASE);
803                 u_int i;
804
805                 scb = ahc_lookup_scb(ahc, scbindex);
806                 for (i = 0; i < num_phases; i++) {
807                         if (lastphase == ahc_phase_table[i].phase)
808                                 break;
809                 }
810                 ahc_print_path(ahc, scb);
811                 kprintf("data overrun detected %s."
812                        "  Tag == 0x%x.\n",
813                        ahc_phase_table[i].phasemsg,
814                        scb->hscb->tag);
815                 ahc_print_path(ahc, scb);
816                 kprintf("%s seen Data Phase.  Length = %ld.  NumSGs = %d.\n",
817                        ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't",
818                        aic_get_transfer_length(scb), scb->sg_count);
819                 if (scb->sg_count > 0) {
820                         for (i = 0; i < scb->sg_count; i++) {
821
822                                 kprintf("sg[%d] - Addr 0x%x%x : Length %d\n",
823                                        i,
824                                        (aic_le32toh(scb->sg_list[i].len) >> 24
825                                         & SG_HIGH_ADDR_BITS),
826                                        aic_le32toh(scb->sg_list[i].addr),
827                                        aic_le32toh(scb->sg_list[i].len)
828                                        & AHC_SG_LEN_MASK);
829                         }
830                 }
831                 /*
832                  * Set this and it will take effect when the
833                  * target does a command complete.
834                  */
835                 ahc_freeze_devq(ahc, scb);
836                 if ((scb->flags & SCB_SENSE) == 0) {
837                         aic_set_transaction_status(scb, CAM_DATA_RUN_ERR);
838                 } else {
839                         scb->flags &= ~SCB_SENSE;
840                         aic_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
841                 }
842                 aic_freeze_scb(scb);
843
844                 if ((ahc->features & AHC_ULTRA2) != 0) {
845                         /*
846                          * Clear the channel in case we return
847                          * to data phase later.
848                          */
849                         ahc_outb(ahc, SXFRCTL0,
850                                  ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
851                         ahc_outb(ahc, SXFRCTL0,
852                                  ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
853                 }
854                 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
855                         u_int dscommand1;
856
857                         /* Ensure HHADDR is 0 for future DMA operations. */
858                         dscommand1 = ahc_inb(ahc, DSCOMMAND1);
859                         ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0);
860                         ahc_outb(ahc, HADDR, 0);
861                         ahc_outb(ahc, DSCOMMAND1, dscommand1);
862                 }
863                 break;
864         }
865         case MKMSG_FAILED:
866         {
867                 u_int scbindex;
868
869                 kprintf("%s:%c:%d:%d: Attempt to issue message failed\n",
870                        ahc_name(ahc), devinfo.channel, devinfo.target,
871                        devinfo.lun);
872                 scbindex = ahc_inb(ahc, SCB_TAG);
873                 scb = ahc_lookup_scb(ahc, scbindex);
874                 if (scb != NULL
875                  && (scb->flags & SCB_RECOVERY_SCB) != 0)
876                         /*
877                          * Ensure that we didn't put a second instance of this
878                          * SCB into the QINFIFO.
879                          */
880                         ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb),
881                                            SCB_GET_CHANNEL(ahc, scb),
882                                            SCB_GET_LUN(scb), scb->hscb->tag,
883                                            ROLE_INITIATOR, /*status*/0,
884                                            SEARCH_REMOVE);
885                 break;
886         }
887         case NO_FREE_SCB:
888         {
889                 kprintf("%s: No free or disconnected SCBs\n", ahc_name(ahc));
890                 ahc_dump_card_state(ahc);
891                 panic("for safety");
892                 break;
893         }
894         case SCB_MISMATCH:
895         {
896                 u_int scbptr;
897
898                 scbptr = ahc_inb(ahc, SCBPTR);
899                 kprintf("Bogus TAG after DMA.  SCBPTR %d, tag %d, our tag %d\n",
900                        scbptr, ahc_inb(ahc, ARG_1),
901                        ahc->scb_data->hscbs[scbptr].tag);
902                 ahc_dump_card_state(ahc);
903                 panic("for saftey");
904                 break;
905         }
906         case OUT_OF_RANGE:
907         {
908                 kprintf("%s: BTT calculation out of range\n", ahc_name(ahc));
909                 kprintf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
910                        "ARG_1 == 0x%x ACCUM = 0x%x\n",
911                        ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN),
912                        ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM));
913                 kprintf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
914                        "SINDEX == 0x%x\n, A == 0x%x\n",
915                        ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR),
916                        ahc_index_busy_tcl(ahc,
917                             BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),
918                                       ahc_inb(ahc, SAVED_LUN))),
919                        ahc_inb(ahc, SINDEX),
920                        ahc_inb(ahc, ACCUM));
921                 kprintf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
922                        "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
923                        ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID),
924                        ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG),
925                        ahc_inb(ahc, SCB_CONTROL));
926                 kprintf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
927                        ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI));
928                 ahc_dump_card_state(ahc);
929                 panic("for safety");
930                 break;
931         }
932         default:
933                 kprintf("ahc_intr: seqint, "
934                        "intstat == 0x%x, scsisigi = 0x%x\n",
935                        intstat, ahc_inb(ahc, SCSISIGI));
936                 break;
937         }
938 unpause:
939         /*
940          *  The sequencer is paused immediately on
941          *  a SEQINT, so we should restart it when
942          *  we're done.
943          */
944         ahc_unpause(ahc);
945 }
946
947 void
948 ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat)
949 {
950         u_int   scb_index;
951         u_int   status0;
952         u_int   status;
953         struct  scb *scb;
954         char    cur_channel;
955         char    intr_channel;
956
957         if ((ahc->features & AHC_TWIN) != 0
958          && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0))
959                 cur_channel = 'B';
960         else
961                 cur_channel = 'A';
962         intr_channel = cur_channel;
963
964         if ((ahc->features & AHC_ULTRA2) != 0)
965                 status0 = ahc_inb(ahc, SSTAT0) & IOERR;
966         else
967                 status0 = 0;
968         status = ahc_inb(ahc, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
969         if (status == 0 && status0 == 0) {
970                 if ((ahc->features & AHC_TWIN) != 0) {
971                         /* Try the other channel */
972                         ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
973                         status = ahc_inb(ahc, SSTAT1)
974                                & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
975                         intr_channel = (cur_channel == 'A') ? 'B' : 'A';
976                 }
977                 if (status == 0) {
978                         kprintf("%s: Spurious SCSI interrupt\n", ahc_name(ahc));
979                         ahc_outb(ahc, CLRINT, CLRSCSIINT);
980                         ahc_unpause(ahc);
981                         return;
982                 }
983         }
984
985         /* Make sure the sequencer is in a safe location. */
986         ahc_clear_critical_section(ahc);
987
988         scb_index = ahc_inb(ahc, SCB_TAG);
989         scb = ahc_lookup_scb(ahc, scb_index);
990         if (scb != NULL
991          && (ahc_inb(ahc, SEQ_FLAGS) & NOT_IDENTIFIED) != 0)
992                 scb = NULL;
993
994         if ((ahc->features & AHC_ULTRA2) != 0
995          && (status0 & IOERR) != 0) {
996                 int now_lvd;
997
998                 now_lvd = ahc_inb(ahc, SBLKCTL) & ENAB40;
999                 kprintf("%s: Transceiver State Has Changed to %s mode\n",
1000                        ahc_name(ahc), now_lvd ? "LVD" : "SE");
1001                 ahc_outb(ahc, CLRSINT0, CLRIOERR);
1002                 /*
1003                  * When transitioning to SE mode, the reset line
1004                  * glitches, triggering an arbitration bug in some
1005                  * Ultra2 controllers.  This bug is cleared when we
1006                  * assert the reset line.  Since a reset glitch has
1007                  * already occurred with this transition and a
1008                  * transceiver state change is handled just like
1009                  * a bus reset anyway, asserting the reset line
1010                  * ourselves is safe.
1011                  */
1012                 ahc_reset_channel(ahc, intr_channel,
1013                                  /*Initiate Reset*/now_lvd == 0);
1014         } else if ((status & SCSIRSTI) != 0) {
1015                 kprintf("%s: Someone reset channel %c\n",
1016                         ahc_name(ahc), intr_channel);
1017                 if (intr_channel != cur_channel)
1018                         ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
1019                 ahc_reset_channel(ahc, intr_channel, /*Initiate Reset*/FALSE);
1020         } else if ((status & SCSIPERR) != 0) {
1021                 /*
1022                  * Determine the bus phase and queue an appropriate message.
1023                  * SCSIPERR is latched true as soon as a parity error
1024                  * occurs.  If the sequencer acked the transfer that
1025                  * caused the parity error and the currently presented
1026                  * transfer on the bus has correct parity, SCSIPERR will
1027                  * be cleared by CLRSCSIPERR.  Use this to determine if
1028                  * we should look at the last phase the sequencer recorded,
1029                  * or the current phase presented on the bus.
1030                  */
1031                 struct  ahc_devinfo devinfo;
1032                 u_int   mesg_out;
1033                 u_int   curphase;
1034                 u_int   errorphase;
1035                 u_int   lastphase;
1036                 u_int   scsirate;
1037                 u_int   i;
1038                 u_int   sstat2;
1039                 int     silent;
1040
1041                 lastphase = ahc_inb(ahc, LASTPHASE);
1042                 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
1043                 sstat2 = ahc_inb(ahc, SSTAT2);
1044                 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR);
1045                 /*
1046                  * For all phases save DATA, the sequencer won't
1047                  * automatically ack a byte that has a parity error
1048                  * in it.  So the only way that the current phase
1049                  * could be 'data-in' is if the parity error is for
1050                  * an already acked byte in the data phase.  During
1051                  * synchronous data-in transfers, we may actually
1052                  * ack bytes before latching the current phase in
1053                  * LASTPHASE, leading to the discrepancy between
1054                  * curphase and lastphase.
1055                  */
1056                 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0
1057                  || curphase == P_DATAIN || curphase == P_DATAIN_DT)
1058                         errorphase = curphase;
1059                 else
1060                         errorphase = lastphase;
1061
1062                 for (i = 0; i < num_phases; i++) {
1063                         if (errorphase == ahc_phase_table[i].phase)
1064                                 break;
1065                 }
1066                 mesg_out = ahc_phase_table[i].mesg_out;
1067                 silent = FALSE;
1068                 if (scb != NULL) {
1069                         if (SCB_IS_SILENT(scb))
1070                                 silent = TRUE;
1071                         else
1072                                 ahc_print_path(ahc, scb);
1073                         scb->flags |= SCB_TRANSMISSION_ERROR;
1074                 } else
1075                         kprintf("%s:%c:%d: ", ahc_name(ahc), intr_channel,
1076                                SCSIID_TARGET(ahc, ahc_inb(ahc, SAVED_SCSIID)));
1077                 scsirate = ahc_inb(ahc, SCSIRATE);
1078                 if (silent == FALSE) {
1079                         kprintf("parity error detected %s. "
1080                                "SEQADDR(0x%x) SCSIRATE(0x%x)\n",
1081                                ahc_phase_table[i].phasemsg,
1082                                ahc_inw(ahc, SEQADDR0),
1083                                scsirate);
1084                         if ((ahc->features & AHC_DT) != 0) {
1085                                 if ((sstat2 & CRCVALERR) != 0)
1086                                         kprintf("\tCRC Value Mismatch\n");
1087                                 if ((sstat2 & CRCENDERR) != 0)
1088                                         kprintf("\tNo terminal CRC packet "
1089                                                "received\n");
1090                                 if ((sstat2 & CRCREQERR) != 0)
1091                                         kprintf("\tIllegal CRC packet "
1092                                                "request\n");
1093                                 if ((sstat2 & DUAL_EDGE_ERR) != 0)
1094                                         kprintf("\tUnexpected %sDT Data Phase\n",
1095                                                (scsirate & SINGLE_EDGE)
1096                                              ? "" : "non-");
1097                         }
1098                 }
1099
1100                 if ((ahc->features & AHC_DT) != 0
1101                  && (sstat2 & DUAL_EDGE_ERR) != 0) {
1102                         /*
1103                          * This error applies regardless of
1104                          * data direction, so ignore the value
1105                          * in the phase table.
1106                          */
1107                         mesg_out = MSG_INITIATOR_DET_ERR;
1108                 }
1109
1110                 /*
1111                  * We've set the hardware to assert ATN if we   
1112                  * get a parity error on "in" phases, so all we  
1113                  * need to do is stuff the message buffer with
1114                  * the appropriate message.  "In" phases have set
1115                  * mesg_out to something other than MSG_NOP.
1116                  */
1117                 if (mesg_out != MSG_NOOP) {
1118                         if (ahc->msg_type != MSG_TYPE_NONE)
1119                                 ahc->send_msg_perror = TRUE;
1120                         else
1121                                 ahc_outb(ahc, MSG_OUT, mesg_out);
1122                 }
1123                 /*
1124                  * Force a renegotiation with this target just in
1125                  * case we are out of sync for some external reason
1126                  * unknown (or unreported) by the target.
1127                  */
1128                 ahc_fetch_devinfo(ahc, &devinfo);
1129                 ahc_force_renegotiation(ahc, &devinfo);
1130
1131                 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1132                 ahc_unpause(ahc);
1133         } else if ((status & SELTO) != 0) {
1134                 u_int   scbptr;
1135
1136                 /* Stop the selection */
1137                 ahc_outb(ahc, SCSISEQ, 0);
1138
1139                 /* No more pending messages */
1140                 ahc_clear_msg_state(ahc);
1141
1142                 /* Clear interrupt state */
1143                 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
1144                 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR);
1145
1146                 /*
1147                  * Although the driver does not care about the
1148                  * 'Selection in Progress' status bit, the busy
1149                  * LED does.  SELINGO is only cleared by a successful
1150                  * selection, so we must manually clear it to insure
1151                  * the LED turns off just in case no future successful
1152                  * selections occur (e.g. no devices on the bus).
1153                  */
1154                 ahc_outb(ahc, CLRSINT0, CLRSELINGO);
1155
1156                 scbptr = ahc_inb(ahc, WAITING_SCBH);
1157                 ahc_outb(ahc, SCBPTR, scbptr);
1158                 scb_index = ahc_inb(ahc, SCB_TAG);
1159
1160                 scb = ahc_lookup_scb(ahc, scb_index);
1161                 if (scb == NULL) {
1162                         kprintf("%s: ahc_intr - referenced scb not "
1163                                "valid during SELTO scb(%d, %d)\n",
1164                                ahc_name(ahc), scbptr, scb_index);
1165                         ahc_dump_card_state(ahc);
1166                 } else {
1167                         struct ahc_devinfo devinfo;
1168 #ifdef AHC_DEBUG
1169                         if ((ahc_debug & AHC_SHOW_SELTO) != 0) {
1170                                 ahc_print_path(ahc, scb);
1171                                 kprintf("Saw Selection Timeout for SCB 0x%x\n",
1172                                        scb_index);
1173                         }
1174 #endif
1175                         /*
1176                          * Force a renegotiation with this target just in
1177                          * case the cable was pulled and will later be
1178                          * re-attached.  The target may forget its negotiation
1179                          * settings with us should it attempt to reselect
1180                          * during the interruption.  The target will not issue
1181                          * a unit attention in this case, so we must always
1182                          * renegotiate.
1183                          */
1184                         ahc_scb_devinfo(ahc, &devinfo, scb);
1185                         ahc_force_renegotiation(ahc, &devinfo);
1186                         aic_set_transaction_status(scb, CAM_SEL_TIMEOUT);
1187                         ahc_freeze_devq(ahc, scb);
1188                 }
1189                 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1190                 ahc_restart(ahc);
1191         } else if ((status & BUSFREE) != 0
1192                 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) {
1193                 struct  ahc_devinfo devinfo;
1194                 u_int   lastphase;
1195                 u_int   saved_scsiid;
1196                 u_int   saved_lun;
1197                 u_int   target;
1198                 u_int   initiator_role_id;
1199                 char    channel;
1200                 int     printerror;
1201
1202                 /*
1203                  * Clear our selection hardware as soon as possible.
1204                  * We may have an entry in the waiting Q for this target,
1205                  * that is affected by this busfree and we don't want to
1206                  * go about selecting the target while we handle the event.
1207                  */
1208                 ahc_outb(ahc, SCSISEQ,
1209                          ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
1210
1211                 /*
1212                  * Disable busfree interrupts and clear the busfree
1213                  * interrupt status.  We do this here so that several
1214                  * bus transactions occur prior to clearing the SCSIINT
1215                  * latch.  It can take a bit for the clearing to take effect.
1216                  */
1217                 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
1218                 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR);
1219
1220                 /*
1221                  * Look at what phase we were last in.
1222                  * If its message out, chances are pretty good
1223                  * that the busfree was in response to one of
1224                  * our abort requests.
1225                  */
1226                 lastphase = ahc_inb(ahc, LASTPHASE);
1227                 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID);
1228                 saved_lun = ahc_inb(ahc, SAVED_LUN);
1229                 target = SCSIID_TARGET(ahc, saved_scsiid);
1230                 initiator_role_id = SCSIID_OUR_ID(saved_scsiid);
1231                 channel = SCSIID_CHANNEL(ahc, saved_scsiid);
1232                 ahc_compile_devinfo(&devinfo, initiator_role_id,
1233                                     target, saved_lun, channel, ROLE_INITIATOR);
1234                 printerror = 1;
1235
1236                 if (lastphase == P_MESGOUT) {
1237                         u_int tag;
1238
1239                         tag = SCB_LIST_NULL;
1240                         if (ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT_TAG, TRUE)
1241                          || ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT, TRUE)) {
1242                                 if (ahc->msgout_buf[ahc->msgout_index - 1]
1243                                  == MSG_ABORT_TAG)
1244                                         tag = scb->hscb->tag;
1245                                 ahc_print_path(ahc, scb);
1246                                 kprintf("SCB %d - Abort%s Completed.\n",
1247                                        scb->hscb->tag, tag == SCB_LIST_NULL ?
1248                                        "" : " Tag");
1249                                 ahc_abort_scbs(ahc, target, channel,
1250                                                saved_lun, tag,
1251                                                ROLE_INITIATOR,
1252                                                CAM_REQ_ABORTED);
1253                                 printerror = 0;
1254                         } else if (ahc_sent_msg(ahc, AHCMSG_1B,
1255                                                 MSG_BUS_DEV_RESET, TRUE)) {
1256 #if defined(__DragonFly__) || defined(__FreeBSD__)
1257                                 /*
1258                                  * Don't mark the user's request for this BDR
1259                                  * as completing with CAM_BDR_SENT.  CAM3
1260                                  * specifies CAM_REQ_CMP.
1261                                  */
1262                                 if (scb != NULL
1263                                  && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV
1264                                  && ahc_match_scb(ahc, scb, target, channel,
1265                                                   CAM_LUN_WILDCARD,
1266                                                   SCB_LIST_NULL,
1267                                                   ROLE_INITIATOR)) {
1268                                         aic_set_transaction_status(scb, CAM_REQ_CMP);
1269                                 }
1270 #endif
1271                                 ahc_compile_devinfo(&devinfo,
1272                                                     initiator_role_id,
1273                                                     target,
1274                                                     CAM_LUN_WILDCARD,
1275                                                     channel,
1276                                                     ROLE_INITIATOR);
1277                                 ahc_handle_devreset(ahc, &devinfo,
1278                                                     CAM_BDR_SENT,
1279                                                     "Bus Device Reset",
1280                                                     /*verbose_level*/0);
1281                                 printerror = 0;
1282                         } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1283                                                 MSG_EXT_PPR, FALSE)) {
1284                                 struct ahc_initiator_tinfo *tinfo;
1285                                 struct ahc_tmode_tstate *tstate;
1286
1287                                 /*
1288                                  * PPR Rejected.  Try non-ppr negotiation
1289                                  * and retry command.
1290                                  */
1291                                 tinfo = ahc_fetch_transinfo(ahc,
1292                                                             devinfo.channel,
1293                                                             devinfo.our_scsiid,
1294                                                             devinfo.target,
1295                                                             &tstate);
1296                                 tinfo->curr.transport_version = 2;
1297                                 tinfo->goal.transport_version = 2;
1298                                 tinfo->goal.ppr_options = 0;
1299                                 ahc_qinfifo_requeue_tail(ahc, scb);
1300                                 printerror = 0;
1301                         } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1302                                                 MSG_EXT_WDTR, FALSE)) {
1303                                 /*
1304                                  * Negotiation Rejected.  Go-narrow and
1305                                  * retry command.
1306                                  */
1307                                 ahc_set_width(ahc, &devinfo,
1308                                               MSG_EXT_WDTR_BUS_8_BIT,
1309                                               AHC_TRANS_CUR|AHC_TRANS_GOAL,
1310                                               /*paused*/TRUE);
1311                                 ahc_qinfifo_requeue_tail(ahc, scb);
1312                                 printerror = 0;
1313                         } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1314                                                 MSG_EXT_SDTR, FALSE)) {
1315                                 /*
1316                                  * Negotiation Rejected.  Go-async and
1317                                  * retry command.
1318                                  */
1319                                 ahc_set_syncrate(ahc, &devinfo,
1320                                                 /*syncrate*/NULL,
1321                                                 /*period*/0, /*offset*/0,
1322                                                 /*ppr_options*/0,
1323                                                 AHC_TRANS_CUR|AHC_TRANS_GOAL,
1324                                                 /*paused*/TRUE);
1325                                 ahc_qinfifo_requeue_tail(ahc, scb);
1326                                 printerror = 0;
1327                         }
1328                 }
1329                 if (printerror != 0) {
1330                         u_int i;
1331
1332                         if (scb != NULL) {
1333                                 u_int tag;
1334
1335                                 if ((scb->hscb->control & TAG_ENB) != 0)
1336                                         tag = scb->hscb->tag;
1337                                 else
1338                                         tag = SCB_LIST_NULL;
1339                                 ahc_print_path(ahc, scb);
1340                                 ahc_abort_scbs(ahc, target, channel,
1341                                                SCB_GET_LUN(scb), tag,
1342                                                ROLE_INITIATOR,
1343                                                CAM_UNEXP_BUSFREE);
1344                         } else {
1345                                 /*
1346                                  * We had not fully identified this connection,
1347                                  * so we cannot abort anything.
1348                                  */
1349                                 kprintf("%s: ", ahc_name(ahc));
1350                         }
1351                         for (i = 0; i < num_phases; i++) {
1352                                 if (lastphase == ahc_phase_table[i].phase)
1353                                         break;
1354                         }
1355                         if (lastphase != P_BUSFREE) {
1356                                 /*
1357                                  * Renegotiate with this device at the
1358                                  * next oportunity just in case this busfree
1359                                  * is due to a negotiation mismatch with the
1360                                  * device.
1361                                  */
1362                                 ahc_force_renegotiation(ahc, &devinfo);
1363                         }
1364                         kprintf("Unexpected busfree %s\n"
1365                                "SEQADDR == 0x%x\n",
1366                                ahc_phase_table[i].phasemsg,
1367                                ahc_inb(ahc, SEQADDR0)
1368                                 | (ahc_inb(ahc, SEQADDR1) << 8));
1369                 }
1370                 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1371                 ahc_restart(ahc);
1372         } else {
1373                 kprintf("%s: Missing case in ahc_handle_scsiint. status = %x\n",
1374                        ahc_name(ahc), status);
1375                 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1376         }
1377 }
1378
1379 /*
1380  * Force renegotiation to occur the next time we initiate
1381  * a command to the current device.
1382  */
1383 static void
1384 ahc_force_renegotiation(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
1385 {
1386         struct  ahc_initiator_tinfo *targ_info;
1387         struct  ahc_tmode_tstate *tstate;
1388
1389         targ_info = ahc_fetch_transinfo(ahc,
1390                                         devinfo->channel,
1391                                         devinfo->our_scsiid,
1392                                         devinfo->target,
1393                                         &tstate);
1394         ahc_update_neg_request(ahc, devinfo, tstate,
1395                                targ_info, AHC_NEG_IF_NON_ASYNC);
1396 }
1397
1398 #define AHC_MAX_STEPS 2000
1399 void
1400 ahc_clear_critical_section(struct ahc_softc *ahc)
1401 {
1402         int     stepping;
1403         int     steps;
1404         u_int   simode0;
1405         u_int   simode1;
1406
1407         if (ahc->num_critical_sections == 0)
1408                 return;
1409
1410         stepping = FALSE;
1411         steps = 0;
1412         simode0 = 0;
1413         simode1 = 0;
1414         for (;;) {
1415                 struct  cs *cs;
1416                 u_int   seqaddr;
1417                 u_int   i;
1418
1419                 seqaddr = ahc_inb(ahc, SEQADDR0)
1420                         | (ahc_inb(ahc, SEQADDR1) << 8);
1421
1422                 /*
1423                  * Seqaddr represents the next instruction to execute, 
1424                  * so we are really executing the instruction just
1425                  * before it.
1426                  */
1427                 if (seqaddr != 0)
1428                         seqaddr -= 1;
1429                 cs = ahc->critical_sections;
1430                 for (i = 0; i < ahc->num_critical_sections; i++, cs++) {
1431                         
1432                         if (cs->begin < seqaddr && cs->end >= seqaddr)
1433                                 break;
1434                 }
1435
1436                 if (i == ahc->num_critical_sections)
1437                         break;
1438
1439                 if (steps > AHC_MAX_STEPS) {
1440                         kprintf("%s: Infinite loop in critical section\n",
1441                                ahc_name(ahc));
1442                         ahc_dump_card_state(ahc);
1443                         panic("critical section loop");
1444                 }
1445
1446                 steps++;
1447                 if (stepping == FALSE) {
1448
1449                         /*
1450                          * Disable all interrupt sources so that the
1451                          * sequencer will not be stuck by a pausing
1452                          * interrupt condition while we attempt to
1453                          * leave a critical section.
1454                          */
1455                         simode0 = ahc_inb(ahc, SIMODE0);
1456                         ahc_outb(ahc, SIMODE0, 0);
1457                         simode1 = ahc_inb(ahc, SIMODE1);
1458                         if ((ahc->features & AHC_DT) != 0)
1459                                 /*
1460                                  * On DT class controllers, we
1461                                  * use the enhanced busfree logic.
1462                                  * Unfortunately we cannot re-enable
1463                                  * busfree detection within the
1464                                  * current connection, so we must
1465                                  * leave it on while single stepping.
1466                                  */
1467                                 ahc_outb(ahc, SIMODE1, simode1 & ENBUSFREE);
1468                         else
1469                                 ahc_outb(ahc, SIMODE1, 0);
1470                         ahc_outb(ahc, CLRINT, CLRSCSIINT);
1471                         ahc_outb(ahc, SEQCTL, ahc->seqctl | STEP);
1472                         stepping = TRUE;
1473                 }
1474                 if ((ahc->features & AHC_DT) != 0) {
1475                         ahc_outb(ahc, CLRSINT1, CLRBUSFREE);
1476                         ahc_outb(ahc, CLRINT, CLRSCSIINT);
1477                 }
1478                 ahc_outb(ahc, HCNTRL, ahc->unpause);
1479                 while (!ahc_is_paused(ahc))
1480                         aic_delay(200);
1481         }
1482         if (stepping) {
1483                 ahc_outb(ahc, SIMODE0, simode0);
1484                 ahc_outb(ahc, SIMODE1, simode1);
1485                 ahc_outb(ahc, SEQCTL, ahc->seqctl);
1486         }
1487 }
1488
1489 /*
1490  * Clear any pending interrupt status.
1491  */
1492 void
1493 ahc_clear_intstat(struct ahc_softc *ahc)
1494 {
1495         /* Clear any interrupt conditions this may have caused */
1496         ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI
1497                                 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG|
1498                                 CLRREQINIT);
1499         ahc_flush_device_writes(ahc);
1500         ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO);
1501         ahc_flush_device_writes(ahc);
1502         ahc_outb(ahc, CLRINT, CLRSCSIINT);
1503         ahc_flush_device_writes(ahc);
1504 }
1505
1506 /**************************** Debugging Routines ******************************/
1507 #ifdef AHC_DEBUG
1508 uint32_t ahc_debug = AHC_DEBUG_OPTS;
1509 #endif
1510
1511 void
1512 ahc_print_scb(struct scb *scb)
1513 {
1514         int i;
1515
1516         struct hardware_scb *hscb = scb->hscb;
1517
1518         kprintf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n",
1519                (void *)scb,
1520                hscb->control,
1521                hscb->scsiid,
1522                hscb->lun,
1523                hscb->cdb_len);
1524         kprintf("Shared Data: ");
1525         for (i = 0; i < sizeof(hscb->shared_data.cdb); i++)
1526                 kprintf("%#02x", hscb->shared_data.cdb[i]);
1527         kprintf("        dataptr:%#x datacnt:%#x sgptr:%#x tag:%#x\n",
1528                 aic_le32toh(hscb->dataptr),
1529                 aic_le32toh(hscb->datacnt),
1530                 aic_le32toh(hscb->sgptr),
1531                 hscb->tag);
1532         if (scb->sg_count > 0) {
1533                 for (i = 0; i < scb->sg_count; i++) {
1534                         kprintf("sg[%d] - Addr 0x%x%x : Length %d\n",
1535                                i,
1536                                (aic_le32toh(scb->sg_list[i].len) >> 24
1537                                 & SG_HIGH_ADDR_BITS),
1538                                aic_le32toh(scb->sg_list[i].addr),
1539                                aic_le32toh(scb->sg_list[i].len));
1540                 }
1541         }
1542 }
1543
1544 /************************* Transfer Negotiation *******************************/
1545 /*
1546  * Allocate per target mode instance (ID we respond to as a target)
1547  * transfer negotiation data structures.
1548  */
1549 static struct ahc_tmode_tstate *
1550 ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel)
1551 {
1552         struct ahc_tmode_tstate *master_tstate;
1553         struct ahc_tmode_tstate *tstate;
1554         int i;
1555
1556         master_tstate = ahc->enabled_targets[ahc->our_id];
1557         if (channel == 'B') {
1558                 scsi_id += 8;
1559                 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8];
1560         }
1561         if (ahc->enabled_targets[scsi_id] != NULL
1562          && ahc->enabled_targets[scsi_id] != master_tstate)
1563                 panic("%s: ahc_alloc_tstate - Target already allocated",
1564                       ahc_name(ahc));
1565         tstate = kmalloc(sizeof(*tstate), M_DEVBUF, M_INTWAIT);
1566
1567         /*
1568          * If we have allocated a master tstate, copy user settings from
1569          * the master tstate (taken from SRAM or the EEPROM) for this
1570          * channel, but reset our current and goal settings to async/narrow
1571          * until an initiator talks to us.
1572          */
1573         if (master_tstate != NULL) {
1574                 memcpy(tstate, master_tstate, sizeof(*tstate));
1575                 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns));
1576                 tstate->ultraenb = 0;
1577                 for (i = 0; i < AHC_NUM_TARGETS; i++) {
1578                         memset(&tstate->transinfo[i].curr, 0,
1579                               sizeof(tstate->transinfo[i].curr));
1580                         memset(&tstate->transinfo[i].goal, 0,
1581                               sizeof(tstate->transinfo[i].goal));
1582                 }
1583         } else
1584                 memset(tstate, 0, sizeof(*tstate));
1585         ahc->enabled_targets[scsi_id] = tstate;
1586         return (tstate);
1587 }
1588
1589 #ifdef AHC_TARGET_MODE
1590 /*
1591  * Free per target mode instance (ID we respond to as a target)
1592  * transfer negotiation data structures.
1593  */
1594 static void
1595 ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force)
1596 {
1597         struct ahc_tmode_tstate *tstate;
1598
1599         /*
1600          * Don't clean up our "master" tstate.
1601          * It has our default user settings.
1602          */
1603         if (((channel == 'B' && scsi_id == ahc->our_id_b)
1604           || (channel == 'A' && scsi_id == ahc->our_id))
1605          && force == FALSE)
1606                 return;
1607
1608         if (channel == 'B')
1609                 scsi_id += 8;
1610         tstate = ahc->enabled_targets[scsi_id];
1611         if (tstate != NULL)
1612                 kfree(tstate, M_DEVBUF);
1613         ahc->enabled_targets[scsi_id] = NULL;
1614 }
1615 #endif
1616
1617 /*
1618  * Called when we have an active connection to a target on the bus,
1619  * this function finds the nearest syncrate to the input period limited
1620  * by the capabilities of the bus connectivity of and sync settings for
1621  * the target.
1622  */
1623 struct ahc_syncrate *
1624 ahc_devlimited_syncrate(struct ahc_softc *ahc,
1625                         struct ahc_initiator_tinfo *tinfo,
1626                         u_int *period, u_int *ppr_options, role_t role)
1627 {
1628         struct  ahc_transinfo *transinfo;
1629         u_int   maxsync;
1630
1631         if ((ahc->features & AHC_ULTRA2) != 0) {
1632                 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0
1633                  && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) {
1634                         maxsync = AHC_SYNCRATE_DT;
1635                 } else {
1636                         maxsync = AHC_SYNCRATE_ULTRA;
1637                         /* Can't do DT on an SE bus */
1638                         *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1639                 }
1640         } else if ((ahc->features & AHC_ULTRA) != 0) {
1641                 maxsync = AHC_SYNCRATE_ULTRA;
1642         } else {
1643                 maxsync = AHC_SYNCRATE_FAST;
1644         }
1645         /*
1646          * Never allow a value higher than our current goal
1647          * period otherwise we may allow a target initiated
1648          * negotiation to go above the limit as set by the
1649          * user.  In the case of an initiator initiated
1650          * sync negotiation, we limit based on the user
1651          * setting.  This allows the system to still accept
1652          * incoming negotiations even if target initiated
1653          * negotiation is not performed.
1654          */
1655         if (role == ROLE_TARGET)
1656                 transinfo = &tinfo->user;
1657         else 
1658                 transinfo = &tinfo->goal;
1659         *ppr_options &= transinfo->ppr_options;
1660         if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) {
1661                 maxsync = MAX(maxsync, AHC_SYNCRATE_ULTRA2);
1662                 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1663         }
1664         if (transinfo->period == 0) {
1665                 *period = 0;
1666                 *ppr_options = 0;
1667                 return (NULL);
1668         }
1669         *period = MAX(*period, transinfo->period);
1670         return (ahc_find_syncrate(ahc, period, ppr_options, maxsync));
1671 }
1672
1673 /*
1674  * Look up the valid period to SCSIRATE conversion in our table.
1675  * Return the period and offset that should be sent to the target
1676  * if this was the beginning of an SDTR.
1677  */
1678 struct ahc_syncrate *
1679 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period,
1680                   u_int *ppr_options, u_int maxsync)
1681 {
1682         struct ahc_syncrate *syncrate;
1683
1684         if ((ahc->features & AHC_DT) == 0)
1685                 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1686
1687         /* Skip all DT only entries if DT is not available */
1688         if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0
1689          && maxsync < AHC_SYNCRATE_ULTRA2)
1690                 maxsync = AHC_SYNCRATE_ULTRA2;
1691         
1692         for (syncrate = &ahc_syncrates[maxsync];
1693              syncrate->rate != NULL;
1694              syncrate++) {
1695
1696                 /*
1697                  * The Ultra2 table doesn't go as low
1698                  * as for the Fast/Ultra cards.
1699                  */
1700                 if ((ahc->features & AHC_ULTRA2) != 0
1701                  && (syncrate->sxfr_u2 == 0))
1702                         break;
1703
1704                 if (*period <= syncrate->period) {
1705                         /*
1706                          * When responding to a target that requests
1707                          * sync, the requested rate may fall between
1708                          * two rates that we can output, but still be
1709                          * a rate that we can receive.  Because of this,
1710                          * we want to respond to the target with
1711                          * the same rate that it sent to us even
1712                          * if the period we use to send data to it
1713                          * is lower.  Only lower the response period
1714                          * if we must.
1715                          */
1716                         if (syncrate == &ahc_syncrates[maxsync])
1717                                 *period = syncrate->period;
1718
1719                         /*
1720                          * At some speeds, we only support
1721                          * ST transfers.
1722                          */
1723                         if ((syncrate->sxfr_u2 & ST_SXFR) != 0)
1724                                 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1725                         break;
1726                 }
1727         }
1728
1729         if ((*period == 0)
1730          || (syncrate->rate == NULL)
1731          || ((ahc->features & AHC_ULTRA2) != 0
1732           && (syncrate->sxfr_u2 == 0))) {
1733                 /* Use asynchronous transfers. */
1734                 *period = 0;
1735                 syncrate = NULL;
1736                 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1737         }
1738         return (syncrate);
1739 }
1740
1741 /*
1742  * Convert from an entry in our syncrate table to the SCSI equivalent
1743  * sync "period" factor.
1744  */
1745 u_int
1746 ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync)
1747 {
1748         struct ahc_syncrate *syncrate;
1749
1750         if ((ahc->features & AHC_ULTRA2) != 0)
1751                 scsirate &= SXFR_ULTRA2;
1752         else
1753                 scsirate &= SXFR;
1754
1755         syncrate = &ahc_syncrates[maxsync];
1756         while (syncrate->rate != NULL) {
1757
1758                 if ((ahc->features & AHC_ULTRA2) != 0) {
1759                         if (syncrate->sxfr_u2 == 0)
1760                                 break;
1761                         else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2))
1762                                 return (syncrate->period);
1763                 } else if (scsirate == (syncrate->sxfr & SXFR)) {
1764                                 return (syncrate->period);
1765                 }
1766                 syncrate++;
1767         }
1768         return (0); /* async */
1769 }
1770
1771 /*
1772  * Truncate the given synchronous offset to a value the
1773  * current adapter type and syncrate are capable of.
1774  */
1775 void
1776 ahc_validate_offset(struct ahc_softc *ahc,
1777                     struct ahc_initiator_tinfo *tinfo,
1778                     struct ahc_syncrate *syncrate,
1779                     u_int *offset, int wide, role_t role)
1780 {
1781         u_int maxoffset;
1782
1783         /* Limit offset to what we can do */
1784         if (syncrate == NULL) {
1785                 maxoffset = 0;
1786         } else if ((ahc->features & AHC_ULTRA2) != 0) {
1787                 maxoffset = MAX_OFFSET_ULTRA2;
1788         } else {
1789                 if (wide)
1790                         maxoffset = MAX_OFFSET_16BIT;
1791                 else
1792                         maxoffset = MAX_OFFSET_8BIT;
1793         }
1794         *offset = MIN(*offset, maxoffset);
1795         if (tinfo != NULL) {
1796                 if (role == ROLE_TARGET)
1797                         *offset = MIN(*offset, tinfo->user.offset);
1798                 else
1799                         *offset = MIN(*offset, tinfo->goal.offset);
1800         }
1801 }
1802
1803 /*
1804  * Truncate the given transfer width parameter to a value the
1805  * current adapter type is capable of.
1806  */
1807 void
1808 ahc_validate_width(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo,
1809                    u_int *bus_width, role_t role)
1810 {
1811         switch (*bus_width) {
1812         default:
1813                 if (ahc->features & AHC_WIDE) {
1814                         /* Respond Wide */
1815                         *bus_width = MSG_EXT_WDTR_BUS_16_BIT;
1816                         break;
1817                 }
1818                 /* FALLTHROUGH */
1819         case MSG_EXT_WDTR_BUS_8_BIT:
1820                 *bus_width = MSG_EXT_WDTR_BUS_8_BIT;
1821                 break;
1822         }
1823         if (tinfo != NULL) {
1824                 if (role == ROLE_TARGET)
1825                         *bus_width = MIN(tinfo->user.width, *bus_width);
1826                 else
1827                         *bus_width = MIN(tinfo->goal.width, *bus_width);
1828         }
1829 }
1830
1831 /*
1832  * Update the bitmask of targets for which the controller should
1833  * negotiate with at the next convenient oportunity.  This currently
1834  * means the next time we send the initial identify messages for
1835  * a new transaction.
1836  */
1837 int
1838 ahc_update_neg_request(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
1839                        struct ahc_tmode_tstate *tstate,
1840                        struct ahc_initiator_tinfo *tinfo, ahc_neg_type neg_type)
1841 {
1842         u_int auto_negotiate_orig;
1843
1844         auto_negotiate_orig = tstate->auto_negotiate;
1845         if (neg_type == AHC_NEG_ALWAYS) {
1846                 /*
1847                  * Force our "current" settings to be
1848                  * unknown so that unless a bus reset
1849                  * occurs the need to renegotiate is
1850                  * recorded persistently.
1851                  */
1852                 if ((ahc->features & AHC_WIDE) != 0)
1853                         tinfo->curr.width = AHC_WIDTH_UNKNOWN;
1854                 tinfo->curr.period = AHC_PERIOD_UNKNOWN;
1855                 tinfo->curr.offset = AHC_OFFSET_UNKNOWN;
1856         }
1857         if (tinfo->curr.period != tinfo->goal.period
1858          || tinfo->curr.width != tinfo->goal.width
1859          || tinfo->curr.offset != tinfo->goal.offset
1860          || tinfo->curr.ppr_options != tinfo->goal.ppr_options
1861          || (neg_type == AHC_NEG_IF_NON_ASYNC
1862           && (tinfo->goal.offset != 0
1863            || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT
1864            || tinfo->goal.ppr_options != 0)))
1865                 tstate->auto_negotiate |= devinfo->target_mask;
1866         else
1867                 tstate->auto_negotiate &= ~devinfo->target_mask;
1868
1869         return (auto_negotiate_orig != tstate->auto_negotiate);
1870 }
1871
1872 /*
1873  * Update the user/goal/curr tables of synchronous negotiation
1874  * parameters as well as, in the case of a current or active update,
1875  * any data structures on the host controller.  In the case of an
1876  * active update, the specified target is currently talking to us on
1877  * the bus, so the transfer parameter update must take effect
1878  * immediately.
1879  */
1880 void
1881 ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
1882                  struct ahc_syncrate *syncrate, u_int period,
1883                  u_int offset, u_int ppr_options, u_int type, int paused)
1884 {
1885         struct  ahc_initiator_tinfo *tinfo;
1886         struct  ahc_tmode_tstate *tstate;
1887         u_int   old_period;
1888         u_int   old_offset;
1889         u_int   old_ppr;
1890         int     active;
1891         int     update_needed;
1892
1893         active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
1894         update_needed = 0;
1895
1896         if (syncrate == NULL) {
1897                 period = 0;
1898                 offset = 0;
1899         }
1900
1901         tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
1902                                     devinfo->target, &tstate);
1903
1904         if ((type & AHC_TRANS_USER) != 0) {
1905                 tinfo->user.period = period;
1906                 tinfo->user.offset = offset;
1907                 tinfo->user.ppr_options = ppr_options;
1908         }
1909
1910         if ((type & AHC_TRANS_GOAL) != 0) {
1911                 tinfo->goal.period = period;
1912                 tinfo->goal.offset = offset;
1913                 tinfo->goal.ppr_options = ppr_options;
1914         }
1915
1916         old_period = tinfo->curr.period;
1917         old_offset = tinfo->curr.offset;
1918         old_ppr    = tinfo->curr.ppr_options;
1919
1920         if ((type & AHC_TRANS_CUR) != 0
1921          && (old_period != period
1922           || old_offset != offset
1923           || old_ppr != ppr_options)) {
1924                 u_int   scsirate;
1925
1926                 update_needed++;
1927                 scsirate = tinfo->scsirate;
1928                 if ((ahc->features & AHC_ULTRA2) != 0) {
1929
1930                         scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC);
1931                         if (syncrate != NULL) {
1932                                 scsirate |= syncrate->sxfr_u2;
1933                                 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0)
1934                                         scsirate |= ENABLE_CRC;
1935                                 else
1936                                         scsirate |= SINGLE_EDGE;
1937                         }
1938                 } else {
1939
1940                         scsirate &= ~(SXFR|SOFS);
1941                         /*
1942                          * Ensure Ultra mode is set properly for
1943                          * this target.
1944                          */
1945                         tstate->ultraenb &= ~devinfo->target_mask;
1946                         if (syncrate != NULL) {
1947                                 if (syncrate->sxfr & ULTRA_SXFR) {
1948                                         tstate->ultraenb |=
1949                                                 devinfo->target_mask;
1950                                 }
1951                                 scsirate |= syncrate->sxfr & SXFR;
1952                                 scsirate |= offset & SOFS;
1953                         }
1954                         if (active) {
1955                                 u_int sxfrctl0;
1956
1957                                 sxfrctl0 = ahc_inb(ahc, SXFRCTL0);
1958                                 sxfrctl0 &= ~FAST20;
1959                                 if (tstate->ultraenb & devinfo->target_mask)
1960                                         sxfrctl0 |= FAST20;
1961                                 ahc_outb(ahc, SXFRCTL0, sxfrctl0);
1962                         }
1963                 }
1964                 if (active) {
1965                         ahc_outb(ahc, SCSIRATE, scsirate);
1966                         if ((ahc->features & AHC_ULTRA2) != 0)
1967                                 ahc_outb(ahc, SCSIOFFSET, offset);
1968                 }
1969
1970                 tinfo->scsirate = scsirate;
1971                 tinfo->curr.period = period;
1972                 tinfo->curr.offset = offset;
1973                 tinfo->curr.ppr_options = ppr_options;
1974
1975                 ahc_send_async(ahc, devinfo->channel, devinfo->target,
1976                                CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
1977                 if (bootverbose) {
1978                         if (offset != 0) {
1979                                 kprintf("%s: target %d synchronous at %sMHz%s, "
1980                                        "offset = 0x%x\n", ahc_name(ahc),
1981                                        devinfo->target, syncrate->rate,
1982                                        (ppr_options & MSG_EXT_PPR_DT_REQ)
1983                                        ? " DT" : "", offset);
1984                         } else {
1985                                 kprintf("%s: target %d using "
1986                                        "asynchronous transfers\n",
1987                                        ahc_name(ahc), devinfo->target);
1988                         }
1989                 }
1990         }
1991
1992         update_needed += ahc_update_neg_request(ahc, devinfo, tstate,
1993                                                 tinfo, AHC_NEG_TO_GOAL);
1994
1995         if (update_needed)
1996                 ahc_update_pending_scbs(ahc);
1997 }
1998
1999 /*
2000  * Update the user/goal/curr tables of wide negotiation
2001  * parameters as well as, in the case of a current or active update,
2002  * any data structures on the host controller.  In the case of an
2003  * active update, the specified target is currently talking to us on
2004  * the bus, so the transfer parameter update must take effect
2005  * immediately.
2006  */
2007 void
2008 ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2009               u_int width, u_int type, int paused)
2010 {
2011         struct  ahc_initiator_tinfo *tinfo;
2012         struct  ahc_tmode_tstate *tstate;
2013         u_int   oldwidth;
2014         int     active;
2015         int     update_needed;
2016
2017         active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
2018         update_needed = 0;
2019         tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
2020                                     devinfo->target, &tstate);
2021
2022         if ((type & AHC_TRANS_USER) != 0)
2023                 tinfo->user.width = width;
2024
2025         if ((type & AHC_TRANS_GOAL) != 0)
2026                 tinfo->goal.width = width;
2027
2028         oldwidth = tinfo->curr.width;
2029         if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) {
2030                 u_int   scsirate;
2031
2032                 update_needed++;
2033                 scsirate =  tinfo->scsirate;
2034                 scsirate &= ~WIDEXFER;
2035                 if (width == MSG_EXT_WDTR_BUS_16_BIT)
2036                         scsirate |= WIDEXFER;
2037
2038                 tinfo->scsirate = scsirate;
2039
2040                 if (active)
2041                         ahc_outb(ahc, SCSIRATE, scsirate);
2042
2043                 tinfo->curr.width = width;
2044
2045                 ahc_send_async(ahc, devinfo->channel, devinfo->target,
2046                                CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
2047                 if (bootverbose) {
2048                         kprintf("%s: target %d using %dbit transfers\n",
2049                                ahc_name(ahc), devinfo->target,
2050                                8 * (0x01 << width));
2051                 }
2052         }
2053
2054         update_needed += ahc_update_neg_request(ahc, devinfo, tstate,
2055                                                 tinfo, AHC_NEG_TO_GOAL);
2056         if (update_needed)
2057                 ahc_update_pending_scbs(ahc);
2058 }
2059
2060 /*
2061  * Update the current state of tagged queuing for a given target.
2062  */
2063 void
2064 ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2065              ahc_queue_alg alg)
2066 {
2067         ahc_platform_set_tags(ahc, devinfo, alg);
2068         ahc_send_async(ahc, devinfo->channel, devinfo->target,
2069                        devinfo->lun, AC_TRANSFER_NEG, &alg);
2070 }
2071
2072 /*
2073  * When the transfer settings for a connection change, update any
2074  * in-transit SCBs to contain the new data so the hardware will
2075  * be set correctly during future (re)selections.
2076  */
2077 static void
2078 ahc_update_pending_scbs(struct ahc_softc *ahc)
2079 {
2080         struct  scb *pending_scb;
2081         int     pending_scb_count;
2082         int     i;
2083         int     paused;
2084         u_int   saved_scbptr;
2085
2086         /*
2087          * Traverse the pending SCB list and ensure that all of the
2088          * SCBs there have the proper settings.
2089          */
2090         pending_scb_count = 0;
2091         LIST_FOREACH(pending_scb, &ahc->pending_scbs, pending_links) {
2092                 struct ahc_devinfo devinfo;
2093                 struct hardware_scb *pending_hscb;
2094                 struct ahc_initiator_tinfo *tinfo;
2095                 struct ahc_tmode_tstate *tstate;
2096
2097                 ahc_scb_devinfo(ahc, &devinfo, pending_scb);
2098                 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel,
2099                                             devinfo.our_scsiid,
2100                                             devinfo.target, &tstate);
2101                 pending_hscb = pending_scb->hscb;
2102                 pending_hscb->control &= ~ULTRAENB;
2103                 if ((tstate->ultraenb & devinfo.target_mask) != 0)
2104                         pending_hscb->control |= ULTRAENB;
2105                 pending_hscb->scsirate = tinfo->scsirate;
2106                 pending_hscb->scsioffset = tinfo->curr.offset;
2107                 if ((tstate->auto_negotiate & devinfo.target_mask) == 0
2108                  && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) {
2109                         pending_scb->flags &= ~SCB_AUTO_NEGOTIATE;
2110                         pending_hscb->control &= ~MK_MESSAGE;
2111                 }
2112                 ahc_sync_scb(ahc, pending_scb,
2113                              BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
2114                 pending_scb_count++;
2115         }
2116
2117         if (pending_scb_count == 0)
2118                 return;
2119
2120         if (ahc_is_paused(ahc)) {
2121                 paused = 1;
2122         } else {
2123                 paused = 0;
2124                 ahc_pause(ahc);
2125         }
2126
2127         saved_scbptr = ahc_inb(ahc, SCBPTR);
2128         /* Ensure that the hscbs down on the card match the new information */
2129         for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
2130                 struct  hardware_scb *pending_hscb;
2131                 u_int   control;
2132                 u_int   scb_tag;
2133
2134                 ahc_outb(ahc, SCBPTR, i);
2135                 scb_tag = ahc_inb(ahc, SCB_TAG);
2136                 pending_scb = ahc_lookup_scb(ahc, scb_tag);
2137                 if (pending_scb == NULL)
2138                         continue;
2139
2140                 pending_hscb = pending_scb->hscb;
2141                 control = ahc_inb(ahc, SCB_CONTROL);
2142                 control &= ~(ULTRAENB|MK_MESSAGE);
2143                 control |= pending_hscb->control & (ULTRAENB|MK_MESSAGE);
2144                 ahc_outb(ahc, SCB_CONTROL, control);
2145                 ahc_outb(ahc, SCB_SCSIRATE, pending_hscb->scsirate);
2146                 ahc_outb(ahc, SCB_SCSIOFFSET, pending_hscb->scsioffset);
2147         }
2148         ahc_outb(ahc, SCBPTR, saved_scbptr);
2149
2150         if (paused == 0)
2151                 ahc_unpause(ahc);
2152 }
2153
2154 /**************************** Pathing Information *****************************/
2155 static void
2156 ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2157 {
2158         u_int   saved_scsiid;
2159         role_t  role;
2160         int     our_id;
2161
2162         if (ahc_inb(ahc, SSTAT0) & TARGET)
2163                 role = ROLE_TARGET;
2164         else
2165                 role = ROLE_INITIATOR;
2166
2167         if (role == ROLE_TARGET
2168          && (ahc->features & AHC_MULTI_TID) != 0
2169          && (ahc_inb(ahc, SEQ_FLAGS)
2170            & (CMDPHASE_PENDING|TARG_CMD_PENDING|NO_DISCONNECT)) != 0) {
2171                 /* We were selected, so pull our id from TARGIDIN */
2172                 our_id = ahc_inb(ahc, TARGIDIN) & OID;
2173         } else if ((ahc->features & AHC_ULTRA2) != 0)
2174                 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID;
2175         else
2176                 our_id = ahc_inb(ahc, SCSIID) & OID;
2177
2178         saved_scsiid = ahc_inb(ahc, SAVED_SCSIID);
2179         ahc_compile_devinfo(devinfo,
2180                             our_id,
2181                             SCSIID_TARGET(ahc, saved_scsiid),
2182                             ahc_inb(ahc, SAVED_LUN),
2183                             SCSIID_CHANNEL(ahc, saved_scsiid),
2184                             role);
2185 }
2186
2187 struct ahc_phase_table_entry*
2188 ahc_lookup_phase_entry(int phase)
2189 {
2190         struct ahc_phase_table_entry *entry;
2191         struct ahc_phase_table_entry *last_entry;
2192
2193         /*
2194          * num_phases doesn't include the default entry which
2195          * will be returned if the phase doesn't match.
2196          */
2197         last_entry = &ahc_phase_table[num_phases];
2198         for (entry = ahc_phase_table; entry < last_entry; entry++) {
2199                 if (phase == entry->phase)
2200                         break;
2201         }
2202         return (entry);
2203 }
2204
2205 void
2206 ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target,
2207                     u_int lun, char channel, role_t role)
2208 {
2209         devinfo->our_scsiid = our_id;
2210         devinfo->target = target;
2211         devinfo->lun = lun;
2212         devinfo->target_offset = target;
2213         devinfo->channel = channel;
2214         devinfo->role = role;
2215         if (channel == 'B')
2216                 devinfo->target_offset += 8;
2217         devinfo->target_mask = (0x01 << devinfo->target_offset);
2218 }
2219
2220 void
2221 ahc_print_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2222 {
2223         kprintf("%s:%c:%d:%d: ", ahc_name(ahc), devinfo->channel,
2224                devinfo->target, devinfo->lun);
2225 }
2226
2227 static void
2228 ahc_scb_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2229                 struct scb *scb)
2230 {
2231         role_t  role;
2232         int     our_id;
2233
2234         our_id = SCSIID_OUR_ID(scb->hscb->scsiid);
2235         role = ROLE_INITIATOR;
2236         if ((scb->flags & SCB_TARGET_SCB) != 0)
2237                 role = ROLE_TARGET;
2238         ahc_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahc, scb),
2239                             SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahc, scb), role);
2240 }
2241
2242
2243 /************************ Message Phase Processing ****************************/
2244 static void
2245 ahc_assert_atn(struct ahc_softc *ahc)
2246 {
2247         u_int scsisigo;
2248
2249         scsisigo = ATNO;
2250         if ((ahc->features & AHC_DT) == 0)
2251                 scsisigo |= ahc_inb(ahc, SCSISIGI);
2252         ahc_outb(ahc, SCSISIGO, scsisigo);
2253 }
2254
2255 /*
2256  * When an initiator transaction with the MK_MESSAGE flag either reconnects
2257  * or enters the initial message out phase, we are interrupted.  Fill our
2258  * outgoing message buffer with the appropriate message and beging handing
2259  * the message phase(s) manually.
2260  */
2261 static void
2262 ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2263                            struct scb *scb)
2264 {
2265         /*
2266          * To facilitate adding multiple messages together,
2267          * each routine should increment the index and len
2268          * variables instead of setting them explicitly.
2269          */
2270         ahc->msgout_index = 0;
2271         ahc->msgout_len = 0;
2272
2273         if ((scb->flags & SCB_DEVICE_RESET) == 0
2274          && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) {
2275                 u_int identify_msg;
2276
2277                 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb);
2278                 if ((scb->hscb->control & DISCENB) != 0)
2279                         identify_msg |= MSG_IDENTIFY_DISCFLAG;
2280                 ahc->msgout_buf[ahc->msgout_index++] = identify_msg;
2281                 ahc->msgout_len++;
2282
2283                 if ((scb->hscb->control & TAG_ENB) != 0) {
2284                         ahc->msgout_buf[ahc->msgout_index++] =
2285                             scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE);
2286                         ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag;
2287                         ahc->msgout_len += 2;
2288                 }
2289         }
2290
2291         if (scb->flags & SCB_DEVICE_RESET) {
2292                 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET;
2293                 ahc->msgout_len++;
2294                 ahc_print_path(ahc, scb);
2295                 kprintf("Bus Device Reset Message Sent\n");
2296                 /*
2297                  * Clear our selection hardware in advance of
2298                  * the busfree.  We may have an entry in the waiting
2299                  * Q for this target, and we don't want to go about
2300                  * selecting while we handle the busfree and blow it
2301                  * away.
2302                  */
2303                 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
2304         } else if ((scb->flags & SCB_ABORT) != 0) {
2305                 if ((scb->hscb->control & TAG_ENB) != 0)
2306                         ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG;
2307                 else
2308                         ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT;
2309                 ahc->msgout_len++;
2310                 ahc_print_path(ahc, scb);
2311                 kprintf("Abort%s Message Sent\n",
2312                        (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : "");
2313                 /*
2314                  * Clear our selection hardware in advance of
2315                  * the busfree.  We may have an entry in the waiting
2316                  * Q for this target, and we don't want to go about
2317                  * selecting while we handle the busfree and blow it
2318                  * away.
2319                  */
2320                 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
2321         } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) {
2322                 ahc_build_transfer_msg(ahc, devinfo);
2323         } else {
2324                 kprintf("ahc_intr: AWAITING_MSG for an SCB that "
2325                        "does not have a waiting message\n");
2326                 kprintf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid,
2327                        devinfo->target_mask);
2328                 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x "
2329                       "SCB flags = %x", scb->hscb->tag, scb->hscb->control,
2330                       ahc_inb(ahc, MSG_OUT), scb->flags);
2331         }
2332
2333         /*
2334          * Clear the MK_MESSAGE flag from the SCB so we aren't
2335          * asked to send this message again.
2336          */
2337         ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE);
2338         scb->hscb->control &= ~MK_MESSAGE;
2339         ahc->msgout_index = 0;
2340         ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2341 }
2342
2343 /*
2344  * Build an appropriate transfer negotiation message for the
2345  * currently active target.
2346  */
2347 static void
2348 ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2349 {
2350         /*
2351          * We need to initiate transfer negotiations.
2352          * If our current and goal settings are identical,
2353          * we want to renegotiate due to a check condition.
2354          */
2355         struct  ahc_initiator_tinfo *tinfo;
2356         struct  ahc_tmode_tstate *tstate;
2357         struct  ahc_syncrate *rate;
2358         int     dowide;
2359         int     dosync;
2360         int     doppr;
2361         u_int   period;
2362         u_int   ppr_options;
2363         u_int   offset;
2364
2365         tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
2366                                     devinfo->target, &tstate);
2367         /*
2368          * Filter our period based on the current connection.
2369          * If we can't perform DT transfers on this segment (not in LVD
2370          * mode for instance), then our decision to issue a PPR message
2371          * may change.
2372          */
2373         period = tinfo->goal.period;
2374         offset = tinfo->goal.offset;
2375         ppr_options = tinfo->goal.ppr_options;
2376         /* Target initiated PPR is not allowed in the SCSI spec */
2377         if (devinfo->role == ROLE_TARGET)
2378                 ppr_options = 0;
2379         rate = ahc_devlimited_syncrate(ahc, tinfo, &period,
2380                                        &ppr_options, devinfo->role);
2381         dowide = tinfo->curr.width != tinfo->goal.width;
2382         dosync = tinfo->curr.offset != offset || tinfo->curr.period != period;
2383         /*
2384          * Only use PPR if we have options that need it, even if the device
2385          * claims to support it.  There might be an expander in the way
2386          * that doesn't.
2387          */
2388         doppr = ppr_options != 0;
2389
2390         if (!dowide && !dosync && !doppr) {
2391                 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT;
2392                 dosync = tinfo->goal.offset != 0;
2393         }
2394
2395         if (!dowide && !dosync && !doppr) {
2396                 /*
2397                  * Force async with a WDTR message if we have a wide bus,
2398                  * or just issue an SDTR with a 0 offset.
2399                  */
2400                 if ((ahc->features & AHC_WIDE) != 0)
2401                         dowide = 1;
2402                 else
2403                         dosync = 1;
2404
2405                 if (bootverbose) {
2406                         ahc_print_devinfo(ahc, devinfo);
2407                         kprintf("Ensuring async\n");
2408                 }
2409         }
2410
2411         /* Target initiated PPR is not allowed in the SCSI spec */
2412         if (devinfo->role == ROLE_TARGET)
2413                 doppr = 0;
2414
2415         /*
2416          * Both the PPR message and SDTR message require the
2417          * goal syncrate to be limited to what the target device
2418          * is capable of handling (based on whether an LVD->SE
2419          * expander is on the bus), so combine these two cases.
2420          * Regardless, guarantee that if we are using WDTR and SDTR
2421          * messages that WDTR comes first.
2422          */
2423         if (doppr || (dosync && !dowide)) {
2424
2425                 offset = tinfo->goal.offset;
2426                 ahc_validate_offset(ahc, tinfo, rate, &offset,
2427                                     doppr ? tinfo->goal.width
2428                                           : tinfo->curr.width,
2429                                     devinfo->role);
2430                 if (doppr) {
2431                         ahc_construct_ppr(ahc, devinfo, period, offset,
2432                                           tinfo->goal.width, ppr_options);
2433                 } else {
2434                         ahc_construct_sdtr(ahc, devinfo, period, offset);
2435                 }
2436         } else {
2437                 ahc_construct_wdtr(ahc, devinfo, tinfo->goal.width);
2438         }
2439 }
2440
2441 /*
2442  * Build a synchronous negotiation message in our message
2443  * buffer based on the input parameters.
2444  */
2445 static void
2446 ahc_construct_sdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2447                    u_int period, u_int offset)
2448 {
2449         if (offset == 0)
2450                 period = AHC_ASYNC_XFER_PERIOD;
2451         ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
2452         ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN;
2453         ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR;
2454         ahc->msgout_buf[ahc->msgout_index++] = period;
2455         ahc->msgout_buf[ahc->msgout_index++] = offset;
2456         ahc->msgout_len += 5;
2457         if (bootverbose) {
2458                 kprintf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n",
2459                        ahc_name(ahc), devinfo->channel, devinfo->target,
2460                        devinfo->lun, period, offset);
2461         }
2462 }
2463
2464 /*
2465  * Build a wide negotiation message in our message
2466  * buffer based on the input parameters.
2467  */
2468 static void
2469 ahc_construct_wdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2470                    u_int bus_width)
2471 {
2472         ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
2473         ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN;
2474         ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR;
2475         ahc->msgout_buf[ahc->msgout_index++] = bus_width;
2476         ahc->msgout_len += 4;
2477         if (bootverbose) {
2478                 kprintf("(%s:%c:%d:%d): Sending WDTR %x\n",
2479                        ahc_name(ahc), devinfo->channel, devinfo->target,
2480                        devinfo->lun, bus_width);
2481         }
2482 }
2483
2484 /*
2485  * Build a parallel protocol request message in our message
2486  * buffer based on the input parameters.
2487  */
2488 static void
2489 ahc_construct_ppr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2490                   u_int period, u_int offset, u_int bus_width,
2491                   u_int ppr_options)
2492 {
2493         if (offset == 0)
2494                 period = AHC_ASYNC_XFER_PERIOD;
2495         ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
2496         ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR_LEN;
2497         ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR;
2498         ahc->msgout_buf[ahc->msgout_index++] = period;
2499         ahc->msgout_buf[ahc->msgout_index++] = 0;
2500         ahc->msgout_buf[ahc->msgout_index++] = offset;
2501         ahc->msgout_buf[ahc->msgout_index++] = bus_width;
2502         ahc->msgout_buf[ahc->msgout_index++] = ppr_options;
2503         ahc->msgout_len += 8;
2504         if (bootverbose) {
2505                 kprintf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, "
2506                        "offset %x, ppr_options %x\n", ahc_name(ahc),
2507                        devinfo->channel, devinfo->target, devinfo->lun,
2508                        bus_width, period, offset, ppr_options);
2509         }
2510 }
2511
2512 /*
2513  * Clear any active message state.
2514  */
2515 static void
2516 ahc_clear_msg_state(struct ahc_softc *ahc)
2517 {
2518         ahc->msgout_len = 0;
2519         ahc->msgin_index = 0;
2520         ahc->msg_type = MSG_TYPE_NONE;
2521         if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0) {
2522                 /*
2523                  * The target didn't care to respond to our
2524                  * message request, so clear ATN.
2525                  */
2526                 ahc_outb(ahc, CLRSINT1, CLRATNO);
2527         }
2528         ahc_outb(ahc, MSG_OUT, MSG_NOOP);
2529         ahc_outb(ahc, SEQ_FLAGS2,
2530                  ahc_inb(ahc, SEQ_FLAGS2) & ~TARGET_MSG_PENDING);
2531 }
2532
2533 static void
2534 ahc_handle_proto_violation(struct ahc_softc *ahc)
2535 {
2536         struct  ahc_devinfo devinfo;
2537         struct  scb *scb;
2538         u_int   scbid;
2539         u_int   seq_flags;
2540         u_int   curphase;
2541         u_int   lastphase;
2542         int     found;
2543
2544         ahc_fetch_devinfo(ahc, &devinfo);
2545         scbid = ahc_inb(ahc, SCB_TAG);
2546         scb = ahc_lookup_scb(ahc, scbid);
2547         seq_flags = ahc_inb(ahc, SEQ_FLAGS);
2548         curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
2549         lastphase = ahc_inb(ahc, LASTPHASE);
2550         if ((seq_flags & NOT_IDENTIFIED) != 0) {
2551
2552                 /*
2553                  * The reconnecting target either did not send an
2554                  * identify message, or did, but we didn't find an SCB
2555                  * to match.
2556                  */
2557                 ahc_print_devinfo(ahc, &devinfo);
2558                 kprintf("Target did not send an IDENTIFY message. "
2559                        "LASTPHASE = 0x%x.\n", lastphase);
2560                 scb = NULL;
2561         } else if (scb == NULL) {
2562                 /*
2563                  * We don't seem to have an SCB active for this
2564                  * transaction.  Print an error and reset the bus.
2565                  */
2566                 ahc_print_devinfo(ahc, &devinfo);
2567                 kprintf("No SCB found during protocol violation\n");
2568                 goto proto_violation_reset;
2569         } else {
2570                 aic_set_transaction_status(scb, CAM_SEQUENCE_FAIL);
2571                 if ((seq_flags & NO_CDB_SENT) != 0) {
2572                         ahc_print_path(ahc, scb);
2573                         kprintf("No or incomplete CDB sent to device.\n");
2574                 } else if ((ahc_inb(ahc, SCB_CONTROL) & STATUS_RCVD) == 0) {
2575                         /*
2576                          * The target never bothered to provide status to
2577                          * us prior to completing the command.  Since we don't
2578                          * know the disposition of this command, we must attempt
2579                          * to abort it.  Assert ATN and prepare to send an abort
2580                          * message.
2581                          */
2582                         ahc_print_path(ahc, scb);
2583                         kprintf("Completed command without status.\n");
2584                 } else {
2585                         ahc_print_path(ahc, scb);
2586                         kprintf("Unknown protocol violation.\n");
2587                         ahc_dump_card_state(ahc);
2588                 }
2589         }
2590         if ((lastphase & ~P_DATAIN_DT) == 0
2591          || lastphase == P_COMMAND) {
2592 proto_violation_reset:
2593                 /*
2594                  * Target either went directly to data/command
2595                  * phase or didn't respond to our ATN.
2596                  * The only safe thing to do is to blow
2597                  * it away with a bus reset.
2598                  */
2599                 found = ahc_reset_channel(ahc, 'A', TRUE);
2600                 kprintf("%s: Issued Channel %c Bus Reset. "
2601                        "%d SCBs aborted\n", ahc_name(ahc), 'A', found);
2602         } else {
2603                 /*
2604                  * Leave the selection hardware off in case
2605                  * this abort attempt will affect yet to
2606                  * be sent commands.
2607                  */
2608                 ahc_outb(ahc, SCSISEQ,
2609                          ahc_inb(ahc, SCSISEQ) & ~ENSELO);
2610                 ahc_assert_atn(ahc);
2611                 ahc_outb(ahc, MSG_OUT, HOST_MSG);
2612                 if (scb == NULL) {
2613                         ahc_print_devinfo(ahc, &devinfo);
2614                         ahc->msgout_buf[0] = MSG_ABORT_TASK;
2615                         ahc->msgout_len = 1;
2616                         ahc->msgout_index = 0;
2617                         ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2618                 } else {
2619                         ahc_print_path(ahc, scb);
2620                         scb->flags |= SCB_ABORT;
2621                 }
2622                 kprintf("Protocol violation %s.  Attempting to abort.\n",
2623                        ahc_lookup_phase_entry(curphase)->phasemsg);
2624         }
2625 }
2626
2627 /*
2628  * Manual message loop handler.
2629  */
2630 static void
2631 ahc_handle_message_phase(struct ahc_softc *ahc)
2632
2633         struct  ahc_devinfo devinfo;
2634         u_int   bus_phase;
2635         int     end_session;
2636
2637         ahc_fetch_devinfo(ahc, &devinfo);
2638         end_session = FALSE;
2639         bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
2640
2641 reswitch:
2642         switch (ahc->msg_type) {
2643         case MSG_TYPE_INITIATOR_MSGOUT:
2644         {
2645                 int lastbyte;
2646                 int phasemis;
2647                 int msgdone;
2648
2649                 if (ahc->msgout_len == 0)
2650                         panic("HOST_MSG_LOOP interrupt with no active message");
2651
2652 #ifdef AHC_DEBUG
2653                 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2654                         ahc_print_devinfo(ahc, &devinfo);
2655                         kprintf("INITIATOR_MSG_OUT");
2656                 }
2657 #endif
2658                 phasemis = bus_phase != P_MESGOUT;
2659                 if (phasemis) {
2660 #ifdef AHC_DEBUG
2661                         if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2662                                 kprintf(" PHASEMIS %s\n",
2663                                        ahc_lookup_phase_entry(bus_phase)
2664                                                              ->phasemsg);
2665                         }
2666 #endif
2667                         if (bus_phase == P_MESGIN) {
2668                                 /*
2669                                  * Change gears and see if
2670                                  * this messages is of interest to
2671                                  * us or should be passed back to
2672                                  * the sequencer.
2673                                  */
2674                                 ahc_outb(ahc, CLRSINT1, CLRATNO);
2675                                 ahc->send_msg_perror = FALSE;
2676                                 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN;
2677                                 ahc->msgin_index = 0;
2678                                 goto reswitch;
2679                         }
2680                         end_session = TRUE;
2681                         break;
2682                 }
2683
2684                 if (ahc->send_msg_perror) {
2685                         ahc_outb(ahc, CLRSINT1, CLRATNO);
2686                         ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2687 #ifdef AHC_DEBUG
2688                         if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2689                                 kprintf(" byte 0x%x\n", ahc->send_msg_perror);
2690 #endif
2691                         ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR);
2692                         break;
2693                 }
2694
2695                 msgdone = ahc->msgout_index == ahc->msgout_len;
2696                 if (msgdone) {
2697                         /*
2698                          * The target has requested a retry.
2699                          * Re-assert ATN, reset our message index to
2700                          * 0, and try again.
2701                          */
2702                         ahc->msgout_index = 0;
2703                         ahc_assert_atn(ahc);
2704                 }
2705
2706                 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1);
2707                 if (lastbyte) {
2708                         /* Last byte is signified by dropping ATN */
2709                         ahc_outb(ahc, CLRSINT1, CLRATNO);
2710                 }
2711
2712                 /*
2713                  * Clear our interrupt status and present
2714                  * the next byte on the bus.
2715                  */
2716                 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2717 #ifdef AHC_DEBUG
2718                 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2719                         kprintf(" byte 0x%x\n",
2720                                ahc->msgout_buf[ahc->msgout_index]);
2721 #endif
2722                 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]);
2723                 break;
2724         }
2725         case MSG_TYPE_INITIATOR_MSGIN:
2726         {
2727                 int phasemis;
2728                 int message_done;
2729
2730 #ifdef AHC_DEBUG
2731                 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2732                         ahc_print_devinfo(ahc, &devinfo);
2733                         kprintf("INITIATOR_MSG_IN");
2734                 }
2735 #endif
2736                 phasemis = bus_phase != P_MESGIN;
2737                 if (phasemis) {
2738 #ifdef AHC_DEBUG
2739                         if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2740                                 kprintf(" PHASEMIS %s\n",
2741                                        ahc_lookup_phase_entry(bus_phase)
2742                                                              ->phasemsg);
2743                         }
2744 #endif
2745                         ahc->msgin_index = 0;
2746                         if (bus_phase == P_MESGOUT
2747                          && (ahc->send_msg_perror == TRUE
2748                           || (ahc->msgout_len != 0
2749                            && ahc->msgout_index == 0))) {
2750                                 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2751                                 goto reswitch;
2752                         }
2753                         end_session = TRUE;
2754                         break;
2755                 }
2756
2757                 /* Pull the byte in without acking it */
2758                 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL);
2759 #ifdef AHC_DEBUG
2760                 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2761                         kprintf(" byte 0x%x\n",
2762                                ahc->msgin_buf[ahc->msgin_index]);
2763 #endif
2764
2765                 message_done = ahc_parse_msg(ahc, &devinfo);
2766
2767                 if (message_done) {
2768                         /*
2769                          * Clear our incoming message buffer in case there
2770                          * is another message following this one.
2771                          */
2772                         ahc->msgin_index = 0;
2773
2774                         /*
2775                          * If this message illicited a response,
2776                          * assert ATN so the target takes us to the
2777                          * message out phase.
2778                          */
2779                         if (ahc->msgout_len != 0) {
2780 #ifdef AHC_DEBUG
2781                                 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2782                                         ahc_print_devinfo(ahc, &devinfo);
2783                                         kprintf("Asserting ATN for response\n");
2784                                 }
2785 #endif
2786                                 ahc_assert_atn(ahc);
2787                         }
2788                 } else 
2789                         ahc->msgin_index++;
2790
2791                 if (message_done == MSGLOOP_TERMINATED) {
2792                         end_session = TRUE;
2793                 } else {
2794                         /* Ack the byte */
2795                         ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2796                         ahc_inb(ahc, SCSIDATL);
2797                 }
2798                 break;
2799         }
2800         case MSG_TYPE_TARGET_MSGIN:
2801         {
2802                 int msgdone;
2803                 int msgout_request;
2804
2805                 if (ahc->msgout_len == 0)
2806                         panic("Target MSGIN with no active message");
2807
2808                 /*
2809                  * If we interrupted a mesgout session, the initiator
2810                  * will not know this until our first REQ.  So, we
2811                  * only honor mesgout requests after we've sent our
2812                  * first byte.
2813                  */
2814                 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0
2815                  && ahc->msgout_index > 0)
2816                         msgout_request = TRUE;
2817                 else
2818                         msgout_request = FALSE;
2819
2820                 if (msgout_request) {
2821
2822                         /*
2823                          * Change gears and see if
2824                          * this messages is of interest to
2825                          * us or should be passed back to
2826                          * the sequencer.
2827                          */
2828                         ahc->msg_type = MSG_TYPE_TARGET_MSGOUT;
2829                         ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO);
2830                         ahc->msgin_index = 0;
2831                         /* Dummy read to REQ for first byte */
2832                         ahc_inb(ahc, SCSIDATL);
2833                         ahc_outb(ahc, SXFRCTL0,
2834                                  ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2835                         break;
2836                 }
2837
2838                 msgdone = ahc->msgout_index == ahc->msgout_len;
2839                 if (msgdone) {
2840                         ahc_outb(ahc, SXFRCTL0,
2841                                  ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
2842                         end_session = TRUE;
2843                         break;
2844                 }
2845
2846                 /*
2847                  * Present the next byte on the bus.
2848                  */
2849                 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2850                 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]);
2851                 break;
2852         }
2853         case MSG_TYPE_TARGET_MSGOUT:
2854         {
2855                 int lastbyte;
2856                 int msgdone;
2857
2858                 /*
2859                  * The initiator signals that this is
2860                  * the last byte by dropping ATN.
2861                  */
2862                 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0;
2863
2864                 /*
2865                  * Read the latched byte, but turn off SPIOEN first
2866                  * so that we don't inadvertently cause a REQ for the
2867                  * next byte.
2868                  */
2869                 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
2870                 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL);
2871                 msgdone = ahc_parse_msg(ahc, &devinfo);
2872                 if (msgdone == MSGLOOP_TERMINATED) {
2873                         /*
2874                          * The message is *really* done in that it caused
2875                          * us to go to bus free.  The sequencer has already
2876                          * been reset at this point, so pull the ejection
2877                          * handle.
2878                          */
2879                         return;
2880                 }
2881                 
2882                 ahc->msgin_index++;
2883
2884                 /*
2885                  * XXX Read spec about initiator dropping ATN too soon
2886                  *     and use msgdone to detect it.
2887                  */
2888                 if (msgdone == MSGLOOP_MSGCOMPLETE) {
2889                         ahc->msgin_index = 0;
2890
2891                         /*
2892                          * If this message illicited a response, transition
2893                          * to the Message in phase and send it.
2894                          */
2895                         if (ahc->msgout_len != 0) {
2896                                 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO);
2897                                 ahc_outb(ahc, SXFRCTL0,
2898                                          ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2899                                 ahc->msg_type = MSG_TYPE_TARGET_MSGIN;
2900                                 ahc->msgin_index = 0;
2901                                 break;
2902                         }
2903                 }
2904
2905                 if (lastbyte)
2906                         end_session = TRUE;
2907                 else {
2908                         /* Ask for the next byte. */
2909                         ahc_outb(ahc, SXFRCTL0,
2910                                  ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2911                 }
2912
2913                 break;
2914         }
2915         default:
2916                 panic("Unknown REQINIT message type");
2917         }
2918
2919         if (end_session) {
2920                 ahc_clear_msg_state(ahc);
2921                 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP);
2922         } else
2923                 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP);
2924 }
2925
2926 /*
2927  * See if we sent a particular extended message to the target.
2928  * If "full" is true, return true only if the target saw the full
2929  * message.  If "full" is false, return true if the target saw at
2930  * least the first byte of the message.
2931  */
2932 static int
2933 ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, u_int msgval, int full)
2934 {
2935         int found;
2936         u_int index;
2937
2938         found = FALSE;
2939         index = 0;
2940
2941         while (index < ahc->msgout_len) {
2942                 if (ahc->msgout_buf[index] == MSG_EXTENDED) {
2943                         u_int end_index;
2944
2945                         end_index = index + 1 + ahc->msgout_buf[index + 1];
2946                         if (ahc->msgout_buf[index+2] == msgval
2947                          && type == AHCMSG_EXT) {
2948
2949                                 if (full) {
2950                                         if (ahc->msgout_index > end_index)
2951                                                 found = TRUE;
2952                                 } else if (ahc->msgout_index > index)
2953                                         found = TRUE;
2954                         }
2955                         index = end_index;
2956                 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_TASK
2957                         && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) {
2958
2959                         /* Skip tag type and tag id or residue param*/
2960                         index += 2;
2961                 } else {
2962                         /* Single byte message */
2963                         if (type == AHCMSG_1B
2964                          && ahc->msgout_buf[index] == msgval
2965                          && ahc->msgout_index > index)
2966                                 found = TRUE;
2967                         index++;
2968                 }
2969
2970                 if (found)
2971                         break;
2972         }
2973         return (found);
2974 }
2975
2976 /*
2977  * Wait for a complete incoming message, parse it, and respond accordingly.
2978  */
2979 static int
2980 ahc_parse_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2981 {
2982         struct  ahc_initiator_tinfo *tinfo;
2983         struct  ahc_tmode_tstate *tstate;
2984         int     reject;
2985         int     done;
2986         int     response;
2987         u_int   targ_scsirate;
2988
2989         done = MSGLOOP_IN_PROG;
2990         response = FALSE;
2991         reject = FALSE;
2992         tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
2993                                     devinfo->target, &tstate);
2994         targ_scsirate = tinfo->scsirate;
2995
2996         /*
2997          * Parse as much of the message as is available,
2998          * rejecting it if we don't support it.  When
2999          * the entire message is available and has been
3000          * handled, return MSGLOOP_MSGCOMPLETE, indicating
3001          * that we have parsed an entire message.
3002          *
3003          * In the case of extended messages, we accept the length
3004          * byte outright and perform more checking once we know the
3005          * extended message type.
3006          */
3007         switch (ahc->msgin_buf[0]) {
3008         case MSG_DISCONNECT:
3009         case MSG_SAVEDATAPOINTER:
3010         case MSG_CMDCOMPLETE:
3011         case MSG_RESTOREPOINTERS:
3012         case MSG_IGN_WIDE_RESIDUE:
3013                 /*
3014                  * End our message loop as these are messages
3015                  * the sequencer handles on its own.
3016                  */
3017                 done = MSGLOOP_TERMINATED;
3018                 break;
3019         case MSG_MESSAGE_REJECT:
3020                 response = ahc_handle_msg_reject(ahc, devinfo);
3021                 /* FALLTHROUGH */
3022         case MSG_NOOP:
3023                 done = MSGLOOP_MSGCOMPLETE;
3024                 break;
3025         case MSG_EXTENDED:
3026         {
3027                 /* Wait for enough of the message to begin validation */
3028                 if (ahc->msgin_index < 2)
3029                         break;
3030                 switch (ahc->msgin_buf[2]) {
3031                 case MSG_EXT_SDTR:
3032                 {
3033                         struct   ahc_syncrate *syncrate;
3034                         u_int    period;
3035                         u_int    ppr_options;
3036                         u_int    offset;
3037                         u_int    saved_offset;
3038                         
3039                         if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) {
3040                                 reject = TRUE;
3041                                 break;
3042                         }
3043
3044                         /*
3045                          * Wait until we have both args before validating
3046                          * and acting on this message.
3047                          *
3048                          * Add one to MSG_EXT_SDTR_LEN to account for
3049                          * the extended message preamble.
3050                          */
3051                         if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1))
3052                                 break;
3053
3054                         period = ahc->msgin_buf[3];
3055                         ppr_options = 0;
3056                         saved_offset = offset = ahc->msgin_buf[4];
3057                         syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period,
3058                                                            &ppr_options,
3059                                                            devinfo->role);
3060                         ahc_validate_offset(ahc, tinfo, syncrate, &offset,
3061                                             targ_scsirate & WIDEXFER,
3062                                             devinfo->role);
3063                         if (bootverbose) {
3064                                 kprintf("(%s:%c:%d:%d): Received "
3065                                        "SDTR period %x, offset %x\n\t"
3066                                        "Filtered to period %x, offset %x\n",
3067                                        ahc_name(ahc), devinfo->channel,
3068                                        devinfo->target, devinfo->lun,
3069                                        ahc->msgin_buf[3], saved_offset,
3070                                        period, offset);
3071                         }
3072                         ahc_set_syncrate(ahc, devinfo, 
3073                                          syncrate, period,
3074                                          offset, ppr_options,
3075                                          AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3076                                          /*paused*/TRUE);
3077
3078                         /*
3079                          * See if we initiated Sync Negotiation
3080                          * and didn't have to fall down to async
3081                          * transfers.
3082                          */
3083                         if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, TRUE)) {
3084                                 /* We started it */
3085                                 if (saved_offset != offset) {
3086                                         /* Went too low - force async */
3087                                         reject = TRUE;
3088                                 }
3089                         } else {
3090                                 /*
3091                                  * Send our own SDTR in reply
3092                                  */
3093                                 if (bootverbose
3094                                  && devinfo->role == ROLE_INITIATOR) {
3095                                         kprintf("(%s:%c:%d:%d): Target "
3096                                                "Initiated SDTR\n",
3097                                                ahc_name(ahc), devinfo->channel,
3098                                                devinfo->target, devinfo->lun);
3099                                 }
3100                                 ahc->msgout_index = 0;
3101                                 ahc->msgout_len = 0;
3102                                 ahc_construct_sdtr(ahc, devinfo,
3103                                                    period, offset);
3104                                 ahc->msgout_index = 0;
3105                                 response = TRUE;
3106                         }
3107                         done = MSGLOOP_MSGCOMPLETE;
3108                         break;
3109                 }
3110                 case MSG_EXT_WDTR:
3111                 {
3112                         u_int bus_width;
3113                         u_int saved_width;
3114                         u_int sending_reply;
3115
3116                         sending_reply = FALSE;
3117                         if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) {
3118                                 reject = TRUE;
3119                                 break;
3120                         }
3121
3122                         /*
3123                          * Wait until we have our arg before validating
3124                          * and acting on this message.
3125                          *
3126                          * Add one to MSG_EXT_WDTR_LEN to account for
3127                          * the extended message preamble.
3128                          */
3129                         if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1))
3130                                 break;
3131
3132                         bus_width = ahc->msgin_buf[3];
3133                         saved_width = bus_width;
3134                         ahc_validate_width(ahc, tinfo, &bus_width,
3135                                            devinfo->role);
3136                         if (bootverbose) {
3137                                 kprintf("(%s:%c:%d:%d): Received WDTR "
3138                                        "%x filtered to %x\n",
3139                                        ahc_name(ahc), devinfo->channel,
3140                                        devinfo->target, devinfo->lun,
3141                                        saved_width, bus_width);
3142                         }
3143
3144                         if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, TRUE)) {
3145                                 /*
3146                                  * Don't send a WDTR back to the
3147                                  * target, since we asked first.
3148                                  * If the width went higher than our
3149                                  * request, reject it.
3150                                  */
3151                                 if (saved_width > bus_width) {
3152                                         reject = TRUE;
3153                                         kprintf("(%s:%c:%d:%d): requested %dBit "
3154                                                "transfers.  Rejecting...\n",
3155                                                ahc_name(ahc), devinfo->channel,
3156                                                devinfo->target, devinfo->lun,
3157                                                8 * (0x01 << bus_width));
3158                                         bus_width = 0;
3159                                 }
3160                         } else {
3161                                 /*
3162                                  * Send our own WDTR in reply
3163                                  */
3164                                 if (bootverbose
3165                                  && devinfo->role == ROLE_INITIATOR) {
3166                                         kprintf("(%s:%c:%d:%d): Target "
3167                                                "Initiated WDTR\n",
3168                                                ahc_name(ahc), devinfo->channel,
3169                                                devinfo->target, devinfo->lun);
3170                                 }
3171                                 ahc->msgout_index = 0;
3172                                 ahc->msgout_len = 0;
3173                                 ahc_construct_wdtr(ahc, devinfo, bus_width);
3174                                 ahc->msgout_index = 0;
3175                                 response = TRUE;
3176                                 sending_reply = TRUE;
3177                         }
3178                         /*
3179                          * After a wide message, we are async, but
3180                          * some devices don't seem to honor this portion
3181                          * of the spec.  Force a renegotiation of the
3182                          * sync component of our transfer agreement even
3183                          * if our goal is async.  By updating our width
3184                          * after forcing the negotiation, we avoid
3185                          * renegotiating for width.
3186                          */
3187                         ahc_update_neg_request(ahc, devinfo, tstate,
3188                                                tinfo, AHC_NEG_ALWAYS);
3189                         ahc_set_width(ahc, devinfo, bus_width,
3190                                       AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3191                                       /*paused*/TRUE);
3192                         if (sending_reply == FALSE && reject == FALSE) {
3193
3194                                 /*
3195                                  * We will always have an SDTR to send.
3196                                  */
3197                                 ahc->msgout_index = 0;
3198                                 ahc->msgout_len = 0;
3199                                 ahc_build_transfer_msg(ahc, devinfo);
3200                                 ahc->msgout_index = 0;
3201                                 response = TRUE;
3202                         }
3203                         done = MSGLOOP_MSGCOMPLETE;
3204                         break;
3205                 }
3206                 case MSG_EXT_PPR:
3207                 {
3208                         struct  ahc_syncrate *syncrate;
3209                         u_int   period;
3210                         u_int   offset;
3211                         u_int   bus_width;
3212                         u_int   ppr_options;
3213                         u_int   saved_width;
3214                         u_int   saved_offset;
3215                         u_int   saved_ppr_options;
3216
3217                         if (ahc->msgin_buf[1] != MSG_EXT_PPR_LEN) {
3218                                 reject = TRUE;
3219                                 break;
3220                         }
3221
3222                         /*
3223                          * Wait until we have all args before validating
3224                          * and acting on this message.
3225                          *
3226                          * Add one to MSG_EXT_PPR_LEN to account for
3227                          * the extended message preamble.
3228                          */
3229                         if (ahc->msgin_index < (MSG_EXT_PPR_LEN + 1))
3230                                 break;
3231
3232                         period = ahc->msgin_buf[3];
3233                         offset = ahc->msgin_buf[5];
3234                         bus_width = ahc->msgin_buf[6];
3235                         saved_width = bus_width;
3236                         ppr_options = ahc->msgin_buf[7];
3237                         /*
3238                          * According to the spec, a DT only
3239                          * period factor with no DT option
3240                          * set implies async.
3241                          */
3242                         if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0
3243                          && period == 9)
3244                                 offset = 0;
3245                         saved_ppr_options = ppr_options;
3246                         saved_offset = offset;
3247
3248                         /*
3249                          * Mask out any options we don't support
3250                          * on any controller.  Transfer options are
3251                          * only available if we are negotiating wide.
3252                          */
3253                         ppr_options &= MSG_EXT_PPR_DT_REQ;
3254                         if (bus_width == 0)
3255                                 ppr_options = 0;
3256
3257                         ahc_validate_width(ahc, tinfo, &bus_width,
3258                                            devinfo->role);
3259                         syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period,
3260                                                            &ppr_options,
3261                                                            devinfo->role);
3262                         ahc_validate_offset(ahc, tinfo, syncrate,
3263                                             &offset, bus_width,
3264                                             devinfo->role);
3265
3266                         if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, TRUE)) {
3267                                 /*
3268                                  * If we are unable to do any of the
3269                                  * requested options (we went too low),
3270                                  * then we'll have to reject the message.
3271                                  */
3272                                 if (saved_width > bus_width
3273                                  || saved_offset != offset
3274                                  || saved_ppr_options != ppr_options) {
3275                                         reject = TRUE;
3276                                         period = 0;
3277                                         offset = 0;
3278                                         bus_width = 0;
3279                                         ppr_options = 0;
3280                                         syncrate = NULL;
3281                                 }
3282                         } else {
3283                                 if (devinfo->role != ROLE_TARGET)
3284                                         kprintf("(%s:%c:%d:%d): Target "
3285                                                "Initiated PPR\n",
3286                                                ahc_name(ahc), devinfo->channel,
3287                                                devinfo->target, devinfo->lun);
3288                                 else
3289                                         kprintf("(%s:%c:%d:%d): Initiator "
3290                                                "Initiated PPR\n",
3291                                                ahc_name(ahc), devinfo->channel,
3292                                                devinfo->target, devinfo->lun);
3293                                 ahc->msgout_index = 0;
3294                                 ahc->msgout_len = 0;
3295                                 ahc_construct_ppr(ahc, devinfo, period, offset,
3296                                                   bus_width, ppr_options);
3297                                 ahc->msgout_index = 0;
3298                                 response = TRUE;
3299                         }
3300                         if (bootverbose) {
3301                                 kprintf("(%s:%c:%d:%d): Received PPR width %x, "
3302                                        "period %x, offset %x,options %x\n"
3303                                        "\tFiltered to width %x, period %x, "
3304                                        "offset %x, options %x\n",
3305                                        ahc_name(ahc), devinfo->channel,
3306                                        devinfo->target, devinfo->lun,
3307                                        saved_width, ahc->msgin_buf[3],
3308                                        saved_offset, saved_ppr_options,
3309                                        bus_width, period, offset, ppr_options);
3310                         }
3311                         ahc_set_width(ahc, devinfo, bus_width,
3312                                       AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3313                                       /*paused*/TRUE);
3314                         ahc_set_syncrate(ahc, devinfo,
3315                                          syncrate, period,
3316                                          offset, ppr_options,
3317                                          AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3318                                          /*paused*/TRUE);
3319                         done = MSGLOOP_MSGCOMPLETE;
3320                         break;
3321                 }
3322                 default:
3323                         /* Unknown extended message.  Reject it. */
3324                         reject = TRUE;
3325                         break;
3326                 }
3327                 break;
3328         }
3329 #ifdef AHC_TARGET_MODE
3330         case MSG_BUS_DEV_RESET:
3331                 ahc_handle_devreset(ahc, devinfo,
3332                                     CAM_BDR_SENT,
3333                                     "Bus Device Reset Received",
3334                                     /*verbose_level*/0);
3335                 ahc_restart(ahc);
3336                 done = MSGLOOP_TERMINATED;
3337                 break;
3338         case MSG_ABORT_TAG:
3339         case MSG_ABORT:
3340         case MSG_CLEAR_QUEUE:
3341         {
3342                 int tag;
3343
3344                 /* Target mode messages */
3345                 if (devinfo->role != ROLE_TARGET) {
3346                         reject = TRUE;
3347                         break;
3348                 }
3349                 tag = SCB_LIST_NULL;
3350                 if (ahc->msgin_buf[0] == MSG_ABORT_TAG)
3351                         tag = ahc_inb(ahc, INITIATOR_TAG);
3352                 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel,
3353                                devinfo->lun, tag, ROLE_TARGET,
3354                                CAM_REQ_ABORTED);
3355
3356                 tstate = ahc->enabled_targets[devinfo->our_scsiid];
3357                 if (tstate != NULL) {
3358                         struct ahc_tmode_lstate* lstate;
3359
3360                         lstate = tstate->enabled_luns[devinfo->lun];
3361                         if (lstate != NULL) {
3362                                 ahc_queue_lstate_event(ahc, lstate,
3363                                                        devinfo->our_scsiid,
3364                                                        ahc->msgin_buf[0],
3365                                                        /*arg*/tag);
3366                                 ahc_send_lstate_events(ahc, lstate);
3367                         }
3368                 }
3369                 ahc_restart(ahc);
3370                 done = MSGLOOP_TERMINATED;
3371                 break;
3372         }
3373 #endif
3374         case MSG_TERM_IO_PROC:
3375         default:
3376                 reject = TRUE;
3377                 break;
3378         }
3379
3380         if (reject) {
3381                 /*
3382                  * Setup to reject the message.
3383                  */
3384                 ahc->msgout_index = 0;
3385                 ahc->msgout_len = 1;
3386                 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT;
3387                 done = MSGLOOP_MSGCOMPLETE;
3388                 response = TRUE;
3389         }
3390
3391         if (done != MSGLOOP_IN_PROG && !response)
3392                 /* Clear the outgoing message buffer */
3393                 ahc->msgout_len = 0;
3394
3395         return (done);
3396 }
3397
3398 /*
3399  * Process a message reject message.
3400  */
3401 static int
3402 ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
3403 {