1 /* $OpenBSD: if_iwmreg.h,v 1.4 2015/06/15 08:06:11 stsp Exp $ */
4 /******************************************************************************
6 * This file is provided under a dual BSD/GPLv2 license. When using or
7 * redistributing this file, you may do so under either license.
11 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
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14 * it under the terms of version 2 of the GNU General Public License as
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24 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
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65 *****************************************************************************/
66 #ifndef __IF_IWM_REG_H__
67 #define __IF_IWM_REG_H__
69 #define le16_to_cpup(_a_) (le16toh(*(const uint16_t *)(_a_)))
70 #define le32_to_cpup(_a_) (le32toh(*(const uint32_t *)(_a_)))
73 * CSR (control and status registers)
75 * CSR registers are mapped directly into PCI bus space, and are accessible
76 * whenever platform supplies power to device, even when device is in
77 * low power states due to driver-invoked device resets
78 * (e.g. IWM_CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.
80 * Use iwl_write32() and iwl_read32() family to access these registers;
81 * these provide simple PCI bus access, without waking up the MAC.
82 * Do not use iwl_write_direct32() family for these registers;
83 * no need to "grab nic access" via IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ.
84 * The MAC (uCode processor, etc.) does not need to be powered up for accessing
87 * NOTE: Device does need to be awake in order to read this memory
88 * via IWM_CSR_EEPROM and IWM_CSR_OTP registers
90 #define IWM_CSR_HW_IF_CONFIG_REG (0x000) /* hardware interface config */
91 #define IWM_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */
92 #define IWM_CSR_INT (0x008) /* host interrupt status/ack */
93 #define IWM_CSR_INT_MASK (0x00c) /* host interrupt enable */
94 #define IWM_CSR_FH_INT_STATUS (0x010) /* busmaster int status/ack*/
95 #define IWM_CSR_GPIO_IN (0x018) /* read external chip pins */
96 #define IWM_CSR_RESET (0x020) /* busmaster enable, NMI, etc*/
97 #define IWM_CSR_GP_CNTRL (0x024)
99 /* 2nd byte of IWM_CSR_INT_COALESCING, not accessible via iwl_write32()! */
100 #define IWM_CSR_INT_PERIODIC_REG (0x005)
103 * Hardware revision info
106 * 15-4: Type of device: see IWM_CSR_HW_REV_TYPE_xxx definitions
107 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D
108 * 1-0: "Dash" (-) value, as in A-1, etc.
110 #define IWM_CSR_HW_REV (0x028)
113 * EEPROM and OTP (one-time-programmable) memory reads
115 * NOTE: Device must be awake, initialized via apm_ops.init(),
118 #define IWM_CSR_EEPROM_REG (0x02c)
119 #define IWM_CSR_EEPROM_GP (0x030)
120 #define IWM_CSR_OTP_GP_REG (0x034)
122 #define IWM_CSR_GIO_REG (0x03C)
123 #define IWM_CSR_GP_UCODE_REG (0x048)
124 #define IWM_CSR_GP_DRIVER_REG (0x050)
127 * UCODE-DRIVER GP (general purpose) mailbox registers.
128 * SET/CLR registers set/clear bit(s) if "1" is written.
130 #define IWM_CSR_UCODE_DRV_GP1 (0x054)
131 #define IWM_CSR_UCODE_DRV_GP1_SET (0x058)
132 #define IWM_CSR_UCODE_DRV_GP1_CLR (0x05c)
133 #define IWM_CSR_UCODE_DRV_GP2 (0x060)
135 #define IWM_CSR_LED_REG (0x094)
136 #define IWM_CSR_DRAM_INT_TBL_REG (0x0A0)
137 #define IWM_CSR_MAC_SHADOW_REG_CTRL (0x0A8) /* 6000 and up */
140 /* GIO Chicken Bits (PCI Express bus link power management) */
141 #define IWM_CSR_GIO_CHICKEN_BITS (0x100)
143 /* Analog phase-lock-loop configuration */
144 #define IWM_CSR_ANA_PLL_CFG (0x20c)
147 * CSR Hardware Revision Workaround Register. Indicates hardware rev;
148 * "step" determines CCK backoff for txpower calculation. Used for 4965 only.
149 * See also IWM_CSR_HW_REV register.
151 * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step
152 * 1-0: "Dash" (-) value, as in C-1, etc.
154 #define IWM_CSR_HW_REV_WA_REG (0x22C)
156 #define IWM_CSR_DBG_HPET_MEM_REG (0x240)
157 #define IWM_CSR_DBG_LINK_PWR_MGMT_REG (0x250)
159 /* Bits for IWM_CSR_HW_IF_CONFIG_REG */
160 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003)
161 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C)
162 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0)
163 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100)
164 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200)
165 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00)
166 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000)
167 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000)
169 #define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0)
170 #define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2)
171 #define IWM_CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6)
172 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10)
173 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12)
174 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14)
176 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000)
177 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
178 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */
179 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */
180 #define IWM_CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */
182 #define IWM_CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/
183 #define IWM_CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/
185 /* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
186 * acknowledged (reset) by host writing "1" to flagged bits. */
187 #define IWM_CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */
188 #define IWM_CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */
189 #define IWM_CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */
190 #define IWM_CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */
191 #define IWM_CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */
192 #define IWM_CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */
193 #define IWM_CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */
194 #define IWM_CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */
195 #define IWM_CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */
196 #define IWM_CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */
197 #define IWM_CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */
199 #define IWM_CSR_INI_SET_MASK (IWM_CSR_INT_BIT_FH_RX | \
200 IWM_CSR_INT_BIT_HW_ERR | \
201 IWM_CSR_INT_BIT_FH_TX | \
202 IWM_CSR_INT_BIT_SW_ERR | \
203 IWM_CSR_INT_BIT_RF_KILL | \
204 IWM_CSR_INT_BIT_SW_RX | \
205 IWM_CSR_INT_BIT_WAKEUP | \
206 IWM_CSR_INT_BIT_ALIVE | \
207 IWM_CSR_INT_BIT_RX_PERIODIC)
209 /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
210 #define IWM_CSR_FH_INT_BIT_ERR (1 << 31) /* Error */
211 #define IWM_CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */
212 #define IWM_CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */
213 #define IWM_CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */
214 #define IWM_CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */
215 #define IWM_CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */
217 #define IWM_CSR_FH_INT_RX_MASK (IWM_CSR_FH_INT_BIT_HI_PRIOR | \
218 IWM_CSR_FH_INT_BIT_RX_CHNL1 | \
219 IWM_CSR_FH_INT_BIT_RX_CHNL0)
221 #define IWM_CSR_FH_INT_TX_MASK (IWM_CSR_FH_INT_BIT_TX_CHNL1 | \
222 IWM_CSR_FH_INT_BIT_TX_CHNL0)
225 #define IWM_CSR_GPIO_IN_BIT_AUX_POWER (0x00000200)
226 #define IWM_CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000)
227 #define IWM_CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200)
230 #define IWM_CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001)
231 #define IWM_CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002)
232 #define IWM_CSR_RESET_REG_FLAG_SW_RESET (0x00000080)
233 #define IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100)
234 #define IWM_CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200)
235 #define IWM_CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000)
238 * GP (general purpose) CONTROL REGISTER
241 * Indicates state of (platform's) hardware RF-Kill switch
242 * 26-24: POWER_SAVE_TYPE
243 * Indicates current power-saving mode:
244 * 000 -- No power saving
245 * 001 -- MAC power-down
246 * 010 -- PHY (radio) power-down
249 * Indicates current system configuration, reflecting pins on chip
250 * as forced high/low by device circuit board.
252 * Indicates MAC is entering a power-saving sleep power-down.
253 * Not a good time to access device-internal resources.
255 * Host sets this to request and maintain MAC wakeup, to allow host
256 * access to device-internal resources. Host must wait for
257 * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR
260 * Host sets this to put device into fully operational D0 power mode.
261 * Host resets this after SW_RESET to put device into low power mode.
263 * Indicates MAC (ucode processor, etc.) is powered up and can run.
264 * Internal resources are accessible.
265 * NOTE: This does not indicate that the processor is actually running.
266 * NOTE: This does not indicate that device has completed
267 * init or post-power-down restore of internal SRAM memory.
268 * Use IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that
269 * SRAM is restored and uCode is in normal operation mode.
270 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
271 * do not need to save/restore it.
272 * NOTE: After device reset, this bit remains "0" until host sets
275 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001)
276 #define IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004)
277 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008)
278 #define IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010)
280 #define IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001)
282 #define IWM_CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000)
283 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000)
284 #define IWM_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000)
288 #define IWM_CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0)
289 #define IWM_CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2)
291 #define IWM_CSR_HW_REV_TYPE_MSK (0x000FFF0)
292 #define IWM_CSR_HW_REV_TYPE_5300 (0x0000020)
293 #define IWM_CSR_HW_REV_TYPE_5350 (0x0000030)
294 #define IWM_CSR_HW_REV_TYPE_5100 (0x0000050)
295 #define IWM_CSR_HW_REV_TYPE_5150 (0x0000040)
296 #define IWM_CSR_HW_REV_TYPE_1000 (0x0000060)
297 #define IWM_CSR_HW_REV_TYPE_6x00 (0x0000070)
298 #define IWM_CSR_HW_REV_TYPE_6x50 (0x0000080)
299 #define IWM_CSR_HW_REV_TYPE_6150 (0x0000084)
300 #define IWM_CSR_HW_REV_TYPE_6x05 (0x00000B0)
301 #define IWM_CSR_HW_REV_TYPE_6x30 IWM_CSR_HW_REV_TYPE_6x05
302 #define IWM_CSR_HW_REV_TYPE_6x35 IWM_CSR_HW_REV_TYPE_6x05
303 #define IWM_CSR_HW_REV_TYPE_2x30 (0x00000C0)
304 #define IWM_CSR_HW_REV_TYPE_2x00 (0x0000100)
305 #define IWM_CSR_HW_REV_TYPE_105 (0x0000110)
306 #define IWM_CSR_HW_REV_TYPE_135 (0x0000120)
307 #define IWM_CSR_HW_REV_TYPE_NONE (0x00001F0)
310 #define IWM_CSR_EEPROM_REG_READ_VALID_MSK (0x00000001)
311 #define IWM_CSR_EEPROM_REG_BIT_CMD (0x00000002)
312 #define IWM_CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC)
313 #define IWM_CSR_EEPROM_REG_MSK_DATA (0xFFFF0000)
316 #define IWM_CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */
317 #define IWM_CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180)
318 #define IWM_CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000)
319 #define IWM_CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001)
320 #define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002)
321 #define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004)
323 /* One-time-programmable memory general purpose reg */
324 #define IWM_CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */
325 #define IWM_CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */
326 #define IWM_CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */
327 #define IWM_CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */
330 #define IWM_CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */
331 #define IWM_CSR_GP_REG_NO_POWER_SAVE (0x00000000)
332 #define IWM_CSR_GP_REG_MAC_POWER_SAVE (0x01000000)
333 #define IWM_CSR_GP_REG_PHY_POWER_SAVE (0x02000000)
334 #define IWM_CSR_GP_REG_POWER_SAVE_ERROR (0x03000000)
338 #define IWM_CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002)
341 * UCODE-DRIVER GP (general purpose) mailbox register 1
342 * Host driver and uCode write and/or read this register to communicate with
346 * Host sets this to request permanent halt of uCode, same as
347 * sending CARD_STATE command with "halt" bit set.
349 * Host sets this to request exit from CT_KILL state, i.e. host thinks
350 * device temperature is low enough to continue normal operation.
352 * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL)
353 * to release uCode to clear all Tx and command queues, enter
354 * unassociated mode, and power down.
355 * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit.
357 * Host sets this when issuing CARD_STATE command to request
360 * uCode sets this when preparing a power-saving power-down.
361 * uCode resets this when power-up is complete and SRAM is sane.
362 * NOTE: device saves internal SRAM data to host when powering down,
363 * and must restore this data after powering back up.
364 * MAC_SLEEP is the best indication that restore is complete.
365 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
366 * do not need to save/restore it.
368 #define IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001)
369 #define IWM_CSR_UCODE_SW_BIT_RFKILL (0x00000002)
370 #define IWM_CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004)
371 #define IWM_CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008)
372 #define IWM_CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020)
375 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003)
376 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000)
377 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001)
378 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002)
379 #define IWM_CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004)
380 #define IWM_CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008)
382 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080)
384 /* GIO Chicken Bits (PCI Express bus link power management) */
385 #define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000)
386 #define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000)
389 #define IWM_CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF)
390 #define IWM_CSR_LED_REG_TURN_ON (0x60)
391 #define IWM_CSR_LED_REG_TURN_OFF (0x20)
394 #define IWM_CSR50_ANA_PLL_CFG_VAL (0x00880300)
397 #define IWM_CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000)
400 #define IWM_CSR_DRAM_INT_TBL_ENABLE (1 << 31)
401 #define IWM_CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27)
403 /* SECURE boot registers */
404 #define IWM_CSR_SECURE_BOOT_CONFIG_ADDR (0x100)
405 enum iwm_secure_boot_config_reg {
406 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP = 0x00000001,
407 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ = 0x00000002,
410 #define IWM_CSR_SECURE_BOOT_CPU1_STATUS_ADDR (0x100)
411 #define IWM_CSR_SECURE_BOOT_CPU2_STATUS_ADDR (0x100)
412 enum iwm_secure_boot_status_reg {
413 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS = 0x00000003,
414 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED = 0x00000002,
415 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_SUCCESS = 0x00000004,
416 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_FAIL = 0x00000008,
417 IWM_CSR_SECURE_BOOT_CPU_STATUS_SIGN_VERF_FAIL = 0x00000010,
420 #define IWM_CSR_UCODE_LOAD_STATUS_ADDR (0x100)
421 enum iwm_secure_load_status_reg {
422 IWM_CSR_CPU_STATUS_LOADING_STARTED = 0x00000001,
423 IWM_CSR_CPU_STATUS_LOADING_COMPLETED = 0x00000002,
424 IWM_CSR_CPU_STATUS_NUM_OF_LAST_COMPLETED = 0x000000F8,
425 IWM_CSR_CPU_STATUS_NUM_OF_LAST_LOADED_BLOCK = 0x0000FF00,
428 #define IWM_CSR_SECURE_INSPECTOR_CODE_ADDR (0x100)
429 #define IWM_CSR_SECURE_INSPECTOR_DATA_ADDR (0x100)
431 #define IWM_CSR_SECURE_TIME_OUT (100)
433 #define IWM_FH_TCSR_0_REG0 (0x1D00)
436 * HBUS (Host-side Bus)
438 * HBUS registers are mapped directly into PCI bus space, but are used
439 * to indirectly access device's internal memory or registers that
440 * may be powered-down.
442 * Use iwl_write_direct32()/iwl_read_direct32() family for these registers;
443 * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
444 * to make sure the MAC (uCode processor, etc.) is powered up for accessing
445 * internal resources.
447 * Do not use iwl_write32()/iwl_read32() family to access these registers;
448 * these provide only simple PCI bus access, without waking up the MAC.
450 #define IWM_HBUS_BASE (0x400)
453 * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM
454 * structures, error log, event log, verifying uCode load).
455 * First write to address register, then read from or write to data register
456 * to complete the job. Once the address register is set up, accesses to
457 * data registers auto-increment the address by one dword.
458 * Bit usage for address registers (read or write):
459 * 0-31: memory address within device
461 #define IWM_HBUS_TARG_MEM_RADDR (IWM_HBUS_BASE+0x00c)
462 #define IWM_HBUS_TARG_MEM_WADDR (IWM_HBUS_BASE+0x010)
463 #define IWM_HBUS_TARG_MEM_WDAT (IWM_HBUS_BASE+0x018)
464 #define IWM_HBUS_TARG_MEM_RDAT (IWM_HBUS_BASE+0x01c)
466 /* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */
467 #define IWM_HBUS_TARG_MBX_C (IWM_HBUS_BASE+0x030)
468 #define IWM_HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004)
471 * Registers for accessing device's internal peripheral registers
472 * (e.g. SCD, BSM, etc.). First write to address register,
473 * then read from or write to data register to complete the job.
474 * Bit usage for address registers (read or write):
475 * 0-15: register address (offset) within device
476 * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword)
478 #define IWM_HBUS_TARG_PRPH_WADDR (IWM_HBUS_BASE+0x044)
479 #define IWM_HBUS_TARG_PRPH_RADDR (IWM_HBUS_BASE+0x048)
480 #define IWM_HBUS_TARG_PRPH_WDAT (IWM_HBUS_BASE+0x04c)
481 #define IWM_HBUS_TARG_PRPH_RDAT (IWM_HBUS_BASE+0x050)
483 /* Used to enable DBGM */
484 #define IWM_HBUS_TARG_TEST_REG (IWM_HBUS_BASE+0x05c)
487 * Per-Tx-queue write pointer (index, really!)
488 * Indicates index to next TFD that driver will fill (1 past latest filled).
490 * 0-7: queue write index
491 * 11-8: queue selector
493 #define IWM_HBUS_TARG_WRPTR (IWM_HBUS_BASE+0x060)
495 /**********************************************************
497 **********************************************************/
499 * host interrupt timeout value
500 * used with setting interrupt coalescing timer
501 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
503 * default interrupt coalescing timer is 64 x 32 = 2048 usecs
505 #define IWM_HOST_INT_TIMEOUT_MAX (0xFF)
506 #define IWM_HOST_INT_TIMEOUT_DEF (0x40)
507 #define IWM_HOST_INT_TIMEOUT_MIN (0x0)
508 #define IWM_HOST_INT_OPER_MODE (1 << 31)
510 /*****************************************************************************
511 * 7000/3000 series SHR DTS addresses *
512 *****************************************************************************/
514 /* Diode Results Register Structure: */
515 enum iwm_dtd_diode_reg {
516 IWM_DTS_DIODE_REG_DIG_VAL = 0x000000FF, /* bits [7:0] */
517 IWM_DTS_DIODE_REG_VREF_LOW = 0x0000FF00, /* bits [15:8] */
518 IWM_DTS_DIODE_REG_VREF_HIGH = 0x00FF0000, /* bits [23:16] */
519 IWM_DTS_DIODE_REG_VREF_ID = 0x03000000, /* bits [25:24] */
520 IWM_DTS_DIODE_REG_PASS_ONCE = 0x80000000, /* bits [31:31] */
521 IWM_DTS_DIODE_REG_FLAGS_MSK = 0xFF000000, /* bits [31:24] */
522 /* Those are the masks INSIDE the flags bit-field: */
523 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID_POS = 0,
524 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID = 0x00000003, /* bits [1:0] */
525 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE_POS = 7,
526 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE = 0x00000080, /* bits [7:7] */
530 * enum iwl_ucode_tlv_flag - ucode API flags
531 * @IWM_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously
532 * was a separate TLV but moved here to save space.
533 * @IWM_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID,
534 * treats good CRC threshold as a boolean
535 * @IWM_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w).
536 * @IWM_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P.
537 * @IWM_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS
538 * @IWM_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD
539 * @IWM_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan
540 * offload profile config command.
541 * @IWM_UCODE_TLV_FLAGS_RX_ENERGY_API: supports rx signal strength api
542 * @IWM_UCODE_TLV_FLAGS_TIME_EVENT_API_V2: using the new time event API.
543 * @IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six
544 * (rather than two) IPv6 addresses
545 * @IWM_UCODE_TLV_FLAGS_BF_UPDATED: new beacon filtering API
546 * @IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element
547 * from the probe request template.
548 * @IWM_UCODE_TLV_FLAGS_D3_CONTINUITY_API: modified D3 API to allow keeping
549 * connection when going back to D0
550 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version)
551 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version)
552 * @IWM_UCODE_TLV_FLAGS_SCHED_SCAN: this uCode image supports scheduled scan.
553 * @IWM_UCODE_TLV_FLAGS_STA_KEY_CMD: new ADD_STA and ADD_STA_KEY command API
554 * @IWM_UCODE_TLV_FLAGS_DEVICE_PS_CMD: support device wide power command
555 * containing CAM (Continuous Active Mode) indication.
556 * @IWM_UCODE_TLV_FLAGS_P2P_PS: P2P client power save is supported (only on a
557 * single bound interface).
558 * @IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD: P2P client supports uAPSD power save
560 enum iwm_ucode_tlv_flag {
561 IWM_UCODE_TLV_FLAGS_PAN = (1 << 0),
562 IWM_UCODE_TLV_FLAGS_NEWSCAN = (1 << 1),
563 IWM_UCODE_TLV_FLAGS_MFP = (1 << 2),
564 IWM_UCODE_TLV_FLAGS_P2P = (1 << 3),
565 IWM_UCODE_TLV_FLAGS_DW_BC_TABLE = (1 << 4),
566 IWM_UCODE_TLV_FLAGS_NEWBT_COEX = (1 << 5),
567 IWM_UCODE_TLV_FLAGS_PM_CMD_SUPPORT = (1 << 6),
568 IWM_UCODE_TLV_FLAGS_SHORT_BL = (1 << 7),
569 IWM_UCODE_TLV_FLAGS_RX_ENERGY_API = (1 << 8),
570 IWM_UCODE_TLV_FLAGS_TIME_EVENT_API_V2 = (1 << 9),
571 IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = (1 << 10),
572 IWM_UCODE_TLV_FLAGS_BF_UPDATED = (1 << 11),
573 IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID = (1 << 12),
574 IWM_UCODE_TLV_FLAGS_D3_CONTINUITY_API = (1 << 14),
575 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = (1 << 15),
576 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = (1 << 16),
577 IWM_UCODE_TLV_FLAGS_SCHED_SCAN = (1 << 17),
578 IWM_UCODE_TLV_FLAGS_STA_KEY_CMD = (1 << 19),
579 IWM_UCODE_TLV_FLAGS_DEVICE_PS_CMD = (1 << 20),
580 IWM_UCODE_TLV_FLAGS_P2P_PS = (1 << 21),
581 IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT = (1 << 24),
582 IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD = (1 << 26),
585 /* The default calibrate table size if not specified by firmware file */
586 #define IWM_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE 18
587 #define IWM_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE 19
588 #define IWM_MAX_PHY_CALIBRATE_TBL_SIZE 253
590 /* The default max probe length if not specified by the firmware file */
591 #define IWM_DEFAULT_MAX_PROBE_LENGTH 200
594 * enumeration of ucode section.
595 * This enumeration is used directly for older firmware (before 16.0).
596 * For new firmware, there can be up to 4 sections (see below) but the
597 * first one packaged into the firmware file is the DATA section and
598 * some debugging code accesses that.
601 IWM_UCODE_SECTION_DATA,
602 IWM_UCODE_SECTION_INST,
605 * For 16.0 uCode and above, there is no differentiation between sections,
606 * just an offset to the HW address.
608 #define IWM_UCODE_SECTION_MAX 6
609 #define IWM_UCODE_FIRST_SECTION_OF_SECOND_CPU (IWM_UCODE_SECTION_MAX/2)
611 /* uCode version contains 4 values: Major/Minor/API/Serial */
612 #define IWM_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24)
613 #define IWM_UCODE_MINOR(ver) (((ver) & 0x00FF0000) >> 16)
614 #define IWM_UCODE_API(ver) (((ver) & 0x0000FF00) >> 8)
615 #define IWM_UCODE_SERIAL(ver) ((ver) & 0x000000FF)
618 * Calibration control struct.
619 * Sent as part of the phy configuration command.
620 * @flow_trigger: bitmap for which calibrations to perform according to
622 * @event_trigger: bitmap for which calibrations to perform according to
625 struct iwm_tlv_calib_ctrl {
626 uint32_t flow_trigger;
627 uint32_t event_trigger;
630 enum iwm_fw_phy_cfg {
631 IWM_FW_PHY_CFG_RADIO_TYPE_POS = 0,
632 IWM_FW_PHY_CFG_RADIO_TYPE = 0x3 << IWM_FW_PHY_CFG_RADIO_TYPE_POS,
633 IWM_FW_PHY_CFG_RADIO_STEP_POS = 2,
634 IWM_FW_PHY_CFG_RADIO_STEP = 0x3 << IWM_FW_PHY_CFG_RADIO_STEP_POS,
635 IWM_FW_PHY_CFG_RADIO_DASH_POS = 4,
636 IWM_FW_PHY_CFG_RADIO_DASH = 0x3 << IWM_FW_PHY_CFG_RADIO_DASH_POS,
637 IWM_FW_PHY_CFG_TX_CHAIN_POS = 16,
638 IWM_FW_PHY_CFG_TX_CHAIN = 0xf << IWM_FW_PHY_CFG_TX_CHAIN_POS,
639 IWM_FW_PHY_CFG_RX_CHAIN_POS = 20,
640 IWM_FW_PHY_CFG_RX_CHAIN = 0xf << IWM_FW_PHY_CFG_RX_CHAIN_POS,
643 #define IWM_UCODE_MAX_CS 1
646 * struct iwm_fw_cipher_scheme - a cipher scheme supported by FW.
647 * @cipher: a cipher suite selector
648 * @flags: cipher scheme flags (currently reserved for a future use)
649 * @hdr_len: a size of MPDU security header
650 * @pn_len: a size of PN
651 * @pn_off: an offset of pn from the beginning of the security header
652 * @key_idx_off: an offset of key index byte in the security header
653 * @key_idx_mask: a bit mask of key_idx bits
654 * @key_idx_shift: bit shift needed to get key_idx
655 * @mic_len: mic length in bytes
656 * @hw_cipher: a HW cipher index used in host commands
658 struct iwm_fw_cipher_scheme {
665 uint8_t key_idx_mask;
666 uint8_t key_idx_shift;
672 * struct iwm_fw_cscheme_list - a cipher scheme list
673 * @size: a number of entries
674 * @cs: cipher scheme entries
676 struct iwm_fw_cscheme_list {
678 struct iwm_fw_cipher_scheme cs[];
681 /* v1/v2 uCode file layout */
682 struct iwm_ucode_header {
683 uint32_t ver; /* major/minor/API/serial */
686 uint32_t inst_size; /* bytes of runtime code */
687 uint32_t data_size; /* bytes of runtime data */
688 uint32_t init_size; /* bytes of init code */
689 uint32_t init_data_size; /* bytes of init data */
690 uint32_t boot_size; /* bytes of bootstrap code */
691 uint8_t data[0]; /* in same order as sizes */
694 uint32_t build; /* build number */
695 uint32_t inst_size; /* bytes of runtime code */
696 uint32_t data_size; /* bytes of runtime data */
697 uint32_t init_size; /* bytes of init code */
698 uint32_t init_data_size; /* bytes of init data */
699 uint32_t boot_size; /* bytes of bootstrap code */
700 uint8_t data[0]; /* in same order as sizes */
706 * new TLV uCode file layout
708 * The new TLV file format contains TLVs, that each specify
709 * some piece of data.
712 enum iwm_ucode_tlv_type {
713 IWM_UCODE_TLV_INVALID = 0, /* unused */
714 IWM_UCODE_TLV_INST = 1,
715 IWM_UCODE_TLV_DATA = 2,
716 IWM_UCODE_TLV_INIT = 3,
717 IWM_UCODE_TLV_INIT_DATA = 4,
718 IWM_UCODE_TLV_BOOT = 5,
719 IWM_UCODE_TLV_PROBE_MAX_LEN = 6, /* a uint32_t value */
720 IWM_UCODE_TLV_PAN = 7,
721 IWM_UCODE_TLV_RUNT_EVTLOG_PTR = 8,
722 IWM_UCODE_TLV_RUNT_EVTLOG_SIZE = 9,
723 IWM_UCODE_TLV_RUNT_ERRLOG_PTR = 10,
724 IWM_UCODE_TLV_INIT_EVTLOG_PTR = 11,
725 IWM_UCODE_TLV_INIT_EVTLOG_SIZE = 12,
726 IWM_UCODE_TLV_INIT_ERRLOG_PTR = 13,
727 IWM_UCODE_TLV_ENHANCE_SENS_TBL = 14,
728 IWM_UCODE_TLV_PHY_CALIBRATION_SIZE = 15,
729 IWM_UCODE_TLV_WOWLAN_INST = 16,
730 IWM_UCODE_TLV_WOWLAN_DATA = 17,
731 IWM_UCODE_TLV_FLAGS = 18,
732 IWM_UCODE_TLV_SEC_RT = 19,
733 IWM_UCODE_TLV_SEC_INIT = 20,
734 IWM_UCODE_TLV_SEC_WOWLAN = 21,
735 IWM_UCODE_TLV_DEF_CALIB = 22,
736 IWM_UCODE_TLV_PHY_SKU = 23,
737 IWM_UCODE_TLV_SECURE_SEC_RT = 24,
738 IWM_UCODE_TLV_SECURE_SEC_INIT = 25,
739 IWM_UCODE_TLV_SECURE_SEC_WOWLAN = 26,
740 IWM_UCODE_TLV_NUM_OF_CPU = 27,
741 IWM_UCODE_TLV_CSCHEME = 28,
744 * Following two are not in our base tag, but allow
745 * handling ucode version 9.
747 IWM_UCODE_TLV_API_CHANGES_SET = 29,
748 IWM_UCODE_TLV_ENABLED_CAPABILITIES = 30
751 struct iwm_ucode_tlv {
752 uint32_t type; /* see above */
753 uint32_t length; /* not including type/length fields */
757 #define IWM_TLV_UCODE_MAGIC 0x0a4c5749
759 struct iwm_tlv_ucode_header {
761 * The TLV style ucode header is distinguished from
762 * the v1/v2 style header by first four bytes being
763 * zero, as such is an invalid combination of
764 * major/minor/API/serial versions.
768 uint8_t human_readable[64];
769 uint32_t ver; /* major/minor/API/serial */
773 * The data contained herein has a TLV layout,
774 * see above for the TLV header and types.
775 * Note that each TLV is padded to a length
776 * that is a multiple of 4 for alignment.
782 * Registers in this file are internal, not PCI bus memory mapped.
783 * Driver accesses these via IWM_HBUS_TARG_PRPH_* registers.
785 #define IWM_PRPH_BASE (0x00000)
786 #define IWM_PRPH_END (0xFFFFF)
788 /* APMG (power management) constants */
789 #define IWM_APMG_BASE (IWM_PRPH_BASE + 0x3000)
790 #define IWM_APMG_CLK_CTRL_REG (IWM_APMG_BASE + 0x0000)
791 #define IWM_APMG_CLK_EN_REG (IWM_APMG_BASE + 0x0004)
792 #define IWM_APMG_CLK_DIS_REG (IWM_APMG_BASE + 0x0008)
793 #define IWM_APMG_PS_CTRL_REG (IWM_APMG_BASE + 0x000c)
794 #define IWM_APMG_PCIDEV_STT_REG (IWM_APMG_BASE + 0x0010)
795 #define IWM_APMG_RFKILL_REG (IWM_APMG_BASE + 0x0014)
796 #define IWM_APMG_RTC_INT_STT_REG (IWM_APMG_BASE + 0x001c)
797 #define IWM_APMG_RTC_INT_MSK_REG (IWM_APMG_BASE + 0x0020)
798 #define IWM_APMG_DIGITAL_SVR_REG (IWM_APMG_BASE + 0x0058)
799 #define IWM_APMG_ANALOG_SVR_REG (IWM_APMG_BASE + 0x006C)
801 #define IWM_APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001)
802 #define IWM_APMG_CLK_VAL_DMA_CLK_RQT (0x00000200)
803 #define IWM_APMG_CLK_VAL_BSM_CLK_RQT (0x00000800)
805 #define IWM_APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000)
806 #define IWM_APMG_PS_CTRL_VAL_RESET_REQ (0x04000000)
807 #define IWM_APMG_PS_CTRL_MSK_PWR_SRC (0x03000000)
808 #define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000)
809 #define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000)
810 #define IWM_APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */
811 #define IWM_APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060)
813 #define IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800)
815 #define IWM_APMG_RTC_INT_STT_RFKILL (0x10000000)
817 /* Device system time */
818 #define IWM_DEVICE_SYSTEM_TIME_REG 0xA0206C
820 /* Device NMI register */
821 #define IWM_DEVICE_SET_NMI_REG 0x00a01c30
823 /*****************************************************************************
824 * 7000/3000 series SHR DTS addresses *
825 *****************************************************************************/
827 #define IWM_SHR_MISC_WFM_DTS_EN (0x00a10024)
828 #define IWM_DTSC_CFG_MODE (0x00a10604)
829 #define IWM_DTSC_VREF_AVG (0x00a10648)
830 #define IWM_DTSC_VREF5_AVG (0x00a1064c)
831 #define IWM_DTSC_CFG_MODE_PERIODIC (0x2)
832 #define IWM_DTSC_PTAT_AVG (0x00a10650)
838 * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs
839 * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in
840 * host DRAM. It steers each frame's Tx command (which contains the frame
841 * data) into one of up to 7 prioritized Tx DMA FIFO channels within the
842 * device. A queue maps to only one (selectable by driver) Tx DMA channel,
843 * but one DMA channel may take input from several queues.
845 * Tx DMA FIFOs have dedicated purposes.
847 * For 5000 series and up, they are used differently
848 * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c):
850 * 0 -- EDCA BK (background) frames, lowest priority
851 * 1 -- EDCA BE (best effort) frames, normal priority
852 * 2 -- EDCA VI (video) frames, higher priority
853 * 3 -- EDCA VO (voice) and management frames, highest priority
859 * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6.
860 * In addition, driver can map the remaining queues to Tx DMA/FIFO
861 * channels 0-3 to support 11n aggregation via EDCA DMA channels.
863 * The driver sets up each queue to work in one of two modes:
865 * 1) Scheduler-Ack, in which the scheduler automatically supports a
866 * block-ack (BA) window of up to 64 TFDs. In this mode, each queue
867 * contains TFDs for a unique combination of Recipient Address (RA)
868 * and Traffic Identifier (TID), that is, traffic of a given
869 * Quality-Of-Service (QOS) priority, destined for a single station.
871 * In scheduler-ack mode, the scheduler keeps track of the Tx status of
872 * each frame within the BA window, including whether it's been transmitted,
873 * and whether it's been acknowledged by the receiving station. The device
874 * automatically processes block-acks received from the receiving STA,
875 * and reschedules un-acked frames to be retransmitted (successful
876 * Tx completion may end up being out-of-order).
878 * The driver must maintain the queue's Byte Count table in host DRAM
880 * This mode does not support fragmentation.
882 * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order.
883 * The device may automatically retry Tx, but will retry only one frame
884 * at a time, until receiving ACK from receiving station, or reaching
885 * retry limit and giving up.
887 * The command queue (#4/#9) must use this mode!
888 * This mode does not require use of the Byte Count table in host DRAM.
890 * Driver controls scheduler operation via 3 means:
891 * 1) Scheduler registers
892 * 2) Shared scheduler data base in internal SRAM
893 * 3) Shared data in host DRAM
897 * When loading, driver should allocate memory for:
898 * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs.
899 * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory
900 * (1024 bytes for each queue).
902 * After receiving "Alive" response from uCode, driver must initialize
903 * the scheduler (especially for queue #4/#9, the command queue, otherwise
904 * the driver can't issue commands!):
906 #define IWM_SCD_MEM_LOWER_BOUND (0x0000)
909 * Max Tx window size is the max number of contiguous TFDs that the scheduler
910 * can keep track of at one time when creating block-ack chains of frames.
911 * Note that "64" matches the number of ack bits in a block-ack packet.
913 #define IWM_SCD_WIN_SIZE 64
914 #define IWM_SCD_FRAME_LIMIT 64
916 #define IWM_SCD_TXFIFO_POS_TID (0)
917 #define IWM_SCD_TXFIFO_POS_RA (4)
918 #define IWM_SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF)
921 #define IWM_SCD_QUEUE_STTS_REG_POS_TXF (0)
922 #define IWM_SCD_QUEUE_STTS_REG_POS_ACTIVE (3)
923 #define IWM_SCD_QUEUE_STTS_REG_POS_WSL (4)
924 #define IWM_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19)
925 #define IWM_SCD_QUEUE_STTS_REG_MSK (0x017F0000)
927 #define IWM_SCD_QUEUE_CTX_REG1_CREDIT_POS (8)
928 #define IWM_SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00)
929 #define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24)
930 #define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000)
931 #define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0)
932 #define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F)
933 #define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16)
934 #define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000)
937 #define IWM_SCD_CONTEXT_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x600)
938 #define IWM_SCD_CONTEXT_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0)
941 #define IWM_SCD_TX_STTS_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0)
942 #define IWM_SCD_TX_STTS_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0)
944 /* Translation Data */
945 #define IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0)
946 #define IWM_SCD_TRANS_TBL_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x808)
948 #define IWM_SCD_CONTEXT_QUEUE_OFFSET(x)\
949 (IWM_SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8))
951 #define IWM_SCD_TX_STTS_QUEUE_OFFSET(x)\
952 (IWM_SCD_TX_STTS_MEM_LOWER_BOUND + ((x) * 16))
954 #define IWM_SCD_TRANS_TBL_OFFSET_QUEUE(x) \
955 ((IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc)
957 #define IWM_SCD_BASE (IWM_PRPH_BASE + 0xa02c00)
959 #define IWM_SCD_SRAM_BASE_ADDR (IWM_SCD_BASE + 0x0)
960 #define IWM_SCD_DRAM_BASE_ADDR (IWM_SCD_BASE + 0x8)
961 #define IWM_SCD_AIT (IWM_SCD_BASE + 0x0c)
962 #define IWM_SCD_TXFACT (IWM_SCD_BASE + 0x10)
963 #define IWM_SCD_ACTIVE (IWM_SCD_BASE + 0x14)
964 #define IWM_SCD_QUEUECHAIN_SEL (IWM_SCD_BASE + 0xe8)
965 #define IWM_SCD_CHAINEXT_EN (IWM_SCD_BASE + 0x244)
966 #define IWM_SCD_AGGR_SEL (IWM_SCD_BASE + 0x248)
967 #define IWM_SCD_INTERRUPT_MASK (IWM_SCD_BASE + 0x108)
969 static inline unsigned int IWM_SCD_QUEUE_WRPTR(unsigned int chnl)
972 return IWM_SCD_BASE + 0x18 + chnl * 4;
973 return IWM_SCD_BASE + 0x284 + (chnl - 20) * 4;
976 static inline unsigned int IWM_SCD_QUEUE_RDPTR(unsigned int chnl)
979 return IWM_SCD_BASE + 0x68 + chnl * 4;
980 return IWM_SCD_BASE + 0x2B4 + (chnl - 20) * 4;
983 static inline unsigned int IWM_SCD_QUEUE_STATUS_BITS(unsigned int chnl)
986 return IWM_SCD_BASE + 0x10c + chnl * 4;
987 return IWM_SCD_BASE + 0x384 + (chnl - 20) * 4;
990 /*********************** END TX SCHEDULER *************************************/
992 /* Oscillator clock */
993 #define IWM_OSC_CLK (0xa04068)
994 #define IWM_OSC_CLK_FORCE_CONTROL (0x8)
996 /****************************/
997 /* Flow Handler Definitions */
998 /****************************/
1001 * This I/O area is directly read/writable by driver (e.g. Linux uses writel())
1002 * Addresses are offsets from device's PCI hardware base address.
1004 #define IWM_FH_MEM_LOWER_BOUND (0x1000)
1005 #define IWM_FH_MEM_UPPER_BOUND (0x2000)
1008 * Keep-Warm (KW) buffer base address.
1010 * Driver must allocate a 4KByte buffer that is for keeping the
1011 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency
1012 * DRAM access when doing Txing or Rxing. The dummy accesses prevent host
1013 * from going into a power-savings mode that would cause higher DRAM latency,
1014 * and possible data over/under-runs, before all Tx/Rx is complete.
1016 * Driver loads IWM_FH_KW_MEM_ADDR_REG with the physical address (bits 35:4)
1017 * of the buffer, which must be 4K aligned. Once this is set up, the device
1018 * automatically invokes keep-warm accesses when normal accesses might not
1019 * be sufficient to maintain fast DRAM response.
1022 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned
1024 #define IWM_FH_KW_MEM_ADDR_REG (IWM_FH_MEM_LOWER_BOUND + 0x97C)
1028 * TFD Circular Buffers Base (CBBC) addresses
1030 * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident
1031 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs)
1032 * (see struct iwm_tfd_frame). These 16 pointer registers are offset by 0x04
1033 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte
1034 * aligned (address bits 0-7 must be 0).
1035 * Later devices have 20 (5000 series) or 30 (higher) queues, but the registers
1036 * for them are in different places.
1038 * Bit fields in each pointer register:
1039 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned
1041 #define IWM_FH_MEM_CBBC_0_15_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0)
1042 #define IWM_FH_MEM_CBBC_0_15_UPPER_BOUN (IWM_FH_MEM_LOWER_BOUND + 0xA10)
1043 #define IWM_FH_MEM_CBBC_16_19_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBF0)
1044 #define IWM_FH_MEM_CBBC_16_19_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00)
1045 #define IWM_FH_MEM_CBBC_20_31_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB20)
1046 #define IWM_FH_MEM_CBBC_20_31_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB80)
1048 /* Find TFD CB base pointer for given queue */
1049 static inline unsigned int IWM_FH_MEM_CBBC_QUEUE(unsigned int chnl)
1052 return IWM_FH_MEM_CBBC_0_15_LOWER_BOUND + 4 * chnl;
1054 return IWM_FH_MEM_CBBC_16_19_LOWER_BOUND + 4 * (chnl - 16);
1055 return IWM_FH_MEM_CBBC_20_31_LOWER_BOUND + 4 * (chnl - 20);
1060 * Rx SRAM Control and Status Registers (RSCSR)
1062 * These registers provide handshake between driver and device for the Rx queue
1063 * (this queue handles *all* command responses, notifications, Rx data, etc.
1064 * sent from uCode to host driver). Unlike Tx, there is only one Rx
1065 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can
1066 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer
1067 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1
1068 * mapping between RBDs and RBs.
1070 * Driver must allocate host DRAM memory for the following, and set the
1071 * physical address of each into device registers:
1073 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256
1074 * entries (although any power of 2, up to 4096, is selectable by driver).
1075 * Each entry (1 dword) points to a receive buffer (RB) of consistent size
1076 * (typically 4K, although 8K or 16K are also selectable by driver).
1077 * Driver sets up RB size and number of RBDs in the CB via Rx config
1078 * register IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG.
1080 * Bit fields within one RBD:
1081 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned
1083 * Driver sets physical address [35:8] of base of RBD circular buffer
1084 * into IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0].
1086 * 2) Rx status buffer, 8 bytes, in which uCode indicates which Rx Buffers
1087 * (RBs) have been filled, via a "write pointer", actually the index of
1088 * the RB's corresponding RBD within the circular buffer. Driver sets
1089 * physical address [35:4] into IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0].
1091 * Bit fields in lower dword of Rx status buffer (upper dword not used
1093 * 31-12: Not used by driver
1094 * 11- 0: Index of last filled Rx buffer descriptor
1095 * (device writes, driver reads this value)
1097 * As the driver prepares Receive Buffers (RBs) for device to fill, driver must
1098 * enter pointers to these RBs into contiguous RBD circular buffer entries,
1099 * and update the device's "write" index register,
1100 * IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG.
1102 * This "write" index corresponds to the *next* RBD that the driver will make
1103 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within
1104 * the circular buffer. This value should initially be 0 (before preparing any
1105 * RBs), should be 8 after preparing the first 8 RBs (for example), and must
1106 * wrap back to 0 at the end of the circular buffer (but don't wrap before
1107 * "read" index has advanced past 1! See below).
1108 * NOTE: DEVICE EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8.
1110 * As the device fills RBs (referenced from contiguous RBDs within the circular
1111 * buffer), it updates the Rx status buffer in host DRAM, 2) described above,
1112 * to tell the driver the index of the latest filled RBD. The driver must
1113 * read this "read" index from DRAM after receiving an Rx interrupt from device
1115 * The driver must also internally keep track of a third index, which is the
1116 * next RBD to process. When receiving an Rx interrupt, driver should process
1117 * all filled but unprocessed RBs up to, but not including, the RB
1118 * corresponding to the "read" index. For example, if "read" index becomes "1",
1119 * driver may process the RB pointed to by RBD 0. Depending on volume of
1120 * traffic, there may be many RBs to process.
1122 * If read index == write index, device thinks there is no room to put new data.
1123 * Due to this, the maximum number of filled RBs is 255, instead of 256. To
1124 * be safe, make sure that there is a gap of at least 2 RBDs between "write"
1125 * and "read" indexes; that is, make sure that there are no more than 254
1126 * buffers waiting to be filled.
1128 #define IWM_FH_MEM_RSCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBC0)
1129 #define IWM_FH_MEM_RSCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00)
1130 #define IWM_FH_MEM_RSCSR_CHNL0 (IWM_FH_MEM_RSCSR_LOWER_BOUND)
1133 * Physical base address of 8-byte Rx Status buffer.
1135 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned.
1137 #define IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0)
1140 * Physical base address of Rx Buffer Descriptor Circular Buffer.
1142 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned.
1144 #define IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x004)
1147 * Rx write pointer (index, really!).
1149 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1.
1150 * NOTE: For 256-entry circular buffer, use only bits [7:0].
1152 #define IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x008)
1153 #define IWM_FH_RSCSR_CHNL0_WPTR (IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG)
1155 #define IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x00c)
1156 #define IWM_FH_RSCSR_CHNL0_RDPTR IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG
1159 * Rx Config/Status Registers (RCSR)
1160 * Rx Config Reg for channel 0 (only channel used)
1162 * Driver must initialize IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for
1163 * normal operation (see bit fields).
1165 * Clearing IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA.
1166 * Driver should poll IWM_FH_MEM_RSSR_RX_STATUS_REG for
1167 * IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing.
1170 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame,
1171 * '10' operate normally
1173 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal),
1174 * min "5" for 32 RBDs, max "12" for 4096 RBDs.
1176 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K,
1177 * '10' 12K, '11' 16K.
1179 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation)
1180 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec)
1181 * typical value 0x10 (about 1/2 msec)
1184 #define IWM_FH_MEM_RCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00)
1185 #define IWM_FH_MEM_RCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xCC0)
1186 #define IWM_FH_MEM_RCSR_CHNL0 (IWM_FH_MEM_RCSR_LOWER_BOUND)
1188 #define IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG (IWM_FH_MEM_RCSR_CHNL0)
1189 #define IWM_FH_MEM_RCSR_CHNL0_RBDCB_WPTR (IWM_FH_MEM_RCSR_CHNL0 + 0x8)
1190 #define IWM_FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ (IWM_FH_MEM_RCSR_CHNL0 + 0x10)
1192 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */
1193 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */
1194 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */
1195 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */
1196 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */
1197 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/
1199 #define IWM_FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20)
1200 #define IWM_FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4)
1201 #define IWM_RX_RB_TIMEOUT (0x11)
1203 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000)
1204 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000)
1205 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000)
1207 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000)
1208 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000)
1209 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000)
1210 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000)
1212 #define IWM_FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004)
1213 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000)
1214 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000)
1217 * Rx Shared Status Registers (RSSR)
1219 * After stopping Rx DMA channel (writing 0 to
1220 * IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll
1221 * IWM_FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle.
1224 * 24: 1 = Channel 0 is idle
1226 * IWM_FH_MEM_RSSR_SHARED_CTRL_REG and IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV
1227 * contain default values that should not be altered by the driver.
1229 #define IWM_FH_MEM_RSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC40)
1230 #define IWM_FH_MEM_RSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00)
1232 #define IWM_FH_MEM_RSSR_SHARED_CTRL_REG (IWM_FH_MEM_RSSR_LOWER_BOUND)
1233 #define IWM_FH_MEM_RSSR_RX_STATUS_REG (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x004)
1234 #define IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\
1235 (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x008)
1237 #define IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000)
1239 #define IWM_FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28
1241 /* TFDB Area - TFDs buffer table */
1242 #define IWM_FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF)
1243 #define IWM_FH_TFDIB_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x900)
1244 #define IWM_FH_TFDIB_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x958)
1245 #define IWM_FH_TFDIB_CTRL0_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl))
1246 #define IWM_FH_TFDIB_CTRL1_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4)
1249 * Transmit DMA Channel Control/Status Registers (TCSR)
1251 * Device has one configuration register for each of 8 Tx DMA/FIFO channels
1252 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM,
1253 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes.
1255 * To use a Tx DMA channel, driver must initialize its
1256 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with:
1258 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1259 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL
1261 * All other bits should be 0.
1264 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame,
1265 * '10' operate normally
1266 * 29- 4: Reserved, set to "0"
1267 * 3: Enable internal DMA requests (1, normal operation), disable (0)
1268 * 2- 0: Reserved, set to "0"
1270 #define IWM_FH_TCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00)
1271 #define IWM_FH_TCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xE60)
1273 /* Find Control/Status reg for given Tx DMA/FIFO channel */
1274 #define IWM_FH_TCSR_CHNL_NUM (8)
1276 /* TCSR: tx_config register values */
1277 #define IWM_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \
1278 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl))
1279 #define IWM_FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \
1280 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4)
1281 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \
1282 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8)
1284 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)
1285 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001)
1287 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000)
1288 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008)
1290 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000)
1291 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000)
1292 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)
1294 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)
1295 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000)
1296 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000)
1298 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
1299 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000)
1300 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
1302 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000)
1303 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000)
1304 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003)
1306 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20)
1307 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12)
1310 * Tx Shared Status Registers (TSSR)
1312 * After stopping Tx DMA channel (writing 0 to
1313 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll
1314 * IWM_FH_TSSR_TX_STATUS_REG until selected Tx channel is idle
1315 * (channel's buffers empty | no pending requests).
1318 * 31-24: 1 = Channel buffers empty (channel 7:0)
1319 * 23-16: 1 = No pending requests (channel 7:0)
1321 #define IWM_FH_TSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEA0)
1322 #define IWM_FH_TSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEC0)
1324 #define IWM_FH_TSSR_TX_STATUS_REG (IWM_FH_TSSR_LOWER_BOUND + 0x010)
1327 * Bit fields for TSSR(Tx Shared Status & Control) error status register:
1328 * 31: Indicates an address error when accessed to internal memory
1329 * uCode/driver must write "1" in order to clear this flag
1330 * 30: Indicates that Host did not send the expected number of dwords to FH
1331 * uCode/driver must write "1" in order to clear this flag
1332 * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA
1333 * command was received from the scheduler while the TRB was already full
1334 * with previous command
1335 * uCode/driver must write "1" in order to clear this flag
1336 * 7-0: Each status bit indicates a channel's TxCredit error. When an error
1337 * bit is set, it indicates that the FH has received a full indication
1338 * from the RTC TxFIFO and the current value of the TxCredit counter was
1339 * not equal to zero. This mean that the credit mechanism was not
1340 * synchronized to the TxFIFO status
1341 * uCode/driver must write "1" in order to clear this flag
1343 #define IWM_FH_TSSR_TX_ERROR_REG (IWM_FH_TSSR_LOWER_BOUND + 0x018)
1344 #define IWM_FH_TSSR_TX_MSG_CONFIG_REG (IWM_FH_TSSR_LOWER_BOUND + 0x008)
1346 #define IWM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16)
1348 /* Tx service channels */
1349 #define IWM_FH_SRVC_CHNL (9)
1350 #define IWM_FH_SRVC_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9C8)
1351 #define IWM_FH_SRVC_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0)
1352 #define IWM_FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \
1353 (IWM_FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4)
1355 #define IWM_FH_TX_CHICKEN_BITS_REG (IWM_FH_MEM_LOWER_BOUND + 0xE98)
1356 #define IWM_FH_TX_TRB_REG(_chan) (IWM_FH_MEM_LOWER_BOUND + 0x958 + \
1359 /* Instruct FH to increment the retry count of a packet when
1360 * it is brought from the memory to TX-FIFO
1362 #define IWM_FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002)
1364 #define IWM_RX_QUEUE_SIZE 256
1365 #define IWM_RX_QUEUE_MASK 255
1366 #define IWM_RX_QUEUE_SIZE_LOG 8
1369 * RX related structures and functions
1371 #define IWM_RX_FREE_BUFFERS 64
1372 #define IWM_RX_LOW_WATERMARK 8
1375 * struct iwm_rb_status - reseve buffer status
1376 * host memory mapped FH registers
1377 * @closed_rb_num [0:11] - Indicates the index of the RB which was closed
1378 * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed
1379 * @finished_rb_num [0:11] - Indicates the index of the current RB
1380 * in which the last frame was written to
1381 * @finished_fr_num [0:11] - Indicates the index of the RX Frame
1382 * which was transferred
1384 struct iwm_rb_status {
1385 uint16_t closed_rb_num;
1386 uint16_t closed_fr_num;
1387 uint16_t finished_rb_num;
1388 uint16_t finished_fr_nam;
1393 #define IWM_TFD_QUEUE_SIZE_MAX (256)
1394 #define IWM_TFD_QUEUE_SIZE_BC_DUP (64)
1395 #define IWM_TFD_QUEUE_BC_SIZE (IWM_TFD_QUEUE_SIZE_MAX + \
1396 IWM_TFD_QUEUE_SIZE_BC_DUP)
1397 #define IWM_TX_DMA_MASK DMA_BIT_MASK(36)
1398 #define IWM_NUM_OF_TBS 20
1400 static inline uint8_t iwm_get_dma_hi_addr(bus_addr_t addr)
1402 return (sizeof(addr) > sizeof(uint32_t) ? (addr >> 16) >> 16 : 0) & 0xF;
1405 * struct iwm_tfd_tb transmit buffer descriptor within transmit frame descriptor
1407 * This structure contains dma address and length of transmission address
1409 * @lo: low [31:0] portion of the dma address of TX buffer
1410 * every even is unaligned on 16 bit boundary
1411 * @hi_n_len 0-3 [35:32] portion of dma
1412 * 4-15 length of the tx buffer
1422 * Transmit Frame Descriptor (TFD)
1424 * @ __reserved1[3] reserved
1425 * @ num_tbs 0-4 number of active tbs
1427 * 6-7 padding (not used)
1428 * @ tbs[20] transmit frame buffer descriptors
1431 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM.
1432 * Both driver and device share these circular buffers, each of which must be
1433 * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes
1435 * Driver must indicate the physical address of the base of each
1436 * circular buffer via the IWM_FH_MEM_CBBC_QUEUE registers.
1438 * Each TFD contains pointer/size information for up to 20 data buffers
1439 * in host DRAM. These buffers collectively contain the (one) frame described
1440 * by the TFD. Each buffer must be a single contiguous block of memory within
1441 * itself, but buffers may be scattered in host DRAM. Each buffer has max size
1442 * of (4K - 4). The concatenates all of a TFD's buffers into a single
1443 * Tx frame, up to 8 KBytes in size.
1445 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx.
1448 uint8_t __reserved1[3];
1450 struct iwm_tfd_tb tbs[IWM_NUM_OF_TBS];
1454 /* Keep Warm Size */
1455 #define IWM_KW_SIZE 0x1000 /* 4k */
1457 /* Fixed (non-configurable) rx data from phy */
1460 * struct iwm_agn_schedq_bc_tbl scheduler byte count table
1461 * base physical address provided by IWM_SCD_DRAM_BASE_ADDR
1462 * @tfd_offset 0-12 - tx command byte count
1463 * 12-16 - station index
1465 struct iwm_agn_scd_bc_tbl {
1466 uint16_t tfd_offset[IWM_TFD_QUEUE_BC_SIZE];
1469 /* maximal number of Tx queues in any platform */
1470 #define IWM_MVM_MAX_QUEUES 20
1472 /* Tx queue numbers */
1474 IWM_MVM_OFFCHANNEL_QUEUE = 8,
1475 IWM_MVM_CMD_QUEUE = 9,
1478 #define IWM_MVM_CMD_FIFO 7
1480 #define IWM_MVM_STATION_COUNT 16
1484 IWM_MVM_ALIVE = 0x1,
1485 IWM_REPLY_ERROR = 0x2,
1487 IWM_INIT_COMPLETE_NOTIF = 0x4,
1489 /* PHY context commands */
1490 IWM_PHY_CONTEXT_CMD = 0x8,
1494 IWM_ADD_STA_KEY = 0x17,
1496 IWM_REMOVE_STA = 0x19,
1500 IWM_TXPATH_FLUSH = 0x1e,
1501 IWM_MGMT_MCAST_KEY = 0x1f,
1506 /* MAC and Binding commands */
1507 IWM_MAC_CONTEXT_CMD = 0x28,
1508 IWM_TIME_EVENT_CMD = 0x29, /* both CMD and response */
1509 IWM_TIME_EVENT_NOTIFICATION = 0x2a,
1510 IWM_BINDING_CONTEXT_CMD = 0x2b,
1511 IWM_TIME_QUOTA_CMD = 0x2c,
1512 IWM_NON_QOS_TX_COUNTER_CMD = 0x2d,
1517 IWM_TEMPERATURE_NOTIFICATION = 0x62,
1518 IWM_CALIBRATION_CFG_CMD = 0x65,
1519 IWM_CALIBRATION_RES_NOTIFICATION = 0x66,
1520 IWM_CALIBRATION_COMPLETE_NOTIFICATION = 0x67,
1521 IWM_RADIO_VERSION_NOTIFICATION = 0x68,
1524 IWM_SCAN_OFFLOAD_REQUEST_CMD = 0x51,
1525 IWM_SCAN_OFFLOAD_ABORT_CMD = 0x52,
1526 IWM_SCAN_OFFLOAD_COMPLETE = 0x6D,
1527 IWM_SCAN_OFFLOAD_UPDATE_PROFILES_CMD = 0x6E,
1528 IWM_SCAN_OFFLOAD_CONFIG_CMD = 0x6f,
1529 IWM_MATCH_FOUND_NOTIFICATION = 0xd9,
1532 IWM_PHY_CONFIGURATION_CMD = 0x6a,
1533 IWM_CALIB_RES_NOTIF_PHY_DB = 0x6b,
1534 /* IWM_PHY_DB_CMD = 0x6c, */
1536 /* Power - legacy power table command */
1537 IWM_POWER_TABLE_CMD = 0x77,
1538 IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78,
1540 /* Thermal Throttling*/
1541 IWM_REPLY_THERMAL_MNG_BACKOFF = 0x7e,
1544 IWM_SCAN_REQUEST_CMD = 0x80,
1545 IWM_SCAN_ABORT_CMD = 0x81,
1546 IWM_SCAN_START_NOTIFICATION = 0x82,
1547 IWM_SCAN_RESULTS_NOTIFICATION = 0x83,
1548 IWM_SCAN_COMPLETE_NOTIFICATION = 0x84,
1551 IWM_NVM_ACCESS_CMD = 0x88,
1553 IWM_SET_CALIB_DEFAULT_CMD = 0x8e,
1555 IWM_BEACON_NOTIFICATION = 0x90,
1556 IWM_BEACON_TEMPLATE_CMD = 0x91,
1557 IWM_TX_ANT_CONFIGURATION_CMD = 0x98,
1558 IWM_BT_CONFIG = 0x9b,
1559 IWM_STATISTICS_NOTIFICATION = 0x9d,
1560 IWM_REDUCE_TX_POWER_CMD = 0x9f,
1562 /* RF-KILL commands and notifications */
1563 IWM_CARD_STATE_CMD = 0xa0,
1564 IWM_CARD_STATE_NOTIFICATION = 0xa1,
1566 IWM_MISSED_BEACONS_NOTIFICATION = 0xa2,
1568 /* Power - new power table command */
1569 IWM_MAC_PM_POWER_TABLE = 0xa9,
1571 IWM_REPLY_RX_PHY_CMD = 0xc0,
1572 IWM_REPLY_RX_MPDU_CMD = 0xc1,
1573 IWM_BA_NOTIF = 0xc5,
1576 IWM_BT_COEX_PRIO_TABLE = 0xcc,
1577 IWM_BT_COEX_PROT_ENV = 0xcd,
1578 IWM_BT_PROFILE_NOTIFICATION = 0xce,
1579 IWM_BT_COEX_CI = 0x5d,
1581 IWM_REPLY_SF_CFG_CMD = 0xd1,
1582 IWM_REPLY_BEACON_FILTERING_CMD = 0xd2,
1584 IWM_REPLY_DEBUG_CMD = 0xf0,
1585 IWM_DEBUG_LOG_MSG = 0xf7,
1587 IWM_MCAST_FILTER_CMD = 0xd0,
1589 /* D3 commands/notifications */
1590 IWM_D3_CONFIG_CMD = 0xd3,
1591 IWM_PROT_OFFLOAD_CONFIG_CMD = 0xd4,
1592 IWM_OFFLOADS_QUERY_CMD = 0xd5,
1593 IWM_REMOTE_WAKE_CONFIG_CMD = 0xd6,
1595 /* for WoWLAN in particular */
1596 IWM_WOWLAN_PATTERNS = 0xe0,
1597 IWM_WOWLAN_CONFIGURATION = 0xe1,
1598 IWM_WOWLAN_TSC_RSC_PARAM = 0xe2,
1599 IWM_WOWLAN_TKIP_PARAM = 0xe3,
1600 IWM_WOWLAN_KEK_KCK_MATERIAL = 0xe4,
1601 IWM_WOWLAN_GET_STATUSES = 0xe5,
1602 IWM_WOWLAN_TX_POWER_PER_DB = 0xe6,
1604 /* and for NetDetect */
1605 IWM_NET_DETECT_CONFIG_CMD = 0x54,
1606 IWM_NET_DETECT_PROFILES_QUERY_CMD = 0x56,
1607 IWM_NET_DETECT_PROFILES_CMD = 0x57,
1608 IWM_NET_DETECT_HOTSPOTS_CMD = 0x58,
1609 IWM_NET_DETECT_HOTSPOTS_QUERY_CMD = 0x59,
1611 IWM_REPLY_MAX = 0xff,
1615 * struct iwm_cmd_response - generic response struct for most commands
1616 * @status: status of the command asked, changes for each one
1618 struct iwm_cmd_response {
1623 * struct iwm_tx_ant_cfg_cmd
1624 * @valid: valid antenna configuration
1626 struct iwm_tx_ant_cfg_cmd {
1631 * struct iwm_reduce_tx_power_cmd - TX power reduction command
1632 * IWM_REDUCE_TX_POWER_CMD = 0x9f
1633 * @flags: (reserved for future implementation)
1634 * @mac_context_id: id of the mac ctx for which we are reducing TX power.
1635 * @pwr_restriction: TX power restriction in dBms.
1637 struct iwm_reduce_tx_power_cmd {
1639 uint8_t mac_context_id;
1640 uint16_t pwr_restriction;
1641 } __packed; /* IWM_TX_REDUCED_POWER_API_S_VER_1 */
1644 * Calibration control struct.
1645 * Sent as part of the phy configuration command.
1646 * @flow_trigger: bitmap for which calibrations to perform according to
1648 * @event_trigger: bitmap for which calibrations to perform according to
1651 struct iwm_calib_ctrl {
1652 uint32_t flow_trigger;
1653 uint32_t event_trigger;
1656 /* This enum defines the bitmap of various calibrations to enable in both
1657 * init ucode and runtime ucode through IWM_CALIBRATION_CFG_CMD.
1659 enum iwm_calib_cfg {
1660 IWM_CALIB_CFG_XTAL_IDX = (1 << 0),
1661 IWM_CALIB_CFG_TEMPERATURE_IDX = (1 << 1),
1662 IWM_CALIB_CFG_VOLTAGE_READ_IDX = (1 << 2),
1663 IWM_CALIB_CFG_PAPD_IDX = (1 << 3),
1664 IWM_CALIB_CFG_TX_PWR_IDX = (1 << 4),
1665 IWM_CALIB_CFG_DC_IDX = (1 << 5),
1666 IWM_CALIB_CFG_BB_FILTER_IDX = (1 << 6),
1667 IWM_CALIB_CFG_LO_LEAKAGE_IDX = (1 << 7),
1668 IWM_CALIB_CFG_TX_IQ_IDX = (1 << 8),
1669 IWM_CALIB_CFG_TX_IQ_SKEW_IDX = (1 << 9),
1670 IWM_CALIB_CFG_RX_IQ_IDX = (1 << 10),
1671 IWM_CALIB_CFG_RX_IQ_SKEW_IDX = (1 << 11),
1672 IWM_CALIB_CFG_SENSITIVITY_IDX = (1 << 12),
1673 IWM_CALIB_CFG_CHAIN_NOISE_IDX = (1 << 13),
1674 IWM_CALIB_CFG_DISCONNECTED_ANT_IDX = (1 << 14),
1675 IWM_CALIB_CFG_ANT_COUPLING_IDX = (1 << 15),
1676 IWM_CALIB_CFG_DAC_IDX = (1 << 16),
1677 IWM_CALIB_CFG_ABS_IDX = (1 << 17),
1678 IWM_CALIB_CFG_AGC_IDX = (1 << 18),
1682 * Phy configuration command.
1684 struct iwm_phy_cfg_cmd {
1686 struct iwm_calib_ctrl calib_control;
1689 #define IWM_PHY_CFG_RADIO_TYPE ((1 << 0) | (1 << 1))
1690 #define IWM_PHY_CFG_RADIO_STEP ((1 << 2) | (1 << 3))
1691 #define IWM_PHY_CFG_RADIO_DASH ((1 << 4) | (1 << 5))
1692 #define IWM_PHY_CFG_PRODUCT_NUMBER ((1 << 6) | (1 << 7))
1693 #define IWM_PHY_CFG_TX_CHAIN_A (1 << 8)
1694 #define IWM_PHY_CFG_TX_CHAIN_B (1 << 9)
1695 #define IWM_PHY_CFG_TX_CHAIN_C (1 << 10)
1696 #define IWM_PHY_CFG_RX_CHAIN_A (1 << 12)
1697 #define IWM_PHY_CFG_RX_CHAIN_B (1 << 13)
1698 #define IWM_PHY_CFG_RX_CHAIN_C (1 << 14)
1701 /* Target of the IWM_NVM_ACCESS_CMD */
1703 IWM_NVM_ACCESS_TARGET_CACHE = 0,
1704 IWM_NVM_ACCESS_TARGET_OTP = 1,
1705 IWM_NVM_ACCESS_TARGET_EEPROM = 2,
1708 /* Section types for IWM_NVM_ACCESS_CMD */
1710 IWM_NVM_SECTION_TYPE_HW = 0,
1711 IWM_NVM_SECTION_TYPE_SW,
1712 IWM_NVM_SECTION_TYPE_PAPD,
1713 IWM_NVM_SECTION_TYPE_BT,
1714 IWM_NVM_SECTION_TYPE_CALIBRATION,
1715 IWM_NVM_SECTION_TYPE_PRODUCTION,
1716 IWM_NVM_SECTION_TYPE_POST_FCS_CALIB,
1717 IWM_NVM_NUM_OF_SECTIONS,
1721 * struct iwm_nvm_access_cmd_ver2 - Request the device to send an NVM section
1722 * @op_code: 0 - read, 1 - write
1723 * @target: IWM_NVM_ACCESS_TARGET_*
1724 * @type: IWM_NVM_SECTION_TYPE_*
1725 * @offset: offset in bytes into the section
1726 * @length: in bytes, to read/write
1727 * @data: if write operation, the data to write. On read its empty
1729 struct iwm_nvm_access_cmd {
1736 } __packed; /* IWM_NVM_ACCESS_CMD_API_S_VER_2 */
1739 * struct iwm_nvm_access_resp_ver2 - response to IWM_NVM_ACCESS_CMD
1740 * @offset: offset in bytes into the section
1741 * @length: in bytes, either how much was written or read
1742 * @type: IWM_NVM_SECTION_TYPE_*
1743 * @status: 0 for success, fail otherwise
1744 * @data: if read operation, the data returned. Empty on write.
1746 struct iwm_nvm_access_resp {
1752 } __packed; /* IWM_NVM_ACCESS_CMD_RESP_API_S_VER_2 */
1754 /* IWM_MVM_ALIVE 0x1 */
1756 /* alive response is_valid values */
1757 #define IWM_ALIVE_RESP_UCODE_OK (1 << 0)
1758 #define IWM_ALIVE_RESP_RFKILL (1 << 1)
1760 /* alive response ver_type values */
1763 IWM_FW_TYPE_PROT = 1,
1765 IWM_FW_TYPE_WOWLAN = 3,
1766 IWM_FW_TYPE_TIMING = 4,
1767 IWM_FW_TYPE_WIPAN = 5
1770 /* alive response ver_subtype values */
1772 IWM_FW_SUBTYPE_FULL_FEATURE = 0,
1773 IWM_FW_SUBTYPE_BOOTSRAP = 1, /* Not valid */
1774 IWM_FW_SUBTYPE_REDUCED = 2,
1775 IWM_FW_SUBTYPE_ALIVE_ONLY = 3,
1776 IWM_FW_SUBTYPE_WOWLAN = 4,
1777 IWM_FW_SUBTYPE_AP_SUBTYPE = 5,
1778 IWM_FW_SUBTYPE_WIPAN = 6,
1779 IWM_FW_SUBTYPE_INITIALIZE = 9
1782 #define IWM_ALIVE_STATUS_ERR 0xDEAD
1783 #define IWM_ALIVE_STATUS_OK 0xCAFE
1785 #define IWM_ALIVE_FLG_RFKILL (1 << 0)
1787 struct iwm_mvm_alive_resp {
1790 uint8_t ucode_minor;
1791 uint8_t ucode_major;
1795 uint8_t ver_subtype;
1801 uint32_t error_event_table_ptr; /* SRAM address for error log */
1802 uint32_t log_event_table_ptr; /* SRAM address for event log */
1803 uint32_t cpu_register_ptr;
1804 uint32_t dbgm_config_ptr;
1805 uint32_t alive_counter_ptr;
1806 uint32_t scd_base_ptr; /* SRAM address for SCD */
1807 } __packed; /* IWM_ALIVE_RES_API_S_VER_1 */
1809 /* Error response/notification */
1811 IWM_FW_ERR_UNKNOWN_CMD = 0x0,
1812 IWM_FW_ERR_INVALID_CMD_PARAM = 0x1,
1813 IWM_FW_ERR_SERVICE = 0x2,
1814 IWM_FW_ERR_ARC_MEMORY = 0x3,
1815 IWM_FW_ERR_ARC_CODE = 0x4,
1816 IWM_FW_ERR_WATCH_DOG = 0x5,
1817 IWM_FW_ERR_WEP_GRP_KEY_INDX = 0x10,
1818 IWM_FW_ERR_WEP_KEY_SIZE = 0x11,
1819 IWM_FW_ERR_OBSOLETE_FUNC = 0x12,
1820 IWM_FW_ERR_UNEXPECTED = 0xFE,
1821 IWM_FW_ERR_FATAL = 0xFF
1825 * struct iwm_error_resp - FW error indication
1826 * ( IWM_REPLY_ERROR = 0x2 )
1827 * @error_type: one of IWM_FW_ERR_*
1828 * @cmd_id: the command ID for which the error occured
1829 * @bad_cmd_seq_num: sequence number of the erroneous command
1830 * @error_service: which service created the error, applicable only if
1831 * error_type = 2, otherwise 0
1832 * @timestamp: TSF in usecs.
1834 struct iwm_error_resp {
1835 uint32_t error_type;
1838 uint16_t bad_cmd_seq_num;
1839 uint32_t error_service;
1844 /* Common PHY, MAC and Bindings definitions */
1846 #define IWM_MAX_MACS_IN_BINDING (3)
1847 #define IWM_MAX_BINDINGS (4)
1848 #define IWM_AUX_BINDING_INDEX (3)
1849 #define IWM_MAX_PHYS (4)
1851 /* Used to extract ID and color from the context dword */
1852 #define IWM_FW_CTXT_ID_POS (0)
1853 #define IWM_FW_CTXT_ID_MSK (0xff << IWM_FW_CTXT_ID_POS)
1854 #define IWM_FW_CTXT_COLOR_POS (8)
1855 #define IWM_FW_CTXT_COLOR_MSK (0xff << IWM_FW_CTXT_COLOR_POS)
1856 #define IWM_FW_CTXT_INVALID (0xffffffff)
1858 #define IWM_FW_CMD_ID_AND_COLOR(_id, _color) ((_id << IWM_FW_CTXT_ID_POS) |\
1859 (_color << IWM_FW_CTXT_COLOR_POS))
1861 /* Possible actions on PHYs, MACs and Bindings */
1863 IWM_FW_CTXT_ACTION_STUB = 0,
1864 IWM_FW_CTXT_ACTION_ADD,
1865 IWM_FW_CTXT_ACTION_MODIFY,
1866 IWM_FW_CTXT_ACTION_REMOVE,
1867 IWM_FW_CTXT_ACTION_NUM
1868 }; /* COMMON_CONTEXT_ACTION_API_E_VER_1 */
1872 /* Time Event types, according to MAC type */
1873 enum iwm_time_event_type {
1874 /* BSS Station Events */
1875 IWM_TE_BSS_STA_AGGRESSIVE_ASSOC,
1876 IWM_TE_BSS_STA_ASSOC,
1877 IWM_TE_BSS_EAP_DHCP_PROT,
1878 IWM_TE_BSS_QUIET_PERIOD,
1880 /* P2P Device Events */
1881 IWM_TE_P2P_DEVICE_DISCOVERABLE,
1882 IWM_TE_P2P_DEVICE_LISTEN,
1883 IWM_TE_P2P_DEVICE_ACTION_SCAN,
1884 IWM_TE_P2P_DEVICE_FULL_SCAN,
1886 /* P2P Client Events */
1887 IWM_TE_P2P_CLIENT_AGGRESSIVE_ASSOC,
1888 IWM_TE_P2P_CLIENT_ASSOC,
1889 IWM_TE_P2P_CLIENT_QUIET_PERIOD,
1892 IWM_TE_P2P_GO_ASSOC_PROT,
1893 IWM_TE_P2P_GO_REPETITIVE_NOA,
1894 IWM_TE_P2P_GO_CT_WINDOW,
1896 /* WiDi Sync Events */
1897 IWM_TE_WIDI_TX_SYNC,
1900 }; /* IWM_MAC_EVENT_TYPE_API_E_VER_1 */
1904 /* Time event - defines for command API v1 */
1907 * @IWM_TE_V1_FRAG_NONE: fragmentation of the time event is NOT allowed.
1908 * @IWM_TE_V1_FRAG_SINGLE: fragmentation of the time event is allowed, but only
1909 * the first fragment is scheduled.
1910 * @IWM_TE_V1_FRAG_DUAL: fragmentation of the time event is allowed, but only
1911 * the first 2 fragments are scheduled.
1912 * @IWM_TE_V1_FRAG_ENDLESS: fragmentation of the time event is allowed, and any
1913 * number of fragments are valid.
1915 * Other than the constant defined above, specifying a fragmentation value 'x'
1916 * means that the event can be fragmented but only the first 'x' will be
1920 IWM_TE_V1_FRAG_NONE = 0,
1921 IWM_TE_V1_FRAG_SINGLE = 1,
1922 IWM_TE_V1_FRAG_DUAL = 2,
1923 IWM_TE_V1_FRAG_ENDLESS = 0xffffffff
1926 /* If a Time Event can be fragmented, this is the max number of fragments */
1927 #define IWM_TE_V1_FRAG_MAX_MSK 0x0fffffff
1928 /* Repeat the time event endlessly (until removed) */
1929 #define IWM_TE_V1_REPEAT_ENDLESS 0xffffffff
1930 /* If a Time Event has bounded repetitions, this is the maximal value */
1931 #define IWM_TE_V1_REPEAT_MAX_MSK_V1 0x0fffffff
1933 /* Time Event dependencies: none, on another TE, or in a specific time */
1935 IWM_TE_V1_INDEPENDENT = 0,
1936 IWM_TE_V1_DEP_OTHER = (1 << 0),
1937 IWM_TE_V1_DEP_TSF = (1 << 1),
1938 IWM_TE_V1_EVENT_SOCIOPATHIC = (1 << 2),
1939 }; /* IWM_MAC_EVENT_DEPENDENCY_POLICY_API_E_VER_2 */
1942 * @IWM_TE_V1_NOTIF_NONE: no notifications
1943 * @IWM_TE_V1_NOTIF_HOST_EVENT_START: request/receive notification on event start
1944 * @IWM_TE_V1_NOTIF_HOST_EVENT_END:request/receive notification on event end
1945 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_START: internal FW use
1946 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_END: internal FW use.
1947 * @IWM_TE_V1_NOTIF_HOST_FRAG_START: request/receive notification on frag start
1948 * @IWM_TE_V1_NOTIF_HOST_FRAG_END:request/receive notification on frag end
1949 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_START: internal FW use.
1950 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_END: internal FW use.
1952 * Supported Time event notifications configuration.
1953 * A notification (both event and fragment) includes a status indicating weather
1954 * the FW was able to schedule the event or not. For fragment start/end
1955 * notification the status is always success. There is no start/end fragment
1956 * notification for monolithic events.
1959 IWM_TE_V1_NOTIF_NONE = 0,
1960 IWM_TE_V1_NOTIF_HOST_EVENT_START = (1 << 0),
1961 IWM_TE_V1_NOTIF_HOST_EVENT_END = (1 << 1),
1962 IWM_TE_V1_NOTIF_INTERNAL_EVENT_START = (1 << 2),
1963 IWM_TE_V1_NOTIF_INTERNAL_EVENT_END = (1 << 3),
1964 IWM_TE_V1_NOTIF_HOST_FRAG_START = (1 << 4),
1965 IWM_TE_V1_NOTIF_HOST_FRAG_END = (1 << 5),
1966 IWM_TE_V1_NOTIF_INTERNAL_FRAG_START = (1 << 6),
1967 IWM_TE_V1_NOTIF_INTERNAL_FRAG_END = (1 << 7),
1968 }; /* IWM_MAC_EVENT_ACTION_API_E_VER_2 */
1972 * struct iwm_time_event_cmd_api_v1 - configuring Time Events
1973 * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_1 (see also
1974 * with version 2. determined by IWM_UCODE_TLV_FLAGS)
1975 * ( IWM_TIME_EVENT_CMD = 0x29 )
1976 * @id_and_color: ID and color of the relevant MAC
1977 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
1978 * @id: this field has two meanings, depending on the action:
1979 * If the action is ADD, then it means the type of event to add.
1980 * For all other actions it is the unique event ID assigned when the
1981 * event was added by the FW.
1982 * @apply_time: When to start the Time Event (in GP2)
1983 * @max_delay: maximum delay to event's start (apply time), in TU
1984 * @depends_on: the unique ID of the event we depend on (if any)
1985 * @interval: interval between repetitions, in TU
1986 * @interval_reciprocal: 2^32 / interval
1987 * @duration: duration of event in TU
1988 * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS
1989 * @dep_policy: one of IWM_TE_V1_INDEPENDENT, IWM_TE_V1_DEP_OTHER, IWM_TE_V1_DEP_TSF
1990 * and IWM_TE_V1_EVENT_SOCIOPATHIC
1991 * @is_present: 0 or 1, are we present or absent during the Time Event
1992 * @max_frags: maximal number of fragments the Time Event can be divided to
1993 * @notify: notifications using IWM_TE_V1_NOTIF_* (whom to notify when)
1995 struct iwm_time_event_cmd_v1 {
1996 /* COMMON_INDEX_HDR_API_S_VER_1 */
1997 uint32_t id_and_color;
2000 /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_1 */
2001 uint32_t apply_time;
2003 uint32_t dep_policy;
2004 uint32_t depends_on;
2005 uint32_t is_present;
2008 uint32_t interval_reciprocal;
2012 } __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_1 */
2015 /* Time event - defines for command API v2 */
2018 * @IWM_TE_V2_FRAG_NONE: fragmentation of the time event is NOT allowed.
2019 * @IWM_TE_V2_FRAG_SINGLE: fragmentation of the time event is allowed, but only
2020 * the first fragment is scheduled.
2021 * @IWM_TE_V2_FRAG_DUAL: fragmentation of the time event is allowed, but only
2022 * the first 2 fragments are scheduled.
2023 * @IWM_TE_V2_FRAG_ENDLESS: fragmentation of the time event is allowed, and any
2024 * number of fragments are valid.
2026 * Other than the constant defined above, specifying a fragmentation value 'x'
2027 * means that the event can be fragmented but only the first 'x' will be
2031 IWM_TE_V2_FRAG_NONE = 0,
2032 IWM_TE_V2_FRAG_SINGLE = 1,
2033 IWM_TE_V2_FRAG_DUAL = 2,
2034 IWM_TE_V2_FRAG_MAX = 0xfe,
2035 IWM_TE_V2_FRAG_ENDLESS = 0xff
2038 /* Repeat the time event endlessly (until removed) */
2039 #define IWM_TE_V2_REPEAT_ENDLESS 0xff
2040 /* If a Time Event has bounded repetitions, this is the maximal value */
2041 #define IWM_TE_V2_REPEAT_MAX 0xfe
2043 #define IWM_TE_V2_PLACEMENT_POS 12
2044 #define IWM_TE_V2_ABSENCE_POS 15
2046 /* Time event policy values (for time event cmd api v2)
2047 * A notification (both event and fragment) includes a status indicating weather
2048 * the FW was able to schedule the event or not. For fragment start/end
2049 * notification the status is always success. There is no start/end fragment
2050 * notification for monolithic events.
2052 * @IWM_TE_V2_DEFAULT_POLICY: independent, social, present, unoticable
2053 * @IWM_TE_V2_NOTIF_HOST_EVENT_START: request/receive notification on event start
2054 * @IWM_TE_V2_NOTIF_HOST_EVENT_END:request/receive notification on event end
2055 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_START: internal FW use
2056 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_END: internal FW use.
2057 * @IWM_TE_V2_NOTIF_HOST_FRAG_START: request/receive notification on frag start
2058 * @IWM_TE_V2_NOTIF_HOST_FRAG_END:request/receive notification on frag end
2059 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_START: internal FW use.
2060 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_END: internal FW use.
2061 * @IWM_TE_V2_DEP_OTHER: depends on another time event
2062 * @IWM_TE_V2_DEP_TSF: depends on a specific time
2063 * @IWM_TE_V2_EVENT_SOCIOPATHIC: can't co-exist with other events of tha same MAC
2064 * @IWM_TE_V2_ABSENCE: are we present or absent during the Time Event.
2067 IWM_TE_V2_DEFAULT_POLICY = 0x0,
2069 /* notifications (event start/stop, fragment start/stop) */
2070 IWM_TE_V2_NOTIF_HOST_EVENT_START = (1 << 0),
2071 IWM_TE_V2_NOTIF_HOST_EVENT_END = (1 << 1),
2072 IWM_TE_V2_NOTIF_INTERNAL_EVENT_START = (1 << 2),
2073 IWM_TE_V2_NOTIF_INTERNAL_EVENT_END = (1 << 3),
2075 IWM_TE_V2_NOTIF_HOST_FRAG_START = (1 << 4),
2076 IWM_TE_V2_NOTIF_HOST_FRAG_END = (1 << 5),
2077 IWM_TE_V2_NOTIF_INTERNAL_FRAG_START = (1 << 6),
2078 IWM_TE_V2_NOTIF_INTERNAL_FRAG_END = (1 << 7),
2080 IWM_TE_V2_NOTIF_MSK = 0xff,
2082 /* placement characteristics */
2083 IWM_TE_V2_DEP_OTHER = (1 << IWM_TE_V2_PLACEMENT_POS),
2084 IWM_TE_V2_DEP_TSF = (1 << (IWM_TE_V2_PLACEMENT_POS + 1)),
2085 IWM_TE_V2_EVENT_SOCIOPATHIC = (1 << (IWM_TE_V2_PLACEMENT_POS + 2)),
2087 /* are we present or absent during the Time Event. */
2088 IWM_TE_V2_ABSENCE = (1 << IWM_TE_V2_ABSENCE_POS),
2092 * struct iwm_time_event_cmd_api_v2 - configuring Time Events
2093 * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 (see also
2094 * with version 1. determined by IWM_UCODE_TLV_FLAGS)
2095 * ( IWM_TIME_EVENT_CMD = 0x29 )
2096 * @id_and_color: ID and color of the relevant MAC
2097 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
2098 * @id: this field has two meanings, depending on the action:
2099 * If the action is ADD, then it means the type of event to add.
2100 * For all other actions it is the unique event ID assigned when the
2101 * event was added by the FW.
2102 * @apply_time: When to start the Time Event (in GP2)
2103 * @max_delay: maximum delay to event's start (apply time), in TU
2104 * @depends_on: the unique ID of the event we depend on (if any)
2105 * @interval: interval between repetitions, in TU
2106 * @duration: duration of event in TU
2107 * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS
2108 * @max_frags: maximal number of fragments the Time Event can be divided to
2109 * @policy: defines whether uCode shall notify the host or other uCode modules
2110 * on event and/or fragment start and/or end
2111 * using one of IWM_TE_INDEPENDENT, IWM_TE_DEP_OTHER, IWM_TE_DEP_TSF
2112 * IWM_TE_EVENT_SOCIOPATHIC
2113 * using IWM_TE_ABSENCE and using IWM_TE_NOTIF_*
2115 struct iwm_time_event_cmd_v2 {
2116 /* COMMON_INDEX_HDR_API_S_VER_1 */
2117 uint32_t id_and_color;
2120 /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 */
2121 uint32_t apply_time;
2123 uint32_t depends_on;
2129 } __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_2 */
2132 * struct iwm_time_event_resp - response structure to iwm_time_event_cmd
2133 * @status: bit 0 indicates success, all others specify errors
2134 * @id: the Time Event type
2135 * @unique_id: the unique ID assigned (in ADD) or given (others) to the TE
2136 * @id_and_color: ID and color of the relevant MAC
2138 struct iwm_time_event_resp {
2142 uint32_t id_and_color;
2143 } __packed; /* IWM_MAC_TIME_EVENT_RSP_API_S_VER_1 */
2146 * struct iwm_time_event_notif - notifications of time event start/stop
2147 * ( IWM_TIME_EVENT_NOTIFICATION = 0x2a )
2148 * @timestamp: action timestamp in GP2
2149 * @session_id: session's unique id
2150 * @unique_id: unique id of the Time Event itself
2151 * @id_and_color: ID and color of the relevant MAC
2152 * @action: one of IWM_TE_NOTIF_START or IWM_TE_NOTIF_END
2153 * @status: true if scheduled, false otherwise (not executed)
2155 struct iwm_time_event_notif {
2157 uint32_t session_id;
2159 uint32_t id_and_color;
2162 } __packed; /* IWM_MAC_TIME_EVENT_NTFY_API_S_VER_1 */
2165 /* Bindings and Time Quota */
2168 * struct iwm_binding_cmd - configuring bindings
2169 * ( IWM_BINDING_CONTEXT_CMD = 0x2b )
2170 * @id_and_color: ID and color of the relevant Binding
2171 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
2172 * @macs: array of MAC id and colors which belong to the binding
2173 * @phy: PHY id and color which belongs to the binding
2175 struct iwm_binding_cmd {
2176 /* COMMON_INDEX_HDR_API_S_VER_1 */
2177 uint32_t id_and_color;
2179 /* IWM_BINDING_DATA_API_S_VER_1 */
2180 uint32_t macs[IWM_MAX_MACS_IN_BINDING];
2182 } __packed; /* IWM_BINDING_CMD_API_S_VER_1 */
2184 /* The maximal number of fragments in the FW's schedule session */
2185 #define IWM_MVM_MAX_QUOTA 128
2188 * struct iwm_time_quota_data - configuration of time quota per binding
2189 * @id_and_color: ID and color of the relevant Binding
2190 * @quota: absolute time quota in TU. The scheduler will try to divide the
2191 * remainig quota (after Time Events) according to this quota.
2192 * @max_duration: max uninterrupted context duration in TU
2194 struct iwm_time_quota_data {
2195 uint32_t id_and_color;
2197 uint32_t max_duration;
2198 } __packed; /* IWM_TIME_QUOTA_DATA_API_S_VER_1 */
2201 * struct iwm_time_quota_cmd - configuration of time quota between bindings
2202 * ( IWM_TIME_QUOTA_CMD = 0x2c )
2203 * @quotas: allocations per binding
2205 struct iwm_time_quota_cmd {
2206 struct iwm_time_quota_data quotas[IWM_MAX_BINDINGS];
2207 } __packed; /* IWM_TIME_QUOTA_ALLOCATION_CMD_API_S_VER_1 */
2212 /* Supported bands */
2213 #define IWM_PHY_BAND_5 (0)
2214 #define IWM_PHY_BAND_24 (1)
2216 /* Supported channel width, vary if there is VHT support */
2217 #define IWM_PHY_VHT_CHANNEL_MODE20 (0x0)
2218 #define IWM_PHY_VHT_CHANNEL_MODE40 (0x1)
2219 #define IWM_PHY_VHT_CHANNEL_MODE80 (0x2)
2220 #define IWM_PHY_VHT_CHANNEL_MODE160 (0x3)
2223 * Control channel position:
2224 * For legacy set bit means upper channel, otherwise lower.
2225 * For VHT - bit-2 marks if the control is lower/upper relative to center-freq
2226 * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0.
2229 * 40Mhz |_______|_______|
2230 * 80Mhz |_______|_______|_______|_______|
2231 * 160Mhz |_______|_______|_______|_______|_______|_______|_______|_______|
2232 * code 011 010 001 000 | 100 101 110 111
2234 #define IWM_PHY_VHT_CTRL_POS_1_BELOW (0x0)
2235 #define IWM_PHY_VHT_CTRL_POS_2_BELOW (0x1)
2236 #define IWM_PHY_VHT_CTRL_POS_3_BELOW (0x2)
2237 #define IWM_PHY_VHT_CTRL_POS_4_BELOW (0x3)
2238 #define IWM_PHY_VHT_CTRL_POS_1_ABOVE (0x4)
2239 #define IWM_PHY_VHT_CTRL_POS_2_ABOVE (0x5)
2240 #define IWM_PHY_VHT_CTRL_POS_3_ABOVE (0x6)
2241 #define IWM_PHY_VHT_CTRL_POS_4_ABOVE (0x7)
2244 * @band: IWM_PHY_BAND_*
2245 * @channel: channel number
2246 * @width: PHY_[VHT|LEGACY]_CHANNEL_*
2247 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_*
2249 struct iwm_fw_channel_info {
2256 #define IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS (0)
2257 #define IWM_PHY_RX_CHAIN_DRIVER_FORCE_MSK \
2258 (0x1 << IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS)
2259 #define IWM_PHY_RX_CHAIN_VALID_POS (1)
2260 #define IWM_PHY_RX_CHAIN_VALID_MSK \
2261 (0x7 << IWM_PHY_RX_CHAIN_VALID_POS)
2262 #define IWM_PHY_RX_CHAIN_FORCE_SEL_POS (4)
2263 #define IWM_PHY_RX_CHAIN_FORCE_SEL_MSK \
2264 (0x7 << IWM_PHY_RX_CHAIN_FORCE_SEL_POS)
2265 #define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7)
2266 #define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \
2267 (0x7 << IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS)
2268 #define IWM_PHY_RX_CHAIN_CNT_POS (10)
2269 #define IWM_PHY_RX_CHAIN_CNT_MSK \
2270 (0x3 << IWM_PHY_RX_CHAIN_CNT_POS)
2271 #define IWM_PHY_RX_CHAIN_MIMO_CNT_POS (12)
2272 #define IWM_PHY_RX_CHAIN_MIMO_CNT_MSK \
2273 (0x3 << IWM_PHY_RX_CHAIN_MIMO_CNT_POS)
2274 #define IWM_PHY_RX_CHAIN_MIMO_FORCE_POS (14)
2275 #define IWM_PHY_RX_CHAIN_MIMO_FORCE_MSK \
2276 (0x1 << IWM_PHY_RX_CHAIN_MIMO_FORCE_POS)
2278 /* TODO: fix the value, make it depend on firmware at runtime? */
2279 #define IWM_NUM_PHY_CTX 3
2281 /* TODO: complete missing documentation */
2283 * struct iwm_phy_context_cmd - config of the PHY context
2284 * ( IWM_PHY_CONTEXT_CMD = 0x8 )
2285 * @id_and_color: ID and color of the relevant Binding
2286 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
2287 * @apply_time: 0 means immediate apply and context switch.
2288 * other value means apply new params after X usecs
2289 * @tx_param_color: ???
2291 * @txchain_info: ???
2292 * @rxchain_info: ???
2293 * @acquisition_data: ???
2294 * @dsp_cfg_flags: set to 0
2296 struct iwm_phy_context_cmd {
2297 /* COMMON_INDEX_HDR_API_S_VER_1 */
2298 uint32_t id_and_color;
2300 /* IWM_PHY_CONTEXT_DATA_API_S_VER_1 */
2301 uint32_t apply_time;
2302 uint32_t tx_param_color;
2303 struct iwm_fw_channel_info ci;
2304 uint32_t txchain_info;
2305 uint32_t rxchain_info;
2306 uint32_t acquisition_data;
2307 uint32_t dsp_cfg_flags;
2308 } __packed; /* IWM_PHY_CONTEXT_CMD_API_VER_1 */
2310 #define IWM_RX_INFO_PHY_CNT 8
2311 #define IWM_RX_INFO_ENERGY_ANT_ABC_IDX 1
2312 #define IWM_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff
2313 #define IWM_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00
2314 #define IWM_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000
2315 #define IWM_RX_INFO_ENERGY_ANT_A_POS 0
2316 #define IWM_RX_INFO_ENERGY_ANT_B_POS 8
2317 #define IWM_RX_INFO_ENERGY_ANT_C_POS 16
2319 #define IWM_RX_INFO_AGC_IDX 1
2320 #define IWM_RX_INFO_RSSI_AB_IDX 2
2321 #define IWM_OFDM_AGC_A_MSK 0x0000007f
2322 #define IWM_OFDM_AGC_A_POS 0
2323 #define IWM_OFDM_AGC_B_MSK 0x00003f80
2324 #define IWM_OFDM_AGC_B_POS 7
2325 #define IWM_OFDM_AGC_CODE_MSK 0x3fe00000
2326 #define IWM_OFDM_AGC_CODE_POS 20
2327 #define IWM_OFDM_RSSI_INBAND_A_MSK 0x00ff
2328 #define IWM_OFDM_RSSI_A_POS 0
2329 #define IWM_OFDM_RSSI_ALLBAND_A_MSK 0xff00
2330 #define IWM_OFDM_RSSI_ALLBAND_A_POS 8
2331 #define IWM_OFDM_RSSI_INBAND_B_MSK 0xff0000
2332 #define IWM_OFDM_RSSI_B_POS 16
2333 #define IWM_OFDM_RSSI_ALLBAND_B_MSK 0xff000000
2334 #define IWM_OFDM_RSSI_ALLBAND_B_POS 24
2337 * struct iwm_rx_phy_info - phy info
2338 * (IWM_REPLY_RX_PHY_CMD = 0xc0)
2339 * @non_cfg_phy_cnt: non configurable DSP phy data byte count
2340 * @cfg_phy_cnt: configurable DSP phy data byte count
2341 * @stat_id: configurable DSP phy data set ID
2343 * @system_timestamp: GP2 at on air rise
2344 * @timestamp: TSF at on air rise
2345 * @beacon_time_stamp: beacon at on-air rise
2346 * @phy_flags: general phy flags: band, modulation, ...
2347 * @channel: channel number
2348 * @non_cfg_phy_buf: for various implementations of non_cfg_phy
2349 * @rate_n_flags: IWM_RATE_MCS_*
2350 * @byte_count: frame's byte-count
2351 * @frame_time: frame's time on the air, based on byte count and frame rate
2353 * @mac_active_msk: what MACs were active when the frame was received
2355 * Before each Rx, the device sends this data. It contains PHY information
2356 * about the reception of the packet.
2358 struct iwm_rx_phy_info {
2359 uint8_t non_cfg_phy_cnt;
2360 uint8_t cfg_phy_cnt;
2363 uint32_t system_timestamp;
2365 uint32_t beacon_time_stamp;
2367 #define IWM_PHY_INFO_FLAG_SHPREAMBLE (1 << 2)
2369 uint32_t non_cfg_phy[IWM_RX_INFO_PHY_CNT];
2373 uint32_t byte_count;
2374 uint16_t mac_active_msk;
2375 uint16_t frame_time;
2378 struct iwm_rx_mpdu_res_start {
2379 uint16_t byte_count;
2384 * enum iwm_rx_phy_flags - to parse %iwm_rx_phy_info phy_flags
2385 * @IWM_RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band
2386 * @IWM_RX_RES_PHY_FLAGS_MOD_CCK:
2387 * @IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short
2388 * @IWM_RX_RES_PHY_FLAGS_NARROW_BAND:
2389 * @IWM_RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received
2390 * @IWM_RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU
2391 * @IWM_RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame
2392 * @IWM_RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble
2393 * @IWM_RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame
2395 enum iwm_rx_phy_flags {
2396 IWM_RX_RES_PHY_FLAGS_BAND_24 = (1 << 0),
2397 IWM_RX_RES_PHY_FLAGS_MOD_CCK = (1 << 1),
2398 IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE = (1 << 2),
2399 IWM_RX_RES_PHY_FLAGS_NARROW_BAND = (1 << 3),
2400 IWM_RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4),
2401 IWM_RX_RES_PHY_FLAGS_ANTENNA_POS = 4,
2402 IWM_RX_RES_PHY_FLAGS_AGG = (1 << 7),
2403 IWM_RX_RES_PHY_FLAGS_OFDM_HT = (1 << 8),
2404 IWM_RX_RES_PHY_FLAGS_OFDM_GF = (1 << 9),
2405 IWM_RX_RES_PHY_FLAGS_OFDM_VHT = (1 << 10),
2409 * enum iwm_mvm_rx_status - written by fw for each Rx packet
2410 * @IWM_RX_MPDU_RES_STATUS_CRC_OK: CRC is fine
2411 * @IWM_RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow
2412 * @IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND:
2413 * @IWM_RX_MPDU_RES_STATUS_KEY_VALID:
2414 * @IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK:
2415 * @IWM_RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed
2416 * @IWM_RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked
2418 * @IWM_RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine
2419 * @IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or
2420 * alg = CCM only. Checks replay attack for 11w frames. Relevant only if
2421 * %IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set.
2422 * @IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted
2423 * @IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP
2424 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM
2425 * @IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP
2426 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC
2427 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted
2428 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm
2429 * @IWM_RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted
2430 * @IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP:
2431 * @IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP:
2432 * @IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT:
2433 * @IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame
2434 * @IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK:
2435 * @IWM_RX_MPDU_RES_STATUS_STA_ID_MSK:
2436 * @IWM_RX_MPDU_RES_STATUS_RRF_KILL:
2437 * @IWM_RX_MPDU_RES_STATUS_FILTERING_MSK:
2438 * @IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK:
2440 enum iwm_mvm_rx_status {
2441 IWM_RX_MPDU_RES_STATUS_CRC_OK = (1 << 0),
2442 IWM_RX_MPDU_RES_STATUS_OVERRUN_OK = (1 << 1),
2443 IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND = (1 << 2),
2444 IWM_RX_MPDU_RES_STATUS_KEY_VALID = (1 << 3),
2445 IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK = (1 << 4),
2446 IWM_RX_MPDU_RES_STATUS_ICV_OK = (1 << 5),
2447 IWM_RX_MPDU_RES_STATUS_MIC_OK = (1 << 6),
2448 IWM_RX_MPDU_RES_STATUS_TTAK_OK = (1 << 7),
2449 IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = (1 << 7),
2450 IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8),
2451 IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8),
2452 IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8),
2453 IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8),
2454 IWM_RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8),
2455 IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC = (6 << 8),
2456 IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8),
2457 IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8),
2458 IWM_RX_MPDU_RES_STATUS_DEC_DONE = (1 << 11),
2459 IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP = (1 << 12),
2460 IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP = (1 << 13),
2461 IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT = (1 << 14),
2462 IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME = (1 << 15),
2463 IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK = (0x3F0000),
2464 IWM_RX_MPDU_RES_STATUS_STA_ID_MSK = (0x1f000000),
2465 IWM_RX_MPDU_RES_STATUS_RRF_KILL = (1 << 29),
2466 IWM_RX_MPDU_RES_STATUS_FILTERING_MSK = (0xc00000),
2467 IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK = (0xc0000000),
2471 * struct iwm_radio_version_notif - information on the radio version
2472 * ( IWM_RADIO_VERSION_NOTIFICATION = 0x68 )
2477 struct iwm_radio_version_notif {
2478 uint32_t radio_flavor;
2479 uint32_t radio_step;
2480 uint32_t radio_dash;
2481 } __packed; /* IWM_RADIO_VERSION_NOTOFICATION_S_VER_1 */
2483 enum iwm_card_state_flags {
2484 IWM_CARD_ENABLED = 0x00,
2485 IWM_HW_CARD_DISABLED = 0x01,
2486 IWM_SW_CARD_DISABLED = 0x02,
2487 IWM_CT_KILL_CARD_DISABLED = 0x04,
2488 IWM_HALT_CARD_DISABLED = 0x08,
2489 IWM_CARD_DISABLED_MSK = 0x0f,
2490 IWM_CARD_IS_RX_ON = 0x10,
2494 * struct iwm_radio_version_notif - information on the radio version
2495 * (IWM_CARD_STATE_NOTIFICATION = 0xa1 )
2496 * @flags: %iwm_card_state_flags
2498 struct iwm_card_state_notif {
2500 } __packed; /* CARD_STATE_NTFY_API_S_VER_1 */
2503 * struct iwm_missed_beacons_notif - information on missed beacons
2504 * ( IWM_MISSED_BEACONS_NOTIFICATION = 0xa2 )
2505 * @mac_id: interface ID
2506 * @consec_missed_beacons_since_last_rx: number of consecutive missed
2507 * beacons since last RX.
2508 * @consec_missed_beacons: number of consecutive missed beacons
2509 * @num_expected_beacons:
2510 * @num_recvd_beacons:
2512 struct iwm_missed_beacons_notif {
2514 uint32_t consec_missed_beacons_since_last_rx;
2515 uint32_t consec_missed_beacons;
2516 uint32_t num_expected_beacons;
2517 uint32_t num_recvd_beacons;
2518 } __packed; /* IWM_MISSED_BEACON_NTFY_API_S_VER_3 */
2521 * struct iwm_set_calib_default_cmd - set default value for calibration.
2522 * ( IWM_SET_CALIB_DEFAULT_CMD = 0x8e )
2523 * @calib_index: the calibration to set value for
2525 * @data: the value to set for the calibration result
2527 struct iwm_set_calib_default_cmd {
2528 uint16_t calib_index;
2531 } __packed; /* IWM_PHY_CALIB_OVERRIDE_VALUES_S */
2533 #define IWM_MAX_PORT_ID_NUM 2
2534 #define IWM_MAX_MCAST_FILTERING_ADDRESSES 256
2537 * struct iwm_mcast_filter_cmd - configure multicast filter.
2538 * @filter_own: Set 1 to filter out multicast packets sent by station itself
2539 * @port_id: Multicast MAC addresses array specifier. This is a strange way
2540 * to identify network interface adopted in host-device IF.
2541 * It is used by FW as index in array of addresses. This array has
2542 * IWM_MAX_PORT_ID_NUM members.
2543 * @count: Number of MAC addresses in the array
2544 * @pass_all: Set 1 to pass all multicast packets.
2545 * @bssid: current association BSSID.
2546 * @addr_list: Place holder for array of MAC addresses.
2547 * IMPORTANT: add padding if necessary to ensure DWORD alignment.
2549 struct iwm_mcast_filter_cmd {
2555 uint8_t reserved[2];
2556 uint8_t addr_list[0];
2557 } __packed; /* IWM_MCAST_FILTERING_CMD_API_S_VER_1 */
2559 struct iwm_mvm_statistics_dbg {
2560 uint32_t burst_check;
2561 uint32_t burst_count;
2562 uint32_t wait_for_silence_timeout_cnt;
2563 uint32_t reserved[3];
2564 } __packed; /* IWM_STATISTICS_DEBUG_API_S_VER_2 */
2566 struct iwm_mvm_statistics_div {
2570 uint32_t probe_time;
2573 } __packed; /* IWM_STATISTICS_SLOW_DIV_API_S_VER_2 */
2575 struct iwm_mvm_statistics_general_common {
2576 uint32_t temperature; /* radio temperature */
2577 uint32_t temperature_m; /* radio voltage */
2578 struct iwm_mvm_statistics_dbg dbg;
2579 uint32_t sleep_time;
2581 uint32_t slots_idle;
2582 uint32_t ttl_timestamp;
2583 struct iwm_mvm_statistics_div div;
2584 uint32_t rx_enable_counter;
2586 * num_of_sos_states:
2587 * count the number of times we have to re-tune
2588 * in order to get out of bad PHY status
2590 uint32_t num_of_sos_states;
2591 } __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */
2593 struct iwm_mvm_statistics_rx_non_phy {
2594 uint32_t bogus_cts; /* CTS received when not expecting CTS */
2595 uint32_t bogus_ack; /* ACK received when not expecting ACK */
2596 uint32_t non_bssid_frames; /* number of frames with BSSID that
2597 * doesn't belong to the STA BSSID */
2598 uint32_t filtered_frames; /* count frames that were dumped in the
2599 * filtering process */
2600 uint32_t non_channel_beacons; /* beacons with our bss id but not on
2601 * our serving channel */
2602 uint32_t channel_beacons; /* beacons with our bss id and in our
2603 * serving channel */
2604 uint32_t num_missed_bcon; /* number of missed beacons */
2605 uint32_t adc_rx_saturation_time; /* count in 0.8us units the time the
2606 * ADC was in saturation */
2607 uint32_t ina_detection_search_time;/* total time (in 0.8us) searched
2609 uint32_t beacon_silence_rssi[3];/* RSSI silence after beacon frame */
2610 uint32_t interference_data_flag; /* flag for interference data
2611 * availability. 1 when data is
2613 uint32_t channel_load; /* counts RX Enable time in uSec */
2614 uint32_t dsp_false_alarms; /* DSP false alarm (both OFDM
2615 * and CCK) counter */
2616 uint32_t beacon_rssi_a;
2617 uint32_t beacon_rssi_b;
2618 uint32_t beacon_rssi_c;
2619 uint32_t beacon_energy_a;
2620 uint32_t beacon_energy_b;
2621 uint32_t beacon_energy_c;
2622 uint32_t num_bt_kills;
2624 uint32_t directed_data_mpdu;
2625 } __packed; /* IWM_STATISTICS_RX_NON_PHY_API_S_VER_3 */
2627 struct iwm_mvm_statistics_rx_phy {
2632 uint32_t overrun_err;
2633 uint32_t early_overrun_err;
2634 uint32_t crc32_good;
2635 uint32_t false_alarm_cnt;
2636 uint32_t fina_sync_err_cnt;
2637 uint32_t sfd_timeout;
2638 uint32_t fina_timeout;
2639 uint32_t unresponded_rts;
2640 uint32_t rxe_frame_limit_overrun;
2641 uint32_t sent_ack_cnt;
2642 uint32_t sent_cts_cnt;
2643 uint32_t sent_ba_rsp_cnt;
2644 uint32_t dsp_self_kill;
2645 uint32_t mh_format_err;
2646 uint32_t re_acq_main_rssi_sum;
2648 } __packed; /* IWM_STATISTICS_RX_PHY_API_S_VER_2 */
2650 struct iwm_mvm_statistics_rx_ht_phy {
2652 uint32_t overrun_err;
2653 uint32_t early_overrun_err;
2654 uint32_t crc32_good;
2656 uint32_t mh_format_err;
2657 uint32_t agg_crc32_good;
2658 uint32_t agg_mpdu_cnt;
2660 uint32_t unsupport_mcs;
2661 } __packed; /* IWM_STATISTICS_HT_RX_PHY_API_S_VER_1 */
2663 #define IWM_MAX_CHAINS 3
2665 struct iwm_mvm_statistics_tx_non_phy_agg {
2666 uint32_t ba_timeout;
2667 uint32_t ba_reschedule_frames;
2668 uint32_t scd_query_agg_frame_cnt;
2669 uint32_t scd_query_no_agg;
2670 uint32_t scd_query_agg;
2671 uint32_t scd_query_mismatch;
2672 uint32_t frame_not_ready;
2674 uint32_t bt_prio_kill;
2675 uint32_t rx_ba_rsp_cnt;
2676 int8_t txpower[IWM_MAX_CHAINS];
2679 } __packed; /* IWM_STATISTICS_TX_NON_PHY_AGG_API_S_VER_1 */
2681 struct iwm_mvm_statistics_tx_channel_width {
2682 uint32_t ext_cca_narrow_ch20[1];
2683 uint32_t ext_cca_narrow_ch40[2];
2684 uint32_t ext_cca_narrow_ch80[3];
2685 uint32_t ext_cca_narrow_ch160[4];
2686 uint32_t last_tx_ch_width_indx;
2687 uint32_t rx_detected_per_ch_width[4];
2688 uint32_t success_per_ch_width[4];
2689 uint32_t fail_per_ch_width[4];
2690 }; /* IWM_STATISTICS_TX_CHANNEL_WIDTH_API_S_VER_1 */
2692 struct iwm_mvm_statistics_tx {
2693 uint32_t preamble_cnt;
2694 uint32_t rx_detected_cnt;
2695 uint32_t bt_prio_defer_cnt;
2696 uint32_t bt_prio_kill_cnt;
2697 uint32_t few_bytes_cnt;
2698 uint32_t cts_timeout;
2699 uint32_t ack_timeout;
2700 uint32_t expected_ack_cnt;
2701 uint32_t actual_ack_cnt;
2702 uint32_t dump_msdu_cnt;
2703 uint32_t burst_abort_next_frame_mismatch_cnt;
2704 uint32_t burst_abort_missing_next_frame_cnt;
2705 uint32_t cts_timeout_collision;
2706 uint32_t ack_or_ba_timeout_collision;
2707 struct iwm_mvm_statistics_tx_non_phy_agg agg;
2708 struct iwm_mvm_statistics_tx_channel_width channel_width;
2709 } __packed; /* IWM_STATISTICS_TX_API_S_VER_4 */
2712 struct iwm_mvm_statistics_bt_activity {
2713 uint32_t hi_priority_tx_req_cnt;
2714 uint32_t hi_priority_tx_denied_cnt;
2715 uint32_t lo_priority_tx_req_cnt;
2716 uint32_t lo_priority_tx_denied_cnt;
2717 uint32_t hi_priority_rx_req_cnt;
2718 uint32_t hi_priority_rx_denied_cnt;
2719 uint32_t lo_priority_rx_req_cnt;
2720 uint32_t lo_priority_rx_denied_cnt;
2721 } __packed; /* IWM_STATISTICS_BT_ACTIVITY_API_S_VER_1 */
2723 struct iwm_mvm_statistics_general {
2724 struct iwm_mvm_statistics_general_common common;
2725 uint32_t beacon_filtered;
2726 uint32_t missed_beacons;
2727 int8_t beacon_filter_average_energy;
2728 int8_t beacon_filter_reason;
2729 int8_t beacon_filter_current_energy;
2730 int8_t beacon_filter_reserved;
2731 uint32_t beacon_filter_delta_time;
2732 struct iwm_mvm_statistics_bt_activity bt_activity;
2733 } __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */
2735 struct iwm_mvm_statistics_rx {
2736 struct iwm_mvm_statistics_rx_phy ofdm;
2737 struct iwm_mvm_statistics_rx_phy cck;
2738 struct iwm_mvm_statistics_rx_non_phy general;
2739 struct iwm_mvm_statistics_rx_ht_phy ofdm_ht;
2740 } __packed; /* IWM_STATISTICS_RX_API_S_VER_3 */
2743 * IWM_STATISTICS_NOTIFICATION = 0x9d (notification only, not a command)
2745 * By default, uCode issues this notification after receiving a beacon
2746 * while associated. To disable this behavior, set DISABLE_NOTIF flag in the
2747 * IWM_REPLY_STATISTICS_CMD 0x9c, above.
2749 * Statistics counters continue to increment beacon after beacon, but are
2750 * cleared when changing channels or when driver issues IWM_REPLY_STATISTICS_CMD
2751 * 0x9c with CLEAR_STATS bit set (see above).
2753 * uCode also issues this notification during scans. uCode clears statistics
2754 * appropriately so that each notification contains statistics for only the
2755 * one channel that has just been scanned.
2758 struct iwm_notif_statistics { /* IWM_STATISTICS_NTFY_API_S_VER_8 */
2760 struct iwm_mvm_statistics_rx rx;
2761 struct iwm_mvm_statistics_tx tx;
2762 struct iwm_mvm_statistics_general general;
2765 /***********************************
2767 ***********************************/
2768 /* Smart Fifo state */
2770 IWM_SF_LONG_DELAY_ON = 0, /* should never be called by driver */
2774 IWM_SF_HW_NUM_STATES
2777 /* Smart Fifo possible scenario */
2778 enum iwm_sf_scenario {
2779 IWM_SF_SCENARIO_SINGLE_UNICAST,
2780 IWM_SF_SCENARIO_AGG_UNICAST,
2781 IWM_SF_SCENARIO_MULTICAST,
2782 IWM_SF_SCENARIO_BA_RESP,
2783 IWM_SF_SCENARIO_TX_RESP,
2787 #define IWM_SF_TRANSIENT_STATES_NUMBER 2 /* IWM_SF_LONG_DELAY_ON and IWM_SF_FULL_ON */
2788 #define IWM_SF_NUM_TIMEOUT_TYPES 2 /* Aging timer and Idle timer */
2790 /* smart FIFO default values */
2791 #define IWM_SF_W_MARK_SISO 4096
2792 #define IWM_SF_W_MARK_MIMO2 8192
2793 #define IWM_SF_W_MARK_MIMO3 6144
2794 #define IWM_SF_W_MARK_LEGACY 4096
2795 #define IWM_SF_W_MARK_SCAN 4096
2797 /* SF Scenarios timers for FULL_ON state (aligned to 32 uSec) */
2798 #define IWM_SF_SINGLE_UNICAST_IDLE_TIMER 320 /* 300 uSec */
2799 #define IWM_SF_SINGLE_UNICAST_AGING_TIMER 2016 /* 2 mSec */
2800 #define IWM_SF_AGG_UNICAST_IDLE_TIMER 320 /* 300 uSec */
2801 #define IWM_SF_AGG_UNICAST_AGING_TIMER 2016 /* 2 mSec */
2802 #define IWM_SF_MCAST_IDLE_TIMER 2016 /* 2 mSec */
2803 #define IWM_SF_MCAST_AGING_TIMER 10016 /* 10 mSec */
2804 #define IWM_SF_BA_IDLE_TIMER 320 /* 300 uSec */
2805 #define IWM_SF_BA_AGING_TIMER 2016 /* 2 mSec */
2806 #define IWM_SF_TX_RE_IDLE_TIMER 320 /* 300 uSec */
2807 #define IWM_SF_TX_RE_AGING_TIMER 2016 /* 2 mSec */
2809 #define IWM_SF_LONG_DELAY_AGING_TIMER 1000000 /* 1 Sec */
2812 * Smart Fifo configuration command.
2813 * @state: smart fifo state, types listed in iwm_sf_sate.
2814 * @watermark: Minimum allowed availabe free space in RXF for transient state.
2815 * @long_delay_timeouts: aging and idle timer values for each scenario
2816 * in long delay state.
2817 * @full_on_timeouts: timer values for each scenario in full on state.
2819 struct iwm_sf_cfg_cmd {
2820 enum iwm_sf_state state;
2821 uint32_t watermark[IWM_SF_TRANSIENT_STATES_NUMBER];
2822 uint32_t long_delay_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES];
2823 uint32_t full_on_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES];
2824 } __packed; /* IWM_SF_CFG_API_S_VER_2 */
2827 * The first MAC indices (starting from 0)
2828 * are available to the driver, AUX follows
2830 #define IWM_MAC_INDEX_AUX 4
2831 #define IWM_MAC_INDEX_MIN_DRIVER 0
2832 #define IWM_NUM_MAC_INDEX_DRIVER IWM_MAC_INDEX_AUX
2843 * enum iwm_mac_protection_flags - MAC context flags
2844 * @IWM_MAC_PROT_FLG_TGG_PROTECT: 11g protection when transmitting OFDM frames,
2845 * this will require CCK RTS/CTS2self.
2846 * RTS/CTS will protect full burst time.
2847 * @IWM_MAC_PROT_FLG_HT_PROT: enable HT protection
2848 * @IWM_MAC_PROT_FLG_FAT_PROT: protect 40 MHz transmissions
2849 * @IWM_MAC_PROT_FLG_SELF_CTS_EN: allow CTS2self
2851 enum iwm_mac_protection_flags {
2852 IWM_MAC_PROT_FLG_TGG_PROTECT = (1 << 3),
2853 IWM_MAC_PROT_FLG_HT_PROT = (1 << 23),
2854 IWM_MAC_PROT_FLG_FAT_PROT = (1 << 24),
2855 IWM_MAC_PROT_FLG_SELF_CTS_EN = (1 << 30),
2858 #define IWM_MAC_FLG_SHORT_SLOT (1 << 4)
2859 #define IWM_MAC_FLG_SHORT_PREAMBLE (1 << 5)
2862 * enum iwm_mac_types - Supported MAC types
2863 * @IWM_FW_MAC_TYPE_FIRST: lowest supported MAC type
2864 * @IWM_FW_MAC_TYPE_AUX: Auxiliary MAC (internal)
2865 * @IWM_FW_MAC_TYPE_LISTENER: monitor MAC type (?)
2866 * @IWM_FW_MAC_TYPE_PIBSS: Pseudo-IBSS
2867 * @IWM_FW_MAC_TYPE_IBSS: IBSS
2868 * @IWM_FW_MAC_TYPE_BSS_STA: BSS (managed) station
2869 * @IWM_FW_MAC_TYPE_P2P_DEVICE: P2P Device
2870 * @IWM_FW_MAC_TYPE_P2P_STA: P2P client
2871 * @IWM_FW_MAC_TYPE_GO: P2P GO
2872 * @IWM_FW_MAC_TYPE_TEST: ?
2873 * @IWM_FW_MAC_TYPE_MAX: highest support MAC type
2875 enum iwm_mac_types {
2876 IWM_FW_MAC_TYPE_FIRST = 1,
2877 IWM_FW_MAC_TYPE_AUX = IWM_FW_MAC_TYPE_FIRST,
2878 IWM_FW_MAC_TYPE_LISTENER,
2879 IWM_FW_MAC_TYPE_PIBSS,
2880 IWM_FW_MAC_TYPE_IBSS,
2881 IWM_FW_MAC_TYPE_BSS_STA,
2882 IWM_FW_MAC_TYPE_P2P_DEVICE,
2883 IWM_FW_MAC_TYPE_P2P_STA,
2885 IWM_FW_MAC_TYPE_TEST,
2886 IWM_FW_MAC_TYPE_MAX = IWM_FW_MAC_TYPE_TEST
2887 }; /* IWM_MAC_CONTEXT_TYPE_API_E_VER_1 */
2890 * enum iwm_tsf_id - TSF hw timer ID
2891 * @IWM_TSF_ID_A: use TSF A
2892 * @IWM_TSF_ID_B: use TSF B
2893 * @IWM_TSF_ID_C: use TSF C
2894 * @IWM_TSF_ID_D: use TSF D
2895 * @IWM_NUM_TSF_IDS: number of TSF timers available
2902 IWM_NUM_TSF_IDS = 4,
2903 }; /* IWM_TSF_ID_API_E_VER_1 */
2906 * struct iwm_mac_data_ap - configuration data for AP MAC context
2907 * @beacon_time: beacon transmit time in system time
2908 * @beacon_tsf: beacon transmit time in TSF
2909 * @bi: beacon interval in TU
2910 * @bi_reciprocal: 2^32 / bi
2911 * @dtim_interval: dtim transmit time in TU
2912 * @dtim_reciprocal: 2^32 / dtim_interval
2913 * @mcast_qid: queue ID for multicast traffic
2914 * @beacon_template: beacon template ID
2916 struct iwm_mac_data_ap {
2917 uint32_t beacon_time;
2918 uint64_t beacon_tsf;
2920 uint32_t bi_reciprocal;
2921 uint32_t dtim_interval;
2922 uint32_t dtim_reciprocal;
2924 uint32_t beacon_template;
2925 } __packed; /* AP_MAC_DATA_API_S_VER_1 */
2928 * struct iwm_mac_data_ibss - configuration data for IBSS MAC context
2929 * @beacon_time: beacon transmit time in system time
2930 * @beacon_tsf: beacon transmit time in TSF
2931 * @bi: beacon interval in TU
2932 * @bi_reciprocal: 2^32 / bi
2933 * @beacon_template: beacon template ID
2935 struct iwm_mac_data_ibss {
2936 uint32_t beacon_time;
2937 uint64_t beacon_tsf;
2939 uint32_t bi_reciprocal;
2940 uint32_t beacon_template;
2941 } __packed; /* IBSS_MAC_DATA_API_S_VER_1 */
2944 * struct iwm_mac_data_sta - configuration data for station MAC context
2945 * @is_assoc: 1 for associated state, 0 otherwise
2946 * @dtim_time: DTIM arrival time in system time
2947 * @dtim_tsf: DTIM arrival time in TSF
2948 * @bi: beacon interval in TU, applicable only when associated
2949 * @bi_reciprocal: 2^32 / bi , applicable only when associated
2950 * @dtim_interval: DTIM interval in TU, applicable only when associated
2951 * @dtim_reciprocal: 2^32 / dtim_interval , applicable only when associated
2952 * @listen_interval: in beacon intervals, applicable only when associated
2953 * @assoc_id: unique ID assigned by the AP during association
2955 struct iwm_mac_data_sta {
2960 uint32_t bi_reciprocal;
2961 uint32_t dtim_interval;
2962 uint32_t dtim_reciprocal;
2963 uint32_t listen_interval;
2965 uint32_t assoc_beacon_arrive_time;
2966 } __packed; /* IWM_STA_MAC_DATA_API_S_VER_1 */
2969 * struct iwm_mac_data_go - configuration data for P2P GO MAC context
2970 * @ap: iwm_mac_data_ap struct with most config data
2971 * @ctwin: client traffic window in TU (period after TBTT when GO is present).
2972 * 0 indicates that there is no CT window.
2973 * @opp_ps_enabled: indicate that opportunistic PS allowed
2975 struct iwm_mac_data_go {
2976 struct iwm_mac_data_ap ap;
2978 uint32_t opp_ps_enabled;
2979 } __packed; /* GO_MAC_DATA_API_S_VER_1 */
2982 * struct iwm_mac_data_p2p_sta - configuration data for P2P client MAC context
2983 * @sta: iwm_mac_data_sta struct with most config data
2984 * @ctwin: client traffic window in TU (period after TBTT when GO is present).
2985 * 0 indicates that there is no CT window.
2987 struct iwm_mac_data_p2p_sta {
2988 struct iwm_mac_data_sta sta;
2990 } __packed; /* P2P_STA_MAC_DATA_API_S_VER_1 */
2993 * struct iwm_mac_data_pibss - Pseudo IBSS config data
2994 * @stats_interval: interval in TU between statistics notifications to host.
2996 struct iwm_mac_data_pibss {
2997 uint32_t stats_interval;
2998 } __packed; /* PIBSS_MAC_DATA_API_S_VER_1 */
3001 * struct iwm_mac_data_p2p_dev - configuration data for the P2P Device MAC
3003 * @is_disc_extended: if set to true, P2P Device discoverability is enabled on
3004 * other channels as well. This should be to true only in case that the
3005 * device is discoverable and there is an active GO. Note that setting this
3006 * field when not needed, will increase the number of interrupts and have
3007 * effect on the platform power, as this setting opens the Rx filters on
3010 struct iwm_mac_data_p2p_dev {
3011 uint32_t is_disc_extended;
3012 } __packed; /* _P2P_DEV_MAC_DATA_API_S_VER_1 */
3015 * enum iwm_mac_filter_flags - MAC context filter flags
3016 * @IWM_MAC_FILTER_IN_PROMISC: accept all data frames
3017 * @IWM_MAC_FILTER_IN_CONTROL_AND_MGMT: pass all mangement and
3018 * control frames to the host
3019 * @IWM_MAC_FILTER_ACCEPT_GRP: accept multicast frames
3020 * @IWM_MAC_FILTER_DIS_DECRYPT: don't decrypt unicast frames
3021 * @IWM_MAC_FILTER_DIS_GRP_DECRYPT: don't decrypt multicast frames
3022 * @IWM_MAC_FILTER_IN_BEACON: transfer foreign BSS's beacons to host
3023 * (in station mode when associated)
3024 * @IWM_MAC_FILTER_OUT_BCAST: filter out all broadcast frames
3025 * @IWM_MAC_FILTER_IN_CRC32: extract FCS and append it to frames
3026 * @IWM_MAC_FILTER_IN_PROBE_REQUEST: pass probe requests to host
3028 enum iwm_mac_filter_flags {
3029 IWM_MAC_FILTER_IN_PROMISC = (1 << 0),
3030 IWM_MAC_FILTER_IN_CONTROL_AND_MGMT = (1 << 1),
3031 IWM_MAC_FILTER_ACCEPT_GRP = (1 << 2),
3032 IWM_MAC_FILTER_DIS_DECRYPT = (1 << 3),
3033 IWM_MAC_FILTER_DIS_GRP_DECRYPT = (1 << 4),
3034 IWM_MAC_FILTER_IN_BEACON = (1 << 6),
3035 IWM_MAC_FILTER_OUT_BCAST = (1 << 8),
3036 IWM_MAC_FILTER_IN_CRC32 = (1 << 11),
3037 IWM_MAC_FILTER_IN_PROBE_REQUEST = (1 << 12),
3041 * enum iwm_mac_qos_flags - QoS flags
3042 * @IWM_MAC_QOS_FLG_UPDATE_EDCA: ?
3043 * @IWM_MAC_QOS_FLG_TGN: HT is enabled
3044 * @IWM_MAC_QOS_FLG_TXOP_TYPE: ?
3047 enum iwm_mac_qos_flags {
3048 IWM_MAC_QOS_FLG_UPDATE_EDCA = (1 << 0),
3049 IWM_MAC_QOS_FLG_TGN = (1 << 1),
3050 IWM_MAC_QOS_FLG_TXOP_TYPE = (1 << 4),
3054 * struct iwm_ac_qos - QOS timing params for IWM_MAC_CONTEXT_CMD
3055 * @cw_min: Contention window, start value in numbers of slots.
3056 * Should be a power-of-2, minus 1. Device's default is 0x0f.
3057 * @cw_max: Contention window, max value in numbers of slots.
3058 * Should be a power-of-2, minus 1. Device's default is 0x3f.
3059 * @aifsn: Number of slots in Arbitration Interframe Space (before
3060 * performing random backoff timing prior to Tx). Device default 1.
3061 * @fifos_mask: FIFOs used by this MAC for this AC
3062 * @edca_txop: Length of Tx opportunity, in uSecs. Device default is 0.
3064 * One instance of this config struct for each of 4 EDCA access categories
3065 * in struct iwm_qosparam_cmd.
3067 * Device will automatically increase contention window by (2*CW) + 1 for each
3068 * transmission retry. Device uses cw_max as a bit mask, ANDed with new CW
3069 * value, to cap the CW value.
3077 } __packed; /* IWM_AC_QOS_API_S_VER_2 */
3080 * struct iwm_mac_ctx_cmd - command structure to configure MAC contexts
3081 * ( IWM_MAC_CONTEXT_CMD = 0x28 )
3082 * @id_and_color: ID and color of the MAC
3083 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
3084 * @mac_type: one of IWM_FW_MAC_TYPE_*
3085 * @tsd_id: TSF HW timer, one of IWM_TSF_ID_*
3086 * @node_addr: MAC address
3087 * @bssid_addr: BSSID
3088 * @cck_rates: basic rates available for CCK
3089 * @ofdm_rates: basic rates available for OFDM
3090 * @protection_flags: combination of IWM_MAC_PROT_FLG_FLAG_*
3091 * @cck_short_preamble: 0x20 for enabling short preamble, 0 otherwise
3092 * @short_slot: 0x10 for enabling short slots, 0 otherwise
3093 * @filter_flags: combination of IWM_MAC_FILTER_*
3094 * @qos_flags: from IWM_MAC_QOS_FLG_*
3095 * @ac: one iwm_mac_qos configuration for each AC
3096 * @mac_specific: one of struct iwm_mac_data_*, according to mac_type
3098 struct iwm_mac_ctx_cmd {
3099 /* COMMON_INDEX_HDR_API_S_VER_1 */
3100 uint32_t id_and_color;
3102 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S_VER_1 */
3105 uint8_t node_addr[6];
3106 uint16_t reserved_for_node_addr;
3107 uint8_t bssid_addr[6];
3108 uint16_t reserved_for_bssid_addr;
3110 uint32_t ofdm_rates;
3111 uint32_t protection_flags;
3112 uint32_t cck_short_preamble;
3113 uint32_t short_slot;
3114 uint32_t filter_flags;
3115 /* IWM_MAC_QOS_PARAM_API_S_VER_1 */
3117 struct iwm_ac_qos ac[IWM_AC_NUM+1];
3118 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S */
3120 struct iwm_mac_data_ap ap;
3121 struct iwm_mac_data_go go;
3122 struct iwm_mac_data_sta sta;
3123 struct iwm_mac_data_p2p_sta p2p_sta;
3124 struct iwm_mac_data_p2p_dev p2p_dev;
3125 struct iwm_mac_data_pibss pibss;
3126 struct iwm_mac_data_ibss ibss;
3128 } __packed; /* IWM_MAC_CONTEXT_CMD_API_S_VER_1 */
3130 static inline uint32_t iwm_mvm_reciprocal(uint32_t v)
3134 return 0xFFFFFFFF / v;
3137 #define IWM_NONQOS_SEQ_GET 0x1
3138 #define IWM_NONQOS_SEQ_SET 0x2
3139 struct iwm_nonqos_seq_query_cmd {
3140 uint32_t get_set_flag;
3141 uint32_t mac_id_n_color;
3144 } __packed; /* IWM_NON_QOS_TX_COUNTER_GET_SET_API_S_VER_1 */
3146 /* Power Management Commands, Responses, Notifications */
3148 /* Radio LP RX Energy Threshold measured in dBm */
3149 #define IWM_POWER_LPRX_RSSI_THRESHOLD 75
3150 #define IWM_POWER_LPRX_RSSI_THRESHOLD_MAX 94
3151 #define IWM_POWER_LPRX_RSSI_THRESHOLD_MIN 30
3154 * enum iwm_scan_flags - masks for power table command flags
3155 * @IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off
3156 * receiver and transmitter. '0' - does not allow.
3157 * @IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK: '0' Driver disables power management,
3158 * '1' Driver enables PM (use rest of parameters)
3159 * @IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK: '0' PM have to walk up every DTIM,
3160 * '1' PM could sleep over DTIM till listen Interval.
3161 * @IWM_POWER_FLAGS_SNOOZE_ENA_MSK: Enable snoozing only if uAPSD is enabled and all
3162 * access categories are both delivery and trigger enabled.
3163 * @IWM_POWER_FLAGS_BT_SCO_ENA: Enable BT SCO coex only if uAPSD and
3164 * PBW Snoozing enabled
3165 * @IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK: Advanced PM (uAPSD) enable mask
3166 * @IWM_POWER_FLAGS_LPRX_ENA_MSK: Low Power RX enable.
3167 * @IWM_POWER_FLAGS_AP_UAPSD_MISBEHAVING_ENA_MSK: AP/GO's uAPSD misbehaving
3168 * detection enablement
3170 enum iwm_power_flags {
3171 IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0),
3172 IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK = (1 << 1),
3173 IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK = (1 << 2),
3174 IWM_POWER_FLAGS_SNOOZE_ENA_MSK = (1 << 5),
3175 IWM_POWER_FLAGS_BT_SCO_ENA = (1 << 8),
3176 IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK = (1 << 9),
3177 IWM_POWER_FLAGS_LPRX_ENA_MSK = (1 << 11),
3178 IWM_POWER_FLAGS_UAPSD_MISBEHAVING_ENA_MSK = (1 << 12),
3181 #define IWM_POWER_VEC_SIZE 5
3184 * struct iwm_powertable_cmd - legacy power command. Beside old API support this
3185 * is used also with a new power API for device wide power settings.
3186 * IWM_POWER_TABLE_CMD = 0x77 (command, has simple generic response)
3188 * @flags: Power table command flags from IWM_POWER_FLAGS_*
3189 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec.
3190 * Minimum allowed:- 3 * DTIM. Keep alive period must be
3191 * set regardless of power scheme or current power state.
3192 * FW use this value also when PM is disabled.
3193 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to
3194 * PSM transition - legacy PM
3195 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to
3196 * PSM transition - legacy PM
3197 * @sleep_interval: not in use
3198 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag
3199 * is set. For example, if it is required to skip over
3200 * one DTIM, this value need to be set to 2 (DTIM periods).
3201 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled.
3204 struct iwm_powertable_cmd {
3205 /* PM_POWER_TABLE_CMD_API_S_VER_6 */
3207 uint8_t keep_alive_seconds;
3208 uint8_t debug_flags;
3209 uint32_t rx_data_timeout;
3210 uint32_t tx_data_timeout;
3211 uint32_t sleep_interval[IWM_POWER_VEC_SIZE];
3212 uint32_t skip_dtim_periods;
3213 uint32_t lprx_rssi_threshold;
3217 * enum iwm_device_power_flags - masks for device power command flags
3218 * @DEVIC_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off
3219 * receiver and transmitter. '0' - does not allow. This flag should be
3220 * always set to '1' unless one need to disable actual power down for debug
3222 * @IWM_DEVICE_POWER_FLAGS_CAM_MSK: '1' CAM (Continuous Active Mode) is set, meaning
3223 * that power management is disabled. '0' Power management is enabled, one
3224 * of power schemes is applied.
3226 enum iwm_device_power_flags {
3227 IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0),
3228 IWM_DEVICE_POWER_FLAGS_CAM_MSK = (1 << 13),
3232 * struct iwm_device_power_cmd - device wide power command.
3233 * IWM_DEVICE_POWER_CMD = 0x77 (command, has simple generic response)
3235 * @flags: Power table command flags from IWM_DEVICE_POWER_FLAGS_*
3237 struct iwm_device_power_cmd {
3238 /* PM_POWER_TABLE_CMD_API_S_VER_6 */
3244 * struct iwm_mac_power_cmd - New power command containing uAPSD support
3245 * IWM_MAC_PM_POWER_TABLE = 0xA9 (command, has simple generic response)
3246 * @id_and_color: MAC contex identifier
3247 * @flags: Power table command flags from POWER_FLAGS_*
3248 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec.
3249 * Minimum allowed:- 3 * DTIM. Keep alive period must be
3250 * set regardless of power scheme or current power state.
3251 * FW use this value also when PM is disabled.
3252 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to
3253 * PSM transition - legacy PM
3254 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to
3255 * PSM transition - legacy PM
3256 * @sleep_interval: not in use
3257 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag
3258 * is set. For example, if it is required to skip over
3259 * one DTIM, this value need to be set to 2 (DTIM periods).
3260 * @rx_data_timeout_uapsd: Minimum time (usec) from last Rx packet for AM to
3261 * PSM transition - uAPSD
3262 * @tx_data_timeout_uapsd: Minimum time (usec) from last Tx packet for AM to
3263 * PSM transition - uAPSD
3264 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled.
3266 * @num_skip_dtim: Number of DTIMs to skip if Skip over DTIM flag is set
3267 * @snooze_interval: Maximum time between attempts to retrieve buffered data
3268 * from the AP [msec]
3269 * @snooze_window: A window of time in which PBW snoozing insures that all
3270 * packets received. It is also the minimum time from last
3271 * received unicast RX packet, before client stops snoozing
3274 * @qndp_tid: TID client shall use for uAPSD QNDP triggers
3275 * @uapsd_ac_flags: Set trigger-enabled and delivery-enabled indication for
3276 * each corresponding AC.
3277 * Use IEEE80211_WMM_IE_STA_QOSINFO_AC* for correct values.
3278 * @uapsd_max_sp: Use IEEE80211_WMM_IE_STA_QOSINFO_SP_* for correct
3280 * @heavy_tx_thld_packets: TX threshold measured in number of packets
3281 * @heavy_rx_thld_packets: RX threshold measured in number of packets
3282 * @heavy_tx_thld_percentage: TX threshold measured in load's percentage
3283 * @heavy_rx_thld_percentage: RX threshold measured in load's percentage
3284 * @limited_ps_threshold:
3286 struct iwm_mac_power_cmd {
3287 /* CONTEXT_DESC_API_T_VER_1 */
3288 uint32_t id_and_color;
3290 /* CLIENT_PM_POWER_TABLE_S_VER_1 */
3292 uint16_t keep_alive_seconds;
3293 uint32_t rx_data_timeout;
3294 uint32_t tx_data_timeout;
3295 uint32_t rx_data_timeout_uapsd;
3296 uint32_t tx_data_timeout_uapsd;
3297 uint8_t lprx_rssi_threshold;
3298 uint8_t skip_dtim_periods;
3299 uint16_t snooze_interval;
3300 uint16_t snooze_window;
3301 uint8_t snooze_step;
3303 uint8_t uapsd_ac_flags;
3304 uint8_t uapsd_max_sp;
3305 uint8_t heavy_tx_thld_packets;
3306 uint8_t heavy_rx_thld_packets;
3307 uint8_t heavy_tx_thld_percentage;
3308 uint8_t heavy_rx_thld_percentage;
3309 uint8_t limited_ps_threshold;
3314 * struct iwm_uapsd_misbehaving_ap_notif - FW sends this notification when
3315 * associated AP is identified as improperly implementing uAPSD protocol.
3316 * IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78
3317 * @sta_id: index of station in uCode's station table - associated AP ID in
3320 struct iwm_uapsd_misbehaving_ap_notif {
3323 uint8_t reserved[3];
3327 * struct iwm_beacon_filter_cmd
3328 * IWM_REPLY_BEACON_FILTERING_CMD = 0xd2 (command)
3329 * @id_and_color: MAC contex identifier
3330 * @bf_energy_delta: Used for RSSI filtering, if in 'normal' state. Send beacon
3331 * to driver if delta in Energy values calculated for this and last
3332 * passed beacon is greater than this threshold. Zero value means that
3333 * the Energy change is ignored for beacon filtering, and beacon will
3334 * not be forced to be sent to driver regardless of this delta. Typical
3336 * @bf_roaming_energy_delta: Used for RSSI filtering, if in 'roaming' state.
3337 * Send beacon to driver if delta in Energy values calculated for this
3338 * and last passed beacon is greater than this threshold. Zero value
3339 * means that the Energy change is ignored for beacon filtering while in
3340 * Roaming state, typical energy delta 1dB.
3341 * @bf_roaming_state: Used for RSSI filtering. If absolute Energy values
3342 * calculated for current beacon is less than the threshold, use
3343 * Roaming Energy Delta Threshold, otherwise use normal Energy Delta
3344 * Threshold. Typical energy threshold is -72dBm.
3345 * @bf_temp_threshold: This threshold determines the type of temperature
3346 * filtering (Slow or Fast) that is selected (Units are in Celsuis):
3347 * If the current temperature is above this threshold - Fast filter
3348 * will be used, If the current temperature is below this threshold -
3349 * Slow filter will be used.
3350 * @bf_temp_fast_filter: Send Beacon to driver if delta in temperature values
3351 * calculated for this and the last passed beacon is greater than this
3352 * threshold. Zero value means that the temperature change is ignored for
3353 * beacon filtering; beacons will not be forced to be sent to driver
3354 * regardless of whether its temerature has been changed.
3355 * @bf_temp_slow_filter: Send Beacon to driver if delta in temperature values
3356 * calculated for this and the last passed beacon is greater than this
3357 * threshold. Zero value means that the temperature change is ignored for
3358 * beacon filtering; beacons will not be forced to be sent to driver
3359 * regardless of whether its temerature has been changed.
3360 * @bf_enable_beacon_filter: 1, beacon filtering is enabled; 0, disabled.
3361 * @bf_filter_escape_timer: Send beacons to to driver if no beacons were passed
3362 * for a specific period of time. Units: Beacons.
3363 * @ba_escape_timer: Fully receive and parse beacon if no beacons were passed
3364 * for a longer period of time then this escape-timeout. Units: Beacons.
3365 * @ba_enable_beacon_abort: 1, beacon abort is enabled; 0, disabled.
3367 struct iwm_beacon_filter_cmd {
3368 uint32_t bf_energy_delta;
3369 uint32_t bf_roaming_energy_delta;
3370 uint32_t bf_roaming_state;
3371 uint32_t bf_temp_threshold;
3372 uint32_t bf_temp_fast_filter;
3373 uint32_t bf_temp_slow_filter;
3374 uint32_t bf_enable_beacon_filter;
3375 uint32_t bf_debug_flag;
3376 uint32_t bf_escape_timer;
3377 uint32_t ba_escape_timer;
3378 uint32_t ba_enable_beacon_abort;
3381 /* Beacon filtering and beacon abort */
3382 #define IWM_BF_ENERGY_DELTA_DEFAULT 5
3383 #define IWM_BF_ENERGY_DELTA_MAX 255
3384 #define IWM_BF_ENERGY_DELTA_MIN 0
3386 #define IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT 1
3387 #define IWM_BF_ROAMING_ENERGY_DELTA_MAX 255
3388 #define IWM_BF_ROAMING_ENERGY_DELTA_MIN 0
3390 #define IWM_BF_ROAMING_STATE_DEFAULT 72
3391 #define IWM_BF_ROAMING_STATE_MAX 255
3392 #define IWM_BF_ROAMING_STATE_MIN 0
3394 #define IWM_BF_TEMP_THRESHOLD_DEFAULT 112
3395 #define IWM_BF_TEMP_THRESHOLD_MAX 255
3396 #define IWM_BF_TEMP_THRESHOLD_MIN 0
3398 #define IWM_BF_TEMP_FAST_FILTER_DEFAULT 1
3399 #define IWM_BF_TEMP_FAST_FILTER_MAX 255
3400 #define IWM_BF_TEMP_FAST_FILTER_MIN 0
3402 #define IWM_BF_TEMP_SLOW_FILTER_DEFAULT 5
3403 #define IWM_BF_TEMP_SLOW_FILTER_MAX 255
3404 #define IWM_BF_TEMP_SLOW_FILTER_MIN 0
3406 #define IWM_BF_ENABLE_BEACON_FILTER_DEFAULT 1
3408 #define IWM_BF_DEBUG_FLAG_DEFAULT 0
3410 #define IWM_BF_ESCAPE_TIMER_DEFAULT 50
3411 #define IWM_BF_ESCAPE_TIMER_MAX 1024
3412 #define IWM_BF_ESCAPE_TIMER_MIN 0
3414 #define IWM_BA_ESCAPE_TIMER_DEFAULT 6
3415 #define IWM_BA_ESCAPE_TIMER_D3 9
3416 #define IWM_BA_ESCAPE_TIMER_MAX 1024
3417 #define IWM_BA_ESCAPE_TIMER_MIN 0
3419 #define IWM_BA_ENABLE_BEACON_ABORT_DEFAULT 1
3421 #define IWM_BF_CMD_CONFIG_DEFAULTS \
3422 .bf_energy_delta = htole32(IWM_BF_ENERGY_DELTA_DEFAULT), \
3423 .bf_roaming_energy_delta = \
3424 htole32(IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT), \
3425 .bf_roaming_state = htole32(IWM_BF_ROAMING_STATE_DEFAULT), \
3426 .bf_temp_threshold = htole32(IWM_BF_TEMP_THRESHOLD_DEFAULT), \
3427 .bf_temp_fast_filter = htole32(IWM_BF_TEMP_FAST_FILTER_DEFAULT), \
3428 .bf_temp_slow_filter = htole32(IWM_BF_TEMP_SLOW_FILTER_DEFAULT), \
3429 .bf_debug_flag = htole32(IWM_BF_DEBUG_FLAG_DEFAULT), \
3430 .bf_escape_timer = htole32(IWM_BF_ESCAPE_TIMER_DEFAULT), \
3431 .ba_escape_timer = htole32(IWM_BA_ESCAPE_TIMER_DEFAULT)
3434 * These serve as indexes into
3435 * struct iwm_rate_info fw_rate_idx_to_plcp[IWM_RATE_COUNT];
3436 * TODO: avoid overlap between legacy and HT rates
3439 IWM_RATE_1M_INDEX = 0,
3440 IWM_FIRST_CCK_RATE = IWM_RATE_1M_INDEX,
3444 IWM_LAST_CCK_RATE = IWM_RATE_11M_INDEX,
3446 IWM_FIRST_OFDM_RATE = IWM_RATE_6M_INDEX,
3447 IWM_RATE_MCS_0_INDEX = IWM_RATE_6M_INDEX,
3448 IWM_FIRST_HT_RATE = IWM_RATE_MCS_0_INDEX,
3449 IWM_FIRST_VHT_RATE = IWM_RATE_MCS_0_INDEX,
3452 IWM_RATE_MCS_1_INDEX = IWM_RATE_12M_INDEX,
3454 IWM_RATE_MCS_2_INDEX = IWM_RATE_18M_INDEX,
3456 IWM_RATE_MCS_3_INDEX = IWM_RATE_24M_INDEX,
3458 IWM_RATE_MCS_4_INDEX = IWM_RATE_36M_INDEX,
3460 IWM_RATE_MCS_5_INDEX = IWM_RATE_48M_INDEX,
3462 IWM_RATE_MCS_6_INDEX = IWM_RATE_54M_INDEX,
3463 IWM_LAST_NON_HT_RATE = IWM_RATE_54M_INDEX,
3465 IWM_RATE_MCS_7_INDEX = IWM_RATE_60M_INDEX,
3466 IWM_LAST_HT_RATE = IWM_RATE_MCS_7_INDEX,
3467 IWM_RATE_MCS_8_INDEX,
3468 IWM_RATE_MCS_9_INDEX,
3469 IWM_LAST_VHT_RATE = IWM_RATE_MCS_9_INDEX,
3470 IWM_RATE_COUNT_LEGACY = IWM_LAST_NON_HT_RATE + 1,
3471 IWM_RATE_COUNT = IWM_LAST_VHT_RATE + 1,
3474 #define IWM_RATE_BIT_MSK(r) (1 << (IWM_RATE_##r##M_INDEX))
3476 /* fw API values for legacy bit rates, both OFDM and CCK */
3478 IWM_RATE_6M_PLCP = 13,
3479 IWM_RATE_9M_PLCP = 15,
3480 IWM_RATE_12M_PLCP = 5,
3481 IWM_RATE_18M_PLCP = 7,
3482 IWM_RATE_24M_PLCP = 9,
3483 IWM_RATE_36M_PLCP = 11,
3484 IWM_RATE_48M_PLCP = 1,
3485 IWM_RATE_54M_PLCP = 3,
3486 IWM_RATE_1M_PLCP = 10,
3487 IWM_RATE_2M_PLCP = 20,
3488 IWM_RATE_5M_PLCP = 55,
3489 IWM_RATE_11M_PLCP = 110,
3490 IWM_RATE_INVM_PLCP = -1,
3494 * rate_n_flags bit fields
3496 * The 32-bit value has different layouts in the low 8 bites depending on the
3497 * format. There are three formats, HT, VHT and legacy (11abg, with subformats
3498 * for CCK and OFDM).
3500 * High-throughput (HT) rate format
3501 * bit 8 is 1, bit 26 is 0, bit 9 is 0 (OFDM)
3502 * Very High-throughput (VHT) rate format
3503 * bit 8 is 0, bit 26 is 1, bit 9 is 0 (OFDM)
3504 * Legacy OFDM rate format for bits 7:0
3505 * bit 8 is 0, bit 26 is 0, bit 9 is 0 (OFDM)
3506 * Legacy CCK rate format for bits 7:0:
3507 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK)
3510 /* Bit 8: (1) HT format, (0) legacy or VHT format */
3511 #define IWM_RATE_MCS_HT_POS 8
3512 #define IWM_RATE_MCS_HT_MSK (1 << IWM_RATE_MCS_HT_POS)
3514 /* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */
3515 #define IWM_RATE_MCS_CCK_POS 9
3516 #define IWM_RATE_MCS_CCK_MSK (1 << IWM_RATE_MCS_CCK_POS)
3518 /* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */
3519 #define IWM_RATE_MCS_VHT_POS 26
3520 #define IWM_RATE_MCS_VHT_MSK (1 << IWM_RATE_MCS_VHT_POS)
3524 * High-throughput (HT) rate format for bits 7:0
3526 * 2-0: MCS rate base
3535 * 4-3: 0) Single stream (SISO)
3536 * 1) Dual stream (MIMO)
3537 * 2) Triple stream (MIMO)
3538 * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data
3539 * (bits 7-6 are zero)
3541 * Together the low 5 bits work out to the MCS index because we don't
3542 * support MCSes above 15/23, and 0-7 have one stream, 8-15 have two
3543 * streams and 16-23 have three streams. We could also support MCS 32
3544 * which is the duplicate 20 MHz MCS (bit 5 set, all others zero.)
3546 #define IWM_RATE_HT_MCS_RATE_CODE_MSK 0x7
3547 #define IWM_RATE_HT_MCS_NSS_POS 3
3548 #define IWM_RATE_HT_MCS_NSS_MSK (3 << IWM_RATE_HT_MCS_NSS_POS)
3550 /* Bit 10: (1) Use Green Field preamble */
3551 #define IWM_RATE_HT_MCS_GF_POS 10
3552 #define IWM_RATE_HT_MCS_GF_MSK (1 << IWM_RATE_HT_MCS_GF_POS)
3554 #define IWM_RATE_HT_MCS_INDEX_MSK 0x3f
3557 * Very High-throughput (VHT) rate format for bits 7:0
3559 * 3-0: VHT MCS (0-9)
3560 * 5-4: number of streams - 1:
3561 * 0) Single stream (SISO)
3562 * 1) Dual stream (MIMO)
3563 * 2) Triple stream (MIMO)
3566 /* Bit 4-5: (0) SISO, (1) MIMO2 (2) MIMO3 */
3567 #define IWM_RATE_VHT_MCS_RATE_CODE_MSK 0xf
3568 #define IWM_RATE_VHT_MCS_NSS_POS 4
3569 #define IWM_RATE_VHT_MCS_NSS_MSK (3 << IWM_RATE_VHT_MCS_NSS_POS)
3572 * Legacy OFDM rate format for bits 7:0
3584 * Legacy CCK rate format for bits 7:0:
3585 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK):
3593 #define IWM_RATE_LEGACY_RATE_MSK 0xff
3597 * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz
3598 * 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT
3600 #define IWM_RATE_MCS_CHAN_WIDTH_POS 11
3601 #define IWM_RATE_MCS_CHAN_WIDTH_MSK (3 << IWM_RATE_MCS_CHAN_WIDTH_POS)
3602 #define IWM_RATE_MCS_CHAN_WIDTH_20 (0 << IWM_RATE_MCS_CHAN_WIDTH_POS)
3603 #define IWM_RATE_MCS_CHAN_WIDTH_40 (1 << IWM_RATE_MCS_CHAN_WIDTH_POS)
3604 #define IWM_RATE_MCS_CHAN_WIDTH_80 (2 << IWM_RATE_MCS_CHAN_WIDTH_POS)
3605 #define IWM_RATE_MCS_CHAN_WIDTH_160 (3 << IWM_RATE_MCS_CHAN_WIDTH_POS)
3607 /* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */
3608 #define IWM_RATE_MCS_SGI_POS 13
3609 #define IWM_RATE_MCS_SGI_MSK (1 << IWM_RATE_MCS_SGI_POS)
3611 /* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C */
3612 #define IWM_RATE_MCS_ANT_POS 14
3613 #define IWM_RATE_MCS_ANT_A_MSK (1 << IWM_RATE_MCS_ANT_POS)
3614 #define IWM_RATE_MCS_ANT_B_MSK (2 << IWM_RATE_MCS_ANT_POS)
3615 #define IWM_RATE_MCS_ANT_C_MSK (4 << IWM_RATE_MCS_ANT_POS)
3616 #define IWM_RATE_MCS_ANT_AB_MSK (IWM_RATE_MCS_ANT_A_MSK | \
3617 IWM_RATE_MCS_ANT_B_MSK)
3618 #define IWM_RATE_MCS_ANT_ABC_MSK (IWM_RATE_MCS_ANT_AB_MSK | \
3619 IWM_RATE_MCS_ANT_C_MSK)
3620 #define IWM_RATE_MCS_ANT_MSK IWM_RATE_MCS_ANT_ABC_MSK
3621 #define IWM_RATE_MCS_ANT_NUM 3
3623 /* Bit 17-18: (0) SS, (1) SS*2 */
3624 #define IWM_RATE_MCS_STBC_POS 17
3625 #define IWM_RATE_MCS_STBC_MSK (1 << IWM_RATE_MCS_STBC_POS)
3627 /* Bit 19: (0) Beamforming is off, (1) Beamforming is on */
3628 #define IWM_RATE_MCS_BF_POS 19
3629 #define IWM_RATE_MCS_BF_MSK (1 << IWM_RATE_MCS_BF_POS)
3631 /* Bit 20: (0) ZLF is off, (1) ZLF is on */
3632 #define IWM_RATE_MCS_ZLF_POS 20
3633 #define IWM_RATE_MCS_ZLF_MSK (1 << IWM_RATE_MCS_ZLF_POS)
3635 /* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */
3636 #define IWM_RATE_MCS_DUP_POS 24
3637 #define IWM_RATE_MCS_DUP_MSK (3 << IWM_RATE_MCS_DUP_POS)
3639 /* Bit 27: (1) LDPC enabled, (0) LDPC disabled */
3640 #define IWM_RATE_MCS_LDPC_POS 27
3641 #define IWM_RATE_MCS_LDPC_MSK (1 << IWM_RATE_MCS_LDPC_POS)
3644 /* Link Quality definitions */
3646 /* # entries in rate scale table to support Tx retries */
3647 #define IWM_LQ_MAX_RETRY_NUM 16
3649 /* Link quality command flags bit fields */
3651 /* Bit 0: (0) Don't use RTS (1) Use RTS */
3652 #define IWM_LQ_FLAG_USE_RTS_POS 0
3653 #define IWM_LQ_FLAG_USE_RTS_MSK (1 << IWM_LQ_FLAG_USE_RTS_POS)
3655 /* Bit 1-3: LQ command color. Used to match responses to LQ commands */
3656 #define IWM_LQ_FLAG_COLOR_POS 1
3657 #define IWM_LQ_FLAG_COLOR_MSK (7 << IWM_LQ_FLAG_COLOR_POS)
3659 /* Bit 4-5: Tx RTS BW Signalling
3660 * (0) No RTS BW signalling
3661 * (1) Static BW signalling
3662 * (2) Dynamic BW signalling
3664 #define IWM_LQ_FLAG_RTS_BW_SIG_POS 4
3665 #define IWM_LQ_FLAG_RTS_BW_SIG_NONE (0 << IWM_LQ_FLAG_RTS_BW_SIG_POS)
3666 #define IWM_LQ_FLAG_RTS_BW_SIG_STATIC (1 << IWM_LQ_FLAG_RTS_BW_SIG_POS)
3667 #define IWM_LQ_FLAG_RTS_BW_SIG_DYNAMIC (2 << IWM_LQ_FLAG_RTS_BW_SIG_POS)
3669 /* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection
3670 * Dyanmic BW selection allows Tx with narrower BW then requested in rates
3672 #define IWM_LQ_FLAG_DYNAMIC_BW_POS 6
3673 #define IWM_LQ_FLAG_DYNAMIC_BW_MSK (1 << IWM_LQ_FLAG_DYNAMIC_BW_POS)
3676 * struct iwm_lq_cmd - link quality command
3677 * @sta_id: station to update
3678 * @control: not used
3679 * @flags: combination of IWM_LQ_FLAG_*
3680 * @mimo_delim: the first SISO index in rs_table, which separates MIMO
3682 * @single_stream_ant_msk: best antenna for SISO (can be dual in CDD).
3683 * Should be ANT_[ABC]
3684 * @dual_stream_ant_msk: best antennas for MIMO, combination of ANT_[ABC]
3685 * @initial_rate_index: first index from rs_table per AC category
3686 * @agg_time_limit: aggregation max time threshold in usec/100, meaning
3687 * value of 100 is one usec. Range is 100 to 8000
3688 * @agg_disable_start_th: try-count threshold for starting aggregation.
3689 * If a frame has higher try-count, it should not be selected for
3690 * starting an aggregation sequence.
3691 * @agg_frame_cnt_limit: max frame count in an aggregation.
3693 * 1: no aggregation (one frame per aggregation)
3694 * 2 - 0x3f: maximal number of frames (up to 3f == 63)
3695 * @rs_table: array of rates for each TX try, each is rate_n_flags,
3696 * meaning it is a combination of IWM_RATE_MCS_* and IWM_RATE_*_PLCP
3697 * @bf_params: beam forming params, currently not used
3703 /* LINK_QUAL_GENERAL_PARAMS_API_S_VER_1 */
3706 uint8_t single_stream_ant_msk;
3707 uint8_t dual_stream_ant_msk;
3708 uint8_t initial_rate_index[IWM_AC_NUM];
3709 /* LINK_QUAL_AGG_PARAMS_API_S_VER_1 */
3710 uint16_t agg_time_limit;
3711 uint8_t agg_disable_start_th;
3712 uint8_t agg_frame_cnt_limit;
3714 uint32_t rs_table[IWM_LQ_MAX_RETRY_NUM];
3716 }; /* LINK_QUALITY_CMD_API_S_VER_1 */
3719 * enum iwm_tx_flags - bitmasks for tx_flags in TX command
3720 * @IWM_TX_CMD_FLG_PROT_REQUIRE: use RTS or CTS-to-self to protect the frame
3721 * @IWM_TX_CMD_FLG_ACK: expect ACK from receiving station
3722 * @IWM_TX_CMD_FLG_STA_RATE: use RS table with initial index from the TX command.
3723 * Otherwise, use rate_n_flags from the TX command
3724 * @IWM_TX_CMD_FLG_BA: this frame is a block ack
3725 * @IWM_TX_CMD_FLG_BAR: this frame is a BA request, immediate BAR is expected
3726 * Must set IWM_TX_CMD_FLG_ACK with this flag.
3727 * @IWM_TX_CMD_FLG_TXOP_PROT: protect frame with full TXOP protection
3728 * @IWM_TX_CMD_FLG_VHT_NDPA: mark frame is NDPA for VHT beamformer sequence
3729 * @IWM_TX_CMD_FLG_HT_NDPA: mark frame is NDPA for HT beamformer sequence
3730 * @IWM_TX_CMD_FLG_CSI_FDBK2HOST: mark to send feedback to host (only if good CRC)
3731 * @IWM_TX_CMD_FLG_BT_DIS: disable BT priority for this frame
3732 * @IWM_TX_CMD_FLG_SEQ_CTL: set if FW should override the sequence control.
3733 * Should be set for mgmt, non-QOS data, mcast, bcast and in scan command
3734 * @IWM_TX_CMD_FLG_MORE_FRAG: this frame is non-last MPDU
3735 * @IWM_TX_CMD_FLG_NEXT_FRAME: this frame includes information of the next frame
3736 * @IWM_TX_CMD_FLG_TSF: FW should calculate and insert TSF in the frame
3737 * Should be set for beacons and probe responses
3738 * @IWM_TX_CMD_FLG_CALIB: activate PA TX power calibrations
3739 * @IWM_TX_CMD_FLG_KEEP_SEQ_CTL: if seq_ctl is set, don't increase inner seq count
3740 * @IWM_TX_CMD_FLG_AGG_START: allow this frame to start aggregation
3741 * @IWM_TX_CMD_FLG_MH_PAD: driver inserted 2 byte padding after MAC header.
3742 * Should be set for 26/30 length MAC headers
3743 * @IWM_TX_CMD_FLG_RESP_TO_DRV: zero this if the response should go only to FW
3744 * @IWM_TX_CMD_FLG_CCMP_AGG: this frame uses CCMP for aggregation acceleration
3745 * @IWM_TX_CMD_FLG_TKIP_MIC_DONE: FW already performed TKIP MIC calculation
3746 * @IWM_TX_CMD_FLG_DUR: disable duration overwriting used in PS-Poll Assoc-id
3747 * @IWM_TX_CMD_FLG_FW_DROP: FW should mark frame to be dropped
3748 * @IWM_TX_CMD_FLG_EXEC_PAPD: execute PAPD
3749 * @IWM_TX_CMD_FLG_PAPD_TYPE: 0 for reference power, 1 for nominal power
3750 * @IWM_TX_CMD_FLG_HCCA_CHUNK: mark start of TSPEC chunk
3753 IWM_TX_CMD_FLG_PROT_REQUIRE = (1 << 0),
3754 IWM_TX_CMD_FLG_ACK = (1 << 3),
3755 IWM_TX_CMD_FLG_STA_RATE = (1 << 4),
3756 IWM_TX_CMD_FLG_BA = (1 << 5),
3757 IWM_TX_CMD_FLG_BAR = (1 << 6),
3758 IWM_TX_CMD_FLG_TXOP_PROT = (1 << 7),
3759 IWM_TX_CMD_FLG_VHT_NDPA = (1 << 8),
3760 IWM_TX_CMD_FLG_HT_NDPA = (1 << 9),
3761 IWM_TX_CMD_FLG_CSI_FDBK2HOST = (1 << 10),
3762 IWM_TX_CMD_FLG_BT_DIS = (1 << 12),
3763 IWM_TX_CMD_FLG_SEQ_CTL = (1 << 13),
3764 IWM_TX_CMD_FLG_MORE_FRAG = (1 << 14),
3765 IWM_TX_CMD_FLG_NEXT_FRAME = (1 << 15),
3766 IWM_TX_CMD_FLG_TSF = (1 << 16),
3767 IWM_TX_CMD_FLG_CALIB = (1 << 17),
3768 IWM_TX_CMD_FLG_KEEP_SEQ_CTL = (1 << 18),
3769 IWM_TX_CMD_FLG_AGG_START = (1 << 19),
3770 IWM_TX_CMD_FLG_MH_PAD = (1 << 20),
3771 IWM_TX_CMD_FLG_RESP_TO_DRV = (1 << 21),
3772 IWM_TX_CMD_FLG_CCMP_AGG = (1 << 22),
3773 IWM_TX_CMD_FLG_TKIP_MIC_DONE = (1 << 23),
3774 IWM_TX_CMD_FLG_DUR = (1 << 25),
3775 IWM_TX_CMD_FLG_FW_DROP = (1 << 26),
3776 IWM_TX_CMD_FLG_EXEC_PAPD = (1 << 27),
3777 IWM_TX_CMD_FLG_PAPD_TYPE = (1 << 28),
3778 IWM_TX_CMD_FLG_HCCA_CHUNK = (1 << 31)
3779 }; /* IWM_TX_FLAGS_BITS_API_S_VER_1 */
3782 * TX command security control
3784 #define IWM_TX_CMD_SEC_WEP 0x01
3785 #define IWM_TX_CMD_SEC_CCM 0x02
3786 #define IWM_TX_CMD_SEC_TKIP 0x03
3787 #define IWM_TX_CMD_SEC_EXT 0x04
3788 #define IWM_TX_CMD_SEC_MSK 0x07
3789 #define IWM_TX_CMD_SEC_WEP_KEY_IDX_POS 6
3790 #define IWM_TX_CMD_SEC_WEP_KEY_IDX_MSK 0xc0
3791 #define IWM_TX_CMD_SEC_KEY128 0x08
3793 /* TODO: how does these values are OK with only 16 bit variable??? */
3795 * TX command next frame info
3797 * bits 0:2 - security control (IWM_TX_CMD_SEC_*)
3798 * bit 3 - immediate ACK required
3799 * bit 4 - rate is taken from STA table
3800 * bit 5 - frame belongs to BA stream
3801 * bit 6 - immediate BA response expected
3803 * bits 8:15 - Station ID
3806 #define IWM_TX_CMD_NEXT_FRAME_ACK_MSK (0x8)
3807 #define IWM_TX_CMD_NEXT_FRAME_STA_RATE_MSK (0x10)
3808 #define IWM_TX_CMD_NEXT_FRAME_BA_MSK (0x20)
3809 #define IWM_TX_CMD_NEXT_FRAME_IMM_BA_RSP_MSK (0x40)
3810 #define IWM_TX_CMD_NEXT_FRAME_FLAGS_MSK (0xf8)
3811 #define IWM_TX_CMD_NEXT_FRAME_STA_ID_MSK (0xff00)
3812 #define IWM_TX_CMD_NEXT_FRAME_STA_ID_POS (8)
3813 #define IWM_TX_CMD_NEXT_FRAME_RATE_MSK (0xffff0000)
3814 #define IWM_TX_CMD_NEXT_FRAME_RATE_POS (16)
3817 * TX command Frame life time in us - to be written in pm_frame_timeout
3819 #define IWM_TX_CMD_LIFE_TIME_INFINITE 0xFFFFFFFF
3820 #define IWM_TX_CMD_LIFE_TIME_DEFAULT 2000000 /* 2000 ms*/
3821 #define IWM_TX_CMD_LIFE_TIME_PROBE_RESP 40000 /* 40 ms */
3822 #define IWM_TX_CMD_LIFE_TIME_EXPIRED_FRAME 0
3825 * TID for non QoS frames - to be written in tid_tspec
3827 #define IWM_TID_NON_QOS IWM_MAX_TID_COUNT
3830 * Limits on the retransmissions - to be written in {data,rts}_retry_limit
3832 #define IWM_DEFAULT_TX_RETRY 15
3833 #define IWM_MGMT_DFAULT_RETRY_LIMIT 3
3834 #define IWM_RTS_DFAULT_RETRY_LIMIT 60
3835 #define IWM_BAR_DFAULT_RETRY_LIMIT 60
3836 #define IWM_LOW_RETRY_LIMIT 7
3838 /* TODO: complete documentation for try_cnt and btkill_cnt */
3840 * struct iwm_tx_cmd - TX command struct to FW
3841 * ( IWM_TX_CMD = 0x1c )
3842 * @len: in bytes of the payload, see below for details
3843 * @next_frame_len: same as len, but for next frame (0 if not applicable)
3844 * Used for fragmentation and bursting, but not in 11n aggregation.
3845 * @tx_flags: combination of IWM_TX_CMD_FLG_*
3846 * @rate_n_flags: rate for *all* Tx attempts, if IWM_TX_CMD_FLG_STA_RATE_MSK is
3847 * cleared. Combination of IWM_RATE_MCS_*
3848 * @sta_id: index of destination station in FW station table
3849 * @sec_ctl: security control, IWM_TX_CMD_SEC_*
3850 * @initial_rate_index: index into the the rate table for initial TX attempt.
3851 * Applied if IWM_TX_CMD_FLG_STA_RATE_MSK is set, normally 0 for data frames.
3852 * @key: security key
3853 * @next_frame_flags: IWM_TX_CMD_SEC_* and IWM_TX_CMD_NEXT_FRAME_*
3854 * @life_time: frame life time (usecs??)
3855 * @dram_lsb_ptr: Physical address of scratch area in the command (try_cnt +
3856 * btkill_cnd + reserved), first 32 bits. "0" disables usage.
3857 * @dram_msb_ptr: upper bits of the scratch physical address
3858 * @rts_retry_limit: max attempts for RTS
3859 * @data_retry_limit: max attempts to send the data packet
3860 * @tid_spec: TID/tspec
3861 * @pm_frame_timeout: PM TX frame timeout
3862 * @driver_txop: duration od EDCA TXOP, in 32-usec units. Set this if not
3863 * specified by HCCA protocol
3865 * The byte count (both len and next_frame_len) includes MAC header
3866 * (24/26/30/32 bytes)
3867 * + 2 bytes pad if 26/30 header size
3868 * + 8 byte IV for CCM or TKIP (not used for WEP)
3870 * + 8-byte MIC (not used for CCM/WEP)
3871 * It does not include post-MAC padding, i.e.,
3872 * MIC (CCM) 8 bytes, ICV (WEP/TKIP/CKIP) 4 bytes, CRC 4 bytes.
3873 * Range of len: 14-2342 bytes.
3875 * After the struct fields the MAC header is placed, plus any padding,
3876 * and then the actial payload.
3880 uint16_t next_frame_len;
3886 } scratch; /* DRAM_SCRATCH_API_U_VER_1 */
3887 uint32_t rate_n_flags;
3890 uint8_t initial_rate_index;
3893 uint16_t next_frame_flags;
3896 uint32_t dram_lsb_ptr;
3897 uint8_t dram_msb_ptr;
3898 uint8_t rts_retry_limit;
3899 uint8_t data_retry_limit;
3901 uint16_t pm_frame_timeout;
3902 uint16_t driver_txop;
3904 struct ieee80211_frame hdr[0];
3905 } __packed; /* IWM_TX_CMD_API_S_VER_3 */
3908 * TX response related data
3912 * enum iwm_tx_status - status that is returned by the fw after attempts to Tx
3913 * @IWM_TX_STATUS_SUCCESS:
3914 * @IWM_TX_STATUS_DIRECT_DONE:
3915 * @IWM_TX_STATUS_POSTPONE_DELAY:
3916 * @IWM_TX_STATUS_POSTPONE_FEW_BYTES:
3917 * @IWM_TX_STATUS_POSTPONE_BT_PRIO:
3918 * @IWM_TX_STATUS_POSTPONE_QUIET_PERIOD:
3919 * @IWM_TX_STATUS_POSTPONE_CALC_TTAK:
3920 * @IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY:
3921 * @IWM_TX_STATUS_FAIL_SHORT_LIMIT:
3922 * @IWM_TX_STATUS_FAIL_LONG_LIMIT:
3923 * @IWM_TX_STATUS_FAIL_UNDERRUN:
3924 * @IWM_TX_STATUS_FAIL_DRAIN_FLOW:
3925 * @IWM_TX_STATUS_FAIL_RFKILL_FLUSH:
3926 * @IWM_TX_STATUS_FAIL_LIFE_EXPIRE:
3927 * @IWM_TX_STATUS_FAIL_DEST_PS:
3928 * @IWM_TX_STATUS_FAIL_HOST_ABORTED:
3929 * @IWM_TX_STATUS_FAIL_BT_RETRY:
3930 * @IWM_TX_STATUS_FAIL_STA_INVALID:
3931 * @IWM_TX_TATUS_FAIL_FRAG_DROPPED:
3932 * @IWM_TX_STATUS_FAIL_TID_DISABLE:
3933 * @IWM_TX_STATUS_FAIL_FIFO_FLUSHED:
3934 * @IWM_TX_STATUS_FAIL_SMALL_CF_POLL:
3935 * @IWM_TX_STATUS_FAIL_FW_DROP:
3936 * @IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH: mismatch between color of Tx cmd and
3938 * @IWM_TX_FRAME_STATUS_INTERNAL_ABORT:
3940 * @IWM_TX_MODE_NO_BURST:
3941 * @IWM_TX_MODE_IN_BURST_SEQ:
3942 * @IWM_TX_MODE_FIRST_IN_BURST:
3943 * @IWM_TX_QUEUE_NUM_MSK:
3945 * Valid only if frame_count =1
3946 * TODO: complete documentation
3948 enum iwm_tx_status {
3949 IWM_TX_STATUS_MSK = 0x000000ff,
3950 IWM_TX_STATUS_SUCCESS = 0x01,
3951 IWM_TX_STATUS_DIRECT_DONE = 0x02,
3953 IWM_TX_STATUS_POSTPONE_DELAY = 0x40,
3954 IWM_TX_STATUS_POSTPONE_FEW_BYTES = 0x41,
3955 IWM_TX_STATUS_POSTPONE_BT_PRIO = 0x42,
3956 IWM_TX_STATUS_POSTPONE_QUIET_PERIOD = 0x43,
3957 IWM_TX_STATUS_POSTPONE_CALC_TTAK = 0x44,
3959 IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY = 0x81,
3960 IWM_TX_STATUS_FAIL_SHORT_LIMIT = 0x82,
3961 IWM_TX_STATUS_FAIL_LONG_LIMIT = 0x83,
3962 IWM_TX_STATUS_FAIL_UNDERRUN = 0x84,
3963 IWM_TX_STATUS_FAIL_DRAIN_FLOW = 0x85,
3964 IWM_TX_STATUS_FAIL_RFKILL_FLUSH = 0x86,
3965 IWM_TX_STATUS_FAIL_LIFE_EXPIRE = 0x87,
3966 IWM_TX_STATUS_FAIL_DEST_PS = 0x88,
3967 IWM_TX_STATUS_FAIL_HOST_ABORTED = 0x89,
3968 IWM_TX_STATUS_FAIL_BT_RETRY = 0x8a,
3969 IWM_TX_STATUS_FAIL_STA_INVALID = 0x8b,
3970 IWM_TX_STATUS_FAIL_FRAG_DROPPED = 0x8c,
3971 IWM_TX_STATUS_FAIL_TID_DISABLE = 0x8d,
3972 IWM_TX_STATUS_FAIL_FIFO_FLUSHED = 0x8e,
3973 IWM_TX_STATUS_FAIL_SMALL_CF_POLL = 0x8f,
3974 IWM_TX_STATUS_FAIL_FW_DROP = 0x90,
3975 IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH = 0x91,
3976 IWM_TX_STATUS_INTERNAL_ABORT = 0x92,
3977 IWM_TX_MODE_MSK = 0x00000f00,
3978 IWM_TX_MODE_NO_BURST = 0x00000000,
3979 IWM_TX_MODE_IN_BURST_SEQ = 0x00000100,
3980 IWM_TX_MODE_FIRST_IN_BURST = 0x00000200,
3981 IWM_TX_QUEUE_NUM_MSK = 0x0001f000,
3982 IWM_TX_NARROW_BW_MSK = 0x00060000,
3983 IWM_TX_NARROW_BW_1DIV2 = 0x00020000,
3984 IWM_TX_NARROW_BW_1DIV4 = 0x00040000,
3985 IWM_TX_NARROW_BW_1DIV8 = 0x00060000,
3989 * enum iwm_tx_agg_status - TX aggregation status
3990 * @IWM_AGG_TX_STATE_STATUS_MSK:
3991 * @IWM_AGG_TX_STATE_TRANSMITTED:
3992 * @IWM_AGG_TX_STATE_UNDERRUN:
3993 * @IWM_AGG_TX_STATE_BT_PRIO:
3994 * @IWM_AGG_TX_STATE_FEW_BYTES:
3995 * @IWM_AGG_TX_STATE_ABORT:
3996 * @IWM_AGG_TX_STATE_LAST_SENT_TTL:
3997 * @IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT:
3998 * @IWM_AGG_TX_STATE_LAST_SENT_BT_KILL:
3999 * @IWM_AGG_TX_STATE_SCD_QUERY:
4000 * @IWM_AGG_TX_STATE_TEST_BAD_CRC32:
4001 * @IWM_AGG_TX_STATE_RESPONSE:
4002 * @IWM_AGG_TX_STATE_DUMP_TX:
4003 * @IWM_AGG_TX_STATE_DELAY_TX:
4004 * @IWM_AGG_TX_STATE_TRY_CNT_MSK: Retry count for 1st frame in aggregation (retries
4005 * occur if tx failed for this frame when it was a member of a previous
4006 * aggregation block). If rate scaling is used, retry count indicates the
4007 * rate table entry used for all frames in the new agg.
4008 *@ IWM_AGG_TX_STATE_SEQ_NUM_MSK: Command ID and sequence number of Tx command for
4011 * TODO: complete documentation
4013 enum iwm_tx_agg_status {
4014 IWM_AGG_TX_STATE_STATUS_MSK = 0x00fff,
4015 IWM_AGG_TX_STATE_TRANSMITTED = 0x000,
4016 IWM_AGG_TX_STATE_UNDERRUN = 0x001,
4017 IWM_AGG_TX_STATE_BT_PRIO = 0x002,
4018 IWM_AGG_TX_STATE_FEW_BYTES = 0x004,
4019 IWM_AGG_TX_STATE_ABORT = 0x008,
4020 IWM_AGG_TX_STATE_LAST_SENT_TTL = 0x010,
4021 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT = 0x020,
4022 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL = 0x040,
4023 IWM_AGG_TX_STATE_SCD_QUERY = 0x080,
4024 IWM_AGG_TX_STATE_TEST_BAD_CRC32 = 0x0100,
4025 IWM_AGG_TX_STATE_RESPONSE = 0x1ff,
4026 IWM_AGG_TX_STATE_DUMP_TX = 0x200,
4027 IWM_AGG_TX_STATE_DELAY_TX = 0x400,
4028 IWM_AGG_TX_STATE_TRY_CNT_POS = 12,
4029 IWM_AGG_TX_STATE_TRY_CNT_MSK = 0xf << IWM_AGG_TX_STATE_TRY_CNT_POS,
4032 #define IWM_AGG_TX_STATE_LAST_SENT_MSK (IWM_AGG_TX_STATE_LAST_SENT_TTL| \
4033 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT| \
4034 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL)
4037 * The mask below describes a status where we are absolutely sure that the MPDU
4038 * wasn't sent. For BA/Underrun we cannot be that sure. All we know that we've
4039 * written the bytes to the TXE, but we know nothing about what the DSP did.
4041 #define IWM_AGG_TX_STAT_FRAME_NOT_SENT (IWM_AGG_TX_STATE_FEW_BYTES | \
4042 IWM_AGG_TX_STATE_ABORT | \
4043 IWM_AGG_TX_STATE_SCD_QUERY)
4046 * IWM_REPLY_TX = 0x1c (response)
4048 * This response may be in one of two slightly different formats, indicated
4049 * by the frame_count field:
4051 * 1) No aggregation (frame_count == 1). This reports Tx results for a single
4052 * frame. Multiple attempts, at various bit rates, may have been made for
4055 * 2) Aggregation (frame_count > 1). This reports Tx results for two or more
4056 * frames that used block-acknowledge. All frames were transmitted at
4057 * same rate. Rate scaling may have been used if first frame in this new
4058 * agg block failed in previous agg block(s).
4060 * Note that, for aggregation, ACK (block-ack) status is not delivered
4061 * here; block-ack has not been received by the time the device records
4063 * This status relates to reasons the tx might have been blocked or aborted
4064 * within the device, rather than whether it was received successfully by
4065 * the destination station.
4069 * struct iwm_agg_tx_status - per packet TX aggregation status
4070 * @status: enum iwm_tx_agg_status
4071 * @sequence: Sequence # for this frame's Tx cmd (not SSN!)
4073 struct iwm_agg_tx_status {
4079 * definitions for initial rate index field
4080 * bits [3:0] initial rate index
4081 * bits [6:4] rate table color, used for the initial rate
4082 * bit-7 invalid rate indication
4084 #define IWM_TX_RES_INIT_RATE_INDEX_MSK 0x0f
4085 #define IWM_TX_RES_RATE_TABLE_COLOR_MSK 0x70
4086 #define IWM_TX_RES_INV_RATE_INDEX_MSK 0x80
4088 #define IWM_MVM_TX_RES_GET_TID(_ra_tid) ((_ra_tid) & 0x0f)
4089 #define IWM_MVM_TX_RES_GET_RA(_ra_tid) ((_ra_tid) >> 4)
4092 * struct iwm_mvm_tx_resp - notifies that fw is TXing a packet
4093 * ( IWM_REPLY_TX = 0x1c )
4094 * @frame_count: 1 no aggregation, >1 aggregation
4095 * @bt_kill_count: num of times blocked by bluetooth (unused for agg)
4096 * @failure_rts: num of failures due to unsuccessful RTS
4097 * @failure_frame: num failures due to no ACK (unused for agg)
4098 * @initial_rate: for non-agg: rate of the successful Tx. For agg: rate of the
4099 * Tx of all the batch. IWM_RATE_MCS_*
4100 * @wireless_media_time: for non-agg: RTS + CTS + frame tx attempts time + ACK.
4101 * for agg: RTS + CTS + aggregation tx time + block-ack time.
4103 * @pa_status: tx power info
4104 * @pa_integ_res_a: tx power info
4105 * @pa_integ_res_b: tx power info
4106 * @pa_integ_res_c: tx power info
4107 * @measurement_req_id: tx power info
4108 * @tfd_info: TFD information set by the FH
4109 * @seq_ctl: sequence control from the Tx cmd
4110 * @byte_cnt: byte count from the Tx cmd
4111 * @tlc_info: TLC rate info
4112 * @ra_tid: bits [3:0] = ra, bits [7:4] = tid
4113 * @frame_ctrl: frame control
4114 * @status: for non-agg: frame status IWM_TX_STATUS_*
4115 * for agg: status of 1st frame, IWM_AGG_TX_STATE_*; other frame status fields
4116 * follow this one, up to frame_count.
4118 * After the array of statuses comes the SSN of the SCD. Look at
4119 * %iwm_mvm_get_scd_ssn for more details.
4121 struct iwm_mvm_tx_resp {
4122 uint8_t frame_count;
4123 uint8_t bt_kill_count;
4124 uint8_t failure_rts;
4125 uint8_t failure_frame;
4126 uint32_t initial_rate;
4127 uint16_t wireless_media_time;
4130 uint8_t pa_integ_res_a[3];
4131 uint8_t pa_integ_res_b[3];
4132 uint8_t pa_integ_res_c[3];
4133 uint16_t measurement_req_id;
4141 uint16_t frame_ctrl;
4143 struct iwm_agg_tx_status status;
4144 } __packed; /* IWM_TX_RSP_API_S_VER_3 */
4147 * struct iwm_mvm_ba_notif - notifies about reception of BA
4148 * ( IWM_BA_NOTIF = 0xc5 )
4149 * @sta_addr_lo32: lower 32 bits of the MAC address
4150 * @sta_addr_hi16: upper 16 bits of the MAC address
4151 * @sta_id: Index of recipient (BA-sending) station in fw's station table
4152 * @tid: tid of the session
4154 * @bitmap: the bitmap of the BA notification as seen in the air
4155 * @scd_flow: the tx queue this BA relates to
4156 * @scd_ssn: the index of the last contiguously sent packet
4157 * @txed: number of Txed frames in this batch
4158 * @txed_2_done: number of Acked frames in this batch
4160 struct iwm_mvm_ba_notif {
4161 uint32_t sta_addr_lo32;
4162 uint16_t sta_addr_hi16;
4172 uint8_t txed_2_done;
4177 * struct iwm_mac_beacon_cmd - beacon template command
4178 * @tx: the tx commands associated with the beacon frame
4179 * @template_id: currently equal to the mac context id of the coresponding
4181 * @tim_idx: the offset of the tim IE in the beacon
4182 * @tim_size: the length of the tim IE
4183 * @frame: the template of the beacon frame
4185 struct iwm_mac_beacon_cmd {
4186 struct iwm_tx_cmd tx;
4187 uint32_t template_id;
4190 struct ieee80211_frame frame[0];
4193 struct iwm_beacon_notif {
4194 struct iwm_mvm_tx_resp beacon_notify_hdr;
4196 uint32_t ibss_mgr_status;
4200 * enum iwm_dump_control - dump (flush) control flags
4201 * @IWM_DUMP_TX_FIFO_FLUSH: Dump MSDUs until the the FIFO is empty
4202 * and the TFD queues are empty.
4204 enum iwm_dump_control {
4205 IWM_DUMP_TX_FIFO_FLUSH = (1 << 1),
4209 * struct iwm_tx_path_flush_cmd -- queue/FIFO flush command
4210 * @queues_ctl: bitmap of queues to flush
4211 * @flush_ctl: control flags
4212 * @reserved: reserved
4214 struct iwm_tx_path_flush_cmd {
4215 uint32_t queues_ctl;
4218 } __packed; /* IWM_TX_PATH_FLUSH_CMD_API_S_VER_1 */
4221 * iwm_mvm_get_scd_ssn - returns the SSN of the SCD
4222 * @tx_resp: the Tx response from the fw (agg or non-agg)
4224 * When the fw sends an AMPDU, it fetches the MPDUs one after the other. Since
4225 * it can't know that everything will go well until the end of the AMPDU, it
4226 * can't know in advance the number of MPDUs that will be sent in the current
4227 * batch. This is why it writes the agg Tx response while it fetches the MPDUs.
4228 * Hence, it can't know in advance what the SSN of the SCD will be at the end
4229 * of the batch. This is why the SSN of the SCD is written at the end of the
4230 * whole struct at a variable offset. This function knows how to cope with the
4231 * variable offset and returns the SSN of the SCD.
4233 static inline uint32_t iwm_mvm_get_scd_ssn(struct iwm_mvm_tx_resp *tx_resp)
4235 return le32_to_cpup((uint32_t *)&tx_resp->status +
4236 tx_resp->frame_count) & 0xfff;
4239 /* Scan Commands, Responses, Notifications */
4241 /* Masks for iwm_scan_channel.type flags */
4242 #define IWM_SCAN_CHANNEL_TYPE_ACTIVE (1 << 0)
4243 #define IWM_SCAN_CHANNEL_NARROW_BAND (1 << 22)
4245 /* Max number of IEs for direct SSID scans in a command */
4246 #define IWM_PROBE_OPTION_MAX 20
4249 * struct iwm_scan_channel - entry in IWM_REPLY_SCAN_CMD channel table
4250 * @channel: band is selected by iwm_scan_cmd "flags" field
4251 * @tx_gain: gain for analog radio
4252 * @dsp_atten: gain for DSP
4253 * @active_dwell: dwell time for active scan in TU, typically 5-50
4254 * @passive_dwell: dwell time for passive scan in TU, typically 20-500
4255 * @type: type is broken down to these bits:
4256 * bit 0: 0 = passive, 1 = active
4257 * bits 1-20: SSID direct bit map. If any of these bits is set then
4258 * the corresponding SSID IE is transmitted in probe request
4259 * (bit i adds IE in position i to the probe request)
4260 * bit 22: channel width, 0 = regular, 1 = TGj narrow channel
4263 * @iteration_interval:
4264 * This struct is used once for each channel in the scan list.
4265 * Each channel can independently select:
4266 * 1) SSID for directed active scans
4267 * 2) Txpower setting (for rate specified within Tx command)
4268 * 3) How long to stay on-channel (behavior may be modified by quiet_time,
4269 * quiet_plcp_th, good_CRC_th)
4271 * To avoid uCode errors, make sure the following are true (see comments
4272 * under struct iwm_scan_cmd about max_out_time and quiet_time):
4273 * 1) If using passive_dwell (i.e. passive_dwell != 0):
4274 * active_dwell <= passive_dwell (< max_out_time if max_out_time != 0)
4275 * 2) quiet_time <= active_dwell
4276 * 3) If restricting off-channel time (i.e. max_out_time !=0):
4277 * passive_dwell < max_out_time
4278 * active_dwell < max_out_time
4280 struct iwm_scan_channel {
4283 uint16_t iteration_count;
4284 uint32_t iteration_interval;
4285 uint16_t active_dwell;
4286 uint16_t passive_dwell;
4287 } __packed; /* IWM_SCAN_CHANNEL_CONTROL_API_S_VER_1 */
4290 * struct iwm_ssid_ie - directed scan network information element
4292 * Up to 20 of these may appear in IWM_REPLY_SCAN_CMD,
4293 * selected by "type" bit field in struct iwm_scan_channel;
4294 * each channel may select different ssids from among the 20 entries.
4295 * SSID IEs get transmitted in reverse order of entry.
4297 struct iwm_ssid_ie {
4300 uint8_t ssid[IEEE80211_NWID_LEN];
4301 } __packed; /* IWM_SCAN_DIRECT_SSID_IE_API_S_VER_1 */
4304 * iwm_scan_flags - masks for scan command flags
4305 *@IWM_SCAN_FLAGS_PERIODIC_SCAN:
4306 *@IWM_SCAN_FLAGS_P2P_PUBLIC_ACTION_FRAME_TX:
4307 *@IWM_SCAN_FLAGS_DELAYED_SCAN_LOWBAND:
4308 *@IWM_SCAN_FLAGS_DELAYED_SCAN_HIGHBAND:
4309 *@IWM_SCAN_FLAGS_FRAGMENTED_SCAN:
4310 *@IWM_SCAN_FLAGS_PASSIVE2ACTIVE: use active scan on channels that was active
4311 * in the past hour, even if they are marked as passive.
4313 enum iwm_scan_flags {
4314 IWM_SCAN_FLAGS_PERIODIC_SCAN = (1 << 0),
4315 IWM_SCAN_FLAGS_P2P_PUBLIC_ACTION_FRAME_TX = (1 << 1),
4316 IWM_SCAN_FLAGS_DELAYED_SCAN_LOWBAND = (1 << 2),
4317 IWM_SCAN_FLAGS_DELAYED_SCAN_HIGHBAND = (1 << 3),
4318 IWM_SCAN_FLAGS_FRAGMENTED_SCAN = (1 << 4),
4319 IWM_SCAN_FLAGS_PASSIVE2ACTIVE = (1 << 5),
4323 * enum iwm_scan_type - Scan types for scan command
4324 * @IWM_SCAN_TYPE_FORCED:
4325 * @IWM_SCAN_TYPE_BACKGROUND:
4326 * @IWM_SCAN_TYPE_OS:
4327 * @IWM_SCAN_TYPE_ROAMING:
4328 * @IWM_SCAN_TYPE_ACTION:
4329 * @IWM_SCAN_TYPE_DISCOVERY:
4330 * @IWM_SCAN_TYPE_DISCOVERY_FORCED:
4332 enum iwm_scan_type {
4333 IWM_SCAN_TYPE_FORCED = 0,
4334 IWM_SCAN_TYPE_BACKGROUND = 1,
4335 IWM_SCAN_TYPE_OS = 2,
4336 IWM_SCAN_TYPE_ROAMING = 3,
4337 IWM_SCAN_TYPE_ACTION = 4,
4338 IWM_SCAN_TYPE_DISCOVERY = 5,
4339 IWM_SCAN_TYPE_DISCOVERY_FORCED = 6,
4340 }; /* IWM_SCAN_ACTIVITY_TYPE_E_VER_1 */
4342 /* Maximal number of channels to scan */
4343 #define IWM_MAX_NUM_SCAN_CHANNELS 0x24
4346 * struct iwm_scan_cmd - scan request command
4347 * ( IWM_SCAN_REQUEST_CMD = 0x80 )
4348 * @len: command length in bytes
4349 * @scan_flags: scan flags from IWM_SCAN_FLAGS_*
4350 * @channel_count: num of channels in channel list (1 - IWM_MAX_NUM_SCAN_CHANNELS)
4351 * @quiet_time: in msecs, dwell this time for active scan on quiet channels
4352 * @quiet_plcp_th: quiet PLCP threshold (channel is quiet if less than
4353 * this number of packets were received (typically 1)
4354 * @passive2active: is auto switching from passive to active during scan allowed
4355 * @rxchain_sel_flags: RXON_RX_CHAIN_*
4356 * @max_out_time: in usecs, max out of serving channel time
4357 * @suspend_time: how long to pause scan when returning to service channel:
4358 * bits 0-19: beacon interal in usecs (suspend before executing)
4359 * bits 20-23: reserved
4360 * bits 24-31: number of beacons (suspend between channels)
4361 * @rxon_flags: RXON_FLG_*
4362 * @filter_flags: RXON_FILTER_*
4363 * @tx_cmd: for active scans (zero for passive), w/o payload,
4364 * no RS so specify TX rate
4365 * @direct_scan: direct scan SSIDs
4366 * @type: one of IWM_SCAN_TYPE_*
4367 * @repeats: how many time to repeat the scan
4369 struct iwm_scan_cmd {
4372 uint8_t channel_count;
4373 uint16_t quiet_time;
4374 uint16_t quiet_plcp_th;
4375 uint16_t passive2active;
4376 uint16_t rxchain_sel_flags;
4377 uint32_t max_out_time;
4378 uint32_t suspend_time;
4379 /* IWM_RX_ON_FLAGS_API_S_VER_1 */
4380 uint32_t rxon_flags;
4381 uint32_t filter_flags;
4382 struct iwm_tx_cmd tx_cmd;
4383 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX];
4388 * Probe request frame, followed by channel list.
4390 * Size of probe request frame is specified by byte count in tx_cmd.
4391 * Channel list follows immediately after probe request frame.
4392 * Number of channels in list is specified by channel_count.
4393 * Each channel in list is of type:
4395 * struct iwm_scan_channel channels[0];
4397 * NOTE: Only one band of channels can be scanned per pass. You
4398 * must not mix 2.4GHz channels and 5.2GHz channels, and you must wait
4399 * for one scan to complete (i.e. receive IWM_SCAN_COMPLETE_NOTIFICATION)
4400 * before requesting another scan.
4403 } __packed; /* IWM_SCAN_REQUEST_FIXED_PART_API_S_VER_5 */
4405 /* Response to scan request contains only status with one of these values */
4406 #define IWM_SCAN_RESPONSE_OK 0x1
4407 #define IWM_SCAN_RESPONSE_ERROR 0x2
4410 * IWM_SCAN_ABORT_CMD = 0x81
4411 * When scan abort is requested, the command has no fields except the common
4412 * header. The response contains only a status with one of these values.
4414 #define IWM_SCAN_ABORT_POSSIBLE 0x1
4415 #define IWM_SCAN_ABORT_IGNORED 0x2 /* no pending scans */
4417 /* TODO: complete documentation */
4418 #define IWM_SCAN_OWNER_STATUS 0x1
4419 #define IWM_MEASURE_OWNER_STATUS 0x2
4422 * struct iwm_scan_start_notif - notifies start of scan in the device
4423 * ( IWM_SCAN_START_NOTIFICATION = 0x82 )
4424 * @tsf_low: TSF timer (lower half) in usecs
4425 * @tsf_high: TSF timer (higher half) in usecs
4426 * @beacon_timer: structured as follows:
4427 * bits 0:19 - beacon interval in usecs
4428 * bits 20:23 - reserved (0)
4429 * bits 24:31 - number of beacons
4430 * @channel: which channel is scanned
4431 * @band: 0 for 5.2 GHz, 1 for 2.4 GHz
4432 * @status: one of *_OWNER_STATUS
4434 struct iwm_scan_start_notif {
4437 uint32_t beacon_timer;
4440 uint8_t reserved[2];
4442 } __packed; /* IWM_SCAN_START_NTF_API_S_VER_1 */
4444 /* scan results probe_status first bit indicates success */
4445 #define IWM_SCAN_PROBE_STATUS_OK 0
4446 #define IWM_SCAN_PROBE_STATUS_TX_FAILED (1 << 0)
4447 /* error statuses combined with TX_FAILED */
4448 #define IWM_SCAN_PROBE_STATUS_FAIL_TTL (1 << 1)
4449 #define IWM_SCAN_PROBE_STATUS_FAIL_BT (1 << 2)
4451 /* How many statistics are gathered for each channel */
4452 #define IWM_SCAN_RESULTS_STATISTICS 1
4455 * enum iwm_scan_complete_status - status codes for scan complete notifications
4456 * @IWM_SCAN_COMP_STATUS_OK: scan completed successfully
4457 * @IWM_SCAN_COMP_STATUS_ABORT: scan was aborted by user
4458 * @IWM_SCAN_COMP_STATUS_ERR_SLEEP: sending null sleep packet failed
4459 * @IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT: timeout before channel is ready
4460 * @IWM_SCAN_COMP_STATUS_ERR_PROBE: sending probe request failed
4461 * @IWM_SCAN_COMP_STATUS_ERR_WAKEUP: sending null wakeup packet failed
4462 * @IWM_SCAN_COMP_STATUS_ERR_ANTENNAS: invalid antennas chosen at scan command
4463 * @IWM_SCAN_COMP_STATUS_ERR_INTERNAL: internal error caused scan abort
4464 * @IWM_SCAN_COMP_STATUS_ERR_COEX: medium was lost ot WiMax
4465 * @IWM_SCAN_COMP_STATUS_P2P_ACTION_OK: P2P public action frame TX was successful
4467 * @IWM_SCAN_COMP_STATUS_ITERATION_END: indicates end of one repeatition the driver
4469 * @IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE: scan could not allocate time events
4471 enum iwm_scan_complete_status {
4472 IWM_SCAN_COMP_STATUS_OK = 0x1,
4473 IWM_SCAN_COMP_STATUS_ABORT = 0x2,
4474 IWM_SCAN_COMP_STATUS_ERR_SLEEP = 0x3,
4475 IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT = 0x4,
4476 IWM_SCAN_COMP_STATUS_ERR_PROBE = 0x5,
4477 IWM_SCAN_COMP_STATUS_ERR_WAKEUP = 0x6,
4478 IWM_SCAN_COMP_STATUS_ERR_ANTENNAS = 0x7,
4479 IWM_SCAN_COMP_STATUS_ERR_INTERNAL = 0x8,
4480 IWM_SCAN_COMP_STATUS_ERR_COEX = 0x9,
4481 IWM_SCAN_COMP_STATUS_P2P_ACTION_OK = 0xA,
4482 IWM_SCAN_COMP_STATUS_ITERATION_END = 0x0B,
4483 IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE = 0x0C,
4487 * struct iwm_scan_results_notif - scan results for one channel
4488 * ( IWM_SCAN_RESULTS_NOTIFICATION = 0x83 )
4489 * @channel: which channel the results are from
4490 * @band: 0 for 5.2 GHz, 1 for 2.4 GHz
4491 * @probe_status: IWM_SCAN_PROBE_STATUS_*, indicates success of probe request
4492 * @num_probe_not_sent: # of request that weren't sent due to not enough time
4493 * @duration: duration spent in channel, in usecs
4494 * @statistics: statistics gathered for this channel
4496 struct iwm_scan_results_notif {
4499 uint8_t probe_status;
4500 uint8_t num_probe_not_sent;
4502 uint32_t statistics[IWM_SCAN_RESULTS_STATISTICS];
4503 } __packed; /* IWM_SCAN_RESULT_NTF_API_S_VER_2 */
4506 * struct iwm_scan_complete_notif - notifies end of scanning (all channels)
4507 * ( IWM_SCAN_COMPLETE_NOTIFICATION = 0x84 )
4508 * @scanned_channels: number of channels scanned (and number of valid results)
4509 * @status: one of IWM_SCAN_COMP_STATUS_*
4510 * @bt_status: BT on/off status
4511 * @last_channel: last channel that was scanned
4512 * @tsf_low: TSF timer (lower half) in usecs
4513 * @tsf_high: TSF timer (higher half) in usecs
4514 * @results: all scan results, only "scanned_channels" of them are valid
4516 struct iwm_scan_complete_notif {
4517 uint8_t scanned_channels;
4520 uint8_t last_channel;
4523 struct iwm_scan_results_notif results[IWM_MAX_NUM_SCAN_CHANNELS];
4524 } __packed; /* IWM_SCAN_COMPLETE_NTF_API_S_VER_2 */
4527 #define IWM_MAX_SCAN_CHANNELS 40
4528 #define IWM_SCAN_MAX_BLACKLIST_LEN 64
4529 #define IWM_SCAN_SHORT_BLACKLIST_LEN 16
4530 #define IWM_SCAN_MAX_PROFILES 11
4531 #define IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE 512
4533 /* Default watchdog (in MS) for scheduled scan iteration */
4534 #define IWM_SCHED_SCAN_WATCHDOG cpu_to_le16(15000)
4536 #define IWM_GOOD_CRC_TH_DEFAULT cpu_to_le16(1)
4537 #define IWM_CAN_ABORT_STATUS 1
4539 #define IWM_FULL_SCAN_MULTIPLIER 5
4540 #define IWM_FAST_SCHED_SCAN_ITERATIONS 3
4542 enum iwm_scan_framework_client {
4543 IWM_SCAN_CLIENT_SCHED_SCAN = (1 << 0),
4544 IWM_SCAN_CLIENT_NETDETECT = (1 << 1),
4545 IWM_SCAN_CLIENT_ASSET_TRACKING = (1 << 2),
4549 * struct iwm_scan_offload_cmd - IWM_SCAN_REQUEST_FIXED_PART_API_S_VER_6
4550 * @scan_flags: see enum iwm_scan_flags
4551 * @channel_count: channels in channel list
4552 * @quiet_time: dwell time, in milisiconds, on quiet channel
4553 * @quiet_plcp_th: quiet channel num of packets threshold
4554 * @good_CRC_th: passive to active promotion threshold
4555 * @rx_chain: RXON rx chain.
4556 * @max_out_time: max uSec to be out of assoceated channel
4557 * @suspend_time: pause scan this long when returning to service channel
4558 * @flags: RXON flags
4559 * @filter_flags: RXONfilter
4560 * @tx_cmd: tx command for active scan; for 2GHz and for 5GHz.
4561 * @direct_scan: list of SSIDs for directed active scan
4562 * @scan_type: see enum iwm_scan_type.
4563 * @rep_count: repetition count for each scheduled scan iteration.
4565 struct iwm_scan_offload_cmd {
4568 uint8_t channel_count;
4569 uint16_t quiet_time;
4570 uint16_t quiet_plcp_th;
4571 uint16_t good_CRC_th;
4573 uint32_t max_out_time;
4574 uint32_t suspend_time;
4575 /* IWM_RX_ON_FLAGS_API_S_VER_1 */
4577 uint32_t filter_flags;
4578 struct iwm_tx_cmd tx_cmd[2];
4579 /* IWM_SCAN_DIRECT_SSID_IE_API_S_VER_1 */
4580 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX];
4585 enum iwm_scan_offload_channel_flags {
4586 IWM_SCAN_OFFLOAD_CHANNEL_ACTIVE = (1 << 0),
4587 IWM_SCAN_OFFLOAD_CHANNEL_NARROW = (1 << 22),
4588 IWM_SCAN_OFFLOAD_CHANNEL_FULL = (1 << 24),
4589 IWM_SCAN_OFFLOAD_CHANNEL_PARTIAL = (1 << 25),
4593 * iwm_scan_channel_cfg - IWM_SCAN_CHANNEL_CFG_S
4594 * @type: bitmap - see enum iwm_scan_offload_channel_flags.
4595 * 0: passive (0) or active (1) scan.
4596 * 1-20: directed scan to i'th ssid.
4597 * 22: channel width configuation - 1 for narrow.
4600 * @channel_number: channel number 1-13 etc.
4601 * @iter_count: repetition count for the channel.
4602 * @iter_interval: interval between two innteration on one channel.
4603 * @dwell_time: entry 0 - active scan, entry 1 - passive scan.
4605 struct iwm_scan_channel_cfg {
4606 uint32_t type[IWM_MAX_SCAN_CHANNELS];
4607 uint16_t channel_number[IWM_MAX_SCAN_CHANNELS];
4608 uint16_t iter_count[IWM_MAX_SCAN_CHANNELS];
4609 uint32_t iter_interval[IWM_MAX_SCAN_CHANNELS];
4610 uint8_t dwell_time[IWM_MAX_SCAN_CHANNELS][2];
4614 * iwm_scan_offload_cfg - IWM_SCAN_OFFLOAD_CONFIG_API_S
4615 * @scan_cmd: scan command fixed part
4616 * @channel_cfg: scan channel configuration
4617 * @data: probe request frames (one per band)
4619 struct iwm_scan_offload_cfg {
4620 struct iwm_scan_offload_cmd scan_cmd;
4621 struct iwm_scan_channel_cfg channel_cfg;
4626 * iwm_scan_offload_blacklist - IWM_SCAN_OFFLOAD_BLACKLIST_S
4627 * @ssid: MAC address to filter out
4628 * @reported_rssi: AP rssi reported to the host
4629 * @client_bitmap: clients ignore this entry - enum scan_framework_client
4631 struct iwm_scan_offload_blacklist {
4632 uint8_t ssid[IEEE80211_ADDR_LEN];
4633 uint8_t reported_rssi;
4634 uint8_t client_bitmap;
4637 enum iwm_scan_offload_network_type {
4638 IWM_NETWORK_TYPE_BSS = 1,
4639 IWM_NETWORK_TYPE_IBSS = 2,
4640 IWM_NETWORK_TYPE_ANY = 3,
4643 enum iwm_scan_offload_band_selection {
4644 IWM_SCAN_OFFLOAD_SELECT_2_4 = 0x4,
4645 IWM_SCAN_OFFLOAD_SELECT_5_2 = 0x8,
4646 IWM_SCAN_OFFLOAD_SELECT_ANY = 0xc,
4650 * iwm_scan_offload_profile - IWM_SCAN_OFFLOAD_PROFILE_S
4651 * @ssid_index: index to ssid list in fixed part
4652 * @unicast_cipher: encryption olgorithm to match - bitmap
4653 * @aut_alg: authentication olgorithm to match - bitmap
4654 * @network_type: enum iwm_scan_offload_network_type
4655 * @band_selection: enum iwm_scan_offload_band_selection
4656 * @client_bitmap: clients waiting for match - enum scan_framework_client
4658 struct iwm_scan_offload_profile {
4660 uint8_t unicast_cipher;
4662 uint8_t network_type;
4663 uint8_t band_selection;
4664 uint8_t client_bitmap;
4665 uint8_t reserved[2];
4669 * iwm_scan_offload_profile_cfg - IWM_SCAN_OFFLOAD_PROFILES_CFG_API_S_VER_1
4670 * @blaclist: AP list to filter off from scan results
4671 * @profiles: profiles to search for match
4672 * @blacklist_len: length of blacklist
4673 * @num_profiles: num of profiles in the list
4674 * @match_notify: clients waiting for match found notification
4675 * @pass_match: clients waiting for the results
4676 * @active_clients: active clients bitmap - enum scan_framework_client
4677 * @any_beacon_notify: clients waiting for match notification without match
4679 struct iwm_scan_offload_profile_cfg {
4680 struct iwm_scan_offload_profile profiles[IWM_SCAN_MAX_PROFILES];
4681 uint8_t blacklist_len;
4682 uint8_t num_profiles;
4683 uint8_t match_notify;
4685 uint8_t active_clients;
4686 uint8_t any_beacon_notify;
4687 uint8_t reserved[2];
4691 * iwm_scan_offload_schedule - schedule of scan offload
4692 * @delay: delay between iterations, in seconds.
4693 * @iterations: num of scan iterations
4694 * @full_scan_mul: number of partial scans before each full scan
4696 struct iwm_scan_offload_schedule {
4699 uint8_t full_scan_mul;
4703 * iwm_scan_offload_flags
4705 * IWM_SCAN_OFFLOAD_FLAG_PASS_ALL: pass all results - no filtering.
4706 * IWM_SCAN_OFFLOAD_FLAG_CACHED_CHANNEL: add cached channels to partial scan.
4707 * IWM_SCAN_OFFLOAD_FLAG_ENERGY_SCAN: use energy based scan before partial scan
4710 enum iwm_scan_offload_flags {
4711 IWM_SCAN_OFFLOAD_FLAG_PASS_ALL = (1 << 0),
4712 IWM_SCAN_OFFLOAD_FLAG_CACHED_CHANNEL = (1 << 2),
4713 IWM_SCAN_OFFLOAD_FLAG_ENERGY_SCAN = (1 << 3),
4717 * iwm_scan_offload_req - scan offload request command
4718 * @flags: bitmap - enum iwm_scan_offload_flags.
4719 * @watchdog: maximum scan duration in TU.
4720 * @delay: delay in seconds before first iteration.
4721 * @schedule_line: scan offload schedule, for fast and regular scan.
4723 struct iwm_scan_offload_req {
4728 struct iwm_scan_offload_schedule schedule_line[2];
4731 enum iwm_scan_offload_compleate_status {
4732 IWM_SCAN_OFFLOAD_COMPLETED = 1,
4733 IWM_SCAN_OFFLOAD_ABORTED = 2,
4737 * iwm_scan_offload_complete - IWM_SCAN_OFFLOAD_COMPLETE_NTF_API_S_VER_1
4738 * @last_schedule_line: last schedule line executed (fast or regular)
4739 * @last_schedule_iteration: last scan iteration executed before scan abort
4740 * @status: enum iwm_scan_offload_compleate_status
4742 struct iwm_scan_offload_complete {
4743 uint8_t last_schedule_line;
4744 uint8_t last_schedule_iteration;
4750 * iwm_sched_scan_results - IWM_SCAN_OFFLOAD_MATCH_FOUND_NTF_API_S_VER_1
4751 * @ssid_bitmap: SSIDs indexes found in this iteration
4752 * @client_bitmap: clients that are active and wait for this notification
4754 struct iwm_sched_scan_results {
4755 uint16_t ssid_bitmap;
4756 uint8_t client_bitmap;
4761 * enum iwm_sta_flags - flags for the ADD_STA host command
4762 * @IWM_STA_FLG_REDUCED_TX_PWR_CTRL:
4763 * @IWM_STA_FLG_REDUCED_TX_PWR_DATA:
4764 * @IWM_STA_FLG_FLG_ANT_MSK: Antenna selection
4765 * @IWM_STA_FLG_PS: set if STA is in Power Save
4766 * @IWM_STA_FLG_INVALID: set if STA is invalid
4767 * @IWM_STA_FLG_DLP_EN: Direct Link Protocol is enabled
4768 * @IWM_STA_FLG_SET_ALL_KEYS: the current key applies to all key IDs
4769 * @IWM_STA_FLG_DRAIN_FLOW: drain flow
4770 * @IWM_STA_FLG_PAN: STA is for PAN interface
4771 * @IWM_STA_FLG_CLASS_AUTH:
4772 * @IWM_STA_FLG_CLASS_ASSOC:
4773 * @IWM_STA_FLG_CLASS_MIMO_PROT:
4774 * @IWM_STA_FLG_MAX_AGG_SIZE_MSK: maximal size for A-MPDU
4775 * @IWM_STA_FLG_AGG_MPDU_DENS_MSK: maximal MPDU density for Tx aggregation
4776 * @IWM_STA_FLG_FAT_EN_MSK: support for channel width (for Tx). This flag is
4777 * initialised by driver and can be updated by fw upon reception of
4778 * action frames that can change the channel width. When cleared the fw
4779 * will send all the frames in 20MHz even when FAT channel is requested.
4780 * @IWM_STA_FLG_MIMO_EN_MSK: support for MIMO. This flag is initialised by the
4781 * driver and can be updated by fw upon reception of action frames.
4782 * @IWM_STA_FLG_MFP_EN: Management Frame Protection
4784 enum iwm_sta_flags {
4785 IWM_STA_FLG_REDUCED_TX_PWR_CTRL = (1 << 3),
4786 IWM_STA_FLG_REDUCED_TX_PWR_DATA = (1 << 6),
4788 IWM_STA_FLG_FLG_ANT_A = (1 << 4),
4789 IWM_STA_FLG_FLG_ANT_B = (2 << 4),
4790 IWM_STA_FLG_FLG_ANT_MSK = (IWM_STA_FLG_FLG_ANT_A |
4791 IWM_STA_FLG_FLG_ANT_B),
4793 IWM_STA_FLG_PS = (1 << 8),
4794 IWM_STA_FLG_DRAIN_FLOW = (1 << 12),
4795 IWM_STA_FLG_PAN = (1 << 13),
4796 IWM_STA_FLG_CLASS_AUTH = (1 << 14),
4797 IWM_STA_FLG_CLASS_ASSOC = (1 << 15),
4798 IWM_STA_FLG_RTS_MIMO_PROT = (1 << 17),
4800 IWM_STA_FLG_MAX_AGG_SIZE_SHIFT = 19,
4801 IWM_STA_FLG_MAX_AGG_SIZE_8K = (0 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
4802 IWM_STA_FLG_MAX_AGG_SIZE_16K = (1 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
4803 IWM_STA_FLG_MAX_AGG_SIZE_32K = (2 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
4804 IWM_STA_FLG_MAX_AGG_SIZE_64K = (3 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
4805 IWM_STA_FLG_MAX_AGG_SIZE_128K = (4 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
4806 IWM_STA_FLG_MAX_AGG_SIZE_256K = (5 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
4807 IWM_STA_FLG_MAX_AGG_SIZE_512K = (6 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
4808 IWM_STA_FLG_MAX_AGG_SIZE_1024K = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
4809 IWM_STA_FLG_MAX_AGG_SIZE_MSK = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
4811 IWM_STA_FLG_AGG_MPDU_DENS_SHIFT = 23,
4812 IWM_STA_FLG_AGG_MPDU_DENS_2US = (4 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
4813 IWM_STA_FLG_AGG_MPDU_DENS_4US = (5 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
4814 IWM_STA_FLG_AGG_MPDU_DENS_8US = (6 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
4815 IWM_STA_FLG_AGG_MPDU_DENS_16US = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
4816 IWM_STA_FLG_AGG_MPDU_DENS_MSK = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
4818 IWM_STA_FLG_FAT_EN_20MHZ = (0 << 26),
4819 IWM_STA_FLG_FAT_EN_40MHZ = (1 << 26),
4820 IWM_STA_FLG_FAT_EN_80MHZ = (2 << 26),
4821 IWM_STA_FLG_FAT_EN_160MHZ = (3 << 26),
4822 IWM_STA_FLG_FAT_EN_MSK = (3 << 26),
4824 IWM_STA_FLG_MIMO_EN_SISO = (0 << 28),
4825 IWM_STA_FLG_MIMO_EN_MIMO2 = (1 << 28),
4826 IWM_STA_FLG_MIMO_EN_MIMO3 = (2 << 28),
4827 IWM_STA_FLG_MIMO_EN_MSK = (3 << 28),
4831 * enum iwm_sta_key_flag - key flags for the ADD_STA host command
4832 * @IWM_STA_KEY_FLG_NO_ENC: no encryption
4833 * @IWM_STA_KEY_FLG_WEP: WEP encryption algorithm
4834 * @IWM_STA_KEY_FLG_CCM: CCMP encryption algorithm
4835 * @IWM_STA_KEY_FLG_TKIP: TKIP encryption algorithm
4836 * @IWM_STA_KEY_FLG_EXT: extended cipher algorithm (depends on the FW support)
4837 * @IWM_STA_KEY_FLG_CMAC: CMAC encryption algorithm
4838 * @IWM_STA_KEY_FLG_ENC_UNKNOWN: unknown encryption algorithm
4839 * @IWM_STA_KEY_FLG_EN_MSK: mask for encryption algorithmi value
4840 * @IWM_STA_KEY_FLG_WEP_KEY_MAP: wep is either a group key (0 - legacy WEP) or from
4841 * station info array (1 - n 1X mode)
4842 * @IWM_STA_KEY_FLG_KEYID_MSK: the index of the key
4843 * @IWM_STA_KEY_NOT_VALID: key is invalid
4844 * @IWM_STA_KEY_FLG_WEP_13BYTES: set for 13 bytes WEP key
4845 * @IWM_STA_KEY_MULTICAST: set for multical key
4846 * @IWM_STA_KEY_MFP: key is used for Management Frame Protection
4848 enum iwm_sta_key_flag {
4849 IWM_STA_KEY_FLG_NO_ENC = (0 << 0),
4850 IWM_STA_KEY_FLG_WEP = (1 << 0),
4851 IWM_STA_KEY_FLG_CCM = (2 << 0),
4852 IWM_STA_KEY_FLG_TKIP = (3 << 0),
4853 IWM_STA_KEY_FLG_EXT = (4 << 0),
4854 IWM_STA_KEY_FLG_CMAC = (6 << 0),
4855 IWM_STA_KEY_FLG_ENC_UNKNOWN = (7 << 0),
4856 IWM_STA_KEY_FLG_EN_MSK = (7 << 0),
4858 IWM_STA_KEY_FLG_WEP_KEY_MAP = (1 << 3),
4859 IWM_STA_KEY_FLG_KEYID_POS = 8,
4860 IWM_STA_KEY_FLG_KEYID_MSK = (3 << IWM_STA_KEY_FLG_KEYID_POS),
4861 IWM_STA_KEY_NOT_VALID = (1 << 11),
4862 IWM_STA_KEY_FLG_WEP_13BYTES = (1 << 12),
4863 IWM_STA_KEY_MULTICAST = (1 << 14),
4864 IWM_STA_KEY_MFP = (1 << 15),
4868 * enum iwm_sta_modify_flag - indicate to the fw what flag are being changed
4869 * @IWM_STA_MODIFY_KEY: this command modifies %key
4870 * @IWM_STA_MODIFY_TID_DISABLE_TX: this command modifies %tid_disable_tx
4871 * @IWM_STA_MODIFY_TX_RATE: unused
4872 * @IWM_STA_MODIFY_ADD_BA_TID: this command modifies %add_immediate_ba_tid
4873 * @IWM_STA_MODIFY_REMOVE_BA_TID: this command modifies %remove_immediate_ba_tid
4874 * @IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT: this command modifies %sleep_tx_count
4875 * @IWM_STA_MODIFY_PROT_TH:
4876 * @IWM_STA_MODIFY_QUEUES: modify the queues used by this station
4878 enum iwm_sta_modify_flag {
4879 IWM_STA_MODIFY_KEY = (1 << 0),
4880 IWM_STA_MODIFY_TID_DISABLE_TX = (1 << 1),
4881 IWM_STA_MODIFY_TX_RATE = (1 << 2),
4882 IWM_STA_MODIFY_ADD_BA_TID = (1 << 3),
4883 IWM_STA_MODIFY_REMOVE_BA_TID = (1 << 4),
4884 IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT = (1 << 5),
4885 IWM_STA_MODIFY_PROT_TH = (1 << 6),
4886 IWM_STA_MODIFY_QUEUES = (1 << 7),
4889 #define IWM_STA_MODE_MODIFY 1
4892 * enum iwm_sta_sleep_flag - type of sleep of the station
4893 * @IWM_STA_SLEEP_STATE_AWAKE:
4894 * @IWM_STA_SLEEP_STATE_PS_POLL:
4895 * @IWM_STA_SLEEP_STATE_UAPSD:
4897 enum iwm_sta_sleep_flag {
4898 IWM_STA_SLEEP_STATE_AWAKE = 0,
4899 IWM_STA_SLEEP_STATE_PS_POLL = (1 << 0),
4900 IWM_STA_SLEEP_STATE_UAPSD = (1 << 1),
4903 /* STA ID and color bits definitions */
4904 #define IWM_STA_ID_SEED (0x0f)
4905 #define IWM_STA_ID_POS (0)
4906 #define IWM_STA_ID_MSK (IWM_STA_ID_SEED << IWM_STA_ID_POS)
4908 #define IWM_STA_COLOR_SEED (0x7)
4909 #define IWM_STA_COLOR_POS (4)
4910 #define IWM_STA_COLOR_MSK (IWM_STA_COLOR_SEED << IWM_STA_COLOR_POS)
4912 #define IWM_STA_ID_N_COLOR_GET_COLOR(id_n_color) \
4913 (((id_n_color) & IWM_STA_COLOR_MSK) >> IWM_STA_COLOR_POS)
4914 #define IWM_STA_ID_N_COLOR_GET_ID(id_n_color) \
4915 (((id_n_color) & IWM_STA_ID_MSK) >> IWM_STA_ID_POS)
4917 #define IWM_STA_KEY_MAX_NUM (16)
4918 #define IWM_STA_KEY_IDX_INVALID (0xff)
4919 #define IWM_STA_KEY_MAX_DATA_KEY_NUM (4)
4920 #define IWM_MAX_GLOBAL_KEYS (4)
4921 #define IWM_STA_KEY_LEN_WEP40 (5)
4922 #define IWM_STA_KEY_LEN_WEP104 (13)
4925 * struct iwm_mvm_keyinfo - key information
4926 * @key_flags: type %iwm_sta_key_flag
4927 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection
4928 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx
4929 * @key_offset: key offset in the fw's key table
4930 * @key: 16-byte unicast decryption key
4931 * @tx_secur_seq_cnt: initial RSC / PN needed for replay check
4932 * @hw_tkip_mic_rx_key: byte: MIC Rx Key - used for TKIP only
4933 * @hw_tkip_mic_tx_key: byte: MIC Tx Key - used for TKIP only
4935 struct iwm_mvm_keyinfo {
4937 uint8_t tkip_rx_tsc_byte2;
4939 uint16_t tkip_rx_ttak[5];
4943 uint64_t tx_secur_seq_cnt;
4944 uint64_t hw_tkip_mic_rx_key;
4945 uint64_t hw_tkip_mic_tx_key;
4949 * struct iwm_mvm_add_sta_cmd_v5 - Add/modify a station in the fw's sta table.
4950 * ( IWM_REPLY_ADD_STA = 0x18 )
4951 * @add_modify: 1: modify existing, 0: add new station
4952 * @unicast_tx_key_id: unicast tx key id. Relevant only when unicast key sent
4953 * @multicast_tx_key_id: multicast tx key id. Relevant only when multicast key
4955 * @mac_id_n_color: the Mac context this station belongs to
4956 * @addr[IEEE80211_ADDR_LEN]: station's MAC address
4957 * @sta_id: index of station in uCode's station table
4958 * @modify_mask: IWM_STA_MODIFY_*, selects which parameters to modify vs. leave
4959 * alone. 1 - modify, 0 - don't change.
4960 * @key: look at %iwm_mvm_keyinfo
4961 * @station_flags: look at %iwm_sta_flags
4962 * @station_flags_msk: what of %station_flags have changed
4963 * @tid_disable_tx: is tid BIT(tid) enabled for Tx. Clear BIT(x) to enable
4964 * AMPDU for tid x. Set %IWM_STA_MODIFY_TID_DISABLE_TX to change this field.
4965 * @add_immediate_ba_tid: tid for which to add block-ack support (Rx)
4966 * Set %IWM_STA_MODIFY_ADD_BA_TID to use this field, and also set
4967 * add_immediate_ba_ssn.
4968 * @remove_immediate_ba_tid: tid for which to remove block-ack support (Rx)
4969 * Set %IWM_STA_MODIFY_REMOVE_BA_TID to use this field
4970 * @add_immediate_ba_ssn: ssn for the Rx block-ack session. Used together with
4971 * add_immediate_ba_tid.
4972 * @sleep_tx_count: number of packets to transmit to station even though it is
4973 * asleep. Used to synchronise PS-poll and u-APSD responses while ucode
4974 * keeps track of STA sleep state.
4975 * @sleep_state_flags: Look at %iwm_sta_sleep_flag.
4976 * @assoc_id: assoc_id to be sent in VHT PLCP (9-bit), for grp use 0, for AP
4978 * @beamform_flags: beam forming controls
4979 * @tfd_queue_msk: tfd queues used by this station
4981 * The device contains an internal table of per-station information, with info
4982 * on security keys, aggregation parameters, and Tx rates for initial Tx
4983 * attempt and any retries (set by IWM_REPLY_TX_LINK_QUALITY_CMD).
4985 * ADD_STA sets up the table entry for one station, either creating a new
4986 * entry, or modifying a pre-existing one.
4988 struct iwm_mvm_add_sta_cmd_v5 {
4990 uint8_t unicast_tx_key_id;
4991 uint8_t multicast_tx_key_id;
4993 uint32_t mac_id_n_color;
4994 uint8_t addr[IEEE80211_ADDR_LEN];
4997 uint8_t modify_mask;
4999 struct iwm_mvm_keyinfo key;
5000 uint32_t station_flags;
5001 uint32_t station_flags_msk;
5002 uint16_t tid_disable_tx;
5004 uint8_t add_immediate_ba_tid;
5005 uint8_t remove_immediate_ba_tid;
5006 uint16_t add_immediate_ba_ssn;
5007 uint16_t sleep_tx_count;
5008 uint16_t sleep_state_flags;
5010 uint16_t beamform_flags;
5011 uint32_t tfd_queue_msk;
5012 } __packed; /* IWM_ADD_STA_CMD_API_S_VER_5 */
5015 * struct iwm_mvm_add_sta_cmd_v6 - Add / modify a station
5016 * VER_6 of this command is quite similar to VER_5 except
5017 * exclusion of all fields related to the security key installation.
5019 struct iwm_mvm_add_sta_cmd_v6 {
5022 uint16_t tid_disable_tx;
5023 uint32_t mac_id_n_color;
5024 uint8_t addr[IEEE80211_ADDR_LEN]; /* _STA_ID_MODIFY_INFO_API_S_VER_1 */
5027 uint8_t modify_mask;
5029 uint32_t station_flags;
5030 uint32_t station_flags_msk;
5031 uint8_t add_immediate_ba_tid;
5032 uint8_t remove_immediate_ba_tid;
5033 uint16_t add_immediate_ba_ssn;
5034 uint16_t sleep_tx_count;
5035 uint16_t sleep_state_flags;
5037 uint16_t beamform_flags;
5038 uint32_t tfd_queue_msk;
5039 } __packed; /* IWM_ADD_STA_CMD_API_S_VER_6 */
5042 * struct iwm_mvm_add_sta_key_cmd - add/modify sta key
5043 * ( IWM_REPLY_ADD_STA_KEY = 0x17 )
5044 * @sta_id: index of station in uCode's station table
5045 * @key_offset: key offset in key storage
5046 * @key_flags: type %iwm_sta_key_flag
5047 * @key: key material data
5048 * @key2: key material data
5049 * @rx_secur_seq_cnt: RX security sequence counter for the key
5050 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection
5051 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx
5053 struct iwm_mvm_add_sta_key_cmd {
5059 uint8_t rx_secur_seq_cnt[16];
5060 uint8_t tkip_rx_tsc_byte2;
5062 uint16_t tkip_rx_ttak[5];
5063 } __packed; /* IWM_ADD_MODIFY_STA_KEY_API_S_VER_1 */
5066 * enum iwm_mvm_add_sta_rsp_status - status in the response to ADD_STA command
5067 * @IWM_ADD_STA_SUCCESS: operation was executed successfully
5068 * @IWM_ADD_STA_STATIONS_OVERLOAD: no room left in the fw's station table
5069 * @IWM_ADD_STA_IMMEDIATE_BA_FAILURE: can't add Rx block ack session
5070 * @IWM_ADD_STA_MODIFY_NON_EXISTING_STA: driver requested to modify a station
5071 * that doesn't exist.
5073 enum iwm_mvm_add_sta_rsp_status {
5074 IWM_ADD_STA_SUCCESS = 0x1,
5075 IWM_ADD_STA_STATIONS_OVERLOAD = 0x2,
5076 IWM_ADD_STA_IMMEDIATE_BA_FAILURE = 0x4,
5077 IWM_ADD_STA_MODIFY_NON_EXISTING_STA = 0x8,
5081 * struct iwm_mvm_rm_sta_cmd - Add / modify a station in the fw's station table
5082 * ( IWM_REMOVE_STA = 0x19 )
5083 * @sta_id: the station id of the station to be removed
5085 struct iwm_mvm_rm_sta_cmd {
5087 uint8_t reserved[3];
5088 } __packed; /* IWM_REMOVE_STA_CMD_API_S_VER_2 */
5091 * struct iwm_mvm_mgmt_mcast_key_cmd
5092 * ( IWM_MGMT_MCAST_KEY = 0x1f )
5093 * @ctrl_flags: %iwm_sta_key_flag
5095 * @K1: IGTK master key
5097 * @sta_id: station ID that support IGTK
5099 * @receive_seq_cnt: initial RSC/PN needed for replay check
5101 struct iwm_mvm_mgmt_mcast_key_cmd {
5102 uint32_t ctrl_flags;
5108 uint64_t receive_seq_cnt;
5109 } __packed; /* SEC_MGMT_MULTICAST_KEY_CMD_API_S_VER_1 */
5111 struct iwm_mvm_wep_key {
5116 uint8_t reserved2[3];
5120 struct iwm_mvm_wep_key_cmd {
5121 uint32_t mac_id_n_color;
5123 uint8_t decryption_type;
5126 struct iwm_mvm_wep_key wep_key[0];
5127 } __packed; /* SEC_CURR_WEP_KEY_CMD_API_S_VER_2 */
5131 * Some cherry-picked definitions
5134 #define IWM_FRAME_LIMIT 64
5136 struct iwm_cmd_header {
5143 enum iwm_power_scheme {
5144 IWM_POWER_SCHEME_CAM = 1,
5145 IWM_POWER_SCHEME_BPS,
5149 #define IWM_DEF_CMD_PAYLOAD_SIZE 320
5150 #define IWM_CMD_FAILED_MSK 0x40
5152 struct iwm_device_cmd {
5153 struct iwm_cmd_header hdr;
5155 uint8_t data[IWM_DEF_CMD_PAYLOAD_SIZE];
5158 struct iwm_rx_packet {
5160 * The first 4 bytes of the RX frame header contain both the RX frame
5161 * size and some flags.
5163 * 31: flag flush RB request
5164 * 30: flag ignore TC (terminal counter) request
5165 * 29: flag fast IRQ request
5167 * 13-00: RX frame size
5169 uint32_t len_n_flags;
5170 struct iwm_cmd_header hdr;
5174 #define IWM_FH_RSCSR_FRAME_SIZE_MSK 0x00003fff
5176 static inline uint32_t
5177 iwm_rx_packet_len(const struct iwm_rx_packet *pkt)
5180 return le32toh(pkt->len_n_flags) & IWM_FH_RSCSR_FRAME_SIZE_MSK;
5183 static inline uint32_t
5184 iwm_rx_packet_payload_len(const struct iwm_rx_packet *pkt)
5187 return iwm_rx_packet_len(pkt) - sizeof(pkt->hdr);
5191 #define IWM_MIN_DBM -100
5192 #define IWM_MAX_DBM -33 /* realistic guess */
5194 #define IWM_READ(sc, reg) \
5195 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
5197 #define IWM_WRITE(sc, reg, val) \
5198 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
5200 #define IWM_WRITE_1(sc, reg, val) \
5201 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
5203 #define IWM_SETBITS(sc, reg, mask) \
5204 IWM_WRITE(sc, reg, IWM_READ(sc, reg) | (mask))
5206 #define IWM_CLRBITS(sc, reg, mask) \
5207 IWM_WRITE(sc, reg, IWM_READ(sc, reg) & ~(mask))
5209 #define IWM_BARRIER_WRITE(sc) \
5210 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \
5211 BUS_SPACE_BARRIER_WRITE)
5213 #define IWM_BARRIER_READ_WRITE(sc) \
5214 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \
5215 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE)
5217 #define IWM_FW_VALID_TX_ANT(sc) \
5218 ((sc->sc_fw_phy_config & IWM_FW_PHY_CFG_TX_CHAIN) \
5219 >> IWM_FW_PHY_CFG_TX_CHAIN_POS)
5220 #define IWM_FW_VALID_RX_ANT(sc) \
5221 ((sc->sc_fw_phy_config & IWM_FW_PHY_CFG_RX_CHAIN) \
5222 >> IWM_FW_PHY_CFG_RX_CHAIN_POS)
5224 #endif /* __IF_IWM_REG_H__ */