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35 #ifndef _E1000_ICH8LAN_H_
36 #define _E1000_ICH8LAN_H_
38 #define ICH_FLASH_GFPREG 0x0000
39 #define ICH_FLASH_HSFSTS 0x0004
40 #define ICH_FLASH_HSFCTL 0x0006
41 #define ICH_FLASH_FADDR 0x0008
42 #define ICH_FLASH_FDATA0 0x0010
44 #define ICH_FLASH_READ_COMMAND_TIMEOUT 500
45 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
46 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
47 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
48 #define ICH_FLASH_CYCLE_REPEAT_COUNT 10
50 #define ICH_CYCLE_READ 0
51 #define ICH_CYCLE_WRITE 2
52 #define ICH_CYCLE_ERASE 3
54 #define FLASH_GFPREG_BASE_MASK 0x1FFF
55 #define FLASH_SECTOR_ADDR_SHIFT 12
57 #define ICH_FLASH_SEG_SIZE_256 256
58 #define ICH_FLASH_SEG_SIZE_4K 4096
59 #define ICH_FLASH_SEG_SIZE_8K 8192
60 #define ICH_FLASH_SEG_SIZE_64K 65536
61 #define ICH_FLASH_SECTOR_SIZE 4096
63 #define ICH_FLASH_REG_MAPSIZE 0x00A0
65 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
66 #define E1000_ICH_FWSM_DISSW 0x10000000 /* FW Disables SW Writes */
67 /* FW established a valid mode */
68 #define E1000_ICH_FWSM_FW_VALID 0x00008000
70 #define E1000_ICH_MNG_IAMT_MODE 0x2
72 #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
73 (ID_LED_DEF1_OFF2 << 8) | \
74 (ID_LED_DEF1_ON2 << 4) | \
77 #define E1000_ICH_NVM_SIG_WORD 0x13
78 #define E1000_ICH_NVM_SIG_MASK 0xC000
80 #define E1000_ICH8_LAN_INIT_TIMEOUT 1500
82 #define E1000_FEXTNVM_SW_CONFIG 1
83 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M */
85 #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
87 #define E1000_ICH_RAR_ENTRIES 7
89 #define PHY_PAGE_SHIFT 5
90 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
91 ((reg) & MAX_PHY_REG_ADDRESS))
92 #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
93 #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
94 #define IGP3_CAPABILITY PHY_REG(776, 19) /* Capability */
95 #define IGP3_PM_CTRL PHY_REG(769, 20) /* Power Management Control */
97 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
98 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
99 #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
100 #define IGP3_PM_CTRL_FORCE_PWR_DOWN 0x0020
103 * Additional interrupts need to be handled for ICH family:
104 * DSW = The FW changed the status of the DISSW bit in FWSM
105 * PHYINT = The LAN connected device generates an interrupt
106 * EPRST = Manageability reset event
108 #define IMS_ICH_ENABLE_MASK (\
113 /* Additional interrupt register bit definitions */
114 #define E1000_ICR_LSECPNC 0x00004000 /* PN threshold - client */
115 #define E1000_IMS_LSECPNC E1000_ICR_LSECPNC /* PN threshold - client */
116 #define E1000_ICS_LSECPNC E1000_ICR_LSECPNC /* PN threshold - client */
118 /* Security Processing bit Indication */
119 #define E1000_RXDEXT_LINKSEC_STATUS_LSECH 0x01000000
120 #define E1000_RXDEXT_LINKSEC_ERROR_BIT_MASK 0x60000000
121 #define E1000_RXDEXT_LINKSEC_ERROR_NO_SA_MATCH 0x20000000
122 #define E1000_RXDEXT_LINKSEC_ERROR_REPLAY_ERROR 0x40000000
123 #define E1000_RXDEXT_LINKSEC_ERROR_BAD_SIG 0x60000000
126 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
128 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
129 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
130 void e1000_disable_gig_wol_ich8lan(struct e1000_hw *hw);