2 * Copyright (c) 2007 The DragonFly Project. All rights reserved.
4 * This code is derived from software contributed to The DragonFly Project
5 * by Sepherosa Ziehau <sepherosa@gmail.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * $DragonFly: src/sys/dev/netif/bwi/if_bwireg.h,v 1.4 2007/10/19 14:27:04 sephe Exp $
41 * Registers for all of the register windows
43 #define BWI_FLAGS 0xf18
44 #define BWI_FLAGS_INTR_MASK __BITS(5, 0)
46 #define BWI_IMSTATE 0xf90
47 #define BWI_IMSTATE_INBAND_ERR __BIT(17)
48 #define BWI_IMSTATE_TIMEOUT __BIT(18)
50 #define BWI_INTRVEC 0xf94
52 #define BWI_STATE_LO 0xf98
53 #define BWI_STATE_LO_RESET __BIT(0)
54 #define BWI_STATE_LO_DISABLE1 __BIT(1)
55 #define BWI_STATE_LO_DISABLE2 __BIT(2)
56 #define BWI_STATE_LO_CLOCK __BIT(16)
57 #define BWI_STATE_LO_GATED_CLOCK __BIT(17)
58 #define BWI_STATE_LO_FLAG_PHYCLKEN __BIT(0)
59 #define BWI_STATE_LO_FLAG_PHYRST __BIT(1)
60 #define BWI_STATE_LO_FLAG_PHYLNK __BIT(11)
61 #define BWI_STATE_LO_FLAGS_MASK __BITS(29, 18)
63 #define BWI_STATE_HI 0xf9c
64 #define BWI_STATE_HI_SERROR __BIT(0)
65 #define BWI_STATE_HI_BUSY __BIT(2)
66 #define BWI_STATE_HI_FLAG_MAGIC1 0x1
67 #define BWI_STATE_HI_FLAG_MAGIC2 0x2
68 #define BWI_STATE_HI_FLAG_64BIT 0x1000
69 #define BWI_STATE_HI_FLAGS_MASK __BITS(28, 16)
71 #define BWI_CONF_LO 0xfa8
72 #define BWI_CONF_LO_SERVTO_MASK __BITS(2, 0) /* service timeout */
73 #define BWI_CONF_LO_SERVTO 2
74 #define BWI_CONF_LO_REQTO_MASK __BITS(6, 4) /* request timeout */
75 #define BWI_CONF_LO_REQTO 3
78 #define BWI_ID_LO 0xff8
79 #define BWI_ID_LO_BUSREV_MASK __BITS(31, 28)
81 #define BWI_BUSREV_0 0
82 #define BWI_BUSREV_1 1
84 #define BWI_ID_HI 0xffc
85 #define BWI_ID_HI_REGWIN_REV(v) (((v) & 0xf) | (((v) & 0x7000) >> 8))
86 #define BWI_ID_HI_REGWIN_TYPE(v) (((v) & 0x8ff0) >> 4)
87 #define BWI_ID_HI_REGWIN_VENDOR_MASK __BITS(31, 16)
90 * Registers for common register window
93 #define BWI_INFO_BBPID_MASK __BITS(15, 0)
94 #define BWI_INFO_BBPREV_MASK __BITS(19, 16)
95 #define BWI_INFO_BBPPKG_MASK __BITS(23, 20)
96 #define BWI_INFO_NREGWIN_MASK __BITS(27, 24)
98 #define BWI_CAPABILITY 0x4
99 #define BWI_CAP_CLKMODE __BIT(18)
101 #define BWI_CONTROL 0x28
102 #define BWI_CONTROL_MAGIC0 0x3a4
103 #define BWI_CONTROL_MAGIC1 0xa4
104 #define BWI_PLL_ON_DELAY 0xb0
105 #define BWI_FREQ_SEL_DELAY 0xb4
107 #define BWI_CLOCK_CTRL 0xb8
108 #define BWI_CLOCK_CTRL_CLKSRC __BITS(2, 0)
109 #define BWI_CLOCK_CTRL_SLOW __BIT(11)
110 #define BWI_CLOCK_CTRL_IGNPLL __BIT(12)
111 #define BWI_CLOCK_CTRL_NODYN __BIT(13)
112 #define BWI_CLOCK_CTRL_FDIV __BITS(31, 16) /* freq divisor */
114 /* Possible values for BWI_CLOCK_CTRL_CLKSRC */
115 #define BWI_CLKSRC_LP_OSC 0 /* Low power oscillator */
116 #define BWI_CLKSRC_CS_OSC 1 /* Crystal oscillator */
117 #define BWI_CLKSRC_PCI 2
118 #define BWI_CLKSRC_MAX 3 /* Maximum of clock source */
119 /* Min/Max frequency for given clock source */
120 #define BWI_CLKSRC_LP_OSC_FMIN 25000
121 #define BWI_CLKSRC_LP_OSC_FMAX 43000
122 #define BWI_CLKSRC_CS_OSC_FMIN 19800000
123 #define BWI_CLKSRC_CS_OSC_FMAX 20200000
124 #define BWI_CLKSRC_PCI_FMIN 25000000
125 #define BWI_CLKSRC_PCI_FMAX 34000000
127 #define BWI_CLOCK_INFO 0xc0
128 #define BWI_CLOCK_INFO_FDIV __BITS(31, 16) /* freq divisor */
131 * Registers for bus register window
133 #define BWI_BUS_ADDR 0x50
134 #define BWI_BUS_ADDR_MAGIC 0xfd8
136 #define BWI_BUS_DATA 0x54
138 #define BWI_BUS_CONFIG 0x108
139 #define BWI_BUS_CONFIG_PREFETCH __BIT(2)
140 #define BWI_BUS_CONFIG_BURST __BIT(3)
141 #define BWI_BUS_CONFIG_MRM __BIT(5)
146 #define BWI_TXRX_INTR_STATUS_BASE 0x20
147 #define BWI_TXRX_INTR_MASK_BASE 0x24
148 #define BWI_TXRX_INTR_STATUS(i) (BWI_TXRX_INTR_STATUS_BASE + ((i) * 8))
149 #define BWI_TXRX_INTR_MASK(i) (BWI_TXRX_INTR_MASK_BASE + ((i) * 8))
151 #define BWI_MAC_STATUS 0x120
152 #define BWI_MAC_STATUS_ENABLE __BIT(0)
153 #define BWI_MAC_STATUS_UCODE_START __BIT(1)
154 #define BWI_MAC_STATUS_UCODE_JUMP0 __BIT(2)
155 #define BWI_MAC_STATUS_IHREN __BIT(10)
156 #define BWI_MAC_STATUS_GPOSEL_MASK __BITS(15, 14)
157 #define BWI_MAC_STATUS_BSWAP __BIT(16)
158 #define BWI_MAC_STATUS_INFRA __BIT(17)
159 #define BWI_MAC_STATUS_OPMODE_HOSTAP __BIT(18)
160 #define BWI_MAC_STATUS_RFLOCK __BIT(19)
161 #define BWI_MAC_STATUS_PASS_BCN __BIT(20)
162 #define BWI_MAC_STATUS_PASS_BADPLCP __BIT(21)
163 #define BWI_MAC_STATUS_PASS_CTL __BIT(22)
164 #define BWI_MAC_STATUS_PASS_BADFCS __BIT(23)
165 #define BWI_MAC_STATUS_PROMISC __BIT(24)
166 #define BWI_MAC_STATUS_HW_PS __BIT(25)
167 #define BWI_MAC_STATUS_WAKEUP __BIT(26)
168 #define BWI_MAC_STATUS_PHYLNK __BIT(31)
170 #define BWI_MAC_INTR_STATUS 0x128
171 #define BWI_MAC_INTR_MASK 0x12c
173 #define BWI_MAC_TMPLT_CTRL 0x130
174 #define BWI_MAC_TMPLT_DATA 0x134
176 #define BWI_MAC_PS_STATUS 0x140
178 #define BWI_MOBJ_CTRL 0x160
179 #define BWI_MOBJ_CTRL_VAL(objid, ofs) ((objid) << 16 | (ofs))
180 #define BWI_MOBJ_DATA 0x164
181 #define BWI_MOBJ_DATA_UNALIGN 0x166
185 #define BWI_WR_MOBJ_AUTOINC 0x100 /* Auto-increment wr */
186 #define BWI_RD_MOBJ_AUTOINC 0x200 /* Auto-increment rd */
187 /* Firmware ucode object */
188 #define BWI_FW_UCODE_MOBJ 0x0
190 #define BWI_COMM_MOBJ 0x1
191 #define BWI_COMM_MOBJ_FWREV 0x0
192 #define BWI_COMM_MOBJ_FWPATCHLV 0x2
193 #define BWI_COMM_MOBJ_SLOTTIME 0x10
194 #define BWI_COMM_MOBJ_MACREV 0x16
195 #define BWI_COMM_MOBJ_TX_ACK 0x22
196 #define BWI_COMM_MOBJ_UCODE_STATE 0x40
197 #define BWI_COMM_MOBJ_SHRETRY_FB 0x44
198 #define BWI_COMM_MOBJ_LGRETEY_FB 0x46
199 #define BWI_COMM_MOBJ_TX_BEACON 0x54
200 #define BWI_COMM_MOBJ_KEYTABLE_OFS 0x56
201 #define BWI_COMM_MOBJ_TSSI_DS 0x58
202 #define BWI_COMM_MOBJ_HFLAGS_LO 0x5e
203 #define BWI_COMM_MOBJ_HFLAGS_MI 0x60
204 #define BWI_COMM_MOBJ_HFLAGS_HI 0x62
205 #define BWI_COMM_MOBJ_RF_ATTEN 0x64
206 #define BWI_COMM_MOBJ_TSSI_OFDM 0x70
207 #define BWI_COMM_MOBJ_PROBE_RESP_TO 0x74
208 #define BWI_COMM_MOBJ_CHAN 0xa0
209 #define BWI_COMM_MOBJ_KEY_ALGO 0x100
210 #define BWI_COMM_MOBJ_TX_PROBE_RESP 0x188
211 #define BWI_HFLAG_AUTO_ANTDIV 0x1ULL
212 #define BWI_HFLAG_SYM_WA 0x2ULL /* ??? SYM work around */
213 #define BWI_HFLAG_PWR_BOOST_DS 0x8ULL
214 #define BWI_HFLAG_GDC_WA 0x20ULL /* ??? GDC work around */
215 #define BWI_HFLAG_OFDM_PA 0x40ULL
216 #define BWI_HFLAG_NOT_JAPAN 0x80ULL
217 #define BWI_HFLAG_MAGIC1 0x200ULL
218 #define BWI_UCODE_STATE_PS 4
219 #define BWI_LO_TSSI_MASK __BITS(7, 0)
220 #define BWI_HI_TSSI_MASK __BITS(15, 8)
221 #define BWI_INVALID_TSSI 0x7f
223 #define BWI_80211_MOBJ 0x2
224 #define BWI_80211_MOBJ_CWMIN 0xc
225 #define BWI_80211_MOBJ_CWMAX 0x10
226 #define BWI_80211_MOBJ_SHRETRY 0x18
227 #define BWI_80211_MOBJ_LGRETRY 0x1c
228 /* Firmware PCM object */
229 #define BWI_FW_PCM_MOBJ 0x3
230 /* MAC address of pairwise keys */
231 #define BWI_PKEY_ADDR_MOBJ 0x4
233 #define BWI_TXSTATUS0 0x170
234 #define BWI_TXSTATUS0_VALID __BIT(0)
235 #define BWI_TXSTATUS0_ACKED __BIT(1)
236 #define BWI_TXSTATUS0_FREASON_MASK __BITS(4, 2) /* Failure reason */
237 #define BWI_TXSTATUS0_AMPDU __BIT(5)
238 #define BWI_TXSTATUS0_PENDING __BIT(6)
239 #define BWI_TXSTATUS0_PM __BIT(7)
240 #define BWI_TXSTATUS0_RTS_TXCNT_MASK __BITS(11, 8)
241 #define BWI_TXSTATUS0_DATA_TXCNT_MASK __BITS(15, 12)
242 #define BWI_TXSTATUS0_TXID_MASK __BITS(31, 16)
243 #define BWI_TXSTATUS1 0x174
245 #define BWI_TXRX_CTRL_BASE 0x200
246 #define BWI_TX32_CTRL 0x0
247 #define BWI_TX32_RINGINFO 0x4
248 #define BWI_TX32_INDEX 0x8
249 #define BWI_TX32_STATUS 0xc
250 #define BWI_TX32_STATUS_STATE_MASK __BITS(15, 12)
251 #define BWI_TX32_STATUS_STATE_DISABLED 0
252 #define BWI_TX32_STATUS_STATE_IDLE 2
253 #define BWI_TX32_STATUS_STATE_STOPPED 3
254 #define BWI_RX32_CTRL 0x10
255 #define BWI_RX32_CTRL_HDRSZ_MASK __BITS(7, 1)
256 #define BWI_RX32_RINGINFO 0x14
257 #define BWI_RX32_INDEX 0x18
258 #define BWI_RX32_STATUS 0x1c
259 #define BWI_RX32_STATUS_INDEX_MASK __BITS(11, 0)
260 #define BWI_RX32_STATUS_STATE_MASK __BITS(15, 12)
261 #define BWI_RX32_STATUS_STATE_DISABLED 0
262 /* Shared by 32bit TX/RX CTRL */
263 #define BWI_TXRX32_CTRL_ENABLE __BIT(0)
264 #define BWI_TXRX32_CTRL_ADDRHI_MASK __BITS(17, 16)
265 /* Shared by 32bit TX/RX RINGINFO */
266 #define BWI_TXRX32_RINGINFO_FUNC_TXRX 0x1
267 #define BWI_TXRX32_RINGINFO_FUNC_MASK __BITS(31, 30)
268 #define BWI_TXRX32_RINGINFO_ADDR_MASK __BITS(29, 0)
270 #define BWI_PHYINFO 0x3e0
271 #define BWI_PHYINFO_REV_MASK __BITS(3, 0)
272 #define BWI_PHYINFO_TYPE_MASK __BITS(11, 8)
273 #define BWI_PHYINFO_TYPE_11A 0
274 #define BWI_PHYINFO_TYPE_11B 1
275 #define BWI_PHYINFO_TYPE_11G 2
276 #define BWI_PHYINFO_TYPE_11N 5
277 #define BWI_PHYINFO_VER_MASK __BITS(15, 12)
279 #define BWI_RF_ANTDIV 0x3e2 /* Antenna Diversity?? */
281 #define BWI_PHY_MAGIC_REG1 0x3e4
282 #define BWI_PHY_MAGIC_REG1_VAL1 0x3000
283 #define BWI_PHY_MAGIC_REG1_VAL2 0x9
285 #define BWI_BBP_ATTEN 0x3e6
286 #define BWI_BBP_ATTEN_MAGIC 0xf4
287 #define BWI_BBP_ATTEN_MAGIC2 0x8140
289 #define BWI_BPHY_CTRL 0x3ec
290 #define BWI_BPHY_CTRL_INIT 0x3f22
292 #define BWI_RF_CHAN 0x3f0
293 #define BWI_RF_CHAN_EX 0x3f4
295 #define BWI_RF_CTRL 0x3f6
296 /* Register values for BWI_RF_CTRL */
297 #define BWI_RF_CTRL_RFINFO 0x1
298 /* XXX extra bits for reading from radio */
299 #define BWI_RF_CTRL_RD_11A 0x40
300 #define BWI_RF_CTRL_RD_11BG 0x80
301 #define BWI_RF_DATA_HI 0x3f8
302 #define BWI_RF_DATA_LO 0x3fa
303 /* Values read from BWI_RF_DATA_{HI,LO} after BWI_RF_CTRL_RFINFO */
304 #define BWI_RFINFO_MANUFACT_MASK __BITS(11, 0)
305 #define BWI_RF_MANUFACT_BCM 0x17f /* XXX */
306 #define BWI_RFINFO_TYPE_MASK __BITS(27, 12)
307 #define BWI_RF_T_BCM2050 0x2050
308 #define BWI_RF_T_BCM2053 0x2053
309 #define BWI_RF_T_BCM2060 0x2060
310 #define BWI_RFINFO_REV_MASK __BITS(31, 28)
312 #define BWI_PHY_CTRL 0x3fc
313 #define BWI_PHY_DATA 0x3fe
315 #define BWI_ADDR_FILTER_CTRL 0x420
316 #define BWI_ADDR_FILTER_CTRL_SET 0x20
317 #define BWI_ADDR_FILTER_MYADDR 0
318 #define BWI_ADDR_FILTER_BSSID 3
319 #define BWI_ADDR_FILTER_DATA 0x422
321 #define BWI_MAC_GPIO_CTRL 0x49c
322 #define BWI_MAC_GPIO_MASK 0x49e
323 #define BWI_MAC_PRE_TBTT 0x612
324 #define BWI_MAC_SLOTTIME 0x684
325 #define BWI_MAC_SLOTTIME_ADJUST 510
326 #define BWI_MAC_POWERUP_DELAY 0x6a8
333 * If common regwin exists, then it is within common regwin,
334 * else it is in bus regwin.
336 #define BWI_GPIO_CTRL 0x6c
339 * Extended PCI registers
341 #define BWI_PCIR_BAR PCIR_BAR(0)
342 #define BWI_PCIR_SEL_REGWIN 0x80
343 /* Register value for BWI_PCIR_SEL_REGWIN */
344 #define BWI_PCIM_REGWIN(id) (((id) * 0x1000) + 0x18000000)
345 #define BWI_PCIR_GPIO_IN 0xb0
346 #define BWI_PCIR_GPIO_OUT 0xb4
347 #define BWI_PCIM_GPIO_OUT_CLKSRC __BIT(4)
348 #define BWI_PCIR_GPIO_ENABLE 0xb8
349 /* Register values for BWI_PCIR_GPIO_{IN,OUT,ENABLE} */
350 #define BWI_PCIM_GPIO_PWR_ON __BIT(6)
351 #define BWI_PCIM_GPIO_PLL_PWR_OFF __BIT(7)
352 #define BWI_PCIR_INTCTL 0x94
357 #define BWI_PCI_SUBDEVICE_BU4306 0x416
358 #define BWI_PCI_SUBDEVICE_BCM4309G 0x421
360 #define BWI_IS_BRCM_BU4306(sc) \
361 ((sc)->sc_pci_subvid == PCI_VENDOR_BROADCOM && \
362 (sc)->sc_pci_subdid == BWI_PCI_SUBDEVICE_BU4306)
363 #define BWI_IS_BRCM_BCM4309G(sc) \
364 ((sc)->sc_pci_subvid == PCI_VENDOR_BROADCOM && \
365 (sc)->sc_pci_subdid == BWI_PCI_SUBDEVICE_BCM4309G)
368 * EEPROM start address
370 #define BWI_SPROM_START 0x1000
371 #define BWI_SPROM_11BG_EADDR 0x48
372 #define BWI_SPROM_11A_EADDR 0x54
373 #define BWI_SPROM_CARD_INFO 0x5c
374 #define BWI_SPROM_CARD_INFO_LOCALE __BITS(11, 8)
375 #define BWI_SPROM_LOCALE_JAPAN 5
376 #define BWI_SPROM_PA_PARAM_11BG 0x5e
377 #define BWI_SPROM_GPIO01 0x64
378 #define BWI_SPROM_GPIO_0 __BITS(7, 0)
379 #define BWI_SPROM_GPIO_1 __BITS(15, 8)
380 #define BWI_SPROM_GPIO23 0x66
381 #define BWI_SPROM_GPIO_2 __BITS(7, 0)
382 #define BWI_SPROM_GPIO_3 __BITS(15, 8)
383 #define BWI_SPROM_MAX_TXPWR 0x68
384 #define BWI_SPROM_MAX_TXPWR_MASK_11BG __BITS(7, 0) /* XXX */
385 #define BWI_SPROM_MAX_TXPWR_MASK_11A __BITS(15, 8) /* XXX */
386 #define BWI_SPROM_PA_PARAM_11A 0x6a
387 #define BWI_SPROM_IDLE_TSSI 0x70
388 #define BWI_SPROM_IDLE_TSSI_MASK_11BG __BITS(7, 0) /* XXX */
389 #define BWI_SPROM_IDLE_TSSI_MASK_11A __BITS(15, 8) /* XXX */
390 #define BWI_SPROM_CARD_FLAGS 0x72
391 #define BWI_SPROM_ANT_GAIN 0x74
392 #define BWI_SPROM_ANT_GAIN_MASK_11A __BITS(7, 0)
393 #define BWI_SPROM_ANT_GAIN_MASK_11BG __BITS(15, 8)
398 #define BWI_CARD_F_PA_GPIO9 __BIT(1) /* GPIO 9 controls PA */
399 #define BWI_CARD_F_SW_NRSSI __BIT(3)
400 #define BWI_CARD_F_NO_SLOWCLK __BIT(5) /* no slow clock */
401 #define BWI_CARD_F_EXT_LNA __BIT(12) /* external LNA */
402 #define BWI_CARD_F_ALT_IQ __BIT(15) /* alternate I/Q */
407 #define BWI_LED_ACT_LOW __BIT(7)
408 #define BWI_LED_ACT_MASK __BITS(6, 0)
409 #define BWI_LED_ACT_OFF 0
410 #define BWI_LED_ACT_ON 1
411 #define BWI_LED_ACT_BLINK 2
412 #define BWI_LED_ACT_RF_ENABLED 3
413 #define BWI_LED_ACT_5GHZ 4
414 #define BWI_LED_ACT_2GHZ 5
415 #define BWI_LED_ACT_11G 6
416 #define BWI_LED_ACT_BLINK_SLOW 7
417 #define BWI_LED_ACT_BLINK_POLL 8
418 #define BWI_LED_ACT_UNKN 9
419 #define BWI_LED_ACT_ASSOC 10
420 #define BWI_LED_ACT_NULL 11
422 #define BWI_VENDOR_LED_ACT_COMPAQ \
423 BWI_LED_ACT_RF_ENABLED, \
428 #define BWI_VENDOR_LED_ACT_LINKSYS \
434 #define BWI_VENDOR_LED_ACT_DEFAULT \
443 #define BWI_BBPID_BCM4301 0x4301
444 #define BWI_BBPID_BCM4306 0x4306
445 #define BWI_BBPID_BCM4317 0x4317
446 #define BWI_BBPID_BCM4320 0x4320
447 #define BWI_BBPID_BCM4321 0x4321
450 * Register window types
452 #define BWI_REGWIN_T_COM 0x800
453 #define BWI_REGWIN_T_BUSPCI 0x804
454 #define BWI_REGWIN_T_MAC 0x812
455 #define BWI_REGWIN_T_BUSPCIE 0x820
460 #define BWI_INTR_READY __BIT(0)
461 #define BWI_INTR_BEACON __BIT(1)
462 #define BWI_INTR_TBTT __BIT(2)
463 #define BWI_INTR_EO_ATIM __BIT(5) /* End of ATIM */
464 #define BWI_INTR_PMQ __BIT(6) /* XXX?? */
465 #define BWI_INTR_MAC_TXERR __BIT(9)
466 #define BWI_INTR_PHY_TXERR __BIT(11)
467 #define BWI_INTR_TIMER1 __BIT(14)
468 #define BWI_INTR_RX_DONE __BIT(15)
469 #define BWI_INTR_TX_FIFO __BIT(16) /* XXX?? */
470 #define BWI_INTR_NOISE __BIT(18)
471 #define BWI_INTR_RF_DISABLED __BIT(28)
472 #define BWI_INTR_TX_DONE __BIT(29)
474 #define BWI_INIT_INTRS \
475 (BWI_INTR_READY | BWI_INTR_BEACON | BWI_INTR_TBTT | \
476 BWI_INTR_EO_ATIM | BWI_INTR_PMQ | BWI_INTR_MAC_TXERR | \
477 BWI_INTR_PHY_TXERR | BWI_INTR_RX_DONE | BWI_INTR_TX_FIFO | \
478 BWI_INTR_NOISE | BWI_INTR_RF_DISABLED | BWI_INTR_TX_DONE)
479 #define BWI_ALL_INTRS 0xffffffff
484 #define BWI_TXRX_INTR_ERROR (__BIT(15) | __BIT(14) | __BITS(12, 10))
485 #define BWI_TXRX_INTR_RX __BIT(16)
486 #define BWI_TXRX_TX_INTRS BWI_TXRX_INTR_ERROR
487 #define BWI_TXRX_RX_INTRS (BWI_TXRX_INTR_ERROR | BWI_TXRX_INTR_RX)
488 #define BWI_TXRX_IS_RX(i) ((i) % 3 == 0)
490 #endif /* !_IF_BWIREG_H */