2 * Copyright (c) 2004, Joerg Sonnenberger <joerg@bec.de>
4 * Copyright (c) 1994,1995 Stefan Esser. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice unmodified, this list of conditions, and the following
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 * $DragonFly: src/sys/bus/pci/pci_pcib.c,v 1.6 2006/10/25 20:55:51 dillon Exp $
32 #include <sys/param.h>
34 #include <sys/kernel.h>
35 #include <sys/malloc.h>
36 #include <sys/module.h>
38 #include <sys/systm.h>
40 #include <bus/pci/pcivar.h>
41 #include <bus/pci/pcireg.h>
43 #include "pcib_private.h"
45 static devclass_t pcib_devclass;
48 * Attach a pci bus device to a motherboard or pci-to-pci bridge bus.
49 * Due to probe recursion it is possible for pci-to-pci bridges (such as
50 * on the DELL2550) to attach before all the motherboard bridges have
51 * attached. We must call device_add_child() with the secondary id
52 * rather then -1 in order to ensure that we do not accidently use
53 * a motherboard PCI id, otherwise the device probe will believe that
54 * the later motherboard bridge bus has already been probed and refuse
55 * to probe it. The result: disappearing busses!
57 * Bridges will cause recursions or duplicate attach attempts. If
58 * we have already attached this bus we don't do it again!
60 * NOTE THE DEVICE TOPOLOGY!
62 * [pcibX]->[pciX]->[pciX.Y]
65 * When attaching a new bus device note that the PCI methods are
66 * based in the parent device, but the device ivars for those methods
67 * are based in our sub-device. The PCI accessor functions all assume
68 * you are passing-in the sub-device.
71 pcib_attach_common(device_t dev)
73 struct pcib_softc *sc;
76 sc = device_get_softc(dev);
80 * Get current bridge configuration.
82 sc->command = pci_read_config(dev, PCIR_COMMAND, 1);
83 sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1);
84 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1);
85 sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2);
86 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2);
87 sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1);
90 * Determine current I/O decode.
92 if (sc->command & PCIM_CMD_PORTEN) {
93 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1);
94 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
95 sc->iobase = PCI_PPBIOBASE(pci_read_config(dev, PCIR_IOBASEH_1, 2),
96 pci_read_config(dev, PCIR_IOBASEL_1, 1));
98 sc->iobase = PCI_PPBIOBASE(0, pci_read_config(dev, PCIR_IOBASEL_1, 1));
101 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1);
102 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
103 sc->iolimit = PCI_PPBIOLIMIT(pci_read_config(dev, PCIR_IOLIMITH_1, 2),
104 pci_read_config(dev, PCIR_IOLIMITL_1, 1));
106 sc->iolimit = PCI_PPBIOLIMIT(0, pci_read_config(dev, PCIR_IOLIMITL_1, 1));
111 * Determine current memory decode.
113 if (sc->command & PCIM_CMD_MEMEN) {
114 sc->membase = PCI_PPBMEMBASE(0, pci_read_config(dev, PCIR_MEMBASE_1, 2));
115 sc->memlimit = PCI_PPBMEMLIMIT(0, pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
116 sc->pmembase = PCI_PPBMEMBASE((pci_addr_t)pci_read_config(dev, PCIR_PMBASEH_1, 4),
117 pci_read_config(dev, PCIR_PMBASEL_1, 2));
118 sc->pmemlimit = PCI_PPBMEMLIMIT((pci_addr_t)pci_read_config(dev, PCIR_PMLIMITH_1, 4),
119 pci_read_config(dev, PCIR_PMLIMITL_1, 2));
125 switch (pci_get_devid(dev)) {
126 case 0x12258086: /* Intel 82454KX/GX (Orion) */
130 supbus = pci_read_config(dev, 0x41, 1);
131 if (supbus != 0xff) {
132 sc->secbus = supbus + 1;
133 sc->subbus = supbus + 1;
139 * The i82380FB mobile docking controller is a PCI-PCI bridge,
140 * and it is a subtractive bridge. However, the ProgIf is wrong
141 * so the normal setting of PCIB_SUBTRACTIVE bit doesn't
142 * happen. There's also a Toshiba bridge that behaves this
145 case 0x124b8086: /* Intel 82380FB Mobile */
146 case 0x060513d7: /* Toshiba ???? */
147 sc->flags |= PCIB_SUBTRACTIVE;
152 * Intel 815, 845 and other chipsets say they are PCI-PCI bridges,
153 * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM,
154 * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese.
155 * This means they act as if they were subtractively decoding
156 * bridges and pass all transactions. Mark them and real ProgIf 1
157 * parts as subtractive.
159 if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 ||
160 pci_read_config(dev, PCIR_PROGIF, 1) == 1)
161 sc->flags |= PCIB_SUBTRACTIVE;
164 device_printf(dev, " secondary bus %d\n", sc->secbus);
165 device_printf(dev, " subordinate bus %d\n", sc->subbus);
166 device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, sc->iolimit);
167 device_printf(dev, " memory decode 0x%x-0x%x\n", sc->membase, sc->memlimit);
168 device_printf(dev, " prefetched decode 0x%x-0x%x\n", sc->pmembase, sc->pmemlimit);
169 if (sc->flags & PCIB_SUBTRACTIVE)
170 device_printf(dev, " Subtractively decoded bridge.\n");
174 * XXX If the secondary bus number is zero, we should assign a bus number
175 * since the BIOS hasn't, then initialise the bridge.
179 * XXX If the subordinate bus number is less than the secondary bus number,
180 * we should pick a better value. One sensible alternative would be to
181 * pick 255; the only tradeoff here is that configuration transactions
182 * would be more widely routed than absolutely necessary.
187 * Called with the bridge candidate, which is under a PCI slot device.
188 * Note that the ivars are stored in the candidate.
191 pci_match_bridge(device_t dev)
193 switch (pci_get_devid(dev)) {
194 /* Intel -- vendor 0x8086 */
196 return ("Intel 82443LX (440 LX) PCI-PCI (AGP) bridge");
198 return ("Intel 82443BX (440 BX) PCI-PCI (AGP) bridge");
200 return ("Intel 82443GX (440 GX) PCI-PCI (AGP) bridge");
202 return ("Intel 82454NX PCI Expander Bridge");
204 return ("Intel 82801BA/BAM (ICH2) PCI-PCI (AGP) bridge");
206 return ("Intel 82380FB mobile PCI to PCI bridge");
208 return ("Intel 82801AA (ICH) Hub to PCI bridge");
210 return ("Intel 82801AB (ICH0) Hub to PCI bridge");
212 return ("Intel 82801BA/CA/DB/EB/FB (ICH2/3/4/5/6) Hub to PCI bridge");
214 return ("Intel 82845 PCI-PCI (AGP) bridge");
216 /* VLSI -- vendor 0x1004 */
218 return ("VLSI 82C534 Eagle II PCI Bus bridge");
220 return ("VLSI 82C538 Eagle II PCI Docking bridge");
222 /* VIA Technologies -- vendor 0x1106 */
224 return ("VIA 8363 (Apollo KT133) PCI-PCI (AGP) bridge");
226 return ("VIA 82C598MVP (Apollo MVP3) PCI-PCI (AGP) bridge");
227 /* Exclude the ACPI function of VT82Cxxx series */
233 /* AcerLabs -- vendor 0x10b9 */
234 /* Funny : The datasheet told me vendor id is "10b8",sub-vendor */
235 /* id is '10b9" but the register always shows "10b9". -Foxfair */
237 return ("AcerLabs M5247 PCI-PCI(AGP Supported) bridge");
238 case 0x524310b9:/* 5243 seems like 5247, need more info to divide*/
239 return ("AcerLabs M5243 PCI-PCI bridge");
241 /* AMD -- vendor 0x1022 */
243 return ("AMD-751 PCI-PCI (1x/2x AGP) bridge");
245 return ("AMD-761 PCI-PCI (4x AGP) bridge");
247 /* DEC -- vendor 0x1011 */
249 return ("DEC 21050 PCI-PCI bridge");
251 return ("DEC 21052 PCI-PCI bridge");
253 return ("DEC 21150 PCI-PCI bridge");
255 return ("DEC 21152 PCI-PCI bridge");
257 return ("DEC 21153 PCI-PCI bridge");
259 return ("DEC 21154 PCI-PCI bridge");
261 /* NVIDIA -- vendor 0x10de */
264 return ("NVIDIA nForce2 PCI-PCI bridge");
268 return ("IBM 82351 PCI-PCI bridge");
269 /* UMC United Microelectronics 0x1060 */
271 return ("UMC UM8881 HB4 486 PCI Chipset");
274 if (pci_get_class(dev) == PCIC_BRIDGE
275 && pci_get_subclass(dev) == PCIS_BRIDGE_PCI) {
276 return pci_bridge_type(dev);
283 * bus/pci/i386/pcibus.c added "pcib" devices under "pci" (slot) devices,
284 * causing us to probe and attach here.
286 * Note that the parent "pci" device has stored ivars in our device. We
287 * are both a "pci" device and potentially a "pcib" device.
290 pcib_probe(device_t dev)
294 desc = pci_match_bridge(dev);
296 device_set_desc_copy(dev, desc);
304 * Note that the "pci" device ivars are stored in the ivar data field
305 * for our device. The "pcib" device ivars are stored in the softc
309 pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
311 struct pcib_softc *sc = device_get_softc(dev);
315 *result = sc->secbus;
322 pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
324 struct pcib_softc *sc = device_get_softc(dev);
335 pcib_attach(device_t dev)
337 struct pcib_softc *sc;
339 pcib_attach_common(dev);
340 sc = device_get_softc(dev);
341 /*chipset_attach(dev, device_get_unit(dev));*/
344 * The pcib unit is not really under our control because
345 * we have are not (XXX) using the identify interface to
346 * assign the bridge driver, instead letting subr_bus do
347 * it via the probe mechanism. However, we *do* directly
348 * create the "pci" children and we can control the unit
349 * number we assign for those. We assign the secondary bus
350 * id as the unit number.
352 if (sc->secbus != 0) {
353 if (devclass_find_unit("pci", sc->secbus)) {
354 device_printf(dev, "Duplicate secondary bus %d, "
355 "cannot attach bridge\n",
359 device_add_child(dev, "pci", sc->secbus);
360 bus_generic_attach(dev);
367 * Is the prefetch window open (eg, can we allocate memory in it?)
370 pcib_is_prefetch_open(struct pcib_softc *sc)
372 return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit);
376 * Is the nonprefetch window open (eg, can we allocate memory in it?)
379 pcib_is_nonprefetch_open(struct pcib_softc *sc)
381 return (sc->membase > 0 && sc->membase < sc->memlimit);
385 * Is the io window open (eg, can we allocate ports in it?)
388 pcib_is_io_open(struct pcib_softc *sc)
390 return (sc->iobase > 0 && sc->iobase < sc->iolimit);
394 * We have to trap resource allocation requests and ensure that the bridge
395 * is set up to, or capable of handling them.
398 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
399 u_long start, u_long end, u_long count, u_int flags)
401 struct pcib_softc *sc = device_get_softc(dev);
405 * Fail the allocation for this range if it's not supported.
410 if (!pcib_is_io_open(sc))
412 ok = (start >= sc->iobase && end <= sc->iolimit);
413 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
415 if (start < sc->iobase)
417 if (end > sc->iolimit)
423 if (start < sc->iobase && end > sc->iolimit) {
430 device_printf(dev, "ioport: end (%lx) < start (%lx)\n", end, start);
436 device_printf(dev, "device %s requested unsupported I/O "
437 "range 0x%lx-0x%lx (decoding 0x%x-0x%x)\n",
438 device_get_nameunit(child), start, end,
439 sc->iobase, sc->iolimit);
443 device_printf(dev, "device %s requested decoded I/O range 0x%lx-0x%lx\n",
444 device_get_nameunit(child), start, end);
449 if (pcib_is_nonprefetch_open(sc))
450 ok = ok || (start >= sc->membase && end <= sc->memlimit);
451 if (pcib_is_prefetch_open(sc))
452 ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit);
453 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
456 if (flags & RF_PREFETCHABLE) {
457 if (pcib_is_prefetch_open(sc)) {
458 if (start < sc->pmembase)
459 start = sc->pmembase;
460 if (end > sc->pmemlimit)
465 } else { /* non-prefetchable */
466 if (pcib_is_nonprefetch_open(sc)) {
467 if (start < sc->membase)
469 if (end > sc->memlimit)
477 ok = 1; /* subtractive bridge: always ok */
479 if (pcib_is_nonprefetch_open(sc)) {
480 if (start < sc->membase && end > sc->memlimit) {
485 if (pcib_is_prefetch_open(sc)) {
486 if (start < sc->pmembase && end > sc->pmemlimit) {
487 start = sc->pmembase;
494 device_printf(dev, "memory: end (%lx) < start (%lx)\n", end, start);
499 if (!ok && bootverbose)
501 "device %s requested unsupported memory range "
502 "0x%lx-0x%lx (decoding 0x%x-0x%x, 0x%x-0x%x)\n",
503 device_get_nameunit(child), start, end,
504 sc->membase, sc->memlimit, sc->pmembase,
509 device_printf(dev,"device %s requested decoded memory range 0x%lx-0x%lx\n",
510 device_get_nameunit(child), start, end);
517 * Bridge is OK decoding this resource, so pass it up.
519 return (bus_generic_alloc_resource(dev, child, type, rid, start, end, count, flags));
523 pcib_maxslots(device_t dev)
529 pcib_read_config(device_t dev, int b, int s, int f,
533 * Pass through to the next ppb up the chain (i.e. our
536 * [pcibX]->[pciX]->[pciX.Y]
539 * getting back to this point.
541 return PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)),
542 b, s, f, reg, width);
546 pcib_write_config(device_t dev, int b, int s, int f,
547 int reg, uint32_t val, int width)
550 * Pass through to the next ppb up the chain (i.e. our
553 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)),
554 b, s, f, reg, val, width);
558 * Route an interrupt across a PCI bridge.
560 * pcib - is the pci bridge device
561 * dev - is the device
564 pcib_route_interrupt(device_t pcib, device_t dev, int pin)
572 * The PCI standard defines a swizzle of the child-side device/intpin
573 * to the parent-side intpin as follows.
575 * device = device on child bus
576 * child_intpin = intpin on child bus slot (0-3)
577 * parent_intpin = intpin on parent bus slot (0-3)
579 * parent_intpin = (device + child_intpin) % 4
581 parent_intpin = (pci_get_slot(pcib) + (pin - 1)) % 4;
584 * Our parent is a PCI bus. Its parent must export the pci interface
585 * which includes the ability to route interrupts.
587 bus = device_get_parent(pcib);
588 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib,
590 device_printf(pcib, "routed slot %d INT%c to irq %d\n",
591 pci_get_slot(dev), 'A' + pin - 1, intnum);
596 * Try to read the bus number of a host-PCI bridge using appropriate config
600 host_pcib_get_busno(pci_read_config_fn read_config, int bus, int slot, int func,
605 id = read_config(bus, slot, func, PCIR_DEVVENDOR, 4);
606 if (id == 0xffffffff)
612 /* XXX This is a guess */
613 /* *busnum = read_config(bus, slot, func, 0x41, 1); */
617 /* Intel 82454KX/GX (Orion) */
618 *busnum = read_config(bus, slot, func, 0x4a, 1);
622 * For the 450nx chipset, there is a whole bundle of
623 * things pretending to be host bridges. The MIOC will
624 * be seen first and isn't really a pci bridge (the
625 * actual busses are attached to the PXB's). We need to
626 * read the registers of the MIOC to figure out the
627 * bus numbers for the PXB channels.
629 * Since the MIOC doesn't have a pci bus attached, we
630 * pretend it wasn't there.
636 /* Intel 82454NX PXB#0, Bus#A */
637 *busnum = read_config(bus, 0x10, func, 0xd0, 1);
640 /* Intel 82454NX PXB#0, Bus#B */
641 *busnum = read_config(bus, 0x10, func, 0xd1, 1) + 1;
644 /* Intel 82454NX PXB#1, Bus#A */
645 *busnum = read_config(bus, 0x10, func, 0xd3, 1);
648 /* Intel 82454NX PXB#1, Bus#B */
649 *busnum = read_config(bus, 0x10, func, 0xd4, 1) + 1;
654 /* ServerWorks -- vendor 0x1166 */
666 *busnum = read_config(bus, slot, func, 0x44, 1);
669 /* Don't know how to read bus number. */
676 static device_method_t pcib_methods[] = {
677 /* Device interface */
678 DEVMETHOD(device_probe, pcib_probe),
679 DEVMETHOD(device_attach, pcib_attach),
680 DEVMETHOD(device_shutdown, bus_generic_shutdown),
681 DEVMETHOD(device_suspend, bus_generic_suspend),
682 DEVMETHOD(device_resume, bus_generic_resume),
685 DEVMETHOD(bus_print_child, bus_generic_print_child),
686 DEVMETHOD(bus_read_ivar, pcib_read_ivar),
687 DEVMETHOD(bus_write_ivar, pcib_write_ivar),
688 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource),
689 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
690 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
691 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
692 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
693 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
696 DEVMETHOD(pcib_maxslots, pcib_maxslots),
697 DEVMETHOD(pcib_read_config, pcib_read_config),
698 DEVMETHOD(pcib_write_config, pcib_write_config),
699 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt),
704 static driver_t pcib_driver = {
707 sizeof(struct pcib_softc)
710 DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0);