1 /* $NetBSD: midway.c,v 1.30 1997/09/29 17:40:38 chuck Exp $ */
2 /* (sync'd to midway.c 1.68) */
6 * Copyright (c) 1996 Charles D. Cranor and Washington University.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by Charles D. Cranor and
20 * Washington University.
21 * 4. The name of the author may not be used to endorse or promote products
22 * derived from this software without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
33 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 * $FreeBSD: src/sys/dev/en/midway.c,v 1.19.2.1 2003/01/23 21:06:42 sam Exp $
36 * $DragonFly: src/sys/dev/atm/en/midway.c,v 1.21 2005/11/28 17:13:37 dillon Exp $
41 * m i d w a y . c e n i 1 5 5 d r i v e r
43 * author: Chuck Cranor <chuck@ccrc.wustl.edu>
44 * started: spring, 1996 (written from scratch).
46 * notes from the author:
47 * Extra special thanks go to Werner Almesberger, EPFL LRC. Werner's
48 * ENI driver was especially useful in figuring out how this card works.
49 * I would also like to thank Werner for promptly answering email and being
54 #undef EN_DEBUG_RANGE /* check ranges on en_read/en_write's? */
55 #define EN_MBUF_OPT /* try and put more stuff in mbuf? */
59 #define EN_DMA 1 /* use dma? */
61 #define EN_NOTXDMA 0 /* hook to disable tx dma only */
62 #define EN_NORXDMA 0 /* hook to disable rx dma only */
63 #define EN_DDBHOOK 1 /* compile in ddb functions */
64 #if defined(MIDWAY_ADPONLY)
65 #define EN_ENIDMAFIX 0 /* no ENI cards to worry about */
67 #define EN_ENIDMAFIX 1 /* avoid byte DMA on the ENI card (see below) */
71 * note on EN_ENIDMAFIX: the byte aligner on the ENI version of the card
72 * appears to be broken. it works just fine if there is no load... however
73 * when the card is loaded the data get corrupted. to see this, one only
74 * has to use "telnet" over ATM. do the following command in "telnet":
75 * cat /usr/share/misc/termcap
76 * "telnet" seems to generate lots of 1023 byte mbufs (which make great
77 * use of the byte aligner). watch "netstat -s" for checksum errors.
79 * I further tested this by adding a function that compared the transmit
80 * data on the card's SRAM with the data in the mbuf chain _after_ the
81 * "transmit DMA complete" interrupt. using the "telnet" test I got data
82 * mismatches where the byte-aligned data should have been. using ddb
83 * and en_dumpmem() I verified that the DTQs fed into the card were
84 * absolutely correct. thus, we are forced to concluded that the ENI
85 * hardware is buggy. note that the Adaptec version of the card works
86 * just fine with byte DMA.
88 * bottom line: we set EN_ENIDMAFIX to 1 to avoid byte DMAs on the ENI
92 #if defined(DIAGNOSTIC) && !defined(EN_DIAG)
93 #define EN_DIAG /* link in with master DIAG option */
96 #define EN_COUNT(X) (X)++
98 #define EN_COUNT(X) /* nothing */
104 #define STATIC /* nothing */
105 #define INLINE /* nothing */
107 #define STATIC static
108 #define INLINE __inline
109 #endif /* EN_DEBUG */
111 #include "use_en.h" /* XXX for midwayvar.h's NEN */
112 #include "opt_inet.h"
113 #include "opt_natm.h"
115 /* enable DDBHOOK when DDB is available */
121 #include <sys/param.h>
122 #include <sys/systm.h>
123 #include <sys/queue.h>
124 #include <sys/sockio.h>
125 #include <sys/mbuf.h>
126 #include <sys/socket.h>
127 #include <sys/proc.h>
128 #include <sys/thread2.h>
131 #include <net/if_atm.h>
135 #if defined(INET) || defined(INET6)
136 #include <netinet/in.h>
137 #include <netinet/if_atm.h>
141 #include <netproto/natm/natm.h>
144 #include "midwayreg.h"
145 #include "midwayvar.h"
146 #include <vm/pmap.h> /* for vtophys proto */
148 #ifndef IFF_NOTRAILERS
149 #define IFF_NOTRAILERS 0
153 #define BPFATTACH(ifp, dlt, hlen) bpfattach((ifp), (dlt), (hlen))
160 #define EN_TXHIWAT (64*1024) /* max 64 KB waiting to be DMAd out */
164 #define EN_MINDMA 32 /* don't DMA anything less than this (bytes) */
167 #define RX_NONE 0xffff /* recv VC not in use */
169 #define EN_OBHDR ATM_PH_DRIVER7 /* TBD in first mbuf ! */
170 #define EN_OBTRL ATM_PH_DRIVER8 /* PDU trailier in last mbuf ! */
172 #define ENOTHER_FREE 0x01 /* free rxslot */
173 #define ENOTHER_DRAIN 0x02 /* almost free (drain DRQ dma) */
174 #define ENOTHER_RAW 0x04 /* 'raw' access (aka boodi mode) */
175 #define ENOTHER_SWSL 0x08 /* in software service list */
177 static int en_dma = EN_DMA; /* use DMA (switch off for dbg) */
180 * autoconfig attachments
183 struct cfdriver en_cd = {
192 * params to en_txlaunch() function
196 u_int32_t tbd1; /* TBD 1 */
197 u_int32_t tbd2; /* TBD 2 */
198 u_int32_t pdu1; /* PDU 1 (aal5) */
199 int nodma; /* don't use DMA */
200 int need; /* total space we need (pad out if less data) */
201 int mlen; /* length of mbuf (for dtq) */
202 struct mbuf *t; /* data */
203 u_int32_t aal; /* aal code */
204 u_int32_t atm_vci; /* vci */
205 u_int8_t atm_flags; /* flags */
210 * dma table (index by # of words)
212 * plan A: use WMAYBE (obsolete)
213 * plan B: avoid WMAYBE
217 u_int8_t bcode; /* code */
218 u_int8_t divshift; /* byte divisor */
221 static struct en_dmatab en_dma_planB[] = {
222 { 0, 0 }, /* 0 */ { MIDDMA_WORD, 2}, /* 1 */
223 { MIDDMA_2WORD, 3}, /* 2 */ { MIDDMA_WORD, 2}, /* 3 */
224 { MIDDMA_4WORD, 4}, /* 4 */ { MIDDMA_WORD, 2}, /* 5 */
225 { MIDDMA_2WORD, 3}, /* 6 */ { MIDDMA_WORD, 2}, /* 7 */
226 { MIDDMA_8WORD, 5}, /* 8 */ { MIDDMA_WORD, 2}, /* 9 */
227 { MIDDMA_2WORD, 3}, /* 10 */ { MIDDMA_WORD, 2}, /* 11 */
228 { MIDDMA_4WORD, 4}, /* 12 */ { MIDDMA_WORD, 2}, /* 13 */
229 { MIDDMA_2WORD, 3}, /* 14 */ { MIDDMA_WORD, 2}, /* 15 */
230 { MIDDMA_16WORD, 6}, /* 16 */
233 static struct en_dmatab *en_dmaplan = en_dma_planB;
239 STATIC INLINE int en_b2sz (int) __attribute__ ((unused));
241 int en_dump (int,int);
242 int en_dumpmem (int,int,int);
244 STATIC void en_dmaprobe (struct en_softc *);
245 STATIC int en_dmaprobe_doit (struct en_softc *, u_int8_t *,
247 STATIC INLINE int en_dqneed (struct en_softc *, caddr_t, u_int,
248 u_int) __attribute__ ((unused));
249 STATIC void en_init (struct en_softc *);
250 STATIC int en_ioctl (struct ifnet *, EN_IOCTL_CMDT, caddr_t,
252 STATIC INLINE int en_k2sz (int) __attribute__ ((unused));
253 STATIC void en_loadvc (struct en_softc *, int);
254 STATIC int en_mfix (struct en_softc *, struct mbuf **,
256 STATIC INLINE struct mbuf *en_mget (struct en_softc *, u_int,
257 u_int *) __attribute__ ((unused));
258 STATIC INLINE u_int32_t en_read (struct en_softc *,
259 u_int32_t) __attribute__ ((unused));
260 STATIC int en_rxctl (struct en_softc *, struct atm_pseudoioctl *,
262 STATIC void en_txdma (struct en_softc *, int);
263 STATIC void en_txlaunch (struct en_softc *, int,
265 STATIC void en_service (struct en_softc *);
266 STATIC void en_start (struct ifnet *);
267 STATIC INLINE int en_sz2b (int) __attribute__ ((unused));
268 STATIC INLINE void en_write (struct en_softc *, u_int32_t,
269 u_int32_t) __attribute__ ((unused));
276 * raw read/write macros
279 #define EN_READDAT(SC,R) en_read(SC,R)
280 #define EN_WRITEDAT(SC,R,V) en_write(SC,R,V)
283 * cooked read/write macros
286 #define EN_READ(SC,R) ntohl(en_read(SC,R))
287 #define EN_WRITE(SC,R,V) en_write(SC,R, htonl(V))
289 #define EN_WRAPADD(START,STOP,CUR,VAL) { \
290 (CUR) = (CUR) + (VAL); \
291 if ((CUR) >= (STOP)) \
292 (CUR) = (START) + ((CUR) - (STOP)); \
295 #define WORD_IDX(START, X) (((X) - (START)) / sizeof(u_int32_t))
297 /* we store sc->dtq and sc->drq data in the following format... */
298 #define EN_DQ_MK(SLOT,LEN) (((SLOT) << 20)|(LEN)|(0x80000))
299 /* the 0x80000 ensures we != 0 */
300 #define EN_DQ_SLOT(X) ((X) >> 20)
301 #define EN_DQ_LEN(X) ((X) & 0x3ffff)
303 /* format of DTQ/DRQ word 1 differs between ENI and ADP */
304 #if defined(MIDWAY_ENIONLY)
306 #define MID_MK_TXQ(SC,CNT,CHAN,END,BCODE) \
307 EN_WRITE((SC), (SC)->dtq_us, \
308 MID_MK_TXQ_ENI((CNT), (CHAN), (END), (BCODE)));
310 #define MID_MK_RXQ(SC,CNT,VCI,END,BCODE) \
311 EN_WRITE((SC), (SC)->drq_us, \
312 MID_MK_RXQ_ENI((CNT), (VCI), (END), (BCODE)));
314 #elif defined(MIDWAY_ADPONLY)
316 #define MID_MK_TXQ(SC,CNT,CHAN,END,JK) \
317 EN_WRITE((SC), (SC)->dtq_us, \
318 MID_MK_TXQ_ADP((CNT), (CHAN), (END), (JK)));
320 #define MID_MK_RXQ(SC,CNT,VCI,END,JK) \
321 EN_WRITE((SC), (SC)->drq_us, \
322 MID_MK_RXQ_ADP((CNT), (VCI), (END), (JK)));
326 #define MID_MK_TXQ(SC,CNT,CHAN,END,JK_OR_BCODE) { \
327 if ((SC)->is_adaptec) \
328 EN_WRITE((SC), (SC)->dtq_us, \
329 MID_MK_TXQ_ADP((CNT), (CHAN), (END), (JK_OR_BCODE))); \
331 EN_WRITE((SC), (SC)->dtq_us, \
332 MID_MK_TXQ_ENI((CNT), (CHAN), (END), (JK_OR_BCODE))); \
335 #define MID_MK_RXQ(SC,CNT,VCI,END,JK_OR_BCODE) { \
336 if ((SC)->is_adaptec) \
337 EN_WRITE((SC), (SC)->drq_us, \
338 MID_MK_RXQ_ADP((CNT), (VCI), (END), (JK_OR_BCODE))); \
340 EN_WRITE((SC), (SC)->drq_us, \
341 MID_MK_RXQ_ENI((CNT), (VCI), (END), (JK_OR_BCODE))); \
346 /* add an item to the DTQ */
347 #define EN_DTQADD(SC,CNT,CHAN,JK_OR_BCODE,ADDR,LEN,END) { \
349 (SC)->dtq[MID_DTQ_A2REG((SC)->dtq_us)] = EN_DQ_MK(CHAN,LEN); \
350 MID_MK_TXQ(SC,CNT,CHAN,END,JK_OR_BCODE); \
352 EN_WRITE((SC), (SC)->dtq_us, (ADDR)); \
353 EN_WRAPADD(MID_DTQOFF, MID_DTQEND, (SC)->dtq_us, 4); \
356 EN_WRITE((SC), MID_DMA_WRTX, MID_DTQ_A2REG((SC)->dtq_us)); \
360 #define EN_DRQADD(SC,CNT,VCI,JK_OR_BCODE,ADDR,LEN,SLOT,END) { \
362 (SC)->drq[MID_DRQ_A2REG((SC)->drq_us)] = EN_DQ_MK(SLOT,LEN); \
363 MID_MK_RXQ(SC,CNT,VCI,END,JK_OR_BCODE); \
365 EN_WRITE((SC), (SC)->drq_us, (ADDR)); \
366 EN_WRAPADD(MID_DRQOFF, MID_DRQEND, (SC)->drq_us, 4); \
369 EN_WRITE((SC), MID_DMA_WRRX, MID_DRQ_A2REG((SC)->drq_us)); \
375 * the code is arranged in a specific way:
376 * [1] short/inline functions
377 * [2] autoconfig stuff
379 * [4] reset -> init -> trasmit -> intr -> receive functions
383 /***********************************************************************/
386 * en_read: read a word from the card. this is the only function
387 * that reads from the card.
390 STATIC INLINE u_int32_t en_read(sc, r)
397 #ifdef EN_DEBUG_RANGE
398 if (r > MID_MAXOFF || (r % 4))
399 panic("en_read out of range, r=0x%x", r);
402 return(bus_space_read_4(sc->en_memt, sc->en_base, r));
406 * en_write: write a word to the card. this is the only function that
407 * writes to the card.
410 STATIC INLINE void en_write(sc, r, v)
416 #ifdef EN_DEBUG_RANGE
417 if (r > MID_MAXOFF || (r % 4))
418 panic("en_write out of range, r=0x%x", r);
421 bus_space_write_4(sc->en_memt, sc->en_base, r, v);
425 * en_k2sz: convert KBytes to a size parameter (a log2)
428 STATIC INLINE int en_k2sz(k)
442 default: panic("en_k2sz");
446 #define en_log2(X) en_k2sz(X)
450 * en_b2sz: convert a DMA burst code to its byte size
453 STATIC INLINE int en_b2sz(b)
459 case MIDDMA_WORD: return(1*4);
461 case MIDDMA_2WORD: return(2*4);
463 case MIDDMA_4WORD: return(4*4);
465 case MIDDMA_8WORD: return(8*4);
466 case MIDDMA_16WMAYBE:
467 case MIDDMA_16WORD: return(16*4);
468 default: panic("en_b2sz");
475 * en_sz2b: convert a burst size (bytes) to DMA burst code
478 STATIC INLINE int en_sz2b(sz)
484 case 1*4: return(MIDDMA_WORD);
485 case 2*4: return(MIDDMA_2WORD);
486 case 4*4: return(MIDDMA_4WORD);
487 case 8*4: return(MIDDMA_8WORD);
488 case 16*4: return(MIDDMA_16WORD);
489 default: panic("en_sz2b");
496 * en_dqneed: calculate number of DTQ/DRQ's needed for a buffer
499 STATIC INLINE int en_dqneed(sc, data, len, tx)
506 int result, needalign, sz;
508 #if !defined(MIDWAY_ENIONLY)
509 #if !defined(MIDWAY_ADPONLY)
511 #endif /* !MIDWAY_ADPONLY */
512 return(1); /* adaptec can DMA anything in one go */
515 #if !defined(MIDWAY_ADPONLY)
517 if (len < EN_MINDMA) {
518 if (!tx) /* XXX: conservative */
519 return(1); /* will copy/DMA_JK */
522 if (tx) { /* byte burst? */
523 needalign = (((uintptr_t) (void *) data) % sizeof(u_int32_t));
526 sz = min(len, sizeof(u_int32_t) - needalign);
532 if (sc->alburst && len) {
533 needalign = (((uintptr_t) (void *) data) & sc->bestburstmask);
535 result++; /* alburst */
536 sz = min(len, sc->bestburstlen - needalign);
541 if (len >= sc->bestburstlen) {
542 sz = len / sc->bestburstlen;
543 sz = sz * sc->bestburstlen;
545 result++; /* best shot */
549 result++; /* clean up */
550 if (tx && (len % sizeof(u_int32_t)) != 0)
551 result++; /* byte cleanup */
555 #endif /* !MIDWAY_ADPONLY */
560 * en_mget: get an mbuf chain that can hold totlen bytes and return it
561 * (for recv) [based on am7990_get from if_le and ieget from if_ie]
562 * after this call the sum of all the m_len's in the chain will be totlen.
565 STATIC INLINE struct mbuf *en_mget(sc, totlen, drqneed)
568 u_int totlen, *drqneed;
572 struct mbuf *top, **mp;
575 MGETHDR(m, MB_DONTWAIT, MT_DATA);
578 m->m_pkthdr.rcvif = &sc->enif;
579 m->m_pkthdr.len = totlen;
584 /* if (top != NULL) then we've already got 1 mbuf on the chain */
587 MGET(m, MB_DONTWAIT, MT_DATA);
590 return(NULL); /* out of mbufs */
594 if (totlen >= MINCLSIZE) {
595 MCLGET(m, MB_DONTWAIT);
596 if ((m->m_flags & M_EXT) == 0) {
599 return(NULL); /* out of mbuf clusters */
603 m->m_len = min(totlen, m->m_len);
608 *drqneed += en_dqneed(sc, m->m_data, m->m_len, 0);
614 /***********************************************************************/
625 struct ifnet *ifp = &sc->enif;
627 u_int32_t reg, lcv, check, ptr, sav, midvloc;
630 * probe card to determine memory size. the stupid ENI card always
631 * reports to PCI that it needs 4MB of space (2MB regs and 2MB RAM).
632 * if it has less than 2MB RAM the addresses wrap in the RAM address space.
633 * (i.e. on a 512KB card addresses 0x3ffffc, 0x37fffc, and 0x2ffffc
634 * are aliases for 0x27fffc [note that RAM starts at offset 0x200000]).
639 EN_WRITE(sc, MID_RESID, 0x0); /* reset card before touching RAM */
640 for (lcv = MID_PROBEOFF; lcv <= MID_MAXOFF ; lcv += MID_PROBSIZE) {
641 EN_WRITE(sc, lcv, lcv); /* data[address] = address */
642 for (check = MID_PROBEOFF ; check < lcv ; check += MID_PROBSIZE) {
643 reg = EN_READ(sc, check);
644 if (reg != check) { /* found an alias! */
645 goto done_probe; /* and quit */
650 lcv -= MID_PROBSIZE; /* take one step back */
651 sc->en_obmemsz = (lcv + 4) - MID_RAMOFF;
654 * determine the largest DMA burst supported
665 EN_WRITE(sc, MID_RESID, 0x0); /* reset */
666 for (lcv = MID_RAMOFF ; lcv < MID_RAMOFF + sc->en_obmemsz ; lcv += 4)
667 EN_WRITE(sc, lcv, 0); /* zero memory */
669 reg = EN_READ(sc, MID_RESID);
671 printf("%s: ATM midway v%d, board IDs %d.%d, %s%s%s, %ldKB on-board RAM\n",
672 sc->sc_dev.dv_xname, MID_VER(reg), MID_MID(reg), MID_DID(reg),
673 (MID_IS_SABRE(reg)) ? "sabre controller, " : "",
674 (MID_IS_SUNI(reg)) ? "SUNI" : "Utopia",
675 (!MID_IS_SUNI(reg) && MID_IS_UPIPE(reg)) ? " (pipelined)" : "",
676 (long)(sc->en_obmemsz / 1024));
678 if (sc->is_adaptec) {
679 if (sc->bestburstlen == 64 && sc->alburst == 0)
680 printf("%s: passed 64 byte DMA test\n", sc->sc_dev.dv_xname);
682 printf("%s: FAILED DMA TEST: burst=%d, alburst=%d\n",
683 sc->sc_dev.dv_xname, sc->bestburstlen, sc->alburst);
685 printf("%s: maximum DMA burst length = %d bytes%s\n", sc->sc_dev.dv_xname,
686 sc->bestburstlen, (sc->alburst) ? " (must align)" : "");
690 * link into network subsystem and prepare card
693 sc->enif.if_softc = sc;
694 ifp->if_flags = IFF_SIMPLEX|IFF_NOTRAILERS;
695 ifp->if_ioctl = en_ioctl;
696 ifp->if_output = atm_output;
697 ifp->if_start = en_start;
703 for (lcv = 0 ; lcv < MID_N_VC ; lcv++) {
704 sc->rxvc2slot[lcv] = RX_NONE;
705 sc->txspeed[lcv] = 0; /* full */
706 sc->txvc2slot[lcv] = 0; /* full speed == slot 0 */
709 sz = sc->en_obmemsz - (MID_BUFOFF - MID_RAMOFF);
710 ptr = sav = MID_BUFOFF;
711 ptr = roundup(ptr, EN_TXSZ * 1024); /* align */
712 sz = sz - (ptr - sav);
713 if (EN_TXSZ*1024 * EN_NTX > sz) {
714 printf("%s: EN_NTX/EN_TXSZ too big\n", sc->sc_dev.dv_xname);
717 for (lcv = 0 ; lcv < EN_NTX ; lcv++) {
718 sc->txslot[lcv].mbsize = 0;
719 sc->txslot[lcv].start = ptr;
720 ptr += (EN_TXSZ * 1024);
721 sz -= (EN_TXSZ * 1024);
722 sc->txslot[lcv].stop = ptr;
723 sc->txslot[lcv].nref = 0;
724 bzero(&sc->txslot[lcv].indma, sizeof(sc->txslot[lcv].indma));
725 bzero(&sc->txslot[lcv].q, sizeof(sc->txslot[lcv].q));
727 printf("%s: tx%d: start 0x%x, stop 0x%x\n", sc->sc_dev.dv_xname, lcv,
728 sc->txslot[lcv].start, sc->txslot[lcv].stop);
733 ptr = roundup(ptr, EN_RXSZ * 1024); /* align */
734 sz = sz - (ptr - sav);
735 sc->en_nrx = sz / (EN_RXSZ * 1024);
736 if (sc->en_nrx <= 0) {
737 printf("%s: EN_NTX/EN_TXSZ/EN_RXSZ too big\n", sc->sc_dev.dv_xname);
742 * ensure that there is always one VC slot on the service list free
743 * so that we can tell the difference between a full and empty list.
745 if (sc->en_nrx >= MID_N_VC)
746 sc->en_nrx = MID_N_VC - 1;
748 for (lcv = 0 ; lcv < sc->en_nrx ; lcv++) {
749 sc->rxslot[lcv].rxhand = NULL;
750 sc->rxslot[lcv].oth_flags = ENOTHER_FREE;
751 bzero(&sc->rxslot[lcv].indma, sizeof(sc->rxslot[lcv].indma));
752 bzero(&sc->rxslot[lcv].q, sizeof(sc->rxslot[lcv].q));
753 midvloc = sc->rxslot[lcv].start = ptr;
754 ptr += (EN_RXSZ * 1024);
755 sz -= (EN_RXSZ * 1024);
756 sc->rxslot[lcv].stop = ptr;
757 midvloc = midvloc - MID_RAMOFF;
758 midvloc = (midvloc & ~((EN_RXSZ*1024) - 1)) >> 2; /* mask, cvt to words */
759 midvloc = midvloc >> MIDV_LOCTOPSHFT; /* we only want the top 11 bits */
760 midvloc = (midvloc & MIDV_LOCMASK) << MIDV_LOCSHIFT;
761 sc->rxslot[lcv].mode = midvloc |
762 (en_k2sz(EN_RXSZ) << MIDV_SZSHIFT) | MIDV_TRASH;
765 printf("%s: rx%d: start 0x%x, stop 0x%x, mode 0x%x\n", sc->sc_dev.dv_xname,
766 lcv, sc->rxslot[lcv].start, sc->rxslot[lcv].stop, sc->rxslot[lcv].mode);
771 sc->vtrash = sc->otrash = sc->mfix = sc->txmbovr = sc->dmaovr = 0;
772 sc->txoutspace = sc->txdtqout = sc->launch = sc->lheader = sc->ltail = 0;
773 sc->hwpull = sc->swadd = sc->rxqnotus = sc->rxqus = sc->rxoutboth = 0;
774 sc->rxdrqout = sc->ttrash = sc->rxmbufout = sc->mfixfail = 0;
775 sc->headbyte = sc->tailbyte = sc->tailflush = 0;
777 sc->need_drqs = sc->need_dtqs = 0;
779 printf("%s: %d %dKB receive buffers, %d %dKB transmit buffers allocated\n",
780 sc->sc_dev.dv_xname, sc->en_nrx, EN_RXSZ, EN_NTX, EN_TXSZ);
782 printf("%s: End Station Identifier (mac address) %6D\n",
783 sc->sc_dev.dv_xname, sc->macaddr, ":");
788 atm_ifattach(ifp, NULL);
793 * en_dmaprobe: helper function for en_attach.
795 * see how the card handles DMA by running a few DMA tests. we need
796 * to figure out the largest number of bytes we can DMA in one burst
797 * ("bestburstlen"), and if the starting address for a burst needs to
798 * be aligned on any sort of boundary or not ("alburst").
801 * sparc1: bestburstlen=4, alburst=0 (ick, broken DMA!)
802 * sparc2: bestburstlen=64, alburst=1
803 * p166: bestburstlen=64, alburst=0
806 #define NBURSTS 3 /* number of bursts to use for dmaprobe */
807 #define BOUNDARY 1024 /* test misaligned dma crossing the bounday.
808 should be n * 64. at least 64*(NBURSTS+1).
809 dell P6 with EDO DRAM has 1K bounday problem */
811 STATIC void en_dmaprobe(sc)
817 /* be careful. kernel stack is only 8K */
818 u_int8_t buffer[BOUNDARY * 2 + 64 * (NBURSTS + 1)];
820 u_int32_t srcbuf[64], dstbuf[64];
823 int bestalgn, bestnotalgn, lcv, try;
828 /* setup src and dst buf at the end of the boundary */
829 sp = (u_int8_t *)roundup((uintptr_t)(void *)buffer, 64);
830 while (((uintptr_t)(void *)sp & (BOUNDARY - 1)) != (BOUNDARY - 64))
835 * we can't dma across page boundary so that, if buf is at a page
836 * boundary, move it to the next page. but still either src or dst
837 * will be at the boundary, which should be ok.
839 if ((((uintptr_t)(void *)sp + 64) & PAGE_MASK) == 0)
841 if ((((uintptr_t)(void *)dp + 64) & PAGE_MASK) == 0)
844 sp = (u_int8_t *) srcbuf;
845 while ((((unsigned long) sp) % MIDDMA_MAXBURST) != 0)
847 dp = (u_int8_t *) dstbuf;
848 while ((((unsigned long) dp) % MIDDMA_MAXBURST) != 0)
850 #endif /* !NBURSTS */
852 bestalgn = bestnotalgn = en_dmaprobe_doit(sc, sp, dp, 0);
854 for (lcv = 4 ; lcv < MIDDMA_MAXBURST ; lcv += 4) {
855 try = en_dmaprobe_doit(sc, sp+lcv, dp+lcv, 0);
857 if (try < bestnotalgn) {
862 if (try < bestnotalgn)
867 if (bestalgn != bestnotalgn) /* need bursts aligned */
870 sc->bestburstlen = bestalgn;
871 sc->bestburstshift = en_log2(bestalgn);
872 sc->bestburstmask = sc->bestburstlen - 1; /* must be power of 2 */
873 sc->bestburstcode = en_sz2b(bestalgn);
876 * correct pci chipsets should be able to handle misaligned-64-byte DMA.
877 * but there are too many broken chipsets around. we try to work around
878 * by finding the best workable dma size, but still some broken machines
879 * exhibit the problem later. so warn it here.
881 if (bestalgn != 64 || sc->alburst != 0) {
882 printf("%s: WARNING: DMA test detects a broken PCI chipset!\n",
883 sc->sc_dev.dv_xname);
884 printf(" trying to work around the problem... but if this doesn't\n");
885 printf(" work for you, you'd better switch to a newer motherboard.\n");
892 * en_dmaprobe_doit: do actual testing
896 en_dmaprobe_doit(sc, sp, dp, wmtry)
903 int lcv, retval = 4, cnt, count;
904 u_int32_t reg, bcode, midvloc;
907 * set up a 1k buffer at MID_BUFOFF
912 EN_WRITE(sc, MID_RESID, 0x0); /* reset card before touching RAM */
914 midvloc = ((MID_BUFOFF - MID_RAMOFF) / sizeof(u_int32_t)) >> MIDV_LOCTOPSHFT;
915 EN_WRITE(sc, MIDX_PLACE(0), MIDX_MKPLACE(en_k2sz(1), midvloc));
916 EN_WRITE(sc, MID_VC(0), (midvloc << MIDV_LOCSHIFT)
917 | (en_k2sz(1) << MIDV_SZSHIFT) | MIDV_TRASH);
918 EN_WRITE(sc, MID_DST_RP(0), 0);
919 EN_WRITE(sc, MID_WP_ST_CNT(0), 0);
922 for (lcv = 0 ; lcv < 64*NBURSTS; lcv++) /* set up sample data */
924 for (lcv = 0 ; lcv < 68 ; lcv++) /* set up sample data */
927 EN_WRITE(sc, MID_MAST_CSR, MID_MCSR_ENDMA); /* enable DMA (only) */
929 sc->drq_chip = MID_DRQ_REG2A(EN_READ(sc, MID_DMA_RDRX));
930 sc->dtq_chip = MID_DTQ_REG2A(EN_READ(sc, MID_DMA_RDTX));
933 * try it now . . . DMA it out, then DMA it back in and compare
935 * note: in order to get the dma stuff to reverse directions it wants
936 * the "end" flag set! since we are not dma'ing valid data we may
937 * get an ident mismatch interrupt (which we will ignore).
939 * note: we've got two different tests rolled up in the same loop
941 * then we are doing a wmaybe test and wmtry is a byte count
942 * else we are doing a burst test
945 for (lcv = 8 ; lcv <= MIDDMA_MAXBURST ; lcv = lcv * 2) {
948 printf("DMA test lcv=%d, sp=0x%x, dp=0x%x, wmtry=%d\n",
952 /* zero SRAM and dest buffer */
953 for (cnt = 0 ; cnt < 1024; cnt += 4)
954 EN_WRITE(sc, MID_BUFOFF+cnt, 0); /* zero memory */
956 for (cnt = 0 ; cnt < 64*NBURSTS; cnt++)
958 for (cnt = 0 ; cnt < 68 ; cnt++)
963 count = (sc->bestburstlen - sizeof(u_int32_t)) / sizeof(u_int32_t);
964 bcode = en_dmaplan[count].bcode;
965 count = wmtry >> en_dmaplan[count].divshift;
967 bcode = en_sz2b(lcv);
971 /* build lcv-byte-DMA x NBURSTS */
973 EN_WRITE(sc, sc->dtq_chip, MID_MK_TXQ_ADP(lcv*NBURSTS, 0, MID_DMA_END, 0));
975 EN_WRITE(sc, sc->dtq_chip, MID_MK_TXQ_ENI(count*NBURSTS, 0, MID_DMA_END, bcode));
976 EN_WRITE(sc, sc->dtq_chip+4, vtophys(sp));
977 EN_WRAPADD(MID_DTQOFF, MID_DTQEND, sc->dtq_chip, 8);
978 EN_WRITE(sc, MID_DMA_WRTX, MID_DTQ_A2REG(sc->dtq_chip));
980 while (EN_READ(sc, MID_DMA_RDTX) != MID_DTQ_A2REG(sc->dtq_chip)) {
984 printf("%s: unexpected timeout in tx DMA test\n", sc->sc_dev.dv_xname);
986 printf(" alignment=0x%x, burst size=%d, dma addr reg=0x%x\n",
987 (u_long)sp & 63, lcv, EN_READ(sc, MID_DMA_ADDR));
989 return(retval); /* timeout, give up */
994 EN_WRITE(sc, sc->dtq_chip, MID_MK_TXQ_ADP(lcv, 0, MID_DMA_END, 0));
996 EN_WRITE(sc, sc->dtq_chip, MID_MK_TXQ_ENI(count, 0, MID_DMA_END, bcode));
997 EN_WRITE(sc, sc->dtq_chip+4, vtophys(sp));
998 EN_WRITE(sc, MID_DMA_WRTX, MID_DTQ_A2REG(sc->dtq_chip+8));
1000 while (EN_READ(sc, MID_DMA_RDTX) == MID_DTQ_A2REG(sc->dtq_chip)) {
1004 printf("%s: unexpected timeout in tx DMA test\n", sc->sc_dev.dv_xname);
1005 return(retval); /* timeout, give up */
1008 EN_WRAPADD(MID_DTQOFF, MID_DTQEND, sc->dtq_chip, 8);
1009 #endif /* !NBURSTS */
1010 reg = EN_READ(sc, MID_INTACK);
1011 if ((reg & MID_INT_DMA_TX) != MID_INT_DMA_TX) {
1012 printf("%s: unexpected status in tx DMA test: 0x%x\n",
1013 sc->sc_dev.dv_xname, reg);
1016 EN_WRITE(sc, MID_MAST_CSR, MID_MCSR_ENDMA); /* re-enable DMA (only) */
1018 /* "return to sender..." address is known ... */
1021 /* build lcv-byte-DMA x NBURSTS */
1023 EN_WRITE(sc, sc->drq_chip, MID_MK_RXQ_ADP(lcv*NBURSTS, 0, MID_DMA_END, 0));
1025 EN_WRITE(sc, sc->drq_chip, MID_MK_RXQ_ENI(count*NBURSTS, 0, MID_DMA_END, bcode));
1026 EN_WRITE(sc, sc->drq_chip+4, vtophys(dp));
1027 EN_WRAPADD(MID_DRQOFF, MID_DRQEND, sc->drq_chip, 8);
1028 EN_WRITE(sc, MID_DMA_WRRX, MID_DRQ_A2REG(sc->drq_chip));
1030 while (EN_READ(sc, MID_DMA_RDRX) != MID_DRQ_A2REG(sc->drq_chip)) {
1034 printf("%s: unexpected timeout in rx DMA test\n", sc->sc_dev.dv_xname);
1035 return(retval); /* timeout, give up */
1038 #else /* !NBURSTS */
1040 EN_WRITE(sc, sc->drq_chip, MID_MK_RXQ_ADP(lcv, 0, MID_DMA_END, 0));
1042 EN_WRITE(sc, sc->drq_chip, MID_MK_RXQ_ENI(count, 0, MID_DMA_END, bcode));
1043 EN_WRITE(sc, sc->drq_chip+4, vtophys(dp));
1044 EN_WRITE(sc, MID_DMA_WRRX, MID_DRQ_A2REG(sc->drq_chip+8));
1046 while (EN_READ(sc, MID_DMA_RDRX) == MID_DRQ_A2REG(sc->drq_chip)) {
1050 printf("%s: unexpected timeout in rx DMA test\n", sc->sc_dev.dv_xname);
1051 return(retval); /* timeout, give up */
1054 EN_WRAPADD(MID_DRQOFF, MID_DRQEND, sc->drq_chip, 8);
1055 #endif /* !NBURSTS */
1056 reg = EN_READ(sc, MID_INTACK);
1057 if ((reg & MID_INT_DMA_RX) != MID_INT_DMA_RX) {
1058 printf("%s: unexpected status in rx DMA test: 0x%x\n",
1059 sc->sc_dev.dv_xname, reg);
1062 EN_WRITE(sc, MID_MAST_CSR, MID_MCSR_ENDMA); /* re-enable DMA (only) */
1065 return(bcmp(sp, dp, wmtry)); /* wmtry always exits here, no looping */
1069 if (bcmp(sp, dp, lcv * NBURSTS)) {
1070 /* printf("DMA test failed! lcv=%d, sp=0x%x, dp=0x%x\n", lcv, sp, dp); */
1071 return(retval); /* failed, use last value */
1074 if (bcmp(sp, dp, lcv))
1075 return(retval); /* failed, use last value */
1081 return(retval); /* studly 64 byte DMA present! oh baby!! */
1084 /***********************************************************************/
1087 * en_ioctl: handle ioctl requests
1089 * NOTE: if you add an ioctl to set txspeed, you should choose a new
1090 * TX channel/slot. Choose the one with the lowest sc->txslot[slot].nref
1091 * value, subtract one from sc->txslot[0].nref, add one to the
1092 * sc->txslot[slot].nref, set sc->txvc2slot[vci] = slot, and then set
1096 STATIC int en_ioctl(ifp, cmd, data, cr)
1104 struct en_softc *sc = (struct en_softc *) ifp->if_softc;
1105 struct ifaddr *ifa = (struct ifaddr *) data;
1106 struct ifreq *ifr = (struct ifreq *) data;
1107 struct atm_pseudoioctl *api = (struct atm_pseudoioctl *)data;
1109 struct atm_rawioctl *ario = (struct atm_rawioctl *)data;
1117 case SIOCATMENA: /* enable circuit for recv */
1118 error = en_rxctl(sc, api, 1);
1121 case SIOCATMDIS: /* disable circuit for recv */
1122 error = en_rxctl(sc, api, 0);
1127 if ((slot = sc->rxvc2slot[ario->npcb->npcb_vci]) == RX_NONE) {
1131 if (ario->rawvalue > EN_RXSZ*1024)
1132 ario->rawvalue = EN_RXSZ*1024;
1133 if (ario->rawvalue) {
1134 sc->rxslot[slot].oth_flags |= ENOTHER_RAW;
1135 sc->rxslot[slot].raw_threshold = ario->rawvalue;
1137 sc->rxslot[slot].oth_flags &= (~ENOTHER_RAW);
1138 sc->rxslot[slot].raw_threshold = 0;
1141 printf("%s: rxvci%d: turn %s raw (boodi) mode\n",
1142 sc->sc_dev.dv_xname, ario->npcb->npcb_vci,
1143 (ario->rawvalue) ? "on" : "off");
1148 ifp->if_flags |= IFF_UP;
1149 #if defined(INET) || defined(INET6)
1150 if (ifa->ifa_addr->sa_family == AF_INET
1151 || ifa->ifa_addr->sa_family == AF_INET6) {
1154 ifa->ifa_rtrequest = atm_rtrequest; /* ??? */
1158 /* what to do if not INET? */
1171 #if defined(SIOCSIFMTU) /* ??? copied from if_de */
1172 #if !defined(ifr_mtu)
1173 #define ifr_mtu ifr_metric
1177 * Set the interface MTU.
1180 if (ifr->ifr_mtu > ATMMTU) {
1185 ifp->if_mtu = ifr->ifr_mtu;
1186 /* XXXCDC: do we really need to reset on MTU size change? */
1190 #endif /* SIOCSIFMTU */
1202 * en_rxctl: turn on and off VCs for recv.
1205 STATIC int en_rxctl(sc, pi, on)
1207 struct en_softc *sc;
1208 struct atm_pseudoioctl *pi;
1212 u_int vci, flags, slot;
1213 u_int32_t oldmode, newmode;
1215 vci = ATM_PH_VCI(&pi->aph);
1216 flags = ATM_PH_FLAGS(&pi->aph);
1219 printf("%s: %s vpi=%d, vci=%d, flags=%d\n", sc->sc_dev.dv_xname,
1220 (on) ? "enable" : "disable", ATM_PH_VPI(&pi->aph), vci, flags);
1223 if (ATM_PH_VPI(&pi->aph) || vci >= MID_N_VC)
1231 if (sc->rxvc2slot[vci] != RX_NONE)
1233 for (slot = 0 ; slot < sc->en_nrx ; slot++)
1234 if (sc->rxslot[slot].oth_flags & ENOTHER_FREE)
1236 if (slot == sc->en_nrx)
1238 sc->rxvc2slot[vci] = slot;
1239 sc->rxslot[slot].rxhand = NULL;
1240 oldmode = sc->rxslot[slot].mode;
1241 newmode = (flags & ATM_PH_AAL5) ? MIDV_AAL5 : MIDV_NOAAL;
1242 sc->rxslot[slot].mode = MIDV_SETMODE(oldmode, newmode);
1243 sc->rxslot[slot].atm_vci = vci;
1244 sc->rxslot[slot].atm_flags = flags;
1245 sc->rxslot[slot].oth_flags = 0;
1246 sc->rxslot[slot].rxhand = pi->rxhand;
1247 if (sc->rxslot[slot].indma.ifq_head || sc->rxslot[slot].q.ifq_head)
1248 panic("en_rxctl: left over mbufs on enable");
1249 sc->txspeed[vci] = 0; /* full speed to start */
1250 sc->txvc2slot[vci] = 0; /* init value */
1251 sc->txslot[0].nref++; /* bump reference count */
1252 en_loadvc(sc, vci); /* does debug printf for us */
1260 if (sc->rxvc2slot[vci] == RX_NONE)
1262 slot = sc->rxvc2slot[vci];
1263 if ((sc->rxslot[slot].oth_flags & (ENOTHER_FREE|ENOTHER_DRAIN)) != 0)
1265 crit_enter(); /* block out enintr() */
1266 oldmode = EN_READ(sc, MID_VC(vci));
1267 newmode = MIDV_SETMODE(oldmode, MIDV_TRASH) & ~MIDV_INSERVICE;
1268 EN_WRITE(sc, MID_VC(vci), (newmode | (oldmode & MIDV_INSERVICE)));
1269 /* halt in tracks, be careful to preserve inserivce bit */
1271 sc->rxslot[slot].rxhand = NULL;
1272 sc->rxslot[slot].mode = newmode;
1274 sc->txslot[sc->txvc2slot[vci]].nref--;
1275 sc->txspeed[vci] = 0;
1276 sc->txvc2slot[vci] = 0;
1278 /* if stuff is still going on we are going to have to drain it out */
1279 if (sc->rxslot[slot].indma.ifq_head ||
1280 sc->rxslot[slot].q.ifq_head ||
1281 (sc->rxslot[slot].oth_flags & ENOTHER_SWSL) != 0) {
1282 sc->rxslot[slot].oth_flags |= ENOTHER_DRAIN;
1284 sc->rxslot[slot].oth_flags = ENOTHER_FREE;
1285 sc->rxslot[slot].atm_vci = RX_NONE;
1286 sc->rxvc2slot[vci] = RX_NONE;
1288 crit_exit(); /* enable enintr() */
1290 printf("%s: rx%d: VCI %d is now %s\n", sc->sc_dev.dv_xname, slot, vci,
1291 (sc->rxslot[slot].oth_flags & ENOTHER_DRAIN) ? "draining" : "free");
1296 /***********************************************************************/
1299 * en_reset: reset the board, throw away work in progress.
1300 * must en_init to recover.
1305 struct en_softc *sc;
1312 printf("%s: reset\n", sc->sc_dev.dv_xname);
1315 if (sc->en_busreset)
1316 sc->en_busreset(sc);
1317 EN_WRITE(sc, MID_RESID, 0x0); /* reset hardware */
1320 * recv: dump any mbufs we are dma'ing into, if DRAINing, then a reset
1324 for (lcv = 0 ; lcv < MID_N_VC ; lcv++) {
1325 if (sc->rxvc2slot[lcv] == RX_NONE)
1327 slot = sc->rxvc2slot[lcv];
1329 IF_DEQUEUE(&sc->rxslot[slot].indma, m);
1331 break; /* >>> exit 'while(1)' here <<< */
1335 IF_DEQUEUE(&sc->rxslot[slot].q, m);
1337 break; /* >>> exit 'while(1)' here <<< */
1340 sc->rxslot[slot].oth_flags &= ~ENOTHER_SWSL;
1341 if (sc->rxslot[slot].oth_flags & ENOTHER_DRAIN) {
1342 sc->rxslot[slot].oth_flags = ENOTHER_FREE;
1343 sc->rxvc2slot[lcv] = RX_NONE;
1345 printf("%s: rx%d: VCI %d is now free\n", sc->sc_dev.dv_xname, slot, lcv);
1351 * xmit: dump everything
1354 for (lcv = 0 ; lcv < EN_NTX ; lcv++) {
1356 IF_DEQUEUE(&sc->txslot[lcv].indma, m);
1358 break; /* >>> exit 'while(1)' here <<< */
1362 IF_DEQUEUE(&sc->txslot[lcv].q, m);
1364 break; /* >>> exit 'while(1)' here <<< */
1368 sc->txslot[lcv].mbsize = 0;
1376 * en_init: init board and sync the card with the data in the softc.
1379 STATIC void en_init(sc)
1381 struct en_softc *sc;
1387 if ((sc->enif.if_flags & IFF_UP) == 0) {
1389 printf("%s: going down\n", sc->sc_dev.dv_xname);
1391 en_reset(sc); /* to be safe */
1392 sc->enif.if_flags &= ~IFF_RUNNING; /* disable */
1397 printf("%s: going up\n", sc->sc_dev.dv_xname);
1399 sc->enif.if_flags |= IFF_RUNNING; /* enable */
1401 if (sc->en_busreset)
1402 sc->en_busreset(sc);
1403 EN_WRITE(sc, MID_RESID, 0x0); /* reset */
1406 * init obmem data structures: vc tab, dma q's, slist.
1408 * note that we set drq_free/dtq_free to one less than the total number
1409 * of DTQ/DRQs present. we do this because the card uses the condition
1410 * (drq_chip == drq_us) to mean "list is empty"... but if you allow the
1411 * circular list to be completely full then (drq_chip == drq_us) [i.e.
1412 * the drq_us pointer will wrap all the way around]. by restricting
1413 * the number of active requests to (N - 1) we prevent the list from
1414 * becoming completely full. note that the card will sometimes give
1415 * us an interrupt for a DTQ/DRQ we have already processes... this helps
1416 * keep that interrupt from messing us up.
1419 for (vc = 0 ; vc < MID_N_VC ; vc++)
1422 bzero(&sc->drq, sizeof(sc->drq));
1423 sc->drq_free = MID_DRQ_N - 1; /* N - 1 */
1424 sc->drq_chip = MID_DRQ_REG2A(EN_READ(sc, MID_DMA_RDRX));
1425 EN_WRITE(sc, MID_DMA_WRRX, MID_DRQ_A2REG(sc->drq_chip));
1426 /* ensure zero queue */
1427 sc->drq_us = sc->drq_chip;
1429 bzero(&sc->dtq, sizeof(sc->dtq));
1430 sc->dtq_free = MID_DTQ_N - 1; /* N - 1 */
1431 sc->dtq_chip = MID_DTQ_REG2A(EN_READ(sc, MID_DMA_RDTX));
1432 EN_WRITE(sc, MID_DMA_WRTX, MID_DRQ_A2REG(sc->dtq_chip));
1433 /* ensure zero queue */
1434 sc->dtq_us = sc->dtq_chip;
1436 sc->hwslistp = MID_SL_REG2A(EN_READ(sc, MID_SERV_WRITE));
1437 sc->swsl_size = sc->swsl_head = sc->swsl_tail = 0;
1440 printf("%s: drq free/chip: %d/0x%x, dtq free/chip: %d/0x%x, hwslist: 0x%x\n",
1441 sc->sc_dev.dv_xname, sc->drq_free, sc->drq_chip,
1442 sc->dtq_free, sc->dtq_chip, sc->hwslistp);
1445 for (slot = 0 ; slot < EN_NTX ; slot++) {
1446 sc->txslot[slot].bfree = EN_TXSZ * 1024;
1447 EN_WRITE(sc, MIDX_READPTR(slot), 0);
1448 EN_WRITE(sc, MIDX_DESCSTART(slot), 0);
1449 loc = sc->txslot[slot].cur = sc->txslot[slot].start;
1450 loc = loc - MID_RAMOFF;
1451 loc = (loc & ~((EN_TXSZ*1024) - 1)) >> 2; /* mask, cvt to words */
1452 loc = loc >> MIDV_LOCTOPSHFT; /* top 11 bits */
1453 EN_WRITE(sc, MIDX_PLACE(slot), MIDX_MKPLACE(en_k2sz(EN_TXSZ), loc));
1455 printf("%s: tx%d: place 0x%x\n", sc->sc_dev.dv_xname, slot,
1456 EN_READ(sc, MIDX_PLACE(slot)));
1464 EN_WRITE(sc, MID_INTENA, MID_INT_TX|MID_INT_DMA_OVR|MID_INT_IDENT|
1465 MID_INT_LERR|MID_INT_DMA_ERR|MID_INT_DMA_RX|MID_INT_DMA_TX|
1466 MID_INT_SERVICE| /* >>> MID_INT_SUNI| XXXCDC<<< */ MID_INT_STATS);
1467 EN_WRITE(sc, MID_MAST_CSR, MID_SETIPL(sc->ipl)|MID_MCSR_ENDMA|
1468 MID_MCSR_ENTX|MID_MCSR_ENRX);
1474 * en_loadvc: load a vc tab entry from a slot
1477 STATIC void en_loadvc(sc, vc)
1479 struct en_softc *sc;
1484 u_int32_t reg = EN_READ(sc, MID_VC(vc));
1486 reg = MIDV_SETMODE(reg, MIDV_TRASH);
1487 EN_WRITE(sc, MID_VC(vc), reg);
1490 if ((slot = sc->rxvc2slot[vc]) == RX_NONE)
1493 /* no need to set CRC */
1494 EN_WRITE(sc, MID_DST_RP(vc), 0); /* read pointer = 0, desc. start = 0 */
1495 EN_WRITE(sc, MID_WP_ST_CNT(vc), 0); /* write pointer = 0 */
1496 EN_WRITE(sc, MID_VC(vc), sc->rxslot[slot].mode); /* set mode, size, loc */
1497 sc->rxslot[slot].cur = sc->rxslot[slot].start;
1500 printf("%s: rx%d: assigned to VCI %d\n", sc->sc_dev.dv_xname, slot, vc);
1506 * en_start: start transmitting the next packet that needs to go out
1507 * if there is one. note that atm_output() has already locked us.
1510 STATIC void en_start(ifp)
1515 struct en_softc *sc = (struct en_softc *) ifp->if_softc;
1516 struct mbuf *m, *lastm, *prev;
1517 struct atm_pseudohdr *ap, *new_ap;
1518 int txchan, mlen, got, need, toadd, cellcnt, first;
1519 u_int32_t atm_vpi, atm_vci, atm_flags, *dat, aal;
1522 if ((ifp->if_flags & IFF_RUNNING) == 0)
1526 * remove everything from interface queue since we handle all queueing
1532 IF_DEQUEUE(&ifp->if_snd, m);
1534 return; /* EMPTY: >>> exit here <<< */
1537 * calculate size of packet (in bytes)
1538 * also, if we are not doing transmit DMA we eliminate all stupid
1539 * (non-word) alignments here using en_mfix(). calls to en_mfix()
1540 * seem to be due to tcp retransmits for the most part.
1542 * after this loop mlen total length of mbuf chain (including atm_ph),
1543 * and lastm is a pointer to the last mbuf on the chain.
1551 if ((!sc->is_adaptec && EN_ENIDMAFIX) || EN_NOTXDMA || !en_dma) {
1552 if ( ((uintptr_t)mtod(lastm, void *) % sizeof(u_int32_t)) != 0 ||
1553 ((lastm->m_len % sizeof(u_int32_t)) != 0 && lastm->m_next)) {
1554 first = (lastm == m);
1555 if (en_mfix(sc, &lastm, prev) == 0) { /* failed? */
1561 m = lastm; /* update */
1566 mlen += lastm->m_len;
1567 if (lastm->m_next == NULL)
1569 lastm = lastm->m_next;
1572 if (m == NULL) /* happens only if mfix fails */
1575 ap = mtod(m, struct atm_pseudohdr *);
1577 atm_vpi = ATM_PH_VPI(ap);
1578 atm_vci = ATM_PH_VCI(ap);
1579 atm_flags = ATM_PH_FLAGS(ap) & ~(EN_OBHDR|EN_OBTRL);
1580 aal = ((atm_flags & ATM_PH_AAL5) != 0)
1581 ? MID_TBD_AAL5 : MID_TBD_NOAAL5;
1584 * check that vpi/vci is one we can use
1587 if (atm_vpi || atm_vci > MID_N_VC) {
1588 printf("%s: output vpi=%d, vci=%d out of card range, dropping...\n",
1589 sc->sc_dev.dv_xname, atm_vpi, atm_vci);
1595 * computing how much padding we need on the end of the mbuf, then
1596 * see if we can put the TBD at the front of the mbuf where the
1597 * link header goes (well behaved protocols will reserve room for us).
1598 * last, check if room for PDU tail.
1600 * got = number of bytes of data we have
1601 * cellcnt = number of cells in this mbuf
1602 * need = number of bytes of data + padding we need (excludes TBD)
1603 * toadd = number of bytes of data we need to add to end of mbuf,
1604 * [including AAL5 PDU, if AAL5]
1607 got = mlen - sizeof(struct atm_pseudohdr *);
1608 toadd = (aal == MID_TBD_AAL5) ? MID_PDU_SIZE : 0; /* PDU */
1609 cellcnt = (got + toadd + (MID_ATMDATASZ - 1)) / MID_ATMDATASZ;
1610 need = cellcnt * MID_ATMDATASZ;
1611 toadd = need - got; /* recompute, including zero padding */
1614 printf("%s: txvci%d: mlen=%d, got=%d, need=%d, toadd=%d, cell#=%d\n",
1615 sc->sc_dev.dv_xname, atm_vci, mlen, got, need, toadd, cellcnt);
1616 printf(" leading_space=%d, trailing_space=%d\n",
1617 M_LEADINGSPACE(m), M_TRAILINGSPACE(lastm));
1623 * note: external storage (M_EXT) can be shared between mbufs
1624 * to avoid copying (see m_copym()). this means that the same
1625 * data buffer could be shared by several mbufs, and thus it isn't
1626 * a good idea to try and write TBDs or PDUs to M_EXT data areas.
1629 if (M_LEADINGSPACE(m) >= MID_TBD_SIZE && (m->m_flags & M_EXT) == 0) {
1630 m->m_data -= MID_TBD_SIZE;
1631 m->m_len += MID_TBD_SIZE;
1632 mlen += MID_TBD_SIZE;
1633 new_ap = mtod(m, struct atm_pseudohdr *);
1634 *new_ap = *ap; /* move it back */
1636 dat = ((u_int32_t *) ap) + 1;
1637 /* make sure the TBD is in proper byte order */
1638 *dat++ = htonl(MID_TBD_MK1(aal, sc->txspeed[atm_vci], cellcnt));
1639 *dat = htonl(MID_TBD_MK2(atm_vci, 0, 0));
1640 atm_flags |= EN_OBHDR;
1643 if (toadd && (lastm->m_flags & M_EXT) == 0 &&
1644 M_TRAILINGSPACE(lastm) >= toadd) {
1645 cp = mtod(lastm, u_int8_t *) + lastm->m_len;
1646 lastm->m_len += toadd;
1648 if (aal == MID_TBD_AAL5) {
1649 bzero(cp, toadd - MID_PDU_SIZE);
1650 dat = (u_int32_t *)(cp + toadd - MID_PDU_SIZE);
1651 /* make sure the PDU is in proper byte order */
1652 *dat = htonl(MID_PDU_MK1(0, 0, got));
1656 atm_flags |= EN_OBTRL;
1658 ATM_PH_FLAGS(ap) = atm_flags; /* update EN_OBHDR/EN_OBTRL bits */
1659 #endif /* EN_MBUF_OPT */
1662 * get assigned channel (will be zero unless txspeed[atm_vci] is set)
1665 txchan = sc->txvc2slot[atm_vci];
1667 if (sc->txslot[txchan].mbsize > EN_TXHIWAT) {
1668 EN_COUNT(sc->txmbovr);
1671 printf("%s: tx%d: buffer space shortage\n", sc->sc_dev.dv_xname,
1677 sc->txslot[txchan].mbsize += mlen;
1680 printf("%s: tx%d: VPI=%d, VCI=%d, FLAGS=0x%x, speed=0x%x\n",
1681 sc->sc_dev.dv_xname, txchan, atm_vpi, atm_vci, atm_flags,
1682 sc->txspeed[atm_vci]);
1683 printf(" adjusted mlen=%d, mbsize=%d\n", mlen,
1684 sc->txslot[txchan].mbsize);
1687 IF_ENQUEUE(&sc->txslot[txchan].q, m);
1689 en_txdma(sc, txchan);
1697 * en_mfix: fix a stupid mbuf
1700 STATIC int en_makeexclusive(struct en_softc *, struct mbuf **, struct mbuf *);
1702 STATIC int en_makeexclusive(sc, mm, prev)
1703 struct en_softc *sc;
1704 struct mbuf **mm, *prev;
1706 struct mbuf *m, *new;
1710 if (m->m_flags & M_EXT) {
1711 if (!(m->m_flags & M_EXT_CLUSTER)) {
1712 /* external buffer isn't an ordinary mbuf cluster! */
1713 printf("%s: mfix: special buffer! can't make a copy!\n",
1714 sc->sc_dev.dv_xname);
1718 if (m_sharecount(m) > 1) {
1719 /* make a real copy of the M_EXT mbuf since it is shared */
1720 new = m_getcl(MB_DONTWAIT, MT_DATA, m->m_flags & M_PKTHDR);
1723 EN_COUNT(sc->mfixfail);
1726 if (m->m_flags & M_PKTHDR)
1727 M_MOVE_PKTHDR(new, m);
1728 bcopy(m->m_data, new->m_data, m->m_len);
1729 new->m_len = m->m_len;
1730 new->m_next = m->m_next;
1737 /* the buffer is not shared, align the data offset using
1739 u_char *d = mtod(m, u_char *);
1740 int off = ((uintptr_t)(void *)d) % sizeof(u_int32_t);
1743 bcopy(d, d - off, m->m_len);
1744 m->m_data = (caddr_t)d - off;
1751 STATIC int en_mfix(sc, mm, prev)
1753 struct en_softc *sc;
1754 struct mbuf **mm, *prev;
1764 EN_COUNT(sc->mfix); /* count # of calls */
1766 printf("%s: mfix mbuf m_data=0x%x, m_len=%d\n", sc->sc_dev.dv_xname,
1767 m->m_data, m->m_len);
1770 d = mtod(m, u_char *);
1771 off = ((uintptr_t) (void *) d) % sizeof(u_int32_t);
1774 if ((m->m_flags & M_EXT) == 0) {
1775 bcopy(d, d - off, m->m_len); /* ALIGN! (with costly data copy...) */
1777 m->m_data = (caddr_t)d;
1779 /* can't write to an M_EXT mbuf since it may be shared */
1780 if (en_makeexclusive(sc, &m, prev) == 0)
1782 *mm = m; /* note: 'd' now invalid */
1786 off = m->m_len % sizeof(u_int32_t);
1790 if (m->m_flags & M_EXT) {
1791 /* can't write to an M_EXT mbuf since it may be shared */
1792 if (en_makeexclusive(sc, &m, prev) == 0)
1794 *mm = m; /* note: 'd' now invalid */
1797 d = mtod(m, u_char *) + m->m_len;
1798 off = sizeof(u_int32_t) - off;
1802 if (nxt != NULL && nxt->m_len == 0) {
1803 /* remove an empty mbuf. this avoids odd byte padding to an empty
1805 m->m_next = nxt = m_free(nxt);
1807 if (nxt == NULL) { /* out of data, zero fill */
1809 continue; /* next "off" */
1811 cp = mtod(nxt, u_char *);
1815 nxt->m_data = (caddr_t)cp;
1817 if (nxt != NULL && nxt->m_len == 0)
1818 m->m_next = m_free(nxt);
1823 * en_txdma: start trasmit DMA, if possible
1826 STATIC void en_txdma(sc, chan)
1828 struct en_softc *sc;
1833 struct atm_pseudohdr *ap;
1834 struct en_launch launch;
1835 int datalen = 0, dtqneed, len, ncells;
1840 printf("%s: tx%d: starting...\n", sc->sc_dev.dv_xname, chan);
1844 * note: now that txlaunch handles non-word aligned/sized requests
1845 * the only time you can safely set launch.nodma is if you've en_mfix()'d
1846 * the mbuf chain. this happens only if EN_NOTXDMA || !en_dma.
1849 launch.nodma = (EN_NOTXDMA || !en_dma);
1854 * get an mbuf waiting for DMA
1857 launch.t = sc->txslot[chan].q.ifq_head; /* peek at head of queue */
1859 if (launch.t == NULL) {
1861 printf("%s: tx%d: ...done!\n", sc->sc_dev.dv_xname, chan);
1863 return; /* >>> exit here if no data waiting for DMA <<< */
1869 * note: launch.need = # bytes we need to get on the card
1870 * dtqneed = # of DTQs we need for this packet
1871 * launch.mlen = # of bytes in in mbuf chain (<= launch.need)
1874 ap = mtod(launch.t, struct atm_pseudohdr *);
1875 launch.atm_vci = ATM_PH_VCI(ap);
1876 launch.atm_flags = ATM_PH_FLAGS(ap);
1877 launch.aal = ((launch.atm_flags & ATM_PH_AAL5) != 0) ?
1878 MID_TBD_AAL5 : MID_TBD_NOAAL5;
1881 * XXX: have to recompute the length again, even though we already did
1882 * it in en_start(). might as well compute dtqneed here as well, so
1883 * this isn't that bad.
1886 if ((launch.atm_flags & EN_OBHDR) == 0) {
1887 dtqneed = 1; /* header still needs to be added */
1888 launch.need = MID_TBD_SIZE; /* not includeded with mbuf */
1890 dtqneed = 0; /* header on-board, dma with mbuf */
1895 for (tmp = launch.t ; tmp != NULL ; tmp = tmp->m_next) {
1898 cp = mtod(tmp, u_int8_t *);
1899 if (tmp == launch.t) {
1900 len -= sizeof(struct atm_pseudohdr); /* don't count this! */
1901 cp += sizeof(struct atm_pseudohdr);
1905 continue; /* atm_pseudohdr alone in first mbuf */
1907 dtqneed += en_dqneed(sc, (caddr_t) cp, len, 1);
1910 if ((launch.need % sizeof(u_int32_t)) != 0)
1911 dtqneed++; /* need DTQ to FLUSH internal buffer */
1913 if ((launch.atm_flags & EN_OBTRL) == 0) {
1914 if (launch.aal == MID_TBD_AAL5) {
1915 datalen = launch.need - MID_TBD_SIZE;
1916 launch.need += MID_PDU_SIZE; /* AAL5: need PDU tail */
1918 dtqneed++; /* need to work on the end a bit */
1922 * finish calculation of launch.need (need to figure out how much padding
1923 * we will need). launch.need includes MID_TBD_SIZE, but we need to
1924 * remove that to so we can round off properly. we have to add
1925 * MID_TBD_SIZE back in after calculating ncells.
1928 launch.need = roundup(launch.need - MID_TBD_SIZE, MID_ATMDATASZ);
1929 ncells = launch.need / MID_ATMDATASZ;
1930 launch.need += MID_TBD_SIZE;
1932 if (launch.need > EN_TXSZ * 1024) {
1933 printf("%s: tx%d: packet larger than xmit buffer (%d > %d)\n",
1934 sc->sc_dev.dv_xname, chan, launch.need, EN_TXSZ * 1024);
1939 * note: don't use the entire buffer space. if WRTX becomes equal
1940 * to RDTX, the transmitter stops assuming the buffer is empty! --kjc
1942 if (launch.need >= sc->txslot[chan].bfree) {
1943 EN_COUNT(sc->txoutspace);
1945 printf("%s: tx%d: out of transmit space\n", sc->sc_dev.dv_xname, chan);
1947 return; /* >>> exit here if out of obmem buffer space <<< */
1951 * ensure we have enough dtqs to go, if not, wait for more.
1957 if (dtqneed > sc->dtq_free) {
1959 EN_COUNT(sc->txdtqout);
1961 printf("%s: tx%d: out of transmit DTQs\n", sc->sc_dev.dv_xname, chan);
1963 return; /* >>> exit here if out of dtqs <<< */
1967 * it is a go, commit! dequeue mbuf start working on the xfer.
1970 IF_DEQUEUE(&sc->txslot[chan].q, tmp);
1972 if (launch.t != tmp)
1973 panic("en dequeue");
1974 #endif /* EN_DIAG */
1980 EN_COUNT(sc->launch);
1984 if ((launch.atm_flags & EN_OBHDR) == 0) {
1985 EN_COUNT(sc->lheader);
1986 /* store tbd1/tbd2 in host byte order */
1987 launch.tbd1 = MID_TBD_MK1(launch.aal, sc->txspeed[launch.atm_vci], ncells);
1988 launch.tbd2 = MID_TBD_MK2(launch.atm_vci, 0, 0);
1990 if ((launch.atm_flags & EN_OBTRL) == 0 && launch.aal == MID_TBD_AAL5) {
1991 EN_COUNT(sc->ltail);
1992 launch.pdu1 = MID_PDU_MK1(0, 0, datalen); /* host byte order */
1995 en_txlaunch(sc, chan, &launch);
1999 * adjust the top of the mbuf to skip the pseudo atm header
2000 * (and TBD, if present) before passing the packet to bpf,
2001 * restore it afterwards.
2003 int size = sizeof(struct atm_pseudohdr);
2004 if (launch.atm_flags & EN_OBHDR)
2005 size += MID_TBD_SIZE;
2007 launch.t->m_data += size;
2008 launch.t->m_len -= size;
2010 BPF_MTAP(ifp, launch.t);
2012 launch.t->m_data -= size;
2013 launch.t->m_len += size;
2016 * do some housekeeping and get the next packet
2019 sc->txslot[chan].bfree -= launch.need;
2020 IF_ENQUEUE(&sc->txslot[chan].indma, launch.t);
2024 * END of txdma loop!
2032 IF_DEQUEUE(&sc->txslot[chan].q, tmp);
2033 if (launch.t != tmp)
2034 panic("en dequeue drop");
2036 sc->txslot[chan].mbsize -= launch.mlen;
2042 * en_txlaunch: launch an mbuf into the dma pool!
2045 STATIC void en_txlaunch(sc, chan, l)
2047 struct en_softc *sc;
2049 struct en_launch *l;
2053 u_int32_t cur = sc->txslot[chan].cur,
2054 start = sc->txslot[chan].start,
2055 stop = sc->txslot[chan].stop,
2056 dma, *data, *datastop, count, bcode;
2057 int pad, addtail, need, len, needalign, cnt, end, mx;
2062 * need = # bytes card still needs (decr. to zero)
2063 * len = # of bytes left in current mbuf
2064 * cur = our current pointer
2065 * dma = last place we programmed into the DMA
2066 * data = pointer into data area of mbuf that needs to go next
2067 * cnt = # of bytes to transfer in this DTQ
2068 * bcode/count = DMA burst code, and chip's version of cnt
2070 * a single buffer can require up to 5 DTQs depending on its size
2071 * and alignment requirements. the 5 possible requests are:
2072 * [1] 1, 2, or 3 byte DMA to align src data pointer to word boundary
2073 * [2] alburst DMA to align src data pointer to bestburstlen
2074 * [3] 1 or more bestburstlen DMAs
2075 * [4] clean up burst (to last word boundary)
2076 * [5] 1, 2, or 3 byte final clean up DMA
2081 addtail = (l->atm_flags & EN_OBTRL) == 0; /* add a tail? */
2084 if ((need - MID_TBD_SIZE) % MID_ATMDATASZ)
2085 printf("%s: tx%d: bogus trasmit needs (%d)\n", sc->sc_dev.dv_xname, chan,
2089 printf("%s: tx%d: launch mbuf %p! cur=0x%x[%d], need=%d, addtail=%d\n",
2090 sc->sc_dev.dv_xname, chan, l->t, cur, (cur-start)/4, need, addtail);
2091 count = EN_READ(sc, MIDX_PLACE(chan));
2092 printf(" HW: base_address=0x%x, size=%d, read=%d, descstart=%d\n",
2093 MIDX_BASE(count), MIDX_SZ(count), EN_READ(sc, MIDX_READPTR(chan)),
2094 EN_READ(sc, MIDX_DESCSTART(chan)));
2098 * do we need to insert the TBD by hand?
2099 * note that tbd1/tbd2/pdu1 are in host byte order.
2102 if ((l->atm_flags & EN_OBHDR) == 0) {
2104 printf("%s: tx%d: insert header 0x%x 0x%x\n", sc->sc_dev.dv_xname,
2105 chan, l->tbd1, l->tbd2);
2107 EN_WRITE(sc, cur, l->tbd1);
2108 EN_WRAPADD(start, stop, cur, 4);
2109 EN_WRITE(sc, cur, l->tbd2);
2110 EN_WRAPADD(start, stop, cur, 4);
2115 * now do the mbufs...
2118 for (tmp = l->t ; tmp != NULL ; tmp = tmp->m_next) {
2120 /* get pointer to data and length */
2121 data = mtod(tmp, u_int32_t *);
2124 data += sizeof(struct atm_pseudohdr)/sizeof(u_int32_t);
2125 len -= sizeof(struct atm_pseudohdr);
2128 /* now, determine if we should copy it */
2129 if (l->nodma || (len < EN_MINDMA &&
2130 (len % 4) == 0 && ((uintptr_t) (void *) data % 4) == 0 &&
2134 * roundup len: the only time this will change the value of len
2135 * is when l->nodma is true, tmp is the last mbuf, and there is
2136 * a non-word number of bytes to transmit. in this case it is
2137 * safe to round up because we've en_mfix'd the mbuf (so the first
2138 * byte is word aligned there must be enough free bytes at the end
2139 * to round off to the next word boundary)...
2141 len = roundup(len, sizeof(u_int32_t));
2142 datastop = data + (len / sizeof(u_int32_t));
2143 /* copy loop: preserve byte order!!! use WRITEDAT */
2144 while (data != datastop) {
2145 EN_WRITEDAT(sc, cur, *data);
2147 EN_WRAPADD(start, stop, cur, 4);
2151 printf("%s: tx%d: copied %d bytes (%d left, cur now 0x%x)\n",
2152 sc->sc_dev.dv_xname, chan, len, need, cur);
2154 continue; /* continue on to next mbuf */
2157 /* going to do DMA, first make sure the dtq is in sync. */
2159 EN_DTQADD(sc, WORD_IDX(start,cur), chan, MIDDMA_JK, 0, 0, 0);
2161 printf("%s: tx%d: dtq_sync: advance pointer to %d\n",
2162 sc->sc_dev.dv_xname, chan, cur);
2167 * if this is the last buffer, and it looks like we are going to need to
2168 * flush the internal buffer, can we extend the length of this mbuf to
2172 if (tmp->m_next == NULL) {
2173 cnt = (need - len) % sizeof(u_int32_t);
2174 if (cnt && M_TRAILINGSPACE(tmp) >= cnt)
2175 len += cnt; /* pad for FLUSH */
2178 #if !defined(MIDWAY_ENIONLY)
2181 * the adaptec DMA engine is smart and handles everything for us.
2184 if (sc->is_adaptec) {
2185 /* need to DMA "len" bytes out to card */
2187 EN_WRAPADD(start, stop, cur, len);
2189 printf("%s: tx%d: adp_dma %d bytes (%d left, cur now 0x%x)\n",
2190 sc->sc_dev.dv_xname, chan, len, need, cur);
2192 end = (need == 0) ? MID_DMA_END : 0;
2193 EN_DTQADD(sc, len, chan, 0, vtophys(data), l->mlen, end);
2196 dma = cur; /* update dma pointer */
2199 #endif /* !MIDWAY_ENIONLY */
2201 #if !defined(MIDWAY_ADPONLY)
2204 * the ENI DMA engine is not so smart and need more help from us
2207 /* do we need to do a DMA op to align to word boundary? */
2208 needalign = (uintptr_t) (void *) data % sizeof(u_int32_t);
2210 EN_COUNT(sc->headbyte);
2211 cnt = sizeof(u_int32_t) - needalign;
2212 if (cnt == 2 && len >= cnt) {
2214 bcode = MIDDMA_2BYTE;
2216 cnt = min(cnt, len); /* prevent overflow */
2218 bcode = MIDDMA_BYTE;
2221 EN_WRAPADD(start, stop, cur, cnt);
2223 printf("%s: tx%d: small al_dma %d bytes (%d left, cur now 0x%x)\n",
2224 sc->sc_dev.dv_xname, chan, cnt, need, cur);
2227 end = (need == 0) ? MID_DMA_END : 0;
2228 EN_DTQADD(sc, count, chan, bcode, vtophys(data), l->mlen, end);
2231 data = (u_int32_t *) ((u_char *)data + cnt);
2234 /* do we need to do a DMA op to align? */
2236 (needalign = (((uintptr_t) (void *) data) & sc->bestburstmask)) != 0
2237 && len >= sizeof(u_int32_t)) {
2238 cnt = sc->bestburstlen - needalign;
2239 mx = len & ~(sizeof(u_int32_t)-1); /* don't go past end */
2242 count = cnt / sizeof(u_int32_t);
2243 bcode = MIDDMA_WORD;
2245 count = cnt / sizeof(u_int32_t);
2246 bcode = en_dmaplan[count].bcode;
2247 count = cnt >> en_dmaplan[count].divshift;
2250 EN_WRAPADD(start, stop, cur, cnt);
2252 printf("%s: tx%d: al_dma %d bytes (%d left, cur now 0x%x)\n",
2253 sc->sc_dev.dv_xname, chan, cnt, need, cur);
2256 end = (need == 0) ? MID_DMA_END : 0;
2257 EN_DTQADD(sc, count, chan, bcode, vtophys(data), l->mlen, end);
2260 data = (u_int32_t *) ((u_char *)data + cnt);
2263 /* do we need to do a max-sized burst? */
2264 if (len >= sc->bestburstlen) {
2265 count = len >> sc->bestburstshift;
2266 cnt = count << sc->bestburstshift;
2267 bcode = sc->bestburstcode;
2269 EN_WRAPADD(start, stop, cur, cnt);
2271 printf("%s: tx%d: best_dma %d bytes (%d left, cur now 0x%x)\n",
2272 sc->sc_dev.dv_xname, chan, cnt, need, cur);
2275 end = (need == 0) ? MID_DMA_END : 0;
2276 EN_DTQADD(sc, count, chan, bcode, vtophys(data), l->mlen, end);
2279 data = (u_int32_t *) ((u_char *)data + cnt);
2282 /* do we need to do a cleanup burst? */
2283 cnt = len & ~(sizeof(u_int32_t)-1);
2285 count = cnt / sizeof(u_int32_t);
2286 bcode = en_dmaplan[count].bcode;
2287 count = cnt >> en_dmaplan[count].divshift;
2289 EN_WRAPADD(start, stop, cur, cnt);
2291 printf("%s: tx%d: cleanup_dma %d bytes (%d left, cur now 0x%x)\n",
2292 sc->sc_dev.dv_xname, chan, cnt, need, cur);
2295 end = (need == 0) ? MID_DMA_END : 0;
2296 EN_DTQADD(sc, count, chan, bcode, vtophys(data), l->mlen, end);
2299 data = (u_int32_t *) ((u_char *)data + cnt);
2302 /* any word fragments left? */
2304 EN_COUNT(sc->tailbyte);
2307 bcode = MIDDMA_2BYTE; /* use 2byte mode */
2310 bcode = MIDDMA_BYTE; /* use 1 byte mode */
2313 EN_WRAPADD(start, stop, cur, len);
2315 printf("%s: tx%d: byte cleanup_dma %d bytes (%d left, cur now 0x%x)\n",
2316 sc->sc_dev.dv_xname, chan, len, need, cur);
2318 end = (need == 0) ? MID_DMA_END : 0;
2319 EN_DTQADD(sc, count, chan, bcode, vtophys(data), l->mlen, end);
2324 dma = cur; /* update dma pointer */
2325 #endif /* !MIDWAY_ADPONLY */
2327 } /* next mbuf, please */
2330 * all mbuf data has been copied out to the obmem (or set up to be DMAd).
2331 * if the trailer or padding needs to be put in, do it now.
2333 * NOTE: experimental results reveal the following fact:
2334 * if you DMA "X" bytes to the card, where X is not a multiple of 4,
2335 * then the card will internally buffer the last (X % 4) bytes (in
2336 * hopes of getting (4 - (X % 4)) more bytes to make a complete word).
2337 * it is imporant to make sure we don't leave any important data in
2338 * this internal buffer because it is discarded on the last (end) DTQ.
2339 * one way to do this is to DMA in (4 - (X % 4)) more bytes to flush
2340 * the darn thing out.
2345 pad = need % sizeof(u_int32_t);
2348 * FLUSH internal data buffer. pad out with random data from the front
2349 * of the mbuf chain...
2351 bcode = (sc->is_adaptec) ? 0 : MIDDMA_BYTE;
2352 EN_COUNT(sc->tailflush);
2353 EN_WRAPADD(start, stop, cur, pad);
2354 EN_DTQADD(sc, pad, chan, bcode, vtophys(l->t->m_data), 0, 0);
2357 printf("%s: tx%d: pad/FLUSH dma %d bytes (%d left, cur now 0x%x)\n",
2358 sc->sc_dev.dv_xname, chan, pad, need, cur);
2363 pad = need / sizeof(u_int32_t); /* round *down* */
2364 if (l->aal == MID_TBD_AAL5)
2367 printf("%s: tx%d: padding %d bytes (cur now 0x%x)\n",
2368 sc->sc_dev.dv_xname, chan, pad * sizeof(u_int32_t), cur);
2371 EN_WRITEDAT(sc, cur, 0); /* no byte order issues with zero */
2372 EN_WRAPADD(start, stop, cur, 4);
2374 if (l->aal == MID_TBD_AAL5) {
2375 EN_WRITE(sc, cur, l->pdu1); /* in host byte order */
2376 EN_WRAPADD(start, stop, cur, 8);
2380 if (addtail || dma != cur) {
2381 /* write final descritor */
2382 EN_DTQADD(sc, WORD_IDX(start,cur), chan, MIDDMA_JK, 0,
2383 l->mlen, MID_DMA_END);
2384 /* dma = cur; */ /* not necessary since we are done */
2388 /* update current pointer */
2389 sc->txslot[chan].cur = cur;
2391 printf("%s: tx%d: DONE! cur now = 0x%x\n",
2392 sc->sc_dev.dv_xname, chan, cur);
2403 EN_INTR_TYPE en_intr(arg)
2408 struct en_softc *sc = (struct en_softc *) arg;
2410 struct atm_pseudohdr ah;
2412 u_int32_t reg, kick, val, mask, chip, vci, slot, dtq, drq;
2413 int lcv, idx, need_softserv = 0;
2415 reg = EN_READ(sc, MID_INTACK);
2417 if ((reg & MID_INT_ANY) == 0)
2418 EN_INTR_RET(0); /* not us */
2421 printf("%s: interrupt=0x%b\n", sc->sc_dev.dv_xname, reg, MID_INTBITS);
2425 * unexpected errors that need a reset
2428 if ((reg & (MID_INT_IDENT|MID_INT_LERR|MID_INT_DMA_ERR|MID_INT_SUNI)) != 0) {
2429 printf("%s: unexpected interrupt=0x%b, resetting card\n",
2430 sc->sc_dev.dv_xname, reg, MID_INTBITS);
2433 Debugger("en: unexpected error");
2435 sc->enif.if_flags &= ~IFF_RUNNING; /* FREEZE! */
2440 EN_INTR_RET(1); /* for us */
2443 /*******************
2447 kick = 0; /* bitmask of channels to kick */
2448 if (reg & MID_INT_TX) { /* TX done! */
2451 * check for tx complete, if detected then this means that some space
2452 * has come free on the card. we must account for it and arrange to
2453 * kick the channel to life (in case it is stalled waiting on the card).
2455 for (mask = 1, lcv = 0 ; lcv < EN_NTX ; lcv++, mask = mask * 2) {
2456 if (reg & MID_TXCHAN(lcv)) {
2457 kick = kick | mask; /* want to kick later */
2458 val = EN_READ(sc, MIDX_READPTR(lcv)); /* current read pointer */
2459 val = (val * sizeof(u_int32_t)) + sc->txslot[lcv].start;
2460 /* convert to offset */
2461 if (val > sc->txslot[lcv].cur)
2462 sc->txslot[lcv].bfree = val - sc->txslot[lcv].cur;
2464 sc->txslot[lcv].bfree = (val + (EN_TXSZ*1024)) - sc->txslot[lcv].cur;
2466 printf("%s: tx%d: trasmit done. %d bytes now free in buffer\n",
2467 sc->sc_dev.dv_xname, lcv, sc->txslot[lcv].bfree);
2473 if (reg & MID_INT_DMA_TX) { /* TX DMA done! */
2476 * check for TX DMA complete, if detected then this means that some DTQs
2477 * are now free. it also means some indma mbufs can be freed.
2478 * if we needed DTQs, kick all channels.
2480 val = EN_READ(sc, MID_DMA_RDTX); /* chip's current location */
2481 idx = MID_DTQ_A2REG(sc->dtq_chip);/* where we last saw chip */
2482 if (sc->need_dtqs) {
2483 kick = MID_NTX_CH - 1; /* assume power of 2, kick all! */
2484 sc->need_dtqs = 0; /* recalculated in "kick" loop below */
2486 printf("%s: cleared need DTQ condition\n", sc->sc_dev.dv_xname);
2489 while (idx != val) {
2491 if ((dtq = sc->dtq[idx]) != 0) {
2492 sc->dtq[idx] = 0; /* don't forget to zero it out when done */
2493 slot = EN_DQ_SLOT(dtq);
2494 IF_DEQUEUE(&sc->txslot[slot].indma, m);
2495 if (!m) panic("enintr: dtqsync");
2496 sc->txslot[slot].mbsize -= EN_DQ_LEN(dtq);
2498 printf("%s: tx%d: free %d dma bytes, mbsize now %d\n",
2499 sc->sc_dev.dv_xname, slot, EN_DQ_LEN(dtq),
2500 sc->txslot[slot].mbsize);
2504 EN_WRAPADD(0, MID_DTQ_N, idx, 1);
2506 sc->dtq_chip = MID_DTQ_REG2A(val); /* sync softc */
2511 * kick xmit channels as needed
2516 printf("%s: tx kick mask = 0x%x\n", sc->sc_dev.dv_xname, kick);
2518 for (mask = 1, lcv = 0 ; lcv < EN_NTX ; lcv++, mask = mask * 2) {
2519 if ((kick & mask) && sc->txslot[lcv].q.ifq_head) {
2520 en_txdma(sc, lcv); /* kick it! */
2522 } /* for each slot */
2526 /*******************
2531 * check for RX DMA complete, and pass the data "upstairs"
2534 if (reg & MID_INT_DMA_RX) {
2535 val = EN_READ(sc, MID_DMA_RDRX); /* chip's current location */
2536 idx = MID_DRQ_A2REG(sc->drq_chip);/* where we last saw chip */
2537 while (idx != val) {
2539 if ((drq = sc->drq[idx]) != 0) {
2540 sc->drq[idx] = 0; /* don't forget to zero it out when done */
2541 slot = EN_DQ_SLOT(drq);
2542 if (EN_DQ_LEN(drq) == 0) { /* "JK" trash DMA? */
2545 IF_DEQUEUE(&sc->rxslot[slot].indma, m);
2547 panic("enintr: drqsync: %s: lost mbuf in slot %d!",
2548 sc->sc_dev.dv_xname, slot);
2550 /* do something with this mbuf */
2551 if (sc->rxslot[slot].oth_flags & ENOTHER_DRAIN) { /* drain? */
2554 vci = sc->rxslot[slot].atm_vci;
2555 if (sc->rxslot[slot].indma.ifq_head == NULL &&
2556 sc->rxslot[slot].q.ifq_head == NULL &&
2557 (EN_READ(sc, MID_VC(vci)) & MIDV_INSERVICE) == 0 &&
2558 (sc->rxslot[slot].oth_flags & ENOTHER_SWSL) == 0) {
2559 sc->rxslot[slot].oth_flags = ENOTHER_FREE; /* done drain */
2560 sc->rxslot[slot].atm_vci = RX_NONE;
2561 sc->rxvc2slot[vci] = RX_NONE;
2563 printf("%s: rx%d: VCI %d now free\n", sc->sc_dev.dv_xname,
2567 } else if (m != NULL) {
2568 ATM_PH_FLAGS(&ah) = sc->rxslot[slot].atm_flags;
2569 ATM_PH_VPI(&ah) = 0;
2570 ATM_PH_SETVCI(&ah, sc->rxslot[slot].atm_vci);
2572 printf("%s: rx%d: rxvci%d: atm_input, mbuf %p, len %d, hand %p\n",
2573 sc->sc_dev.dv_xname, slot, sc->rxslot[slot].atm_vci, m,
2574 EN_DQ_LEN(drq), sc->rxslot[slot].rxhand);
2582 atm_input(ifp, &ah, m, sc->rxslot[slot].rxhand);
2586 EN_WRAPADD(0, MID_DRQ_N, idx, 1);
2588 sc->drq_chip = MID_DRQ_REG2A(val); /* sync softc */
2590 if (sc->need_drqs) { /* true if we had a DRQ shortage */
2594 printf("%s: cleared need DRQ condition\n", sc->sc_dev.dv_xname);
2600 * handle service interrupts
2603 if (reg & MID_INT_SERVICE) {
2604 chip = MID_SL_REG2A(EN_READ(sc, MID_SERV_WRITE));
2606 while (sc->hwslistp != chip) {
2608 /* fetch and remove it from hardware service list */
2609 vci = EN_READ(sc, sc->hwslistp);
2610 EN_WRAPADD(MID_SLOFF, MID_SLEND, sc->hwslistp, 4);/* advance hw ptr */
2611 slot = sc->rxvc2slot[vci];
2612 if (slot == RX_NONE) {
2614 printf("%s: unexpected rx interrupt on VCI %d\n",
2615 sc->sc_dev.dv_xname, vci);
2617 EN_WRITE(sc, MID_VC(vci), MIDV_TRASH); /* rx off, damn it! */
2618 continue; /* next */
2620 EN_WRITE(sc, MID_VC(vci), sc->rxslot[slot].mode); /* remove from hwsl */
2621 EN_COUNT(sc->hwpull);
2624 printf("%s: pulled VCI %d off hwslist\n", sc->sc_dev.dv_xname, vci);
2627 /* add it to the software service list (if needed) */
2628 if ((sc->rxslot[slot].oth_flags & ENOTHER_SWSL) == 0) {
2629 EN_COUNT(sc->swadd);
2631 sc->rxslot[slot].oth_flags |= ENOTHER_SWSL;
2632 sc->swslist[sc->swsl_tail] = slot;
2633 EN_WRAPADD(0, MID_SL_N, sc->swsl_tail, 1);
2636 printf("%s: added VCI %d to swslist\n", sc->sc_dev.dv_xname, vci);
2643 * now service (function too big to include here)
2653 if (reg & MID_INT_DMA_OVR) {
2654 EN_COUNT(sc->dmaovr);
2656 printf("%s: MID_INT_DMA_OVR\n", sc->sc_dev.dv_xname);
2659 reg = EN_READ(sc, MID_STAT);
2661 sc->otrash += MID_OTRASH(reg);
2662 sc->vtrash += MID_VTRASH(reg);
2665 EN_INTR_RET(1); /* for us */
2670 * en_service: handle a service interrupt
2672 * Q: why do we need a software service list?
2674 * A: if we remove a VCI from the hardware list and we find that we are
2675 * out of DRQs we must defer processing until some DRQs become free.
2676 * so we must remember to look at this RX VCI/slot later, but we can't
2677 * put it back on the hardware service list (since that isn't allowed).
2678 * so we instead save it on the software service list. it would be nice
2679 * if we could peek at the VCI on top of the hwservice list without removing
2680 * it, however this leads to a race condition: if we peek at it and
2681 * decide we are done with it new data could come in before we have a
2682 * chance to remove it from the hwslist. by the time we get it out of
2683 * the list the interrupt for the new data will be lost. oops!
2687 STATIC void en_service(sc)
2689 struct en_softc *sc;
2692 struct mbuf *m, *tmp;
2693 u_int32_t cur, dstart, rbd, pdu, *sav, dma, bcode, count, *data, *datastop;
2694 u_int32_t start, stop, cnt, needalign;
2695 int slot, raw, aal5, llc, vci, fill, mlen, tlen, drqneed, need, needfill, end;
2697 aal5 = 0; /* Silence gcc */
2699 if (sc->swsl_size == 0) {
2701 printf("%s: en_service done\n", sc->sc_dev.dv_xname);
2703 return; /* >>> exit here if swsl now empty <<< */
2707 * get slot/vci to service
2710 slot = sc->swslist[sc->swsl_head];
2711 vci = sc->rxslot[slot].atm_vci;
2713 if (sc->rxvc2slot[vci] != slot) panic("en_service rx slot/vci sync");
2717 * determine our mode and if we've got any work to do
2720 raw = sc->rxslot[slot].oth_flags & ENOTHER_RAW;
2721 start= sc->rxslot[slot].start;
2722 stop= sc->rxslot[slot].stop;
2723 cur = sc->rxslot[slot].cur;
2726 printf("%s: rx%d: service vci=%d raw=%d start/stop/cur=0x%x 0x%x 0x%x\n",
2727 sc->sc_dev.dv_xname, slot, vci, raw, start, stop, cur);
2731 dstart = MIDV_DSTART(EN_READ(sc, MID_DST_RP(vci)));
2732 dstart = (dstart * sizeof(u_int32_t)) + start;
2734 /* check to see if there is any data at all */
2735 if (dstart == cur) {
2736 defer: /* defer processing */
2737 EN_WRAPADD(0, MID_SL_N, sc->swsl_head, 1);
2738 sc->rxslot[slot].oth_flags &= ~ENOTHER_SWSL;
2740 /* >>> remove from swslist <<< */
2742 printf("%s: rx%d: remove vci %d from swslist\n",
2743 sc->sc_dev.dv_xname, slot, vci);
2749 * figure out how many bytes we need
2750 * [mlen = # bytes to go in mbufs, fill = # bytes to dump (MIDDMA_JK)]
2755 /* raw mode (aka boodi mode) */
2758 mlen = dstart - cur;
2760 mlen = (dstart + (EN_RXSZ*1024)) - cur;
2762 if (mlen < sc->rxslot[slot].raw_threshold)
2763 goto defer; /* too little data to deal with */
2768 aal5 = (sc->rxslot[slot].atm_flags & ATM_PH_AAL5);
2769 llc = (aal5 && (sc->rxslot[slot].atm_flags & ATM_PH_LLCSNAP)) ? 1 : 0;
2770 rbd = EN_READ(sc, cur);
2771 if (MID_RBD_ID(rbd) != MID_RBD_STDID)
2772 panic("en_service: id mismatch");
2774 if (rbd & MID_RBD_T) {
2775 mlen = 0; /* we've got trash */
2776 fill = MID_RBD_SIZE;
2777 EN_COUNT(sc->ttrash);
2779 printf("RX overflow lost %d cells!\n", MID_RBD_CNT(rbd));
2782 mlen = MID_RBD_SIZE + MID_CHDR_SIZE + MID_ATMDATASZ; /* 1 cell (ick!) */
2787 tlen = (MID_RBD_CNT(rbd) * MID_ATMDATASZ) + MID_RBD_SIZE;
2788 pdu = cur + tlen - MID_PDU_SIZE;
2790 pdu -= (EN_RXSZ*1024);
2791 pdu = EN_READ(sc, pdu); /* get PDU in correct byte order */
2792 fill = tlen - MID_RBD_SIZE - MID_PDU_LEN(pdu);
2793 if (fill < 0 || (rbd & MID_RBD_CRCERR) != 0) {
2794 static int first = 1;
2797 printf("%s: %s, dropping frame\n", sc->sc_dev.dv_xname,
2798 (rbd & MID_RBD_CRCERR) ?
2799 "CRC error" : "invalid AAL5 PDU length");
2800 printf("%s: got %d cells (%d bytes), AAL5 len is %d bytes (pdu=0x%x)\n",
2801 sc->sc_dev.dv_xname, MID_RBD_CNT(rbd),
2802 tlen - MID_RBD_SIZE, MID_PDU_LEN(pdu), pdu);
2804 printf("CRC error report disabled from now on!\n");
2820 * now allocate mbufs for mlen bytes of data, if out of mbufs, trash all
2823 * 1. it is possible that we've already allocated an mbuf for this pkt
2824 * but ran out of DRQs, in which case we saved the allocated mbuf on
2826 * 2. if we save an mbuf in "q" we store the "cur" (pointer) in the front
2827 * of the mbuf as an identity (that we can check later), and we also
2828 * store drqneed (so we don't have to recompute it).
2829 * 3. after this block of code, if m is still NULL then we ran out of mbufs
2832 m = sc->rxslot[slot].q.ifq_head;
2835 sav = mtod(m, u_int32_t *);
2836 if (sav[0] != cur) {
2838 printf("%s: rx%d: q'ed mbuf %p not ours\n",
2839 sc->sc_dev.dv_xname, slot, m);
2841 m = NULL; /* wasn't ours */
2842 EN_COUNT(sc->rxqnotus);
2844 EN_COUNT(sc->rxqus);
2845 IF_DEQUEUE(&sc->rxslot[slot].q, m);
2848 printf("%s: rx%d: recovered q'ed mbuf %p (drqneed=%d)\n",
2849 sc->sc_dev.dv_xname, slot, m, drqneed);
2854 if (mlen != 0 && m == NULL) {
2855 m = en_mget(sc, mlen, &drqneed); /* allocate! */
2859 EN_COUNT(sc->rxmbufout);
2861 printf("%s: rx%d: out of mbufs\n", sc->sc_dev.dv_xname, slot);
2865 printf("%s: rx%d: allocate mbuf %p, mlen=%d, drqneed=%d\n",
2866 sc->sc_dev.dv_xname, slot, m, mlen, drqneed);
2871 printf("%s: rx%d: VCI %d, mbuf_chain %p, mlen %d, fill %d\n",
2872 sc->sc_dev.dv_xname, slot, vci, m, mlen, fill);
2876 * now check to see if we've got the DRQs needed. if we are out of
2877 * DRQs we must quit (saving our mbuf, if we've got one).
2880 needfill = (fill) ? 1 : 0;
2881 if (drqneed + needfill > sc->drq_free) {
2882 sc->need_drqs = 1; /* flag condition */
2884 EN_COUNT(sc->rxoutboth);
2886 printf("%s: rx%d: out of DRQs *and* mbufs!\n", sc->sc_dev.dv_xname, slot);
2888 return; /* >>> exit here if out of both mbufs and DRQs <<< */
2890 sav = mtod(m, u_int32_t *);
2893 IF_ENQUEUE(&sc->rxslot[slot].q, m);
2894 EN_COUNT(sc->rxdrqout);
2896 printf("%s: rx%d: out of DRQs\n", sc->sc_dev.dv_xname, slot);
2898 return; /* >>> exit here if out of DRQs <<< */
2902 * at this point all resources have been allocated and we are commited
2903 * to servicing this slot.
2905 * dma = last location we told chip about
2906 * cur = current location
2907 * mlen = space in the mbuf we want
2908 * need = bytes to xfer in (decrs to zero)
2909 * fill = how much fill we need
2910 * tlen = how much data to transfer to this mbuf
2911 * cnt/bcode/count = <same as xmit>
2913 * 'needfill' not used after this point
2916 dma = cur; /* dma = last location we told chip about */
2917 need = roundup(mlen, sizeof(u_int32_t));
2918 fill = fill - (need - mlen); /* note: may invalidate 'needfill' */
2920 for (tmp = m ; tmp != NULL && need > 0 ; tmp = tmp->m_next) {
2921 tlen = roundup(tmp->m_len, sizeof(u_int32_t)); /* m_len set by en_mget */
2922 data = mtod(tmp, u_int32_t *);
2925 printf("%s: rx%d: load mbuf %p, m_len=%d, m_data=%p, tlen=%d\n",
2926 sc->sc_dev.dv_xname, slot, tmp, tmp->m_len, tmp->m_data, tlen);
2930 if (EN_NORXDMA || !en_dma || tlen < EN_MINDMA) {
2931 datastop = (u_int32_t *)((u_char *) data + tlen);
2932 /* copy loop: preserve byte order!!! use READDAT */
2933 while (data != datastop) {
2934 *data = EN_READDAT(sc, cur);
2936 EN_WRAPADD(start, stop, cur, 4);
2940 printf("%s: rx%d: vci%d: copied %d bytes (%d left)\n",
2941 sc->sc_dev.dv_xname, slot, vci, tlen, need);
2946 /* DMA data (check to see if we need to sync DRQ first) */
2948 EN_DRQADD(sc, WORD_IDX(start,cur), vci, MIDDMA_JK, 0, 0, 0, 0);
2950 printf("%s: rx%d: vci%d: drq_sync: advance pointer to %d\n",
2951 sc->sc_dev.dv_xname, slot, vci, cur);
2955 #if !defined(MIDWAY_ENIONLY)
2958 * the adaptec DMA engine is smart and handles everything for us.
2961 if (sc->is_adaptec) {
2963 EN_WRAPADD(start, stop, cur, tlen);
2965 printf("%s: rx%d: vci%d: adp_dma %d bytes (%d left)\n",
2966 sc->sc_dev.dv_xname, slot, vci, tlen, need);
2968 end = (need == 0 && !fill) ? MID_DMA_END : 0;
2969 EN_DRQADD(sc, tlen, vci, 0, vtophys(data), mlen, slot, end);
2972 dma = cur; /* update dma pointer */
2975 #endif /* !MIDWAY_ENIONLY */
2978 #if !defined(MIDWAY_ADPONLY)
2981 * the ENI DMA engine is not so smart and need more help from us
2984 /* do we need to do a DMA op to align? */
2986 (needalign = (((uintptr_t) (void *) data) & sc->bestburstmask)) != 0) {
2987 cnt = sc->bestburstlen - needalign;
2990 count = cnt / sizeof(u_int32_t);
2991 bcode = MIDDMA_WORD;
2993 count = cnt / sizeof(u_int32_t);
2994 bcode = en_dmaplan[count].bcode;
2995 count = cnt >> en_dmaplan[count].divshift;
2998 EN_WRAPADD(start, stop, cur, cnt);
3000 printf("%s: rx%d: vci%d: al_dma %d bytes (%d left)\n",
3001 sc->sc_dev.dv_xname, slot, vci, cnt, need);
3004 end = (need == 0 && !fill) ? MID_DMA_END : 0;
3005 EN_DRQADD(sc, count, vci, bcode, vtophys(data), mlen, slot, end);
3008 data = (u_int32_t *)((u_char *) data + cnt);
3011 /* do we need a max-sized burst? */
3012 if (tlen >= sc->bestburstlen) {
3013 count = tlen >> sc->bestburstshift;
3014 cnt = count << sc->bestburstshift;
3015 bcode = sc->bestburstcode;
3017 EN_WRAPADD(start, stop, cur, cnt);
3019 printf("%s: rx%d: vci%d: best_dma %d bytes (%d left)\n",
3020 sc->sc_dev.dv_xname, slot, vci, cnt, need);
3023 end = (need == 0 && !fill) ? MID_DMA_END : 0;
3024 EN_DRQADD(sc, count, vci, bcode, vtophys(data), mlen, slot, end);
3027 data = (u_int32_t *)((u_char *) data + cnt);
3030 /* do we need to do a cleanup burst? */
3032 count = tlen / sizeof(u_int32_t);
3033 bcode = en_dmaplan[count].bcode;
3034 count = tlen >> en_dmaplan[count].divshift;
3036 EN_WRAPADD(start, stop, cur, tlen);
3038 printf("%s: rx%d: vci%d: cleanup_dma %d bytes (%d left)\n",
3039 sc->sc_dev.dv_xname, slot, vci, tlen, need);
3041 end = (need == 0 && !fill) ? MID_DMA_END : 0;
3042 EN_DRQADD(sc, count, vci, bcode, vtophys(data), mlen, slot, end);
3047 dma = cur; /* update dma pointer */
3049 #endif /* !MIDWAY_ADPONLY */
3054 if (fill || dma != cur) {
3057 printf("%s: rx%d: vci%d: skipping %d bytes of fill\n",
3058 sc->sc_dev.dv_xname, slot, vci, fill);
3060 printf("%s: rx%d: vci%d: syncing chip from 0x%x to 0x%x [cur]\n",
3061 sc->sc_dev.dv_xname, slot, vci, dma, cur);
3063 EN_WRAPADD(start, stop, cur, fill);
3064 EN_DRQADD(sc, WORD_IDX(start,cur), vci, MIDDMA_JK, 0, mlen,
3066 /* dma = cur; */ /* not necessary since we are done */
3070 * done, remove stuff we don't want to pass up:
3071 * raw mode (boodi mode): pass everything up for later processing
3073 * aal0: remove RBD + cell header
3080 if (!aal5) cnt += MID_CHDR_SIZE;
3081 m->m_len -= cnt; /* chop! */
3082 m->m_pkthdr.len -= cnt;
3085 IF_ENQUEUE(&sc->rxslot[slot].indma, m);
3087 sc->rxslot[slot].cur = cur; /* update master copy of 'cur' */
3090 printf("%s: rx%d: vci%d: DONE! cur now =0x%x\n",
3091 sc->sc_dev.dv_xname, slot, vci, cur);
3094 goto same_vci; /* get next packet in this slot */
3100 * functions we can call from ddb
3104 * en_dump: dump the state
3107 #define END_SWSL 0x00000040 /* swsl state */
3108 #define END_DRQ 0x00000020 /* drq state */
3109 #define END_DTQ 0x00000010 /* dtq state */
3110 #define END_RX 0x00000008 /* rx state */
3111 #define END_TX 0x00000004 /* tx state */
3112 #define END_MREGS 0x00000002 /* registers */
3113 #define END_STATS 0x00000001 /* dump stats */
3115 #define END_BITS "\20\7SWSL\6DRQ\5DTQ\4RX\3TX\2MREGS\1STATS"
3117 /* Do not staticize - meant for calling from DDB! */
3118 int en_dump(unit, level)
3123 struct en_softc *sc;
3127 for (lcv = 0 ; lcv < en_cd.cd_ndevs ; lcv++) {
3128 sc = (struct en_softc *) en_cd.cd_devs[lcv];
3129 if (sc == NULL) continue;
3130 if (unit != -1 && unit != lcv)
3133 printf("dumping device %s at level 0x%b\n", sc->sc_dev.dv_xname, level,
3136 if (sc->dtq_us == 0) {
3137 printf("<hasn't been en_init'd yet>\n");
3141 if (level & END_STATS) {
3142 printf(" en_stats:\n");
3143 printf(" %d mfix (%d failed); %d/%d head/tail byte DMAs, %d flushes\n",
3144 sc->mfix, sc->mfixfail, sc->headbyte, sc->tailbyte, sc->tailflush);
3145 printf(" %d rx dma overflow interrupts\n", sc->dmaovr);
3146 printf(" %d times we ran out of TX space and stalled\n",
3148 printf(" %d times we ran out of DTQs\n", sc->txdtqout);
3149 printf(" %d times we launched a packet\n", sc->launch);
3150 printf(" %d times we launched without on-board header\n", sc->lheader);
3151 printf(" %d times we launched without on-board tail\n", sc->ltail);
3152 printf(" %d times we pulled the hw service list\n", sc->hwpull);
3153 printf(" %d times we pushed a vci on the sw service list\n",
3155 printf(" %d times RX pulled an mbuf from Q that wasn't ours\n",
3157 printf(" %d times RX pulled a good mbuf from Q\n", sc->rxqus);
3158 printf(" %d times we ran out of mbufs *and* DRQs\n", sc->rxoutboth);
3159 printf(" %d times we ran out of DRQs\n", sc->rxdrqout);
3161 printf(" %d trasmit packets dropped due to mbsize\n", sc->txmbovr);
3162 printf(" %d cells trashed due to turned off rxvc\n", sc->vtrash);
3163 printf(" %d cells trashed due to totally full buffer\n", sc->otrash);
3164 printf(" %d cells trashed due almost full buffer\n", sc->ttrash);
3165 printf(" %d rx mbuf allocation failures\n", sc->rxmbufout);
3166 #if defined(NATM) && defined(NATM_STAT)
3167 printf(" natmintr so_rcv: ok/drop cnt: %d/%d, ok/drop bytes: %d/%d\n",
3168 natm_sookcnt, natm_sodropcnt, natm_sookbytes, natm_sodropbytes);
3172 if (level & END_MREGS) {
3174 printf("resid = 0x%lx\n", (u_long)EN_READ(sc, MID_RESID));
3175 printf("interrupt status = 0x%b\n",
3176 (int)EN_READ(sc, MID_INTSTAT), MID_INTBITS);
3177 printf("interrupt enable = 0x%b\n",
3178 (int)EN_READ(sc, MID_INTENA), MID_INTBITS);
3179 printf("mcsr = 0x%b\n", (int)EN_READ(sc, MID_MAST_CSR), MID_MCSRBITS);
3180 printf("serv_write = [chip=%ld] [us=%d]\n",
3181 (long)EN_READ(sc, MID_SERV_WRITE),
3182 MID_SL_A2REG(sc->hwslistp));
3183 printf("dma addr = 0x%lx\n", (u_long)EN_READ(sc, MID_DMA_ADDR));
3184 printf("DRQ: chip[rd=0x%lx,wr=0x%lx], sc[chip=0x%x,us=0x%x]\n",
3185 (u_long)MID_DRQ_REG2A(EN_READ(sc, MID_DMA_RDRX)),
3186 (u_long)MID_DRQ_REG2A(EN_READ(sc, MID_DMA_WRRX)),
3187 sc->drq_chip, sc->drq_us);
3188 printf("DTQ: chip[rd=0x%lx,wr=0x%lx], sc[chip=0x%x,us=0x%x]\n",
3189 (u_long)MID_DTQ_REG2A(EN_READ(sc, MID_DMA_RDTX)),
3190 (u_long)MID_DTQ_REG2A(EN_READ(sc, MID_DMA_WRTX)),
3191 sc->dtq_chip, sc->dtq_us);
3193 printf(" unusal txspeeds: ");
3194 for (cnt = 0 ; cnt < MID_N_VC ; cnt++)
3195 if (sc->txspeed[cnt])
3196 printf(" vci%d=0x%x", cnt, sc->txspeed[cnt]);
3199 printf(" rxvc slot mappings: ");
3200 for (cnt = 0 ; cnt < MID_N_VC ; cnt++)
3201 if (sc->rxvc2slot[cnt] != RX_NONE)
3202 printf(" %d->%d", cnt, sc->rxvc2slot[cnt]);
3207 if (level & END_TX) {
3209 for (slot = 0 ; slot < EN_NTX; slot++) {
3210 printf("tx%d: start/stop/cur=0x%x/0x%x/0x%x [%d] ", slot,
3211 sc->txslot[slot].start, sc->txslot[slot].stop, sc->txslot[slot].cur,
3212 (sc->txslot[slot].cur - sc->txslot[slot].start)/4);
3213 printf("mbsize=%d, bfree=%d\n", sc->txslot[slot].mbsize,
3214 sc->txslot[slot].bfree);
3215 printf("txhw: base_address=0x%lx, size=%ld, read=%ld, descstart=%ld\n",
3216 (u_long)MIDX_BASE(EN_READ(sc, MIDX_PLACE(slot))),
3217 (u_long)MIDX_SZ(EN_READ(sc, MIDX_PLACE(slot))),
3218 (long)EN_READ(sc, MIDX_READPTR(slot)),
3219 (long)EN_READ(sc, MIDX_DESCSTART(slot)));
3223 if (level & END_RX) {
3224 printf(" recv slots:\n");
3225 for (slot = 0 ; slot < sc->en_nrx; slot++) {
3226 printf("rx%d: vci=%d: start/stop/cur=0x%x/0x%x/0x%x ", slot,
3227 sc->rxslot[slot].atm_vci, sc->rxslot[slot].start,
3228 sc->rxslot[slot].stop, sc->rxslot[slot].cur);
3229 printf("mode=0x%x, atm_flags=0x%x, oth_flags=0x%x\n",
3230 sc->rxslot[slot].mode, sc->rxslot[slot].atm_flags,
3231 sc->rxslot[slot].oth_flags);
3232 printf("RXHW: mode=0x%lx, DST_RP=0x%lx, WP_ST_CNT=0x%lx\n",
3233 (u_long)EN_READ(sc, MID_VC(sc->rxslot[slot].atm_vci)),
3234 (u_long)EN_READ(sc, MID_DST_RP(sc->rxslot[slot].atm_vci)),
3235 (u_long)EN_READ(sc, MID_WP_ST_CNT(sc->rxslot[slot].atm_vci)));
3239 if (level & END_DTQ) {
3240 printf(" dtq [need_dtqs=%d,dtq_free=%d]:\n",
3241 sc->need_dtqs, sc->dtq_free);
3243 while (ptr != sc->dtq_us) {
3244 reg = EN_READ(sc, ptr);
3245 printf("\t0x%x=[cnt=%d, chan=%d, end=%d, type=%d @ 0x%lx]\n",
3246 sc->dtq[MID_DTQ_A2REG(ptr)], MID_DMA_CNT(reg), MID_DMA_TXCHAN(reg),
3247 (reg & MID_DMA_END) != 0, MID_DMA_TYPE(reg),
3248 (u_long)EN_READ(sc, ptr+4));
3249 EN_WRAPADD(MID_DTQOFF, MID_DTQEND, ptr, 8);
3253 if (level & END_DRQ) {
3254 printf(" drq [need_drqs=%d,drq_free=%d]:\n",
3255 sc->need_drqs, sc->drq_free);
3257 while (ptr != sc->drq_us) {
3258 reg = EN_READ(sc, ptr);
3259 printf("\t0x%x=[cnt=%d, chan=%d, end=%d, type=%d @ 0x%lx]\n",
3260 sc->drq[MID_DRQ_A2REG(ptr)], MID_DMA_CNT(reg), MID_DMA_RXVCI(reg),
3261 (reg & MID_DMA_END) != 0, MID_DMA_TYPE(reg),
3262 (u_long)EN_READ(sc, ptr+4));
3263 EN_WRAPADD(MID_DRQOFF, MID_DRQEND, ptr, 8);
3267 if (level & END_SWSL) {
3268 printf(" swslist [size=%d]: ", sc->swsl_size);
3269 for (cnt = sc->swsl_head ; cnt != sc->swsl_tail ;
3270 cnt = (cnt + 1) % MID_SL_N)
3271 printf("0x%x ", sc->swslist[cnt]);
3279 * en_dumpmem: dump the memory
3282 /* Do not staticize - meant for calling from DDB! */
3283 int en_dumpmem(unit, addr, len)
3285 int unit, addr, len;
3288 struct en_softc *sc;
3291 if (unit < 0 || unit > en_cd.cd_ndevs ||
3292 (sc = (struct en_softc *) en_cd.cd_devs[unit]) == NULL) {
3293 printf("invalid unit number: %d\n", unit);
3297 if (addr < MID_RAMOFF || addr + len*4 > MID_MAXOFF || len <= 0) {
3298 printf("invalid addr/len number: %d, %d\n", addr, len);
3301 printf("dumping %d words starting at offset 0x%x\n", len, addr);
3303 reg = EN_READ(sc, addr);
3304 printf("mem[0x%x] = 0x%x\n", addr, reg);