1 /******************************************************************************
3 Copyright (c) 2001-2017, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
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16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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30 POSSIBILITY OF SUCH DAMAGE.
32 ******************************************************************************/
35 #include "ixgbe_x540.h"
36 #include "ixgbe_type.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
41 #define IXGBE_X540_MAX_TX_QUEUES 128
42 #define IXGBE_X540_MAX_RX_QUEUES 128
43 #define IXGBE_X540_RAR_ENTRIES 128
44 #define IXGBE_X540_MC_TBL_SIZE 128
45 #define IXGBE_X540_VFT_TBL_SIZE 128
46 #define IXGBE_X540_RX_PB_SIZE 384
48 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
49 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
50 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
53 * ixgbe_init_ops_X540 - Inits func ptrs and MAC type
54 * @hw: pointer to hardware structure
56 * Initialize the function pointers and assign the MAC type for X540.
57 * Does not touch the hardware.
59 s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw)
61 struct ixgbe_mac_info *mac = &hw->mac;
62 struct ixgbe_phy_info *phy = &hw->phy;
63 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
66 DEBUGFUNC("ixgbe_init_ops_X540");
68 ret_val = ixgbe_init_phy_ops_generic(hw);
69 ret_val = ixgbe_init_ops_generic(hw);
73 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
74 eeprom->ops.read = ixgbe_read_eerd_X540;
75 eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_X540;
76 eeprom->ops.write = ixgbe_write_eewr_X540;
77 eeprom->ops.write_buffer = ixgbe_write_eewr_buffer_X540;
78 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X540;
79 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X540;
80 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X540;
83 phy->ops.init = ixgbe_init_phy_ops_generic;
84 phy->ops.reset = NULL;
85 phy->ops.set_phy_power = ixgbe_set_copper_phy_power;
88 mac->ops.reset_hw = ixgbe_reset_hw_X540;
89 mac->ops.enable_relaxed_ordering = ixgbe_enable_relaxed_ordering_gen2;
90 mac->ops.get_media_type = ixgbe_get_media_type_X540;
91 mac->ops.get_supported_physical_layer =
92 ixgbe_get_supported_physical_layer_X540;
93 mac->ops.read_analog_reg8 = NULL;
94 mac->ops.write_analog_reg8 = NULL;
95 mac->ops.start_hw = ixgbe_start_hw_X540;
96 mac->ops.get_san_mac_addr = ixgbe_get_san_mac_addr_generic;
97 mac->ops.set_san_mac_addr = ixgbe_set_san_mac_addr_generic;
98 mac->ops.get_device_caps = ixgbe_get_device_caps_generic;
99 mac->ops.get_wwn_prefix = ixgbe_get_wwn_prefix_generic;
100 mac->ops.get_fcoe_boot_status = ixgbe_get_fcoe_boot_status_generic;
101 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X540;
102 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X540;
103 mac->ops.init_swfw_sync = ixgbe_init_swfw_sync_X540;
104 mac->ops.disable_sec_rx_path = ixgbe_disable_sec_rx_path_generic;
105 mac->ops.enable_sec_rx_path = ixgbe_enable_sec_rx_path_generic;
107 /* RAR, Multicast, VLAN */
108 mac->ops.set_vmdq = ixgbe_set_vmdq_generic;
109 mac->ops.set_vmdq_san_mac = ixgbe_set_vmdq_san_mac_generic;
110 mac->ops.clear_vmdq = ixgbe_clear_vmdq_generic;
111 mac->ops.insert_mac_addr = ixgbe_insert_mac_addr_generic;
112 mac->rar_highwater = 1;
113 mac->ops.set_vfta = ixgbe_set_vfta_generic;
114 mac->ops.set_vlvf = ixgbe_set_vlvf_generic;
115 mac->ops.clear_vfta = ixgbe_clear_vfta_generic;
116 mac->ops.init_uta_tables = ixgbe_init_uta_tables_generic;
117 mac->ops.set_mac_anti_spoofing = ixgbe_set_mac_anti_spoofing;
118 mac->ops.set_vlan_anti_spoofing = ixgbe_set_vlan_anti_spoofing;
121 mac->ops.get_link_capabilities =
122 ixgbe_get_copper_link_capabilities_generic;
123 mac->ops.setup_link = ixgbe_setup_mac_link_X540;
124 mac->ops.setup_rxpba = ixgbe_set_rxpba_generic;
125 mac->ops.check_link = ixgbe_check_mac_link_generic;
126 mac->ops.bypass_rw = ixgbe_bypass_rw_generic;
127 mac->ops.bypass_valid_rd = ixgbe_bypass_valid_rd_generic;
128 mac->ops.bypass_set = ixgbe_bypass_set_generic;
129 mac->ops.bypass_rd_eep = ixgbe_bypass_rd_eep_generic;
132 mac->mcft_size = IXGBE_X540_MC_TBL_SIZE;
133 mac->vft_size = IXGBE_X540_VFT_TBL_SIZE;
134 mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES;
135 mac->rx_pb_size = IXGBE_X540_RX_PB_SIZE;
136 mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES;
137 mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES;
138 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
142 * ARC supported; valid only if manageability features are
145 mac->arc_subsystem_valid = !!(IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw))
146 & IXGBE_FWSM_MODE_MASK);
148 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
151 mac->ops.blink_led_start = ixgbe_blink_led_start_X540;
152 mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540;
154 /* Manageability interface */
155 mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_generic;
157 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
163 * ixgbe_get_link_capabilities_X540 - Determines link capabilities
164 * @hw: pointer to hardware structure
165 * @speed: pointer to link speed
166 * @autoneg: TRUE when autoneg or autotry is enabled
168 * Determines the link capabilities by reading the AUTOC register.
170 s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw,
171 ixgbe_link_speed *speed,
174 ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg);
176 return IXGBE_SUCCESS;
180 * ixgbe_get_media_type_X540 - Get media type
181 * @hw: pointer to hardware structure
183 * Returns the media type (fiber, copper, backplane)
185 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
187 UNREFERENCED_1PARAMETER(hw);
188 return ixgbe_media_type_copper;
192 * ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities
193 * @hw: pointer to hardware structure
194 * @speed: new link speed
195 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
197 s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,
198 ixgbe_link_speed speed,
199 bool autoneg_wait_to_complete)
201 DEBUGFUNC("ixgbe_setup_mac_link_X540");
202 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
206 * ixgbe_reset_hw_X540 - Perform hardware reset
207 * @hw: pointer to hardware structure
209 * Resets the hardware by resetting the transmit and receive units, masks
210 * and clears all interrupts, and perform a reset.
212 s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
216 u32 swfw_mask = hw->phy.phy_semaphore_mask;
218 DEBUGFUNC("ixgbe_reset_hw_X540");
220 /* Call adapter stop to disable tx/rx and clear interrupts */
221 status = hw->mac.ops.stop_adapter(hw);
222 if (status != IXGBE_SUCCESS)
225 /* flush pending Tx transactions */
226 ixgbe_clear_tx_pending(hw);
229 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
230 if (status != IXGBE_SUCCESS) {
231 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
232 "semaphore failed with %d", status);
233 return IXGBE_ERR_SWFW_SYNC;
235 ctrl = IXGBE_CTRL_RST;
236 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
237 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
238 IXGBE_WRITE_FLUSH(hw);
239 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
241 /* Poll for reset bit to self-clear indicating reset is complete */
242 for (i = 0; i < 10; i++) {
244 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
245 if (!(ctrl & IXGBE_CTRL_RST_MASK))
249 if (ctrl & IXGBE_CTRL_RST_MASK) {
250 status = IXGBE_ERR_RESET_FAILED;
251 ERROR_REPORT1(IXGBE_ERROR_POLLING,
252 "Reset polling failed to complete.\n");
257 * Double resets are required for recovery from certain error
258 * conditions. Between resets, it is necessary to stall to allow time
259 * for any pending HW events to complete.
261 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
262 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
266 /* Set the Rx packet buffer size. */
267 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
269 /* Store the permanent mac address */
270 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
273 * Store MAC address from RAR0, clear receive address registers, and
274 * clear the multicast table. Also reset num_rar_entries to 128,
275 * since we modify this value when programming the SAN MAC address.
277 hw->mac.num_rar_entries = 128;
278 hw->mac.ops.init_rx_addrs(hw);
280 /* Store the permanent SAN mac address */
281 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
283 /* Add the SAN MAC address to the RAR only if it's a valid address */
284 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
285 /* Save the SAN MAC RAR index */
286 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
288 hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index,
289 hw->mac.san_addr, 0, IXGBE_RAH_AV);
291 /* clear VMDq pool/queue selection for this RAR */
292 hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index,
293 IXGBE_CLEAR_VMDQ_ALL);
295 /* Reserve the last RAR for the SAN MAC address */
296 hw->mac.num_rar_entries--;
299 /* Store the alternative WWNN/WWPN prefix */
300 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
301 &hw->mac.wwpn_prefix);
308 * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx
309 * @hw: pointer to hardware structure
311 * Starts the hardware using the generic start_hw function
312 * and the generation start_hw function.
313 * Then performs revision-specific operations, if any.
315 s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)
317 s32 ret_val = IXGBE_SUCCESS;
319 DEBUGFUNC("ixgbe_start_hw_X540");
321 ret_val = ixgbe_start_hw_generic(hw);
322 if (ret_val != IXGBE_SUCCESS)
325 ret_val = ixgbe_start_hw_gen2(hw);
332 * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type
333 * @hw: pointer to hardware structure
335 * Determines physical layer capabilities of the current configuration.
337 u64 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw)
339 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
342 DEBUGFUNC("ixgbe_get_supported_physical_layer_X540");
344 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
345 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
346 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
347 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
348 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
349 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
350 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
351 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
353 return physical_layer;
357 * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
358 * @hw: pointer to hardware structure
360 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
361 * ixgbe_hw struct in order to set up EEPROM access.
363 s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
365 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
369 DEBUGFUNC("ixgbe_init_eeprom_params_X540");
371 if (eeprom->type == ixgbe_eeprom_uninitialized) {
372 eeprom->semaphore_delay = 10;
373 eeprom->type = ixgbe_flash;
375 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
376 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
377 IXGBE_EEC_SIZE_SHIFT);
378 eeprom->word_size = 1 << (eeprom_size +
379 IXGBE_EEPROM_WORD_SIZE_SHIFT);
381 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
382 eeprom->type, eeprom->word_size);
385 return IXGBE_SUCCESS;
389 * ixgbe_read_eerd_X540- Read EEPROM word using EERD
390 * @hw: pointer to hardware structure
391 * @offset: offset of word in the EEPROM to read
392 * @data: word read from the EEPROM
394 * Reads a 16 bit word from the EEPROM using the EERD register.
396 s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
398 s32 status = IXGBE_SUCCESS;
400 DEBUGFUNC("ixgbe_read_eerd_X540");
401 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
403 status = ixgbe_read_eerd_generic(hw, offset, data);
404 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
406 status = IXGBE_ERR_SWFW_SYNC;
413 * ixgbe_read_eerd_buffer_X540- Read EEPROM word(s) using EERD
414 * @hw: pointer to hardware structure
415 * @offset: offset of word in the EEPROM to read
416 * @words: number of words
417 * @data: word(s) read from the EEPROM
419 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
421 s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
422 u16 offset, u16 words, u16 *data)
424 s32 status = IXGBE_SUCCESS;
426 DEBUGFUNC("ixgbe_read_eerd_buffer_X540");
427 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
429 status = ixgbe_read_eerd_buffer_generic(hw, offset,
431 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
433 status = IXGBE_ERR_SWFW_SYNC;
440 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
441 * @hw: pointer to hardware structure
442 * @offset: offset of word in the EEPROM to write
443 * @data: word write to the EEPROM
445 * Write a 16 bit word to the EEPROM using the EEWR register.
447 s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
449 s32 status = IXGBE_SUCCESS;
451 DEBUGFUNC("ixgbe_write_eewr_X540");
452 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
454 status = ixgbe_write_eewr_generic(hw, offset, data);
455 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
457 status = IXGBE_ERR_SWFW_SYNC;
464 * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
465 * @hw: pointer to hardware structure
466 * @offset: offset of word in the EEPROM to write
467 * @words: number of words
468 * @data: word(s) write to the EEPROM
470 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
472 s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
473 u16 offset, u16 words, u16 *data)
475 s32 status = IXGBE_SUCCESS;
477 DEBUGFUNC("ixgbe_write_eewr_buffer_X540");
478 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
480 status = ixgbe_write_eewr_buffer_generic(hw, offset,
482 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
484 status = IXGBE_ERR_SWFW_SYNC;
491 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
493 * This function does not use synchronization for EERD and EEWR. It can
494 * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.
496 * @hw: pointer to hardware structure
498 * Returns a negative error code on error, or the 16-bit checksum
500 s32 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
507 u16 ptr_start = IXGBE_PCIE_ANALOG_PTR;
509 /* Do not use hw->eeprom.ops.read because we do not want to take
510 * the synchronization semaphores here. Instead use
511 * ixgbe_read_eerd_generic
514 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X540");
516 /* Include 0x0 up to IXGBE_EEPROM_CHECKSUM; do not include the
519 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
520 if (ixgbe_read_eerd_generic(hw, i, &word)) {
521 DEBUGOUT("EEPROM read failed\n");
522 return IXGBE_ERR_EEPROM;
527 /* Include all data from pointers 0x3, 0x6-0xE. This excludes the
528 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
530 for (i = ptr_start; i < IXGBE_FW_PTR; i++) {
531 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
534 if (ixgbe_read_eerd_generic(hw, i, &pointer)) {
535 DEBUGOUT("EEPROM read failed\n");
536 return IXGBE_ERR_EEPROM;
539 /* Skip pointer section if the pointer is invalid. */
540 if (pointer == 0xFFFF || pointer == 0 ||
541 pointer >= hw->eeprom.word_size)
544 if (ixgbe_read_eerd_generic(hw, pointer, &length)) {
545 DEBUGOUT("EEPROM read failed\n");
546 return IXGBE_ERR_EEPROM;
549 /* Skip pointer section if length is invalid. */
550 if (length == 0xFFFF || length == 0 ||
551 (pointer + length) >= hw->eeprom.word_size)
554 for (j = pointer + 1; j <= pointer + length; j++) {
555 if (ixgbe_read_eerd_generic(hw, j, &word)) {
556 DEBUGOUT("EEPROM read failed\n");
557 return IXGBE_ERR_EEPROM;
563 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
565 return (s32)checksum;
569 * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum
570 * @hw: pointer to hardware structure
571 * @checksum_val: calculated checksum
573 * Performs checksum calculation and validates the EEPROM checksum. If the
574 * caller does not need checksum_val, the value can be NULL.
576 s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
581 u16 read_checksum = 0;
583 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X540");
585 /* Read the first word from the EEPROM. If this times out or fails, do
586 * not continue or we could be in for a very long wait while every
589 status = hw->eeprom.ops.read(hw, 0, &checksum);
591 DEBUGOUT("EEPROM read failed\n");
595 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
596 return IXGBE_ERR_SWFW_SYNC;
598 status = hw->eeprom.ops.calc_checksum(hw);
602 checksum = (u16)(status & 0xffff);
604 /* Do not use hw->eeprom.ops.read because we do not want to take
605 * the synchronization semaphores twice here.
607 status = ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
612 /* Verify read checksum from EEPROM is the same as
613 * calculated checksum
615 if (read_checksum != checksum) {
616 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
617 "Invalid EEPROM checksum");
618 status = IXGBE_ERR_EEPROM_CHECKSUM;
621 /* If the user cares, return the calculated checksum */
623 *checksum_val = checksum;
626 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
632 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
633 * @hw: pointer to hardware structure
635 * After writing EEPROM to shadow RAM using EEWR register, software calculates
636 * checksum and updates the EEPROM and instructs the hardware to update
639 s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
644 DEBUGFUNC("ixgbe_update_eeprom_checksum_X540");
646 /* Read the first word from the EEPROM. If this times out or fails, do
647 * not continue or we could be in for a very long wait while every
650 status = hw->eeprom.ops.read(hw, 0, &checksum);
652 DEBUGOUT("EEPROM read failed\n");
656 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
657 return IXGBE_ERR_SWFW_SYNC;
659 status = hw->eeprom.ops.calc_checksum(hw);
663 checksum = (u16)(status & 0xffff);
665 /* Do not use hw->eeprom.ops.write because we do not want to
666 * take the synchronization semaphores twice here.
668 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, checksum);
672 status = ixgbe_update_flash_X540(hw);
675 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
681 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
682 * @hw: pointer to hardware structure
684 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
685 * EEPROM from shadow RAM to the flash device.
687 s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
692 DEBUGFUNC("ixgbe_update_flash_X540");
694 status = ixgbe_poll_flash_update_done_X540(hw);
695 if (status == IXGBE_ERR_EEPROM) {
696 DEBUGOUT("Flash update time out\n");
700 flup = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)) | IXGBE_EEC_FLUP;
701 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), flup);
703 status = ixgbe_poll_flash_update_done_X540(hw);
704 if (status == IXGBE_SUCCESS)
705 DEBUGOUT("Flash update complete\n");
707 DEBUGOUT("Flash update time out\n");
709 if (hw->mac.type == ixgbe_mac_X540 && hw->revision_id == 0) {
710 flup = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
712 if (flup & IXGBE_EEC_SEC1VAL) {
713 flup |= IXGBE_EEC_FLUP;
714 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), flup);
717 status = ixgbe_poll_flash_update_done_X540(hw);
718 if (status == IXGBE_SUCCESS)
719 DEBUGOUT("Flash update complete\n");
721 DEBUGOUT("Flash update time out\n");
728 * ixgbe_poll_flash_update_done_X540 - Poll flash update status
729 * @hw: pointer to hardware structure
731 * Polls the FLUDONE (bit 26) of the EEC Register to determine when the
732 * flash update is done.
734 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
738 s32 status = IXGBE_ERR_EEPROM;
740 DEBUGFUNC("ixgbe_poll_flash_update_done_X540");
742 for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
743 reg = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
744 if (reg & IXGBE_EEC_FLUDONE) {
745 status = IXGBE_SUCCESS;
751 if (i == IXGBE_FLUDONE_ATTEMPTS)
752 ERROR_REPORT1(IXGBE_ERROR_POLLING,
753 "Flash update status polling timed out");
759 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
760 * @hw: pointer to hardware structure
761 * @mask: Mask to specify which semaphore to acquire
763 * Acquires the SWFW semaphore thought the SW_FW_SYNC register for
764 * the specified function (CSR, PHY0, PHY1, NVM, Flash)
766 s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
768 u32 swmask = mask & IXGBE_GSSR_NVM_PHY_MASK;
769 u32 fwmask = swmask << 5;
770 u32 swi2c_mask = mask & IXGBE_GSSR_I2C_MASK;
776 DEBUGFUNC("ixgbe_acquire_swfw_sync_X540");
778 if (swmask & IXGBE_GSSR_EEP_SM)
779 hwmask |= IXGBE_GSSR_FLASH_SM;
781 /* SW only mask doesn't have FW bit pair */
782 if (mask & IXGBE_GSSR_SW_MNG_SM)
783 swmask |= IXGBE_GSSR_SW_MNG_SM;
785 swmask |= swi2c_mask;
786 fwmask |= swi2c_mask << 2;
787 if (hw->mac.type == ixgbe_mac_X550)
790 for (i = 0; i < timeout; i++) {
791 /* SW NVM semaphore bit is used for access to all
792 * SW_FW_SYNC bits (not just NVM)
794 if (ixgbe_get_swfw_sync_semaphore(hw)) {
795 DEBUGOUT("Failed to get NVM access and register semaphore, returning IXGBE_ERR_SWFW_SYNC\n");
796 return IXGBE_ERR_SWFW_SYNC;
799 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
800 if (!(swfw_sync & (fwmask | swmask | hwmask))) {
802 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw),
804 ixgbe_release_swfw_sync_semaphore(hw);
805 return IXGBE_SUCCESS;
807 /* Firmware currently using resource (fwmask), hardware
808 * currently using resource (hwmask), or other software
809 * thread currently using resource (swmask)
811 ixgbe_release_swfw_sync_semaphore(hw);
815 /* If the resource is not released by the FW/HW the SW can assume that
816 * the FW/HW malfunctions. In that case the SW should set the SW bit(s)
817 * of the requested resource(s) while ignoring the corresponding FW/HW
818 * bits in the SW_FW_SYNC register.
820 if (ixgbe_get_swfw_sync_semaphore(hw)) {
821 DEBUGOUT("Failed to get NVM sempahore and register semaphore while forcefully ignoring FW sempahore bit(s) and setting SW semaphore bit(s), returning IXGBE_ERR_SWFW_SYNC\n");
822 return IXGBE_ERR_SWFW_SYNC;
824 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
825 if (swfw_sync & (fwmask | hwmask)) {
827 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync);
828 ixgbe_release_swfw_sync_semaphore(hw);
830 return IXGBE_SUCCESS;
832 /* If the resource is not released by other SW the SW can assume that
833 * the other SW malfunctions. In that case the SW should clear all SW
834 * flags that it does not own and then repeat the whole process once
837 if (swfw_sync & swmask) {
838 u32 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM |
839 IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM |
840 IXGBE_GSSR_SW_MNG_SM;
843 rmask |= IXGBE_GSSR_I2C_MASK;
844 ixgbe_release_swfw_sync_X540(hw, rmask);
845 ixgbe_release_swfw_sync_semaphore(hw);
846 DEBUGOUT("Resource not released by other SW, returning IXGBE_ERR_SWFW_SYNC\n");
847 return IXGBE_ERR_SWFW_SYNC;
849 ixgbe_release_swfw_sync_semaphore(hw);
850 DEBUGOUT("Returning error IXGBE_ERR_SWFW_SYNC\n");
852 return IXGBE_ERR_SWFW_SYNC;
856 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
857 * @hw: pointer to hardware structure
858 * @mask: Mask to specify which semaphore to release
860 * Releases the SWFW semaphore through the SW_FW_SYNC register
861 * for the specified function (CSR, PHY0, PHY1, EVM, Flash)
863 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
865 u32 swmask = mask & (IXGBE_GSSR_NVM_PHY_MASK | IXGBE_GSSR_SW_MNG_SM);
868 DEBUGFUNC("ixgbe_release_swfw_sync_X540");
870 if (mask & IXGBE_GSSR_I2C_MASK)
871 swmask |= mask & IXGBE_GSSR_I2C_MASK;
872 ixgbe_get_swfw_sync_semaphore(hw);
874 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
875 swfw_sync &= ~swmask;
876 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync);
878 ixgbe_release_swfw_sync_semaphore(hw);
883 * ixgbe_get_swfw_sync_semaphore - Get hardware semaphore
884 * @hw: pointer to hardware structure
886 * Sets the hardware semaphores so SW/FW can gain control of shared resources
888 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
890 s32 status = IXGBE_ERR_EEPROM;
895 DEBUGFUNC("ixgbe_get_swfw_sync_semaphore");
897 /* Get SMBI software semaphore between device drivers first */
898 for (i = 0; i < timeout; i++) {
900 * If the SMBI bit is 0 when we read it, then the bit will be
901 * set and we have the semaphore
903 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
904 if (!(swsm & IXGBE_SWSM_SMBI)) {
905 status = IXGBE_SUCCESS;
911 /* Now get the semaphore between SW/FW through the REGSMP bit */
912 if (status == IXGBE_SUCCESS) {
913 for (i = 0; i < timeout; i++) {
914 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
915 if (!(swsm & IXGBE_SWFW_REGSMP))
922 * Release semaphores and return error if SW NVM semaphore
923 * was not granted because we don't have access to the EEPROM
926 ERROR_REPORT1(IXGBE_ERROR_POLLING,
927 "REGSMP Software NVM semaphore not granted.\n");
928 ixgbe_release_swfw_sync_semaphore(hw);
929 status = IXGBE_ERR_EEPROM;
932 ERROR_REPORT1(IXGBE_ERROR_POLLING,
933 "Software semaphore SMBI between device drivers "
941 * ixgbe_release_swfw_sync_semaphore - Release hardware semaphore
942 * @hw: pointer to hardware structure
944 * This function clears hardware semaphore bits.
946 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
950 DEBUGFUNC("ixgbe_release_swfw_sync_semaphore");
952 /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
954 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
955 swsm &= ~IXGBE_SWFW_REGSMP;
956 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swsm);
958 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
959 swsm &= ~IXGBE_SWSM_SMBI;
960 IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm);
962 IXGBE_WRITE_FLUSH(hw);
966 * ixgbe_init_swfw_sync_X540 - Release hardware semaphore
967 * @hw: pointer to hardware structure
969 * This function reset hardware semaphore bits for a semaphore that may
970 * have be left locked due to a catastrophic failure.
972 void ixgbe_init_swfw_sync_X540(struct ixgbe_hw *hw)
976 /* First try to grab the semaphore but we don't need to bother
977 * looking to see whether we got the lock or not since we do
978 * the same thing regardless of whether we got the lock or not.
979 * We got the lock - we release it.
980 * We timeout trying to get the lock - we force its release.
982 ixgbe_get_swfw_sync_semaphore(hw);
983 ixgbe_release_swfw_sync_semaphore(hw);
985 /* Acquire and release all software resources. */
986 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM |
987 IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM |
988 IXGBE_GSSR_SW_MNG_SM;
990 rmask |= IXGBE_GSSR_I2C_MASK;
991 ixgbe_acquire_swfw_sync_X540(hw, rmask);
992 ixgbe_release_swfw_sync_X540(hw, rmask);
996 * ixgbe_blink_led_start_X540 - Blink LED based on index.
997 * @hw: pointer to hardware structure
998 * @index: led number to blink
1000 * Devices that implement the version 2 interface:
1003 s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
1007 ixgbe_link_speed speed;
1010 DEBUGFUNC("ixgbe_blink_led_start_X540");
1013 return IXGBE_ERR_PARAM;
1016 * Link should be up in order for the blink bit in the LED control
1017 * register to work. Force link and speed in the MAC if link is down.
1018 * This will be reversed when we stop the blinking.
1020 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
1021 if (link_up == FALSE) {
1022 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
1023 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS;
1024 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
1026 /* Set the LED to LINK_UP + BLINK. */
1027 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1028 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
1029 ledctl_reg |= IXGBE_LED_BLINK(index);
1030 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
1031 IXGBE_WRITE_FLUSH(hw);
1033 return IXGBE_SUCCESS;
1037 * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index.
1038 * @hw: pointer to hardware structure
1039 * @index: led number to stop blinking
1041 * Devices that implement the version 2 interface:
1044 s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
1050 return IXGBE_ERR_PARAM;
1052 DEBUGFUNC("ixgbe_blink_led_stop_X540");
1054 /* Restore the LED to its default value. */
1055 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1056 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
1057 ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
1058 ledctl_reg &= ~IXGBE_LED_BLINK(index);
1059 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
1061 /* Unforce link and speed in the MAC. */
1062 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
1063 macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS);
1064 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
1065 IXGBE_WRITE_FLUSH(hw);
1067 return IXGBE_SUCCESS;