2 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
3 * Copyright (c) 1992 Terrence R. Lambert.
4 * Copyright (c) 2003 Peter Wemm.
5 * Copyright (c) 2008 The DragonFly Project.
8 * This code is derived from software contributed to Berkeley by
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the University of
22 * California, Berkeley and its contributors.
23 * 4. Neither the name of the University nor the names of its contributors
24 * may be used to endorse or promote products derived from this software
25 * without specific prior written permission.
27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
40 * $FreeBSD: src/sys/i386/i386/machdep.c,v 1.385.2.30 2003/05/31 08:48:05 alc Exp $
43 //#include "use_npx.h"
45 #include "opt_compat.h"
48 #include "opt_directio.h"
51 #include "opt_msgbuf.h"
54 #include <sys/param.h>
55 #include <sys/systm.h>
56 #include <sys/sysproto.h>
57 #include <sys/signalvar.h>
58 #include <sys/kernel.h>
59 #include <sys/linker.h>
60 #include <sys/malloc.h>
64 #include <sys/reboot.h>
66 #include <sys/msgbuf.h>
67 #include <sys/sysent.h>
68 #include <sys/sysctl.h>
69 #include <sys/vmmeter.h>
71 #include <sys/usched.h>
74 #include <sys/ctype.h>
75 #include <sys/serialize.h>
76 #include <sys/systimer.h>
79 #include <vm/vm_param.h>
81 #include <vm/vm_kern.h>
82 #include <vm/vm_object.h>
83 #include <vm/vm_page.h>
84 #include <vm/vm_map.h>
85 #include <vm/vm_pager.h>
86 #include <vm/vm_extern.h>
88 #include <sys/thread2.h>
89 #include <sys/mplock2.h>
90 #include <sys/mutex2.h>
98 #include <machine/cpu.h>
99 #include <machine/clock.h>
100 #include <machine/specialreg.h>
102 #include <machine/bootinfo.h>
104 #include <machine/md_var.h>
105 #include <machine/metadata.h>
106 #include <machine/pc/bios.h>
107 #include <machine/pcb_ext.h> /* pcb.h included via sys/user.h */
108 #include <machine/globaldata.h> /* CPU_prvspace */
109 #include <machine/smp.h>
111 #include <machine/perfmon.h>
113 #include <machine/cputypes.h>
114 #include <machine/intr_machdep.h>
117 #include <bus/isa/isa_device.h>
119 #include <machine_base/isa/isa_intr.h>
120 #include <bus/isa/rtc.h>
121 #include <sys/random.h>
122 #include <sys/ptrace.h>
123 #include <machine/sigframe.h>
125 #include <sys/machintr.h>
126 #include <machine_base/icu/icu_abi.h>
127 #include <machine_base/icu/elcr_var.h>
128 #include <machine_base/apic/lapic.h>
129 #include <machine_base/apic/ioapic.h>
130 #include <machine_base/apic/ioapic_abi.h>
131 #include <machine/mptable.h>
133 #define PHYSMAP_ENTRIES 10
135 extern u_int64_t hammer_time(u_int64_t, u_int64_t);
137 extern void printcpuinfo(void); /* XXX header file */
138 extern void identify_cpu(void);
140 extern void finishidentcpu(void);
142 extern void panicifcpuunsupported(void);
144 static void cpu_startup(void *);
145 static void pic_finish(void *);
146 static void cpu_finish(void *);
148 #ifndef CPU_DISABLE_SSE
149 static void set_fpregs_xmm(struct save87 *, struct savexmm *);
150 static void fill_fpregs_xmm(struct savexmm *, struct save87 *);
151 #endif /* CPU_DISABLE_SSE */
153 extern void ffs_rawread_setup(void);
154 #endif /* DIRECTIO */
155 static void init_locks(void);
157 SYSINIT(cpu, SI_BOOT2_START_CPU, SI_ORDER_FIRST, cpu_startup, NULL)
158 SYSINIT(pic_finish, SI_BOOT2_FINISH_PIC, SI_ORDER_FIRST, pic_finish, NULL)
159 SYSINIT(cpu_finish, SI_BOOT2_FINISH_CPU, SI_ORDER_FIRST, cpu_finish, NULL)
162 extern vm_offset_t ksym_start, ksym_end;
165 struct privatespace CPU_prvspace[MAXCPU] __aligned(4096); /* XXX */
167 int _udatasel, _ucodesel, _ucode32sel;
169 int64_t tsc_offsets[MAXCPU];
171 static int cpu_mwait_halt; /* MWAIT hint (EAX) or CPU_MWAIT_HINT_ */
173 #if defined(SWTCH_OPTIM_STATS)
174 extern int swtch_optim_stats;
175 SYSCTL_INT(_debug, OID_AUTO, swtch_optim_stats,
176 CTLFLAG_RD, &swtch_optim_stats, 0, "");
177 SYSCTL_INT(_debug, OID_AUTO, tlb_flush_count,
178 CTLFLAG_RD, &tlb_flush_count, 0, "");
180 SYSCTL_INT(_hw, OID_AUTO, cpu_mwait_halt,
181 CTLFLAG_RD, &cpu_mwait_halt, 0, "");
183 #define CPU_MWAIT_C1 1
184 #define CPU_MWAIT_C2 2
185 #define CPU_MWAIT_C3 3
186 #define CPU_MWAIT_CX_MAX 8
188 #define CPU_MWAIT_HINT_AUTO -1 /* C1 and C2 */
189 #define CPU_MWAIT_HINT_AUTODEEP -2 /* C3+ */
191 SYSCTL_NODE(_machdep, 0, mwait, CTLFLAG_RW, 0, "MWAIT features");
192 SYSCTL_NODE(_machdep_mwait, 0, CX, CTLFLAG_RW, 0, "MWAIT Cx settings");
194 struct cpu_mwait_cx {
197 struct sysctl_ctx_list sysctl_ctx;
198 struct sysctl_oid *sysctl_tree;
200 static struct cpu_mwait_cx cpu_mwait_cx_info[CPU_MWAIT_CX_MAX];
201 static char cpu_mwait_cx_supported[256];
203 static int cpu_mwait_hints_cnt;
204 static int *cpu_mwait_hints;
206 static int cpu_mwait_deep_hints_cnt;
207 static int *cpu_mwait_deep_hints;
209 static u_int cpu_idle_repeat = 750;
210 static u_long cpu_idle_repeat_max;
212 #define CPU_MWAIT_C3_PREAMBLE_BM_ARB 0x1
213 #define CPU_MWAIT_C3_PREAMBLE_BM_STS 0x2
215 static int cpu_mwait_c3_preamble =
216 CPU_MWAIT_C3_PREAMBLE_BM_ARB |
217 CPU_MWAIT_C3_PREAMBLE_BM_STS;
219 SYSCTL_STRING(_machdep_mwait_CX, OID_AUTO, supported, CTLFLAG_RD,
220 cpu_mwait_cx_supported, 0, "MWAIT supported C states");
222 static struct lwkt_serialize cpu_mwait_cx_slize = LWKT_SERIALIZE_INITIALIZER;
223 static int cpu_mwait_cx_select_sysctl(SYSCTL_HANDLER_ARGS,
225 static int cpu_mwait_cx_idle_sysctl(SYSCTL_HANDLER_ARGS);
226 static int cpu_mwait_cx_spin_sysctl(SYSCTL_HANDLER_ARGS);
228 SYSCTL_PROC(_machdep_mwait_CX, OID_AUTO, idle, CTLTYPE_STRING|CTLFLAG_RW,
229 NULL, 0, cpu_mwait_cx_idle_sysctl, "A", "");
230 SYSCTL_PROC(_machdep_mwait_CX, OID_AUTO, spin, CTLTYPE_STRING|CTLFLAG_RW,
231 NULL, 0, cpu_mwait_cx_spin_sysctl, "A", "");
235 u_long ebda_addr = 0;
237 int imcr_present = 0;
239 int naps = 0; /* # of Applications processors */
242 struct mtx dt_lock; /* lock for GDT and LDT */
245 sysctl_hw_physmem(SYSCTL_HANDLER_ARGS)
247 u_long pmem = ctob(physmem);
249 int error = sysctl_handle_long(oidp, &pmem, 0, req);
253 SYSCTL_PROC(_hw, HW_PHYSMEM, physmem, CTLTYPE_ULONG|CTLFLAG_RD,
254 0, 0, sysctl_hw_physmem, "LU", "Total system memory in bytes (number of pages * page size)");
257 sysctl_hw_usermem(SYSCTL_HANDLER_ARGS)
259 int error = sysctl_handle_int(oidp, 0,
260 ctob(physmem - vmstats.v_wire_count), req);
264 SYSCTL_PROC(_hw, HW_USERMEM, usermem, CTLTYPE_INT|CTLFLAG_RD,
265 0, 0, sysctl_hw_usermem, "IU", "");
268 sysctl_hw_availpages(SYSCTL_HANDLER_ARGS)
270 int error = sysctl_handle_int(oidp, 0,
271 x86_64_btop(avail_end - avail_start), req);
275 SYSCTL_PROC(_hw, OID_AUTO, availpages, CTLTYPE_INT|CTLFLAG_RD,
276 0, 0, sysctl_hw_availpages, "I", "");
282 * The number of PHYSMAP entries must be one less than the number of
283 * PHYSSEG entries because the PHYSMAP entry that spans the largest
284 * physical address that is accessible by ISA DMA is split into two
287 #define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1))
289 vm_paddr_t phys_avail[PHYSMAP_SIZE + 2];
290 vm_paddr_t dump_avail[PHYSMAP_SIZE + 2];
292 /* must be 2 less so 0 0 can signal end of chunks */
293 #define PHYS_AVAIL_ARRAY_END (NELEM(phys_avail) - 2)
294 #define DUMP_AVAIL_ARRAY_END (NELEM(dump_avail) - 2)
296 static vm_offset_t buffer_sva, buffer_eva;
297 vm_offset_t clean_sva, clean_eva;
298 static vm_offset_t pager_sva, pager_eva;
299 static struct trapframe proc0_tf;
302 cpu_startup(void *dummy)
306 vm_offset_t firstaddr;
309 * Good {morning,afternoon,evening,night}.
311 kprintf("%s", version);
314 panicifcpuunsupported();
318 kprintf("real memory = %ju (%ju MB)\n",
320 (intmax_t)Realmem / 1024 / 1024);
322 * Display any holes after the first chunk of extended memory.
327 kprintf("Physical memory chunk(s):\n");
328 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) {
329 vm_paddr_t size1 = phys_avail[indx + 1] - phys_avail[indx];
331 kprintf("0x%08jx - 0x%08jx, %ju bytes (%ju pages)\n",
332 (intmax_t)phys_avail[indx],
333 (intmax_t)phys_avail[indx + 1] - 1,
335 (intmax_t)(size1 / PAGE_SIZE));
340 * Allocate space for system data structures.
341 * The first available kernel virtual address is in "v".
342 * As pages of kernel virtual memory are allocated, "v" is incremented.
343 * As pages of memory are allocated and cleared,
344 * "firstaddr" is incremented.
345 * An index into the kernel page table corresponding to the
346 * virtual memory address maintained in "v" is kept in "mapaddr".
350 * Make two passes. The first pass calculates how much memory is
351 * needed and allocates it. The second pass assigns virtual
352 * addresses to the various data structures.
356 v = (caddr_t)firstaddr;
358 #define valloc(name, type, num) \
359 (name) = (type *)v; v = (caddr_t)((name)+(num))
360 #define valloclim(name, type, num, lim) \
361 (name) = (type *)v; v = (caddr_t)((lim) = ((name)+(num)))
364 * The nominal buffer size (and minimum KVA allocation) is BKVASIZE.
365 * For the first 64MB of ram nominally allocate sufficient buffers to
366 * cover 1/4 of our ram. Beyond the first 64MB allocate additional
367 * buffers to cover 1/20 of our ram over 64MB. When auto-sizing
368 * the buffer cache we limit the eventual kva reservation to
371 * factor represents the 1/4 x ram conversion.
374 long factor = 4 * BKVASIZE / 1024;
375 long kbytes = physmem * (PAGE_SIZE / 1024);
379 nbuf += min((kbytes - 4096) / factor, 65536 / factor);
381 nbuf += (kbytes - 65536) * 2 / (factor * 5);
382 if (maxbcache && nbuf > maxbcache / BKVASIZE)
383 nbuf = maxbcache / BKVASIZE;
387 * Do not allow the buffer_map to be more then 1/2 the size of the
390 if (nbuf > (virtual_end - virtual_start +
391 virtual2_end - virtual2_start) / (BKVASIZE * 2)) {
392 nbuf = (virtual_end - virtual_start +
393 virtual2_end - virtual2_start) / (BKVASIZE * 2);
394 kprintf("Warning: nbufs capped at %ld due to kvm\n", nbuf);
398 * Do not allow the buffer_map to use more than 50% of available
399 * physical-equivalent memory. Since the VM pages which back
400 * individual buffers are typically wired, having too many bufs
401 * can prevent the system from paging properly.
403 if (nbuf > physmem * PAGE_SIZE / (BKVASIZE * 2)) {
404 nbuf = physmem * PAGE_SIZE / (BKVASIZE * 2);
405 kprintf("Warning: nbufs capped at %ld due to physmem\n", nbuf);
409 * Do not allow the sizeof(struct buf) * nbuf to exceed half of
410 * the valloc space which is just the virtual_end - virtual_start
411 * section. We use valloc() to allocate the buf header array.
413 if (nbuf > (virtual_end - virtual_start) / sizeof(struct buf) / 2) {
414 nbuf = (virtual_end - virtual_start) /
415 sizeof(struct buf) / 2;
416 kprintf("Warning: nbufs capped at %ld due to valloc "
417 "considerations", nbuf);
420 nswbuf = lmax(lmin(nbuf / 4, 256), 16);
422 if (nswbuf < NSWBUF_MIN)
429 valloc(swbuf, struct buf, nswbuf);
430 valloc(buf, struct buf, nbuf);
433 * End of first pass, size has been calculated so allocate memory
435 if (firstaddr == 0) {
436 size = (vm_size_t)(v - firstaddr);
437 firstaddr = kmem_alloc(&kernel_map, round_page(size));
439 panic("startup: no room for tables");
444 * End of second pass, addresses have been assigned
446 * nbuf is an int, make sure we don't overflow the field.
448 * On 64-bit systems we always reserve maximal allocations for
449 * buffer cache buffers and there are no fragmentation issues,
450 * so the KVA segment does not have to be excessively oversized.
452 if ((vm_size_t)(v - firstaddr) != size)
453 panic("startup: table size inconsistency");
455 kmem_suballoc(&kernel_map, &clean_map, &clean_sva, &clean_eva,
456 ((vm_offset_t)(nbuf + 16) * BKVASIZE) +
457 (nswbuf * MAXPHYS) + pager_map_size);
458 kmem_suballoc(&clean_map, &buffer_map, &buffer_sva, &buffer_eva,
459 ((vm_offset_t)(nbuf + 16) * BKVASIZE));
460 buffer_map.system_map = 1;
461 kmem_suballoc(&clean_map, &pager_map, &pager_sva, &pager_eva,
462 ((vm_offset_t)nswbuf * MAXPHYS) + pager_map_size);
463 pager_map.system_map = 1;
465 #if defined(USERCONFIG)
467 cninit(); /* the preferred console may have changed */
470 kprintf("avail memory = %ju (%ju MB)\n",
471 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages),
472 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages) /
476 struct cpu_idle_stat {
481 u_long mwait_cx[CPU_MWAIT_CX_MAX];
484 #define CPU_IDLE_STAT_HALT -1
485 #define CPU_IDLE_STAT_SPIN -2
487 static struct cpu_idle_stat cpu_idle_stats[MAXCPU];
490 sysctl_cpu_idle_cnt(SYSCTL_HANDLER_ARGS)
492 int idx = arg2, cpu, error;
495 if (idx == CPU_IDLE_STAT_HALT) {
496 for (cpu = 0; cpu < ncpus; ++cpu)
497 val += cpu_idle_stats[cpu].halt;
498 } else if (idx == CPU_IDLE_STAT_SPIN) {
499 for (cpu = 0; cpu < ncpus; ++cpu)
500 val += cpu_idle_stats[cpu].spin;
502 KASSERT(idx >= 0 && idx < CPU_MWAIT_CX_MAX,
503 ("invalid index %d", idx));
504 for (cpu = 0; cpu < ncpus; ++cpu)
505 val += cpu_idle_stats[cpu].mwait_cx[idx];
508 error = sysctl_handle_quad(oidp, &val, 0, req);
509 if (error || req->newptr == NULL)
512 if (idx == CPU_IDLE_STAT_HALT) {
513 for (cpu = 0; cpu < ncpus; ++cpu)
514 cpu_idle_stats[cpu].halt = 0;
515 cpu_idle_stats[0].halt = val;
516 } else if (idx == CPU_IDLE_STAT_SPIN) {
517 for (cpu = 0; cpu < ncpus; ++cpu)
518 cpu_idle_stats[cpu].spin = 0;
519 cpu_idle_stats[0].spin = val;
521 KASSERT(idx >= 0 && idx < CPU_MWAIT_CX_MAX,
522 ("invalid index %d", idx));
523 for (cpu = 0; cpu < ncpus; ++cpu)
524 cpu_idle_stats[cpu].mwait_cx[idx] = 0;
525 cpu_idle_stats[0].mwait_cx[idx] = val;
531 cpu_finish(void *dummy __unused)
537 cpu_idle_repeat_max = cpu_idle_repeat;
538 if ((cpu_feature2 & CPUID2_MON) &&
539 (cpu_mwait_feature & CPUID_MWAIT_EXT)) {
543 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
544 (CPUID_TO_FAMILY(cpu_id) > 0xf ||
545 (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
546 CPUID_TO_MODEL(cpu_id) >= 0xf))) {
547 atomic_clear_int(&cpu_mwait_c3_preamble,
548 CPU_MWAIT_C3_PREAMBLE_BM_ARB);
551 sbuf_new(&sb, cpu_mwait_cx_supported,
552 sizeof(cpu_mwait_cx_supported), SBUF_FIXEDLEN);
554 for (i = 0; i < CPU_MWAIT_CX_MAX; ++i) {
555 struct cpu_mwait_cx *cx = &cpu_mwait_cx_info[i];
558 ksnprintf(cx->name, sizeof(cx->name), "C%d", i);
560 sysctl_ctx_init(&cx->sysctl_ctx);
561 cx->sysctl_tree = SYSCTL_ADD_NODE(&cx->sysctl_ctx,
562 SYSCTL_STATIC_CHILDREN(_machdep_mwait), OID_AUTO,
563 cx->name, CTLFLAG_RW, NULL, "Cx control/info");
564 if (cx->sysctl_tree == NULL)
567 cx->subcnt = CPUID_MWAIT_CX_SUBCNT(cpu_mwait_extemu, i);
568 SYSCTL_ADD_INT(&cx->sysctl_ctx,
569 SYSCTL_CHILDREN(cx->sysctl_tree), OID_AUTO,
570 "subcnt", CTLFLAG_RD, &cx->subcnt, 0,
572 SYSCTL_ADD_PROC(&cx->sysctl_ctx,
573 SYSCTL_CHILDREN(cx->sysctl_tree), OID_AUTO,
574 "entered", (CTLTYPE_QUAD | CTLFLAG_RW), 0,
575 i, sysctl_cpu_idle_cnt, "Q", "# of times entered");
577 for (sub = 0; sub < cx->subcnt; ++sub)
578 sbuf_printf(&sb, "C%d/%d ", i, sub);
586 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_C3; ++i)
587 cpu_mwait_hints_cnt += cpu_mwait_cx_info[i].subcnt;
588 cpu_mwait_hints = kmalloc(sizeof(int) * cpu_mwait_hints_cnt,
592 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_C3; ++i) {
595 subcnt = cpu_mwait_cx_info[i].subcnt;
596 for (j = 0; j < subcnt; ++j) {
597 KASSERT(hint_idx < cpu_mwait_hints_cnt,
598 ("invalid mwait hint index %d", hint_idx));
599 cpu_mwait_hints[hint_idx] =
600 MWAIT_EAX_HINT(i, j);
604 KASSERT(hint_idx == cpu_mwait_hints_cnt,
605 ("mwait hint count %d != index %d",
606 cpu_mwait_hints_cnt, hint_idx));
609 kprintf("MWAIT hints:\n");
610 for (i = 0; i < cpu_mwait_hints_cnt; ++i) {
611 int hint = cpu_mwait_hints[i];
613 kprintf(" C%d/%d hint 0x%04x\n",
614 MWAIT_EAX_TO_CX(hint),
615 MWAIT_EAX_TO_CX_SUB(hint), hint);
622 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_CX_MAX; ++i)
623 cpu_mwait_deep_hints_cnt += cpu_mwait_cx_info[i].subcnt;
624 cpu_mwait_deep_hints =
625 kmalloc(sizeof(int) * cpu_mwait_deep_hints_cnt,
629 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_CX_MAX; ++i) {
632 subcnt = cpu_mwait_cx_info[i].subcnt;
633 for (j = 0; j < subcnt; ++j) {
634 KASSERT(hint_idx < cpu_mwait_deep_hints_cnt,
635 ("invalid mwait deep hint index %d",
637 cpu_mwait_deep_hints[hint_idx] =
638 MWAIT_EAX_HINT(i, j);
642 KASSERT(hint_idx == cpu_mwait_deep_hints_cnt,
643 ("mwait deep hint count %d != index %d",
644 cpu_mwait_deep_hints_cnt, hint_idx));
647 kprintf("MWAIT deep hints:\n");
648 for (i = 0; i < cpu_mwait_deep_hints_cnt; ++i) {
649 int hint = cpu_mwait_deep_hints[i];
651 kprintf(" C%d/%d hint 0x%04x\n",
652 MWAIT_EAX_TO_CX(hint),
653 MWAIT_EAX_TO_CX_SUB(hint), hint);
656 cpu_idle_repeat_max = 64 * cpu_mwait_deep_hints_cnt;
661 pic_finish(void *dummy __unused)
663 /* Log ELCR information */
666 /* Log MPTABLE information */
667 mptable_pci_int_dump();
670 MachIntrABI.finalize();
674 * Send an interrupt to process.
676 * Stack is set up to allow sigcode stored
677 * at top to call routine, followed by kcall
678 * to sigreturn routine below. After sigreturn
679 * resets the signal mask, the stack, and the
680 * frame pointer, it returns to the user
684 sendsig(sig_t catcher, int sig, sigset_t *mask, u_long code)
686 struct lwp *lp = curthread->td_lwp;
687 struct proc *p = lp->lwp_proc;
688 struct trapframe *regs;
689 struct sigacts *psp = p->p_sigacts;
690 struct sigframe sf, *sfp;
694 regs = lp->lwp_md.md_regs;
695 oonstack = (lp->lwp_sigstk.ss_flags & SS_ONSTACK) ? 1 : 0;
697 /* Save user context */
698 bzero(&sf, sizeof(struct sigframe));
699 sf.sf_uc.uc_sigmask = *mask;
700 sf.sf_uc.uc_stack = lp->lwp_sigstk;
701 sf.sf_uc.uc_mcontext.mc_onstack = oonstack;
702 KKASSERT(__offsetof(struct trapframe, tf_rdi) == 0);
703 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(struct trapframe));
705 /* Make the size of the saved context visible to userland */
706 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext);
708 /* Allocate and validate space for the signal handler context. */
709 if ((lp->lwp_flags & LWP_ALTSTACK) != 0 && !oonstack &&
710 SIGISMEMBER(psp->ps_sigonstack, sig)) {
711 sp = (char *)(lp->lwp_sigstk.ss_sp + lp->lwp_sigstk.ss_size -
712 sizeof(struct sigframe));
713 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
715 /* We take red zone into account */
716 sp = (char *)regs->tf_rsp - sizeof(struct sigframe) - 128;
720 * XXX AVX needs 64-byte alignment but sigframe has other fields and
721 * the embedded ucontext is not at the front, so aligning this won't
722 * help us. Fortunately we bcopy in/out of the sigframe, so the
725 * The problem though is if userland winds up trying to use the
728 sfp = (struct sigframe *)((intptr_t)sp & ~(intptr_t)0xF);
730 /* Translate the signal is appropriate */
731 if (p->p_sysent->sv_sigtbl) {
732 if (sig <= p->p_sysent->sv_sigsize)
733 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)];
737 * Build the argument list for the signal handler.
739 * Arguments are in registers (%rdi, %rsi, %rdx, %rcx)
741 regs->tf_rdi = sig; /* argument 1 */
742 regs->tf_rdx = (register_t)&sfp->sf_uc; /* argument 3 */
744 if (SIGISMEMBER(psp->ps_siginfo, sig)) {
746 * Signal handler installed with SA_SIGINFO.
748 * action(signo, siginfo, ucontext)
750 regs->tf_rsi = (register_t)&sfp->sf_si; /* argument 2 */
751 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */
752 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher;
754 /* fill siginfo structure */
755 sf.sf_si.si_signo = sig;
756 sf.sf_si.si_code = code;
757 sf.sf_si.si_addr = (void *)regs->tf_addr;
760 * Old FreeBSD-style arguments.
762 * handler (signo, code, [uc], addr)
764 regs->tf_rsi = (register_t)code; /* argument 2 */
765 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */
766 sf.sf_ahu.sf_handler = catcher;
770 * If we're a vm86 process, we want to save the segment registers.
771 * We also change eflags to be our emulated eflags, not the actual
775 if (regs->tf_eflags & PSL_VM) {
776 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
777 struct vm86_kernel *vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
779 sf.sf_uc.uc_mcontext.mc_gs = tf->tf_vm86_gs;
780 sf.sf_uc.uc_mcontext.mc_fs = tf->tf_vm86_fs;
781 sf.sf_uc.uc_mcontext.mc_es = tf->tf_vm86_es;
782 sf.sf_uc.uc_mcontext.mc_ds = tf->tf_vm86_ds;
784 if (vm86->vm86_has_vme == 0)
785 sf.sf_uc.uc_mcontext.mc_eflags =
786 (tf->tf_eflags & ~(PSL_VIF | PSL_VIP)) |
787 (vm86->vm86_eflags & (PSL_VIF | PSL_VIP));
790 * Clear PSL_NT to inhibit T_TSSFLT faults on return from
791 * syscalls made by the signal handler. This just avoids
792 * wasting time for our lazy fixup of such faults. PSL_NT
793 * does nothing in vm86 mode, but vm86 programs can set it
794 * almost legitimately in probes for old cpu types.
796 tf->tf_eflags &= ~(PSL_VM | PSL_NT | PSL_VIF | PSL_VIP);
801 * Save the FPU state and reinit the FP unit
803 npxpush(&sf.sf_uc.uc_mcontext);
806 * Copy the sigframe out to the user's stack.
808 if (copyout(&sf, sfp, sizeof(struct sigframe)) != 0) {
810 * Something is wrong with the stack pointer.
811 * ...Kill the process.
816 regs->tf_rsp = (register_t)sfp;
817 regs->tf_rip = PS_STRINGS - *(p->p_sysent->sv_szsigcode);
820 * i386 abi specifies that the direction flag must be cleared
823 regs->tf_rflags &= ~(PSL_T|PSL_D);
826 * 64 bit mode has a code and stack selector but
827 * no data or extra selector. %fs and %gs are not
830 regs->tf_cs = _ucodesel;
831 regs->tf_ss = _udatasel;
836 * Sanitize the trapframe for a virtual kernel passing control to a custom
837 * VM context. Remove any items that would otherwise create a privilage
840 * XXX at the moment we allow userland to set the resume flag. Is this a
844 cpu_sanitize_frame(struct trapframe *frame)
846 frame->tf_cs = _ucodesel;
847 frame->tf_ss = _udatasel;
848 /* XXX VM (8086) mode not supported? */
849 frame->tf_rflags &= (PSL_RF | PSL_USERCHANGE | PSL_VM_UNSUPP);
850 frame->tf_rflags |= PSL_RESERVED_DEFAULT | PSL_I;
856 * Sanitize the tls so loading the descriptor does not blow up
857 * on us. For x86_64 we don't have to do anything.
860 cpu_sanitize_tls(struct savetls *tls)
866 * sigreturn(ucontext_t *sigcntxp)
868 * System call to cleanup state after a signal
869 * has been taken. Reset signal mask and
870 * stack state from context left by sendsig (above).
871 * Return to previous pc and psl as specified by
872 * context left by sendsig. Check carefully to
873 * make sure that the user has not modified the
874 * state to gain improper privileges.
878 #define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0)
879 #define CS_SECURE(cs) (ISPL(cs) == SEL_UPL)
882 sys_sigreturn(struct sigreturn_args *uap)
884 struct lwp *lp = curthread->td_lwp;
885 struct trapframe *regs;
893 * We have to copy the information into kernel space so userland
894 * can't modify it while we are sniffing it.
896 regs = lp->lwp_md.md_regs;
897 error = copyin(uap->sigcntxp, &uc, sizeof(uc));
901 rflags = ucp->uc_mcontext.mc_rflags;
903 /* VM (8086) mode not supported */
904 rflags &= ~PSL_VM_UNSUPP;
907 if (eflags & PSL_VM) {
908 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
909 struct vm86_kernel *vm86;
912 * if pcb_ext == 0 or vm86_inited == 0, the user hasn't
913 * set up the vm86 area, and we can't enter vm86 mode.
915 if (lp->lwp_thread->td_pcb->pcb_ext == 0)
917 vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
918 if (vm86->vm86_inited == 0)
921 /* go back to user mode if both flags are set */
922 if ((eflags & PSL_VIP) && (eflags & PSL_VIF))
923 trapsignal(lp, SIGBUS, 0);
925 if (vm86->vm86_has_vme) {
926 eflags = (tf->tf_eflags & ~VME_USERCHANGE) |
927 (eflags & VME_USERCHANGE) | PSL_VM;
929 vm86->vm86_eflags = eflags; /* save VIF, VIP */
930 eflags = (tf->tf_eflags & ~VM_USERCHANGE) |
931 (eflags & VM_USERCHANGE) | PSL_VM;
933 bcopy(&ucp->uc_mcontext.mc_gs, tf, sizeof(struct trapframe));
934 tf->tf_eflags = eflags;
935 tf->tf_vm86_ds = tf->tf_ds;
936 tf->tf_vm86_es = tf->tf_es;
937 tf->tf_vm86_fs = tf->tf_fs;
938 tf->tf_vm86_gs = tf->tf_gs;
939 tf->tf_ds = _udatasel;
940 tf->tf_es = _udatasel;
941 tf->tf_fs = _udatasel;
942 tf->tf_gs = _udatasel;
947 * Don't allow users to change privileged or reserved flags.
950 * XXX do allow users to change the privileged flag PSL_RF.
951 * The cpu sets PSL_RF in tf_eflags for faults. Debuggers
952 * should sometimes set it there too. tf_eflags is kept in
953 * the signal context during signal handling and there is no
954 * other place to remember it, so the PSL_RF bit may be
955 * corrupted by the signal handler without us knowing.
956 * Corruption of the PSL_RF bit at worst causes one more or
957 * one less debugger trap, so allowing it is fairly harmless.
959 if (!EFL_SECURE(rflags & ~PSL_RF, regs->tf_rflags & ~PSL_RF)) {
960 kprintf("sigreturn: rflags = 0x%lx\n", (long)rflags);
965 * Don't allow users to load a valid privileged %cs. Let the
966 * hardware check for invalid selectors, excess privilege in
967 * other selectors, invalid %eip's and invalid %esp's.
969 cs = ucp->uc_mcontext.mc_cs;
970 if (!CS_SECURE(cs)) {
971 kprintf("sigreturn: cs = 0x%x\n", cs);
972 trapsignal(lp, SIGBUS, T_PROTFLT);
975 bcopy(&ucp->uc_mcontext.mc_rdi, regs, sizeof(struct trapframe));
979 * Restore the FPU state from the frame
982 npxpop(&ucp->uc_mcontext);
984 if (ucp->uc_mcontext.mc_onstack & 1)
985 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
987 lp->lwp_sigstk.ss_flags &= ~SS_ONSTACK;
989 lp->lwp_sigmask = ucp->uc_sigmask;
990 SIG_CANTMASK(lp->lwp_sigmask);
997 * Machine dependent boot() routine
999 * I haven't seen anything to put here yet
1000 * Possibly some stuff might be grafted back here from boot()
1008 * Shutdown the CPU as much as possible
1014 __asm__ __volatile("hlt");
1018 * cpu_idle() represents the idle LWKT. You cannot return from this function
1019 * (unless you want to blow things up!). Instead we look for runnable threads
1020 * and loop or halt as appropriate. Giant is not held on entry to the thread.
1022 * The main loop is entered with a critical section held, we must release
1023 * the critical section before doing anything else. lwkt_switch() will
1024 * check for pending interrupts due to entering and exiting its own
1027 * NOTE: On an SMP system we rely on a scheduler IPI to wake a HLTed cpu up.
1028 * However, there are cases where the idlethread will be entered with
1029 * the possibility that no IPI will occur and in such cases
1030 * lwkt_switch() sets TDF_IDLE_NOHLT.
1032 * NOTE: cpu_idle_repeat determines how many entries into the idle thread
1033 * must occur before it starts using ACPI halt.
1035 static int cpu_idle_hlt = 2;
1036 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hlt, CTLFLAG_RW,
1037 &cpu_idle_hlt, 0, "Idle loop HLT enable");
1038 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_repeat, CTLFLAG_RW,
1039 &cpu_idle_repeat, 0, "Idle entries before acpi hlt");
1041 SYSCTL_PROC(_machdep, OID_AUTO, cpu_idle_hltcnt, (CTLTYPE_QUAD | CTLFLAG_RW),
1042 0, CPU_IDLE_STAT_HALT, sysctl_cpu_idle_cnt, "Q", "Idle loop entry halts");
1043 SYSCTL_PROC(_machdep, OID_AUTO, cpu_idle_spincnt, (CTLTYPE_QUAD | CTLFLAG_RW),
1044 0, CPU_IDLE_STAT_SPIN, sysctl_cpu_idle_cnt, "Q", "Idle loop entry spins");
1047 cpu_idle_default_hook(void)
1050 * We must guarentee that hlt is exactly the instruction
1051 * following the sti.
1053 __asm __volatile("sti; hlt");
1056 /* Other subsystems (e.g., ACPI) can hook this later. */
1057 void (*cpu_idle_hook)(void) = cpu_idle_default_hook;
1060 cpu_mwait_cx_hint(struct cpu_idle_stat *stat)
1065 if (cpu_mwait_halt >= 0) {
1066 hint = cpu_mwait_halt;
1070 idx = (stat->repeat + stat->repeat_last) >> 1;
1071 if (cpu_mwait_halt == CPU_MWAIT_HINT_AUTODEEP) {
1072 if (idx >= cpu_mwait_deep_hints_cnt)
1073 idx = cpu_mwait_deep_hints_cnt - 1;
1074 hint = cpu_mwait_deep_hints[idx];
1076 if (idx >= cpu_mwait_hints_cnt)
1077 idx = cpu_mwait_hints_cnt - 1;
1078 hint = cpu_mwait_hints[idx];
1081 cx_idx = MWAIT_EAX_TO_CX(hint);
1082 if (cx_idx >= 0 && cx_idx < CPU_MWAIT_CX_MAX)
1083 stat->mwait_cx[cx_idx]++;
1090 globaldata_t gd = mycpu;
1091 struct cpu_idle_stat *stat = &cpu_idle_stats[gd->gd_cpuid];
1092 struct thread *td __debugvar = gd->gd_curthread;
1096 stat->repeat = stat->repeat_last = cpu_idle_repeat_max;
1099 KKASSERT(td->td_critcount == 0);
1102 * See if there are any LWKTs ready to go.
1107 * When halting inside a cli we must check for reqflags
1108 * races, particularly [re]schedule requests. Running
1109 * splz() does the job.
1112 * 0 Never halt, just spin
1114 * 1 Always use HLT (or MONITOR/MWAIT if avail).
1115 * This typically eats more power than the
1118 * 2 Use HLT/MONITOR/MWAIT up to a point and then
1119 * use the ACPI halt (default). This is a hybrid
1120 * approach. See machdep.cpu_idle_repeat.
1122 * 3 Always use the ACPI halt. This typically
1123 * eats the least amount of power but the cpu
1124 * will be slow waking up. Slows down e.g.
1125 * compiles and other pipe/event oriented stuff.
1127 * NOTE: Interrupts are enabled and we are not in a critical
1130 * NOTE: Preemptions do not reset gd_idle_repeat. Also we
1131 * don't bother capping gd_idle_repeat, it is ok if
1134 if (gd->gd_idle_repeat == 0) {
1135 stat->repeat = (stat->repeat + stat->repeat_last) >> 1;
1136 if (stat->repeat > cpu_idle_repeat_max)
1137 stat->repeat = cpu_idle_repeat_max;
1138 stat->repeat_last = 0;
1140 ++stat->repeat_last;
1142 ++gd->gd_idle_repeat;
1143 reqflags = gd->gd_reqflags;
1144 quick = (cpu_idle_hlt == 1) ||
1145 (cpu_idle_hlt < 3 &&
1146 gd->gd_idle_repeat < cpu_idle_repeat);
1148 if (quick && (cpu_mi_feature & CPU_MI_MONITOR) &&
1149 (reqflags & RQF_IDLECHECK_WK_MASK) == 0) {
1151 cpu_mmw_pause_int(&gd->gd_reqflags, reqflags,
1152 cpu_mwait_cx_hint(stat), 0);
1154 } else if (cpu_idle_hlt) {
1155 __asm __volatile("cli");
1157 if ((gd->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) {
1159 cpu_idle_default_hook();
1163 __asm __volatile("sti");
1167 __asm __volatile("sti");
1174 * This routine is called if a spinlock has been held through the
1175 * exponential backoff period and is seriously contested. On a real cpu
1179 cpu_spinlock_contested(void)
1185 * Clear registers on exec
1188 exec_setregs(u_long entry, u_long stack, u_long ps_strings)
1190 struct thread *td = curthread;
1191 struct lwp *lp = td->td_lwp;
1192 struct pcb *pcb = td->td_pcb;
1193 struct trapframe *regs = lp->lwp_md.md_regs;
1195 /* was i386_user_cleanup() in NetBSD */
1199 bzero((char *)regs, sizeof(struct trapframe));
1200 regs->tf_rip = entry;
1201 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8; /* align the stack */
1202 regs->tf_rdi = stack; /* argv */
1203 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T);
1204 regs->tf_ss = _udatasel;
1205 regs->tf_cs = _ucodesel;
1206 regs->tf_rbx = ps_strings;
1209 * Reset the hardware debug registers if they were in use.
1210 * They won't have any meaning for the newly exec'd process.
1212 if (pcb->pcb_flags & PCB_DBREGS) {
1218 pcb->pcb_dr7 = 0; /* JG set bit 10? */
1219 if (pcb == td->td_pcb) {
1221 * Clear the debug registers on the running
1222 * CPU, otherwise they will end up affecting
1223 * the next process we switch to.
1227 pcb->pcb_flags &= ~PCB_DBREGS;
1231 * Initialize the math emulator (if any) for the current process.
1232 * Actually, just clear the bit that says that the emulator has
1233 * been initialized. Initialization is delayed until the process
1234 * traps to the emulator (if it is done at all) mainly because
1235 * emulators don't provide an entry point for initialization.
1237 pcb->pcb_flags &= ~FP_SOFTFP;
1240 * NOTE: do not set CR0_TS here. npxinit() must do it after clearing
1241 * gd_npxthread. Otherwise a preemptive interrupt thread
1242 * may panic in npxdna().
1245 load_cr0(rcr0() | CR0_MP);
1248 * NOTE: The MSR values must be correct so we can return to
1249 * userland. gd_user_fs/gs must be correct so the switch
1250 * code knows what the current MSR values are.
1252 pcb->pcb_fsbase = 0; /* Values loaded from PCB on switch */
1253 pcb->pcb_gsbase = 0;
1254 mdcpu->gd_user_fs = 0; /* Cache of current MSR values */
1255 mdcpu->gd_user_gs = 0;
1256 wrmsr(MSR_FSBASE, 0); /* Set MSR values for return to userland */
1257 wrmsr(MSR_KGSBASE, 0);
1259 /* Initialize the npx (if any) for the current process. */
1260 npxinit(__INITIAL_FPUCW__);
1263 pcb->pcb_ds = _udatasel;
1264 pcb->pcb_es = _udatasel;
1265 pcb->pcb_fs = _udatasel;
1266 pcb->pcb_gs = _udatasel;
1275 cr0 |= CR0_NE; /* Done by npxinit() */
1276 cr0 |= CR0_MP | CR0_TS; /* Done at every execve() too. */
1277 cr0 |= CR0_WP | CR0_AM;
1283 sysctl_machdep_adjkerntz(SYSCTL_HANDLER_ARGS)
1286 error = sysctl_handle_int(oidp, oidp->oid_arg1, oidp->oid_arg2,
1288 if (!error && req->newptr)
1293 SYSCTL_PROC(_machdep, CPU_ADJKERNTZ, adjkerntz, CTLTYPE_INT|CTLFLAG_RW,
1294 &adjkerntz, 0, sysctl_machdep_adjkerntz, "I", "");
1296 SYSCTL_INT(_machdep, CPU_DISRTCSET, disable_rtc_set,
1297 CTLFLAG_RW, &disable_rtc_set, 0, "");
1300 SYSCTL_STRUCT(_machdep, CPU_BOOTINFO, bootinfo,
1301 CTLFLAG_RD, &bootinfo, bootinfo, "");
1304 SYSCTL_INT(_machdep, CPU_WALLCLOCK, wall_cmos_clock,
1305 CTLFLAG_RW, &wall_cmos_clock, 0, "");
1307 extern u_long bootdev; /* not a cdev_t - encoding is different */
1308 SYSCTL_ULONG(_machdep, OID_AUTO, guessed_bootdev,
1309 CTLFLAG_RD, &bootdev, 0, "Boot device (not in cdev_t format)");
1312 * Initialize 386 and configure to run kernel
1316 * Initialize segments & interrupt table
1320 struct user_segment_descriptor gdt[NGDT * MAXCPU]; /* global descriptor table */
1321 struct gate_descriptor idt_arr[MAXCPU][NIDT];
1323 union descriptor ldt[NLDT]; /* local descriptor table */
1326 /* table descriptors - used to load tables by cpu */
1327 struct region_descriptor r_gdt;
1328 struct region_descriptor r_idt_arr[MAXCPU];
1330 /* JG proc0paddr is a virtual address */
1333 char proc0paddr_buff[LWKT_THREAD_STACK];
1336 /* software prototypes -- in more palatable form */
1337 struct soft_segment_descriptor gdt_segs[] = {
1338 /* GNULL_SEL 0 Null Descriptor */
1339 { 0x0, /* segment base address */
1341 0, /* segment type */
1342 0, /* segment descriptor priority level */
1343 0, /* segment descriptor present */
1345 0, /* default 32 vs 16 bit size */
1346 0 /* limit granularity (byte/page units)*/ },
1347 /* GCODE_SEL 1 Code Descriptor for kernel */
1348 { 0x0, /* segment base address */
1349 0xfffff, /* length - all address space */
1350 SDT_MEMERA, /* segment type */
1351 SEL_KPL, /* segment descriptor priority level */
1352 1, /* segment descriptor present */
1354 0, /* default 32 vs 16 bit size */
1355 1 /* limit granularity (byte/page units)*/ },
1356 /* GDATA_SEL 2 Data Descriptor for kernel */
1357 { 0x0, /* segment base address */
1358 0xfffff, /* length - all address space */
1359 SDT_MEMRWA, /* segment type */
1360 SEL_KPL, /* segment descriptor priority level */
1361 1, /* segment descriptor present */
1363 0, /* default 32 vs 16 bit size */
1364 1 /* limit granularity (byte/page units)*/ },
1365 /* GUCODE32_SEL 3 32 bit Code Descriptor for user */
1366 { 0x0, /* segment base address */
1367 0xfffff, /* length - all address space */
1368 SDT_MEMERA, /* segment type */
1369 SEL_UPL, /* segment descriptor priority level */
1370 1, /* segment descriptor present */
1372 1, /* default 32 vs 16 bit size */
1373 1 /* limit granularity (byte/page units)*/ },
1374 /* GUDATA_SEL 4 32/64 bit Data Descriptor for user */
1375 { 0x0, /* segment base address */
1376 0xfffff, /* length - all address space */
1377 SDT_MEMRWA, /* segment type */
1378 SEL_UPL, /* segment descriptor priority level */
1379 1, /* segment descriptor present */
1381 1, /* default 32 vs 16 bit size */
1382 1 /* limit granularity (byte/page units)*/ },
1383 /* GUCODE_SEL 5 64 bit Code Descriptor for user */
1384 { 0x0, /* segment base address */
1385 0xfffff, /* length - all address space */
1386 SDT_MEMERA, /* segment type */
1387 SEL_UPL, /* segment descriptor priority level */
1388 1, /* segment descriptor present */
1390 0, /* default 32 vs 16 bit size */
1391 1 /* limit granularity (byte/page units)*/ },
1392 /* GPROC0_SEL 6 Proc 0 Tss Descriptor */
1394 0x0, /* segment base address */
1395 sizeof(struct x86_64tss)-1,/* length - all address space */
1396 SDT_SYSTSS, /* segment type */
1397 SEL_KPL, /* segment descriptor priority level */
1398 1, /* segment descriptor present */
1400 0, /* unused - default 32 vs 16 bit size */
1401 0 /* limit granularity (byte/page units)*/ },
1402 /* Actually, the TSS is a system descriptor which is double size */
1403 { 0x0, /* segment base address */
1405 0, /* segment type */
1406 0, /* segment descriptor priority level */
1407 0, /* segment descriptor present */
1409 0, /* default 32 vs 16 bit size */
1410 0 /* limit granularity (byte/page units)*/ },
1411 /* GUGS32_SEL 8 32 bit GS Descriptor for user */
1412 { 0x0, /* segment base address */
1413 0xfffff, /* length - all address space */
1414 SDT_MEMRWA, /* segment type */
1415 SEL_UPL, /* segment descriptor priority level */
1416 1, /* segment descriptor present */
1418 1, /* default 32 vs 16 bit size */
1419 1 /* limit granularity (byte/page units)*/ },
1423 setidt_global(int idx, inthand_t *func, int typ, int dpl, int ist)
1427 for (cpu = 0; cpu < MAXCPU; ++cpu) {
1428 struct gate_descriptor *ip = &idt_arr[cpu][idx];
1430 ip->gd_looffset = (uintptr_t)func;
1431 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL);
1437 ip->gd_hioffset = ((uintptr_t)func)>>16 ;
1442 setidt(int idx, inthand_t *func, int typ, int dpl, int ist, int cpu)
1444 struct gate_descriptor *ip;
1446 KASSERT(cpu >= 0 && cpu < ncpus, ("invalid cpu %d", cpu));
1448 ip = &idt_arr[cpu][idx];
1449 ip->gd_looffset = (uintptr_t)func;
1450 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL);
1456 ip->gd_hioffset = ((uintptr_t)func)>>16 ;
1459 #define IDTVEC(name) __CONCAT(X,name)
1462 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl),
1463 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm),
1464 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot),
1465 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align),
1466 IDTVEC(xmm), IDTVEC(dblfault),
1467 IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
1469 #ifdef DEBUG_INTERRUPTS
1470 extern inthand_t *Xrsvdary[256];
1474 sdtossd(struct user_segment_descriptor *sd, struct soft_segment_descriptor *ssd)
1476 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase;
1477 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit;
1478 ssd->ssd_type = sd->sd_type;
1479 ssd->ssd_dpl = sd->sd_dpl;
1480 ssd->ssd_p = sd->sd_p;
1481 ssd->ssd_def32 = sd->sd_def32;
1482 ssd->ssd_gran = sd->sd_gran;
1486 ssdtosd(struct soft_segment_descriptor *ssd, struct user_segment_descriptor *sd)
1489 sd->sd_lobase = (ssd->ssd_base) & 0xffffff;
1490 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff;
1491 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff;
1492 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf;
1493 sd->sd_type = ssd->ssd_type;
1494 sd->sd_dpl = ssd->ssd_dpl;
1495 sd->sd_p = ssd->ssd_p;
1496 sd->sd_long = ssd->ssd_long;
1497 sd->sd_def32 = ssd->ssd_def32;
1498 sd->sd_gran = ssd->ssd_gran;
1502 ssdtosyssd(struct soft_segment_descriptor *ssd,
1503 struct system_segment_descriptor *sd)
1506 sd->sd_lobase = (ssd->ssd_base) & 0xffffff;
1507 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful;
1508 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff;
1509 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf;
1510 sd->sd_type = ssd->ssd_type;
1511 sd->sd_dpl = ssd->ssd_dpl;
1512 sd->sd_p = ssd->ssd_p;
1513 sd->sd_gran = ssd->ssd_gran;
1517 * Populate the (physmap) array with base/bound pairs describing the
1518 * available physical memory in the system, then test this memory and
1519 * build the phys_avail array describing the actually-available memory.
1521 * If we cannot accurately determine the physical memory map, then use
1522 * value from the 0xE801 call, and failing that, the RTC.
1524 * Total memory size may be set by the kernel environment variable
1525 * hw.physmem or the compile-time define MAXMEM.
1527 * Memory is aligned to PHYSMAP_ALIGN which must be a multiple
1528 * of PAGE_SIZE. This also greatly reduces the memory test time
1529 * which would otherwise be excessive on machines with > 8G of ram.
1531 * XXX first should be vm_paddr_t.
1534 #define PHYSMAP_ALIGN (vm_paddr_t)(128 * 1024)
1535 #define PHYSMAP_ALIGN_MASK (vm_paddr_t)(PHYSMAP_ALIGN - 1)
1538 getmemsize(caddr_t kmdp, u_int64_t first)
1540 int off, physmap_idx, pa_indx, da_indx;
1542 vm_paddr_t physmap[PHYSMAP_SIZE];
1544 vm_paddr_t msgbuf_size;
1545 u_long physmem_tunable;
1547 struct bios_smap *smapbase, *smap, *smapend;
1549 quad_t dcons_addr, dcons_size;
1551 bzero(physmap, sizeof(physmap));
1555 * get memory map from INT 15:E820, kindly supplied by the loader.
1557 * subr_module.c says:
1558 * "Consumer may safely assume that size value precedes data."
1559 * ie: an int32_t immediately precedes smap.
1561 smapbase = (struct bios_smap *)preload_search_info(kmdp,
1562 MODINFO_METADATA | MODINFOMD_SMAP);
1563 if (smapbase == NULL)
1564 panic("No BIOS smap info from loader!");
1566 smapsize = *((u_int32_t *)smapbase - 1);
1567 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize);
1569 for (smap = smapbase; smap < smapend; smap++) {
1570 if (boothowto & RB_VERBOSE)
1571 kprintf("SMAP type=%02x base=%016lx len=%016lx\n",
1572 smap->type, smap->base, smap->length);
1574 if (smap->type != SMAP_TYPE_MEMORY)
1577 if (smap->length == 0)
1580 for (i = 0; i <= physmap_idx; i += 2) {
1581 if (smap->base < physmap[i + 1]) {
1582 if (boothowto & RB_VERBOSE) {
1583 kprintf("Overlapping or non-monotonic "
1584 "memory region, ignoring "
1590 if (i <= physmap_idx)
1593 Realmem += smap->length;
1595 if (smap->base == physmap[physmap_idx + 1]) {
1596 physmap[physmap_idx + 1] += smap->length;
1601 if (physmap_idx == PHYSMAP_SIZE) {
1602 kprintf("Too many segments in the physical "
1603 "address map, giving up\n");
1606 physmap[physmap_idx] = smap->base;
1607 physmap[physmap_idx + 1] = smap->base + smap->length;
1610 base_memory = physmap[1] / 1024;
1611 /* make hole for AP bootstrap code */
1612 physmap[1] = mp_bootaddress(base_memory);
1614 /* Save EBDA address, if any */
1615 ebda_addr = (u_long)(*(u_short *)(KERNBASE + 0x40e));
1619 * Maxmem isn't the "maximum memory", it's one larger than the
1620 * highest page of the physical address space. It should be
1621 * called something like "Maxphyspage". We may adjust this
1622 * based on ``hw.physmem'' and the results of the memory test.
1624 Maxmem = atop(physmap[physmap_idx + 1]);
1627 Maxmem = MAXMEM / 4;
1630 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable))
1631 Maxmem = atop(physmem_tunable);
1634 * Don't allow MAXMEM or hw.physmem to extend the amount of memory
1637 if (Maxmem > atop(physmap[physmap_idx + 1]))
1638 Maxmem = atop(physmap[physmap_idx + 1]);
1641 * Blowing out the DMAP will blow up the system.
1643 if (Maxmem > atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS)) {
1644 kprintf("Limiting Maxmem due to DMAP size\n");
1645 Maxmem = atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS);
1648 if (atop(physmap[physmap_idx + 1]) != Maxmem &&
1649 (boothowto & RB_VERBOSE)) {
1650 kprintf("Physical memory use set to %ldK\n", Maxmem * 4);
1654 * Call pmap initialization to make new kernel address space
1658 pmap_bootstrap(&first);
1659 physmap[0] = PAGE_SIZE;
1662 * Align the physmap to PHYSMAP_ALIGN and cut out anything
1665 for (i = j = 0; i <= physmap_idx; i += 2) {
1666 if (physmap[i+1] > ptoa(Maxmem))
1667 physmap[i+1] = ptoa(Maxmem);
1668 physmap[i] = (physmap[i] + PHYSMAP_ALIGN_MASK) &
1669 ~PHYSMAP_ALIGN_MASK;
1670 physmap[i+1] = physmap[i+1] & ~PHYSMAP_ALIGN_MASK;
1672 physmap[j] = physmap[i];
1673 physmap[j+1] = physmap[i+1];
1675 if (physmap[i] < physmap[i+1])
1678 physmap_idx = j - 2;
1681 * Align anything else used in the validation loop.
1683 first = (first + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK;
1686 * Size up each available chunk of physical memory.
1690 phys_avail[pa_indx++] = physmap[0];
1691 phys_avail[pa_indx] = physmap[0];
1692 dump_avail[da_indx] = physmap[0];
1696 * Get dcons buffer address
1698 if (kgetenv_quad("dcons.addr", &dcons_addr) == 0 ||
1699 kgetenv_quad("dcons.size", &dcons_size) == 0)
1703 * Validate the physical memory. The physical memory segments
1704 * have already been aligned to PHYSMAP_ALIGN which is a multiple
1707 for (i = 0; i <= physmap_idx; i += 2) {
1710 end = physmap[i + 1];
1712 for (pa = physmap[i]; pa < end; pa += PHYSMAP_ALIGN) {
1713 int tmp, page_bad, full;
1714 int *ptr = (int *)CADDR1;
1718 * block out kernel memory as not available.
1720 if (pa >= 0x200000 && pa < first)
1724 * block out dcons buffer
1727 && pa >= trunc_page(dcons_addr)
1728 && pa < dcons_addr + dcons_size) {
1735 * map page into kernel: valid, read/write,non-cacheable
1738 kernel_pmap.pmap_bits[PG_V_IDX] |
1739 kernel_pmap.pmap_bits[PG_RW_IDX] |
1740 kernel_pmap.pmap_bits[PG_N_IDX];
1745 * Test for alternating 1's and 0's
1747 *(volatile int *)ptr = 0xaaaaaaaa;
1749 if (*(volatile int *)ptr != 0xaaaaaaaa)
1752 * Test for alternating 0's and 1's
1754 *(volatile int *)ptr = 0x55555555;
1756 if (*(volatile int *)ptr != 0x55555555)
1761 *(volatile int *)ptr = 0xffffffff;
1763 if (*(volatile int *)ptr != 0xffffffff)
1768 *(volatile int *)ptr = 0x0;
1770 if (*(volatile int *)ptr != 0x0)
1773 * Restore original value.
1778 * Adjust array of valid/good pages.
1780 if (page_bad == TRUE)
1783 * If this good page is a continuation of the
1784 * previous set of good pages, then just increase
1785 * the end pointer. Otherwise start a new chunk.
1786 * Note that "end" points one higher than end,
1787 * making the range >= start and < end.
1788 * If we're also doing a speculative memory
1789 * test and we at or past the end, bump up Maxmem
1790 * so that we keep going. The first bad page
1791 * will terminate the loop.
1793 if (phys_avail[pa_indx] == pa) {
1794 phys_avail[pa_indx] += PHYSMAP_ALIGN;
1797 if (pa_indx == PHYS_AVAIL_ARRAY_END) {
1799 "Too many holes in the physical address space, giving up\n");
1804 phys_avail[pa_indx++] = pa;
1805 phys_avail[pa_indx] = pa + PHYSMAP_ALIGN;
1807 physmem += PHYSMAP_ALIGN / PAGE_SIZE;
1809 if (dump_avail[da_indx] == pa) {
1810 dump_avail[da_indx] += PHYSMAP_ALIGN;
1813 if (da_indx == DUMP_AVAIL_ARRAY_END) {
1817 dump_avail[da_indx++] = pa;
1818 dump_avail[da_indx] = pa + PHYSMAP_ALIGN;
1829 * The last chunk must contain at least one page plus the message
1830 * buffer to avoid complicating other code (message buffer address
1831 * calculation, etc.).
1833 msgbuf_size = (MSGBUF_SIZE + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK;
1835 while (phys_avail[pa_indx - 1] + PHYSMAP_ALIGN +
1836 msgbuf_size >= phys_avail[pa_indx]) {
1837 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]);
1838 phys_avail[pa_indx--] = 0;
1839 phys_avail[pa_indx--] = 0;
1842 Maxmem = atop(phys_avail[pa_indx]);
1844 /* Trim off space for the message buffer. */
1845 phys_avail[pa_indx] -= msgbuf_size;
1847 avail_end = phys_avail[pa_indx];
1849 /* Map the message buffer. */
1850 for (off = 0; off < msgbuf_size; off += PAGE_SIZE) {
1851 pmap_kenter((vm_offset_t)msgbufp + off,
1852 phys_avail[pa_indx] + off);
1856 struct machintr_abi MachIntrABI;
1867 * 7 Device Not Available (x87)
1869 * 9 Coprocessor Segment overrun (unsupported, reserved)
1871 * 11 Segment not present
1873 * 13 General Protection
1876 * 16 x87 FP Exception pending
1877 * 17 Alignment Check
1879 * 19 SIMD floating point
1881 * 32-255 INTn/external sources
1884 hammer_time(u_int64_t modulep, u_int64_t physfree)
1887 int gsel_tss, x, cpu;
1889 int metadata_missing, off;
1891 struct mdglobaldata *gd;
1895 * Prevent lowering of the ipl if we call tsleep() early.
1897 gd = &CPU_prvspace[0].mdglobaldata;
1898 bzero(gd, sizeof(*gd));
1901 * Note: on both UP and SMP curthread must be set non-NULL
1902 * early in the boot sequence because the system assumes
1903 * that 'curthread' is never NULL.
1906 gd->mi.gd_curthread = &thread0;
1907 thread0.td_gd = &gd->mi;
1909 atdevbase = ISA_HOLE_START + PTOV_OFFSET;
1912 metadata_missing = 0;
1913 if (bootinfo.bi_modulep) {
1914 preload_metadata = (caddr_t)bootinfo.bi_modulep + KERNBASE;
1915 preload_bootstrap_relocate(KERNBASE);
1917 metadata_missing = 1;
1919 if (bootinfo.bi_envp)
1920 kern_envp = (caddr_t)bootinfo.bi_envp + KERNBASE;
1923 preload_metadata = (caddr_t)(uintptr_t)(modulep + PTOV_OFFSET);
1924 preload_bootstrap_relocate(PTOV_OFFSET);
1925 kmdp = preload_search_by_type("elf kernel");
1927 kmdp = preload_search_by_type("elf64 kernel");
1928 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int);
1929 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + PTOV_OFFSET;
1931 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t);
1932 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t);
1935 if (boothowto & RB_VERBOSE)
1939 * Default MachIntrABI to ICU
1941 MachIntrABI = MachIntrABI_ICU;
1944 * start with one cpu. Note: with one cpu, ncpus2_shift, ncpus2_mask,
1945 * and ncpus_fit_mask remain 0.
1950 /* Init basic tunables, hz etc */
1954 * make gdt memory segments
1956 gdt_segs[GPROC0_SEL].ssd_base =
1957 (uintptr_t) &CPU_prvspace[0].mdglobaldata.gd_common_tss;
1959 gd->mi.gd_prvspace = &CPU_prvspace[0];
1961 for (x = 0; x < NGDT; x++) {
1962 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
1963 ssdtosd(&gdt_segs[x], &gdt[x]);
1965 ssdtosyssd(&gdt_segs[GPROC0_SEL],
1966 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]);
1968 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
1969 r_gdt.rd_base = (long) gdt;
1972 wrmsr(MSR_FSBASE, 0); /* User value */
1973 wrmsr(MSR_GSBASE, (u_int64_t)&gd->mi);
1974 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */
1976 mi_gdinit(&gd->mi, 0);
1978 proc0paddr = proc0paddr_buff;
1979 mi_proc0init(&gd->mi, proc0paddr);
1980 safepri = TDPRI_MAX;
1982 /* spinlocks and the BGL */
1986 for (x = 0; x < NIDT; x++)
1987 setidt_global(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0);
1988 setidt_global(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0);
1989 setidt_global(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 0);
1990 setidt_global(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 1);
1991 setidt_global(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0);
1992 setidt_global(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0);
1993 setidt_global(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0);
1994 setidt_global(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0);
1995 setidt_global(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0);
1996 setidt_global(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1);
1997 setidt_global(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0);
1998 setidt_global(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0);
1999 setidt_global(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0);
2000 setidt_global(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0);
2001 setidt_global(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0);
2002 setidt_global(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0);
2003 setidt_global(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0);
2004 setidt_global(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0);
2005 setidt_global(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0);
2006 setidt_global(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0);
2008 for (cpu = 0; cpu < MAXCPU; ++cpu) {
2009 r_idt_arr[cpu].rd_limit = sizeof(idt_arr[cpu]) - 1;
2010 r_idt_arr[cpu].rd_base = (long) &idt_arr[cpu][0];
2013 lidt(&r_idt_arr[0]);
2016 * Initialize the console before we print anything out.
2021 if (metadata_missing)
2022 kprintf("WARNING: loader(8) metadata is missing!\n");
2032 * Initialize IRQ mapping
2035 * SHOULD be after elcr_probe()
2037 MachIntrABI_ICU.initmap();
2038 MachIntrABI_IOAPIC.initmap();
2042 if (boothowto & RB_KDB)
2043 Debugger("Boot flags requested debugger");
2047 finishidentcpu(); /* Final stage of CPU initialization */
2048 setidt(6, &IDTVEC(ill), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2049 setidt(13, &IDTVEC(prot), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2051 identify_cpu(); /* Final stage of CPU initialization */
2052 initializecpu(0); /* Initialize CPU registers */
2054 TUNABLE_INT_FETCH("hw.apic_io_enable", &ioapic_enable); /* for compat */
2055 TUNABLE_INT_FETCH("hw.ioapic_enable", &ioapic_enable);
2056 TUNABLE_INT_FETCH("hw.lapic_enable", &lapic_enable);
2059 * Some of the virtual machines do not work w/ I/O APIC
2060 * enabled. If the user does not explicitly enable or
2061 * disable the I/O APIC (ioapic_enable < 0), then we
2062 * disable I/O APIC on all virtual machines.
2065 * This must be done after identify_cpu(), which sets
2068 if (ioapic_enable < 0) {
2069 if (cpu_feature2 & CPUID2_VMM)
2075 /* make an initial tss so cpu can get interrupt stack on syscall! */
2076 gd->gd_common_tss.tss_rsp0 =
2077 (register_t)(thread0.td_kstack +
2078 KSTACK_PAGES * PAGE_SIZE - sizeof(struct pcb));
2079 /* Ensure the stack is aligned to 16 bytes */
2080 gd->gd_common_tss.tss_rsp0 &= ~(register_t)0xF;
2082 /* double fault stack */
2083 gd->gd_common_tss.tss_ist1 =
2084 (long)&gd->mi.gd_prvspace->idlestack[
2085 sizeof(gd->mi.gd_prvspace->idlestack)];
2087 /* Set the IO permission bitmap (empty due to tss seg limit) */
2088 gd->gd_common_tss.tss_iobase = sizeof(struct x86_64tss);
2090 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
2091 gd->gd_tss_gdt = &gdt[GPROC0_SEL];
2092 gd->gd_common_tssd = *gd->gd_tss_gdt;
2095 /* Set up the fast syscall stuff */
2096 msr = rdmsr(MSR_EFER) | EFER_SCE;
2097 wrmsr(MSR_EFER, msr);
2098 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
2099 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
2100 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
2101 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
2102 wrmsr(MSR_STAR, msr);
2103 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D|PSL_IOPL);
2105 getmemsize(kmdp, physfree);
2106 init_param2(physmem);
2108 /* now running on new page tables, configured,and u/iom is accessible */
2110 /* Map the message buffer. */
2112 for (off = 0; off < round_page(MSGBUF_SIZE); off += PAGE_SIZE)
2113 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off);
2116 msgbufinit(msgbufp, MSGBUF_SIZE);
2119 /* transfer to user mode */
2121 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL);
2122 _udatasel = GSEL(GUDATA_SEL, SEL_UPL);
2123 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL);
2129 /* setup proc 0's pcb */
2130 thread0.td_pcb->pcb_flags = 0;
2131 thread0.td_pcb->pcb_cr3 = KPML4phys;
2132 thread0.td_pcb->pcb_ext = NULL;
2133 lwp0.lwp_md.md_regs = &proc0_tf; /* XXX needed? */
2135 /* Location of kernel stack for locore */
2136 return ((u_int64_t)thread0.td_pcb);
2140 * Initialize machine-dependant portions of the global data structure.
2141 * Note that the global data area and cpu0's idlestack in the private
2142 * data space were allocated in locore.
2144 * Note: the idlethread's cpl is 0
2146 * WARNING! Called from early boot, 'mycpu' may not work yet.
2149 cpu_gdinit(struct mdglobaldata *gd, int cpu)
2152 gd->mi.gd_curthread = &gd->mi.gd_idlethread;
2154 lwkt_init_thread(&gd->mi.gd_idlethread,
2155 gd->mi.gd_prvspace->idlestack,
2156 sizeof(gd->mi.gd_prvspace->idlestack),
2158 lwkt_set_comm(&gd->mi.gd_idlethread, "idle_%d", cpu);
2159 gd->mi.gd_idlethread.td_switch = cpu_lwkt_switch;
2160 gd->mi.gd_idlethread.td_sp -= sizeof(void *);
2161 *(void **)gd->mi.gd_idlethread.td_sp = cpu_idle_restore;
2165 is_globaldata_space(vm_offset_t saddr, vm_offset_t eaddr)
2167 if (saddr >= (vm_offset_t)&CPU_prvspace[0] &&
2168 eaddr <= (vm_offset_t)&CPU_prvspace[MAXCPU]) {
2171 if (saddr >= DMAP_MIN_ADDRESS && eaddr <= DMAP_MAX_ADDRESS)
2177 globaldata_find(int cpu)
2179 KKASSERT(cpu >= 0 && cpu < ncpus);
2180 return(&CPU_prvspace[cpu].mdglobaldata.mi);
2184 ptrace_set_pc(struct lwp *lp, unsigned long addr)
2186 lp->lwp_md.md_regs->tf_rip = addr;
2191 ptrace_single_step(struct lwp *lp)
2193 lp->lwp_md.md_regs->tf_rflags |= PSL_T;
2198 fill_regs(struct lwp *lp, struct reg *regs)
2200 struct trapframe *tp;
2202 if ((tp = lp->lwp_md.md_regs) == NULL)
2204 bcopy(&tp->tf_rdi, ®s->r_rdi, sizeof(*regs));
2209 set_regs(struct lwp *lp, struct reg *regs)
2211 struct trapframe *tp;
2213 tp = lp->lwp_md.md_regs;
2214 if (!EFL_SECURE(regs->r_rflags, tp->tf_rflags) ||
2215 !CS_SECURE(regs->r_cs))
2217 bcopy(®s->r_rdi, &tp->tf_rdi, sizeof(*regs));
2222 #ifndef CPU_DISABLE_SSE
2224 fill_fpregs_xmm(struct savexmm *sv_xmm, struct save87 *sv_87)
2226 struct env87 *penv_87 = &sv_87->sv_env;
2227 struct envxmm *penv_xmm = &sv_xmm->sv_env;
2230 /* FPU control/status */
2231 penv_87->en_cw = penv_xmm->en_cw;
2232 penv_87->en_sw = penv_xmm->en_sw;
2233 penv_87->en_tw = penv_xmm->en_tw;
2234 penv_87->en_fip = penv_xmm->en_fip;
2235 penv_87->en_fcs = penv_xmm->en_fcs;
2236 penv_87->en_opcode = penv_xmm->en_opcode;
2237 penv_87->en_foo = penv_xmm->en_foo;
2238 penv_87->en_fos = penv_xmm->en_fos;
2241 for (i = 0; i < 8; ++i)
2242 sv_87->sv_ac[i] = sv_xmm->sv_fp[i].fp_acc;
2246 set_fpregs_xmm(struct save87 *sv_87, struct savexmm *sv_xmm)
2248 struct env87 *penv_87 = &sv_87->sv_env;
2249 struct envxmm *penv_xmm = &sv_xmm->sv_env;
2252 /* FPU control/status */
2253 penv_xmm->en_cw = penv_87->en_cw;
2254 penv_xmm->en_sw = penv_87->en_sw;
2255 penv_xmm->en_tw = penv_87->en_tw;
2256 penv_xmm->en_fip = penv_87->en_fip;
2257 penv_xmm->en_fcs = penv_87->en_fcs;
2258 penv_xmm->en_opcode = penv_87->en_opcode;
2259 penv_xmm->en_foo = penv_87->en_foo;
2260 penv_xmm->en_fos = penv_87->en_fos;
2263 for (i = 0; i < 8; ++i)
2264 sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i];
2266 #endif /* CPU_DISABLE_SSE */
2269 fill_fpregs(struct lwp *lp, struct fpreg *fpregs)
2271 if (lp->lwp_thread == NULL || lp->lwp_thread->td_pcb == NULL)
2273 #ifndef CPU_DISABLE_SSE
2275 fill_fpregs_xmm(&lp->lwp_thread->td_pcb->pcb_save.sv_xmm,
2276 (struct save87 *)fpregs);
2279 #endif /* CPU_DISABLE_SSE */
2280 bcopy(&lp->lwp_thread->td_pcb->pcb_save.sv_87, fpregs, sizeof *fpregs);
2285 set_fpregs(struct lwp *lp, struct fpreg *fpregs)
2287 #ifndef CPU_DISABLE_SSE
2289 set_fpregs_xmm((struct save87 *)fpregs,
2290 &lp->lwp_thread->td_pcb->pcb_save.sv_xmm);
2293 #endif /* CPU_DISABLE_SSE */
2294 bcopy(fpregs, &lp->lwp_thread->td_pcb->pcb_save.sv_87, sizeof *fpregs);
2299 fill_dbregs(struct lwp *lp, struct dbreg *dbregs)
2304 dbregs->dr[0] = rdr0();
2305 dbregs->dr[1] = rdr1();
2306 dbregs->dr[2] = rdr2();
2307 dbregs->dr[3] = rdr3();
2308 dbregs->dr[4] = rdr4();
2309 dbregs->dr[5] = rdr5();
2310 dbregs->dr[6] = rdr6();
2311 dbregs->dr[7] = rdr7();
2314 if (lp->lwp_thread == NULL || (pcb = lp->lwp_thread->td_pcb) == NULL)
2316 dbregs->dr[0] = pcb->pcb_dr0;
2317 dbregs->dr[1] = pcb->pcb_dr1;
2318 dbregs->dr[2] = pcb->pcb_dr2;
2319 dbregs->dr[3] = pcb->pcb_dr3;
2322 dbregs->dr[6] = pcb->pcb_dr6;
2323 dbregs->dr[7] = pcb->pcb_dr7;
2328 set_dbregs(struct lwp *lp, struct dbreg *dbregs)
2331 load_dr0(dbregs->dr[0]);
2332 load_dr1(dbregs->dr[1]);
2333 load_dr2(dbregs->dr[2]);
2334 load_dr3(dbregs->dr[3]);
2335 load_dr4(dbregs->dr[4]);
2336 load_dr5(dbregs->dr[5]);
2337 load_dr6(dbregs->dr[6]);
2338 load_dr7(dbregs->dr[7]);
2341 struct ucred *ucred;
2343 uint64_t mask1, mask2;
2346 * Don't let an illegal value for dr7 get set. Specifically,
2347 * check for undefined settings. Setting these bit patterns
2348 * result in undefined behaviour and can lead to an unexpected
2351 /* JG this loop looks unreadable */
2352 /* Check 4 2-bit fields for invalid patterns.
2353 * These fields are R/Wi, for i = 0..3
2355 /* Is 10 in LENi allowed when running in compatibility mode? */
2356 /* Pattern 10 in R/Wi might be used to indicate
2357 * breakpoint on I/O. Further analysis should be
2358 * carried to decide if it is safe and useful to
2359 * provide access to that capability
2361 for (i = 0, mask1 = 0x3<<16, mask2 = 0x2<<16; i < 4;
2362 i++, mask1 <<= 4, mask2 <<= 4)
2363 if ((dbregs->dr[7] & mask1) == mask2)
2366 pcb = lp->lwp_thread->td_pcb;
2367 ucred = lp->lwp_proc->p_ucred;
2370 * Don't let a process set a breakpoint that is not within the
2371 * process's address space. If a process could do this, it
2372 * could halt the system by setting a breakpoint in the kernel
2373 * (if ddb was enabled). Thus, we need to check to make sure
2374 * that no breakpoints are being enabled for addresses outside
2375 * process's address space, unless, perhaps, we were called by
2378 * XXX - what about when the watched area of the user's
2379 * address space is written into from within the kernel
2380 * ... wouldn't that still cause a breakpoint to be generated
2381 * from within kernel mode?
2384 if (priv_check_cred(ucred, PRIV_ROOT, 0) != 0) {
2385 if (dbregs->dr[7] & 0x3) {
2386 /* dr0 is enabled */
2387 if (dbregs->dr[0] >= VM_MAX_USER_ADDRESS)
2391 if (dbregs->dr[7] & (0x3<<2)) {
2392 /* dr1 is enabled */
2393 if (dbregs->dr[1] >= VM_MAX_USER_ADDRESS)
2397 if (dbregs->dr[7] & (0x3<<4)) {
2398 /* dr2 is enabled */
2399 if (dbregs->dr[2] >= VM_MAX_USER_ADDRESS)
2403 if (dbregs->dr[7] & (0x3<<6)) {
2404 /* dr3 is enabled */
2405 if (dbregs->dr[3] >= VM_MAX_USER_ADDRESS)
2410 pcb->pcb_dr0 = dbregs->dr[0];
2411 pcb->pcb_dr1 = dbregs->dr[1];
2412 pcb->pcb_dr2 = dbregs->dr[2];
2413 pcb->pcb_dr3 = dbregs->dr[3];
2414 pcb->pcb_dr6 = dbregs->dr[6];
2415 pcb->pcb_dr7 = dbregs->dr[7];
2417 pcb->pcb_flags |= PCB_DBREGS;
2424 * Return > 0 if a hardware breakpoint has been hit, and the
2425 * breakpoint was in user space. Return 0, otherwise.
2428 user_dbreg_trap(void)
2430 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */
2431 u_int64_t bp; /* breakpoint bits extracted from dr6 */
2432 int nbp; /* number of breakpoints that triggered */
2433 caddr_t addr[4]; /* breakpoint addresses */
2437 if ((dr7 & 0xff) == 0) {
2439 * all GE and LE bits in the dr7 register are zero,
2440 * thus the trap couldn't have been caused by the
2441 * hardware debug registers
2452 * None of the breakpoint bits are set meaning this
2453 * trap was not caused by any of the debug registers
2459 * at least one of the breakpoints were hit, check to see
2460 * which ones and if any of them are user space addresses
2464 addr[nbp++] = (caddr_t)rdr0();
2467 addr[nbp++] = (caddr_t)rdr1();
2470 addr[nbp++] = (caddr_t)rdr2();
2473 addr[nbp++] = (caddr_t)rdr3();
2476 for (i=0; i<nbp; i++) {
2478 (caddr_t)VM_MAX_USER_ADDRESS) {
2480 * addr[i] is in user space
2487 * None of the breakpoints are in user space.
2495 Debugger(const char *msg)
2497 kprintf("Debugger(\"%s\") called.\n", msg);
2504 * Provide inb() and outb() as functions. They are normally only
2505 * available as macros calling inlined functions, thus cannot be
2506 * called inside DDB.
2508 * The actual code is stolen from <machine/cpufunc.h>, and de-inlined.
2514 /* silence compiler warnings */
2516 void outb(u_int, u_char);
2523 * We use %%dx and not %1 here because i/o is done at %dx and not at
2524 * %edx, while gcc generates inferior code (movw instead of movl)
2525 * if we tell it to load (u_short) port.
2527 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port));
2532 outb(u_int port, u_char data)
2536 * Use an unnecessary assignment to help gcc's register allocator.
2537 * This make a large difference for gcc-1.40 and a tiny difference
2538 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for
2539 * best results. gcc-2.6.0 can't handle this.
2542 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port));
2550 * initialize all the SMP locks
2553 /* critical region when masking or unmasking interupts */
2554 struct spinlock_deprecated imen_spinlock;
2556 /* critical region for old style disable_intr/enable_intr */
2557 struct spinlock_deprecated mpintr_spinlock;
2559 /* critical region around INTR() routines */
2560 struct spinlock_deprecated intr_spinlock;
2562 /* lock region used by kernel profiling */
2563 struct spinlock_deprecated mcount_spinlock;
2565 /* locks com (tty) data/hardware accesses: a FASTINTR() */
2566 struct spinlock_deprecated com_spinlock;
2568 /* lock regions around the clock hardware */
2569 struct spinlock_deprecated clock_spinlock;
2575 * Get the initial mplock with a count of 1 for the BSP.
2576 * This uses a LOGICAL cpu ID, ie BSP == 0.
2578 cpu_get_initial_mplock();
2580 spin_lock_init(&mcount_spinlock);
2581 spin_lock_init(&intr_spinlock);
2582 spin_lock_init(&mpintr_spinlock);
2583 spin_lock_init(&imen_spinlock);
2584 spin_lock_init(&com_spinlock);
2585 spin_lock_init(&clock_spinlock);
2587 /* our token pool needs to work early */
2588 lwkt_token_pool_init();
2592 cpu_mwait_hint_valid(uint32_t hint)
2596 cx_idx = MWAIT_EAX_TO_CX(hint);
2597 if (cx_idx >= CPU_MWAIT_CX_MAX)
2600 sub = MWAIT_EAX_TO_CX_SUB(hint);
2601 if (sub >= cpu_mwait_cx_info[cx_idx].subcnt)
2608 cpu_mwait_cx_no_bmsts(void)
2610 atomic_clear_int(&cpu_mwait_c3_preamble, CPU_MWAIT_C3_PREAMBLE_BM_STS);
2614 cpu_mwait_cx_select_sysctl(SYSCTL_HANDLER_ARGS, int *hint0,
2615 boolean_t allow_auto)
2617 int error, cx_idx, old_cx_idx, sub = 0, hint;
2618 char name[16], *ptr, *start;
2622 old_cx_idx = MWAIT_EAX_TO_CX(hint);
2623 sub = MWAIT_EAX_TO_CX_SUB(hint);
2624 } else if (hint == CPU_MWAIT_HINT_AUTO) {
2625 old_cx_idx = allow_auto ? CPU_MWAIT_C2 : CPU_MWAIT_CX_MAX;
2626 } else if (hint == CPU_MWAIT_HINT_AUTODEEP) {
2627 old_cx_idx = allow_auto ? CPU_MWAIT_C3 : CPU_MWAIT_CX_MAX;
2629 old_cx_idx = CPU_MWAIT_CX_MAX;
2632 if ((cpu_feature2 & CPUID2_MON) == 0 ||
2633 (cpu_mwait_feature & CPUID_MWAIT_EXT) == 0)
2634 strlcpy(name, "NONE", sizeof(name));
2635 else if (allow_auto && hint == CPU_MWAIT_HINT_AUTO)
2636 strlcpy(name, "AUTO", sizeof(name));
2637 else if (allow_auto && hint == CPU_MWAIT_HINT_AUTODEEP)
2638 strlcpy(name, "AUTODEEP", sizeof(name));
2639 else if (old_cx_idx >= CPU_MWAIT_CX_MAX ||
2640 sub >= cpu_mwait_cx_info[old_cx_idx].subcnt)
2641 strlcpy(name, "INVALID", sizeof(name));
2643 ksnprintf(name, sizeof(name), "C%d/%d", old_cx_idx, sub);
2645 error = sysctl_handle_string(oidp, name, sizeof(name), req);
2646 if (error != 0 || req->newptr == NULL)
2649 if ((cpu_feature2 & CPUID2_MON) == 0 ||
2650 (cpu_mwait_feature & CPUID_MWAIT_EXT) == 0)
2653 if (allow_auto && strcmp(name, "AUTO") == 0) {
2654 hint = CPU_MWAIT_HINT_AUTO;
2655 cx_idx = CPU_MWAIT_C2;
2658 if (allow_auto && strcmp(name, "AUTODEEP") == 0) {
2659 hint = CPU_MWAIT_HINT_AUTODEEP;
2660 cx_idx = CPU_MWAIT_C3;
2664 if (strlen(name) < 4 || toupper(name[0]) != 'C')
2669 cx_idx = strtol(start, &ptr, 10);
2670 if (ptr == start || *ptr != '/')
2672 if (cx_idx < 0 || cx_idx >= CPU_MWAIT_CX_MAX)
2678 sub = strtol(start, &ptr, 10);
2681 if (sub < 0 || sub >= cpu_mwait_cx_info[cx_idx].subcnt)
2684 hint = MWAIT_EAX_HINT(cx_idx, sub);
2686 if (cx_idx >= CPU_MWAIT_C3 && cpu_mwait_c3_preamble)
2688 if (old_cx_idx < CPU_MWAIT_C3 && cx_idx >= CPU_MWAIT_C3) {
2689 error = cputimer_intr_powersave_addreq();
2692 } else if (old_cx_idx >= CPU_MWAIT_C3 && cx_idx < CPU_MWAIT_C3) {
2693 cputimer_intr_powersave_remreq();
2701 cpu_mwait_cx_idle_sysctl(SYSCTL_HANDLER_ARGS)
2705 lwkt_serialize_enter(&cpu_mwait_cx_slize);
2706 error = cpu_mwait_cx_select_sysctl(oidp, arg1, arg2, req,
2707 &cpu_mwait_halt, TRUE);
2708 lwkt_serialize_exit(&cpu_mwait_cx_slize);
2713 cpu_mwait_cx_spin_sysctl(SYSCTL_HANDLER_ARGS)
2717 lwkt_serialize_enter(&cpu_mwait_cx_slize);
2718 error = cpu_mwait_cx_select_sysctl(oidp, arg1, arg2, req,
2719 &cpu_mwait_spin, FALSE);
2720 lwkt_serialize_exit(&cpu_mwait_cx_slize);