sys/net/i4b/layer1/ifpi2/i4b_ifpi2_pci.c

   1 /*
   2  *   Copyright (c) 2001 Gary Jennejohn. All rights reserved.
   3  *
   4  *   Redistribution and use in source and binary forms, with or without
   5  *   modification, are permitted provided that the following conditions
   6  *   are met:
   7  *
   8  *   1. Redistributions of source code must retain the above copyright
   9  *      notice, this list of conditions and the following disclaimer.
  10  *   2. Redistributions in binary form must reproduce the above copyright
  11  *      notice, this list of conditions and the following disclaimer in the
  12  *      documentation and/or other materials provided with the distribution.
  13  *   3. Neither the name of the author nor the names of any co-contributors
  14  *      may be used to endorse or promote products derived from this software
  15  *      without specific prior written permission.
  16  *   4. Altered versions must be plainly marked as such, and must not be
  17  *      misrepresented as being the original software and/or documentation.
  18  *
  19  *   THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  20  *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  *   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  *   ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  23  *   FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  24  *   DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  25  *   OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  26  *   HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  27  *   LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  28  *   OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  29  *   SUCH DAMAGE.
  30  *
  31  *---------------------------------------------------------------------------
  32  *
  33  *      i4b_ifpi2_pci.c: AVM Fritz!Card PCI hardware driver
  34  *      --------------------------------------------------
  35  *
  36  *      $Id$
  37  *
  38  * $FreeBSD: src/sys/i4b/layer1/ifpi2/i4b_ifpi2_pci.c,v 1.6.2.2 2002/05/15 08:12:42 gj Exp $
  39  * $DragonFly: src/sys/net/i4b/layer1/ifpi2/i4b_ifpi2_pci.c,v 1.9 2005/06/03 16:50:02 dillon Exp $
  40  *
  41  *      last edit-date: [Fri Jan 12 17:01:26 2001]
  42  *
  43  *---------------------------------------------------------------------------*/
  44
  45 #include "use_ifpi2.h"
  46 #include "use_pci.h"
  47 #include "opt_i4b.h"
  48
  49 #if (NIFPI2 > 0) && (NPCI > 0)
  50
  51 #include <sys/param.h>
  52 #include <sys/kernel.h>
  53 #include <sys/systm.h>
  54 #include <sys/mbuf.h>
  55
  56 #include <machine/bus.h>
  57 #include <sys/bus.h>
  58 #include <sys/rman.h>
  59 #include <sys/thread2.h>
  60
  61 #include <bus/pci/pcireg.h>
  62 #include <bus/pci/pcivar.h>
  63
  64 #include <sys/socket.h>
  65 #include <net/if.h>
  66
  67 #include <net/i4b/include/machine/i4b_debug.h>
  68 #include <net/i4b/include/machine/i4b_ioctl.h>
  69 #include <net/i4b/include/machine/i4b_trace.h>
  70
  71 #include "../../include/i4b_global.h"
  72 #include "../../include/i4b_mbuf.h"
  73
  74 #include "../i4b_l1.h"
  75 #include "../isic/i4b_isic.h"
  76 /*#include "../isic/i4b_isac.h"*/
  77 #include "../isic/i4b_hscx.h"
  78
  79 #include "i4b_ifpi2_ext.h"
  80 #include "i4b_ifpi2_isacsx.h"
  81
  82 #define PCI_AVMA1_VID 0x1244
  83 #define PCI_AVMA1_V2_DID 0x0e00
  84
  85 /* prototypes */
  86 static void avma1pp2_disable(device_t);
  87
  88 static void avma1pp2_intr(void *);
  89 static void hscx_write_reg(int, u_int, struct l1_softc *);
  90 static u_char hscx_read_reg(int, struct l1_softc *);
  91 static u_int hscx_read_reg_int(int, struct l1_softc *);
  92 static void hscx_read_fifo(int, void *, size_t, struct l1_softc *);
  93 static void hscx_write_fifo(int, void *, size_t, struct l1_softc *);
  94 static void avma1pp2_hscx_int_handler(struct l1_softc *);
  95 static void avma1pp2_hscx_intr(int, u_int, struct l1_softc *);
  96 static void avma1pp2_init_linktab(struct l1_softc *);
  97 static void avma1pp2_bchannel_setup(int, int, int, int);
  98 static void avma1pp2_bchannel_start(int, int);
  99 static void avma1pp2_hscx_init(struct l1_softc *, int, int);
 100 static void avma1pp2_bchannel_stat(int, int, bchan_statistics_t *);
 101 static void avma1pp2_set_linktab(int, int, drvr_link_t *);
 102 static isdn_link_t * avma1pp2_ret_linktab(int, int);
 103 static int avma1pp2_pci_probe(device_t);
 104 static int avma1pp2_hscx_fifo(l1_bchan_state_t *, struct l1_softc *);
 105 int avma1pp2_attach_avma1pp(device_t);
 106 static void ifpi2_isacsx_intr(struct l1_softc *sc);
 107
 108 static device_method_t avma1pp2_pci_methods[] = {
 109         /* Device interface */
 110         DEVMETHOD(device_probe,         avma1pp2_pci_probe),
 111         DEVMETHOD(device_attach,        avma1pp2_attach_avma1pp),
 112         DEVMETHOD(device_shutdown,      avma1pp2_disable),
 113
 114         /* bus interface */
 115         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 116         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 117
 118         { 0, 0 }
 119 };
 120
 121 static driver_t avma1pp2_pci_driver = {
 122         "ifpi2-",
 123         avma1pp2_pci_methods,
 124         sizeof(struct l1_softc)
 125 };
 126
 127 static devclass_t avma1pp2_pci_devclass;
 128
 129 DRIVER_MODULE(avma1pp2, pci, avma1pp2_pci_driver, avma1pp2_pci_devclass, 0, 0);
 130
 131 /* jump table for multiplex routines */
 132
 133 struct i4b_l1mux_func avma1pp2_l1mux_func = {
 134         avma1pp2_ret_linktab,
 135         avma1pp2_set_linktab,
 136         ifpi2_mph_command_req,
 137         ifpi2_ph_data_req,
 138         ifpi2_ph_activate_req,
 139 };
 140
 141 struct l1_softc *ifpi2_scp[IFPI2_MAXUNIT];
 142
 143 /*---------------------------------------------------------------------------*
 144  *      AVM PCI Fritz!Card V. 2 special registers
 145  *---------------------------------------------------------------------------*/
 146
 147 /*
 148  *      AVM PCI Status Latch 0 read only bits
 149  */
 150 #define ASL_IRQ_ISAC            0x01    /* ISAC  interrupt, active high */
 151 #define ASL_IRQ_HSCX            0x02    /* HSX   interrupt, active high */
 152 #define ASL_IRQ_TIMER           0x04    /* Timer interrupt, active high */
 153 #define ASL_IRQ_BCHAN           ASL_IRQ_HSCX
 154 /* actually active high */
 155 #define ASL_IRQ_Pending         (ASL_IRQ_ISAC | ASL_IRQ_HSCX | ASL_IRQ_TIMER)
 156
 157 /*
 158  *      AVM PCI Status Latch 0 read only bits
 159  */
 160 #define ASL_TIMERRESET          0x04
 161 #define ASL_ENABLE_INT          0x08
 162
 163 /*
 164  * "HSCX" status bits
 165  */
 166 #define  HSCX_STAT_RME          0x01
 167 #define  HSCX_STAT_RDO          0x10
 168 #define  HSCX_STAT_CRCVFRRAB    0x0E
 169 #define  HSCX_STAT_CRCVFR       0x06
 170 #define  HSCX_STAT_RML_MASK     0x3f00
 171
 172 /*
 173  * "HSCX" interrupt bits
 174  */
 175 #define  HSCX_INT_XPR           0x80
 176 #define  HSCX_INT_XDU           0x40
 177 #define  HSCX_INT_RPR           0x20
 178 #define  HSCX_INT_MASK          0xE0
 179
 180 /*
 181  * "HSCX" command bits
 182  */
 183 #define  HSCX_CMD_XRS           0x80
 184 #define  HSCX_CMD_XME           0x01
 185 #define  HSCX_CMD_RRS           0x20
 186 #define  HSCX_CMD_XML_MASK      0x3f00
 187
 188 /* "HSCX" mode bits */
 189 #define HSCX_MODE_ITF_FLG       0x01
 190 #define HSCX_MODE_TRANS         0x02
 191
 192 /* offsets to various registers in the ASIC, evidently */
 193 #define  STAT0_OFFSET           0x02
 194
 195 #define  HSCX_FIFO1             0x10
 196 #define  HSCX_FIFO2             0x18
 197
 198 #define  HSCX_STAT1             0x14
 199 #define  HSCX_STAT2             0x1c
 200
 201 #define  ISACSX_INDEX           0x04
 202 #define  ISACSX_DATA            0x08
 203
 204 /*
 205  * Commands and parameters are sent to the "HSCX" as a long, but the
 206  * fields are handled as bytes.
 207  *
 208  * The long contains:
 209  *      (prot << 16)|(txl << 8)|cmd
 210  *
 211  * where:
 212  *      prot = protocol to use
 213  *      txl = transmit length
 214  *      cmd = the command to be executed
 215  *
 216  * The fields are defined as u_char in struct l1_softc.
 217  *
 218  * Macro to coalesce the byte fields into a u_int
 219  */
 220 #define AVMA1PPSETCMDLONG(f) (f) = ((sc->avma1pp_cmd) | (sc->avma1pp_txl << 8) \
 221                                         | (sc->avma1pp_prot << 16))
 222
 223 /*
 224  * to prevent deactivating the "HSCX" when both channels are active we
 225  * define an HSCX_ACTIVE flag which is or'd into the channel's state
 226  * flag in avma1pp2_bchannel_setup upon active and cleared upon deactivation.
 227  * It is set high to allow room for new flags.
 228  */
 229 #define HSCX_AVMA1PP_ACTIVE     0x1000
 230
 231 /*---------------------------------------------------------------------------*
 232  *      AVM read fifo routines
 233  *---------------------------------------------------------------------------*/
 234
 235 static void
 236 avma1pp2_read_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
 237 {
 238         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 239         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 240         int i;
 241
 242         switch (what) {
 243                 case ISIC_WHAT_ISAC:
 244                         bus_space_write_4(btag, bhandle, ISACSX_INDEX, 0);
 245                         /* evidently each byte must be read as a long */
 246                         for (i = 0; i < size; i++)
 247                                 ((u_int8_t *)buf)[i] = (u_int8_t)bus_space_read_4(btag, bhandle, ISACSX_DATA);
 248                         break;
 249                 case ISIC_WHAT_HSCXA:
 250                         hscx_read_fifo(0, buf, size, sc);
 251                         break;
 252                 case ISIC_WHAT_HSCXB:
 253                         hscx_read_fifo(1, buf, size, sc);
 254                         break;
 255         }
 256 }
 257
 258 static void
 259 hscx_read_fifo(int chan, void *buf, size_t len, struct l1_softc *sc)
 260 {
 261         u_int32_t *ip;
 262         size_t cnt;
 263         int dataoff;
 264         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 265         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 266
 267         dataoff = chan ? HSCX_FIFO2 : HSCX_FIFO1;
 268
 269         ip = (u_int32_t *)buf;
 270         cnt = 0;
 271         /* what if len isn't a multiple of sizeof(int) and buf is */
 272         /* too small ???? */
 273         while (cnt < len)
 274         {
 275                 *ip++ = bus_space_read_4(btag, bhandle, dataoff);
 276                 cnt += 4;
 277         }
 278 }
 279
 280 /*---------------------------------------------------------------------------*
 281  *      AVM write fifo routines
 282  *---------------------------------------------------------------------------*/
 283 static void
 284 avma1pp2_write_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
 285 {
 286         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 287         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 288         int i;
 289
 290         switch (what) {
 291                 case ISIC_WHAT_ISAC:
 292                         bus_space_write_4(btag, bhandle,  ISACSX_INDEX, 0);
 293                         /* evidently each byte must written as a long */
 294                         for (i = 0; i < size; i++)
 295                                 bus_space_write_4(btag, bhandle,  ISACSX_DATA, ((unsigned char *)buf)[i]);
 296                         break;
 297                 case ISIC_WHAT_HSCXA:
 298                         hscx_write_fifo(0, buf, size, sc);
 299                         break;
 300                 case ISIC_WHAT_HSCXB:
 301                         hscx_write_fifo(1, buf, size, sc);
 302                         break;
 303         }
 304 }
 305
 306 static void
 307 hscx_write_fifo(int chan, void *buf, size_t len, struct l1_softc *sc)
 308 {
 309         u_int32_t *ip;
 310         size_t cnt;
 311         int dataoff;
 312         l1_bchan_state_t *Bchan = &sc->sc_chan[chan];
 313         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 314         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 315
 316         dataoff = chan ? HSCX_FIFO2 : HSCX_FIFO1;
 317
 318         sc->avma1pp_cmd &= ~HSCX_CMD_XME;
 319         sc->avma1pp_txl = 0;
 320         if (Bchan->out_mbuf_cur == NULL)
 321         {
 322           if (Bchan->bprot != BPROT_NONE)
 323                  sc->avma1pp_cmd |= HSCX_CMD_XME;
 324         }
 325         if (len != sc->sc_bfifolen)
 326                 sc->avma1pp_txl = len;
 327
 328         cnt = 0; /* borrow cnt */
 329         AVMA1PPSETCMDLONG(cnt);
 330         hscx_write_reg(chan, cnt, sc);
 331
 332         ip = (u_int32_t *)buf;
 333         cnt = 0;
 334         while (cnt < len)
 335         {
 336                 bus_space_write_4(btag, bhandle, dataoff, *ip);
 337                 ip++;
 338                 cnt += 4;
 339         }
 340 }
 341
 342 /*---------------------------------------------------------------------------*
 343  *      AVM write register routines
 344  *---------------------------------------------------------------------------*/
 345
 346 static void
 347 avma1pp2_write_reg(struct l1_softc *sc, int what, bus_size_t offs, u_int8_t data)
 348 {
 349         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 350         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 351
 352         switch (what) {
 353                 case ISIC_WHAT_ISAC:
 354                         bus_space_write_4(btag, bhandle, ISACSX_INDEX, offs);
 355                         bus_space_write_4(btag, bhandle, ISACSX_DATA, data);
 356                         break;
 357                 case ISIC_WHAT_HSCXA:
 358                         hscx_write_reg(0, data, sc);
 359                         break;
 360                 case ISIC_WHAT_HSCXB:
 361                         hscx_write_reg(1, data, sc);
 362                         break;
 363         }
 364 }
 365
 366 static void
 367 hscx_write_reg(int chan, u_int val, struct l1_softc *sc)
 368 {
 369         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 370         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 371         u_int off;
 372
 373         off = (chan == 0 ? HSCX_STAT1 : HSCX_STAT2);
 374
 375         bus_space_write_4(btag, bhandle, off, val);
 376 }
 377
 378 /*---------------------------------------------------------------------------*
 379  *      AVM read register routines
 380  *---------------------------------------------------------------------------*/
 381 static u_int8_t
 382 avma1pp2_read_reg(struct l1_softc *sc, int what, bus_size_t offs)
 383 {
 384         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 385         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 386         u_int8_t val;
 387
 388         switch (what) {
 389                 case ISIC_WHAT_ISAC:
 390                         bus_space_write_4(btag, bhandle, ISACSX_INDEX, offs);
 391                         val = (u_int8_t)bus_space_read_4(btag, bhandle, ISACSX_DATA);
 392                         return(val);
 393                 case ISIC_WHAT_HSCXA:
 394                         return hscx_read_reg(0, sc);
 395                 case ISIC_WHAT_HSCXB:
 396                         return hscx_read_reg(1, sc);
 397         }
 398         return 0;
 399 }
 400
 401 static u_char
 402 hscx_read_reg(int chan, struct l1_softc *sc)
 403 {
 404         return(hscx_read_reg_int(chan, sc) & 0xff);
 405 }
 406
 407 /*
 408  * need to be able to return an int because the RBCH is in the 2nd
 409  * byte.
 410  */
 411 static u_int
 412 hscx_read_reg_int(int chan, struct l1_softc *sc)
 413 {
 414         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 415         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 416         u_int off;
 417
 418         off = (chan == 0 ? HSCX_STAT1 : HSCX_STAT2);
 419         return(bus_space_read_4(btag, bhandle, off));
 420 }
 421
 422 /*---------------------------------------------------------------------------*
 423  *      avma1pp2_probe - probe for a card
 424  *---------------------------------------------------------------------------*/
 425 static int
 426 avma1pp2_pci_probe(dev)
 427         device_t                dev;
 428 {
 429         u_int16_t               did, vid;
 430
 431         vid = pci_get_vendor(dev);
 432         did = pci_get_device(dev);
 433
 434         if ((vid == PCI_AVMA1_VID) && (did == PCI_AVMA1_V2_DID)) {
 435                 device_set_desc(dev, "AVM Fritz!Card PCI Version 2");
 436                 return(0);
 437         }
 438
 439         return(ENXIO);
 440 }
 441
 442 /*---------------------------------------------------------------------------*
 443  *      avma1pp2_attach_avma1pp - attach Fritz!Card PCI
 444  *---------------------------------------------------------------------------*/
 445 int
 446 avma1pp2_attach_avma1pp(device_t dev)
 447 {
 448         struct l1_softc *sc;
 449         u_int v;
 450         int unit, error = 0;
 451         u_int16_t did, vid;
 452         void *ih = 0;
 453         bus_space_handle_t bhandle;
 454         bus_space_tag_t btag;
 455 #if defined (__FreeBSD__) && __FreeBSD__ > 4
 456         l1_bchan_state_t *chan;
 457 #endif
 458
 459         crit_enter();
 460
 461         vid = pci_get_vendor(dev);
 462         did = pci_get_device(dev);
 463         sc = device_get_softc(dev);
 464         unit = device_get_unit(dev);
 465         bzero(sc, sizeof(struct l1_softc));
 466
 467         /* probably not really required */
 468         if(unit > IFPI2_MAXUNIT) {
 469                 printf("ifpi2-%d: Error, unit > IFPI_MAXUNIT!\n", unit);
 470                 crit_exit();
 471                 return(ENXIO);
 472         }
 473
 474         if ((vid != PCI_AVMA1_VID) && (did != PCI_AVMA1_V2_DID)) {
 475                 printf("ifpi2-%d: unknown device!?\n", unit);
 476                 goto fail;
 477         }
 478
 479         ifpi2_scp[unit] = sc;
 480
 481         sc->sc_resources.io_rid[0] = PCIR_MAPS+4;
 482         sc->sc_resources.io_base[0] = bus_alloc_resource(dev, SYS_RES_IOPORT,
 483                 &sc->sc_resources.io_rid[0],
 484                 0, ~0, 1, RF_ACTIVE);
 485
 486         if (sc->sc_resources.io_base[0] == NULL) {
 487                 printf("ifpi2-%d: couldn't map IO port\n", unit);
 488                 error = ENXIO;
 489                 goto fail;
 490         }
 491
 492         bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 493         btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 494
 495         /* Allocate interrupt */
 496         sc->sc_resources.irq_rid = 0;
 497         sc->sc_resources.irq = bus_alloc_resource(dev, SYS_RES_IRQ,
 498                 &sc->sc_resources.irq_rid, 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE);
 499
 500         if (sc->sc_resources.irq == NULL) {
 501                 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS+4, sc->sc_resources.io_base[0]);
 502                 printf("ifpi2-%d: couldn't map interrupt\n", unit);
 503                 error = ENXIO;
 504                 goto fail;
 505         }
 506
 507         error = bus_setup_intr(dev, sc->sc_resources.irq, INTR_TYPE_NET,
 508                                avma1pp2_intr, sc, &ih, NULL);
 509
 510         if (error) {
 511                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_resources.irq);
 512                 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS+4, sc->sc_resources.io_base[0]);
 513                 printf("ifpi2-%d: couldn't set up irq\n", unit);
 514                 goto fail;
 515         }
 516
 517         sc->sc_unit = unit;
 518
 519         /* end of new-bus stuff */
 520
 521         ISAC_BASE = (caddr_t)ISIC_WHAT_ISAC;
 522
 523         HSCX_A_BASE = (caddr_t)ISIC_WHAT_HSCXA;
 524         HSCX_B_BASE = (caddr_t)ISIC_WHAT_HSCXB;
 525
 526         /* setup access routines */
 527
 528         sc->clearirq = NULL;
 529         sc->readreg = avma1pp2_read_reg;
 530         sc->writereg = avma1pp2_write_reg;
 531
 532         sc->readfifo = avma1pp2_read_fifo;
 533         sc->writefifo = avma1pp2_write_fifo;
 534
 535         /* setup card type */
 536
 537         sc->sc_cardtyp = CARD_TYPEP_AVMA1PCI_V2;
 538
 539         /* setup IOM bus type */
 540
 541         sc->sc_bustyp = BUS_TYPE_IOM2;
 542
 543         /* set up some other miscellaneous things */
 544         sc->sc_ipac = 0;
 545         sc->sc_bfifolen = HSCX_FIFO_LEN;
 546
 547         /* reset the card */
 548         /* the Linux driver does this to clear any pending ISAC interrupts */
 549         v = 0;
 550         v = ISAC_READ(I_RMODED);
 551 #ifdef AVMA1PCI_V2_DEBUG
 552         printf("avma1pp2_attach: I_MODED %x...", v);
 553 #endif
 554         v = ISAC_READ(I_ISTAD);
 555 #ifdef AVMA1PCI_V2_DEBUG
 556         printf("avma1pp2_attach: I_ISTAD %x...", v);
 557 #endif
 558         v = ISAC_READ(I_ISTA);
 559 #ifdef AVMA1PCI_V2_DEBUG
 560         printf("avma1pp2_attach: I_ISTA %x...", v);
 561 #endif
 562         ISAC_WRITE(I_MASKD, 0xff);
 563         ISAC_WRITE(I_MASK, 0xff);
 564         /* the Linux driver does this to clear any pending HSCX interrupts */
 565         v = hscx_read_reg_int(0, sc);
 566 #ifdef AVMA1PCI_V2_DEBUG
 567         printf("avma1pp2_attach: 0 HSCX_STAT %x...", v);
 568 #endif
 569         v = hscx_read_reg_int(1, sc);
 570 #ifdef AVMA1PCI_V2_DEBUG
 571         printf("avma1pp2_attach: 1 HSCX_STAT %x\n", v);
 572 #endif
 573
 574         bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_TIMERRESET);
 575         DELAY(SEC_DELAY/100); /* 10 ms */
 576         bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_ENABLE_INT);
 577         DELAY(SEC_DELAY/100); /* 10 ms */
 578
 579    /* from here to the end would normally be done in isic_pciattach */
 580
 581          printf("ifpi2-%d: ISACSX %s\n", unit, "PSB3186");
 582
 583         /* init the ISAC */
 584         ifpi2_isacsx_init(sc);
 585
 586 #if defined (__FreeBSD__) && __FreeBSD__ > 4
 587         /* Init the channel mutexes */
 588         chan = &sc->sc_chan[HSCX_CH_A];
 589         mtx_init(&chan->rx_queue.ifq_mtx, "i4b_avma1pp2_rx", MTX_DEF);
 590         mtx_init(&chan->tx_queue.ifq_mtx, "i4b_avma1pp2_tx", MTX_DEF);
 591         chan = &sc->sc_chan[HSCX_CH_B];
 592         mtx_init(&chan->rx_queue.ifq_mtx, "i4b_avma1pp2_rx", MTX_DEF);
 593         mtx_init(&chan->tx_queue.ifq_mtx, "i4b_avma1pp2_tx", MTX_DEF);
 594 #endif
 595
 596         /* init the "HSCX" */
 597         avma1pp2_bchannel_setup(sc->sc_unit, HSCX_CH_A, BPROT_NONE, 0);
 598
 599         avma1pp2_bchannel_setup(sc->sc_unit, HSCX_CH_B, BPROT_NONE, 0);
 600
 601         /* can't use the normal B-Channel stuff */
 602         avma1pp2_init_linktab(sc);
 603
 604         /* set trace level */
 605
 606         sc->sc_trace = TRACE_OFF;
 607
 608         sc->sc_state = ISAC_IDLE;
 609
 610         sc->sc_ibuf = NULL;
 611         sc->sc_ib = NULL;
 612         sc->sc_ilen = 0;
 613
 614         sc->sc_obuf = NULL;
 615         sc->sc_op = NULL;
 616         sc->sc_ol = 0;
 617         sc->sc_freeflag = 0;
 618
 619         sc->sc_obuf2 = NULL;
 620         sc->sc_freeflag2 = 0;
 621
 622         callout_init(&sc->sc_T3_timeout);
 623         callout_init(&sc->sc_T4_timeout);
 624
 625         /* init higher protocol layers */
 626
 627         i4b_l1_mph_status_ind(L0IFPI2UNIT(sc->sc_unit), STI_ATTACH, sc->sc_cardtyp, &avma1pp2_l1mux_func);
 628
 629   fail:
 630         crit_exit();
 631         return(error);
 632 }
 633
 634 /*
 635  * this is the real interrupt routine
 636  */
 637 static void
 638 avma1pp2_hscx_intr(int h_chan, u_int stat, struct l1_softc *sc)
 639 {
 640         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
 641         int activity = -1;
 642         u_int param = 0;
 643
 644         NDBGL1(L1_H_IRQ, "%#x", stat);
 645
 646         if((stat & HSCX_INT_XDU) && (chan->bprot != BPROT_NONE))/* xmit data underrun */
 647         {
 648                 chan->stat_XDU++;
 649                 NDBGL1(L1_H_XFRERR, "xmit data underrun");
 650                 /* abort the transmission */
 651                 sc->avma1pp_txl = 0;
 652                 sc->avma1pp_cmd |= HSCX_CMD_XRS;
 653                 AVMA1PPSETCMDLONG(param);
 654                 hscx_write_reg(h_chan, param, sc);
 655                 sc->avma1pp_cmd &= ~HSCX_CMD_XRS;
 656                 AVMA1PPSETCMDLONG(param);
 657                 hscx_write_reg(h_chan, param, sc);
 658
 659                 if (chan->out_mbuf_head != NULL)  /* don't continue to transmit this buffer */
 660                 {
 661                         i4b_Bfreembuf(chan->out_mbuf_head);
 662                         chan->out_mbuf_cur = chan->out_mbuf_head = NULL;
 663                 }
 664         }
 665
 666         /*
 667          * The following is based on examination of the Linux driver.
 668          *
 669          * The logic here is different than with a "real" HSCX; all kinds
 670          * of information (interrupt/status bits) are in stat.
 671          *              HSCX_INT_RPR indicates a receive interrupt
 672          *                      HSCX_STAT_RDO indicates an overrun condition, abort -
 673          *                      otherwise read the bytes ((stat & HSCX_STZT_RML_MASK) >> 8)
 674          *                      HSCX_STAT_RME indicates end-of-frame and apparently any
 675          *                      CRC/framing errors are only reported in this state.
 676          *                              if ((stat & HSCX_STAT_CRCVFRRAB) != HSCX_STAT_CRCVFR)
 677          *                                      CRC/framing error
 678          */
 679
 680         if(stat & HSCX_INT_RPR)
 681         {
 682                 int fifo_data_len;
 683                 int error = 0;
 684                 /* always have to read the FIFO, so use a scratch buffer */
 685                 u_char scrbuf[HSCX_FIFO_LEN];
 686
 687                 if(stat & HSCX_STAT_RDO)
 688                 {
 689                         chan->stat_RDO++;
 690                         NDBGL1(L1_H_XFRERR, "receive data overflow");
 691                         error++;
 692                 }
 693
 694                 /*
 695                  * check whether we're receiving data for an inactive B-channel
 696                  * and discard it. This appears to happen for telephony when
 697                  * both B-channels are active and one is deactivated. Since
 698                  * it is not really possible to deactivate the channel in that
 699                  * case (the ASIC seems to deactivate _both_ channels), the
 700                  * "deactivated" channel keeps receiving data which can lead
 701                  * to exhaustion of mbufs and a kernel panic.
 702                  *
 703                  * This is a hack, but it's the only solution I can think of
 704                  * without having the documentation for the ASIC.
 705                  * GJ - 28 Nov 1999
 706                  */
 707                  if (chan->state == HSCX_IDLE)
 708                  {
 709                         NDBGL1(L1_H_XFRERR, "toss data from %d", h_chan);
 710                         error++;
 711                  }
 712
 713                 fifo_data_len = ((stat & HSCX_STAT_RML_MASK) >> 8);
 714
 715                 if(fifo_data_len == 0)
 716                         fifo_data_len = sc->sc_bfifolen;
 717
 718                 /* ALWAYS read data from HSCX fifo */
 719
 720                 HSCX_RDFIFO(h_chan, scrbuf, fifo_data_len);
 721                 chan->rxcount += fifo_data_len;
 722
 723                 /* all error conditions checked, now decide and take action */
 724
 725                 if(error == 0)
 726                 {
 727                         if(chan->in_mbuf == NULL)
 728                         {
 729                                 if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
 730                                         panic("L1 avma1pp2_hscx_intr: RME, cannot allocate mbuf!\n");
 731                                 chan->in_cbptr = chan->in_mbuf->m_data;
 732                                 chan->in_len = 0;
 733                         }
 734
 735                         if((chan->in_len + fifo_data_len) <= BCH_MAX_DATALEN)
 736                         {
 737                                 /* OK to copy the data */
 738                                 bcopy(scrbuf, chan->in_cbptr, fifo_data_len);
 739                                 chan->in_cbptr += fifo_data_len;
 740                                 chan->in_len += fifo_data_len;
 741
 742                                 /* setup mbuf data length */
 743
 744                                 chan->in_mbuf->m_len = chan->in_len;
 745                                 chan->in_mbuf->m_pkthdr.len = chan->in_len;
 746
 747                                 if(sc->sc_trace & TRACE_B_RX)
 748                                 {
 749                                         i4b_trace_hdr_t hdr;
 750                                         hdr.unit = L0IFPI2UNIT(sc->sc_unit);
 751                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 752                                         hdr.dir = FROM_NT;
 753                                         hdr.count = ++sc->sc_trace_bcount;
 754                                         MICROTIME(hdr.time);
 755                                         i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
 756                                 }
 757
 758                                 if (stat & HSCX_STAT_RME)
 759                                 {
 760                                   if((stat & HSCX_STAT_CRCVFRRAB) == HSCX_STAT_CRCVFR)
 761                                   {
 762                                          (*chan->isic_drvr_linktab->bch_rx_data_ready)(chan->isic_drvr_linktab->unit);
 763                                          activity = ACT_RX;
 764
 765                                          /* mark buffer ptr as unused */
 766
 767                                          chan->in_mbuf = NULL;
 768                                          chan->in_cbptr = NULL;
 769                                          chan->in_len = 0;
 770                                   }
 771                                   else
 772                                   {
 773                                                 chan->stat_CRC++;
 774                                                 NDBGL1(L1_H_XFRERR, "CRC/RAB");
 775                                           if (chan->in_mbuf != NULL)
 776                                           {
 777                                                   i4b_Bfreembuf(chan->in_mbuf);
 778                                                   chan->in_mbuf = NULL;
 779                                                   chan->in_cbptr = NULL;
 780                                                   chan->in_len = 0;
 781                                           }
 782                                   }
 783                                 }
 784                         } /* END enough space in mbuf */
 785                         else
 786                         {
 787                                  if(chan->bprot == BPROT_NONE)
 788                                  {
 789                                           /* setup mbuf data length */
 790
 791                                           chan->in_mbuf->m_len = chan->in_len;
 792                                           chan->in_mbuf->m_pkthdr.len = chan->in_len;
 793
 794                                           if(sc->sc_trace & TRACE_B_RX)
 795                                           {
 796                                                         i4b_trace_hdr_t hdr;
 797                                                         hdr.unit = L0IFPI2UNIT(sc->sc_unit);
 798                                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 799                                                         hdr.dir = FROM_NT;
 800                                                         hdr.count = ++sc->sc_trace_bcount;
 801                                                         MICROTIME(hdr.time);
 802                                                         i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
 803                                                 }
 804
 805                                           if(!(i4b_l1_bchan_tel_silence(chan->in_mbuf->m_data, chan->in_mbuf->m_len)))
 806                                                  activity = ACT_RX;
 807
 808                                           /* move rx'd data to rx queue */
 809
 810 #if defined (__FreeBSD__) && __FreeBSD__ > 4
 811                                           (void) IF_HANDOFF(&chan->rx_queue, chan->in_mbuf, NULL);
 812 #else
 813                                           if(!(IF_QFULL(&chan->rx_queue)))
 814                                           {
 815                                                 IF_ENQUEUE(&chan->rx_queue, chan->in_mbuf);
 816                                           }
 817                                           else
 818                                           {
 819                                                 i4b_Bfreembuf(chan->in_mbuf);
 820                                           }
 821 #endif
 822                                           /* signal upper layer that data are available */
 823                                           (*chan->isic_drvr_linktab->bch_rx_data_ready)(chan->isic_drvr_linktab->unit);
 824
 825                                           /* alloc new buffer */
 826
 827                                           if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
 828                                                  panic("L1 avma1pp2_hscx_intr: RPF, cannot allocate new mbuf!\n");
 829
 830                                           /* setup new data ptr */
 831
 832                                           chan->in_cbptr = chan->in_mbuf->m_data;
 833
 834                                           /* OK to copy the data */
 835                                           bcopy(scrbuf, chan->in_cbptr, fifo_data_len);
 836
 837                                           chan->in_cbptr += fifo_data_len;
 838                                           chan->in_len = fifo_data_len;
 839
 840                                           chan->rxcount += fifo_data_len;
 841                                         }
 842                                  else
 843                                         {
 844                                           NDBGL1(L1_H_XFRERR, "RAWHDLC rx buffer overflow in RPF, in_len=%d", chan->in_len);
 845                                           chan->in_cbptr = chan->in_mbuf->m_data;
 846                                           chan->in_len = 0;
 847                                         }
 848                           }
 849                 } /* if(error == 0) */
 850                 else
 851                 {
 852                         /* land here for RDO */
 853                         if (chan->in_mbuf != NULL)
 854                         {
 855                                 i4b_Bfreembuf(chan->in_mbuf);
 856                                 chan->in_mbuf = NULL;
 857                                 chan->in_cbptr = NULL;
 858                                 chan->in_len = 0;
 859                         }
 860                         sc->avma1pp_txl = 0;
 861                         sc->avma1pp_cmd |= HSCX_CMD_RRS;
 862                         AVMA1PPSETCMDLONG(param);
 863                         hscx_write_reg(h_chan, param, sc);
 864                         sc->avma1pp_cmd &= ~HSCX_CMD_RRS;
 865                         AVMA1PPSETCMDLONG(param);
 866                         hscx_write_reg(h_chan, param, sc);
 867                 }
 868         }
 869
 870
 871         /* transmit fifo empty, new data can be written to fifo */
 872
 873         if(stat & HSCX_INT_XPR)
 874         {
 875                 /*
 876                  * for a description what is going on here, please have
 877                  * a look at isic_bchannel_start() in i4b_bchan.c !
 878                  */
 879
 880                 NDBGL1(L1_H_IRQ, "unit %d, chan %d - XPR, Tx Fifo Empty!", sc->sc_unit, h_chan);
 881
 882                 if(chan->out_mbuf_cur == NULL)  /* last frame is transmitted */
 883                 {
 884                         IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
 885
 886                         if(chan->out_mbuf_head == NULL)
 887                         {
 888                                 chan->state &= ~HSCX_TX_ACTIVE;
 889                                 (*chan->isic_drvr_linktab->bch_tx_queue_empty)(chan->isic_drvr_linktab->unit);
 890                         }
 891                         else
 892                         {
 893                                 chan->state |= HSCX_TX_ACTIVE;
 894                                 chan->out_mbuf_cur = chan->out_mbuf_head;
 895                                 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
 896                                 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
 897
 898                                 if(sc->sc_trace & TRACE_B_TX)
 899                                 {
 900                                         i4b_trace_hdr_t hdr;
 901                                         hdr.unit = L0IFPI2UNIT(sc->sc_unit);
 902                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 903                                         hdr.dir = FROM_TE;
 904                                         hdr.count = ++sc->sc_trace_bcount;
 905                                         MICROTIME(hdr.time);
 906                                         i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
 907                                 }
 908
 909                                 if(chan->bprot == BPROT_NONE)
 910                                 {
 911                                         if(!(i4b_l1_bchan_tel_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
 912                                                 activity = ACT_TX;
 913                                 }
 914                                 else
 915                                 {
 916                                         activity = ACT_TX;
 917                                 }
 918                         }
 919                 }
 920
 921                 avma1pp2_hscx_fifo(chan, sc);
 922         }
 923
 924         /* call timeout handling routine */
 925
 926         if(activity == ACT_RX || activity == ACT_TX)
 927                 (*chan->isic_drvr_linktab->bch_activity)(chan->isic_drvr_linktab->unit, activity);
 928 }
 929
 930 /*
 931  * this is the main routine which checks each channel and then calls
 932  * the real interrupt routine as appropriate
 933  */
 934 static void
 935 avma1pp2_hscx_int_handler(struct l1_softc *sc)
 936 {
 937         u_int stat;
 938
 939         /* has to be a u_int because the byte count is in the 2nd byte */
 940         stat = hscx_read_reg_int(0, sc);
 941         if (stat & HSCX_INT_MASK)
 942           avma1pp2_hscx_intr(0, stat, sc);
 943         stat = hscx_read_reg_int(1, sc);
 944         if (stat & HSCX_INT_MASK)
 945           avma1pp2_hscx_intr(1, stat, sc);
 946 }
 947
 948 static void
 949 avma1pp2_disable(device_t dev)
 950 {
 951         struct l1_softc *sc = device_get_softc(dev);
 952         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 953         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 954
 955         /* could still be wrong, but it seems to help */
 956         bus_space_write_1(btag, bhandle, STAT0_OFFSET, 0x00);
 957 }
 958
 959 static void
 960 avma1pp2_intr(void *xsc)
 961 {
 962         u_char stat;
 963         struct l1_softc *sc;
 964         bus_space_handle_t bhandle;
 965         bus_space_tag_t btag;
 966
 967         sc = xsc;
 968         bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 969         btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 970
 971         stat = bus_space_read_1(btag, bhandle, STAT0_OFFSET);
 972         NDBGL1(L1_H_IRQ, "stat %x", stat);
 973         /* was there an interrupt from this card ? */
 974         if ((stat & ASL_IRQ_Pending) == 0)
 975                 return; /* no */
 976         /* For slow machines loop as long as an interrupt is active */
 977         for (; ((stat & ASL_IRQ_Pending) != 0) ;)
 978         {
 979                 /* interrupts are high active */
 980                 if (stat & ASL_IRQ_TIMER)
 981                         NDBGL1(L1_H_IRQ, "timer interrupt ???");
 982                 if (stat & ASL_IRQ_HSCX)
 983                 {
 984                         NDBGL1(L1_H_IRQ, "HSCX");
 985                         avma1pp2_hscx_int_handler(sc);
 986                 }
 987                 if (stat & ASL_IRQ_ISAC)
 988                 {
 989                        NDBGL1(L1_H_IRQ, "ISAC");
 990                        ifpi2_isacsx_intr(sc);
 991                 }
 992                 stat = bus_space_read_1(btag, bhandle, STAT0_OFFSET);
 993                 NDBGL1(L1_H_IRQ, "stat %x", stat);
 994
 995         }
 996 }
 997
 998 static void
 999 avma1pp2_hscx_init(struct l1_softc *sc, int h_chan, int activate)
1000 {
1001         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1002         u_int param = 0;
1003
1004         NDBGL1(L1_BCHAN, "unit=%d, channel=%d, %s",
1005                 sc->sc_unit, h_chan, activate ? "activate" : "deactivate");
1006
1007         sc->avma1pp_cmd = sc->avma1pp_prot = sc->avma1pp_txl = 0;
1008
1009         if (activate == 0)
1010         {
1011                 /* only deactivate if both channels are idle */
1012                 if (sc->sc_chan[HSCX_CH_A].state != HSCX_IDLE ||
1013                         sc->sc_chan[HSCX_CH_B].state != HSCX_IDLE)
1014                 {
1015                         return;
1016                 }
1017                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1018                 sc->avma1pp_prot = HSCX_MODE_TRANS;
1019                 AVMA1PPSETCMDLONG(param);
1020                 hscx_write_reg(h_chan, param, sc);
1021                 return;
1022         }
1023         if(chan->bprot == BPROT_RHDLC)
1024         {
1025                   NDBGL1(L1_BCHAN, "BPROT_RHDLC");
1026
1027                 /* HDLC Frames, transparent mode 0 */
1028                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1029                 sc->avma1pp_prot = HSCX_MODE_ITF_FLG;
1030                 AVMA1PPSETCMDLONG(param);
1031                 hscx_write_reg(h_chan, param, sc);
1032                 sc->avma1pp_cmd = HSCX_CMD_XRS;
1033                 AVMA1PPSETCMDLONG(param);
1034                 hscx_write_reg(h_chan, param, sc);
1035                 sc->avma1pp_cmd = 0;
1036         }
1037         else
1038         {
1039                   NDBGL1(L1_BCHAN, "BPROT_NONE??");
1040
1041                 /* Raw Telephony, extended transparent mode 1 */
1042                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1043                 sc->avma1pp_prot = HSCX_MODE_TRANS;
1044                 AVMA1PPSETCMDLONG(param);
1045                 hscx_write_reg(h_chan, param, sc);
1046                 sc->avma1pp_cmd = HSCX_CMD_XRS;
1047                 AVMA1PPSETCMDLONG(param);
1048                 hscx_write_reg(h_chan, param, sc);
1049                 sc->avma1pp_cmd = 0;
1050         }
1051 }
1052
1053 static void
1054 avma1pp2_bchannel_setup(int unit, int h_chan, int bprot, int activate)
1055 {
1056 #if defined(__DragonFly__) || defined(__FreeBSD__)
1057         struct l1_softc *sc = ifpi2_scp[unit];
1058 #else
1059         struct l1_softc *sc = isic_find_sc(unit);
1060 #endif
1061         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1062
1063         crit_enter();
1064
1065         if(activate == 0)
1066         {
1067                 /* deactivation */
1068                 chan->state = HSCX_IDLE;
1069                 avma1pp2_hscx_init(sc, h_chan, activate);
1070         }
1071
1072         NDBGL1(L1_BCHAN, "unit=%d, channel=%d, %s",
1073                 sc->sc_unit, h_chan, activate ? "activate" : "deactivate");
1074
1075         /* general part */
1076
1077         chan->unit = sc->sc_unit;       /* unit number */
1078         chan->channel = h_chan;         /* B channel */
1079         chan->bprot = bprot;            /* B channel protocol */
1080         chan->state = HSCX_IDLE;        /* B channel state */
1081
1082         /* receiver part */
1083
1084         chan->rx_queue.ifq_maxlen = IFQ_MAXLEN;
1085
1086         i4b_Bcleanifq(&chan->rx_queue); /* clean rx queue */
1087
1088         chan->rxcount = 0;              /* reset rx counter */
1089
1090         i4b_Bfreembuf(chan->in_mbuf);   /* clean rx mbuf */
1091
1092         chan->in_mbuf = NULL;           /* reset mbuf ptr */
1093         chan->in_cbptr = NULL;          /* reset mbuf curr ptr */
1094         chan->in_len = 0;               /* reset mbuf data len */
1095
1096         /* transmitter part */
1097
1098         chan->tx_queue.ifq_maxlen = IFQ_MAXLEN;
1099
1100         i4b_Bcleanifq(&chan->tx_queue); /* clean tx queue */
1101
1102         chan->txcount = 0;              /* reset tx counter */
1103
1104         i4b_Bfreembuf(chan->out_mbuf_head);     /* clean tx mbuf */
1105
1106         chan->out_mbuf_head = NULL;     /* reset head mbuf ptr */
1107         chan->out_mbuf_cur = NULL;      /* reset current mbuf ptr */
1108         chan->out_mbuf_cur_ptr = NULL;  /* reset current mbuf data ptr */
1109         chan->out_mbuf_cur_len = 0;     /* reset current mbuf data cnt */
1110
1111         if(activate != 0)
1112         {
1113                 /* activation */
1114                 avma1pp2_hscx_init(sc, h_chan, activate);
1115                 chan->state |= HSCX_AVMA1PP_ACTIVE;
1116         }
1117
1118         crit_exit();
1119 }
1120
1121 static void
1122 avma1pp2_bchannel_start(int unit, int h_chan)
1123 {
1124 #if defined(__DragonFly__) || defined(__FreeBSD__)
1125         struct l1_softc *sc = ifpi2_scp[unit];
1126 #else
1127         struct l1_softc *sc = isic_find_sc(unit);
1128 #endif
1129         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1130         int activity = -1;
1131
1132         crit_enter();
1133         if(chan->state & HSCX_TX_ACTIVE)        /* already running ? */
1134         {
1135                 crit_exit();
1136                 return;                         /* yes, leave */
1137         }
1138
1139         /* get next mbuf from queue */
1140
1141         IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
1142
1143         if(chan->out_mbuf_head == NULL)         /* queue empty ? */
1144         {
1145                 crit_exit();
1146                 return;                         /* yes, exit */
1147         }
1148
1149         /* init current mbuf values */
1150
1151         chan->out_mbuf_cur = chan->out_mbuf_head;
1152         chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1153         chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1154
1155         /* activity indicator for timeout handling */
1156
1157         if(chan->bprot == BPROT_NONE)
1158         {
1159                 if(!(i4b_l1_bchan_tel_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
1160                         activity = ACT_TX;
1161         }
1162         else
1163         {
1164                 activity = ACT_TX;
1165         }
1166
1167         chan->state |= HSCX_TX_ACTIVE;          /* we start transmitting */
1168
1169         if(sc->sc_trace & TRACE_B_TX)   /* if trace, send mbuf to trace dev */
1170         {
1171                 i4b_trace_hdr_t hdr;
1172                 hdr.unit = L0IFPI2UNIT(sc->sc_unit);
1173                 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1174                 hdr.dir = FROM_TE;
1175                 hdr.count = ++sc->sc_trace_bcount;
1176                 MICROTIME(hdr.time);
1177                 i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1178         }
1179
1180         avma1pp2_hscx_fifo(chan, sc);
1181
1182         /* call timeout handling routine */
1183
1184         if(activity == ACT_RX || activity == ACT_TX)
1185                 (*chan->isic_drvr_linktab->bch_activity)(chan->isic_drvr_linktab->unit, activity);
1186
1187         crit_exit();
1188 }
1189
1190 /*---------------------------------------------------------------------------*
1191  *      return the address of isic drivers linktab
1192  *---------------------------------------------------------------------------*/
1193 static isdn_link_t *
1194 avma1pp2_ret_linktab(int unit, int channel)
1195 {
1196 #if defined(__DragonFly__) || defined(__FreeBSD__)
1197         struct l1_softc *sc = ifpi2_scp[unit];
1198 #else
1199         struct l1_softc *sc = isic_find_sc(unit);
1200 #endif
1201         l1_bchan_state_t *chan = &sc->sc_chan[channel];
1202
1203         return(&chan->isic_isdn_linktab);
1204 }
1205
1206 /*---------------------------------------------------------------------------*
1207  *      set the driver linktab in the b channel softc
1208  *---------------------------------------------------------------------------*/
1209 static void
1210 avma1pp2_set_linktab(int unit, int channel, drvr_link_t *dlt)
1211 {
1212 #if defined(__DragonFly__) || defined(__FreeBSD__)
1213         struct l1_softc *sc = ifpi2_scp[unit];
1214 #else
1215         struct l1_softc *sc = isic_find_sc(unit);
1216 #endif
1217         l1_bchan_state_t *chan = &sc->sc_chan[channel];
1218
1219         chan->isic_drvr_linktab = dlt;
1220 }
1221
1222
1223 /*---------------------------------------------------------------------------*
1224  *      initialize our local linktab
1225  *---------------------------------------------------------------------------*/
1226 static void
1227 avma1pp2_init_linktab(struct l1_softc *sc)
1228 {
1229         l1_bchan_state_t *chan = &sc->sc_chan[HSCX_CH_A];
1230         isdn_link_t *lt = &chan->isic_isdn_linktab;
1231
1232         /* make sure the hardware driver is known to layer 4 */
1233         /* avoid overwriting if already set */
1234         if (ctrl_types[CTRL_PASSIVE].set_linktab == NULL)
1235         {
1236                 ctrl_types[CTRL_PASSIVE].set_linktab = i4b_l1_set_linktab;
1237                 ctrl_types[CTRL_PASSIVE].get_linktab = i4b_l1_ret_linktab;
1238         }
1239
1240         /* local setup */
1241         lt->unit = sc->sc_unit;
1242         lt->channel = HSCX_CH_A;
1243         lt->bch_config = avma1pp2_bchannel_setup;
1244         lt->bch_tx_start = avma1pp2_bchannel_start;
1245         lt->bch_stat = avma1pp2_bchannel_stat;
1246         lt->tx_queue = &chan->tx_queue;
1247
1248         /* used by non-HDLC data transfers, i.e. telephony drivers */
1249         lt->rx_queue = &chan->rx_queue;
1250
1251         /* used by HDLC data transfers, i.e. ipr and isp drivers */
1252         lt->rx_mbuf = &chan->in_mbuf;
1253
1254         chan = &sc->sc_chan[HSCX_CH_B];
1255         lt = &chan->isic_isdn_linktab;
1256
1257         lt->unit = sc->sc_unit;
1258         lt->channel = HSCX_CH_B;
1259         lt->bch_config = avma1pp2_bchannel_setup;
1260         lt->bch_tx_start = avma1pp2_bchannel_start;
1261         lt->bch_stat = avma1pp2_bchannel_stat;
1262         lt->tx_queue = &chan->tx_queue;
1263
1264         /* used by non-HDLC data transfers, i.e. telephony drivers */
1265         lt->rx_queue = &chan->rx_queue;
1266
1267         /* used by HDLC data transfers, i.e. ipr and isp drivers */
1268         lt->rx_mbuf = &chan->in_mbuf;
1269 }
1270
1271 /*
1272  * use this instead of isic_bchannel_stat in i4b_bchan.c because it's static
1273  */
1274 static void
1275 avma1pp2_bchannel_stat(int unit, int h_chan, bchan_statistics_t *bsp)
1276 {
1277 #if defined(__DragonFly__) || defined(__FreeBSD__)
1278         struct l1_softc *sc = ifpi2_scp[unit];
1279 #else
1280         struct l1_softc *sc = isic_find_sc(unit);
1281 #endif
1282         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1283
1284         crit_enter();
1285
1286         bsp->outbytes = chan->txcount;
1287         bsp->inbytes = chan->rxcount;
1288
1289         chan->txcount = 0;
1290         chan->rxcount = 0;
1291
1292         crit_exit();
1293 }
1294
1295 /*---------------------------------------------------------------------------*
1296  *      fill HSCX fifo with data from the current mbuf
1297  *      Put this here until it can go into i4b_hscx.c
1298  *---------------------------------------------------------------------------*/
1299 static int
1300 avma1pp2_hscx_fifo(l1_bchan_state_t *chan, struct l1_softc *sc)
1301 {
1302         int len;
1303         int nextlen;
1304         int i;
1305         int cmd = 0;
1306         /* using a scratch buffer simplifies writing to the FIFO */
1307         u_char scrbuf[HSCX_FIFO_LEN];
1308
1309         len = 0;
1310
1311         /*
1312          * fill the HSCX tx fifo with data from the current mbuf. if
1313          * current mbuf holds less data than HSCX fifo length, try to
1314          * get the next mbuf from (a possible) mbuf chain. if there is
1315          * not enough data in a single mbuf or in a chain, then this
1316          * is the last mbuf and we tell the HSCX that it has to send
1317          * CRC and closing flag
1318          */
1319
1320         while(chan->out_mbuf_cur && len != sc->sc_bfifolen)
1321         {
1322                 nextlen = min(chan->out_mbuf_cur_len, sc->sc_bfifolen - len);
1323
1324 #ifdef NOTDEF
1325                 printf("i:mh=%p, mc=%p, mcp=%p, mcl=%d l=%d nl=%d # ",
1326                         chan->out_mbuf_head,
1327                         chan->out_mbuf_cur,
1328                         chan->out_mbuf_cur_ptr,
1329                         chan->out_mbuf_cur_len,
1330                         len,
1331                         nextlen);
1332 #endif
1333
1334                 cmd |= HSCX_CMDR_XTF;
1335                 /* collect the data in the scratch buffer */
1336                 for (i = 0; i < nextlen; i++)
1337                         scrbuf[i + len] = chan->out_mbuf_cur_ptr[i];
1338
1339                 len += nextlen;
1340                 chan->txcount += nextlen;
1341
1342                 chan->out_mbuf_cur_ptr += nextlen;
1343                 chan->out_mbuf_cur_len -= nextlen;
1344
1345                 if(chan->out_mbuf_cur_len == 0)
1346                 {
1347                         if((chan->out_mbuf_cur = chan->out_mbuf_cur->m_next) != NULL)
1348                         {
1349                                 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1350                                 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1351
1352                                 if(sc->sc_trace & TRACE_B_TX)
1353                                 {
1354                                         i4b_trace_hdr_t hdr;
1355                                         hdr.unit = L0IFPI2UNIT(sc->sc_unit);
1356                                         hdr.type = (chan->channel == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1357                                         hdr.dir = FROM_TE;
1358                                         hdr.count = ++sc->sc_trace_bcount;
1359                                         MICROTIME(hdr.time);
1360                                         i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1361                                 }
1362                         }
1363                         else
1364                         {
1365                                 if (chan->bprot != BPROT_NONE)
1366                                         cmd |= HSCX_CMDR_XME;
1367                                 i4b_Bfreembuf(chan->out_mbuf_head);
1368                                 chan->out_mbuf_head = NULL;
1369                         }
1370                 }
1371         }
1372         /* write what we have from the scratch buf to the HSCX fifo */
1373         if (len != 0)
1374                 HSCX_WRFIFO(chan->channel, scrbuf, len);
1375         return(cmd);
1376 }
1377
1378 /*---------------------------------------------------------------------------*
1379  *      ifpi2 - ISAC interrupt routine
1380  *---------------------------------------------------------------------------*/
1381 static void
1382 ifpi2_isacsx_intr(struct l1_softc *sc)
1383 {
1384         u_char isacsx_irq_stat;
1385
1386         for(;;)
1387         {
1388                 /* get isac irq status */
1389                 /* ISTA tells us whether it was a C/I or HDLC int. */
1390                 isacsx_irq_stat = ISAC_READ(I_ISTA);
1391
1392                 if(isacsx_irq_stat)
1393                         ifpi2_isacsx_irq(sc, isacsx_irq_stat); /* isac handler */
1394                 else
1395                         break;
1396         }
1397
1398         ISAC_WRITE(I_MASKD, 0xff);
1399         ISAC_WRITE(I_MASK, 0xff);
1400
1401         DELAY(100);
1402
1403         ISAC_WRITE(I_MASKD, isacsx_imaskd);
1404         ISAC_WRITE(I_MASK, isacsx_imask);
1405 }
1406
1407 /*---------------------------------------------------------------------------*
1408  *      ifpi2_recover - try to recover from irq lockup
1409  *---------------------------------------------------------------------------*/
1410 void
1411 ifpi2_recover(struct l1_softc *sc)
1412 {
1413         printf("ifpi2_recover %d\n", sc->sc_unit);
1414 #if 0 /* fix me later */
1415         u_char byte;
1416
1417         /* get isac irq status */
1418
1419         byte = ISAC_READ(I_ISTA);
1420
1421         NDBGL1(L1_ERROR, "  ISAC: ISTA = 0x%x", byte);
1422
1423         if(byte & ISACSX_ISTA_EXI)
1424                 NDBGL1(L1_ERROR, "  ISAC: EXIR = 0x%x", (u_char)ISAC_READ(I_EXIR));
1425
1426         if(byte & ISACSX_ISTA_CISQ)
1427         {
1428                 byte = ISAC_READ(I_CIRR);
1429
1430                 NDBGL1(L1_ERROR, "  ISAC: CISQ = 0x%x", byte);
1431
1432                 if(byte & ISACSX_CIRR_SQC)
1433                         NDBGL1(L1_ERROR, "  ISAC: SQRR = 0x%x", (u_char)ISAC_READ(I_SQRR));
1434         }
1435
1436         NDBGL1(L1_ERROR, "  ISAC: IMASK = 0x%x", ISACSX_IMASK);
1437
1438         ISAC_WRITE(I_MASKD, 0xff);
1439         ISAC_WRITE(I_MASK, 0xff);
1440         DELAY(100);
1441         ISAC_WRITE(I_MASKD, isacsx_imaskd);
1442         ISAC_WRITE(I_MASK, isacsx_imask);
1443 #endif
1444 }
1445
1446
1447 #endif /* NIFPI2 > 0 */