2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2000, 2001
4 * Bill Paul <wpaul@bsdi.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
33 * $FreeBSD: src/sys/dev/nge/if_nge.c,v 1.13.2.13 2003/02/05 22:03:57 mbr Exp $
34 * $DragonFly: src/sys/dev/netif/nge/if_nge.c,v 1.15 2004/09/15 00:06:16 joerg Exp $
36 * $FreeBSD: src/sys/dev/nge/if_nge.c,v 1.13.2.13 2003/02/05 22:03:57 mbr Exp $
40 * National Semiconductor DP83820/DP83821 gigabit ethernet driver
41 * for FreeBSD. Datasheets are available from:
43 * http://www.national.com/ds/DP/DP83820.pdf
44 * http://www.national.com/ds/DP/DP83821.pdf
46 * These chips are used on several low cost gigabit ethernet NICs
47 * sold by D-Link, Addtron, SMC and Asante. Both parts are
48 * virtually the same, except the 83820 is a 64-bit/32-bit part,
49 * while the 83821 is 32-bit only.
51 * Many cards also use National gigE transceivers, such as the
52 * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet
53 * contains a full register description that applies to all of these
56 * http://www.national.com/ds/DP/DP83861.pdf
58 * Written by Bill Paul <wpaul@bsdi.com>
59 * BSDi Open Source Solutions
63 * The NatSemi DP83820 and 83821 controllers are enhanced versions
64 * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100
65 * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII
66 * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP
67 * hardware checksum offload (IPv4 only), VLAN tagging and filtering,
68 * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern
69 * matching buffers, one perfect address filter buffer and interrupt
70 * moderation. The 83820 supports both 64-bit and 32-bit addressing
71 * and data transfers: the 64-bit support can be toggled on or off
72 * via software. This affects the size of certain fields in the DMA
75 * There are two bugs/misfeatures in the 83820/83821 that I have
78 * - Receive buffers must be aligned on 64-bit boundaries, which means
79 * you must resort to copying data in order to fix up the payload
82 * - In order to transmit jumbo frames larger than 8170 bytes, you have
83 * to turn off transmit checksum offloading, because the chip can't
84 * compute the checksum on an outgoing frame unless it fits entirely
85 * within the TX FIFO, which is only 8192 bytes in size. If you have
86 * TX checksum offload enabled and you transmit attempt to transmit a
87 * frame larger than 8170 bytes, the transmitter will wedge.
89 * To work around the latter problem, TX checksum offload is disabled
90 * if the user selects an MTU larger than 8152 (8170 - 18).
93 #include <sys/param.h>
94 #include <sys/systm.h>
95 #include <sys/sockio.h>
97 #include <sys/malloc.h>
98 #include <sys/kernel.h>
99 #include <sys/socket.h>
102 #include <net/if_arp.h>
103 #include <net/ethernet.h>
104 #include <net/if_dl.h>
105 #include <net/if_media.h>
106 #include <net/if_types.h>
107 #include <net/vlan/if_vlan_var.h>
111 #include <vm/vm.h> /* for vtophys */
112 #include <vm/pmap.h> /* for vtophys */
113 #include <machine/clock.h> /* for DELAY */
114 #include <machine/bus_pio.h>
115 #include <machine/bus_memio.h>
116 #include <machine/bus.h>
117 #include <machine/resource.h>
119 #include <sys/rman.h>
121 #include "../mii_layer/mii.h"
122 #include "../mii_layer/miivar.h"
124 #include <bus/pci/pcireg.h>
125 #include <bus/pci/pcivar.h>
127 #define NGE_USEIOSPACE
129 #include "if_ngereg.h"
132 /* "controller miibus0" required. See GENERIC if you get errors here. */
133 #include "miibus_if.h"
135 #define NGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
138 * Various supported device vendors/types and their names.
140 static struct nge_type nge_devs[] = {
141 { NGE_VENDORID, NGE_DEVICEID,
142 "National Semiconductor Gigabit Ethernet" },
146 static int nge_probe (device_t);
147 static int nge_attach (device_t);
148 static int nge_detach (device_t);
150 static int nge_alloc_jumbo_mem (struct nge_softc *);
151 static void nge_free_jumbo_mem (struct nge_softc *);
152 static void *nge_jalloc (struct nge_softc *);
153 static void nge_jfree (caddr_t, u_int);
154 static void nge_jref (caddr_t, u_int);
156 static int nge_newbuf (struct nge_softc *,
157 struct nge_desc *, struct mbuf *);
158 static int nge_encap (struct nge_softc *,
159 struct mbuf *, u_int32_t *);
160 static void nge_rxeof (struct nge_softc *);
161 static void nge_txeof (struct nge_softc *);
162 static void nge_intr (void *);
163 static void nge_tick (void *);
164 static void nge_start (struct ifnet *);
165 static int nge_ioctl (struct ifnet *, u_long, caddr_t,
167 static void nge_init (void *);
168 static void nge_stop (struct nge_softc *);
169 static void nge_watchdog (struct ifnet *);
170 static void nge_shutdown (device_t);
171 static int nge_ifmedia_upd (struct ifnet *);
172 static void nge_ifmedia_sts (struct ifnet *, struct ifmediareq *);
174 static void nge_delay (struct nge_softc *);
175 static void nge_eeprom_idle (struct nge_softc *);
176 static void nge_eeprom_putbyte (struct nge_softc *, int);
177 static void nge_eeprom_getword (struct nge_softc *, int, u_int16_t *);
178 static void nge_read_eeprom (struct nge_softc *, caddr_t, int, int, int);
180 static void nge_mii_sync (struct nge_softc *);
181 static void nge_mii_send (struct nge_softc *, u_int32_t, int);
182 static int nge_mii_readreg (struct nge_softc *, struct nge_mii_frame *);
183 static int nge_mii_writereg (struct nge_softc *, struct nge_mii_frame *);
185 static int nge_miibus_readreg (device_t, int, int);
186 static int nge_miibus_writereg (device_t, int, int, int);
187 static void nge_miibus_statchg (device_t);
189 static void nge_setmulti (struct nge_softc *);
190 static u_int32_t nge_crc (struct nge_softc *, caddr_t);
191 static void nge_reset (struct nge_softc *);
192 static int nge_list_rx_init (struct nge_softc *);
193 static int nge_list_tx_init (struct nge_softc *);
195 #ifdef NGE_USEIOSPACE
196 #define NGE_RES SYS_RES_IOPORT
197 #define NGE_RID NGE_PCI_LOIO
199 #define NGE_RES SYS_RES_MEMORY
200 #define NGE_RID NGE_PCI_LOMEM
203 static device_method_t nge_methods[] = {
204 /* Device interface */
205 DEVMETHOD(device_probe, nge_probe),
206 DEVMETHOD(device_attach, nge_attach),
207 DEVMETHOD(device_detach, nge_detach),
208 DEVMETHOD(device_shutdown, nge_shutdown),
211 DEVMETHOD(bus_print_child, bus_generic_print_child),
212 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
215 DEVMETHOD(miibus_readreg, nge_miibus_readreg),
216 DEVMETHOD(miibus_writereg, nge_miibus_writereg),
217 DEVMETHOD(miibus_statchg, nge_miibus_statchg),
222 static driver_t nge_driver = {
225 sizeof(struct nge_softc)
228 static devclass_t nge_devclass;
230 DECLARE_DUMMY_MODULE(if_nge);
231 MODULE_DEPEND(if_nge, miibus, 1, 1, 1);
232 DRIVER_MODULE(if_nge, pci, nge_driver, nge_devclass, 0, 0);
233 DRIVER_MODULE(miibus, nge, miibus_driver, miibus_devclass, 0, 0);
235 #define NGE_SETBIT(sc, reg, x) \
236 CSR_WRITE_4(sc, reg, \
237 CSR_READ_4(sc, reg) | (x))
239 #define NGE_CLRBIT(sc, reg, x) \
240 CSR_WRITE_4(sc, reg, \
241 CSR_READ_4(sc, reg) & ~(x))
244 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | x)
247 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~x)
249 static void nge_delay(sc)
250 struct nge_softc *sc;
254 for (idx = (300 / 33) + 1; idx > 0; idx--)
255 CSR_READ_4(sc, NGE_CSR);
260 static void nge_eeprom_idle(sc)
261 struct nge_softc *sc;
265 SIO_SET(NGE_MEAR_EE_CSEL);
267 SIO_SET(NGE_MEAR_EE_CLK);
270 for (i = 0; i < 25; i++) {
271 SIO_CLR(NGE_MEAR_EE_CLK);
273 SIO_SET(NGE_MEAR_EE_CLK);
277 SIO_CLR(NGE_MEAR_EE_CLK);
279 SIO_CLR(NGE_MEAR_EE_CSEL);
281 CSR_WRITE_4(sc, NGE_MEAR, 0x00000000);
287 * Send a read command and address to the EEPROM, check for ACK.
289 static void nge_eeprom_putbyte(sc, addr)
290 struct nge_softc *sc;
295 d = addr | NGE_EECMD_READ;
298 * Feed in each bit and stobe the clock.
300 for (i = 0x400; i; i >>= 1) {
302 SIO_SET(NGE_MEAR_EE_DIN);
304 SIO_CLR(NGE_MEAR_EE_DIN);
307 SIO_SET(NGE_MEAR_EE_CLK);
309 SIO_CLR(NGE_MEAR_EE_CLK);
317 * Read a word of data stored in the EEPROM at address 'addr.'
319 static void nge_eeprom_getword(sc, addr, dest)
320 struct nge_softc *sc;
327 /* Force EEPROM to idle state. */
330 /* Enter EEPROM access mode. */
332 SIO_CLR(NGE_MEAR_EE_CLK);
334 SIO_SET(NGE_MEAR_EE_CSEL);
338 * Send address of word we want to read.
340 nge_eeprom_putbyte(sc, addr);
343 * Start reading bits from EEPROM.
345 for (i = 0x8000; i; i >>= 1) {
346 SIO_SET(NGE_MEAR_EE_CLK);
348 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT)
351 SIO_CLR(NGE_MEAR_EE_CLK);
355 /* Turn off EEPROM access mode. */
364 * Read a sequence of words from the EEPROM.
366 static void nge_read_eeprom(sc, dest, off, cnt, swap)
367 struct nge_softc *sc;
374 u_int16_t word = 0, *ptr;
376 for (i = 0; i < cnt; i++) {
377 nge_eeprom_getword(sc, off + i, &word);
378 ptr = (u_int16_t *)(dest + (i * 2));
389 * Sync the PHYs by setting data bit and strobing the clock 32 times.
391 static void nge_mii_sync(sc)
392 struct nge_softc *sc;
396 SIO_SET(NGE_MEAR_MII_DIR|NGE_MEAR_MII_DATA);
398 for (i = 0; i < 32; i++) {
399 SIO_SET(NGE_MEAR_MII_CLK);
401 SIO_CLR(NGE_MEAR_MII_CLK);
409 * Clock a series of bits through the MII.
411 static void nge_mii_send(sc, bits, cnt)
412 struct nge_softc *sc;
418 SIO_CLR(NGE_MEAR_MII_CLK);
420 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
422 SIO_SET(NGE_MEAR_MII_DATA);
424 SIO_CLR(NGE_MEAR_MII_DATA);
427 SIO_CLR(NGE_MEAR_MII_CLK);
429 SIO_SET(NGE_MEAR_MII_CLK);
434 * Read an PHY register through the MII.
436 static int nge_mii_readreg(sc, frame)
437 struct nge_softc *sc;
438 struct nge_mii_frame *frame;
446 * Set up frame for RX.
448 frame->mii_stdelim = NGE_MII_STARTDELIM;
449 frame->mii_opcode = NGE_MII_READOP;
450 frame->mii_turnaround = 0;
453 CSR_WRITE_4(sc, NGE_MEAR, 0);
458 SIO_SET(NGE_MEAR_MII_DIR);
463 * Send command/address info.
465 nge_mii_send(sc, frame->mii_stdelim, 2);
466 nge_mii_send(sc, frame->mii_opcode, 2);
467 nge_mii_send(sc, frame->mii_phyaddr, 5);
468 nge_mii_send(sc, frame->mii_regaddr, 5);
471 SIO_CLR((NGE_MEAR_MII_CLK|NGE_MEAR_MII_DATA));
473 SIO_SET(NGE_MEAR_MII_CLK);
477 SIO_CLR(NGE_MEAR_MII_DIR);
479 SIO_CLR(NGE_MEAR_MII_CLK);
481 ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA;
482 SIO_SET(NGE_MEAR_MII_CLK);
486 * Now try reading data bits. If the ack failed, we still
487 * need to clock through 16 cycles to keep the PHY(s) in sync.
490 for(i = 0; i < 16; i++) {
491 SIO_CLR(NGE_MEAR_MII_CLK);
493 SIO_SET(NGE_MEAR_MII_CLK);
499 for (i = 0x8000; i; i >>= 1) {
500 SIO_CLR(NGE_MEAR_MII_CLK);
503 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA)
504 frame->mii_data |= i;
507 SIO_SET(NGE_MEAR_MII_CLK);
513 SIO_CLR(NGE_MEAR_MII_CLK);
515 SIO_SET(NGE_MEAR_MII_CLK);
526 * Write to a PHY register through the MII.
528 static int nge_mii_writereg(sc, frame)
529 struct nge_softc *sc;
530 struct nge_mii_frame *frame;
537 * Set up frame for TX.
540 frame->mii_stdelim = NGE_MII_STARTDELIM;
541 frame->mii_opcode = NGE_MII_WRITEOP;
542 frame->mii_turnaround = NGE_MII_TURNAROUND;
545 * Turn on data output.
547 SIO_SET(NGE_MEAR_MII_DIR);
551 nge_mii_send(sc, frame->mii_stdelim, 2);
552 nge_mii_send(sc, frame->mii_opcode, 2);
553 nge_mii_send(sc, frame->mii_phyaddr, 5);
554 nge_mii_send(sc, frame->mii_regaddr, 5);
555 nge_mii_send(sc, frame->mii_turnaround, 2);
556 nge_mii_send(sc, frame->mii_data, 16);
559 SIO_SET(NGE_MEAR_MII_CLK);
561 SIO_CLR(NGE_MEAR_MII_CLK);
567 SIO_CLR(NGE_MEAR_MII_DIR);
574 static int nge_miibus_readreg(dev, phy, reg)
578 struct nge_softc *sc;
579 struct nge_mii_frame frame;
581 sc = device_get_softc(dev);
583 bzero((char *)&frame, sizeof(frame));
585 frame.mii_phyaddr = phy;
586 frame.mii_regaddr = reg;
587 nge_mii_readreg(sc, &frame);
589 return(frame.mii_data);
592 static int nge_miibus_writereg(dev, phy, reg, data)
596 struct nge_softc *sc;
597 struct nge_mii_frame frame;
599 sc = device_get_softc(dev);
601 bzero((char *)&frame, sizeof(frame));
603 frame.mii_phyaddr = phy;
604 frame.mii_regaddr = reg;
605 frame.mii_data = data;
606 nge_mii_writereg(sc, &frame);
611 static void nge_miibus_statchg(dev)
615 struct nge_softc *sc;
616 struct mii_data *mii;
618 sc = device_get_softc(dev);
620 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
622 status = CSR_READ_4(sc, NGE_TBI_ANLPAR);
623 if (status == 0 || status & NGE_TBIANAR_FDX) {
624 NGE_SETBIT(sc, NGE_TX_CFG,
625 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
626 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
628 NGE_CLRBIT(sc, NGE_TX_CFG,
629 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
630 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
633 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
635 NGE_CLRBIT(sc, NGE_TX_CFG,
636 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
637 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
639 NGE_SETBIT(sc, NGE_TX_CFG,
640 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
641 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
644 mii = device_get_softc(sc->nge_miibus);
646 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
647 NGE_SETBIT(sc, NGE_TX_CFG,
648 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
649 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
651 NGE_CLRBIT(sc, NGE_TX_CFG,
652 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
653 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
656 /* If we have a 1000Mbps link, set the mode_1000 bit. */
657 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX ||
658 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
659 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_MODE_1000);
661 NGE_CLRBIT(sc, NGE_CFG, NGE_CFG_MODE_1000);
667 static u_int32_t nge_crc(sc, addr)
668 struct nge_softc *sc;
671 u_int32_t crc, carry;
675 /* Compute CRC for the address value. */
676 crc = 0xFFFFFFFF; /* initial value */
678 for (i = 0; i < 6; i++) {
680 for (j = 0; j < 8; j++) {
681 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
685 crc = (crc ^ 0x04c11db6) | carry;
690 * return the filter bit position
693 return((crc >> 21) & 0x00000FFF);
696 static void nge_setmulti(sc)
697 struct nge_softc *sc;
700 struct ifmultiaddr *ifma;
701 u_int32_t h = 0, i, filtsave;
704 ifp = &sc->arpcom.ac_if;
706 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
707 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
708 NGE_RXFILTCTL_MCHASH|NGE_RXFILTCTL_UCHASH);
709 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLMULTI);
714 * We have to explicitly enable the multicast hash table
715 * on the NatSemi chip if we want to use it, which we do.
716 * We also have to tell it that we don't want to use the
717 * hash table for matching unicast addresses.
719 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_MCHASH);
720 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
721 NGE_RXFILTCTL_ALLMULTI|NGE_RXFILTCTL_UCHASH);
723 filtsave = CSR_READ_4(sc, NGE_RXFILT_CTL);
725 /* first, zot all the existing hash bits */
726 for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) {
727 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i);
728 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0);
732 * From the 11 bits returned by the crc routine, the top 7
733 * bits represent the 16-bit word in the mcast hash table
734 * that needs to be updated, and the lower 4 bits represent
735 * which bit within that byte needs to be set.
737 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
738 if (ifma->ifma_addr->sa_family != AF_LINK)
740 h = nge_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
741 index = (h >> 4) & 0x7F;
743 CSR_WRITE_4(sc, NGE_RXFILT_CTL,
744 NGE_FILTADDR_MCAST_LO + (index * 2));
745 NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit));
748 CSR_WRITE_4(sc, NGE_RXFILT_CTL, filtsave);
753 static void nge_reset(sc)
754 struct nge_softc *sc;
758 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET);
760 for (i = 0; i < NGE_TIMEOUT; i++) {
761 if (!(CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET))
765 if (i == NGE_TIMEOUT)
766 printf("nge%d: reset never completed\n", sc->nge_unit);
768 /* Wait a little while for the chip to get its brains in order. */
772 * If this is a NetSemi chip, make sure to clear
775 CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS);
776 CSR_WRITE_4(sc, NGE_CLKRUN, 0);
782 * Probe for an NatSemi chip. Check the PCI vendor and device
783 * IDs against our list and return a device name if we find a match.
785 static int nge_probe(dev)
792 while(t->nge_name != NULL) {
793 if ((pci_get_vendor(dev) == t->nge_vid) &&
794 (pci_get_device(dev) == t->nge_did)) {
795 device_set_desc(dev, t->nge_name);
805 * Attach the interface. Allocate softc structures, do ifmedia
806 * setup and ethernet/BPF attach.
808 static int nge_attach(dev)
812 u_char eaddr[ETHER_ADDR_LEN];
814 struct nge_softc *sc;
816 int unit, error = 0, rid;
817 const char *sep = "";
821 sc = device_get_softc(dev);
822 unit = device_get_unit(dev);
823 bzero(sc, sizeof(struct nge_softc));
824 callout_init(&sc->nge_stat_timer);
827 * Handle power management nonsense.
831 command = pci_read_config(dev, NGE_PCI_CAPID, 4) & 0x000000FF;
832 if (command == 0x01) {
834 command = pci_read_config(dev, NGE_PCI_PWRMGMTCTRL, 4);
835 if (command & NGE_PSTATE_MASK) {
836 u_int32_t iobase, membase, irq;
838 /* Save important PCI config data. */
839 iobase = pci_read_config(dev, NGE_PCI_LOIO, 4);
840 membase = pci_read_config(dev, NGE_PCI_LOMEM, 4);
841 irq = pci_read_config(dev, NGE_PCI_INTLINE, 4);
843 /* Reset the power state. */
844 printf("nge%d: chip is in D%d power mode "
845 "-- setting to D0\n", unit, command & NGE_PSTATE_MASK);
846 command &= 0xFFFFFFFC;
847 pci_write_config(dev, NGE_PCI_PWRMGMTCTRL, command, 4);
849 /* Restore PCI config data. */
850 pci_write_config(dev, NGE_PCI_LOIO, iobase, 4);
851 pci_write_config(dev, NGE_PCI_LOMEM, membase, 4);
852 pci_write_config(dev, NGE_PCI_INTLINE, irq, 4);
857 * Map control/status registers.
859 command = pci_read_config(dev, PCIR_COMMAND, 4);
860 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
861 pci_write_config(dev, PCIR_COMMAND, command, 4);
862 command = pci_read_config(dev, PCIR_COMMAND, 4);
864 #ifdef NGE_USEIOSPACE
865 if (!(command & PCIM_CMD_PORTEN)) {
866 printf("nge%d: failed to enable I/O ports!\n", unit);
871 if (!(command & PCIM_CMD_MEMEN)) {
872 printf("nge%d: failed to enable memory mapping!\n", unit);
879 sc->nge_res = bus_alloc_resource(dev, NGE_RES, &rid,
880 0, ~0, 1, RF_ACTIVE);
882 if (sc->nge_res == NULL) {
883 printf("nge%d: couldn't map ports/memory\n", unit);
888 sc->nge_btag = rman_get_bustag(sc->nge_res);
889 sc->nge_bhandle = rman_get_bushandle(sc->nge_res);
891 /* Allocate interrupt */
893 sc->nge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
894 RF_SHAREABLE | RF_ACTIVE);
896 if (sc->nge_irq == NULL) {
897 printf("nge%d: couldn't map interrupt\n", unit);
898 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
903 error = bus_setup_intr(dev, sc->nge_irq, INTR_TYPE_NET,
904 nge_intr, sc, &sc->nge_intrhand);
907 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
908 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
909 printf("nge%d: couldn't set up irq\n", unit);
913 /* Reset the adapter. */
917 * Get station address from the EEPROM.
919 nge_read_eeprom(sc, (caddr_t)&eaddr[4], NGE_EE_NODEADDR, 1, 0);
920 nge_read_eeprom(sc, (caddr_t)&eaddr[2], NGE_EE_NODEADDR + 1, 1, 0);
921 nge_read_eeprom(sc, (caddr_t)&eaddr[0], NGE_EE_NODEADDR + 2, 1, 0);
925 sc->nge_ldata = contigmalloc(sizeof(struct nge_list_data), M_DEVBUF,
926 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
928 if (sc->nge_ldata == NULL) {
929 printf("nge%d: no memory for list buffers!\n", unit);
930 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand);
931 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
932 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
936 bzero(sc->nge_ldata, sizeof(struct nge_list_data));
938 /* Try to allocate memory for jumbo buffers. */
939 if (nge_alloc_jumbo_mem(sc)) {
940 printf("nge%d: jumbo buffer allocation failed\n",
942 contigfree(sc->nge_ldata,
943 sizeof(struct nge_list_data), M_DEVBUF);
944 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand);
945 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
946 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
951 ifp = &sc->arpcom.ac_if;
953 if_initname(ifp, "nge", unit);
954 ifp->if_mtu = ETHERMTU;
955 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
956 ifp->if_ioctl = nge_ioctl;
957 ifp->if_start = nge_start;
958 ifp->if_watchdog = nge_watchdog;
959 ifp->if_init = nge_init;
960 ifp->if_baudrate = 1000000000;
961 ifp->if_snd.ifq_maxlen = NGE_TX_LIST_CNT - 1;
962 ifp->if_hwassist = NGE_CSUM_FEATURES;
963 ifp->if_capabilities = IFCAP_HWCSUM;
964 ifp->if_capenable = ifp->if_capabilities;
969 if (mii_phy_probe(dev, &sc->nge_miibus,
970 nge_ifmedia_upd, nge_ifmedia_sts)) {
971 if (CSR_READ_4(sc, NGE_CFG) & NGE_CFG_TBI_EN) {
973 device_printf(dev, "Using TBI\n");
975 sc->nge_miibus = dev;
977 ifmedia_init(&sc->nge_ifmedia, 0, nge_ifmedia_upd,
979 #define ADD(m, c) ifmedia_add(&sc->nge_ifmedia, (m), (c), NULL)
980 #define PRINT(s) printf("%s%s", sep, s); sep = ", "
981 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, 0), 0);
982 device_printf(dev, " ");
983 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, 0, 0), 0);
985 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, 0),0);
986 PRINT("1000baseSX-FDX");
987 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0), 0);
993 ifmedia_set(&sc->nge_ifmedia,
994 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0));
996 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
998 | NGE_GPIO_GP1_OUTENB | NGE_GPIO_GP2_OUTENB
999 | NGE_GPIO_GP3_OUTENB
1000 | NGE_GPIO_GP3_IN | NGE_GPIO_GP4_IN);
1003 printf("nge%d: MII without any PHY!\n", sc->nge_unit);
1004 nge_free_jumbo_mem(sc);
1005 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand);
1006 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
1007 bus_release_resource(dev, NGE_RES, NGE_RID,
1015 * Call MI attach routine.
1017 ether_ifattach(ifp, eaddr);
1025 static int nge_detach(dev)
1028 struct nge_softc *sc;
1034 sc = device_get_softc(dev);
1035 ifp = &sc->arpcom.ac_if;
1039 ether_ifdetach(ifp);
1041 bus_generic_detach(dev);
1043 device_delete_child(dev, sc->nge_miibus);
1045 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand);
1046 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
1047 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
1049 contigfree(sc->nge_ldata, sizeof(struct nge_list_data), M_DEVBUF);
1050 nge_free_jumbo_mem(sc);
1058 * Initialize the transmit descriptors.
1060 static int nge_list_tx_init(sc)
1061 struct nge_softc *sc;
1063 struct nge_list_data *ld;
1064 struct nge_ring_data *cd;
1067 cd = &sc->nge_cdata;
1070 for (i = 0; i < NGE_TX_LIST_CNT; i++) {
1071 if (i == (NGE_TX_LIST_CNT - 1)) {
1072 ld->nge_tx_list[i].nge_nextdesc =
1073 &ld->nge_tx_list[0];
1074 ld->nge_tx_list[i].nge_next =
1075 vtophys(&ld->nge_tx_list[0]);
1077 ld->nge_tx_list[i].nge_nextdesc =
1078 &ld->nge_tx_list[i + 1];
1079 ld->nge_tx_list[i].nge_next =
1080 vtophys(&ld->nge_tx_list[i + 1]);
1082 ld->nge_tx_list[i].nge_mbuf = NULL;
1083 ld->nge_tx_list[i].nge_ptr = 0;
1084 ld->nge_tx_list[i].nge_ctl = 0;
1087 cd->nge_tx_prod = cd->nge_tx_cons = cd->nge_tx_cnt = 0;
1094 * Initialize the RX descriptors and allocate mbufs for them. Note that
1095 * we arrange the descriptors in a closed ring, so that the last descriptor
1096 * points back to the first.
1098 static int nge_list_rx_init(sc)
1099 struct nge_softc *sc;
1101 struct nge_list_data *ld;
1102 struct nge_ring_data *cd;
1106 cd = &sc->nge_cdata;
1108 for (i = 0; i < NGE_RX_LIST_CNT; i++) {
1109 if (nge_newbuf(sc, &ld->nge_rx_list[i], NULL) == ENOBUFS)
1111 if (i == (NGE_RX_LIST_CNT - 1)) {
1112 ld->nge_rx_list[i].nge_nextdesc =
1113 &ld->nge_rx_list[0];
1114 ld->nge_rx_list[i].nge_next =
1115 vtophys(&ld->nge_rx_list[0]);
1117 ld->nge_rx_list[i].nge_nextdesc =
1118 &ld->nge_rx_list[i + 1];
1119 ld->nge_rx_list[i].nge_next =
1120 vtophys(&ld->nge_rx_list[i + 1]);
1124 cd->nge_rx_prod = 0;
1130 * Initialize an RX descriptor and attach an MBUF cluster.
1132 static int nge_newbuf(sc, c, m)
1133 struct nge_softc *sc;
1137 struct mbuf *m_new = NULL;
1138 caddr_t *buf = NULL;
1141 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
1142 if (m_new == NULL) {
1143 printf("nge%d: no memory for rx list "
1144 "-- packet dropped!\n", sc->nge_unit);
1148 /* Allocate the jumbo buffer */
1149 buf = nge_jalloc(sc);
1152 printf("nge%d: jumbo allocation failed "
1153 "-- packet dropped!\n", sc->nge_unit);
1158 /* Attach the buffer to the mbuf */
1159 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf;
1160 m_new->m_flags |= M_EXT | M_EXT_OLD;
1161 m_new->m_ext.ext_size = m_new->m_pkthdr.len =
1162 m_new->m_len = NGE_MCLBYTES;
1163 m_new->m_ext.ext_nfree.old = nge_jfree;
1164 m_new->m_ext.ext_nref.old = nge_jref;
1167 m_new->m_len = m_new->m_pkthdr.len = NGE_MCLBYTES;
1168 m_new->m_data = m_new->m_ext.ext_buf;
1171 m_adj(m_new, sizeof(u_int64_t));
1173 c->nge_mbuf = m_new;
1174 c->nge_ptr = vtophys(mtod(m_new, caddr_t));
1175 c->nge_ctl = m_new->m_len;
1181 static int nge_alloc_jumbo_mem(sc)
1182 struct nge_softc *sc;
1186 struct nge_jpool_entry *entry;
1188 /* Grab a big chunk o' storage. */
1189 sc->nge_cdata.nge_jumbo_buf = contigmalloc(NGE_JMEM, M_DEVBUF,
1190 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1192 if (sc->nge_cdata.nge_jumbo_buf == NULL) {
1193 printf("nge%d: no memory for jumbo buffers!\n", sc->nge_unit);
1197 SLIST_INIT(&sc->nge_jfree_listhead);
1198 SLIST_INIT(&sc->nge_jinuse_listhead);
1201 * Now divide it up into 9K pieces and save the addresses
1204 ptr = sc->nge_cdata.nge_jumbo_buf;
1205 for (i = 0; i < NGE_JSLOTS; i++) {
1207 aptr = (u_int64_t **)ptr;
1208 aptr[0] = (u_int64_t *)sc;
1209 ptr += sizeof(u_int64_t);
1210 sc->nge_cdata.nge_jslots[i].nge_buf = ptr;
1211 sc->nge_cdata.nge_jslots[i].nge_inuse = 0;
1212 ptr += NGE_MCLBYTES;
1213 entry = malloc(sizeof(struct nge_jpool_entry),
1214 M_DEVBUF, M_WAITOK);
1215 if (entry == NULL) {
1216 printf("nge%d: no memory for jumbo "
1217 "buffer queue!\n", sc->nge_unit);
1221 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead,
1222 entry, jpool_entries);
1228 static void nge_free_jumbo_mem(sc)
1229 struct nge_softc *sc;
1232 struct nge_jpool_entry *entry;
1234 for (i = 0; i < NGE_JSLOTS; i++) {
1235 entry = SLIST_FIRST(&sc->nge_jfree_listhead);
1236 SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jpool_entries);
1237 free(entry, M_DEVBUF);
1240 contigfree(sc->nge_cdata.nge_jumbo_buf, NGE_JMEM, M_DEVBUF);
1246 * Allocate a jumbo buffer.
1248 static void *nge_jalloc(sc)
1249 struct nge_softc *sc;
1251 struct nge_jpool_entry *entry;
1253 entry = SLIST_FIRST(&sc->nge_jfree_listhead);
1255 if (entry == NULL) {
1257 printf("nge%d: no free jumbo buffers\n", sc->nge_unit);
1262 SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jpool_entries);
1263 SLIST_INSERT_HEAD(&sc->nge_jinuse_listhead, entry, jpool_entries);
1264 sc->nge_cdata.nge_jslots[entry->slot].nge_inuse = 1;
1265 return(sc->nge_cdata.nge_jslots[entry->slot].nge_buf);
1269 * Adjust usage count on a jumbo buffer. In general this doesn't
1270 * get used much because our jumbo buffers don't get passed around
1271 * a lot, but it's implemented for correctness.
1273 static void nge_jref(buf, size)
1277 struct nge_softc *sc;
1281 /* Extract the softc struct pointer. */
1282 aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
1283 sc = (struct nge_softc *)(aptr[0]);
1286 panic("nge_jref: can't find softc pointer!");
1288 if (size != NGE_MCLBYTES)
1289 panic("nge_jref: adjusting refcount of buf of wrong size!");
1291 /* calculate the slot this buffer belongs to */
1293 i = ((vm_offset_t)aptr
1294 - (vm_offset_t)sc->nge_cdata.nge_jumbo_buf) / NGE_JLEN;
1296 if ((i < 0) || (i >= NGE_JSLOTS))
1297 panic("nge_jref: asked to reference buffer "
1298 "that we don't manage!");
1299 else if (sc->nge_cdata.nge_jslots[i].nge_inuse == 0)
1300 panic("nge_jref: buffer already free!");
1302 sc->nge_cdata.nge_jslots[i].nge_inuse++;
1308 * Release a jumbo buffer.
1310 static void nge_jfree(buf, size)
1314 struct nge_softc *sc;
1317 struct nge_jpool_entry *entry;
1319 /* Extract the softc struct pointer. */
1320 aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
1321 sc = (struct nge_softc *)(aptr[0]);
1324 panic("nge_jfree: can't find softc pointer!");
1326 if (size != NGE_MCLBYTES)
1327 panic("nge_jfree: freeing buffer of wrong size!");
1329 /* calculate the slot this buffer belongs to */
1331 i = ((vm_offset_t)aptr
1332 - (vm_offset_t)sc->nge_cdata.nge_jumbo_buf) / NGE_JLEN;
1334 if ((i < 0) || (i >= NGE_JSLOTS))
1335 panic("nge_jfree: asked to free buffer that we don't manage!");
1336 else if (sc->nge_cdata.nge_jslots[i].nge_inuse == 0)
1337 panic("nge_jfree: buffer already free!");
1339 sc->nge_cdata.nge_jslots[i].nge_inuse--;
1340 if(sc->nge_cdata.nge_jslots[i].nge_inuse == 0) {
1341 entry = SLIST_FIRST(&sc->nge_jinuse_listhead);
1343 panic("nge_jfree: buffer not in use!");
1345 SLIST_REMOVE_HEAD(&sc->nge_jinuse_listhead,
1347 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead,
1348 entry, jpool_entries);
1355 * A frame has been uploaded: pass the resulting mbuf chain up to
1356 * the higher level protocols.
1358 static void nge_rxeof(sc)
1359 struct nge_softc *sc;
1363 struct nge_desc *cur_rx;
1364 int i, total_len = 0;
1367 ifp = &sc->arpcom.ac_if;
1368 i = sc->nge_cdata.nge_rx_prod;
1370 while(NGE_OWNDESC(&sc->nge_ldata->nge_rx_list[i])) {
1371 struct mbuf *m0 = NULL;
1374 #ifdef DEVICE_POLLING
1375 if (ifp->if_flags & IFF_POLLING) {
1376 if (sc->rxcycles <= 0)
1380 #endif /* DEVICE_POLLING */
1382 cur_rx = &sc->nge_ldata->nge_rx_list[i];
1383 rxstat = cur_rx->nge_rxstat;
1384 extsts = cur_rx->nge_extsts;
1385 m = cur_rx->nge_mbuf;
1386 cur_rx->nge_mbuf = NULL;
1387 total_len = NGE_RXBYTES(cur_rx);
1388 NGE_INC(i, NGE_RX_LIST_CNT);
1390 * If an error occurs, update stats, clear the
1391 * status word and leave the mbuf cluster in place:
1392 * it should simply get re-used next time this descriptor
1393 * comes up in the ring.
1395 if (!(rxstat & NGE_CMDSTS_PKT_OK)) {
1397 nge_newbuf(sc, cur_rx, m);
1402 * Ok. NatSemi really screwed up here. This is the
1403 * only gigE chip I know of with alignment constraints
1404 * on receive buffers. RX buffers must be 64-bit aligned.
1408 * By popular demand, ignore the alignment problems
1409 * on the Intel x86 platform. The performance hit
1410 * incurred due to unaligned accesses is much smaller
1411 * than the hit produced by forcing buffer copies all
1412 * the time, especially with jumbo frames. We still
1413 * need to fix up the alignment everywhere else though.
1415 if (nge_newbuf(sc, cur_rx, NULL) == ENOBUFS) {
1417 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1418 total_len + ETHER_ALIGN, 0, ifp, NULL);
1419 nge_newbuf(sc, cur_rx, m);
1421 printf("nge%d: no receive buffers "
1422 "available -- packet dropped!\n",
1427 m_adj(m0, ETHER_ALIGN);
1431 m->m_pkthdr.rcvif = ifp;
1432 m->m_pkthdr.len = m->m_len = total_len;
1438 /* Do IP checksum checking. */
1439 if (extsts & NGE_RXEXTSTS_IPPKT)
1440 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1441 if (!(extsts & NGE_RXEXTSTS_IPCSUMERR))
1442 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1443 if ((extsts & NGE_RXEXTSTS_TCPPKT &&
1444 !(extsts & NGE_RXEXTSTS_TCPCSUMERR)) ||
1445 (extsts & NGE_RXEXTSTS_UDPPKT &&
1446 !(extsts & NGE_RXEXTSTS_UDPCSUMERR))) {
1447 m->m_pkthdr.csum_flags |=
1448 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1449 m->m_pkthdr.csum_data = 0xffff;
1453 * If we received a packet with a vlan tag, pass it
1454 * to vlan_input() instead of ether_input().
1456 if (extsts & NGE_RXEXTSTS_VLANPKT)
1457 VLAN_INPUT_TAG(m, extsts & NGE_RXEXTSTS_VTCI);
1459 (*ifp->if_input)(ifp, m);
1462 sc->nge_cdata.nge_rx_prod = i;
1468 * A frame was downloaded to the chip. It's safe for us to clean up
1472 static void nge_txeof(sc)
1473 struct nge_softc *sc;
1475 struct nge_desc *cur_tx = NULL;
1479 ifp = &sc->arpcom.ac_if;
1481 /* Clear the timeout timer. */
1485 * Go through our tx list and free mbufs for those
1486 * frames that have been transmitted.
1488 idx = sc->nge_cdata.nge_tx_cons;
1489 while (idx != sc->nge_cdata.nge_tx_prod) {
1490 cur_tx = &sc->nge_ldata->nge_tx_list[idx];
1492 if (NGE_OWNDESC(cur_tx))
1495 if (cur_tx->nge_ctl & NGE_CMDSTS_MORE) {
1496 sc->nge_cdata.nge_tx_cnt--;
1497 NGE_INC(idx, NGE_TX_LIST_CNT);
1501 if (!(cur_tx->nge_ctl & NGE_CMDSTS_PKT_OK)) {
1503 if (cur_tx->nge_txstat & NGE_TXSTAT_EXCESSCOLLS)
1504 ifp->if_collisions++;
1505 if (cur_tx->nge_txstat & NGE_TXSTAT_OUTOFWINCOLL)
1506 ifp->if_collisions++;
1509 ifp->if_collisions +=
1510 (cur_tx->nge_txstat & NGE_TXSTAT_COLLCNT) >> 16;
1513 if (cur_tx->nge_mbuf != NULL) {
1514 m_freem(cur_tx->nge_mbuf);
1515 cur_tx->nge_mbuf = NULL;
1518 sc->nge_cdata.nge_tx_cnt--;
1519 NGE_INC(idx, NGE_TX_LIST_CNT);
1523 sc->nge_cdata.nge_tx_cons = idx;
1526 ifp->if_flags &= ~IFF_OACTIVE;
1531 static void nge_tick(xsc)
1534 struct nge_softc *sc;
1535 struct mii_data *mii;
1542 ifp = &sc->arpcom.ac_if;
1545 if (!sc->nge_link) {
1546 if (CSR_READ_4(sc, NGE_TBI_BMSR)
1547 & NGE_TBIBMSR_ANEG_DONE) {
1548 printf("nge%d: gigabit link up\n",
1550 nge_miibus_statchg(sc->nge_miibus);
1552 if (ifp->if_snd.ifq_head != NULL)
1557 mii = device_get_softc(sc->nge_miibus);
1560 if (!sc->nge_link) {
1561 if (mii->mii_media_status & IFM_ACTIVE &&
1562 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1564 if (IFM_SUBTYPE(mii->mii_media_active)
1566 printf("nge%d: gigabit link up\n",
1568 if (ifp->if_snd.ifq_head != NULL)
1573 callout_reset(&sc->nge_stat_timer, hz, nge_tick, sc);
1580 #ifdef DEVICE_POLLING
1581 static poll_handler_t nge_poll;
1584 nge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1586 struct nge_softc *sc = ifp->if_softc;
1588 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
1589 CSR_WRITE_4(sc, NGE_IER, 1);
1594 * On the nge, reading the status register also clears it.
1595 * So before returning to intr mode we must make sure that all
1596 * possible pending sources of interrupts have been served.
1597 * In practice this means run to completion the *eof routines,
1598 * and then call the interrupt routine
1600 sc->rxcycles = count;
1603 if (ifp->if_snd.ifq_head != NULL)
1606 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) {
1609 /* Reading the ISR register clears all interrupts. */
1610 status = CSR_READ_4(sc, NGE_ISR);
1612 if (status & (NGE_ISR_RX_ERR|NGE_ISR_RX_OFLOW))
1615 if (status & (NGE_ISR_RX_IDLE))
1616 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
1618 if (status & NGE_ISR_SYSERR) {
1624 #endif /* DEVICE_POLLING */
1626 static void nge_intr(arg)
1629 struct nge_softc *sc;
1634 ifp = &sc->arpcom.ac_if;
1636 #ifdef DEVICE_POLLING
1637 if (ifp->if_flags & IFF_POLLING)
1639 if (ether_poll_register(nge_poll, ifp)) { /* ok, disable interrupts */
1640 CSR_WRITE_4(sc, NGE_IER, 0);
1641 nge_poll(ifp, 0, 1);
1644 #endif /* DEVICE_POLLING */
1646 /* Supress unwanted interrupts */
1647 if (!(ifp->if_flags & IFF_UP)) {
1652 /* Disable interrupts. */
1653 CSR_WRITE_4(sc, NGE_IER, 0);
1655 /* Data LED on for TBI mode */
1657 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
1658 | NGE_GPIO_GP3_OUT);
1661 /* Reading the ISR register clears all interrupts. */
1662 status = CSR_READ_4(sc, NGE_ISR);
1664 if ((status & NGE_INTRS) == 0)
1667 if ((status & NGE_ISR_TX_DESC_OK) ||
1668 (status & NGE_ISR_TX_ERR) ||
1669 (status & NGE_ISR_TX_OK) ||
1670 (status & NGE_ISR_TX_IDLE))
1673 if ((status & NGE_ISR_RX_DESC_OK) ||
1674 (status & NGE_ISR_RX_ERR) ||
1675 (status & NGE_ISR_RX_OFLOW) ||
1676 (status & NGE_ISR_RX_FIFO_OFLOW) ||
1677 (status & NGE_ISR_RX_IDLE) ||
1678 (status & NGE_ISR_RX_OK))
1681 if ((status & NGE_ISR_RX_IDLE))
1682 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
1684 if (status & NGE_ISR_SYSERR) {
1686 ifp->if_flags &= ~IFF_RUNNING;
1691 /* mii_tick should only be called once per second */
1692 if (status & NGE_ISR_PHY_INTR) {
1699 /* Re-enable interrupts. */
1700 CSR_WRITE_4(sc, NGE_IER, 1);
1702 if (ifp->if_snd.ifq_head != NULL)
1705 /* Data LED off for TBI mode */
1708 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
1709 & ~NGE_GPIO_GP3_OUT);
1715 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1716 * pointers to the fragment pointers.
1718 static int nge_encap(sc, m_head, txidx)
1719 struct nge_softc *sc;
1720 struct mbuf *m_head;
1723 struct nge_desc *f = NULL;
1725 int frag, cur, cnt = 0;
1726 struct ifvlan *ifv = NULL;
1728 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
1729 m_head->m_pkthdr.rcvif != NULL &&
1730 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN)
1731 ifv = m_head->m_pkthdr.rcvif->if_softc;
1734 * Start packing the mbufs in this chain into
1735 * the fragment pointers. Stop when we run out
1736 * of fragments or hit the end of the mbuf chain.
1739 cur = frag = *txidx;
1741 for (m = m_head; m != NULL; m = m->m_next) {
1742 if (m->m_len != 0) {
1743 if ((NGE_TX_LIST_CNT -
1744 (sc->nge_cdata.nge_tx_cnt + cnt)) < 2)
1746 f = &sc->nge_ldata->nge_tx_list[frag];
1747 f->nge_ctl = NGE_CMDSTS_MORE | m->m_len;
1748 f->nge_ptr = vtophys(mtod(m, vm_offset_t));
1750 f->nge_ctl |= NGE_CMDSTS_OWN;
1752 NGE_INC(frag, NGE_TX_LIST_CNT);
1760 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts = 0;
1761 if (m_head->m_pkthdr.csum_flags) {
1762 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
1763 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |=
1764 NGE_TXEXTSTS_IPCSUM;
1765 if (m_head->m_pkthdr.csum_flags & CSUM_TCP)
1766 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |=
1767 NGE_TXEXTSTS_TCPCSUM;
1768 if (m_head->m_pkthdr.csum_flags & CSUM_UDP)
1769 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |=
1770 NGE_TXEXTSTS_UDPCSUM;
1774 sc->nge_ldata->nge_tx_list[cur].nge_extsts |=
1775 (NGE_TXEXTSTS_VLANPKT|ifv->ifv_tag);
1778 sc->nge_ldata->nge_tx_list[cur].nge_mbuf = m_head;
1779 sc->nge_ldata->nge_tx_list[cur].nge_ctl &= ~NGE_CMDSTS_MORE;
1780 sc->nge_ldata->nge_tx_list[*txidx].nge_ctl |= NGE_CMDSTS_OWN;
1781 sc->nge_cdata.nge_tx_cnt += cnt;
1788 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1789 * to the mbuf data regions directly in the transmit lists. We also save a
1790 * copy of the pointers since the transmit list fragment pointers are
1791 * physical addresses.
1794 static void nge_start(ifp)
1797 struct nge_softc *sc;
1798 struct mbuf *m_head = NULL;
1806 idx = sc->nge_cdata.nge_tx_prod;
1808 if (ifp->if_flags & IFF_OACTIVE)
1811 while(sc->nge_ldata->nge_tx_list[idx].nge_mbuf == NULL) {
1812 IF_DEQUEUE(&ifp->if_snd, m_head);
1816 if (nge_encap(sc, m_head, &idx)) {
1817 IF_PREPEND(&ifp->if_snd, m_head);
1818 ifp->if_flags |= IFF_OACTIVE;
1823 * If there's a BPF listener, bounce a copy of this frame
1827 bpf_mtap(ifp, m_head);
1832 sc->nge_cdata.nge_tx_prod = idx;
1833 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_ENABLE);
1836 * Set a timeout in case the chip goes out to lunch.
1843 static void nge_init(xsc)
1846 struct nge_softc *sc = xsc;
1847 struct ifnet *ifp = &sc->arpcom.ac_if;
1848 struct mii_data *mii;
1851 if (ifp->if_flags & IFF_RUNNING)
1857 * Cancel pending I/O and free all RX/TX buffers.
1860 callout_reset(&sc->nge_stat_timer, hz, nge_tick, sc);
1865 mii = device_get_softc(sc->nge_miibus);
1868 /* Set MAC address */
1869 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0);
1870 CSR_WRITE_4(sc, NGE_RXFILT_DATA,
1871 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]);
1872 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1);
1873 CSR_WRITE_4(sc, NGE_RXFILT_DATA,
1874 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]);
1875 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2);
1876 CSR_WRITE_4(sc, NGE_RXFILT_DATA,
1877 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]);
1879 /* Init circular RX list. */
1880 if (nge_list_rx_init(sc) == ENOBUFS) {
1881 printf("nge%d: initialization failed: no "
1882 "memory for rx buffers\n", sc->nge_unit);
1889 * Init tx descriptors.
1891 nge_list_tx_init(sc);
1894 * For the NatSemi chip, we have to explicitly enable the
1895 * reception of ARP frames, as well as turn on the 'perfect
1896 * match' filter where we store the station address, otherwise
1897 * we won't receive unicasts meant for this host.
1899 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ARP);
1900 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_PERFECT);
1902 /* If we want promiscuous mode, set the allframes bit. */
1903 if (ifp->if_flags & IFF_PROMISC) {
1904 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS);
1906 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS);
1910 * Set the capture broadcast bit to capture broadcast frames.
1912 if (ifp->if_flags & IFF_BROADCAST) {
1913 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD);
1915 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD);
1919 * Load the multicast filter.
1923 /* Turn the receive filter on */
1924 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ENABLE);
1927 * Load the address of the RX and TX lists.
1929 CSR_WRITE_4(sc, NGE_RX_LISTPTR,
1930 vtophys(&sc->nge_ldata->nge_rx_list[0]));
1931 CSR_WRITE_4(sc, NGE_TX_LISTPTR,
1932 vtophys(&sc->nge_ldata->nge_tx_list[0]));
1934 /* Set RX configuration */
1935 CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG);
1937 * Enable hardware checksum validation for all IPv4
1938 * packets, do not reject packets with bad checksums.
1940 CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB);
1943 * Tell the chip to detect and strip VLAN tag info from
1944 * received frames. The tag will be provided in the extsts
1945 * field in the RX descriptors.
1947 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL,
1948 NGE_VIPRXCTL_TAG_DETECT_ENB|NGE_VIPRXCTL_TAG_STRIP_ENB);
1950 /* Set TX configuration */
1951 CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG);
1954 * Enable TX IPv4 checksumming on a per-packet basis.
1956 CSR_WRITE_4(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_CSUM_PER_PKT);
1959 * Tell the chip to insert VLAN tags on a per-packet basis as
1960 * dictated by the code in the frame encapsulation routine.
1962 NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT);
1964 /* Set full/half duplex mode. */
1966 if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
1968 NGE_SETBIT(sc, NGE_TX_CFG,
1969 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1970 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1972 NGE_CLRBIT(sc, NGE_TX_CFG,
1973 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1974 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1977 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1978 NGE_SETBIT(sc, NGE_TX_CFG,
1979 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1980 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1982 NGE_CLRBIT(sc, NGE_TX_CFG,
1983 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1984 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1989 * Enable the delivery of PHY interrupts based on
1990 * link/speed/duplex status changes. Also enable the
1991 * extsts field in the DMA descriptors (needed for
1992 * TCP/IP checksum offload on transmit).
1994 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD|
1995 NGE_CFG_PHYINTR_LNK|NGE_CFG_PHYINTR_DUP|NGE_CFG_EXTSTS_ENB);
1998 * Configure interrupt holdoff (moderation). We can
1999 * have the chip delay interrupt delivery for a certain
2000 * period. Units are in 100us, and the max setting
2001 * is 25500us (0xFF x 100us). Default is a 100us holdoff.
2003 CSR_WRITE_4(sc, NGE_IHR, 0x01);
2006 * Enable interrupts.
2008 CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS);
2009 #ifdef DEVICE_POLLING
2011 * ... only enable interrupts if we are not polling, make sure
2012 * they are off otherwise.
2014 if (ifp->if_flags & IFF_POLLING)
2015 CSR_WRITE_4(sc, NGE_IER, 0);
2017 #endif /* DEVICE_POLLING */
2018 CSR_WRITE_4(sc, NGE_IER, 1);
2020 /* Enable receiver and transmitter. */
2021 NGE_CLRBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE);
2022 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
2024 nge_ifmedia_upd(ifp);
2026 ifp->if_flags |= IFF_RUNNING;
2027 ifp->if_flags &= ~IFF_OACTIVE;
2035 * Set media options.
2037 static int nge_ifmedia_upd(ifp)
2040 struct nge_softc *sc;
2041 struct mii_data *mii;
2046 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
2048 CSR_WRITE_4(sc, NGE_TBI_ANAR,
2049 CSR_READ_4(sc, NGE_TBI_ANAR)
2050 | NGE_TBIANAR_HDX | NGE_TBIANAR_FDX
2051 | NGE_TBIANAR_PS1 | NGE_TBIANAR_PS2);
2052 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG
2053 | NGE_TBIBMCR_RESTART_ANEG);
2054 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG);
2055 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media
2056 & IFM_GMASK) == IFM_FDX) {
2057 NGE_SETBIT(sc, NGE_TX_CFG,
2058 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
2059 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
2061 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0);
2062 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0);
2064 NGE_CLRBIT(sc, NGE_TX_CFG,
2065 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
2066 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
2068 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0);
2069 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0);
2072 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
2073 & ~NGE_GPIO_GP3_OUT);
2075 mii = device_get_softc(sc->nge_miibus);
2077 if (mii->mii_instance) {
2078 struct mii_softc *miisc;
2079 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
2080 miisc = LIST_NEXT(miisc, mii_list))
2081 mii_phy_reset(miisc);
2090 * Report current media status.
2092 static void nge_ifmedia_sts(ifp, ifmr)
2094 struct ifmediareq *ifmr;
2096 struct nge_softc *sc;
2097 struct mii_data *mii;
2102 ifmr->ifm_status = IFM_AVALID;
2103 ifmr->ifm_active = IFM_ETHER;
2105 if (CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE) {
2106 ifmr->ifm_status |= IFM_ACTIVE;
2108 if (CSR_READ_4(sc, NGE_TBI_BMCR) & NGE_TBIBMCR_LOOPBACK)
2109 ifmr->ifm_active |= IFM_LOOP;
2110 if (!CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE) {
2111 ifmr->ifm_active |= IFM_NONE;
2112 ifmr->ifm_status = 0;
2115 ifmr->ifm_active |= IFM_1000_SX;
2116 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
2118 ifmr->ifm_active |= IFM_AUTO;
2119 if (CSR_READ_4(sc, NGE_TBI_ANLPAR)
2120 & NGE_TBIANAR_FDX) {
2121 ifmr->ifm_active |= IFM_FDX;
2122 }else if (CSR_READ_4(sc, NGE_TBI_ANLPAR)
2123 & NGE_TBIANAR_HDX) {
2124 ifmr->ifm_active |= IFM_HDX;
2126 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
2128 ifmr->ifm_active |= IFM_FDX;
2130 ifmr->ifm_active |= IFM_HDX;
2133 mii = device_get_softc(sc->nge_miibus);
2135 ifmr->ifm_active = mii->mii_media_active;
2136 ifmr->ifm_status = mii->mii_media_status;
2142 static int nge_ioctl(ifp, command, data, cr)
2148 struct nge_softc *sc = ifp->if_softc;
2149 struct ifreq *ifr = (struct ifreq *) data;
2150 struct mii_data *mii;
2158 error = ether_ioctl(ifp, command, data);
2161 if (ifr->ifr_mtu > NGE_JUMBO_MTU)
2164 ifp->if_mtu = ifr->ifr_mtu;
2166 * Workaround: if the MTU is larger than
2167 * 8152 (TX FIFO size minus 64 minus 18), turn off
2168 * TX checksum offloading.
2170 if (ifr->ifr_mtu >= 8152)
2171 ifp->if_hwassist = 0;
2173 ifp->if_hwassist = NGE_CSUM_FEATURES;
2177 if (ifp->if_flags & IFF_UP) {
2178 if (ifp->if_flags & IFF_RUNNING &&
2179 ifp->if_flags & IFF_PROMISC &&
2180 !(sc->nge_if_flags & IFF_PROMISC)) {
2181 NGE_SETBIT(sc, NGE_RXFILT_CTL,
2182 NGE_RXFILTCTL_ALLPHYS|
2183 NGE_RXFILTCTL_ALLMULTI);
2184 } else if (ifp->if_flags & IFF_RUNNING &&
2185 !(ifp->if_flags & IFF_PROMISC) &&
2186 sc->nge_if_flags & IFF_PROMISC) {
2187 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
2188 NGE_RXFILTCTL_ALLPHYS);
2189 if (!(ifp->if_flags & IFF_ALLMULTI))
2190 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
2191 NGE_RXFILTCTL_ALLMULTI);
2193 ifp->if_flags &= ~IFF_RUNNING;
2197 if (ifp->if_flags & IFF_RUNNING)
2200 sc->nge_if_flags = ifp->if_flags;
2211 error = ifmedia_ioctl(ifp, ifr, &sc->nge_ifmedia,
2214 mii = device_get_softc(sc->nge_miibus);
2215 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
2229 static void nge_watchdog(ifp)
2232 struct nge_softc *sc;
2237 printf("nge%d: watchdog timeout\n", sc->nge_unit);
2241 ifp->if_flags &= ~IFF_RUNNING;
2244 if (ifp->if_snd.ifq_head != NULL)
2251 * Stop the adapter and free any mbufs allocated to the
2254 static void nge_stop(sc)
2255 struct nge_softc *sc;
2259 struct ifmedia_entry *ifm;
2260 struct mii_data *mii;
2263 ifp = &sc->arpcom.ac_if;
2268 mii = device_get_softc(sc->nge_miibus);
2271 callout_stop(&sc->nge_stat_timer);
2272 #ifdef DEVICE_POLLING
2273 ether_poll_deregister(ifp);
2275 CSR_WRITE_4(sc, NGE_IER, 0);
2276 CSR_WRITE_4(sc, NGE_IMR, 0);
2277 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE);
2279 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 0);
2280 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 0);
2283 * Isolate/power down the PHY, but leave the media selection
2284 * unchanged so that things will be put back to normal when
2285 * we bring the interface back up.
2287 itmp = ifp->if_flags;
2288 ifp->if_flags |= IFF_UP;
2291 ifm = sc->nge_ifmedia.ifm_cur;
2293 ifm = mii->mii_media.ifm_cur;
2295 mtmp = ifm->ifm_media;
2296 ifm->ifm_media = IFM_ETHER|IFM_NONE;
2300 ifm->ifm_media = mtmp;
2301 ifp->if_flags = itmp;
2306 * Free data in the RX lists.
2308 for (i = 0; i < NGE_RX_LIST_CNT; i++) {
2309 if (sc->nge_ldata->nge_rx_list[i].nge_mbuf != NULL) {
2310 m_freem(sc->nge_ldata->nge_rx_list[i].nge_mbuf);
2311 sc->nge_ldata->nge_rx_list[i].nge_mbuf = NULL;
2314 bzero((char *)&sc->nge_ldata->nge_rx_list,
2315 sizeof(sc->nge_ldata->nge_rx_list));
2318 * Free the TX list buffers.
2320 for (i = 0; i < NGE_TX_LIST_CNT; i++) {
2321 if (sc->nge_ldata->nge_tx_list[i].nge_mbuf != NULL) {
2322 m_freem(sc->nge_ldata->nge_tx_list[i].nge_mbuf);
2323 sc->nge_ldata->nge_tx_list[i].nge_mbuf = NULL;
2327 bzero((char *)&sc->nge_ldata->nge_tx_list,
2328 sizeof(sc->nge_ldata->nge_tx_list));
2330 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2336 * Stop all chip I/O so that the kernel's probe routines don't
2337 * get confused by errant DMAs when rebooting.
2339 static void nge_shutdown(dev)
2342 struct nge_softc *sc;
2344 sc = device_get_softc(dev);