2 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
3 * Copyright (c) 1992 Terrence R. Lambert.
4 * Copyright (c) 2003 Peter Wemm.
5 * Copyright (c) 2008 The DragonFly Project.
8 * This code is derived from software contributed to Berkeley by
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the University of
22 * California, Berkeley and its contributors.
23 * 4. Neither the name of the University nor the names of its contributors
24 * may be used to endorse or promote products derived from this software
25 * without specific prior written permission.
27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
40 * $FreeBSD: src/sys/i386/i386/machdep.c,v 1.385.2.30 2003/05/31 08:48:05 alc Exp $
43 //#include "use_npx.h"
45 #include "opt_compat.h"
48 #include "opt_directio.h"
50 #include "opt_msgbuf.h"
53 #include <sys/param.h>
54 #include <sys/systm.h>
55 #include <sys/sysproto.h>
56 #include <sys/signalvar.h>
57 #include <sys/kernel.h>
58 #include <sys/linker.h>
59 #include <sys/malloc.h>
63 #include <sys/reboot.h>
65 #include <sys/msgbuf.h>
66 #include <sys/sysent.h>
67 #include <sys/sysctl.h>
68 #include <sys/vmmeter.h>
70 #include <sys/usched.h>
73 #include <sys/ctype.h>
74 #include <sys/serialize.h>
75 #include <sys/systimer.h>
78 #include <vm/vm_param.h>
80 #include <vm/vm_kern.h>
81 #include <vm/vm_object.h>
82 #include <vm/vm_page.h>
83 #include <vm/vm_map.h>
84 #include <vm/vm_pager.h>
85 #include <vm/vm_extern.h>
87 #include <sys/thread2.h>
88 #include <sys/mplock2.h>
89 #include <sys/mutex2.h>
99 #include <machine/cpu.h>
100 #include <machine/clock.h>
101 #include <machine/specialreg.h>
103 #include <machine/bootinfo.h>
105 #include <machine/md_var.h>
106 #include <machine/metadata.h>
107 #include <machine/pc/bios.h>
108 #include <machine/pcb_ext.h> /* pcb.h included via sys/user.h */
109 #include <machine/globaldata.h> /* CPU_prvspace */
110 #include <machine/smp.h>
112 #include <machine/perfmon.h>
114 #include <machine/cputypes.h>
115 #include <machine/intr_machdep.h>
116 #include <machine/framebuffer.h>
119 #include <bus/isa/isa_device.h>
121 #include <machine_base/isa/isa_intr.h>
122 #include <bus/isa/rtc.h>
123 #include <sys/random.h>
124 #include <sys/ptrace.h>
125 #include <machine/sigframe.h>
127 #include <sys/machintr.h>
128 #include <machine_base/icu/icu_abi.h>
129 #include <machine_base/icu/elcr_var.h>
130 #include <machine_base/apic/lapic.h>
131 #include <machine_base/apic/ioapic.h>
132 #include <machine_base/apic/ioapic_abi.h>
133 #include <machine/mptable.h>
135 #define PHYSMAP_ENTRIES 10
137 extern u_int64_t hammer_time(u_int64_t, u_int64_t);
139 extern void printcpuinfo(void); /* XXX header file */
140 extern void identify_cpu(void);
142 extern void finishidentcpu(void);
144 extern void panicifcpuunsupported(void);
146 static void cpu_startup(void *);
147 static void pic_finish(void *);
148 static void cpu_finish(void *);
150 static void set_fpregs_xmm(struct save87 *, struct savexmm *);
151 static void fill_fpregs_xmm(struct savexmm *, struct save87 *);
153 extern void ffs_rawread_setup(void);
154 #endif /* DIRECTIO */
155 static void init_locks(void);
157 extern void pcpu_timer_always(struct intrframe *);
159 SYSINIT(cpu, SI_BOOT2_START_CPU, SI_ORDER_FIRST, cpu_startup, NULL);
160 SYSINIT(pic_finish, SI_BOOT2_FINISH_PIC, SI_ORDER_FIRST, pic_finish, NULL);
161 SYSINIT(cpu_finish, SI_BOOT2_FINISH_CPU, SI_ORDER_FIRST, cpu_finish, NULL);
164 extern vm_offset_t ksym_start, ksym_end;
167 struct privatespace CPU_prvspace_bsp __aligned(4096);
168 struct privatespace *CPU_prvspace[MAXCPU] = { &CPU_prvspace_bsp };
170 int _udatasel, _ucodesel, _ucode32sel;
172 int64_t tsc_offsets[MAXCPU];
173 cpumask_t smp_idleinvl_mask;
174 cpumask_t smp_idleinvl_reqs;
176 static int cpu_mwait_halt_global; /* MWAIT hint (EAX) or CPU_MWAIT_HINT_ */
178 #if defined(SWTCH_OPTIM_STATS)
179 extern int swtch_optim_stats;
180 SYSCTL_INT(_debug, OID_AUTO, swtch_optim_stats,
181 CTLFLAG_RD, &swtch_optim_stats, 0, "");
182 SYSCTL_INT(_debug, OID_AUTO, tlb_flush_count,
183 CTLFLAG_RD, &tlb_flush_count, 0, "");
185 SYSCTL_INT(_hw, OID_AUTO, cpu_mwait_halt,
186 CTLFLAG_RD, &cpu_mwait_halt_global, 0, "");
187 SYSCTL_INT(_hw, OID_AUTO, cpu_mwait_spin, CTLFLAG_RD, &cpu_mwait_spin, 0,
188 "monitor/mwait target state");
190 #define CPU_MWAIT_HAS_CX \
191 ((cpu_feature2 & CPUID2_MON) && \
192 (cpu_mwait_feature & CPUID_MWAIT_EXT))
194 #define CPU_MWAIT_CX_NAMELEN 16
196 #define CPU_MWAIT_C1 1
197 #define CPU_MWAIT_C2 2
198 #define CPU_MWAIT_C3 3
199 #define CPU_MWAIT_CX_MAX 8
201 #define CPU_MWAIT_HINT_AUTO -1 /* C1 and C2 */
202 #define CPU_MWAIT_HINT_AUTODEEP -2 /* C3+ */
204 SYSCTL_NODE(_machdep, OID_AUTO, mwait, CTLFLAG_RW, 0, "MWAIT features");
205 SYSCTL_NODE(_machdep_mwait, OID_AUTO, CX, CTLFLAG_RW, 0, "MWAIT Cx settings");
207 struct cpu_mwait_cx {
210 struct sysctl_ctx_list sysctl_ctx;
211 struct sysctl_oid *sysctl_tree;
213 static struct cpu_mwait_cx cpu_mwait_cx_info[CPU_MWAIT_CX_MAX];
214 static char cpu_mwait_cx_supported[256];
216 static int cpu_mwait_c1_hints_cnt;
217 static int cpu_mwait_hints_cnt;
218 static int *cpu_mwait_hints;
220 static int cpu_mwait_deep_hints_cnt;
221 static int *cpu_mwait_deep_hints;
223 #define CPU_IDLE_REPEAT_DEFAULT 750
225 static u_int cpu_idle_repeat = CPU_IDLE_REPEAT_DEFAULT;
226 static u_long cpu_idle_repeat_max = CPU_IDLE_REPEAT_DEFAULT;
227 static u_int cpu_mwait_repeat_shift = 1;
229 #define CPU_MWAIT_C3_PREAMBLE_BM_ARB 0x1
230 #define CPU_MWAIT_C3_PREAMBLE_BM_STS 0x2
232 static int cpu_mwait_c3_preamble =
233 CPU_MWAIT_C3_PREAMBLE_BM_ARB |
234 CPU_MWAIT_C3_PREAMBLE_BM_STS;
236 SYSCTL_STRING(_machdep_mwait_CX, OID_AUTO, supported, CTLFLAG_RD,
237 cpu_mwait_cx_supported, 0, "MWAIT supported C states");
238 SYSCTL_INT(_machdep_mwait_CX, OID_AUTO, c3_preamble, CTLFLAG_RD,
239 &cpu_mwait_c3_preamble, 0, "C3+ preamble mask");
241 static int cpu_mwait_cx_select_sysctl(SYSCTL_HANDLER_ARGS,
243 static int cpu_mwait_cx_idle_sysctl(SYSCTL_HANDLER_ARGS);
244 static int cpu_mwait_cx_pcpu_idle_sysctl(SYSCTL_HANDLER_ARGS);
245 static int cpu_mwait_cx_spin_sysctl(SYSCTL_HANDLER_ARGS);
247 SYSCTL_PROC(_machdep_mwait_CX, OID_AUTO, idle, CTLTYPE_STRING|CTLFLAG_RW,
248 NULL, 0, cpu_mwait_cx_idle_sysctl, "A", "");
249 SYSCTL_PROC(_machdep_mwait_CX, OID_AUTO, spin, CTLTYPE_STRING|CTLFLAG_RW,
250 NULL, 0, cpu_mwait_cx_spin_sysctl, "A", "");
251 SYSCTL_UINT(_machdep_mwait_CX, OID_AUTO, repeat_shift, CTLFLAG_RW,
252 &cpu_mwait_repeat_shift, 0, "");
256 u_long ebda_addr = 0;
258 int imcr_present = 0;
260 int naps = 0; /* # of Applications processors */
263 struct mtx dt_lock; /* lock for GDT and LDT */
266 sysctl_hw_physmem(SYSCTL_HANDLER_ARGS)
268 u_long pmem = ctob(physmem);
270 int error = sysctl_handle_long(oidp, &pmem, 0, req);
274 SYSCTL_PROC(_hw, HW_PHYSMEM, physmem, CTLTYPE_ULONG|CTLFLAG_RD,
275 0, 0, sysctl_hw_physmem, "LU", "Total system memory in bytes (number of pages * page size)");
278 sysctl_hw_usermem(SYSCTL_HANDLER_ARGS)
280 int error = sysctl_handle_int(oidp, 0,
281 ctob(physmem - vmstats.v_wire_count), req);
285 SYSCTL_PROC(_hw, HW_USERMEM, usermem, CTLTYPE_INT|CTLFLAG_RD,
286 0, 0, sysctl_hw_usermem, "IU", "");
289 sysctl_hw_availpages(SYSCTL_HANDLER_ARGS)
291 int error = sysctl_handle_int(oidp, 0,
292 x86_64_btop(avail_end - avail_start), req);
296 SYSCTL_PROC(_hw, OID_AUTO, availpages, CTLTYPE_INT|CTLFLAG_RD,
297 0, 0, sysctl_hw_availpages, "I", "");
303 * The number of PHYSMAP entries must be one less than the number of
304 * PHYSSEG entries because the PHYSMAP entry that spans the largest
305 * physical address that is accessible by ISA DMA is split into two
308 #define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1))
310 vm_paddr_t phys_avail[PHYSMAP_SIZE + 2];
311 vm_paddr_t dump_avail[PHYSMAP_SIZE + 2];
313 /* must be 2 less so 0 0 can signal end of chunks */
314 #define PHYS_AVAIL_ARRAY_END (NELEM(phys_avail) - 2)
315 #define DUMP_AVAIL_ARRAY_END (NELEM(dump_avail) - 2)
317 static vm_offset_t buffer_sva, buffer_eva;
318 vm_offset_t clean_sva, clean_eva;
319 static vm_offset_t pager_sva, pager_eva;
320 static struct trapframe proc0_tf;
323 cpu_startup(void *dummy)
327 vm_offset_t firstaddr;
330 * Good {morning,afternoon,evening,night}.
332 kprintf("%s", version);
335 panicifcpuunsupported();
339 kprintf("real memory = %ju (%ju MB)\n",
341 (intmax_t)Realmem / 1024 / 1024);
343 * Display any holes after the first chunk of extended memory.
348 kprintf("Physical memory chunk(s):\n");
349 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) {
350 vm_paddr_t size1 = phys_avail[indx + 1] - phys_avail[indx];
352 kprintf("0x%08jx - 0x%08jx, %ju bytes (%ju pages)\n",
353 (intmax_t)phys_avail[indx],
354 (intmax_t)phys_avail[indx + 1] - 1,
356 (intmax_t)(size1 / PAGE_SIZE));
361 * Allocate space for system data structures.
362 * The first available kernel virtual address is in "v".
363 * As pages of kernel virtual memory are allocated, "v" is incremented.
364 * As pages of memory are allocated and cleared,
365 * "firstaddr" is incremented.
366 * An index into the kernel page table corresponding to the
367 * virtual memory address maintained in "v" is kept in "mapaddr".
371 * Make two passes. The first pass calculates how much memory is
372 * needed and allocates it. The second pass assigns virtual
373 * addresses to the various data structures.
377 v = (caddr_t)firstaddr;
379 #define valloc(name, type, num) \
380 (name) = (type *)v; v = (caddr_t)((name)+(num))
381 #define valloclim(name, type, num, lim) \
382 (name) = (type *)v; v = (caddr_t)((lim) = ((name)+(num)))
385 * The nominal buffer size (and minimum KVA allocation) is BKVASIZE.
386 * For the first 64MB of ram nominally allocate sufficient buffers to
387 * cover 1/4 of our ram. Beyond the first 64MB allocate additional
388 * buffers to cover 1/20 of our ram over 64MB. When auto-sizing
389 * the buffer cache we limit the eventual kva reservation to
392 * factor represents the 1/4 x ram conversion.
395 long factor = 4 * BKVASIZE / 1024;
396 long kbytes = physmem * (PAGE_SIZE / 1024);
400 nbuf += min((kbytes - 4096) / factor, 65536 / factor);
402 nbuf += (kbytes - 65536) * 2 / (factor * 5);
403 if (maxbcache && nbuf > maxbcache / BKVASIZE)
404 nbuf = maxbcache / BKVASIZE;
408 * Do not allow the buffer_map to be more then 1/2 the size of the
411 if (nbuf > (virtual_end - virtual_start +
412 virtual2_end - virtual2_start) / (BKVASIZE * 2)) {
413 nbuf = (virtual_end - virtual_start +
414 virtual2_end - virtual2_start) / (BKVASIZE * 2);
415 kprintf("Warning: nbufs capped at %ld due to kvm\n", nbuf);
419 * Do not allow the buffer_map to use more than 50% of available
420 * physical-equivalent memory. Since the VM pages which back
421 * individual buffers are typically wired, having too many bufs
422 * can prevent the system from paging properly.
424 if (nbuf > physmem * PAGE_SIZE / (BKVASIZE * 2)) {
425 nbuf = physmem * PAGE_SIZE / (BKVASIZE * 2);
426 kprintf("Warning: nbufs capped at %ld due to physmem\n", nbuf);
430 * Do not allow the sizeof(struct buf) * nbuf to exceed half of
431 * the valloc space which is just the virtual_end - virtual_start
432 * section. We use valloc() to allocate the buf header array.
434 if (nbuf > (virtual_end - virtual_start) / sizeof(struct buf) / 2) {
435 nbuf = (virtual_end - virtual_start) /
436 sizeof(struct buf) / 2;
437 kprintf("Warning: nbufs capped at %ld due to valloc "
438 "considerations", nbuf);
441 nswbuf = lmax(lmin(nbuf / 4, 256), 16);
443 if (nswbuf < NSWBUF_MIN)
450 valloc(swbuf, struct buf, nswbuf);
451 valloc(buf, struct buf, nbuf);
454 * End of first pass, size has been calculated so allocate memory
456 if (firstaddr == 0) {
457 size = (vm_size_t)(v - firstaddr);
458 firstaddr = kmem_alloc(&kernel_map, round_page(size));
460 panic("startup: no room for tables");
465 * End of second pass, addresses have been assigned
467 * nbuf is an int, make sure we don't overflow the field.
469 * On 64-bit systems we always reserve maximal allocations for
470 * buffer cache buffers and there are no fragmentation issues,
471 * so the KVA segment does not have to be excessively oversized.
473 if ((vm_size_t)(v - firstaddr) != size)
474 panic("startup: table size inconsistency");
476 kmem_suballoc(&kernel_map, &clean_map, &clean_sva, &clean_eva,
477 ((vm_offset_t)(nbuf + 16) * BKVASIZE) +
478 (nswbuf * MAXPHYS) + pager_map_size);
479 kmem_suballoc(&clean_map, &buffer_map, &buffer_sva, &buffer_eva,
480 ((vm_offset_t)(nbuf + 16) * BKVASIZE));
481 buffer_map.system_map = 1;
482 kmem_suballoc(&clean_map, &pager_map, &pager_sva, &pager_eva,
483 ((vm_offset_t)nswbuf * MAXPHYS) + pager_map_size);
484 pager_map.system_map = 1;
485 kprintf("avail memory = %ju (%ju MB)\n",
486 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages),
487 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages) /
491 struct cpu_idle_stat {
499 u_long mwait_cx[CPU_MWAIT_CX_MAX];
502 #define CPU_IDLE_STAT_HALT -1
503 #define CPU_IDLE_STAT_SPIN -2
505 static struct cpu_idle_stat cpu_idle_stats[MAXCPU];
508 sysctl_cpu_idle_cnt(SYSCTL_HANDLER_ARGS)
510 int idx = arg2, cpu, error;
513 if (idx == CPU_IDLE_STAT_HALT) {
514 for (cpu = 0; cpu < ncpus; ++cpu)
515 val += cpu_idle_stats[cpu].halt;
516 } else if (idx == CPU_IDLE_STAT_SPIN) {
517 for (cpu = 0; cpu < ncpus; ++cpu)
518 val += cpu_idle_stats[cpu].spin;
520 KASSERT(idx >= 0 && idx < CPU_MWAIT_CX_MAX,
521 ("invalid index %d", idx));
522 for (cpu = 0; cpu < ncpus; ++cpu)
523 val += cpu_idle_stats[cpu].mwait_cx[idx];
526 error = sysctl_handle_quad(oidp, &val, 0, req);
527 if (error || req->newptr == NULL)
530 if (idx == CPU_IDLE_STAT_HALT) {
531 for (cpu = 0; cpu < ncpus; ++cpu)
532 cpu_idle_stats[cpu].halt = 0;
533 cpu_idle_stats[0].halt = val;
534 } else if (idx == CPU_IDLE_STAT_SPIN) {
535 for (cpu = 0; cpu < ncpus; ++cpu)
536 cpu_idle_stats[cpu].spin = 0;
537 cpu_idle_stats[0].spin = val;
539 KASSERT(idx >= 0 && idx < CPU_MWAIT_CX_MAX,
540 ("invalid index %d", idx));
541 for (cpu = 0; cpu < ncpus; ++cpu)
542 cpu_idle_stats[cpu].mwait_cx[idx] = 0;
543 cpu_idle_stats[0].mwait_cx[idx] = val;
549 cpu_mwait_attach(void)
554 if (!CPU_MWAIT_HAS_CX)
557 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
558 (CPUID_TO_FAMILY(cpu_id) > 0xf ||
559 (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
560 CPUID_TO_MODEL(cpu_id) >= 0xf))) {
564 * Pentium dual-core, Core 2 and beyond do not need any
565 * additional activities to enter deep C-state, i.e. C3(+).
567 cpu_mwait_cx_no_bmarb();
569 TUNABLE_INT_FETCH("machdep.cpu.mwait.bm_sts", &bm_sts);
571 cpu_mwait_cx_no_bmsts();
574 sbuf_new(&sb, cpu_mwait_cx_supported,
575 sizeof(cpu_mwait_cx_supported), SBUF_FIXEDLEN);
577 for (i = 0; i < CPU_MWAIT_CX_MAX; ++i) {
578 struct cpu_mwait_cx *cx = &cpu_mwait_cx_info[i];
581 ksnprintf(cx->name, sizeof(cx->name), "C%d", i);
583 sysctl_ctx_init(&cx->sysctl_ctx);
584 cx->sysctl_tree = SYSCTL_ADD_NODE(&cx->sysctl_ctx,
585 SYSCTL_STATIC_CHILDREN(_machdep_mwait), OID_AUTO,
586 cx->name, CTLFLAG_RW, NULL, "Cx control/info");
587 if (cx->sysctl_tree == NULL)
590 cx->subcnt = CPUID_MWAIT_CX_SUBCNT(cpu_mwait_extemu, i);
591 SYSCTL_ADD_INT(&cx->sysctl_ctx,
592 SYSCTL_CHILDREN(cx->sysctl_tree), OID_AUTO,
593 "subcnt", CTLFLAG_RD, &cx->subcnt, 0,
595 SYSCTL_ADD_PROC(&cx->sysctl_ctx,
596 SYSCTL_CHILDREN(cx->sysctl_tree), OID_AUTO,
597 "entered", (CTLTYPE_QUAD | CTLFLAG_RW), 0,
598 i, sysctl_cpu_idle_cnt, "Q", "# of times entered");
600 for (sub = 0; sub < cx->subcnt; ++sub)
601 sbuf_printf(&sb, "C%d/%d ", i, sub);
609 cpu_mwait_c1_hints_cnt = cpu_mwait_cx_info[CPU_MWAIT_C1].subcnt;
610 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_C3; ++i)
611 cpu_mwait_hints_cnt += cpu_mwait_cx_info[i].subcnt;
612 cpu_mwait_hints = kmalloc(sizeof(int) * cpu_mwait_hints_cnt,
616 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_C3; ++i) {
619 subcnt = cpu_mwait_cx_info[i].subcnt;
620 for (j = 0; j < subcnt; ++j) {
621 KASSERT(hint_idx < cpu_mwait_hints_cnt,
622 ("invalid mwait hint index %d", hint_idx));
623 cpu_mwait_hints[hint_idx] = MWAIT_EAX_HINT(i, j);
627 KASSERT(hint_idx == cpu_mwait_hints_cnt,
628 ("mwait hint count %d != index %d",
629 cpu_mwait_hints_cnt, hint_idx));
632 kprintf("MWAIT hints (%d C1 hints):\n", cpu_mwait_c1_hints_cnt);
633 for (i = 0; i < cpu_mwait_hints_cnt; ++i) {
634 int hint = cpu_mwait_hints[i];
636 kprintf(" C%d/%d hint 0x%04x\n",
637 MWAIT_EAX_TO_CX(hint), MWAIT_EAX_TO_CX_SUB(hint),
645 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_CX_MAX; ++i)
646 cpu_mwait_deep_hints_cnt += cpu_mwait_cx_info[i].subcnt;
647 cpu_mwait_deep_hints = kmalloc(sizeof(int) * cpu_mwait_deep_hints_cnt,
651 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_CX_MAX; ++i) {
654 subcnt = cpu_mwait_cx_info[i].subcnt;
655 for (j = 0; j < subcnt; ++j) {
656 KASSERT(hint_idx < cpu_mwait_deep_hints_cnt,
657 ("invalid mwait deep hint index %d", hint_idx));
658 cpu_mwait_deep_hints[hint_idx] = MWAIT_EAX_HINT(i, j);
662 KASSERT(hint_idx == cpu_mwait_deep_hints_cnt,
663 ("mwait deep hint count %d != index %d",
664 cpu_mwait_deep_hints_cnt, hint_idx));
667 kprintf("MWAIT deep hints:\n");
668 for (i = 0; i < cpu_mwait_deep_hints_cnt; ++i) {
669 int hint = cpu_mwait_deep_hints[i];
671 kprintf(" C%d/%d hint 0x%04x\n",
672 MWAIT_EAX_TO_CX(hint), MWAIT_EAX_TO_CX_SUB(hint),
676 cpu_idle_repeat_max = 256 * cpu_mwait_deep_hints_cnt;
678 for (i = 0; i < ncpus; ++i) {
681 ksnprintf(name, sizeof(name), "idle%d", i);
682 SYSCTL_ADD_PROC(NULL,
683 SYSCTL_STATIC_CHILDREN(_machdep_mwait_CX), OID_AUTO,
684 name, (CTLTYPE_STRING | CTLFLAG_RW), &cpu_idle_stats[i],
685 0, cpu_mwait_cx_pcpu_idle_sysctl, "A", "");
690 cpu_finish(void *dummy __unused)
697 pic_finish(void *dummy __unused)
699 /* Log ELCR information */
702 /* Log MPTABLE information */
703 mptable_pci_int_dump();
706 MachIntrABI.finalize();
710 * Send an interrupt to process.
712 * Stack is set up to allow sigcode stored
713 * at top to call routine, followed by kcall
714 * to sigreturn routine below. After sigreturn
715 * resets the signal mask, the stack, and the
716 * frame pointer, it returns to the user
720 sendsig(sig_t catcher, int sig, sigset_t *mask, u_long code)
722 struct lwp *lp = curthread->td_lwp;
723 struct proc *p = lp->lwp_proc;
724 struct trapframe *regs;
725 struct sigacts *psp = p->p_sigacts;
726 struct sigframe sf, *sfp;
730 regs = lp->lwp_md.md_regs;
731 oonstack = (lp->lwp_sigstk.ss_flags & SS_ONSTACK) ? 1 : 0;
733 /* Save user context */
734 bzero(&sf, sizeof(struct sigframe));
735 sf.sf_uc.uc_sigmask = *mask;
736 sf.sf_uc.uc_stack = lp->lwp_sigstk;
737 sf.sf_uc.uc_mcontext.mc_onstack = oonstack;
738 KKASSERT(__offsetof(struct trapframe, tf_rdi) == 0);
739 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(struct trapframe));
741 /* Make the size of the saved context visible to userland */
742 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext);
744 /* Allocate and validate space for the signal handler context. */
745 if ((lp->lwp_flags & LWP_ALTSTACK) != 0 && !oonstack &&
746 SIGISMEMBER(psp->ps_sigonstack, sig)) {
747 sp = (char *)(lp->lwp_sigstk.ss_sp + lp->lwp_sigstk.ss_size -
748 sizeof(struct sigframe));
749 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
751 /* We take red zone into account */
752 sp = (char *)regs->tf_rsp - sizeof(struct sigframe) - 128;
756 * XXX AVX needs 64-byte alignment but sigframe has other fields and
757 * the embedded ucontext is not at the front, so aligning this won't
758 * help us. Fortunately we bcopy in/out of the sigframe, so the
761 * The problem though is if userland winds up trying to use the
764 sfp = (struct sigframe *)((intptr_t)sp & ~(intptr_t)0xF);
766 /* Translate the signal is appropriate */
767 if (p->p_sysent->sv_sigtbl) {
768 if (sig <= p->p_sysent->sv_sigsize)
769 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)];
773 * Build the argument list for the signal handler.
775 * Arguments are in registers (%rdi, %rsi, %rdx, %rcx)
777 regs->tf_rdi = sig; /* argument 1 */
778 regs->tf_rdx = (register_t)&sfp->sf_uc; /* argument 3 */
780 if (SIGISMEMBER(psp->ps_siginfo, sig)) {
782 * Signal handler installed with SA_SIGINFO.
784 * action(signo, siginfo, ucontext)
786 regs->tf_rsi = (register_t)&sfp->sf_si; /* argument 2 */
787 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */
788 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher;
790 /* fill siginfo structure */
791 sf.sf_si.si_signo = sig;
792 sf.sf_si.si_code = code;
793 sf.sf_si.si_addr = (void *)regs->tf_addr;
796 * Old FreeBSD-style arguments.
798 * handler (signo, code, [uc], addr)
800 regs->tf_rsi = (register_t)code; /* argument 2 */
801 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */
802 sf.sf_ahu.sf_handler = catcher;
806 * If we're a vm86 process, we want to save the segment registers.
807 * We also change eflags to be our emulated eflags, not the actual
811 if (regs->tf_eflags & PSL_VM) {
812 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
813 struct vm86_kernel *vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
815 sf.sf_uc.uc_mcontext.mc_gs = tf->tf_vm86_gs;
816 sf.sf_uc.uc_mcontext.mc_fs = tf->tf_vm86_fs;
817 sf.sf_uc.uc_mcontext.mc_es = tf->tf_vm86_es;
818 sf.sf_uc.uc_mcontext.mc_ds = tf->tf_vm86_ds;
820 if (vm86->vm86_has_vme == 0)
821 sf.sf_uc.uc_mcontext.mc_eflags =
822 (tf->tf_eflags & ~(PSL_VIF | PSL_VIP)) |
823 (vm86->vm86_eflags & (PSL_VIF | PSL_VIP));
826 * Clear PSL_NT to inhibit T_TSSFLT faults on return from
827 * syscalls made by the signal handler. This just avoids
828 * wasting time for our lazy fixup of such faults. PSL_NT
829 * does nothing in vm86 mode, but vm86 programs can set it
830 * almost legitimately in probes for old cpu types.
832 tf->tf_eflags &= ~(PSL_VM | PSL_NT | PSL_VIF | PSL_VIP);
837 * Save the FPU state and reinit the FP unit
839 npxpush(&sf.sf_uc.uc_mcontext);
842 * Copy the sigframe out to the user's stack.
844 if (copyout(&sf, sfp, sizeof(struct sigframe)) != 0) {
846 * Something is wrong with the stack pointer.
847 * ...Kill the process.
852 regs->tf_rsp = (register_t)sfp;
853 regs->tf_rip = PS_STRINGS - *(p->p_sysent->sv_szsigcode);
856 * i386 abi specifies that the direction flag must be cleared
859 regs->tf_rflags &= ~(PSL_T|PSL_D);
862 * 64 bit mode has a code and stack selector but
863 * no data or extra selector. %fs and %gs are not
866 regs->tf_cs = _ucodesel;
867 regs->tf_ss = _udatasel;
872 * Sanitize the trapframe for a virtual kernel passing control to a custom
873 * VM context. Remove any items that would otherwise create a privilage
876 * XXX at the moment we allow userland to set the resume flag. Is this a
880 cpu_sanitize_frame(struct trapframe *frame)
882 frame->tf_cs = _ucodesel;
883 frame->tf_ss = _udatasel;
884 /* XXX VM (8086) mode not supported? */
885 frame->tf_rflags &= (PSL_RF | PSL_USERCHANGE | PSL_VM_UNSUPP);
886 frame->tf_rflags |= PSL_RESERVED_DEFAULT | PSL_I;
892 * Sanitize the tls so loading the descriptor does not blow up
893 * on us. For x86_64 we don't have to do anything.
896 cpu_sanitize_tls(struct savetls *tls)
902 * sigreturn(ucontext_t *sigcntxp)
904 * System call to cleanup state after a signal
905 * has been taken. Reset signal mask and
906 * stack state from context left by sendsig (above).
907 * Return to previous pc and psl as specified by
908 * context left by sendsig. Check carefully to
909 * make sure that the user has not modified the
910 * state to gain improper privileges.
914 #define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0)
915 #define CS_SECURE(cs) (ISPL(cs) == SEL_UPL)
918 sys_sigreturn(struct sigreturn_args *uap)
920 struct lwp *lp = curthread->td_lwp;
921 struct trapframe *regs;
929 * We have to copy the information into kernel space so userland
930 * can't modify it while we are sniffing it.
932 regs = lp->lwp_md.md_regs;
933 error = copyin(uap->sigcntxp, &uc, sizeof(uc));
937 rflags = ucp->uc_mcontext.mc_rflags;
939 /* VM (8086) mode not supported */
940 rflags &= ~PSL_VM_UNSUPP;
943 if (eflags & PSL_VM) {
944 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
945 struct vm86_kernel *vm86;
948 * if pcb_ext == 0 or vm86_inited == 0, the user hasn't
949 * set up the vm86 area, and we can't enter vm86 mode.
951 if (lp->lwp_thread->td_pcb->pcb_ext == 0)
953 vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
954 if (vm86->vm86_inited == 0)
957 /* go back to user mode if both flags are set */
958 if ((eflags & PSL_VIP) && (eflags & PSL_VIF))
959 trapsignal(lp, SIGBUS, 0);
961 if (vm86->vm86_has_vme) {
962 eflags = (tf->tf_eflags & ~VME_USERCHANGE) |
963 (eflags & VME_USERCHANGE) | PSL_VM;
965 vm86->vm86_eflags = eflags; /* save VIF, VIP */
966 eflags = (tf->tf_eflags & ~VM_USERCHANGE) |
967 (eflags & VM_USERCHANGE) | PSL_VM;
969 bcopy(&ucp->uc_mcontext.mc_gs, tf, sizeof(struct trapframe));
970 tf->tf_eflags = eflags;
971 tf->tf_vm86_ds = tf->tf_ds;
972 tf->tf_vm86_es = tf->tf_es;
973 tf->tf_vm86_fs = tf->tf_fs;
974 tf->tf_vm86_gs = tf->tf_gs;
975 tf->tf_ds = _udatasel;
976 tf->tf_es = _udatasel;
977 tf->tf_fs = _udatasel;
978 tf->tf_gs = _udatasel;
983 * Don't allow users to change privileged or reserved flags.
986 * XXX do allow users to change the privileged flag PSL_RF.
987 * The cpu sets PSL_RF in tf_eflags for faults. Debuggers
988 * should sometimes set it there too. tf_eflags is kept in
989 * the signal context during signal handling and there is no
990 * other place to remember it, so the PSL_RF bit may be
991 * corrupted by the signal handler without us knowing.
992 * Corruption of the PSL_RF bit at worst causes one more or
993 * one less debugger trap, so allowing it is fairly harmless.
995 if (!EFL_SECURE(rflags & ~PSL_RF, regs->tf_rflags & ~PSL_RF)) {
996 kprintf("sigreturn: rflags = 0x%lx\n", (long)rflags);
1001 * Don't allow users to load a valid privileged %cs. Let the
1002 * hardware check for invalid selectors, excess privilege in
1003 * other selectors, invalid %eip's and invalid %esp's.
1005 cs = ucp->uc_mcontext.mc_cs;
1006 if (!CS_SECURE(cs)) {
1007 kprintf("sigreturn: cs = 0x%x\n", cs);
1008 trapsignal(lp, SIGBUS, T_PROTFLT);
1011 bcopy(&ucp->uc_mcontext.mc_rdi, regs, sizeof(struct trapframe));
1015 * Restore the FPU state from the frame
1018 npxpop(&ucp->uc_mcontext);
1020 if (ucp->uc_mcontext.mc_onstack & 1)
1021 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
1023 lp->lwp_sigstk.ss_flags &= ~SS_ONSTACK;
1025 lp->lwp_sigmask = ucp->uc_sigmask;
1026 SIG_CANTMASK(lp->lwp_sigmask);
1029 return(EJUSTRETURN);
1033 * Machine dependent boot() routine
1035 * I haven't seen anything to put here yet
1036 * Possibly some stuff might be grafted back here from boot()
1044 * Shutdown the CPU as much as possible
1050 __asm__ __volatile("hlt");
1054 * cpu_idle() represents the idle LWKT. You cannot return from this function
1055 * (unless you want to blow things up!). Instead we look for runnable threads
1056 * and loop or halt as appropriate. Giant is not held on entry to the thread.
1058 * The main loop is entered with a critical section held, we must release
1059 * the critical section before doing anything else. lwkt_switch() will
1060 * check for pending interrupts due to entering and exiting its own
1063 * NOTE: On an SMP system we rely on a scheduler IPI to wake a HLTed cpu up.
1064 * However, there are cases where the idlethread will be entered with
1065 * the possibility that no IPI will occur and in such cases
1066 * lwkt_switch() sets TDF_IDLE_NOHLT.
1068 * NOTE: cpu_idle_repeat determines how many entries into the idle thread
1069 * must occur before it starts using ACPI halt.
1071 * NOTE: Value overridden in hammer_time().
1073 static int cpu_idle_hlt = 2;
1074 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hlt, CTLFLAG_RW,
1075 &cpu_idle_hlt, 0, "Idle loop HLT enable");
1076 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_repeat, CTLFLAG_RW,
1077 &cpu_idle_repeat, 0, "Idle entries before acpi hlt");
1079 SYSCTL_PROC(_machdep, OID_AUTO, cpu_idle_hltcnt, (CTLTYPE_QUAD | CTLFLAG_RW),
1080 0, CPU_IDLE_STAT_HALT, sysctl_cpu_idle_cnt, "Q", "Idle loop entry halts");
1081 SYSCTL_PROC(_machdep, OID_AUTO, cpu_idle_spincnt, (CTLTYPE_QUAD | CTLFLAG_RW),
1082 0, CPU_IDLE_STAT_SPIN, sysctl_cpu_idle_cnt, "Q", "Idle loop entry spins");
1085 cpu_idle_default_hook(void)
1088 * We must guarentee that hlt is exactly the instruction
1089 * following the sti.
1091 __asm __volatile("sti; hlt");
1094 /* Other subsystems (e.g., ACPI) can hook this later. */
1095 void (*cpu_idle_hook)(void) = cpu_idle_default_hook;
1098 cpu_mwait_cx_hint(struct cpu_idle_stat *stat)
1107 idx = (stat->repeat + stat->repeat_last + stat->repeat_delta) >>
1108 cpu_mwait_repeat_shift;
1109 if (idx >= cpu_mwait_c1_hints_cnt) {
1110 /* Step up faster, once we walked through all C1 states */
1111 stat->repeat_delta += 1 << (cpu_mwait_repeat_shift + 1);
1113 if (hint == CPU_MWAIT_HINT_AUTODEEP) {
1114 if (idx >= cpu_mwait_deep_hints_cnt)
1115 idx = cpu_mwait_deep_hints_cnt - 1;
1116 hint = cpu_mwait_deep_hints[idx];
1118 if (idx >= cpu_mwait_hints_cnt)
1119 idx = cpu_mwait_hints_cnt - 1;
1120 hint = cpu_mwait_hints[idx];
1123 cx_idx = MWAIT_EAX_TO_CX(hint);
1124 if (cx_idx >= 0 && cx_idx < CPU_MWAIT_CX_MAX)
1125 stat->mwait_cx[cx_idx]++;
1132 globaldata_t gd = mycpu;
1133 struct cpu_idle_stat *stat = &cpu_idle_stats[gd->gd_cpuid];
1134 struct thread *td __debugvar = gd->gd_curthread;
1138 stat->repeat = stat->repeat_last = cpu_idle_repeat_max;
1141 KKASSERT(td->td_critcount == 0);
1145 * See if there are any LWKTs ready to go.
1150 * When halting inside a cli we must check for reqflags
1151 * races, particularly [re]schedule requests. Running
1152 * splz() does the job.
1155 * 0 Never halt, just spin
1157 * 1 Always use HLT (or MONITOR/MWAIT if avail).
1159 * Better default for modern (Haswell+) Intel
1162 * 2 Use HLT/MONITOR/MWAIT up to a point and then
1163 * use the ACPI halt (default). This is a hybrid
1164 * approach. See machdep.cpu_idle_repeat.
1166 * Better default for modern AMD cpus and older
1169 * 3 Always use the ACPI halt. This typically
1170 * eats the least amount of power but the cpu
1171 * will be slow waking up. Slows down e.g.
1172 * compiles and other pipe/event oriented stuff.
1176 * NOTE: Interrupts are enabled and we are not in a critical
1179 * NOTE: Preemptions do not reset gd_idle_repeat. Also we
1180 * don't bother capping gd_idle_repeat, it is ok if
1183 * Implement optimized invltlb operations when halted
1184 * in idle. By setting the bit in smp_idleinvl_mask
1185 * we inform other cpus that they can set _reqs to
1186 * request an invltlb. Current the code to do that
1187 * sets the bits in _reqs anyway, but then check _mask
1188 * to determine if they can assume the invltlb will execute.
1190 * A critical section is required to ensure that interrupts
1191 * do not fully run until after we've had a chance to execute
1194 if (gd->gd_idle_repeat == 0) {
1195 stat->repeat = (stat->repeat + stat->repeat_last) >> 1;
1196 if (stat->repeat > cpu_idle_repeat_max)
1197 stat->repeat = cpu_idle_repeat_max;
1198 stat->repeat_last = 0;
1199 stat->repeat_delta = 0;
1201 ++stat->repeat_last;
1203 ++gd->gd_idle_repeat;
1204 reqflags = gd->gd_reqflags;
1205 quick = (cpu_idle_hlt == 1) ||
1206 (cpu_idle_hlt < 3 &&
1207 gd->gd_idle_repeat < cpu_idle_repeat);
1209 if (quick && (cpu_mi_feature & CPU_MI_MONITOR) &&
1210 (reqflags & RQF_IDLECHECK_WK_MASK) == 0) {
1213 ATOMIC_CPUMASK_ORBIT(smp_idleinvl_mask, gd->gd_cpuid);
1214 cpu_mmw_pause_int(&gd->gd_reqflags, reqflags,
1215 cpu_mwait_cx_hint(stat), 0);
1217 ATOMIC_CPUMASK_NANDBIT(smp_idleinvl_mask, gd->gd_cpuid);
1218 if (ATOMIC_CPUMASK_TESTANDCLR(smp_idleinvl_reqs,
1223 } else if (cpu_idle_hlt) {
1224 __asm __volatile("cli");
1227 ATOMIC_CPUMASK_ORBIT(smp_idleinvl_mask, gd->gd_cpuid);
1228 if ((gd->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) {
1230 cpu_idle_default_hook();
1234 __asm __volatile("sti");
1236 ATOMIC_CPUMASK_NANDBIT(smp_idleinvl_mask, gd->gd_cpuid);
1237 if (ATOMIC_CPUMASK_TESTANDCLR(smp_idleinvl_reqs,
1244 __asm __volatile("sti");
1251 * This routine is called if a spinlock has been held through the
1252 * exponential backoff period and is seriously contested. On a real cpu
1256 cpu_spinlock_contested(void)
1262 * Clear registers on exec
1265 exec_setregs(u_long entry, u_long stack, u_long ps_strings)
1267 struct thread *td = curthread;
1268 struct lwp *lp = td->td_lwp;
1269 struct pcb *pcb = td->td_pcb;
1270 struct trapframe *regs = lp->lwp_md.md_regs;
1272 /* was i386_user_cleanup() in NetBSD */
1276 bzero((char *)regs, sizeof(struct trapframe));
1277 regs->tf_rip = entry;
1278 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8; /* align the stack */
1279 regs->tf_rdi = stack; /* argv */
1280 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T);
1281 regs->tf_ss = _udatasel;
1282 regs->tf_cs = _ucodesel;
1283 regs->tf_rbx = ps_strings;
1286 * Reset the hardware debug registers if they were in use.
1287 * They won't have any meaning for the newly exec'd process.
1289 if (pcb->pcb_flags & PCB_DBREGS) {
1295 pcb->pcb_dr7 = 0; /* JG set bit 10? */
1296 if (pcb == td->td_pcb) {
1298 * Clear the debug registers on the running
1299 * CPU, otherwise they will end up affecting
1300 * the next process we switch to.
1304 pcb->pcb_flags &= ~PCB_DBREGS;
1308 * Initialize the math emulator (if any) for the current process.
1309 * Actually, just clear the bit that says that the emulator has
1310 * been initialized. Initialization is delayed until the process
1311 * traps to the emulator (if it is done at all) mainly because
1312 * emulators don't provide an entry point for initialization.
1314 pcb->pcb_flags &= ~FP_SOFTFP;
1317 * NOTE: do not set CR0_TS here. npxinit() must do it after clearing
1318 * gd_npxthread. Otherwise a preemptive interrupt thread
1319 * may panic in npxdna().
1322 load_cr0(rcr0() | CR0_MP);
1325 * NOTE: The MSR values must be correct so we can return to
1326 * userland. gd_user_fs/gs must be correct so the switch
1327 * code knows what the current MSR values are.
1329 pcb->pcb_fsbase = 0; /* Values loaded from PCB on switch */
1330 pcb->pcb_gsbase = 0;
1331 mdcpu->gd_user_fs = 0; /* Cache of current MSR values */
1332 mdcpu->gd_user_gs = 0;
1333 wrmsr(MSR_FSBASE, 0); /* Set MSR values for return to userland */
1334 wrmsr(MSR_KGSBASE, 0);
1336 /* Initialize the npx (if any) for the current process. */
1340 pcb->pcb_ds = _udatasel;
1341 pcb->pcb_es = _udatasel;
1342 pcb->pcb_fs = _udatasel;
1343 pcb->pcb_gs = _udatasel;
1352 cr0 |= CR0_NE; /* Done by npxinit() */
1353 cr0 |= CR0_MP | CR0_TS; /* Done at every execve() too. */
1354 cr0 |= CR0_WP | CR0_AM;
1360 sysctl_machdep_adjkerntz(SYSCTL_HANDLER_ARGS)
1363 error = sysctl_handle_int(oidp, oidp->oid_arg1, oidp->oid_arg2,
1365 if (!error && req->newptr)
1370 SYSCTL_PROC(_machdep, CPU_ADJKERNTZ, adjkerntz, CTLTYPE_INT|CTLFLAG_RW,
1371 &adjkerntz, 0, sysctl_machdep_adjkerntz, "I", "");
1373 SYSCTL_INT(_machdep, CPU_DISRTCSET, disable_rtc_set,
1374 CTLFLAG_RW, &disable_rtc_set, 0, "");
1377 SYSCTL_STRUCT(_machdep, CPU_BOOTINFO, bootinfo,
1378 CTLFLAG_RD, &bootinfo, bootinfo, "");
1381 SYSCTL_INT(_machdep, CPU_WALLCLOCK, wall_cmos_clock,
1382 CTLFLAG_RW, &wall_cmos_clock, 0, "");
1384 extern u_long bootdev; /* not a cdev_t - encoding is different */
1385 SYSCTL_ULONG(_machdep, OID_AUTO, guessed_bootdev,
1386 CTLFLAG_RD, &bootdev, 0, "Boot device (not in cdev_t format)");
1389 * Initialize 386 and configure to run kernel
1393 * Initialize segments & interrupt table
1397 struct user_segment_descriptor gdt[NGDT * MAXCPU]; /* global descriptor table */
1398 struct gate_descriptor idt_arr[MAXCPU][NIDT];
1400 union descriptor ldt[NLDT]; /* local descriptor table */
1403 /* table descriptors - used to load tables by cpu */
1404 struct region_descriptor r_gdt;
1405 struct region_descriptor r_idt_arr[MAXCPU];
1407 /* JG proc0paddr is a virtual address */
1410 char proc0paddr_buff[LWKT_THREAD_STACK];
1413 /* software prototypes -- in more palatable form */
1414 struct soft_segment_descriptor gdt_segs[] = {
1415 /* GNULL_SEL 0 Null Descriptor */
1416 { 0x0, /* segment base address */
1418 0, /* segment type */
1419 0, /* segment descriptor priority level */
1420 0, /* segment descriptor present */
1422 0, /* default 32 vs 16 bit size */
1423 0 /* limit granularity (byte/page units)*/ },
1424 /* GCODE_SEL 1 Code Descriptor for kernel */
1425 { 0x0, /* segment base address */
1426 0xfffff, /* length - all address space */
1427 SDT_MEMERA, /* segment type */
1428 SEL_KPL, /* segment descriptor priority level */
1429 1, /* segment descriptor present */
1431 0, /* default 32 vs 16 bit size */
1432 1 /* limit granularity (byte/page units)*/ },
1433 /* GDATA_SEL 2 Data Descriptor for kernel */
1434 { 0x0, /* segment base address */
1435 0xfffff, /* length - all address space */
1436 SDT_MEMRWA, /* segment type */
1437 SEL_KPL, /* segment descriptor priority level */
1438 1, /* segment descriptor present */
1440 0, /* default 32 vs 16 bit size */
1441 1 /* limit granularity (byte/page units)*/ },
1442 /* GUCODE32_SEL 3 32 bit Code Descriptor for user */
1443 { 0x0, /* segment base address */
1444 0xfffff, /* length - all address space */
1445 SDT_MEMERA, /* segment type */
1446 SEL_UPL, /* segment descriptor priority level */
1447 1, /* segment descriptor present */
1449 1, /* default 32 vs 16 bit size */
1450 1 /* limit granularity (byte/page units)*/ },
1451 /* GUDATA_SEL 4 32/64 bit Data Descriptor for user */
1452 { 0x0, /* segment base address */
1453 0xfffff, /* length - all address space */
1454 SDT_MEMRWA, /* segment type */
1455 SEL_UPL, /* segment descriptor priority level */
1456 1, /* segment descriptor present */
1458 1, /* default 32 vs 16 bit size */
1459 1 /* limit granularity (byte/page units)*/ },
1460 /* GUCODE_SEL 5 64 bit Code Descriptor for user */
1461 { 0x0, /* segment base address */
1462 0xfffff, /* length - all address space */
1463 SDT_MEMERA, /* segment type */
1464 SEL_UPL, /* segment descriptor priority level */
1465 1, /* segment descriptor present */
1467 0, /* default 32 vs 16 bit size */
1468 1 /* limit granularity (byte/page units)*/ },
1469 /* GPROC0_SEL 6 Proc 0 Tss Descriptor */
1471 0x0, /* segment base address */
1472 sizeof(struct x86_64tss)-1,/* length - all address space */
1473 SDT_SYSTSS, /* segment type */
1474 SEL_KPL, /* segment descriptor priority level */
1475 1, /* segment descriptor present */
1477 0, /* unused - default 32 vs 16 bit size */
1478 0 /* limit granularity (byte/page units)*/ },
1479 /* Actually, the TSS is a system descriptor which is double size */
1480 { 0x0, /* segment base address */
1482 0, /* segment type */
1483 0, /* segment descriptor priority level */
1484 0, /* segment descriptor present */
1486 0, /* default 32 vs 16 bit size */
1487 0 /* limit granularity (byte/page units)*/ },
1488 /* GUGS32_SEL 8 32 bit GS Descriptor for user */
1489 { 0x0, /* segment base address */
1490 0xfffff, /* length - all address space */
1491 SDT_MEMRWA, /* segment type */
1492 SEL_UPL, /* segment descriptor priority level */
1493 1, /* segment descriptor present */
1495 1, /* default 32 vs 16 bit size */
1496 1 /* limit granularity (byte/page units)*/ },
1500 setidt_global(int idx, inthand_t *func, int typ, int dpl, int ist)
1504 for (cpu = 0; cpu < MAXCPU; ++cpu) {
1505 struct gate_descriptor *ip = &idt_arr[cpu][idx];
1507 ip->gd_looffset = (uintptr_t)func;
1508 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL);
1514 ip->gd_hioffset = ((uintptr_t)func)>>16 ;
1519 setidt(int idx, inthand_t *func, int typ, int dpl, int ist, int cpu)
1521 struct gate_descriptor *ip;
1523 KASSERT(cpu >= 0 && cpu < ncpus, ("invalid cpu %d", cpu));
1525 ip = &idt_arr[cpu][idx];
1526 ip->gd_looffset = (uintptr_t)func;
1527 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL);
1533 ip->gd_hioffset = ((uintptr_t)func)>>16 ;
1536 #define IDTVEC(name) __CONCAT(X,name)
1539 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl),
1540 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm),
1541 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot),
1542 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align),
1543 IDTVEC(xmm), IDTVEC(dblfault),
1544 IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
1547 sdtossd(struct user_segment_descriptor *sd, struct soft_segment_descriptor *ssd)
1549 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase;
1550 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit;
1551 ssd->ssd_type = sd->sd_type;
1552 ssd->ssd_dpl = sd->sd_dpl;
1553 ssd->ssd_p = sd->sd_p;
1554 ssd->ssd_def32 = sd->sd_def32;
1555 ssd->ssd_gran = sd->sd_gran;
1559 ssdtosd(struct soft_segment_descriptor *ssd, struct user_segment_descriptor *sd)
1562 sd->sd_lobase = (ssd->ssd_base) & 0xffffff;
1563 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff;
1564 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff;
1565 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf;
1566 sd->sd_type = ssd->ssd_type;
1567 sd->sd_dpl = ssd->ssd_dpl;
1568 sd->sd_p = ssd->ssd_p;
1569 sd->sd_long = ssd->ssd_long;
1570 sd->sd_def32 = ssd->ssd_def32;
1571 sd->sd_gran = ssd->ssd_gran;
1575 ssdtosyssd(struct soft_segment_descriptor *ssd,
1576 struct system_segment_descriptor *sd)
1579 sd->sd_lobase = (ssd->ssd_base) & 0xffffff;
1580 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful;
1581 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff;
1582 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf;
1583 sd->sd_type = ssd->ssd_type;
1584 sd->sd_dpl = ssd->ssd_dpl;
1585 sd->sd_p = ssd->ssd_p;
1586 sd->sd_gran = ssd->ssd_gran;
1590 * Populate the (physmap) array with base/bound pairs describing the
1591 * available physical memory in the system, then test this memory and
1592 * build the phys_avail array describing the actually-available memory.
1594 * If we cannot accurately determine the physical memory map, then use
1595 * value from the 0xE801 call, and failing that, the RTC.
1597 * Total memory size may be set by the kernel environment variable
1598 * hw.physmem or the compile-time define MAXMEM.
1600 * Memory is aligned to PHYSMAP_ALIGN which must be a multiple
1601 * of PAGE_SIZE. This also greatly reduces the memory test time
1602 * which would otherwise be excessive on machines with > 8G of ram.
1604 * XXX first should be vm_paddr_t.
1607 #define PHYSMAP_ALIGN (vm_paddr_t)(128 * 1024)
1608 #define PHYSMAP_ALIGN_MASK (vm_paddr_t)(PHYSMAP_ALIGN - 1)
1609 vm_paddr_t physmap[PHYSMAP_SIZE];
1610 struct bios_smap *smapbase, *smap, *smapend;
1611 struct efi_map_header *efihdrbase;
1615 add_smap_entries(int *physmap_idx)
1619 smapsize = *((u_int32_t *)smapbase - 1);
1620 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize);
1622 for (smap = smapbase; smap < smapend; smap++) {
1623 if (boothowto & RB_VERBOSE)
1624 kprintf("SMAP type=%02x base=%016lx len=%016lx\n",
1625 smap->type, smap->base, smap->length);
1627 if (smap->type != SMAP_TYPE_MEMORY)
1630 if (smap->length == 0)
1633 for (i = 0; i <= *physmap_idx; i += 2) {
1634 if (smap->base < physmap[i + 1]) {
1635 if (boothowto & RB_VERBOSE) {
1636 kprintf("Overlapping or non-monotonic "
1637 "memory region, ignoring "
1643 if (i <= *physmap_idx)
1646 Realmem += smap->length;
1648 if (smap->base == physmap[*physmap_idx + 1]) {
1649 physmap[*physmap_idx + 1] += smap->length;
1654 if (*physmap_idx == PHYSMAP_SIZE) {
1655 kprintf("Too many segments in the physical "
1656 "address map, giving up\n");
1659 physmap[*physmap_idx] = smap->base;
1660 physmap[*physmap_idx + 1] = smap->base + smap->length;
1664 #define efi_next_descriptor(ptr, size) \
1665 ((struct efi_md *)(((uint8_t *) ptr) + size))
1668 add_efi_map_entries(int *physmap_idx)
1670 struct efi_md *map, *p;
1675 static const char *types[] = {
1681 "RuntimeServicesCode",
1682 "RuntimeServicesData",
1683 "ConventionalMemory",
1685 "ACPIReclaimMemory",
1688 "MemoryMappedIOPortSpace",
1693 * Memory map data provided by UEFI via the GetMemoryMap
1694 * Boot Services API.
1696 efisz = (sizeof(struct efi_map_header) + 0xf) & ~0xf;
1697 map = (struct efi_md *)((uint8_t *)efihdrbase + efisz);
1699 if (efihdrbase->descriptor_size == 0)
1701 ndesc = efihdrbase->memory_size / efihdrbase->descriptor_size;
1703 if (boothowto & RB_VERBOSE)
1704 kprintf("%23s %12s %12s %8s %4s\n",
1705 "Type", "Physical", "Virtual", "#Pages", "Attr");
1707 for (i = 0, p = map; i < ndesc; i++,
1708 p = efi_next_descriptor(p, efihdrbase->descriptor_size)) {
1709 if (boothowto & RB_VERBOSE) {
1710 if (p->md_type <= EFI_MD_TYPE_PALCODE)
1711 type = types[p->md_type];
1714 kprintf("%23s %012lx %12p %08lx ", type, p->md_phys,
1715 p->md_virt, p->md_pages);
1716 if (p->md_attr & EFI_MD_ATTR_UC)
1718 if (p->md_attr & EFI_MD_ATTR_WC)
1720 if (p->md_attr & EFI_MD_ATTR_WT)
1722 if (p->md_attr & EFI_MD_ATTR_WB)
1724 if (p->md_attr & EFI_MD_ATTR_UCE)
1726 if (p->md_attr & EFI_MD_ATTR_WP)
1728 if (p->md_attr & EFI_MD_ATTR_RP)
1730 if (p->md_attr & EFI_MD_ATTR_XP)
1732 if (p->md_attr & EFI_MD_ATTR_RT)
1737 switch (p->md_type) {
1738 case EFI_MD_TYPE_CODE:
1739 case EFI_MD_TYPE_DATA:
1740 case EFI_MD_TYPE_BS_CODE:
1741 case EFI_MD_TYPE_BS_DATA:
1742 case EFI_MD_TYPE_FREE:
1744 * We're allowed to use any entry with these types.
1751 Realmem += p->md_pages * PAGE_SIZE;
1753 if (p->md_phys == physmap[*physmap_idx + 1]) {
1754 physmap[*physmap_idx + 1] += p->md_pages * PAGE_SIZE;
1759 if (*physmap_idx == PHYSMAP_SIZE) {
1760 kprintf("Too many segments in the physical "
1761 "address map, giving up\n");
1764 physmap[*physmap_idx] = p->md_phys;
1765 physmap[*physmap_idx + 1] = p->md_phys + p->md_pages * PAGE_SIZE;
1769 struct fb_info efi_fb_info;
1770 static int have_efi_framebuffer = 0;
1773 efi_fb_init_vaddr(int direct_map)
1776 vm_offset_t addr, v;
1778 v = efi_fb_info.vaddr;
1779 sz = efi_fb_info.stride * efi_fb_info.height;
1782 addr = PHYS_TO_DMAP(efi_fb_info.paddr);
1783 if (addr >= DMAP_MIN_ADDRESS && addr + sz < DMAP_MAX_ADDRESS)
1784 efi_fb_info.vaddr = addr;
1786 efi_fb_info.vaddr = (vm_offset_t)pmap_mapdev_attr(
1787 efi_fb_info.paddr, sz, PAT_WRITE_COMBINING);
1790 if (v == 0 && efi_fb_info.vaddr != 0)
1791 memset((void *)efi_fb_info.vaddr, 0x77, sz);
1795 probe_efi_fb(int early)
1797 struct efi_fb *efifb;
1800 if (have_efi_framebuffer) {
1802 (efi_fb_info.vaddr == 0 ||
1803 efi_fb_info.vaddr == PHYS_TO_DMAP(efi_fb_info.paddr)))
1804 efi_fb_init_vaddr(0);
1808 kmdp = preload_search_by_type("elf kernel");
1810 kmdp = preload_search_by_type("elf64 kernel");
1811 efifb = (struct efi_fb *)preload_search_info(kmdp,
1812 MODINFO_METADATA | MODINFOMD_EFI_FB);
1816 have_efi_framebuffer = 1;
1818 efi_fb_info.is_vga_boot_display = 1;
1819 efi_fb_info.width = efifb->fb_width;
1820 efi_fb_info.height = efifb->fb_height;
1821 efi_fb_info.stride = efifb->fb_stride * 4;
1822 efi_fb_info.depth = 32;
1823 efi_fb_info.paddr = efifb->fb_addr;
1825 efi_fb_info.vaddr = 0;
1827 efi_fb_init_vaddr(0);
1829 efi_fb_info.restore = NULL;
1830 efi_fb_info.device = NULL;
1836 efifb_startup(void *arg)
1841 SYSINIT(efi_fb_info, SI_BOOT1_POST, SI_ORDER_FIRST, efifb_startup, NULL);
1844 getmemsize(caddr_t kmdp, u_int64_t first)
1846 int off, physmap_idx, pa_indx, da_indx;
1849 vm_paddr_t msgbuf_size;
1850 u_long physmem_tunable;
1852 quad_t dcons_addr, dcons_size;
1854 bzero(physmap, sizeof(physmap));
1858 * get memory map from INT 15:E820, kindly supplied by the loader.
1860 * subr_module.c says:
1861 * "Consumer may safely assume that size value precedes data."
1862 * ie: an int32_t immediately precedes smap.
1864 efihdrbase = (struct efi_map_header *)preload_search_info(kmdp,
1865 MODINFO_METADATA | MODINFOMD_EFI_MAP);
1866 smapbase = (struct bios_smap *)preload_search_info(kmdp,
1867 MODINFO_METADATA | MODINFOMD_SMAP);
1868 if (smapbase == NULL && efihdrbase == NULL)
1869 panic("No BIOS smap or EFI map info from loader!");
1871 if (efihdrbase == NULL)
1872 add_smap_entries(&physmap_idx);
1874 add_efi_map_entries(&physmap_idx);
1876 base_memory = physmap[1] / 1024;
1877 /* make hole for AP bootstrap code */
1878 physmap[1] = mp_bootaddress(base_memory);
1880 /* Save EBDA address, if any */
1881 ebda_addr = (u_long)(*(u_short *)(KERNBASE + 0x40e));
1885 * Maxmem isn't the "maximum memory", it's one larger than the
1886 * highest page of the physical address space. It should be
1887 * called something like "Maxphyspage". We may adjust this
1888 * based on ``hw.physmem'' and the results of the memory test.
1890 Maxmem = atop(physmap[physmap_idx + 1]);
1893 Maxmem = MAXMEM / 4;
1896 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable))
1897 Maxmem = atop(physmem_tunable);
1900 * Don't allow MAXMEM or hw.physmem to extend the amount of memory
1903 if (Maxmem > atop(physmap[physmap_idx + 1]))
1904 Maxmem = atop(physmap[physmap_idx + 1]);
1907 * Blowing out the DMAP will blow up the system.
1909 if (Maxmem > atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS)) {
1910 kprintf("Limiting Maxmem due to DMAP size\n");
1911 Maxmem = atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS);
1914 if (atop(physmap[physmap_idx + 1]) != Maxmem &&
1915 (boothowto & RB_VERBOSE)) {
1916 kprintf("Physical memory use set to %ldK\n", Maxmem * 4);
1920 * Call pmap initialization to make new kernel address space
1924 pmap_bootstrap(&first);
1925 physmap[0] = PAGE_SIZE;
1928 * Align the physmap to PHYSMAP_ALIGN and cut out anything
1931 for (i = j = 0; i <= physmap_idx; i += 2) {
1932 if (physmap[i+1] > ptoa(Maxmem))
1933 physmap[i+1] = ptoa(Maxmem);
1934 physmap[i] = (physmap[i] + PHYSMAP_ALIGN_MASK) &
1935 ~PHYSMAP_ALIGN_MASK;
1936 physmap[i+1] = physmap[i+1] & ~PHYSMAP_ALIGN_MASK;
1938 physmap[j] = physmap[i];
1939 physmap[j+1] = physmap[i+1];
1941 if (physmap[i] < physmap[i+1])
1944 physmap_idx = j - 2;
1947 * Align anything else used in the validation loop.
1949 first = (first + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK;
1952 * Size up each available chunk of physical memory.
1956 phys_avail[pa_indx++] = physmap[0];
1957 phys_avail[pa_indx] = physmap[0];
1958 dump_avail[da_indx] = physmap[0];
1962 * Get dcons buffer address
1964 if (kgetenv_quad("dcons.addr", &dcons_addr) == 0 ||
1965 kgetenv_quad("dcons.size", &dcons_size) == 0)
1969 * Validate the physical memory. The physical memory segments
1970 * have already been aligned to PHYSMAP_ALIGN which is a multiple
1973 for (i = 0; i <= physmap_idx; i += 2) {
1976 end = physmap[i + 1];
1978 for (pa = physmap[i]; pa < end; pa += PHYSMAP_ALIGN) {
1979 int tmp, page_bad, full;
1980 int *ptr = (int *)CADDR1;
1984 * block out kernel memory as not available.
1986 if (pa >= 0x200000 && pa < first)
1990 * block out dcons buffer
1993 && pa >= trunc_page(dcons_addr)
1994 && pa < dcons_addr + dcons_size) {
2001 * map page into kernel: valid, read/write,non-cacheable
2004 kernel_pmap.pmap_bits[PG_V_IDX] |
2005 kernel_pmap.pmap_bits[PG_RW_IDX] |
2006 kernel_pmap.pmap_bits[PG_N_IDX];
2011 * Test for alternating 1's and 0's
2013 *(volatile int *)ptr = 0xaaaaaaaa;
2015 if (*(volatile int *)ptr != 0xaaaaaaaa)
2018 * Test for alternating 0's and 1's
2020 *(volatile int *)ptr = 0x55555555;
2022 if (*(volatile int *)ptr != 0x55555555)
2027 *(volatile int *)ptr = 0xffffffff;
2029 if (*(volatile int *)ptr != 0xffffffff)
2034 *(volatile int *)ptr = 0x0;
2036 if (*(volatile int *)ptr != 0x0)
2039 * Restore original value.
2044 * Adjust array of valid/good pages.
2046 if (page_bad == TRUE)
2049 * If this good page is a continuation of the
2050 * previous set of good pages, then just increase
2051 * the end pointer. Otherwise start a new chunk.
2052 * Note that "end" points one higher than end,
2053 * making the range >= start and < end.
2054 * If we're also doing a speculative memory
2055 * test and we at or past the end, bump up Maxmem
2056 * so that we keep going. The first bad page
2057 * will terminate the loop.
2059 if (phys_avail[pa_indx] == pa) {
2060 phys_avail[pa_indx] += PHYSMAP_ALIGN;
2063 if (pa_indx == PHYS_AVAIL_ARRAY_END) {
2065 "Too many holes in the physical address space, giving up\n");
2070 phys_avail[pa_indx++] = pa;
2071 phys_avail[pa_indx] = pa + PHYSMAP_ALIGN;
2073 physmem += PHYSMAP_ALIGN / PAGE_SIZE;
2075 if (dump_avail[da_indx] == pa) {
2076 dump_avail[da_indx] += PHYSMAP_ALIGN;
2079 if (da_indx == DUMP_AVAIL_ARRAY_END) {
2083 dump_avail[da_indx++] = pa;
2084 dump_avail[da_indx] = pa + PHYSMAP_ALIGN;
2095 * The last chunk must contain at least one page plus the message
2096 * buffer to avoid complicating other code (message buffer address
2097 * calculation, etc.).
2099 msgbuf_size = (MSGBUF_SIZE + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK;
2101 while (phys_avail[pa_indx - 1] + PHYSMAP_ALIGN +
2102 msgbuf_size >= phys_avail[pa_indx]) {
2103 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]);
2104 phys_avail[pa_indx--] = 0;
2105 phys_avail[pa_indx--] = 0;
2108 Maxmem = atop(phys_avail[pa_indx]);
2110 /* Trim off space for the message buffer. */
2111 phys_avail[pa_indx] -= msgbuf_size;
2113 avail_end = phys_avail[pa_indx];
2115 /* Map the message buffer. */
2116 for (off = 0; off < msgbuf_size; off += PAGE_SIZE) {
2117 pmap_kenter((vm_offset_t)msgbufp + off,
2118 phys_avail[pa_indx] + off);
2120 /* Try to get EFI framebuffer working as early as possible */
2121 if (have_efi_framebuffer)
2122 efi_fb_init_vaddr(1);
2125 struct machintr_abi MachIntrABI;
2136 * 7 Device Not Available (x87)
2138 * 9 Coprocessor Segment overrun (unsupported, reserved)
2140 * 11 Segment not present
2142 * 13 General Protection
2145 * 16 x87 FP Exception pending
2146 * 17 Alignment Check
2148 * 19 SIMD floating point
2150 * 32-255 INTn/external sources
2153 hammer_time(u_int64_t modulep, u_int64_t physfree)
2156 int gsel_tss, x, cpu;
2158 int metadata_missing, off;
2160 struct mdglobaldata *gd;
2164 * Prevent lowering of the ipl if we call tsleep() early.
2166 gd = &CPU_prvspace[0]->mdglobaldata;
2167 bzero(gd, sizeof(*gd));
2170 * Note: on both UP and SMP curthread must be set non-NULL
2171 * early in the boot sequence because the system assumes
2172 * that 'curthread' is never NULL.
2175 gd->mi.gd_curthread = &thread0;
2176 thread0.td_gd = &gd->mi;
2178 atdevbase = ISA_HOLE_START + PTOV_OFFSET;
2181 metadata_missing = 0;
2182 if (bootinfo.bi_modulep) {
2183 preload_metadata = (caddr_t)bootinfo.bi_modulep + KERNBASE;
2184 preload_bootstrap_relocate(KERNBASE);
2186 metadata_missing = 1;
2188 if (bootinfo.bi_envp)
2189 kern_envp = (caddr_t)bootinfo.bi_envp + KERNBASE;
2192 preload_metadata = (caddr_t)(uintptr_t)(modulep + PTOV_OFFSET);
2193 preload_bootstrap_relocate(PTOV_OFFSET);
2194 kmdp = preload_search_by_type("elf kernel");
2196 kmdp = preload_search_by_type("elf64 kernel");
2197 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int);
2198 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + PTOV_OFFSET;
2200 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t);
2201 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t);
2204 if (boothowto & RB_VERBOSE)
2208 * Default MachIntrABI to ICU
2210 MachIntrABI = MachIntrABI_ICU;
2213 * start with one cpu. Note: with one cpu, ncpus2_shift, ncpus2_mask,
2214 * and ncpus_fit_mask remain 0.
2219 /* Init basic tunables, hz etc */
2223 * make gdt memory segments
2225 gdt_segs[GPROC0_SEL].ssd_base =
2226 (uintptr_t) &CPU_prvspace[0]->mdglobaldata.gd_common_tss;
2228 gd->mi.gd_prvspace = CPU_prvspace[0];
2230 for (x = 0; x < NGDT; x++) {
2231 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
2232 ssdtosd(&gdt_segs[x], &gdt[x]);
2234 ssdtosyssd(&gdt_segs[GPROC0_SEL],
2235 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]);
2237 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
2238 r_gdt.rd_base = (long) gdt;
2241 wrmsr(MSR_FSBASE, 0); /* User value */
2242 wrmsr(MSR_GSBASE, (u_int64_t)&gd->mi);
2243 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */
2245 mi_gdinit(&gd->mi, 0);
2247 proc0paddr = proc0paddr_buff;
2248 mi_proc0init(&gd->mi, proc0paddr);
2249 safepri = TDPRI_MAX;
2251 /* spinlocks and the BGL */
2255 for (x = 0; x < NIDT; x++)
2256 setidt_global(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0);
2257 setidt_global(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0);
2258 setidt_global(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 0);
2259 setidt_global(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 1);
2260 setidt_global(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0);
2261 setidt_global(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0);
2262 setidt_global(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0);
2263 setidt_global(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0);
2264 setidt_global(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0);
2265 setidt_global(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1);
2266 setidt_global(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0);
2267 setidt_global(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0);
2268 setidt_global(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0);
2269 setidt_global(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0);
2270 setidt_global(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0);
2271 setidt_global(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0);
2272 setidt_global(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0);
2273 setidt_global(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0);
2274 setidt_global(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0);
2275 setidt_global(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0);
2277 for (cpu = 0; cpu < MAXCPU; ++cpu) {
2278 r_idt_arr[cpu].rd_limit = sizeof(idt_arr[cpu]) - 1;
2279 r_idt_arr[cpu].rd_base = (long) &idt_arr[cpu][0];
2282 lidt(&r_idt_arr[0]);
2285 * Initialize the console before we print anything out.
2290 if (metadata_missing)
2291 kprintf("WARNING: loader(8) metadata is missing!\n");
2301 * Initialize IRQ mapping
2304 * SHOULD be after elcr_probe()
2306 MachIntrABI_ICU.initmap();
2307 MachIntrABI_IOAPIC.initmap();
2311 if (boothowto & RB_KDB)
2312 Debugger("Boot flags requested debugger");
2316 finishidentcpu(); /* Final stage of CPU initialization */
2317 setidt(6, &IDTVEC(ill), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2318 setidt(13, &IDTVEC(prot), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2320 identify_cpu(); /* Final stage of CPU initialization */
2321 initializecpu(0); /* Initialize CPU registers */
2324 * On modern intel cpus, haswell or later, cpu_idle_hlt=1 is better
2325 * because the cpu does significant power management in MWAIT
2326 * (also suggested is to set sysctl machdep.mwait.CX.idle=AUTODEEP).
2328 * On modern amd cpus cpu_idle_hlt=3 is better, because the cpu does
2329 * significant power management in HLT or ACPI (but cpu_idle_hlt=1
2330 * would try to use MWAIT).
2332 * On older amd or intel cpus, cpu_idle_hlt=2 is better because ACPI
2333 * is needed to reduce power consumption, but wakeup times are often
2336 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
2337 CPUID_TO_MODEL(cpu_id) >= 0x3C) { /* Haswell or later */
2340 if (cpu_vendor_id == CPU_VENDOR_AMD &&
2341 CPUID_TO_FAMILY(cpu_id) >= 0x14) { /* Bobcat or later */
2345 TUNABLE_INT_FETCH("hw.apic_io_enable", &ioapic_enable); /* for compat */
2346 TUNABLE_INT_FETCH("hw.ioapic_enable", &ioapic_enable);
2347 TUNABLE_INT_FETCH("hw.lapic_enable", &lapic_enable);
2348 TUNABLE_INT_FETCH("machdep.cpu_idle_hlt", &cpu_idle_hlt);
2351 * Some of the virtual machines do not work w/ I/O APIC
2352 * enabled. If the user does not explicitly enable or
2353 * disable the I/O APIC (ioapic_enable < 0), then we
2354 * disable I/O APIC on all virtual machines.
2357 * This must be done after identify_cpu(), which sets
2360 if (ioapic_enable < 0) {
2361 if (cpu_feature2 & CPUID2_VMM)
2367 /* make an initial tss so cpu can get interrupt stack on syscall! */
2368 gd->gd_common_tss.tss_rsp0 =
2369 (register_t)(thread0.td_kstack +
2370 KSTACK_PAGES * PAGE_SIZE - sizeof(struct pcb));
2371 /* Ensure the stack is aligned to 16 bytes */
2372 gd->gd_common_tss.tss_rsp0 &= ~(register_t)0xF;
2374 /* double fault stack */
2375 gd->gd_common_tss.tss_ist1 =
2376 (long)&gd->mi.gd_prvspace->idlestack[
2377 sizeof(gd->mi.gd_prvspace->idlestack)];
2379 /* Set the IO permission bitmap (empty due to tss seg limit) */
2380 gd->gd_common_tss.tss_iobase = sizeof(struct x86_64tss);
2382 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
2383 gd->gd_tss_gdt = &gdt[GPROC0_SEL];
2384 gd->gd_common_tssd = *gd->gd_tss_gdt;
2387 /* Set up the fast syscall stuff */
2388 msr = rdmsr(MSR_EFER) | EFER_SCE;
2389 wrmsr(MSR_EFER, msr);
2390 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
2391 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
2392 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
2393 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
2394 wrmsr(MSR_STAR, msr);
2395 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D|PSL_IOPL);
2397 getmemsize(kmdp, physfree);
2398 init_param2(physmem);
2400 /* now running on new page tables, configured,and u/iom is accessible */
2402 /* Map the message buffer. */
2404 for (off = 0; off < round_page(MSGBUF_SIZE); off += PAGE_SIZE)
2405 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off);
2408 msgbufinit(msgbufp, MSGBUF_SIZE);
2411 /* transfer to user mode */
2413 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL);
2414 _udatasel = GSEL(GUDATA_SEL, SEL_UPL);
2415 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL);
2421 /* setup proc 0's pcb */
2422 thread0.td_pcb->pcb_flags = 0;
2423 thread0.td_pcb->pcb_cr3 = KPML4phys;
2424 thread0.td_pcb->pcb_ext = NULL;
2425 lwp0.lwp_md.md_regs = &proc0_tf; /* XXX needed? */
2427 /* Location of kernel stack for locore */
2428 return ((u_int64_t)thread0.td_pcb);
2432 * Initialize machine-dependant portions of the global data structure.
2433 * Note that the global data area and cpu0's idlestack in the private
2434 * data space were allocated in locore.
2436 * Note: the idlethread's cpl is 0
2438 * WARNING! Called from early boot, 'mycpu' may not work yet.
2441 cpu_gdinit(struct mdglobaldata *gd, int cpu)
2444 gd->mi.gd_curthread = &gd->mi.gd_idlethread;
2446 lwkt_init_thread(&gd->mi.gd_idlethread,
2447 gd->mi.gd_prvspace->idlestack,
2448 sizeof(gd->mi.gd_prvspace->idlestack),
2450 lwkt_set_comm(&gd->mi.gd_idlethread, "idle_%d", cpu);
2451 gd->mi.gd_idlethread.td_switch = cpu_lwkt_switch;
2452 gd->mi.gd_idlethread.td_sp -= sizeof(void *);
2453 *(void **)gd->mi.gd_idlethread.td_sp = cpu_idle_restore;
2457 * We only have to check for DMAP bounds, the globaldata space is
2458 * actually part of the kernel_map so we don't have to waste time
2459 * checking CPU_prvspace[*].
2462 is_globaldata_space(vm_offset_t saddr, vm_offset_t eaddr)
2465 if (saddr >= (vm_offset_t)&CPU_prvspace[0] &&
2466 eaddr <= (vm_offset_t)&CPU_prvspace[MAXCPU]) {
2470 if (saddr >= DMAP_MIN_ADDRESS && eaddr <= DMAP_MAX_ADDRESS)
2476 globaldata_find(int cpu)
2478 KKASSERT(cpu >= 0 && cpu < ncpus);
2479 return(&CPU_prvspace[cpu]->mdglobaldata.mi);
2483 * This path should be safe from the SYSRET issue because only stopped threads
2484 * can have their %rip adjusted this way (and all heavy weight thread switches
2485 * clear QUICKREF and thus do not use SYSRET). However, the code path is
2486 * convoluted so add a safety by forcing %rip to be cannonical.
2489 ptrace_set_pc(struct lwp *lp, unsigned long addr)
2491 if (addr & 0x0000800000000000LLU)
2492 lp->lwp_md.md_regs->tf_rip = addr | 0xFFFF000000000000LLU;
2494 lp->lwp_md.md_regs->tf_rip = addr & 0x0000FFFFFFFFFFFFLLU;
2499 ptrace_single_step(struct lwp *lp)
2501 lp->lwp_md.md_regs->tf_rflags |= PSL_T;
2506 fill_regs(struct lwp *lp, struct reg *regs)
2508 struct trapframe *tp;
2510 if ((tp = lp->lwp_md.md_regs) == NULL)
2512 bcopy(&tp->tf_rdi, ®s->r_rdi, sizeof(*regs));
2517 set_regs(struct lwp *lp, struct reg *regs)
2519 struct trapframe *tp;
2521 tp = lp->lwp_md.md_regs;
2522 if (!EFL_SECURE(regs->r_rflags, tp->tf_rflags) ||
2523 !CS_SECURE(regs->r_cs))
2525 bcopy(®s->r_rdi, &tp->tf_rdi, sizeof(*regs));
2531 fill_fpregs_xmm(struct savexmm *sv_xmm, struct save87 *sv_87)
2533 struct env87 *penv_87 = &sv_87->sv_env;
2534 struct envxmm *penv_xmm = &sv_xmm->sv_env;
2537 /* FPU control/status */
2538 penv_87->en_cw = penv_xmm->en_cw;
2539 penv_87->en_sw = penv_xmm->en_sw;
2540 penv_87->en_tw = penv_xmm->en_tw;
2541 penv_87->en_fip = penv_xmm->en_fip;
2542 penv_87->en_fcs = penv_xmm->en_fcs;
2543 penv_87->en_opcode = penv_xmm->en_opcode;
2544 penv_87->en_foo = penv_xmm->en_foo;
2545 penv_87->en_fos = penv_xmm->en_fos;
2548 for (i = 0; i < 8; ++i)
2549 sv_87->sv_ac[i] = sv_xmm->sv_fp[i].fp_acc;
2553 set_fpregs_xmm(struct save87 *sv_87, struct savexmm *sv_xmm)
2555 struct env87 *penv_87 = &sv_87->sv_env;
2556 struct envxmm *penv_xmm = &sv_xmm->sv_env;
2559 /* FPU control/status */
2560 penv_xmm->en_cw = penv_87->en_cw;
2561 penv_xmm->en_sw = penv_87->en_sw;
2562 penv_xmm->en_tw = penv_87->en_tw;
2563 penv_xmm->en_fip = penv_87->en_fip;
2564 penv_xmm->en_fcs = penv_87->en_fcs;
2565 penv_xmm->en_opcode = penv_87->en_opcode;
2566 penv_xmm->en_foo = penv_87->en_foo;
2567 penv_xmm->en_fos = penv_87->en_fos;
2570 for (i = 0; i < 8; ++i)
2571 sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i];
2575 fill_fpregs(struct lwp *lp, struct fpreg *fpregs)
2577 if (lp->lwp_thread == NULL || lp->lwp_thread->td_pcb == NULL)
2580 fill_fpregs_xmm(&lp->lwp_thread->td_pcb->pcb_save.sv_xmm,
2581 (struct save87 *)fpregs);
2584 bcopy(&lp->lwp_thread->td_pcb->pcb_save.sv_87, fpregs, sizeof *fpregs);
2589 set_fpregs(struct lwp *lp, struct fpreg *fpregs)
2592 set_fpregs_xmm((struct save87 *)fpregs,
2593 &lp->lwp_thread->td_pcb->pcb_save.sv_xmm);
2596 bcopy(fpregs, &lp->lwp_thread->td_pcb->pcb_save.sv_87, sizeof *fpregs);
2601 fill_dbregs(struct lwp *lp, struct dbreg *dbregs)
2606 dbregs->dr[0] = rdr0();
2607 dbregs->dr[1] = rdr1();
2608 dbregs->dr[2] = rdr2();
2609 dbregs->dr[3] = rdr3();
2610 dbregs->dr[4] = rdr4();
2611 dbregs->dr[5] = rdr5();
2612 dbregs->dr[6] = rdr6();
2613 dbregs->dr[7] = rdr7();
2616 if (lp->lwp_thread == NULL || (pcb = lp->lwp_thread->td_pcb) == NULL)
2618 dbregs->dr[0] = pcb->pcb_dr0;
2619 dbregs->dr[1] = pcb->pcb_dr1;
2620 dbregs->dr[2] = pcb->pcb_dr2;
2621 dbregs->dr[3] = pcb->pcb_dr3;
2624 dbregs->dr[6] = pcb->pcb_dr6;
2625 dbregs->dr[7] = pcb->pcb_dr7;
2630 set_dbregs(struct lwp *lp, struct dbreg *dbregs)
2633 load_dr0(dbregs->dr[0]);
2634 load_dr1(dbregs->dr[1]);
2635 load_dr2(dbregs->dr[2]);
2636 load_dr3(dbregs->dr[3]);
2637 load_dr4(dbregs->dr[4]);
2638 load_dr5(dbregs->dr[5]);
2639 load_dr6(dbregs->dr[6]);
2640 load_dr7(dbregs->dr[7]);
2643 struct ucred *ucred;
2645 uint64_t mask1, mask2;
2648 * Don't let an illegal value for dr7 get set. Specifically,
2649 * check for undefined settings. Setting these bit patterns
2650 * result in undefined behaviour and can lead to an unexpected
2653 /* JG this loop looks unreadable */
2654 /* Check 4 2-bit fields for invalid patterns.
2655 * These fields are R/Wi, for i = 0..3
2657 /* Is 10 in LENi allowed when running in compatibility mode? */
2658 /* Pattern 10 in R/Wi might be used to indicate
2659 * breakpoint on I/O. Further analysis should be
2660 * carried to decide if it is safe and useful to
2661 * provide access to that capability
2663 for (i = 0, mask1 = 0x3<<16, mask2 = 0x2<<16; i < 4;
2664 i++, mask1 <<= 4, mask2 <<= 4)
2665 if ((dbregs->dr[7] & mask1) == mask2)
2668 pcb = lp->lwp_thread->td_pcb;
2669 ucred = lp->lwp_proc->p_ucred;
2672 * Don't let a process set a breakpoint that is not within the
2673 * process's address space. If a process could do this, it
2674 * could halt the system by setting a breakpoint in the kernel
2675 * (if ddb was enabled). Thus, we need to check to make sure
2676 * that no breakpoints are being enabled for addresses outside
2677 * process's address space, unless, perhaps, we were called by
2680 * XXX - what about when the watched area of the user's
2681 * address space is written into from within the kernel
2682 * ... wouldn't that still cause a breakpoint to be generated
2683 * from within kernel mode?
2686 if (priv_check_cred(ucred, PRIV_ROOT, 0) != 0) {
2687 if (dbregs->dr[7] & 0x3) {
2688 /* dr0 is enabled */
2689 if (dbregs->dr[0] >= VM_MAX_USER_ADDRESS)
2693 if (dbregs->dr[7] & (0x3<<2)) {
2694 /* dr1 is enabled */
2695 if (dbregs->dr[1] >= VM_MAX_USER_ADDRESS)
2699 if (dbregs->dr[7] & (0x3<<4)) {
2700 /* dr2 is enabled */
2701 if (dbregs->dr[2] >= VM_MAX_USER_ADDRESS)
2705 if (dbregs->dr[7] & (0x3<<6)) {
2706 /* dr3 is enabled */
2707 if (dbregs->dr[3] >= VM_MAX_USER_ADDRESS)
2712 pcb->pcb_dr0 = dbregs->dr[0];
2713 pcb->pcb_dr1 = dbregs->dr[1];
2714 pcb->pcb_dr2 = dbregs->dr[2];
2715 pcb->pcb_dr3 = dbregs->dr[3];
2716 pcb->pcb_dr6 = dbregs->dr[6];
2717 pcb->pcb_dr7 = dbregs->dr[7];
2719 pcb->pcb_flags |= PCB_DBREGS;
2726 * Return > 0 if a hardware breakpoint has been hit, and the
2727 * breakpoint was in user space. Return 0, otherwise.
2730 user_dbreg_trap(void)
2732 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */
2733 u_int64_t bp; /* breakpoint bits extracted from dr6 */
2734 int nbp; /* number of breakpoints that triggered */
2735 caddr_t addr[4]; /* breakpoint addresses */
2739 if ((dr7 & 0xff) == 0) {
2741 * all GE and LE bits in the dr7 register are zero,
2742 * thus the trap couldn't have been caused by the
2743 * hardware debug registers
2754 * None of the breakpoint bits are set meaning this
2755 * trap was not caused by any of the debug registers
2761 * at least one of the breakpoints were hit, check to see
2762 * which ones and if any of them are user space addresses
2766 addr[nbp++] = (caddr_t)rdr0();
2769 addr[nbp++] = (caddr_t)rdr1();
2772 addr[nbp++] = (caddr_t)rdr2();
2775 addr[nbp++] = (caddr_t)rdr3();
2778 for (i=0; i<nbp; i++) {
2780 (caddr_t)VM_MAX_USER_ADDRESS) {
2782 * addr[i] is in user space
2789 * None of the breakpoints are in user space.
2797 Debugger(const char *msg)
2799 kprintf("Debugger(\"%s\") called.\n", msg);
2806 * Provide inb() and outb() as functions. They are normally only
2807 * available as macros calling inlined functions, thus cannot be
2808 * called inside DDB.
2810 * The actual code is stolen from <machine/cpufunc.h>, and de-inlined.
2816 /* silence compiler warnings */
2818 void outb(u_int, u_char);
2825 * We use %%dx and not %1 here because i/o is done at %dx and not at
2826 * %edx, while gcc generates inferior code (movw instead of movl)
2827 * if we tell it to load (u_short) port.
2829 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port));
2834 outb(u_int port, u_char data)
2838 * Use an unnecessary assignment to help gcc's register allocator.
2839 * This make a large difference for gcc-1.40 and a tiny difference
2840 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for
2841 * best results. gcc-2.6.0 can't handle this.
2844 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port));
2852 * initialize all the SMP locks
2855 /* critical region when masking or unmasking interupts */
2856 struct spinlock_deprecated imen_spinlock;
2858 /* lock region used by kernel profiling */
2859 struct spinlock_deprecated mcount_spinlock;
2861 /* locks com (tty) data/hardware accesses: a FASTINTR() */
2862 struct spinlock_deprecated com_spinlock;
2864 /* lock regions around the clock hardware */
2865 struct spinlock_deprecated clock_spinlock;
2871 * Get the initial mplock with a count of 1 for the BSP.
2872 * This uses a LOGICAL cpu ID, ie BSP == 0.
2874 cpu_get_initial_mplock();
2876 spin_init_deprecated(&mcount_spinlock);
2877 spin_init_deprecated(&imen_spinlock);
2878 spin_init_deprecated(&com_spinlock);
2879 spin_init_deprecated(&clock_spinlock);
2881 /* our token pool needs to work early */
2882 lwkt_token_pool_init();
2886 cpu_mwait_hint_valid(uint32_t hint)
2890 cx_idx = MWAIT_EAX_TO_CX(hint);
2891 if (cx_idx >= CPU_MWAIT_CX_MAX)
2894 sub = MWAIT_EAX_TO_CX_SUB(hint);
2895 if (sub >= cpu_mwait_cx_info[cx_idx].subcnt)
2902 cpu_mwait_cx_no_bmsts(void)
2904 atomic_clear_int(&cpu_mwait_c3_preamble, CPU_MWAIT_C3_PREAMBLE_BM_STS);
2908 cpu_mwait_cx_no_bmarb(void)
2910 atomic_clear_int(&cpu_mwait_c3_preamble, CPU_MWAIT_C3_PREAMBLE_BM_ARB);
2914 cpu_mwait_cx_hint2name(int hint, char *name, int namelen, boolean_t allow_auto)
2916 int old_cx_idx, sub = 0;
2919 old_cx_idx = MWAIT_EAX_TO_CX(hint);
2920 sub = MWAIT_EAX_TO_CX_SUB(hint);
2921 } else if (hint == CPU_MWAIT_HINT_AUTO) {
2922 old_cx_idx = allow_auto ? CPU_MWAIT_C2 : CPU_MWAIT_CX_MAX;
2923 } else if (hint == CPU_MWAIT_HINT_AUTODEEP) {
2924 old_cx_idx = allow_auto ? CPU_MWAIT_C3 : CPU_MWAIT_CX_MAX;
2926 old_cx_idx = CPU_MWAIT_CX_MAX;
2929 if (!CPU_MWAIT_HAS_CX)
2930 strlcpy(name, "NONE", namelen);
2931 else if (allow_auto && hint == CPU_MWAIT_HINT_AUTO)
2932 strlcpy(name, "AUTO", namelen);
2933 else if (allow_auto && hint == CPU_MWAIT_HINT_AUTODEEP)
2934 strlcpy(name, "AUTODEEP", namelen);
2935 else if (old_cx_idx >= CPU_MWAIT_CX_MAX ||
2936 sub >= cpu_mwait_cx_info[old_cx_idx].subcnt)
2937 strlcpy(name, "INVALID", namelen);
2939 ksnprintf(name, namelen, "C%d/%d", old_cx_idx, sub);
2945 cpu_mwait_cx_name2hint(char *name, int *hint0, boolean_t allow_auto)
2947 int cx_idx, sub, hint;
2950 if (allow_auto && strcmp(name, "AUTO") == 0) {
2951 hint = CPU_MWAIT_HINT_AUTO;
2952 cx_idx = CPU_MWAIT_C2;
2955 if (allow_auto && strcmp(name, "AUTODEEP") == 0) {
2956 hint = CPU_MWAIT_HINT_AUTODEEP;
2957 cx_idx = CPU_MWAIT_C3;
2961 if (strlen(name) < 4 || toupper(name[0]) != 'C')
2966 cx_idx = strtol(start, &ptr, 10);
2967 if (ptr == start || *ptr != '/')
2969 if (cx_idx < 0 || cx_idx >= CPU_MWAIT_CX_MAX)
2975 sub = strtol(start, &ptr, 10);
2978 if (sub < 0 || sub >= cpu_mwait_cx_info[cx_idx].subcnt)
2981 hint = MWAIT_EAX_HINT(cx_idx, sub);
2988 cpu_mwait_cx_transit(int old_cx_idx, int cx_idx)
2990 if (cx_idx >= CPU_MWAIT_C3 && cpu_mwait_c3_preamble)
2992 if (old_cx_idx < CPU_MWAIT_C3 && cx_idx >= CPU_MWAIT_C3) {
2995 error = cputimer_intr_powersave_addreq();
2998 } else if (old_cx_idx >= CPU_MWAIT_C3 && cx_idx < CPU_MWAIT_C3) {
2999 cputimer_intr_powersave_remreq();
3005 cpu_mwait_cx_select_sysctl(SYSCTL_HANDLER_ARGS, int *hint0,
3006 boolean_t allow_auto)
3008 int error, cx_idx, old_cx_idx, hint;
3009 char name[CPU_MWAIT_CX_NAMELEN];
3012 old_cx_idx = cpu_mwait_cx_hint2name(hint, name, sizeof(name),
3015 error = sysctl_handle_string(oidp, name, sizeof(name), req);
3016 if (error != 0 || req->newptr == NULL)
3019 if (!CPU_MWAIT_HAS_CX)
3022 cx_idx = cpu_mwait_cx_name2hint(name, &hint, allow_auto);
3026 error = cpu_mwait_cx_transit(old_cx_idx, cx_idx);
3035 cpu_mwait_cx_setname(struct cpu_idle_stat *stat, const char *cx_name)
3037 int error, cx_idx, old_cx_idx, hint;
3038 char name[CPU_MWAIT_CX_NAMELEN];
3040 KASSERT(CPU_MWAIT_HAS_CX, ("cpu does not support mwait CX extension"));
3043 old_cx_idx = cpu_mwait_cx_hint2name(hint, name, sizeof(name), TRUE);
3045 strlcpy(name, cx_name, sizeof(name));
3046 cx_idx = cpu_mwait_cx_name2hint(name, &hint, TRUE);
3050 error = cpu_mwait_cx_transit(old_cx_idx, cx_idx);
3059 cpu_mwait_cx_idle_sysctl(SYSCTL_HANDLER_ARGS)
3061 int hint = cpu_mwait_halt_global;
3062 int error, cx_idx, cpu;
3063 char name[CPU_MWAIT_CX_NAMELEN], cx_name[CPU_MWAIT_CX_NAMELEN];
3065 cpu_mwait_cx_hint2name(hint, name, sizeof(name), TRUE);
3067 error = sysctl_handle_string(oidp, name, sizeof(name), req);
3068 if (error != 0 || req->newptr == NULL)
3071 if (!CPU_MWAIT_HAS_CX)
3074 /* Save name for later per-cpu CX configuration */
3075 strlcpy(cx_name, name, sizeof(cx_name));
3077 cx_idx = cpu_mwait_cx_name2hint(name, &hint, TRUE);
3081 /* Change per-cpu CX configuration */
3082 for (cpu = 0; cpu < ncpus; ++cpu) {
3083 error = cpu_mwait_cx_setname(&cpu_idle_stats[cpu], cx_name);
3088 cpu_mwait_halt_global = hint;
3093 cpu_mwait_cx_pcpu_idle_sysctl(SYSCTL_HANDLER_ARGS)
3095 struct cpu_idle_stat *stat = arg1;
3098 error = cpu_mwait_cx_select_sysctl(oidp, arg1, arg2, req,
3104 cpu_mwait_cx_spin_sysctl(SYSCTL_HANDLER_ARGS)
3108 error = cpu_mwait_cx_select_sysctl(oidp, arg1, arg2, req,
3109 &cpu_mwait_spin, FALSE);
3114 * This manual debugging code is called unconditionally from Xtimer
3115 * (the per-cpu timer interrupt) whether the current thread is in a
3116 * critical section or not) and can be useful in tracking down lockups.
3118 * NOTE: MANUAL DEBUG CODE
3121 static int saveticks[SMP_MAXCPU];
3122 static int savecounts[SMP_MAXCPU];
3126 pcpu_timer_always(struct intrframe *frame)
3129 globaldata_t gd = mycpu;
3130 int cpu = gd->gd_cpuid;
3136 gptr = (short *)0xFFFFFFFF800b8000 + 80 * cpu;
3137 *gptr = ((*gptr + 1) & 0x00FF) | 0x0700;
3140 ksnprintf(buf, sizeof(buf), " %p %16s %d %16s ",
3141 (void *)frame->if_rip, gd->gd_curthread->td_comm, ticks,
3143 for (i = 0; buf[i]; ++i) {
3144 gptr[i] = 0x0700 | (unsigned char)buf[i];
3148 if (saveticks[gd->gd_cpuid] != ticks) {
3149 saveticks[gd->gd_cpuid] = ticks;
3150 savecounts[gd->gd_cpuid] = 0;
3152 ++savecounts[gd->gd_cpuid];
3153 if (savecounts[gd->gd_cpuid] > 2000 && panicstr == NULL) {
3154 panic("cpud %d panicing on ticks failure",
3157 for (i = 0; i < ncpus; ++i) {
3159 if (saveticks[i] && panicstr == NULL) {
3160 delta = saveticks[i] - ticks;
3161 if (delta < -10 || delta > 10) {
3162 panic("cpu %d panicing on cpu %d watchdog",