3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
5 * Copyright (c) 1997, 1998-2003
6 * Bill Paul <wpaul@windriver.com>. All rights reserved.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Bill Paul.
19 * 4. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGE.
35 * $FreeBSD: src/sys/dev/re/if_re.c,v 1.25 2004/06/09 14:34:01 naddy Exp $
36 * $DragonFly: src/sys/dev/netif/re/if_re.c,v 1.25 2006/10/16 13:32:02 sephe Exp $
40 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver
42 * Written by Bill Paul <wpaul@windriver.com>
43 * Senior Networking Software Engineer
48 * This driver is designed to support RealTek's next generation of
49 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
50 * four devices in this family: the RTL8139C+, the RTL8169, the RTL8169S
53 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
54 * with the older 8139 family, however it also supports a special
55 * C+ mode of operation that provides several new performance enhancing
56 * features. These include:
58 * o Descriptor based DMA mechanism. Each descriptor represents
59 * a single packet fragment. Data buffers may be aligned on
64 * o TCP/IP checksum offload for both RX and TX
66 * o High and normal priority transmit DMA rings
68 * o VLAN tag insertion and extraction
70 * o TCP large send (segmentation offload)
72 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
73 * programming API is fairly straightforward. The RX filtering, EEPROM
74 * access and PHY access is the same as it is on the older 8139 series
77 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
78 * same programming API and feature set as the 8139C+ with the following
79 * differences and additions:
85 * o GMII and TBI ports/registers for interfacing with copper
88 * o RX and TX DMA rings can have up to 1024 descriptors
89 * (the 8139C+ allows a maximum of 64)
91 * o Slight differences in register layout from the 8139C+
93 * The TX start and timer interrupt registers are at different locations
94 * on the 8169 than they are on the 8139C+. Also, the status word in the
95 * RX descriptor has a slightly different bit layout. The 8169 does not
96 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
99 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
100 * (the 'S' stands for 'single-chip'). These devices have the same
101 * programming API as the older 8169, but also have some vendor-specific
102 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
103 * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
105 * This driver takes advantage of the RX and TX checksum offload and
106 * VLAN tag insertion/extraction features. It also implements TX
107 * interrupt moderation using the timer interrupt registers, which
108 * significantly reduces TX interrupt load. There is also support
109 * for jumbo frames, however the 8169/8169S/8110S can not transmit
110 * jumbo frames larger than 7440, so the max MTU possible with this
111 * driver is 7422 bytes.
114 #include "opt_polling.h"
116 #include <sys/param.h>
117 #include <sys/endian.h>
118 #include <sys/systm.h>
119 #include <sys/sockio.h>
120 #include <sys/mbuf.h>
121 #include <sys/malloc.h>
122 #include <sys/module.h>
123 #include <sys/kernel.h>
124 #include <sys/socket.h>
125 #include <sys/serialize.h>
126 #include <sys/thread2.h>
129 #include <net/ifq_var.h>
130 #include <net/if_arp.h>
131 #include <net/ethernet.h>
132 #include <net/if_dl.h>
133 #include <net/if_media.h>
134 #include <net/if_types.h>
135 #include <net/vlan/if_vlan_var.h>
139 #include <machine/bus_pio.h>
140 #include <machine/bus_memio.h>
141 #include <machine/bus.h>
142 #include <machine/resource.h>
144 #include <sys/rman.h>
146 #include <dev/netif/mii_layer/mii.h>
147 #include <dev/netif/mii_layer/miivar.h>
149 #include <bus/pci/pcidevs.h>
150 #include <bus/pci/pcireg.h>
151 #include <bus/pci/pcivar.h>
153 /* "controller miibus0" required. See GENERIC if you get errors here. */
154 #include "miibus_if.h"
156 #include <dev/netif/re/if_rereg.h>
159 * The hardware supports checksumming but, as usual, some chipsets screw it
160 * all up and produce bogus packets, so we disable it by default.
162 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
163 #define RE_DISABLE_HWCSUM
166 * Various supported device vendors/types and their names.
168 static struct re_type re_devs[] = {
169 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE528T, RE_HWREV_8169S,
170 "D-Link DGE-528(T) Gigabit Ethernet Adapter" },
171 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139, RE_HWREV_8139CPLUS,
172 "RealTek 8139C+ 10/100BaseTX" },
173 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169,
174 "RealTek 8169 Gigabit Ethernet" },
175 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169S,
176 "RealTek 8169S Single-chip Gigabit Ethernet" },
177 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8110S,
178 "RealTek 8110S Single-chip Gigabit Ethernet" },
179 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_CG_LAPCIGT, RE_HWREV_8169S,
180 "Corega CG-LAPCIGT Gigabit Ethernet" },
184 static struct re_hwrev re_hwrevs[] = {
185 { RE_HWREV_8139CPLUS, RE_8139CPLUS, "C+"},
186 { RE_HWREV_8169, RE_8169, "8169"},
187 { RE_HWREV_8169S, RE_8169, "8169S"},
188 { RE_HWREV_8110S, RE_8169, "8110S"},
192 static int re_probe(device_t);
193 static int re_attach(device_t);
194 static int re_detach(device_t);
196 static int re_encap(struct re_softc *, struct mbuf **, int *, int *);
198 static void re_dma_map_addr(void *, bus_dma_segment_t *, int, int);
199 static void re_dma_map_desc(void *, bus_dma_segment_t *, int,
201 static int re_allocmem(device_t, struct re_softc *);
202 static int re_newbuf(struct re_softc *, int, struct mbuf *);
203 static int re_rx_list_init(struct re_softc *);
204 static int re_tx_list_init(struct re_softc *);
205 static void re_rxeof(struct re_softc *);
206 static void re_txeof(struct re_softc *);
207 static void re_intr(void *);
208 static void re_tick(void *);
209 static void re_tick_serialized(void *);
210 static void re_start(struct ifnet *);
211 static int re_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
212 static void re_init(void *);
213 static void re_stop(struct re_softc *);
214 static void re_watchdog(struct ifnet *);
215 static int re_suspend(device_t);
216 static int re_resume(device_t);
217 static void re_shutdown(device_t);
218 static int re_ifmedia_upd(struct ifnet *);
219 static void re_ifmedia_sts(struct ifnet *, struct ifmediareq *);
221 static void re_eeprom_putbyte(struct re_softc *, int);
222 static void re_eeprom_getword(struct re_softc *, int, u_int16_t *);
223 static void re_read_eeprom(struct re_softc *, caddr_t, int, int, int);
224 static int re_gmii_readreg(device_t, int, int);
225 static int re_gmii_writereg(device_t, int, int, int);
227 static int re_miibus_readreg(device_t, int, int);
228 static int re_miibus_writereg(device_t, int, int, int);
229 static void re_miibus_statchg(device_t);
231 static void re_setmulti(struct re_softc *);
232 static void re_reset(struct re_softc *);
234 static int re_diag(struct re_softc *);
235 #ifdef DEVICE_POLLING
236 static void re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
239 static device_method_t re_methods[] = {
240 /* Device interface */
241 DEVMETHOD(device_probe, re_probe),
242 DEVMETHOD(device_attach, re_attach),
243 DEVMETHOD(device_detach, re_detach),
244 DEVMETHOD(device_suspend, re_suspend),
245 DEVMETHOD(device_resume, re_resume),
246 DEVMETHOD(device_shutdown, re_shutdown),
249 DEVMETHOD(bus_print_child, bus_generic_print_child),
250 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
253 DEVMETHOD(miibus_readreg, re_miibus_readreg),
254 DEVMETHOD(miibus_writereg, re_miibus_writereg),
255 DEVMETHOD(miibus_statchg, re_miibus_statchg),
260 static driver_t re_driver = {
263 sizeof(struct re_softc)
266 static devclass_t re_devclass;
268 DECLARE_DUMMY_MODULE(if_re);
269 DRIVER_MODULE(if_re, pci, re_driver, re_devclass, 0, 0);
270 DRIVER_MODULE(if_re, cardbus, re_driver, re_devclass, 0, 0);
271 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0);
274 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) | (x))
277 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) & ~(x))
280 * Send a read command and address to the EEPROM, check for ACK.
283 re_eeprom_putbyte(struct re_softc *sc, int addr)
287 d = addr | sc->re_eecmd_read;
290 * Feed in each bit and strobe the clock.
292 for (i = 0x400; i != 0; i >>= 1) {
294 EE_SET(RE_EE_DATAIN);
296 EE_CLR(RE_EE_DATAIN);
306 * Read a word of data stored in the EEPROM at address 'addr.'
309 re_eeprom_getword(struct re_softc *sc, int addr, uint16_t *dest)
314 /* Enter EEPROM access mode. */
315 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_PROGRAM|RE_EE_SEL);
318 * Send address of word we want to read.
320 re_eeprom_putbyte(sc, addr);
322 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_PROGRAM|RE_EE_SEL);
325 * Start reading bits from EEPROM.
327 for (i = 0x8000; i != 0; i >>= 1) {
330 if (CSR_READ_1(sc, RE_EECMD) & RE_EE_DATAOUT)
336 /* Turn off EEPROM access mode. */
337 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF);
343 * Read a sequence of words from the EEPROM.
346 re_read_eeprom(struct re_softc *sc, caddr_t dest, int off, int cnt, int swap)
349 uint16_t word = 0, *ptr;
351 for (i = 0; i < cnt; i++) {
352 re_eeprom_getword(sc, off + i, &word);
353 ptr = (u_int16_t *)(dest + (i * 2));
355 *ptr = be16toh(word);
362 re_gmii_readreg(device_t dev, int phy, int reg)
364 struct re_softc *sc = device_get_softc(dev);
371 /* Let the rgephy driver read the GMEDIASTAT register */
373 if (reg == RE_GMEDIASTAT)
374 return(CSR_READ_1(sc, RE_GMEDIASTAT));
376 CSR_WRITE_4(sc, RE_PHYAR, reg << 16);
379 for (i = 0; i < RE_TIMEOUT; i++) {
380 rval = CSR_READ_4(sc, RE_PHYAR);
381 if (rval & RE_PHYAR_BUSY)
386 if (i == RE_TIMEOUT) {
387 device_printf(dev, "PHY read failed\n");
391 return(rval & RE_PHYAR_PHYDATA);
395 re_gmii_writereg(device_t dev, int phy, int reg, int data)
397 struct re_softc *sc = device_get_softc(dev);
401 CSR_WRITE_4(sc, RE_PHYAR,
402 (reg << 16) | (data & RE_PHYAR_PHYDATA) | RE_PHYAR_BUSY);
405 for (i = 0; i < RE_TIMEOUT; i++) {
406 rval = CSR_READ_4(sc, RE_PHYAR);
407 if ((rval & RE_PHYAR_BUSY) == 0)
413 device_printf(dev, "PHY write failed\n");
419 re_miibus_readreg(device_t dev, int phy, int reg)
421 struct re_softc *sc = device_get_softc(dev);
423 uint16_t re8139_reg = 0;
425 if (sc->re_type == RE_8169) {
426 rval = re_gmii_readreg(dev, phy, reg);
430 /* Pretend the internal PHY is only at address 0 */
436 re8139_reg = RE_BMCR;
439 re8139_reg = RE_BMSR;
442 re8139_reg = RE_ANAR;
445 re8139_reg = RE_ANER;
448 re8139_reg = RE_LPAR;
454 * Allow the rlphy driver to read the media status
455 * register. If we have a link partner which does not
456 * support NWAY, this is the register which will tell
457 * us the results of parallel detection.
460 return(CSR_READ_1(sc, RE_MEDIASTAT));
462 device_printf(dev, "bad phy register\n");
465 rval = CSR_READ_2(sc, re8139_reg);
470 re_miibus_writereg(device_t dev, int phy, int reg, int data)
472 struct re_softc *sc= device_get_softc(dev);
473 u_int16_t re8139_reg = 0;
475 if (sc->re_type == RE_8169)
476 return(re_gmii_writereg(dev, phy, reg, data));
478 /* Pretend the internal PHY is only at address 0 */
484 re8139_reg = RE_BMCR;
487 re8139_reg = RE_BMSR;
490 re8139_reg = RE_ANAR;
493 re8139_reg = RE_ANER;
496 re8139_reg = RE_LPAR;
502 device_printf(dev, "bad phy register\n");
505 CSR_WRITE_2(sc, re8139_reg, data);
510 re_miibus_statchg(device_t dev)
515 * Program the 64-bit multicast hash filter.
518 re_setmulti(struct re_softc *sc)
520 struct ifnet *ifp = &sc->arpcom.ac_if;
522 uint32_t hashes[2] = { 0, 0 };
523 struct ifmultiaddr *ifma;
527 rxfilt = CSR_READ_4(sc, RE_RXCFG);
529 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
530 rxfilt |= RE_RXCFG_RX_MULTI;
531 CSR_WRITE_4(sc, RE_RXCFG, rxfilt);
532 CSR_WRITE_4(sc, RE_MAR0, 0xFFFFFFFF);
533 CSR_WRITE_4(sc, RE_MAR4, 0xFFFFFFFF);
537 /* first, zot all the existing hash bits */
538 CSR_WRITE_4(sc, RE_MAR0, 0);
539 CSR_WRITE_4(sc, RE_MAR4, 0);
541 /* now program new ones */
542 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
543 if (ifma->ifma_addr->sa_family != AF_LINK)
545 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
546 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
548 hashes[0] |= (1 << h);
550 hashes[1] |= (1 << (h - 32));
555 rxfilt |= RE_RXCFG_RX_MULTI;
557 rxfilt &= ~RE_RXCFG_RX_MULTI;
559 CSR_WRITE_4(sc, RE_RXCFG, rxfilt);
560 CSR_WRITE_4(sc, RE_MAR0, hashes[0]);
561 CSR_WRITE_4(sc, RE_MAR4, hashes[1]);
565 re_reset(struct re_softc *sc)
569 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_RESET);
571 for (i = 0; i < RE_TIMEOUT; i++) {
573 if ((CSR_READ_1(sc, RE_COMMAND) & RE_CMD_RESET) == 0)
577 if_printf(&sc->arpcom.ac_if, "reset never completed!\n");
579 CSR_WRITE_1(sc, 0x82, 1);
583 * The following routine is designed to test for a defect on some
584 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
585 * lines connected to the bus, however for a 32-bit only card, they
586 * should be pulled high. The result of this defect is that the
587 * NIC will not work right if you plug it into a 64-bit slot: DMA
588 * operations will be done with 64-bit transfers, which will fail
589 * because the 64-bit data lines aren't connected.
591 * There's no way to work around this (short of talking a soldering
592 * iron to the board), however we can detect it. The method we use
593 * here is to put the NIC into digital loopback mode, set the receiver
594 * to promiscuous mode, and then try to send a frame. We then compare
595 * the frame data we sent to what was received. If the data matches,
596 * then the NIC is working correctly, otherwise we know the user has
597 * a defective NIC which has been mistakenly plugged into a 64-bit PCI
598 * slot. In the latter case, there's no way the NIC can work correctly,
599 * so we print out a message on the console and abort the device attach.
603 re_diag(struct re_softc *sc)
605 struct ifnet *ifp = &sc->arpcom.ac_if;
607 struct ether_header *eh;
608 struct re_desc *cur_rx;
611 int total_len, i, error = 0;
612 uint8_t dst[ETHER_ADDR_LEN] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
613 uint8_t src[ETHER_ADDR_LEN] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
615 /* Allocate a single mbuf */
617 MGETHDR(m0, MB_DONTWAIT, MT_DATA);
622 * Initialize the NIC in test mode. This sets the chip up
623 * so that it can send and receive frames, but performs the
624 * following special functions:
625 * - Puts receiver in promiscuous mode
626 * - Enables digital loopback mode
627 * - Leaves interrupts turned off
630 ifp->if_flags |= IFF_PROMISC;
637 /* Put some data in the mbuf */
639 eh = mtod(m0, struct ether_header *);
640 bcopy (dst, eh->ether_dhost, ETHER_ADDR_LEN);
641 bcopy (src, eh->ether_shost, ETHER_ADDR_LEN);
642 eh->ether_type = htons(ETHERTYPE_IP);
643 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
646 * Queue the packet, start transmission.
647 * Note: ifq_handoff() ultimately calls re_start() for us.
650 CSR_WRITE_2(sc, RE_ISR, 0xFFFF);
651 error = ifq_handoff(ifp, m0, NULL);
658 /* Wait for it to propagate through the chip */
661 for (i = 0; i < RE_TIMEOUT; i++) {
662 status = CSR_READ_2(sc, RE_ISR);
663 if ((status & (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) ==
664 (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK))
669 if (i == RE_TIMEOUT) {
670 if_printf(ifp, "diagnostic failed to receive packet "
671 "in loopback mode\n");
677 * The packet should have been dumped into the first
678 * entry in the RX DMA ring. Grab it from there.
681 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
682 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD);
683 bus_dmamap_sync(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0],
684 BUS_DMASYNC_POSTWRITE);
685 bus_dmamap_unload(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0]);
687 m0 = sc->re_ldata.re_rx_mbuf[0];
688 sc->re_ldata.re_rx_mbuf[0] = NULL;
689 eh = mtod(m0, struct ether_header *);
691 cur_rx = &sc->re_ldata.re_rx_list[0];
692 total_len = RE_RXBYTES(cur_rx);
693 rxstat = le32toh(cur_rx->re_cmdstat);
695 if (total_len != ETHER_MIN_LEN) {
696 if_printf(ifp, "diagnostic failed, received short packet\n");
701 /* Test that the received packet data matches what we sent. */
703 if (bcmp(eh->ether_dhost, dst, ETHER_ADDR_LEN) ||
704 bcmp(eh->ether_shost, &src, ETHER_ADDR_LEN) ||
705 be16toh(eh->ether_type) != ETHERTYPE_IP) {
706 if_printf(ifp, "WARNING, DMA FAILURE!\n");
707 if_printf(ifp, "expected TX data: %6D/%6D/0x%x\n",
708 dst, ":", src, ":", ETHERTYPE_IP);
709 if_printf(ifp, "received RX data: %6D/%6D/0x%x\n",
710 eh->ether_dhost, ":", eh->ether_shost, ":",
711 ntohs(eh->ether_type));
712 if_printf(ifp, "You may have a defective 32-bit NIC plugged "
713 "into a 64-bit PCI slot.\n");
714 if_printf(ifp, "Please re-install the NIC in a 32-bit slot "
715 "for proper operation.\n");
716 if_printf(ifp, "Read the re(4) man page for more details.\n");
721 /* Turn interface off, release resources */
724 ifp->if_flags &= ~IFF_PROMISC;
733 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
734 * IDs against our list and return a device name if we find a match.
737 re_probe(device_t dev)
743 uint16_t vendor, product;
747 vendor = pci_get_vendor(dev);
748 product = pci_get_device(dev);
750 for (t = re_devs; t->re_name != NULL; t++) {
751 if (product == t->re_did && vendor == t->re_vid)
756 * Check if we found a RealTek device.
758 if (t->re_name == NULL)
762 * Temporarily map the I/O space so we can read the chip ID register.
764 sc = kmalloc(sizeof(*sc), M_TEMP, M_WAITOK | M_ZERO);
766 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
768 if (sc->re_res == NULL) {
769 device_printf(dev, "couldn't map ports/memory\n");
774 sc->re_btag = rman_get_bustag(sc->re_res);
775 sc->re_bhandle = rman_get_bushandle(sc->re_res);
777 hwrev = CSR_READ_4(sc, RE_TXCFG) & RE_TXCFG_HWREV;
778 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, sc->re_res);
782 * and continue matching for the specific chip...
784 for (; t->re_name != NULL; t++) {
785 if (product == t->re_did && vendor == t->re_vid &&
786 t->re_basetype == hwrev) {
787 device_set_desc(dev, t->re_name);
795 * This routine takes the segment list provided as the result of
796 * a bus_dma_map_load() operation and assigns the addresses/lengths
797 * to RealTek DMA descriptors. This can be called either by the RX
798 * code or the TX code. In the RX case, we'll probably wind up mapping
799 * at most one segment. For the TX case, there could be any number of
800 * segments since TX packets may span multiple mbufs. In either case,
801 * if the number of segments is larger than the re_maxsegs limit
802 * specified by the caller, we abort the mapping operation. Sadly,
803 * whoever designed the buffer mapping API did not provide a way to
804 * return an error from here, so we have to fake it a bit.
808 re_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg,
809 bus_size_t mapsize, int error)
811 struct re_dmaload_arg *ctx;
812 struct re_desc *d = NULL;
821 /* Signal error to caller if there's too many segments */
822 if (nseg > ctx->re_maxsegs) {
828 * Map the segment array into descriptors. Note that we set the
829 * start-of-frame and end-of-frame markers for either TX or RX, but
830 * they really only have meaning in the TX case. (In the RX case,
831 * it's the chip that tells us where packets begin and end.)
832 * We also keep track of the end of the ring and set the
833 * end-of-ring bits as needed, and we set the ownership bits
834 * in all except the very first descriptor. (The caller will
835 * set this descriptor later when it start transmission or
840 d = &ctx->re_ring[idx];
841 if (le32toh(d->re_cmdstat) & RE_RDESC_STAT_OWN) {
845 cmdstat = segs[i].ds_len;
846 d->re_bufaddr_lo = htole32(RE_ADDR_LO(segs[i].ds_addr));
847 d->re_bufaddr_hi = htole32(RE_ADDR_HI(segs[i].ds_addr));
849 cmdstat |= RE_TDESC_CMD_SOF;
851 cmdstat |= RE_TDESC_CMD_OWN;
852 if (idx == (RE_RX_DESC_CNT - 1))
853 cmdstat |= RE_TDESC_CMD_EOR;
854 d->re_cmdstat = htole32(cmdstat | ctx->re_flags);
861 d->re_cmdstat |= htole32(RE_TDESC_CMD_EOF);
862 ctx->re_maxsegs = nseg;
867 * Map a single buffer address.
871 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
878 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
880 *addr = segs->ds_addr;
884 re_allocmem(device_t dev, struct re_softc *sc)
889 * Allocate map for RX mbufs.
892 error = bus_dma_tag_create(sc->re_parent_tag, ETHER_ALIGN, 0,
893 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
894 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW,
895 &sc->re_ldata.re_mtag);
897 device_printf(dev, "could not allocate dma tag\n");
902 * Allocate map for TX descriptor list.
904 error = bus_dma_tag_create(sc->re_parent_tag, RE_RING_ALIGN,
905 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
906 NULL, RE_TX_LIST_SZ, 1, RE_TX_LIST_SZ, BUS_DMA_ALLOCNOW,
907 &sc->re_ldata.re_tx_list_tag);
909 device_printf(dev, "could not allocate dma tag\n");
913 /* Allocate DMA'able memory for the TX ring */
915 error = bus_dmamem_alloc(sc->re_ldata.re_tx_list_tag,
916 (void **)&sc->re_ldata.re_tx_list, BUS_DMA_WAITOK | BUS_DMA_ZERO,
917 &sc->re_ldata.re_tx_list_map);
919 device_printf(dev, "could not allocate TX ring\n");
923 /* Load the map for the TX ring. */
925 error = bus_dmamap_load(sc->re_ldata.re_tx_list_tag,
926 sc->re_ldata.re_tx_list_map, sc->re_ldata.re_tx_list,
927 RE_TX_LIST_SZ, re_dma_map_addr,
928 &sc->re_ldata.re_tx_list_addr, BUS_DMA_NOWAIT);
930 device_printf(dev, "could not get addres of TX ring\n");
934 /* Create DMA maps for TX buffers */
936 for (i = 0; i < RE_TX_DESC_CNT; i++) {
937 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0,
938 &sc->re_ldata.re_tx_dmamap[i]);
940 device_printf(dev, "can't create DMA map for TX\n");
946 * Allocate map for RX descriptor list.
948 error = bus_dma_tag_create(sc->re_parent_tag, RE_RING_ALIGN,
949 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
950 NULL, RE_RX_LIST_SZ, 1, RE_RX_LIST_SZ, BUS_DMA_ALLOCNOW,
951 &sc->re_ldata.re_rx_list_tag);
953 device_printf(dev, "could not allocate dma tag\n");
957 /* Allocate DMA'able memory for the RX ring */
959 error = bus_dmamem_alloc(sc->re_ldata.re_rx_list_tag,
960 (void **)&sc->re_ldata.re_rx_list, BUS_DMA_WAITOK | BUS_DMA_ZERO,
961 &sc->re_ldata.re_rx_list_map);
963 device_printf(dev, "could not allocate RX ring\n");
967 /* Load the map for the RX ring. */
969 error = bus_dmamap_load(sc->re_ldata.re_rx_list_tag,
970 sc->re_ldata.re_rx_list_map, sc->re_ldata.re_rx_list,
971 RE_RX_LIST_SZ, re_dma_map_addr,
972 &sc->re_ldata.re_rx_list_addr, BUS_DMA_NOWAIT);
974 device_printf(dev, "could not get address of RX ring\n");
978 /* Create DMA maps for RX buffers */
980 for (i = 0; i < RE_RX_DESC_CNT; i++) {
981 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0,
982 &sc->re_ldata.re_rx_dmamap[i]);
984 device_printf(dev, "can't create DMA map for RX\n");
993 * Attach the interface. Allocate softc structures, do ifmedia
994 * setup and ethernet/BPF attach.
997 re_attach(device_t dev)
999 struct re_softc *sc = device_get_softc(dev);
1001 struct re_hwrev *hw_rev;
1002 uint8_t eaddr[ETHER_ADDR_LEN];
1004 u_int16_t re_did = 0;
1005 int error = 0, rid, i;
1007 callout_init(&sc->re_timer);
1009 #ifndef BURN_BRIDGES
1011 * Handle power management nonsense.
1014 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1015 uint32_t membase, irq;
1017 /* Save important PCI config data. */
1018 membase = pci_read_config(dev, RE_PCI_LOMEM, 4);
1019 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1021 /* Reset the power state. */
1022 device_printf(dev, "chip is is in D%d power mode "
1023 "-- setting to D0\n", pci_get_powerstate(dev));
1025 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1027 /* Restore PCI config data. */
1028 pci_write_config(dev, RE_PCI_LOMEM, membase, 4);
1029 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1033 * Map control/status registers.
1035 pci_enable_busmaster(dev);
1038 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
1041 if (sc->re_res == NULL) {
1042 device_printf(dev, "couldn't map ports/memory\n");
1047 sc->re_btag = rman_get_bustag(sc->re_res);
1048 sc->re_bhandle = rman_get_bushandle(sc->re_res);
1050 /* Allocate interrupt */
1052 sc->re_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1053 RF_SHAREABLE | RF_ACTIVE);
1055 if (sc->re_irq == NULL) {
1056 device_printf(dev, "couldn't map interrupt\n");
1061 /* Reset the adapter. */
1064 hwrev = CSR_READ_4(sc, RE_TXCFG) & RE_TXCFG_HWREV;
1065 for (hw_rev = re_hwrevs; hw_rev->re_desc != NULL; hw_rev++) {
1066 if (hw_rev->re_rev == hwrev) {
1067 sc->re_type = hw_rev->re_type;
1072 if (sc->re_type == RE_8169) {
1073 /* Set RX length mask */
1074 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN;
1076 /* Force station address autoload from the EEPROM */
1077 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_AUTOLOAD);
1078 for (i = 0; i < RE_TIMEOUT; i++) {
1079 if ((CSR_READ_1(sc, RE_EECMD) & RE_EEMODE_AUTOLOAD) == 0)
1083 if (i == RE_TIMEOUT)
1084 device_printf(dev, "eeprom autoload timed out\n");
1086 for (i = 0; i < ETHER_ADDR_LEN; i++)
1087 eaddr[i] = CSR_READ_1(sc, RE_IDR0 + i);
1091 /* Set RX length mask */
1092 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN;
1094 sc->re_eecmd_read = RE_EECMD_READ_6BIT;
1095 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1, 0);
1096 if (re_did != 0x8129)
1097 sc->re_eecmd_read = RE_EECMD_READ_8BIT;
1100 * Get station address from the EEPROM.
1102 re_read_eeprom(sc, (caddr_t)as, RE_EE_EADDR, 3, 0);
1103 for (i = 0; i < 3; i++) {
1104 eaddr[(i * 2) + 0] = as[i] & 0xff;
1105 eaddr[(i * 2) + 1] = as[i] >> 8;
1110 * Allocate the parent bus DMA tag appropriate for PCI.
1112 #define RE_NSEG_NEW 32
1113 error = bus_dma_tag_create(NULL, /* parent */
1114 1, 0, /* alignment, boundary */
1115 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
1116 BUS_SPACE_MAXADDR, /* highaddr */
1117 NULL, NULL, /* filter, filterarg */
1118 MAXBSIZE, RE_NSEG_NEW, /* maxsize, nsegments */
1119 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1120 BUS_DMA_ALLOCNOW, /* flags */
1121 &sc->re_parent_tag);
1125 error = re_allocmem(dev, sc);
1131 if (mii_phy_probe(dev, &sc->re_miibus,
1132 re_ifmedia_upd, re_ifmedia_sts)) {
1133 device_printf(dev, "MII without any phy!\n");
1138 ifp = &sc->arpcom.ac_if;
1140 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1141 ifp->if_mtu = ETHERMTU;
1142 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1143 ifp->if_ioctl = re_ioctl;
1144 ifp->if_capabilities = IFCAP_VLAN_MTU;
1145 ifp->if_start = re_start;
1146 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING;
1147 #ifdef DEVICE_POLLING
1148 ifp->if_poll = re_poll;
1150 ifp->if_watchdog = re_watchdog;
1151 ifp->if_init = re_init;
1152 if (sc->re_type == RE_8169)
1153 ifp->if_baudrate = 1000000000;
1155 ifp->if_baudrate = 100000000;
1156 ifq_set_maxlen(&ifp->if_snd, RE_IFQ_MAXLEN);
1157 ifq_set_ready(&ifp->if_snd);
1158 #ifdef RE_DISABLE_HWCSUM
1159 ifp->if_capenable = ifp->if_capabilities & ~IFCAP_HWCSUM;
1160 ifp->if_hwassist = 0;
1162 ifp->if_capenable = ifp->if_capabilities;
1163 ifp->if_hwassist = RE_CSUM_FEATURES;
1167 * Call MI attach routine.
1169 ether_ifattach(ifp, eaddr, NULL);
1171 lwkt_serialize_enter(ifp->if_serializer);
1172 /* Perform hardware diagnostic. */
1173 error = re_diag(sc);
1174 lwkt_serialize_exit(ifp->if_serializer);
1177 device_printf(dev, "hardware diagnostic failure\n");
1178 ether_ifdetach(ifp);
1182 /* Hook interrupt last to avoid having to lock softc */
1183 error = bus_setup_intr(dev, sc->re_irq, INTR_NETSAFE, re_intr, sc,
1184 &sc->re_intrhand, ifp->if_serializer);
1187 device_printf(dev, "couldn't set up irq\n");
1188 ether_ifdetach(ifp);
1200 * Shutdown hardware and free up resources. This can be called any
1201 * time after the mutex has been initialized. It is called in both
1202 * the error case in attach and the normal detach case so it needs
1203 * to be careful about only freeing resources that have actually been
1207 re_detach(device_t dev)
1209 struct re_softc *sc = device_get_softc(dev);
1210 struct ifnet *ifp = &sc->arpcom.ac_if;
1213 /* These should only be active if attach succeeded */
1214 if (device_is_attached(dev)) {
1215 lwkt_serialize_enter(ifp->if_serializer);
1217 bus_teardown_intr(dev, sc->re_irq, sc->re_intrhand);
1218 lwkt_serialize_exit(ifp->if_serializer);
1220 ether_ifdetach(ifp);
1223 device_delete_child(dev, sc->re_miibus);
1224 bus_generic_detach(dev);
1227 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->re_irq);
1229 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO,
1233 /* Unload and free the RX DMA ring memory and map */
1235 if (sc->re_ldata.re_rx_list_tag) {
1236 bus_dmamap_unload(sc->re_ldata.re_rx_list_tag,
1237 sc->re_ldata.re_rx_list_map);
1238 bus_dmamem_free(sc->re_ldata.re_rx_list_tag,
1239 sc->re_ldata.re_rx_list,
1240 sc->re_ldata.re_rx_list_map);
1241 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag);
1244 /* Unload and free the TX DMA ring memory and map */
1246 if (sc->re_ldata.re_tx_list_tag) {
1247 bus_dmamap_unload(sc->re_ldata.re_tx_list_tag,
1248 sc->re_ldata.re_tx_list_map);
1249 bus_dmamem_free(sc->re_ldata.re_tx_list_tag,
1250 sc->re_ldata.re_tx_list,
1251 sc->re_ldata.re_tx_list_map);
1252 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag);
1255 /* Destroy all the RX and TX buffer maps */
1257 if (sc->re_ldata.re_mtag) {
1258 for (i = 0; i < RE_TX_DESC_CNT; i++)
1259 bus_dmamap_destroy(sc->re_ldata.re_mtag,
1260 sc->re_ldata.re_tx_dmamap[i]);
1261 for (i = 0; i < RE_RX_DESC_CNT; i++)
1262 bus_dmamap_destroy(sc->re_ldata.re_mtag,
1263 sc->re_ldata.re_rx_dmamap[i]);
1264 bus_dma_tag_destroy(sc->re_ldata.re_mtag);
1267 /* Unload and free the stats buffer and map */
1269 if (sc->re_ldata.re_stag) {
1270 bus_dmamap_unload(sc->re_ldata.re_stag,
1271 sc->re_ldata.re_rx_list_map);
1272 bus_dmamem_free(sc->re_ldata.re_stag,
1273 sc->re_ldata.re_stats,
1274 sc->re_ldata.re_smap);
1275 bus_dma_tag_destroy(sc->re_ldata.re_stag);
1278 if (sc->re_parent_tag)
1279 bus_dma_tag_destroy(sc->re_parent_tag);
1285 re_newbuf(struct re_softc *sc, int idx, struct mbuf *m)
1287 struct re_dmaload_arg arg;
1288 struct mbuf *n = NULL;
1292 n = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
1297 m->m_data = m->m_ext.ext_buf;
1300 * Initialize mbuf length fields and fixup
1301 * alignment so that the frame payload is
1304 m->m_len = m->m_pkthdr.len = MCLBYTES;
1305 m_adj(m, ETHER_ALIGN);
1311 arg.re_ring = sc->re_ldata.re_rx_list;
1313 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag,
1314 sc->re_ldata.re_rx_dmamap[idx], m, re_dma_map_desc,
1315 &arg, BUS_DMA_NOWAIT);
1316 if (error || arg.re_maxsegs != 1) {
1322 sc->re_ldata.re_rx_list[idx].re_cmdstat |= htole32(RE_RDESC_CMD_OWN);
1323 sc->re_ldata.re_rx_mbuf[idx] = m;
1325 bus_dmamap_sync(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[idx],
1326 BUS_DMASYNC_PREREAD);
1332 re_tx_list_init(struct re_softc *sc)
1334 bzero(sc->re_ldata.re_tx_list, RE_TX_LIST_SZ);
1335 bzero(&sc->re_ldata.re_tx_mbuf, RE_TX_DESC_CNT * sizeof(struct mbuf *));
1337 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
1338 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_PREWRITE);
1339 sc->re_ldata.re_tx_prodidx = 0;
1340 sc->re_ldata.re_tx_considx = 0;
1341 sc->re_ldata.re_tx_free = RE_TX_DESC_CNT;
1347 re_rx_list_init(struct re_softc *sc)
1351 bzero(sc->re_ldata.re_rx_list, RE_RX_LIST_SZ);
1352 bzero(&sc->re_ldata.re_rx_mbuf, RE_RX_DESC_CNT * sizeof(struct mbuf *));
1354 for (i = 0; i < RE_RX_DESC_CNT; i++) {
1355 error = re_newbuf(sc, i, NULL);
1360 /* Flush the RX descriptors */
1362 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1363 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_PREWRITE);
1365 sc->re_ldata.re_rx_prodidx = 0;
1366 sc->re_head = sc->re_tail = NULL;
1372 * RX handler for C+ and 8169. For the gigE chips, we support
1373 * the reception of jumbo frames that have been fragmented
1374 * across multiple 2K mbuf cluster buffers.
1377 re_rxeof(struct re_softc *sc)
1379 struct ifnet *ifp = &sc->arpcom.ac_if;
1381 struct re_desc *cur_rx;
1382 uint32_t rxstat, rxvlan;
1385 /* Invalidate the descriptor memory */
1387 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1388 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD);
1390 for (i = sc->re_ldata.re_rx_prodidx;
1391 RE_OWN(&sc->re_ldata.re_rx_list[i]) == 0 ; RE_DESC_INC(i)) {
1392 cur_rx = &sc->re_ldata.re_rx_list[i];
1393 m = sc->re_ldata.re_rx_mbuf[i];
1394 total_len = RE_RXBYTES(cur_rx);
1395 rxstat = le32toh(cur_rx->re_cmdstat);
1396 rxvlan = le32toh(cur_rx->re_vlanctl);
1398 /* Invalidate the RX mbuf and unload its map */
1400 bus_dmamap_sync(sc->re_ldata.re_mtag,
1401 sc->re_ldata.re_rx_dmamap[i],
1402 BUS_DMASYNC_POSTWRITE);
1403 bus_dmamap_unload(sc->re_ldata.re_mtag,
1404 sc->re_ldata.re_rx_dmamap[i]);
1406 if ((rxstat & RE_RDESC_STAT_EOF) == 0) {
1407 m->m_len = MCLBYTES - ETHER_ALIGN;
1408 if (sc->re_head == NULL) {
1409 sc->re_head = sc->re_tail = m;
1411 sc->re_tail->m_next = m;
1414 re_newbuf(sc, i, NULL);
1419 * NOTE: for the 8139C+, the frame length field
1420 * is always 12 bits in size, but for the gigE chips,
1421 * it is 13 bits (since the max RX frame length is 16K).
1422 * Unfortunately, all 32 bits in the status word
1423 * were already used, so to make room for the extra
1424 * length bit, RealTek took out the 'frame alignment
1425 * error' bit and shifted the other status bits
1426 * over one slot. The OWN, EOR, FS and LS bits are
1427 * still in the same places. We have already extracted
1428 * the frame length and checked the OWN bit, so rather
1429 * than using an alternate bit mapping, we shift the
1430 * status bits one space to the right so we can evaluate
1431 * them using the 8169 status as though it was in the
1432 * same format as that of the 8139C+.
1434 if (sc->re_type == RE_8169)
1437 if (rxstat & RE_RDESC_STAT_RXERRSUM) {
1440 * If this is part of a multi-fragment packet,
1441 * discard all the pieces.
1443 if (sc->re_head != NULL) {
1444 m_freem(sc->re_head);
1445 sc->re_head = sc->re_tail = NULL;
1447 re_newbuf(sc, i, m);
1452 * If allocating a replacement mbuf fails,
1453 * reload the current one.
1456 if (re_newbuf(sc, i, NULL)) {
1458 if (sc->re_head != NULL) {
1459 m_freem(sc->re_head);
1460 sc->re_head = sc->re_tail = NULL;
1462 re_newbuf(sc, i, m);
1466 if (sc->re_head != NULL) {
1467 m->m_len = total_len % (MCLBYTES - ETHER_ALIGN);
1469 * Special case: if there's 4 bytes or less
1470 * in this buffer, the mbuf can be discarded:
1471 * the last 4 bytes is the CRC, which we don't
1472 * care about anyway.
1474 if (m->m_len <= ETHER_CRC_LEN) {
1475 sc->re_tail->m_len -=
1476 (ETHER_CRC_LEN - m->m_len);
1479 m->m_len -= ETHER_CRC_LEN;
1480 sc->re_tail->m_next = m;
1483 sc->re_head = sc->re_tail = NULL;
1484 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
1486 m->m_pkthdr.len = m->m_len =
1487 (total_len - ETHER_CRC_LEN);
1490 m->m_pkthdr.rcvif = ifp;
1492 /* Do RX checksumming if enabled */
1494 if (ifp->if_capenable & IFCAP_RXCSUM) {
1496 /* Check IP header checksum */
1497 if (rxstat & RE_RDESC_STAT_PROTOID)
1498 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1499 if ((rxstat & RE_RDESC_STAT_IPSUMBAD) == 0)
1500 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1502 /* Check TCP/UDP checksum */
1503 if ((RE_TCPPKT(rxstat) &&
1504 (rxstat & RE_RDESC_STAT_TCPSUMBAD) == 0) ||
1505 (RE_UDPPKT(rxstat) &&
1506 (rxstat & RE_RDESC_STAT_UDPSUMBAD)) == 0) {
1507 m->m_pkthdr.csum_flags |=
1508 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1509 m->m_pkthdr.csum_data = 0xffff;
1513 if (rxvlan & RE_RDESC_VLANCTL_TAG) {
1515 be16toh((rxvlan & RE_RDESC_VLANCTL_DATA)));
1517 ifp->if_input(ifp, m);
1521 /* Flush the RX DMA ring */
1523 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1524 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_PREWRITE);
1526 sc->re_ldata.re_rx_prodidx = i;
1530 re_txeof(struct re_softc *sc)
1532 struct ifnet *ifp = &sc->arpcom.ac_if;
1536 /* Invalidate the TX descriptor list */
1538 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
1539 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_POSTREAD);
1541 for (idx = sc->re_ldata.re_tx_considx;
1542 idx != sc->re_ldata.re_tx_prodidx; RE_DESC_INC(idx)) {
1543 txstat = le32toh(sc->re_ldata.re_tx_list[idx].re_cmdstat);
1544 if (txstat & RE_TDESC_CMD_OWN)
1548 * We only stash mbufs in the last descriptor
1549 * in a fragment chain, which also happens to
1550 * be the only place where the TX status bits
1553 if (txstat & RE_TDESC_CMD_EOF) {
1554 m_freem(sc->re_ldata.re_tx_mbuf[idx]);
1555 sc->re_ldata.re_tx_mbuf[idx] = NULL;
1556 bus_dmamap_unload(sc->re_ldata.re_mtag,
1557 sc->re_ldata.re_tx_dmamap[idx]);
1558 if (txstat & (RE_TDESC_STAT_EXCESSCOL|
1559 RE_TDESC_STAT_COLCNT))
1560 ifp->if_collisions++;
1561 if (txstat & RE_TDESC_STAT_TXERRSUM)
1566 sc->re_ldata.re_tx_free++;
1569 /* No changes made to the TX ring, so no flush needed */
1570 if (idx != sc->re_ldata.re_tx_considx) {
1571 sc->re_ldata.re_tx_considx = idx;
1572 ifp->if_flags &= ~IFF_OACTIVE;
1577 * If not all descriptors have been released reaped yet,
1578 * reload the timer so that we will eventually get another
1579 * interrupt that will cause us to re-enter this routine.
1580 * This is done in case the transmitter has gone idle.
1582 if (sc->re_ldata.re_tx_free != RE_TX_DESC_CNT)
1583 CSR_WRITE_4(sc, RE_TIMERCNT, 1);
1589 struct re_softc *sc = xsc;
1591 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
1592 re_tick_serialized(xsc);
1593 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
1597 re_tick_serialized(void *xsc)
1599 struct re_softc *sc = xsc;
1600 struct mii_data *mii;
1602 mii = device_get_softc(sc->re_miibus);
1605 callout_reset(&sc->re_timer, hz, re_tick, sc);
1608 #ifdef DEVICE_POLLING
1611 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1613 struct re_softc *sc = ifp->if_softc;
1617 /* disable interrupts */
1618 CSR_WRITE_2(sc, RE_IMR, 0x0000);
1620 case POLL_DEREGISTER:
1621 /* enable interrupts */
1622 CSR_WRITE_2(sc, RE_IMR, RE_INTRS_CPLUS);
1625 sc->rxcycles = count;
1629 if (!ifq_is_empty(&ifp->if_snd))
1630 (*ifp->if_start)(ifp);
1632 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
1635 status = CSR_READ_2(sc, RE_ISR);
1636 if (status == 0xffff)
1639 CSR_WRITE_2(sc, RE_ISR, status);
1642 * XXX check behaviour on receiver stalls.
1645 if (status & RE_ISR_SYSTEM_ERR) {
1653 #endif /* DEVICE_POLLING */
1658 struct re_softc *sc = arg;
1659 struct ifnet *ifp = &sc->arpcom.ac_if;
1662 if (sc->suspended || (ifp->if_flags & IFF_UP) == 0)
1666 status = CSR_READ_2(sc, RE_ISR);
1667 /* If the card has gone away the read returns 0xffff. */
1668 if (status == 0xffff)
1671 CSR_WRITE_2(sc, RE_ISR, status);
1673 if ((status & RE_INTRS_CPLUS) == 0)
1676 if (status & RE_ISR_RX_OK)
1679 if (status & RE_ISR_RX_ERR)
1682 if ((status & RE_ISR_TIMEOUT_EXPIRED) ||
1683 (status & RE_ISR_TX_ERR) ||
1684 (status & RE_ISR_TX_DESC_UNAVAIL))
1687 if (status & RE_ISR_SYSTEM_ERR) {
1692 if (status & RE_ISR_LINKCHG)
1693 re_tick_serialized(sc);
1696 if (!ifq_is_empty(&ifp->if_snd))
1697 (*ifp->if_start)(ifp);
1701 re_encap(struct re_softc *sc, struct mbuf **m_head, int *idx, int *called_defrag)
1703 struct ifnet *ifp = &sc->arpcom.ac_if;
1704 struct mbuf *m, *m_new = NULL;
1705 struct re_dmaload_arg arg;
1710 if (sc->re_ldata.re_tx_free <= 4)
1716 * Set up checksum offload. Note: checksum offload bits must
1717 * appear in all descriptors of a multi-descriptor transmit
1718 * attempt. (This is according to testing done with an 8169
1719 * chip. I'm not sure if this is a requirement or a bug.)
1724 if (m->m_pkthdr.csum_flags & CSUM_IP)
1725 arg.re_flags |= RE_TDESC_CMD_IPCSUM;
1726 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1727 arg.re_flags |= RE_TDESC_CMD_TCPCSUM;
1728 if (m->m_pkthdr.csum_flags & CSUM_UDP)
1729 arg.re_flags |= RE_TDESC_CMD_UDPCSUM;
1733 arg.re_maxsegs = sc->re_ldata.re_tx_free;
1734 if (arg.re_maxsegs > 4)
1735 arg.re_maxsegs -= 4;
1736 arg.re_ring = sc->re_ldata.re_tx_list;
1738 map = sc->re_ldata.re_tx_dmamap[*idx];
1739 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map,
1740 m, re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
1742 if (error && error != EFBIG) {
1743 if_printf(ifp, "can't map mbuf (error %d)\n", error);
1747 /* Too many segments to map, coalesce into a single mbuf */
1749 if (error || arg.re_maxsegs == 0) {
1750 m_new = m_defrag_nofree(m, MB_DONTWAIT);
1761 arg.re_maxsegs = sc->re_ldata.re_tx_free;
1762 arg.re_ring = sc->re_ldata.re_tx_list;
1764 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map,
1765 m, re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
1768 if_printf(ifp, "can't map mbuf (error %d)\n", error);
1774 * Insure that the map for this transmission
1775 * is placed at the array index of the last descriptor
1778 sc->re_ldata.re_tx_dmamap[*idx] =
1779 sc->re_ldata.re_tx_dmamap[arg.re_idx];
1780 sc->re_ldata.re_tx_dmamap[arg.re_idx] = map;
1782 sc->re_ldata.re_tx_mbuf[arg.re_idx] = m;
1783 sc->re_ldata.re_tx_free -= arg.re_maxsegs;
1786 * Set up hardware VLAN tagging. Note: vlan tag info must
1787 * appear in the first descriptor of a multi-descriptor
1788 * transmission attempt.
1791 if ((m->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
1792 m->m_pkthdr.rcvif != NULL &&
1793 m->m_pkthdr.rcvif->if_type == IFT_L2VLAN) {
1795 ifv = m->m_pkthdr.rcvif->if_softc;
1797 sc->re_ldata.re_tx_list[*idx].re_vlanctl =
1798 htole32(htobe16(ifv->ifv_tag) | RE_TDESC_VLANCTL_TAG);
1801 /* Transfer ownership of packet to the chip. */
1803 sc->re_ldata.re_tx_list[arg.re_idx].re_cmdstat |=
1804 htole32(RE_TDESC_CMD_OWN);
1805 if (*idx != arg.re_idx)
1806 sc->re_ldata.re_tx_list[*idx].re_cmdstat |=
1807 htole32(RE_TDESC_CMD_OWN);
1809 RE_DESC_INC(arg.re_idx);
1816 * Main transmit routine for C+ and gigE NICs.
1820 re_start(struct ifnet *ifp)
1822 struct re_softc *sc = ifp->if_softc;
1823 struct mbuf *m_head;
1824 struct mbuf *m_head2;
1825 int called_defrag, idx, need_trans;
1827 idx = sc->re_ldata.re_tx_prodidx;
1830 while (sc->re_ldata.re_tx_mbuf[idx] == NULL) {
1831 m_head = ifq_poll(&ifp->if_snd);
1835 if (re_encap(sc, &m_head2, &idx, &called_defrag)) {
1837 * If we could not encapsulate the defragged packet,
1838 * the returned m_head2 is garbage and we must dequeue
1839 * and throw away the original packet.
1841 if (called_defrag) {
1842 ifq_dequeue(&ifp->if_snd, m_head);
1845 ifp->if_flags |= IFF_OACTIVE;
1850 * Clean out the packet we encapsulated. If we defragged
1851 * the packet the m_head2 is the one that got encapsulated
1852 * and the original must be thrown away. Otherwise m_head2
1853 * *IS* the original.
1855 ifq_dequeue(&ifp->if_snd, m_head);
1861 * If there's a BPF listener, bounce a copy of this frame
1864 BPF_MTAP(ifp, m_head2);
1871 /* Flush the TX descriptors */
1872 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
1873 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_PREWRITE);
1875 sc->re_ldata.re_tx_prodidx = idx;
1878 * RealTek put the TX poll request register in a different
1879 * location on the 8169 gigE chip. I don't know why.
1881 if (sc->re_type == RE_8169)
1882 CSR_WRITE_2(sc, RE_GTXSTART, RE_TXSTART_START);
1884 CSR_WRITE_2(sc, RE_TXSTART, RE_TXSTART_START);
1887 * Use the countdown timer for interrupt moderation.
1888 * 'TX done' interrupts are disabled. Instead, we reset the
1889 * countdown timer, which will begin counting until it hits
1890 * the value in the TIMERINT register, and then trigger an
1891 * interrupt. Each time we write to the TIMERCNT register,
1892 * the timer count is reset to 0.
1894 CSR_WRITE_4(sc, RE_TIMERCNT, 1);
1897 * Set a timeout in case the chip goes out to lunch.
1905 struct re_softc *sc = xsc;
1906 struct ifnet *ifp = &sc->arpcom.ac_if;
1907 struct mii_data *mii;
1910 mii = device_get_softc(sc->re_miibus);
1913 * Cancel pending I/O and free all RX/TX buffers.
1918 * Enable C+ RX and TX mode, as well as VLAN stripping and
1919 * RX checksum offload. We must configure the C+ register
1920 * before all others.
1922 CSR_WRITE_2(sc, RE_CPLUS_CMD, RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB |
1923 RE_CPLUSCMD_PCI_MRW | RE_CPLUSCMD_VLANSTRIP |
1924 (ifp->if_capenable & IFCAP_RXCSUM ?
1925 RE_CPLUSCMD_RXCSUM_ENB : 0));
1928 * Init our MAC address. Even though the chipset
1929 * documentation doesn't mention it, we need to enter "Config
1930 * register write enable" mode to modify the ID registers.
1932 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_WRITECFG);
1933 CSR_WRITE_STREAM_4(sc, RE_IDR0,
1934 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1935 CSR_WRITE_STREAM_4(sc, RE_IDR4,
1936 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1937 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF);
1940 * For C+ mode, initialize the RX descriptors and mbufs.
1942 re_rx_list_init(sc);
1943 re_tx_list_init(sc);
1946 * Enable transmit and receive.
1948 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB);
1951 * Set the initial TX and RX configuration.
1953 if (sc->re_testmode) {
1954 if (sc->re_type == RE_8169)
1955 CSR_WRITE_4(sc, RE_TXCFG,
1956 RE_TXCFG_CONFIG | RE_LOOPTEST_ON);
1958 CSR_WRITE_4(sc, RE_TXCFG,
1959 RE_TXCFG_CONFIG | RE_LOOPTEST_ON_CPLUS);
1961 CSR_WRITE_4(sc, RE_TXCFG, RE_TXCFG_CONFIG);
1962 CSR_WRITE_4(sc, RE_RXCFG, RE_RXCFG_CONFIG);
1964 /* Set the individual bit to receive frames for this host only. */
1965 rxcfg = CSR_READ_4(sc, RE_RXCFG);
1966 rxcfg |= RE_RXCFG_RX_INDIV;
1968 /* If we want promiscuous mode, set the allframes bit. */
1969 if (ifp->if_flags & IFF_PROMISC) {
1970 rxcfg |= RE_RXCFG_RX_ALLPHYS;
1971 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
1973 rxcfg &= ~RE_RXCFG_RX_ALLPHYS;
1974 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
1978 * Set capture broadcast bit to capture broadcast frames.
1980 if (ifp->if_flags & IFF_BROADCAST) {
1981 rxcfg |= RE_RXCFG_RX_BROAD;
1982 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
1984 rxcfg &= ~RE_RXCFG_RX_BROAD;
1985 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
1989 * Program the multicast filter, if necessary.
1993 #ifdef DEVICE_POLLING
1995 * Disable interrupts if we are polling.
1997 if (ifp->if_flags & IFF_POLLING)
1998 CSR_WRITE_2(sc, RE_IMR, 0);
1999 else /* otherwise ... */
2000 #endif /* DEVICE_POLLING */
2002 * Enable interrupts.
2004 if (sc->re_testmode)
2005 CSR_WRITE_2(sc, RE_IMR, 0);
2007 CSR_WRITE_2(sc, RE_IMR, RE_INTRS_CPLUS);
2009 /* Set initial TX threshold */
2010 sc->re_txthresh = RE_TX_THRESH_INIT;
2012 /* Start RX/TX process. */
2013 CSR_WRITE_4(sc, RE_MISSEDPKT, 0);
2015 /* Enable receiver and transmitter. */
2016 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB);
2019 * Load the addresses of the RX and TX lists into the chip.
2022 CSR_WRITE_4(sc, RE_RXLIST_ADDR_HI,
2023 RE_ADDR_HI(sc->re_ldata.re_rx_list_addr));
2024 CSR_WRITE_4(sc, RE_RXLIST_ADDR_LO,
2025 RE_ADDR_LO(sc->re_ldata.re_rx_list_addr));
2027 CSR_WRITE_4(sc, RE_TXLIST_ADDR_HI,
2028 RE_ADDR_HI(sc->re_ldata.re_tx_list_addr));
2029 CSR_WRITE_4(sc, RE_TXLIST_ADDR_LO,
2030 RE_ADDR_LO(sc->re_ldata.re_tx_list_addr));
2032 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, 16);
2035 * Initialize the timer interrupt register so that
2036 * a timer interrupt will be generated once the timer
2037 * reaches a certain number of ticks. The timer is
2038 * reloaded on each transmit. This gives us TX interrupt
2039 * moderation, which dramatically improves TX frame rate.
2042 if (sc->re_type == RE_8169)
2043 CSR_WRITE_4(sc, RE_TIMERINT_8169, 0x800);
2045 CSR_WRITE_4(sc, RE_TIMERINT, 0x400);
2048 * For 8169 gigE NICs, set the max allowed RX packet
2049 * size so we can receive jumbo frames.
2051 if (sc->re_type == RE_8169)
2052 CSR_WRITE_2(sc, RE_MAXRXPKTLEN, 16383);
2054 if (sc->re_testmode) {
2060 CSR_WRITE_1(sc, RE_CFG1, RE_CFG1_DRVLOAD|RE_CFG1_FULLDUPLEX);
2062 ifp->if_flags |= IFF_RUNNING;
2063 ifp->if_flags &= ~IFF_OACTIVE;
2065 callout_reset(&sc->re_timer, hz, re_tick, sc);
2069 * Set media options.
2072 re_ifmedia_upd(struct ifnet *ifp)
2074 struct re_softc *sc = ifp->if_softc;
2075 struct mii_data *mii;
2077 mii = device_get_softc(sc->re_miibus);
2084 * Report current media status.
2087 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2089 struct re_softc *sc = ifp->if_softc;
2090 struct mii_data *mii;
2092 mii = device_get_softc(sc->re_miibus);
2095 ifmr->ifm_active = mii->mii_media_active;
2096 ifmr->ifm_status = mii->mii_media_status;
2100 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2102 struct re_softc *sc = ifp->if_softc;
2103 struct ifreq *ifr = (struct ifreq *) data;
2104 struct mii_data *mii;
2109 if (ifr->ifr_mtu > RE_JUMBO_MTU)
2111 ifp->if_mtu = ifr->ifr_mtu;
2114 if (ifp->if_flags & IFF_UP)
2116 else if (ifp->if_flags & IFF_RUNNING)
2127 mii = device_get_softc(sc->re_miibus);
2128 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2131 ifp->if_capenable &= ~(IFCAP_HWCSUM);
2132 ifp->if_capenable |=
2133 ifr->ifr_reqcap & (IFCAP_HWCSUM);
2134 if (ifp->if_capenable & IFCAP_TXCSUM)
2135 ifp->if_hwassist = RE_CSUM_FEATURES;
2137 ifp->if_hwassist = 0;
2138 if (ifp->if_flags & IFF_RUNNING)
2142 error = ether_ioctl(ifp, command, data);
2149 re_watchdog(struct ifnet *ifp)
2151 struct re_softc *sc = ifp->if_softc;
2153 if_printf(ifp, "watchdog timeout\n");
2162 if (!ifq_is_empty(&ifp->if_snd))
2167 * Stop the adapter and free any mbufs allocated to the
2171 re_stop(struct re_softc *sc)
2173 struct ifnet *ifp = &sc->arpcom.ac_if;
2177 callout_stop(&sc->re_timer);
2179 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2181 CSR_WRITE_1(sc, RE_COMMAND, 0x00);
2182 CSR_WRITE_2(sc, RE_IMR, 0x0000);
2184 if (sc->re_head != NULL) {
2185 m_freem(sc->re_head);
2186 sc->re_head = sc->re_tail = NULL;
2189 /* Free the TX list buffers. */
2190 for (i = 0; i < RE_TX_DESC_CNT; i++) {
2191 if (sc->re_ldata.re_tx_mbuf[i] != NULL) {
2192 bus_dmamap_unload(sc->re_ldata.re_mtag,
2193 sc->re_ldata.re_tx_dmamap[i]);
2194 m_freem(sc->re_ldata.re_tx_mbuf[i]);
2195 sc->re_ldata.re_tx_mbuf[i] = NULL;
2199 /* Free the RX list buffers. */
2200 for (i = 0; i < RE_RX_DESC_CNT; i++) {
2201 if (sc->re_ldata.re_rx_mbuf[i] != NULL) {
2202 bus_dmamap_unload(sc->re_ldata.re_mtag,
2203 sc->re_ldata.re_rx_dmamap[i]);
2204 m_freem(sc->re_ldata.re_rx_mbuf[i]);
2205 sc->re_ldata.re_rx_mbuf[i] = NULL;
2211 * Device suspend routine. Stop the interface and save some PCI
2212 * settings in case the BIOS doesn't restore them properly on
2216 re_suspend(device_t dev)
2218 #ifndef BURN_BRIDGES
2221 struct re_softc *sc = device_get_softc(dev);
2225 #ifndef BURN_BRIDGES
2226 for (i = 0; i < 5; i++)
2227 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
2228 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
2229 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
2230 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
2231 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
2240 * Device resume routine. Restore some PCI settings in case the BIOS
2241 * doesn't, re-enable busmastering, and restart the interface if
2245 re_resume(device_t dev)
2247 struct re_softc *sc = device_get_softc(dev);
2248 struct ifnet *ifp = &sc->arpcom.ac_if;
2249 #ifndef BURN_BRIDGES
2253 #ifndef BURN_BRIDGES
2254 /* better way to do this? */
2255 for (i = 0; i < 5; i++)
2256 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
2257 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
2258 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
2259 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
2260 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
2262 /* reenable busmastering */
2263 pci_enable_busmaster(dev);
2264 pci_enable_io(dev, SYS_RES_IOPORT);
2267 /* reinitialize interface if necessary */
2268 if (ifp->if_flags & IFF_UP)
2277 * Stop all chip I/O so that the kernel's probe routines don't
2278 * get confused by errant DMAs when rebooting.
2281 re_shutdown(device_t dev)
2283 struct re_softc *sc = device_get_softc(dev);