2 * Copyright (c) 2002 Myson Technology Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions, and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. The name of the author may not be used to endorse or promote products
12 * derived from this software without specific prior written permission.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
18 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * Written by: yen_cw@myson.com.tw available at: http://www.myson.com.tw/
28 * $FreeBSD: src/sys/dev/my/if_my.c,v 1.2.2.4 2002/04/17 02:05:27 julian Exp $
29 * $DragonFly: src/sys/dev/netif/my/if_my.c,v 1.17 2005/05/24 09:52:13 joerg Exp $
31 * Myson fast ethernet PCI NIC driver
33 * $Id: if_my.c,v 1.40 2001/11/30 03:55:00 <yen_cw@myson.com.tw> wpaul Exp $
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/sockio.h>
39 #include <sys/malloc.h>
40 #include <sys/kernel.h>
41 #include <sys/socket.h>
42 #include <sys/queue.h>
43 #include <sys/types.h>
45 #include <sys/module.h>
50 #include <net/ifq_var.h>
51 #include <net/if_arp.h>
52 #include <net/ethernet.h>
53 #include <net/if_media.h>
54 #include <net/if_dl.h>
57 #include <vm/vm.h> /* for vtophys */
58 #include <vm/pmap.h> /* for vtophys */
59 #include <machine/clock.h> /* for DELAY */
60 #include <machine/bus_memio.h>
61 #include <machine/bus_pio.h>
62 #include <machine/bus.h>
63 #include <machine/resource.h>
67 #include <bus/pci/pcireg.h>
68 #include <bus/pci/pcivar.h>
70 #include "../mii_layer/mii.h"
71 #include "../mii_layer/miivar.h"
73 #include "miibus_if.h"
76 * #define MY_USEIOSPACE
79 static int MY_USEIOSPACE = 1;
82 #define MY_RES SYS_RES_IOPORT
83 #define MY_RID MY_PCI_LOIO
85 #define MY_RES SYS_RES_MEMORY
86 #define MY_RID MY_PCI_LOMEM
93 * Various supported device vendors/types and their names.
95 struct my_type *my_info_tmp;
96 static struct my_type my_devs[] = {
97 {MYSONVENDORID, MTD800ID, "Myson MTD80X Based Fast Ethernet Card"},
98 {MYSONVENDORID, MTD803ID, "Myson MTD80X Based Fast Ethernet Card"},
99 {MYSONVENDORID, MTD891ID, "Myson MTD89X Based Giga Ethernet Card"},
104 * Various supported PHY vendors/types and their names. Note that this driver
105 * will work with pretty much any MII-compliant PHY, so failure to positively
106 * identify the chip is not a fatal error.
108 static struct my_type my_phys[] = {
109 {MysonPHYID0, MysonPHYID0, "<MYSON MTD981>"},
110 {SeeqPHYID0, SeeqPHYID0, "<SEEQ 80225>"},
111 {AhdocPHYID0, AhdocPHYID0, "<AHDOC 101>"},
112 {MarvellPHYID0, MarvellPHYID0, "<MARVELL 88E1000>"},
113 {LevelOnePHYID0, LevelOnePHYID0, "<LevelOne LXT1000>"},
114 {0, 0, "<MII-compliant physical interface>"}
117 static int my_probe(device_t);
118 static int my_attach(device_t);
119 static int my_detach(device_t);
120 static int my_newbuf(struct my_softc *, struct my_chain_onefrag *);
121 static int my_encap(struct my_softc *, struct my_chain *, struct mbuf *);
122 static void my_rxeof(struct my_softc *);
123 static void my_txeof(struct my_softc *);
124 static void my_txeoc(struct my_softc *);
125 static void my_intr(void *);
126 static void my_start(struct ifnet *);
127 static int my_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
128 static void my_init(void *);
129 static void my_stop(struct my_softc *);
130 static void my_watchdog(struct ifnet *);
131 static void my_shutdown(device_t);
132 static int my_ifmedia_upd(struct ifnet *);
133 static void my_ifmedia_sts(struct ifnet *, struct ifmediareq *);
134 static u_int16_t my_phy_readreg(struct my_softc *, int);
135 static void my_phy_writereg(struct my_softc *, int, int);
136 static void my_autoneg_xmit(struct my_softc *);
137 static void my_autoneg_mii(struct my_softc *, int, int);
138 static void my_setmode_mii(struct my_softc *, int);
139 static void my_getmode_mii(struct my_softc *);
140 static void my_setcfg(struct my_softc *, int);
141 static u_int8_t my_calchash(caddr_t);
142 static void my_setmulti(struct my_softc *);
143 static void my_reset(struct my_softc *);
144 static int my_list_rx_init(struct my_softc *);
145 static int my_list_tx_init(struct my_softc *);
146 static long my_send_cmd_to_phy(struct my_softc *, int, int);
148 #define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
149 #define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
151 static device_method_t my_methods[] = {
152 /* Device interface */
153 DEVMETHOD(device_probe, my_probe),
154 DEVMETHOD(device_attach, my_attach),
155 DEVMETHOD(device_detach, my_detach),
156 DEVMETHOD(device_shutdown, my_shutdown),
161 static driver_t my_driver = {
164 sizeof(struct my_softc)
167 static devclass_t my_devclass;
169 DECLARE_DUMMY_MODULE(if_my);
170 DRIVER_MODULE(if_my, pci, my_driver, my_devclass, 0, 0);
173 my_send_cmd_to_phy(struct my_softc * sc, int opcode, int regad)
181 /* enable MII output */
182 miir = CSR_READ_4(sc, MY_MANAGEMENT);
185 miir |= MY_MASK_MIIR_MII_WRITE + MY_MASK_MIIR_MII_MDO;
187 /* send 32 1's preamble */
188 for (i = 0; i < 32; i++) {
189 /* low MDC; MDO is already high (miir) */
190 miir &= ~MY_MASK_MIIR_MII_MDC;
191 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
194 miir |= MY_MASK_MIIR_MII_MDC;
195 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
198 /* calculate ST+OP+PHYAD+REGAD+TA */
199 data = opcode | (sc->my_phy_addr << 7) | (regad << 2);
204 /* low MDC, prepare MDO */
205 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO);
207 miir |= MY_MASK_MIIR_MII_MDO;
209 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
211 miir |= MY_MASK_MIIR_MII_MDC;
212 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
217 if (mask == 0x2 && opcode == MY_OP_READ)
218 miir &= ~MY_MASK_MIIR_MII_WRITE;
227 my_phy_readreg(struct my_softc * sc, int reg)
234 if (sc->my_info->my_did == MTD803ID)
235 data = CSR_READ_2(sc, MY_PHYBASE + reg * 2);
237 miir = my_send_cmd_to_phy(sc, MY_OP_READ, reg);
244 miir &= ~MY_MASK_MIIR_MII_MDC;
245 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
248 miir = CSR_READ_4(sc, MY_MANAGEMENT);
249 if (miir & MY_MASK_MIIR_MII_MDI)
252 /* high MDC, and wait */
253 miir |= MY_MASK_MIIR_MII_MDC;
254 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
262 miir &= ~MY_MASK_MIIR_MII_MDC;
263 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
267 return (u_int16_t) data;
272 my_phy_writereg(struct my_softc * sc, int reg, int data)
279 if (sc->my_info->my_did == MTD803ID)
280 CSR_WRITE_2(sc, MY_PHYBASE + reg * 2, data);
282 miir = my_send_cmd_to_phy(sc, MY_OP_WRITE, reg);
287 /* low MDC, prepare MDO */
288 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO);
290 miir |= MY_MASK_MIIR_MII_MDO;
291 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
295 miir |= MY_MASK_MIIR_MII_MDC;
296 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
304 miir &= ~MY_MASK_MIIR_MII_MDC;
305 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
312 my_calchash(caddr_t addr)
314 u_int32_t crc, carry;
318 /* Compute CRC for the address value. */
319 crc = 0xFFFFFFFF; /* initial value */
321 for (i = 0; i < 6; i++) {
323 for (j = 0; j < 8; j++) {
324 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
328 crc = (crc ^ 0x04c11db6) | carry;
333 * return the filter bit position Note: I arrived at the following
334 * nonsense through experimentation. It's not the usual way to
335 * generate the bit position but it's the only thing I could come up
338 return (~(crc >> 26) & 0x0000003F);
343 * Program the 64-bit multicast hash filter.
346 my_setmulti(struct my_softc * sc)
350 u_int32_t hashes[2] = {0, 0};
351 struct ifmultiaddr *ifma;
357 ifp = &sc->arpcom.ac_if;
359 rxfilt = CSR_READ_4(sc, MY_TCRRCR);
361 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
363 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt);
364 CSR_WRITE_4(sc, MY_MAR0, 0xFFFFFFFF);
365 CSR_WRITE_4(sc, MY_MAR1, 0xFFFFFFFF);
371 /* first, zot all the existing hash bits */
372 CSR_WRITE_4(sc, MY_MAR0, 0);
373 CSR_WRITE_4(sc, MY_MAR1, 0);
375 /* now program new ones */
376 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
377 if (ifma->ifma_addr->sa_family != AF_LINK)
379 h = my_calchash(LLADDR((struct sockaddr_dl *) ifma->ifma_addr));
381 hashes[0] |= (1 << h);
383 hashes[1] |= (1 << (h - 32));
391 CSR_WRITE_4(sc, MY_MAR0, hashes[0]);
392 CSR_WRITE_4(sc, MY_MAR1, hashes[1]);
393 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt);
399 * Initiate an autonegotiation session.
402 my_autoneg_xmit(struct my_softc * sc)
404 u_int16_t phy_sts = 0;
408 my_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
410 while (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET);
412 phy_sts = my_phy_readreg(sc, PHY_BMCR);
413 phy_sts |= PHY_BMCR_AUTONEGENBL | PHY_BMCR_AUTONEGRSTR;
414 my_phy_writereg(sc, PHY_BMCR, phy_sts);
422 * Invoke autonegotiation on a PHY.
425 my_autoneg_mii(struct my_softc * sc, int flag, int verbose)
427 u_int16_t phy_sts = 0, media, advert, ability;
428 u_int16_t ability2 = 0;
435 ifp = &sc->arpcom.ac_if;
437 ifm->ifm_media = IFM_ETHER | IFM_AUTO;
439 #ifndef FORCE_AUTONEG_TFOUR
441 * First, see if autoneg is supported. If not, there's no point in
444 phy_sts = my_phy_readreg(sc, PHY_BMSR);
445 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) {
447 printf("my%d: autonegotiation not supported\n",
449 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
455 case MY_FLAG_FORCEDELAY:
457 * XXX Never use this option anywhere but in the probe
458 * routine: making the kernel stop dead in its tracks for
459 * three whole seconds after we've gone multi-user is really
465 case MY_FLAG_SCHEDDELAY:
467 * Wait for the transmitter to go idle before starting an
468 * autoneg session, otherwise my_start() may clobber our
469 * timeout, and we don't want to allow transmission during an
470 * autoneg session since that can screw it up.
472 if (sc->my_cdata.my_tx_head != NULL) {
473 sc->my_want_auto = 1;
480 sc->my_want_auto = 0;
483 case MY_FLAG_DELAYTIMEO:
488 printf("my%d: invalid autoneg flag: %d\n", sc->my_unit, flag);
493 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) {
495 printf("my%d: autoneg complete, ", sc->my_unit);
496 phy_sts = my_phy_readreg(sc, PHY_BMSR);
499 printf("my%d: autoneg not complete, ", sc->my_unit);
502 media = my_phy_readreg(sc, PHY_BMCR);
504 /* Link is good. Report modes and set duplex mode. */
505 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) {
507 printf("my%d: link status good. ", sc->my_unit);
508 advert = my_phy_readreg(sc, PHY_ANAR);
509 ability = my_phy_readreg(sc, PHY_LPAR);
510 if ((sc->my_pinfo->my_vid == MarvellPHYID0) ||
511 (sc->my_pinfo->my_vid == LevelOnePHYID0)) {
512 ability2 = my_phy_readreg(sc, PHY_1000SR);
513 if (ability2 & PHY_1000SR_1000BTXFULL) {
517 * this version did not support 1000M,
519 * IFM_ETHER | IFM_1000_T | IFM_FDX;
522 IFM_ETHER | IFM_100_TX | IFM_FDX;
523 media &= ~PHY_BMCR_SPEEDSEL;
524 media |= PHY_BMCR_1000;
525 media |= PHY_BMCR_DUPLEX;
526 printf("(full-duplex, 1000Mbps)\n");
527 } else if (ability2 & PHY_1000SR_1000BTXHALF) {
531 * this version did not support 1000M,
532 * ifm->ifm_media = IFM_ETHER | IFM_1000_T;
534 ifm->ifm_media = IFM_ETHER | IFM_100_TX;
535 media &= ~PHY_BMCR_SPEEDSEL;
536 media &= ~PHY_BMCR_DUPLEX;
537 media |= PHY_BMCR_1000;
538 printf("(half-duplex, 1000Mbps)\n");
541 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) {
542 ifm->ifm_media = IFM_ETHER | IFM_100_T4;
543 media |= PHY_BMCR_SPEEDSEL;
544 media &= ~PHY_BMCR_DUPLEX;
545 printf("(100baseT4)\n");
546 } else if (advert & PHY_ANAR_100BTXFULL &&
547 ability & PHY_ANAR_100BTXFULL) {
548 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX;
549 media |= PHY_BMCR_SPEEDSEL;
550 media |= PHY_BMCR_DUPLEX;
551 printf("(full-duplex, 100Mbps)\n");
552 } else if (advert & PHY_ANAR_100BTXHALF &&
553 ability & PHY_ANAR_100BTXHALF) {
554 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX;
555 media |= PHY_BMCR_SPEEDSEL;
556 media &= ~PHY_BMCR_DUPLEX;
557 printf("(half-duplex, 100Mbps)\n");
558 } else if (advert & PHY_ANAR_10BTFULL &&
559 ability & PHY_ANAR_10BTFULL) {
560 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX;
561 media &= ~PHY_BMCR_SPEEDSEL;
562 media |= PHY_BMCR_DUPLEX;
563 printf("(full-duplex, 10Mbps)\n");
565 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
566 media &= ~PHY_BMCR_SPEEDSEL;
567 media &= ~PHY_BMCR_DUPLEX;
568 printf("(half-duplex, 10Mbps)\n");
570 media &= ~PHY_BMCR_AUTONEGENBL;
572 /* Set ASIC's duplex mode to match the PHY. */
573 my_phy_writereg(sc, PHY_BMCR, media);
574 my_setcfg(sc, media);
577 printf("my%d: no carrier\n", sc->my_unit);
581 if (sc->my_tx_pend) {
591 * To get PHY ability.
594 my_getmode_mii(struct my_softc * sc)
600 ifp = &sc->arpcom.ac_if;
601 bmsr = my_phy_readreg(sc, PHY_BMSR);
603 printf("my%d: PHY status word: %x\n", sc->my_unit, bmsr);
606 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
608 if (bmsr & PHY_BMSR_10BTHALF) {
610 printf("my%d: 10Mbps half-duplex mode supported\n",
612 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_HDX,
614 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T, 0, NULL);
616 if (bmsr & PHY_BMSR_10BTFULL) {
618 printf("my%d: 10Mbps full-duplex mode supported\n",
621 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX,
623 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX;
625 if (bmsr & PHY_BMSR_100BTXHALF) {
627 printf("my%d: 100Mbps half-duplex mode supported\n",
629 ifp->if_baudrate = 100000000;
630 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL);
631 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_HDX,
633 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX;
635 if (bmsr & PHY_BMSR_100BTXFULL) {
637 printf("my%d: 100Mbps full-duplex mode supported\n",
639 ifp->if_baudrate = 100000000;
640 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX,
642 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX;
644 /* Some also support 100BaseT4. */
645 if (bmsr & PHY_BMSR_100BT4) {
647 printf("my%d: 100baseT4 mode supported\n", sc->my_unit);
648 ifp->if_baudrate = 100000000;
649 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_T4, 0, NULL);
650 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_T4;
651 #ifdef FORCE_AUTONEG_TFOUR
653 printf("my%d: forcing on autoneg support for BT4\n",
655 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0 NULL):
656 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO;
659 #if 0 /* this version did not support 1000M, */
660 if (sc->my_pinfo->my_vid == MarvellPHYID0) {
662 printf("my%d: 1000Mbps half-duplex mode supported\n",
665 ifp->if_baudrate = 1000000000;
666 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL);
667 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_HDX,
670 printf("my%d: 1000Mbps full-duplex mode supported\n",
672 ifp->if_baudrate = 1000000000;
673 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX,
675 sc->ifmedia.ifm_media = IFM_ETHER | IFM_1000_T | IFM_FDX;
678 if (bmsr & PHY_BMSR_CANAUTONEG) {
680 printf("my%d: autoneg supported\n", sc->my_unit);
681 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
682 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO;
689 * Set speed and duplex mode.
692 my_setmode_mii(struct my_softc * sc, int media)
698 ifp = &sc->arpcom.ac_if;
700 * If an autoneg session is in progress, stop it.
702 if (sc->my_autoneg) {
703 printf("my%d: canceling autoneg session\n", sc->my_unit);
704 ifp->if_timer = sc->my_autoneg = sc->my_want_auto = 0;
705 bmcr = my_phy_readreg(sc, PHY_BMCR);
706 bmcr &= ~PHY_BMCR_AUTONEGENBL;
707 my_phy_writereg(sc, PHY_BMCR, bmcr);
709 printf("my%d: selecting MII, ", sc->my_unit);
710 bmcr = my_phy_readreg(sc, PHY_BMCR);
711 bmcr &= ~(PHY_BMCR_AUTONEGENBL | PHY_BMCR_SPEEDSEL | PHY_BMCR_1000 |
712 PHY_BMCR_DUPLEX | PHY_BMCR_LOOPBK);
714 #if 0 /* this version did not support 1000M, */
715 if (IFM_SUBTYPE(media) == IFM_1000_T) {
716 printf("1000Mbps/T4, half-duplex\n");
717 bmcr &= ~PHY_BMCR_SPEEDSEL;
718 bmcr &= ~PHY_BMCR_DUPLEX;
719 bmcr |= PHY_BMCR_1000;
722 if (IFM_SUBTYPE(media) == IFM_100_T4) {
723 printf("100Mbps/T4, half-duplex\n");
724 bmcr |= PHY_BMCR_SPEEDSEL;
725 bmcr &= ~PHY_BMCR_DUPLEX;
727 if (IFM_SUBTYPE(media) == IFM_100_TX) {
729 bmcr |= PHY_BMCR_SPEEDSEL;
731 if (IFM_SUBTYPE(media) == IFM_10_T) {
733 bmcr &= ~PHY_BMCR_SPEEDSEL;
735 if ((media & IFM_GMASK) == IFM_FDX) {
736 printf("full duplex\n");
737 bmcr |= PHY_BMCR_DUPLEX;
739 printf("half duplex\n");
740 bmcr &= ~PHY_BMCR_DUPLEX;
742 my_phy_writereg(sc, PHY_BMCR, bmcr);
749 * The Myson manual states that in order to fiddle with the 'full-duplex' and
750 * '100Mbps' bits in the netconfig register, we first have to put the
751 * transmit and/or receive logic in the idle state.
754 my_setcfg(struct my_softc * sc, int bmcr)
759 if (CSR_READ_4(sc, MY_TCRRCR) & (MY_TE | MY_RE)) {
761 MY_CLRBIT(sc, MY_TCRRCR, (MY_TE | MY_RE));
762 for (i = 0; i < MY_TIMEOUT; i++) {
764 if (!(CSR_READ_4(sc, MY_TCRRCR) &
765 (MY_TXRUN | MY_RXRUN)))
769 printf("my%d: failed to force tx and rx to idle \n",
772 MY_CLRBIT(sc, MY_TCRRCR, MY_PS1000);
773 MY_CLRBIT(sc, MY_TCRRCR, MY_PS10);
774 if (bmcr & PHY_BMCR_1000)
775 MY_SETBIT(sc, MY_TCRRCR, MY_PS1000);
776 else if (!(bmcr & PHY_BMCR_SPEEDSEL))
777 MY_SETBIT(sc, MY_TCRRCR, MY_PS10);
778 if (bmcr & PHY_BMCR_DUPLEX)
779 MY_SETBIT(sc, MY_TCRRCR, MY_FD);
781 MY_CLRBIT(sc, MY_TCRRCR, MY_FD);
783 MY_SETBIT(sc, MY_TCRRCR, MY_TE | MY_RE);
789 my_reset(struct my_softc * sc)
794 MY_SETBIT(sc, MY_BCR, MY_SWR);
795 for (i = 0; i < MY_TIMEOUT; i++) {
797 if (!(CSR_READ_4(sc, MY_BCR) & MY_SWR))
801 printf("m0x%d: reset never completed!\n", sc->my_unit);
803 /* Wait a little while for the chip to get its brains in order. */
810 * Probe for a Myson chip. Check the PCI vendor and device IDs against our
811 * list and return a device name if we find a match.
814 my_probe(device_t dev)
819 while (t->my_name != NULL) {
820 if ((pci_get_vendor(dev) == t->my_vid) &&
821 (pci_get_device(dev) == t->my_did)) {
822 device_set_desc(dev, t->my_name);
832 * Attach the interface. Allocate softc structures, do ifmedia setup and
833 * ethernet/BPF attach.
836 my_attach(device_t dev)
839 u_char eaddr[ETHER_ADDR_LEN];
840 u_int32_t command, iobase;
843 int media = IFM_ETHER | IFM_100_TX | IFM_FDX;
847 u_int16_t phy_vid, phy_did, phy_sts = 0;
848 int rid, unit, error = 0;
851 sc = device_get_softc(dev);
852 unit = device_get_unit(dev);
854 printf("my%d: no memory for softc struct!\n", unit);
859 bzero(sc, sizeof(struct my_softc));
860 /*mtx_init(&sc->my_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE);*/
864 * Map control/status registers.
867 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4);
868 command |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
869 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command & 0x000000ff, 4);
870 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4);
872 command = pci_read_config(dev, PCIR_COMMAND, 4);
873 command |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
874 pci_write_config(dev, PCIR_COMMAND, command & 0x000000ff, 4);
875 command = pci_read_config(dev, PCIR_COMMAND, 4);
877 if (my_info_tmp->my_did == MTD800ID) {
878 iobase = pci_read_config(dev, MY_PCI_LOIO, 4);
883 if (!(command & PCIM_CMD_PORTEN)) {
884 printf("my%d: failed to enable I/O ports!\n", unit);
890 if (!pci_map_port(config_id, MY_PCI_LOIO, (u_int16_t *) & (sc->my_bhandle))) {
891 printf("my%d: couldn't map ports\n", unit);
896 sc->my_btag = I386_BUS_SPACE_IO;
899 if (!(command & PCIM_CMD_MEMEN)) {
900 printf("my%d: failed to enable memory mapping!\n",
906 if (!pci_map_mem(config_id, MY_PCI_LOMEM, &vbase, &pbase)) {
907 printf ("my%d: couldn't map memory\n", unit);
911 sc->my_btag = I386_BUS_SPACE_MEM;
912 sc->my_bhandle = vbase;
917 sc->my_res = bus_alloc_resource_any(dev, MY_RES, &rid, RF_ACTIVE);
919 if (sc->my_res == NULL) {
920 printf("my%d: couldn't map ports/memory\n", unit);
924 sc->my_btag = rman_get_bustag(sc->my_res);
925 sc->my_bhandle = rman_get_bushandle(sc->my_res);
928 sc->my_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
929 RF_SHAREABLE | RF_ACTIVE);
931 if (sc->my_irq == NULL) {
932 printf("my%d: couldn't map interrupt\n", unit);
933 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res);
937 error = bus_setup_intr(dev, sc->my_irq, INTR_TYPE_NET,
938 my_intr, sc, &sc->my_intrhand);
941 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq);
942 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res);
943 printf("my%d: couldn't set up irq\n", unit);
946 callout_init(&sc->my_stat_ch);
948 sc->my_info = my_info_tmp;
950 /* Reset the adapter. */
954 * Get station address
956 for (i = 0; i < ETHER_ADDR_LEN; ++i)
957 eaddr[i] = CSR_READ_1(sc, MY_PAR0 + i);
961 sc->my_ldata_ptr = malloc(sizeof(struct my_list_data) + 8,
963 if (sc->my_ldata_ptr == NULL) {
965 printf("my%d: no memory for list buffers!\n", unit);
969 sc->my_ldata = (struct my_list_data *) sc->my_ldata_ptr;
970 round = (unsigned int)sc->my_ldata_ptr & 0xF;
971 roundptr = sc->my_ldata_ptr;
972 for (i = 0; i < 8; i++) {
979 sc->my_ldata = (struct my_list_data *) roundptr;
980 bzero(sc->my_ldata, sizeof(struct my_list_data));
982 ifp = &sc->arpcom.ac_if;
984 if_initname(ifp, "my", unit);
985 ifp->if_mtu = ETHERMTU;
986 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
987 ifp->if_ioctl = my_ioctl;
988 ifp->if_start = my_start;
989 ifp->if_watchdog = my_watchdog;
990 ifp->if_init = my_init;
991 ifp->if_baudrate = 10000000;
992 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN);
993 ifq_set_ready(&ifp->if_snd);
995 if (sc->my_info->my_did == MTD803ID)
996 sc->my_pinfo = my_phys;
999 printf("my%d: probing for a PHY\n", sc->my_unit);
1000 for (i = MY_PHYADDR_MIN; i < MY_PHYADDR_MAX + 1; i++) {
1002 printf("my%d: checking address: %d\n",
1004 sc->my_phy_addr = i;
1005 phy_sts = my_phy_readreg(sc, PHY_BMSR);
1006 if ((phy_sts != 0) && (phy_sts != 0xffff))
1012 phy_vid = my_phy_readreg(sc, PHY_VENID);
1013 phy_did = my_phy_readreg(sc, PHY_DEVID);
1015 printf("my%d: found PHY at address %d, ",
1016 sc->my_unit, sc->my_phy_addr);
1017 printf("vendor id: %x device id: %x\n",
1022 if (phy_vid == p->my_vid) {
1028 if (sc->my_pinfo == NULL)
1029 sc->my_pinfo = &my_phys[PHY_UNKNOWN];
1031 printf("my%d: PHY type: %s\n",
1032 sc->my_unit, sc->my_pinfo->my_name);
1034 printf("my%d: MII without any phy!\n", sc->my_unit);
1040 /* Do ifmedia setup. */
1041 ifmedia_init(&sc->ifmedia, 0, my_ifmedia_upd, my_ifmedia_sts);
1043 my_autoneg_mii(sc, MY_FLAG_FORCEDELAY, 1);
1044 media = sc->ifmedia.ifm_media;
1046 ifmedia_set(&sc->ifmedia, media);
1048 ether_ifattach(ifp, eaddr);
1051 at_shutdown(my_shutdown, sc, SHUTDOWN_POST_SYNC);
1052 shutdownhook_establish(my_shutdown, sc);
1060 /*mtx_destroy(&sc->my_mtx);*/
1066 my_detach(device_t dev)
1068 struct my_softc *sc;
1073 sc = device_get_softc(dev);
1075 ifp = &sc->arpcom.ac_if;
1076 ether_ifdetach(ifp);
1080 bus_generic_detach(dev);
1081 device_delete_child(dev, sc->rl_miibus);
1084 bus_teardown_intr(dev, sc->my_irq, sc->my_intrhand);
1085 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq);
1086 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res);
1088 contigfree(sc->my_cdata.my_rx_buf, MY_RXBUFLEN + 32, M_DEVBUF);
1093 /*mtx_destroy(&sc->my_mtx);*/
1099 * Initialize the transmit descriptors.
1102 my_list_tx_init(struct my_softc * sc)
1104 struct my_chain_data *cd;
1105 struct my_list_data *ld;
1111 for (i = 0; i < MY_TX_LIST_CNT; i++) {
1112 cd->my_tx_chain[i].my_ptr = &ld->my_tx_list[i];
1113 if (i == (MY_TX_LIST_CNT - 1))
1114 cd->my_tx_chain[i].my_nextdesc = &cd->my_tx_chain[0];
1116 cd->my_tx_chain[i].my_nextdesc =
1117 &cd->my_tx_chain[i + 1];
1119 cd->my_tx_free = &cd->my_tx_chain[0];
1120 cd->my_tx_tail = cd->my_tx_head = NULL;
1126 * Initialize the RX descriptors and allocate mbufs for them. Note that we
1127 * arrange the descriptors in a closed ring, so that the last descriptor
1128 * points back to the first.
1131 my_list_rx_init(struct my_softc * sc)
1133 struct my_chain_data *cd;
1134 struct my_list_data *ld;
1140 for (i = 0; i < MY_RX_LIST_CNT; i++) {
1141 cd->my_rx_chain[i].my_ptr =
1142 (struct my_desc *) & ld->my_rx_list[i];
1143 if (my_newbuf(sc, &cd->my_rx_chain[i]) == ENOBUFS)
1145 if (i == (MY_RX_LIST_CNT - 1)) {
1146 cd->my_rx_chain[i].my_nextdesc = &cd->my_rx_chain[0];
1147 ld->my_rx_list[i].my_next = vtophys(&ld->my_rx_list[0]);
1149 cd->my_rx_chain[i].my_nextdesc =
1150 &cd->my_rx_chain[i + 1];
1151 ld->my_rx_list[i].my_next =
1152 vtophys(&ld->my_rx_list[i + 1]);
1155 cd->my_rx_head = &cd->my_rx_chain[0];
1161 * Initialize an RX descriptor and attach an MBUF cluster.
1164 my_newbuf(struct my_softc * sc, struct my_chain_onefrag * c)
1166 struct mbuf *m_new = NULL;
1169 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
1170 if (m_new == NULL) {
1171 printf("my%d: no memory for rx list -- packet dropped!\n",
1175 MCLGET(m_new, MB_DONTWAIT);
1176 if (!(m_new->m_flags & M_EXT)) {
1177 printf("my%d: no memory for rx list -- packet dropped!\n",
1183 c->my_ptr->my_data = vtophys(mtod(m_new, caddr_t));
1184 c->my_ptr->my_ctl = (MCLBYTES - 1) << MY_RBSShift;
1185 c->my_ptr->my_status = MY_OWNByNIC;
1191 * A frame has been uploaded: pass the resulting mbuf chain up to the higher
1195 my_rxeof(struct my_softc * sc)
1199 struct my_chain_onefrag *cur_rx;
1204 ifp = &sc->arpcom.ac_if;
1205 while (!((rxstat = sc->my_cdata.my_rx_head->my_ptr->my_status)
1207 cur_rx = sc->my_cdata.my_rx_head;
1208 sc->my_cdata.my_rx_head = cur_rx->my_nextdesc;
1210 if (rxstat & MY_ES) { /* error summary: give up this rx pkt */
1212 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1215 /* No errors; receive the packet. */
1216 total_len = (rxstat & MY_FLNGMASK) >> MY_FLNGShift;
1217 total_len -= ETHER_CRC_LEN;
1219 if (total_len < MINCLSIZE) {
1220 m = m_devget(mtod(cur_rx->my_mbuf, char *),
1221 total_len, 0, ifp, NULL);
1222 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1228 m = cur_rx->my_mbuf;
1230 * Try to conjure up a new mbuf cluster. If that
1231 * fails, it means we have an out of memory condition
1232 * and should leave the buffer in place and continue.
1233 * This will result in a lost packet, but there's
1234 * little else we can do in this situation.
1236 if (my_newbuf(sc, cur_rx) == ENOBUFS) {
1238 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1241 m->m_pkthdr.rcvif = ifp;
1242 m->m_pkthdr.len = m->m_len = total_len;
1245 (*ifp->if_input)(ifp, m);
1253 * A frame was downloaded to the chip. It's safe for us to clean up the list
1257 my_txeof(struct my_softc * sc)
1259 struct my_chain *cur_tx;
1263 ifp = &sc->arpcom.ac_if;
1264 /* Clear the timeout timer. */
1266 if (sc->my_cdata.my_tx_head == NULL)
1269 * Go through our tx list and free mbufs for those frames that have
1272 while (sc->my_cdata.my_tx_head->my_mbuf != NULL) {
1275 cur_tx = sc->my_cdata.my_tx_head;
1276 txstat = MY_TXSTATUS(cur_tx);
1277 if ((txstat & MY_OWNByNIC) || txstat == MY_UNSENT)
1279 if (!(CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced)) {
1280 if (txstat & MY_TXERR) {
1282 if (txstat & MY_EC) /* excessive collision */
1283 ifp->if_collisions++;
1284 if (txstat & MY_LC) /* late collision */
1285 ifp->if_collisions++;
1287 ifp->if_collisions += (txstat & MY_NCRMASK) >>
1291 m_freem(cur_tx->my_mbuf);
1292 cur_tx->my_mbuf = NULL;
1293 if (sc->my_cdata.my_tx_head == sc->my_cdata.my_tx_tail) {
1294 sc->my_cdata.my_tx_head = NULL;
1295 sc->my_cdata.my_tx_tail = NULL;
1298 sc->my_cdata.my_tx_head = cur_tx->my_nextdesc;
1300 if (CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced) {
1301 ifp->if_collisions += (CSR_READ_4(sc, MY_TSR) & MY_NCRMask);
1308 * TX 'end of channel' interrupt handler.
1311 my_txeoc(struct my_softc * sc)
1316 ifp = &sc->arpcom.ac_if;
1318 if (sc->my_cdata.my_tx_head == NULL) {
1319 ifp->if_flags &= ~IFF_OACTIVE;
1320 sc->my_cdata.my_tx_tail = NULL;
1321 if (sc->my_want_auto)
1322 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1);
1324 if (MY_TXOWN(sc->my_cdata.my_tx_head) == MY_UNSENT) {
1325 MY_TXOWN(sc->my_cdata.my_tx_head) = MY_OWNByNIC;
1327 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF);
1337 struct my_softc *sc;
1343 ifp = &sc->arpcom.ac_if;
1344 if (!(ifp->if_flags & IFF_UP)) {
1348 /* Disable interrupts. */
1349 CSR_WRITE_4(sc, MY_IMR, 0x00000000);
1352 status = CSR_READ_4(sc, MY_ISR);
1355 CSR_WRITE_4(sc, MY_ISR, status);
1359 if (status & MY_RI) /* receive interrupt */
1362 if ((status & MY_RBU) || (status & MY_RxErr)) {
1363 /* rx buffer unavailable or rx error */
1371 if (status & MY_TI) /* tx interrupt */
1373 if (status & MY_ETI) /* tx early interrupt */
1375 if (status & MY_TBU) /* tx buffer unavailable */
1378 #if 0 /* 90/1/18 delete */
1379 if (status & MY_FBE) {
1387 /* Re-enable interrupts. */
1388 CSR_WRITE_4(sc, MY_IMR, MY_INTRS);
1389 if (!ifq_is_empty(&ifp->if_snd))
1396 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1397 * pointers to the fragment pointers.
1400 my_encap(struct my_softc * sc, struct my_chain * c, struct mbuf * m_head)
1402 struct my_desc *f = NULL;
1404 struct mbuf *m, *m_new = NULL;
1407 /* calculate the total tx pkt length */
1409 for (m = m_head; m != NULL; m = m->m_next)
1410 total_len += m->m_len;
1412 * Start packing the mbufs in this chain into the fragment pointers.
1413 * Stop when we run out of fragments or hit the end of the mbuf
1417 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
1418 if (m_new == NULL) {
1419 printf("my%d: no memory for tx list", sc->my_unit);
1422 if (m_head->m_pkthdr.len > MHLEN) {
1423 MCLGET(m_new, MB_DONTWAIT);
1424 if (!(m_new->m_flags & M_EXT)) {
1426 printf("my%d: no memory for tx list", sc->my_unit);
1430 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t));
1431 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1434 f = &c->my_ptr->my_frag[0];
1436 f->my_data = vtophys(mtod(m_new, caddr_t));
1437 total_len = m_new->m_len;
1438 f->my_ctl = MY_TXFD | MY_TXLD | MY_CRCEnable | MY_PADEnable;
1439 f->my_ctl |= total_len << MY_PKTShift; /* pkt size */
1440 f->my_ctl |= total_len; /* buffer size */
1441 /* 89/12/29 add, for mtd891 *//* [ 89? ] */
1442 if (sc->my_info->my_did == MTD891ID)
1443 f->my_ctl |= MY_ETIControl | MY_RetryTxLC;
1444 c->my_mbuf = m_head;
1446 MY_TXNEXT(c) = vtophys(&c->my_nextdesc->my_ptr->my_frag[0]);
1452 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1453 * to the mbuf data regions directly in the transmit lists. We also save a
1454 * copy of the pointers since the transmit list fragment pointers are
1455 * physical addresses.
1458 my_start(struct ifnet * ifp)
1460 struct my_softc *sc;
1461 struct mbuf *m_head = NULL;
1462 struct my_chain *cur_tx = NULL, *start_tx;
1466 if (sc->my_autoneg) {
1472 * Check for an available queue slot. If there are none, punt.
1474 if (sc->my_cdata.my_tx_free->my_mbuf != NULL) {
1475 ifp->if_flags |= IFF_OACTIVE;
1479 start_tx = sc->my_cdata.my_tx_free;
1480 while (sc->my_cdata.my_tx_free->my_mbuf == NULL) {
1481 m_head = ifq_dequeue(&ifp->if_snd);
1485 /* Pick a descriptor off the free list. */
1486 cur_tx = sc->my_cdata.my_tx_free;
1487 sc->my_cdata.my_tx_free = cur_tx->my_nextdesc;
1489 /* Pack the data into the descriptor. */
1490 my_encap(sc, cur_tx, m_head);
1492 if (cur_tx != start_tx)
1493 MY_TXOWN(cur_tx) = MY_OWNByNIC;
1494 BPF_MTAP(ifp, cur_tx->my_mbuf);
1497 * If there are no packets queued, bail.
1499 if (cur_tx == NULL) {
1504 * Place the request for the upload interrupt in the last descriptor
1505 * in the chain. This way, if we're chaining several packets at once,
1506 * we'll only get an interupt once for the whole chain rather than
1507 * once for each packet.
1509 MY_TXCTL(cur_tx) |= MY_TXIC;
1510 cur_tx->my_ptr->my_frag[0].my_ctl |= MY_TXIC;
1511 sc->my_cdata.my_tx_tail = cur_tx;
1512 if (sc->my_cdata.my_tx_head == NULL)
1513 sc->my_cdata.my_tx_head = start_tx;
1514 MY_TXOWN(start_tx) = MY_OWNByNIC;
1515 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); /* tx polling demand */
1518 * Set a timeout in case the chip goes out to lunch.
1528 struct my_softc *sc = xsc;
1529 struct ifnet *ifp = &sc->arpcom.ac_if;
1531 u_int16_t phy_bmcr = 0;
1534 if (sc->my_autoneg) {
1539 if (sc->my_pinfo != NULL)
1540 phy_bmcr = my_phy_readreg(sc, PHY_BMCR);
1542 * Cancel pending I/O and free all RX/TX buffers.
1548 * Set cache alignment and burst length.
1550 #if 0 /* 89/9/1 modify, */
1551 CSR_WRITE_4(sc, MY_BCR, MY_RPBLE512);
1552 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF);
1554 CSR_WRITE_4(sc, MY_BCR, MY_PBL8);
1555 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF | MY_RBLEN | MY_RPBLE512);
1557 * 89/12/29 add, for mtd891,
1559 if (sc->my_info->my_did == MTD891ID) {
1560 MY_SETBIT(sc, MY_BCR, MY_PROG);
1561 MY_SETBIT(sc, MY_TCRRCR, MY_Enhanced);
1563 my_setcfg(sc, phy_bmcr);
1564 /* Init circular RX list. */
1565 if (my_list_rx_init(sc) == ENOBUFS) {
1566 printf("my%d: init failed: no memory for rx buffers\n",
1573 /* Init TX descriptors. */
1574 my_list_tx_init(sc);
1576 /* If we want promiscuous mode, set the allframes bit. */
1577 if (ifp->if_flags & IFF_PROMISC)
1578 MY_SETBIT(sc, MY_TCRRCR, MY_PROM);
1580 MY_CLRBIT(sc, MY_TCRRCR, MY_PROM);
1583 * Set capture broadcast bit to capture broadcast frames.
1585 if (ifp->if_flags & IFF_BROADCAST)
1586 MY_SETBIT(sc, MY_TCRRCR, MY_AB);
1588 MY_CLRBIT(sc, MY_TCRRCR, MY_AB);
1591 * Program the multicast filter, if necessary.
1596 * Load the address of the RX list.
1598 MY_CLRBIT(sc, MY_TCRRCR, MY_RE);
1599 CSR_WRITE_4(sc, MY_RXLBA, vtophys(&sc->my_ldata->my_rx_list[0]));
1602 * Enable interrupts.
1604 CSR_WRITE_4(sc, MY_IMR, MY_INTRS);
1605 CSR_WRITE_4(sc, MY_ISR, 0xFFFFFFFF);
1607 /* Enable receiver and transmitter. */
1608 MY_SETBIT(sc, MY_TCRRCR, MY_RE);
1609 MY_CLRBIT(sc, MY_TCRRCR, MY_TE);
1610 CSR_WRITE_4(sc, MY_TXLBA, vtophys(&sc->my_ldata->my_tx_list[0]));
1611 MY_SETBIT(sc, MY_TCRRCR, MY_TE);
1613 /* Restore state of BMCR */
1614 if (sc->my_pinfo != NULL)
1615 my_phy_writereg(sc, PHY_BMCR, phy_bmcr);
1616 ifp->if_flags |= IFF_RUNNING;
1617 ifp->if_flags &= ~IFF_OACTIVE;
1624 * Set media options.
1628 my_ifmedia_upd(struct ifnet * ifp)
1630 struct my_softc *sc;
1631 struct ifmedia *ifm;
1636 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) {
1640 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO)
1641 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1);
1643 my_setmode_mii(sc, ifm->ifm_media);
1649 * Report current media status.
1653 my_ifmedia_sts(struct ifnet * ifp, struct ifmediareq * ifmr)
1655 struct my_softc *sc;
1656 u_int16_t advert = 0, ability = 0;
1660 ifmr->ifm_active = IFM_ETHER;
1661 if (!(my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) {
1662 #if 0 /* this version did not support 1000M, */
1663 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_1000)
1664 ifmr->ifm_active = IFM_ETHER | IFM_1000TX;
1666 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL)
1667 ifmr->ifm_active = IFM_ETHER | IFM_100_TX;
1669 ifmr->ifm_active = IFM_ETHER | IFM_10_T;
1670 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX)
1671 ifmr->ifm_active |= IFM_FDX;
1673 ifmr->ifm_active |= IFM_HDX;
1678 ability = my_phy_readreg(sc, PHY_LPAR);
1679 advert = my_phy_readreg(sc, PHY_ANAR);
1681 #if 0 /* this version did not support 1000M, */
1682 if (sc->my_pinfo->my_vid = MarvellPHYID0) {
1683 ability2 = my_phy_readreg(sc, PHY_1000SR);
1684 if (ability2 & PHY_1000SR_1000BTXFULL) {
1687 ifmr->ifm_active = IFM_ETHER | IFM_1000_T | IFM_FDX;
1688 } else if (ability & PHY_1000SR_1000BTXHALF) {
1691 ifmr->ifm_active = IFM_ETHER | IFM_1000_T | IFM_HDX;
1695 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4)
1696 ifmr->ifm_active = IFM_ETHER | IFM_100_T4;
1697 else if (advert & PHY_ANAR_100BTXFULL && ability & PHY_ANAR_100BTXFULL)
1698 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1699 else if (advert & PHY_ANAR_100BTXHALF && ability & PHY_ANAR_100BTXHALF)
1700 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_HDX;
1701 else if (advert & PHY_ANAR_10BTFULL && ability & PHY_ANAR_10BTFULL)
1702 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_FDX;
1703 else if (advert & PHY_ANAR_10BTHALF && ability & PHY_ANAR_10BTHALF)
1704 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_HDX;
1710 my_ioctl(struct ifnet * ifp, u_long command, caddr_t data, struct ucred *cr)
1712 struct my_softc *sc = ifp->if_softc;
1713 struct ifreq *ifr = (struct ifreq *) data;
1722 error = ether_ioctl(ifp, command, data);
1725 if (ifp->if_flags & IFF_UP)
1727 else if (ifp->if_flags & IFF_RUNNING)
1738 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
1750 my_watchdog(struct ifnet * ifp)
1752 struct my_softc *sc;
1756 if (sc->my_autoneg) {
1757 my_autoneg_mii(sc, MY_FLAG_DELAYTIMEO, 1);
1762 printf("my%d: watchdog timeout\n", sc->my_unit);
1763 if (!(my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
1764 printf("my%d: no carrier - transceiver cable problem?\n",
1769 if (!ifq_is_empty(&ifp->if_snd))
1777 * Stop the adapter and free any mbufs allocated to the RX and TX lists.
1780 my_stop(struct my_softc * sc)
1786 ifp = &sc->arpcom.ac_if;
1789 MY_CLRBIT(sc, MY_TCRRCR, (MY_RE | MY_TE));
1790 CSR_WRITE_4(sc, MY_IMR, 0x00000000);
1791 CSR_WRITE_4(sc, MY_TXLBA, 0x00000000);
1792 CSR_WRITE_4(sc, MY_RXLBA, 0x00000000);
1795 * Free data in the RX lists.
1797 for (i = 0; i < MY_RX_LIST_CNT; i++) {
1798 if (sc->my_cdata.my_rx_chain[i].my_mbuf != NULL) {
1799 m_freem(sc->my_cdata.my_rx_chain[i].my_mbuf);
1800 sc->my_cdata.my_rx_chain[i].my_mbuf = NULL;
1803 bzero((char *)&sc->my_ldata->my_rx_list,
1804 sizeof(sc->my_ldata->my_rx_list));
1806 * Free the TX list buffers.
1808 for (i = 0; i < MY_TX_LIST_CNT; i++) {
1809 if (sc->my_cdata.my_tx_chain[i].my_mbuf != NULL) {
1810 m_freem(sc->my_cdata.my_tx_chain[i].my_mbuf);
1811 sc->my_cdata.my_tx_chain[i].my_mbuf = NULL;
1814 bzero((char *)&sc->my_ldata->my_tx_list,
1815 sizeof(sc->my_ldata->my_tx_list));
1816 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1822 * Stop all chip I/O so that the kernel's probe routines don't get confused
1823 * by errant DMAs when rebooting.
1826 my_shutdown(device_t dev)
1828 struct my_softc *sc;
1830 sc = device_get_softc(dev);