2 * Copyright (c) 1993 Herb Peyerl (hpeyerl@novatel.ca) All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are
6 * met: 1. Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer. 2. The name
8 * of the author may not be used to endorse or promote products derived from
9 * this software without specific prior written permission
11 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
14 * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
15 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
16 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
17 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
18 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
19 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
20 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 * $FreeBSD: src/sys/dev/vx/if_vxreg.h,v 1.6 2000/05/01 19:54:26 peter Exp $
23 * $DragonFly: src/sys/dev/netif/vx/if_vxreg.h,v 1.5 2004/09/15 01:09:23 joerg Exp $
27 Modified by: Andres Vega Garcia
29 INRIA - Sophia Antipolis, France
30 e-mail: avega@sophia.inria.fr
31 finger: avega@pax.inria.fr
36 * Created from if_epreg.h by Fred Gray (fgray@rice.edu) to support the
41 * Promiscuous mode added and interrupt logic slightly changed
42 * to reduce the number of adapter failures. Transceiver select
43 * logic changed to use value from EEPROM. Autoconfiguration
47 * Chelindbank (Chelyabinsk, Russia)
48 * babkin@hq.icb.chel.su
52 * Ethernet software status per interface.
55 struct arpcom arpcom; /* Ethernet common part */
56 int unit; /* unit number */
57 bus_space_handle_t vx_bhandle;
58 bus_space_tag_t vx_btag;
60 struct resource *vx_irq;
61 struct resource *vx_res;
62 #define MAX_MBS 8 /* # of mbufs we keep around */
63 struct mbuf *mb[MAX_MBS]; /* spare mbuf storage. */
64 int next_mb; /* Which mbuf to use next. */
65 int last_mb; /* Last mbuf. */
66 char vx_connectors; /* Connectors on this card. */
67 char vx_connector; /* Connector to use. */
68 short tx_start_thresh; /* Current TX_start_thresh. */
69 int tx_succ_ok; /* # packets sent in sequence */
71 struct callout vx_timer; /* Callout handle for timeouts */
75 #define CSR_WRITE_4(sc, reg, val) \
76 bus_space_write_4(sc->vx_btag, sc->vx_bhandle, reg, val)
77 #define CSR_WRITE_2(sc, reg, val) \
78 bus_space_write_2(sc->vx_btag, sc->vx_bhandle, reg, val)
79 #define CSR_WRITE_1(sc, reg, val) \
80 bus_space_write_1(sc->vx_btag, sc->vx_bhandle, reg, val)
82 #define CSR_READ_4(sc, reg) \
83 bus_space_read_4(sc->vx_btag, sc->vx_bhandle, reg)
84 #define CSR_READ_2(sc, reg) \
85 bus_space_read_2(sc->vx_btag, sc->vx_bhandle, reg)
86 #define CSR_READ_1(sc, reg) \
87 bus_space_read_1(sc->vx_btag, sc->vx_bhandle, reg)
90 * Some global constants
93 #define TX_INIT_RATE 16
94 #define TX_INIT_MAX_RATE 64
95 #define RX_INIT_LATENCY 64
96 #define RX_INIT_EARLY_THRESH 64
97 #define MIN_RX_EARLY_THRESHF 16 /* not less than ether_header */
98 #define MIN_RX_EARLY_THRESHL 4
100 #define EEPROMSIZE 0x40
101 #define MAX_EEPROMBUSY 1000
102 #define VX_LAST_TAG 0xd7
103 #define VX_MAX_BOARDS 16
104 #define VX_ID_PORT 0x100
107 * some macros to acces long named fields
109 #define BASE (sc->vx_io_addr)
112 * Commands to read/write EEPROM trough EEPROM command register (Window 0,
115 #define EEPROM_CMD_RD 0x0080 /* Read: Address required (5 bits) */
116 #define EEPROM_CMD_WR 0x0040 /* Write: Address required (5 bits) */
117 #define EEPROM_CMD_ERASE 0x00c0 /* Erase: Address required (5 bits) */
118 #define EEPROM_CMD_EWEN 0x0030 /* Erase/Write Enable: No data required */
120 #define EEPROM_BUSY (1<<15)
123 * Some short functions, worth to let them be a macro
126 /**************************************************************************
128 * These define the EEPROM data structure. They are used in the probe
129 * function to verify the existence of the adapter after having sent
132 * There are others but only the ones we use are defined here.
134 **************************************************************************/
136 #define EEPROM_NODE_ADDR_0 0x0 /* Word */
137 #define EEPROM_NODE_ADDR_1 0x1 /* Word */
138 #define EEPROM_NODE_ADDR_2 0x2 /* Word */
139 #define EEPROM_PROD_ID 0x3 /* 0x9[0-f]50 */
140 #define EEPROM_MFG_ID 0x7 /* 0x6d50 */
141 #define EEPROM_ADDR_CFG 0x8 /* Base addr */
142 #define EEPROM_RESOURCE_CFG 0x9 /* IRQ. Bits 12-15 */
143 #define EEPROM_OEM_ADDR_0 0xa /* Word */
144 #define EEPROM_OEM_ADDR_1 0xb /* Word */
145 #define EEPROM_OEM_ADDR_2 0xc /* Word */
146 #define EEPROM_SOFT_INFO_2 0xf /* Software information 2 */
148 #define NO_RX_OVN_ANOMALY (1<<5)
150 /**************************************************************************
152 * These are the registers for the 3Com 3c509 and their bit patterns when *
153 * applicable. They have been taken out the the "EtherLink III Parallel *
154 * Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual *
157 **************************************************************************/
159 #define VX_COMMAND 0x0e /* Write. BASE+0x0e is always a
161 #define VX_STATUS 0x0e /* Read. BASE+0x0e is always status
163 #define VX_WINDOW 0x0f /* Read. BASE+0x0f is always window
166 * Window 0 registers. Setup.
169 #define VX_W0_EEPROM_DATA 0x0c
170 #define VX_W0_EEPROM_COMMAND 0x0a
171 #define VX_W0_RESOURCE_CFG 0x08
172 #define VX_W0_ADDRESS_CFG 0x06
173 #define VX_W0_CONFIG_CTRL 0x04
175 #define VX_W0_PRODUCT_ID 0x02
176 #define VX_W0_MFG_ID 0x00
180 * Window 1 registers. Operating Set.
183 #define VX_W1_TX_PIO_WR_2 0x02
184 #define VX_W1_TX_PIO_WR_1 0x00
186 #define VX_W1_FREE_TX 0x0c
187 #define VX_W1_TX_STATUS 0x0b /* byte */
188 #define VX_W1_TIMER 0x0a /* byte */
189 #define VX_W1_RX_STATUS 0x08
190 #define VX_W1_RX_PIO_RD_2 0x02
191 #define VX_W1_RX_PIO_RD_1 0x00
194 * Window 2 registers. Station Address Setup/Read
197 #define VX_W2_ADDR_5 0x05
198 #define VX_W2_ADDR_4 0x04
199 #define VX_W2_ADDR_3 0x03
200 #define VX_W2_ADDR_2 0x02
201 #define VX_W2_ADDR_1 0x01
202 #define VX_W2_ADDR_0 0x00
205 * Window 3 registers. FIFO Management.
208 #define VX_W3_INTERNAL_CFG 0x00
209 #define VX_W3_RESET_OPT 0x08
210 #define VX_W3_FREE_TX 0x0c
211 #define VX_W3_FREE_RX 0x0a
214 * Window 4 registers. Diagnostics.
217 #define VX_W4_MEDIA_TYPE 0x0a
218 #define VX_W4_CTRLR_STATUS 0x08
219 #define VX_W4_NET_DIAG 0x06
220 #define VX_W4_FIFO_DIAG 0x04
221 #define VX_W4_HOST_DIAG 0x02
222 #define VX_W4_TX_DIAG 0x00
225 * Window 5 Registers. Results and Internal status.
228 #define VX_W5_READ_0_MASK 0x0c
229 #define VX_W5_INTR_MASK 0x0a
230 #define VX_W5_RX_FILTER 0x08
231 #define VX_W5_RX_EARLY_THRESH 0x06
232 #define VX_W5_TX_AVAIL_THRESH 0x02
233 #define VX_W5_TX_START_THRESH 0x00
236 * Window 6 registers. Statistics.
239 #define TX_TOTAL_OK 0x0c
240 #define RX_TOTAL_OK 0x0a
241 #define TX_DEFERRALS 0x08
242 #define RX_FRAMES_OK 0x07
243 #define TX_FRAMES_OK 0x06
244 #define RX_OVERRUNS 0x05
245 #define TX_COLLISIONS 0x04
246 #define TX_AFTER_1_COLLISION 0x03
247 #define TX_AFTER_X_COLLISIONS 0x02
248 #define TX_NO_SQE 0x01
249 #define TX_CD_LOST 0x00
251 /****************************************
253 * Register definitions.
255 ****************************************/
258 * Command register. All windows.
261 * 15-11: 5-bit code for command to be executed.
262 * 10-0: 11-bit arg if any. For commands with no args;
263 * this can be set to anything.
265 #define GLOBAL_RESET (u_short) 0x0000 /* Wait at least 1ms
267 #define WINDOW_SELECT (u_short) (0x1<<11)
268 #define START_TRANSCEIVER (u_short) (0x2<<11) /* Read ADDR_CFG reg to
272 * before using trans-
274 #define RX_DISABLE (u_short) (0x3<<11) /* state disabled on
276 #define RX_ENABLE (u_short) (0x4<<11)
277 #define RX_RESET (u_short) (0x5<<11)
278 #define RX_DISCARD_TOP_PACK (u_short) (0x8<<11)
279 #define TX_ENABLE (u_short) (0x9<<11)
280 #define TX_DISABLE (u_short) (0xa<<11)
281 #define TX_RESET (u_short) (0xb<<11)
282 #define REQ_INTR (u_short) (0xc<<11)
284 * The following C_* acknowledge the various interrupts. Some of them don't
285 * do anything. See the manual.
287 #define ACK_INTR (u_short) (0x6800)
288 # define C_INTR_LATCH (u_short) (ACK_INTR|0x1)
289 # define C_CARD_FAILURE (u_short) (ACK_INTR|0x2)
290 # define C_TX_COMPLETE (u_short) (ACK_INTR|0x4)
291 # define C_TX_AVAIL (u_short) (ACK_INTR|0x8)
292 # define C_RX_COMPLETE (u_short) (ACK_INTR|0x10)
293 # define C_RX_EARLY (u_short) (ACK_INTR|0x20)
294 # define C_INT_RQD (u_short) (ACK_INTR|0x40)
295 # define C_UPD_STATS (u_short) (ACK_INTR|0x80)
296 #define SET_INTR_MASK (u_short) (0xe<<11)
297 #define SET_RD_0_MASK (u_short) (0xf<<11)
298 #define SET_RX_FILTER (u_short) (0x10<<11)
299 # define FIL_INDIVIDUAL (u_short) (0x1)
300 # define FIL_MULTICAST (u_short) (0x02)
301 # define FIL_BRDCST (u_short) (0x04)
302 # define FIL_PROMISC (u_short) (0x08)
303 #define SET_RX_EARLY_THRESH (u_short) (0x11<<11)
304 #define SET_TX_AVAIL_THRESH (u_short) (0x12<<11)
305 #define SET_TX_START_THRESH (u_short) (0x13<<11)
306 #define STATS_ENABLE (u_short) (0x15<<11)
307 #define STATS_DISABLE (u_short) (0x16<<11)
308 #define STOP_TRANSCEIVER (u_short) (0x17<<11)
311 * Status register. All windows.
313 * 15-13: Window number(0-7).
314 * 12: Command_in_progress.
319 * 7: Update Statistics.
320 * 6: Interrupt Requested.
325 * 1: Adapter Failure.
326 * 0: Interrupt Latch.
328 #define S_INTR_LATCH (u_short) (0x1)
329 #define S_CARD_FAILURE (u_short) (0x2)
330 #define S_TX_COMPLETE (u_short) (0x4)
331 #define S_TX_AVAIL (u_short) (0x8)
332 #define S_RX_COMPLETE (u_short) (0x10)
333 #define S_RX_EARLY (u_short) (0x20)
334 #define S_INT_RQD (u_short) (0x40)
335 #define S_UPD_STATS (u_short) (0x80)
336 #define S_COMMAND_IN_PROGRESS (u_short) (0x1000)
338 #define VX_BUSY_WAIT while (CSR_READ_2(sc, VX_STATUS) & S_COMMAND_IN_PROGRESS)
340 /* Address Config. Register.
344 #define ACF_CONNECTOR_BITS 14
345 #define ACF_CONNECTOR_UTP 0
346 #define ACF_CONNECTOR_AUI 1
347 #define ACF_CONNECTOR_BNC 3
349 #define INTERNAL_CONNECTOR_BITS 20
350 #define INTERNAL_CONNECTOR_MASK 0x01700000
353 * FIFO Registers. RX Status.
355 * 15: Incomplete or FIFO empty.
356 * 14: 1: Error in RX Packet 0: Incomplete or no error.
357 * 13-11: Type of error.
359 * 1011 = Run Packet Error.
360 * 1100 = Alignment Error.
362 * 1001 = Oversize Packet Error (>1514 bytes)
363 * 0010 = Dribble Bits.
364 * (all other error codes, no errors.)
366 * 10-0: RX Bytes (0-1514)
368 #define ERR_INCOMPLETE (u_short) (0x8000)
369 #define ERR_RX (u_short) (0x4000)
370 #define ERR_MASK (u_short) (0x7800)
371 #define ERR_OVERRUN (u_short) (0x4000)
372 #define ERR_RUNT (u_short) (0x5800)
373 #define ERR_ALIGNMENT (u_short) (0x6000)
374 #define ERR_CRC (u_short) (0x6800)
375 #define ERR_OVERSIZE (u_short) (0x4800)
376 #define ERR_DRIBBLE (u_short) (0x1000)
381 * Reports the transmit status of a completed transmission. Writing this
382 * register pops the transmit completion stack.
384 * Window 1/Port 0x0b.
387 * 6: Interrupt on successful transmission requested.
388 * 5: Jabber Error (TP Only, TX Reset required. )
389 * 4: Underrun (TX Reset required. )
390 * 3: Maximum Collisions.
391 * 2: TX Status Overflow.
395 #define TXS_COMPLETE 0x80
396 #define TXS_INTR_REQ 0x40
397 #define TXS_JABBER 0x20
398 #define TXS_UNDERRUN 0x10
399 #define TXS_MAX_COLLISION 0x8
400 #define TXS_STATUS_OVERFLOW 0x4
402 #define RS_AUI (1<<5)
403 #define RS_BNC (1<<4)
404 #define RS_UTP (1<<3)
408 #define RS_MII (1<<6)
412 * FIFO Status (Window 4)
414 * Supports FIFO diagnostics
416 * Window 4/Port 0x04.1
418 * 15: 1=RX receiving (RO). Set when a packet is being received
421 * 13: 1=RX underrun (RO). Generates Adapter Failure interrupt.
422 * Requires RX Reset or Global Reset command to recover.
423 * It is generated when you read past the end of a packet -
424 * reading past what has been received so far will give bad
426 * 12: 1=RX status overrun (RO). Set when there are already 8
427 * packets in the RX FIFO. While this bit is set, no additional
428 * packets are received. Requires no action on the part of
429 * the host. The condition is cleared once a packet has been
430 * read out of the RX FIFO.
431 * 11: 1=RX overrun (RO). Set when the RX FIFO is full (there
432 * may not be an overrun packet yet). While this bit is set,
433 * no additional packets will be received (some additional
434 * bytes can still be pending between the wire and the RX
435 * FIFO). Requires no action on the part of the host. The
436 * condition is cleared once a few bytes have been read out
438 * 10: 1=TX overrun (RO). Generates adapter failure interrupt.
439 * Requires TX Reset or Global Reset command to recover.
440 * Disables Transmitter.
442 * 7-0: Built in self test bits for the RX and TX FIFO's.
444 #define FIFOS_RX_RECEIVING (u_short) 0x8000
445 #define FIFOS_RX_UNDERRUN (u_short) 0x2000
446 #define FIFOS_RX_STATUS_OVERRUN (u_short) 0x1000
447 #define FIFOS_RX_OVERRUN (u_short) 0x0800
448 #define FIFOS_TX_OVERRUN (u_short) 0x0400
451 * Misc defines for various things.
453 #define TAG_ADAPTER 0xd0
454 #define ACTIVATE_ADAPTER_TO_CONFIG 0xff
455 #define ENABLE_DRQ_IRQ 0x0001
456 #define MFG_ID 0x506d /* `TCM' */
457 #define PROD_ID 0x5090
458 #define GO_WINDOW(x) CSR_WRITE_2(sc, VX_COMMAND, WINDOW_SELECT|(x))
459 #define JABBER_GUARD_ENABLE 0x40
460 #define LINKBEAT_ENABLE 0x80
461 #define ENABLE_UTP (JABBER_GUARD_ENABLE | LINKBEAT_ENABLE)
462 #define DISABLE_UTP 0x0
463 #define RX_BYTES_MASK (u_short) (0x07ff)
464 #define TX_INDICATE 1<<15
466 #define VX_IOSIZE 0x20
468 #define VX_CONNECTORS 8
470 extern struct vx_softc *vx_softc[];
471 extern u_long vx_count;
472 extern struct vx_softc *vxalloc (int);
473 extern void vxfree (struct vx_softc *);
474 extern int vxattach (struct vx_softc *);
475 extern void vxstop (struct vx_softc *);
476 extern void vxintr (void *);
477 extern int vxbusyeeprom (struct vx_softc *);