sys/dev/pccard/exca/excareg.h

   1 /*      $NetBSD: i82365reg.h,v 1.3 1998/12/20 17:53:28 nathanw Exp $    */
   2 /* $FreeBSD: src/sys/dev/exca/excareg.h,v 1.2 2002/07/26 08:01:08 imp Exp $ */
   3 /* $DragonFly: src/sys/dev/pccard/exca/excareg.h,v 1.1 2004/02/10 07:55:47 joerg Exp $ */
   4
   5 /*
   6  * Copyright (c) 2002 M Warner Losh.  All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * This software may be derived from NetBSD i82365.c and other files with
  29  * the following copyright:
  30  *
  31  * Copyright (c) 1997 Marc Horowitz.  All rights reserved.
  32  *
  33  * Redistribution and use in source and binary forms, with or without
  34  * modification, are permitted provided that the following conditions
  35  * are met:
  36  * 1. Redistributions of source code must retain the above copyright
  37  *    notice, this list of conditions and the following disclaimer.
  38  * 2. Redistributions in binary form must reproduce the above copyright
  39  *    notice, this list of conditions and the following disclaimer in the
  40  *    documentation and/or other materials provided with the distribution.
  41  * 3. All advertising materials mentioning features or use of this software
  42  *    must display the following acknowledgement:
  43  *      This product includes software developed by Marc Horowitz.
  44  * 4. The name of the author may not be used to endorse or promote products
  45  *    derived from this software without specific prior written permission.
  46  *
  47  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  48  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  49  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  50  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  51  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  52  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  53  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  54  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  55  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  56  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  57  */
  58
  59 #ifndef _SYS_DEV_EXCA_EXCAREG_H
  60 #define _SYS_DEV_EXCA_EXCAREG_H
  61
  62 /*
  63  * All information is from the intel 82365sl PC Card Interface Controller
  64  * (PCIC) data sheet, marked "preliminary".  Order number 290423-002, January
  65  * 1993.
  66  */
  67
  68 #define EXCA_IOSIZE             2
  69
  70 #define EXCA_REG_INDEX          0
  71 #define EXCA_REG_DATA           1
  72
  73 #define EXCA_NSLOTS             4       /* 2 in 2 chips */
  74
  75 /*
  76  * I/o ports
  77  */
  78 #define EXCA_INDEX0             0x3e0
  79
  80 /*
  81  * The PCIC allows two chips to share the same address.  In order not to run
  82  * afoul of the bsd device model, this driver will treat those chips as
  83  * the same device.
  84  */
  85
  86 #define EXCA_CHIP0_BASE         0x00
  87 #define EXCA_CHIP1_BASE         0x80
  88
  89 /* Each PCIC chip can drive two sockets */
  90
  91 #define EXCA_SOCKET_SIZE        0x40
  92 #define EXCA_SOCKETA_INDEX      0x00
  93 #define EXCA_SOCKETB_INDEX      EXCA_SOCKET_SIZE
  94
  95 /* general setup registers */
  96
  97 #define EXCA_IDENT                              0x00    /* RO */
  98 #define EXCA_IDENT_IFTYPE_MASK                  0xC0
  99 #define EXCA_IDENT_IFTYPE_IO_ONLY               0x00
 100 #define EXCA_IDENT_IFTYPE_MEM_ONLY              0x40
 101 #define EXCA_IDENT_IFTYPE_MEM_AND_IO            0x80
 102 #define EXCA_IDENT_IFTYPE_RESERVED              0xC0
 103 #define EXCA_IDENT_ZERO                         0x30
 104 #define EXCA_IDENT_REV_MASK                     0x0F
 105 #define EXCA_IDENT_REV_I82365SLR0               0x02
 106 #define EXCA_IDENT_REV_I82365SLR1               0x03
 107
 108 #define EXCA_IF_STATUS                          0x01    /* RO */
 109 #define EXCA_IF_STATUS_GPI                      0x80 /* General Purpose Input */
 110 #define EXCA_IF_STATUS_POWERACTIVE              0x40
 111 #define EXCA_IF_STATUS_READY                    0x20 /* really READY/!BUSY */
 112 #define EXCA_IF_STATUS_MEM_WP                   0x10
 113 #define EXCA_IF_STATUS_CARDDETECT_MASK          0x0C
 114 #define EXCA_IF_STATUS_CARDDETECT_PRESENT       0x0C
 115 #define EXCA_IF_STATUS_BATTERY_MASK             0x03
 116 #define EXCA_IF_STATUS_BATTERY_DEAD1            0x00
 117 #define EXCA_IF_STATUS_BATTERY_DEAD2            0x01
 118 #define EXCA_IF_STATUS_BATTERY_WARNING          0x02
 119 #define EXCA_IF_STATUS_BATTERY_GOOD             0x03
 120
 121 #define EXCA_PWRCTL                             0x02    /* RW */
 122 #define EXCA_PWRCTL_OE                          0x80    /* output enable */
 123 #define EXCA_PWRCTL_DISABLE_RESETDRV            0x40
 124 #define EXCA_PWRCTL_AUTOSWITCH_ENABLE           0x20
 125 #define EXCA_PWRCTL_PWR_ENABLE                  0x10
 126 #define EXCA_PWRCTL_VPP2_MASK                   0x0C
 127 /* XXX these are a little unclear from the data sheet */
 128 #define EXCA_PWRCTL_VPP2_RESERVED               0x0C
 129 #define EXCA_PWRCTL_VPP2_EN1                    0x08
 130 #define EXCA_PWRCTL_VPP2_EN0                    0x04
 131 #define EXCA_PWRCTL_VPP2_ENX                    0x00
 132 #define EXCA_PWRCTL_VPP1_MASK                   0x03
 133 /* XXX these are a little unclear from the data sheet */
 134 #define EXCA_PWRCTL_VPP1_RESERVED               0x03
 135 #define EXCA_PWRCTL_VPP1_EN1                    0x02
 136 #define EXCA_PWRCTL_VPP1_EN0                    0x01
 137 #define EXCA_PWRCTL_VPP1_ENX                    0x00
 138
 139 #define EXCA_CSC                                0x04    /* RW */
 140 #define EXCA_CSC_ZERO                           0xE0
 141 #define EXCA_CSC_GPI                            0x10
 142 #define EXCA_CSC_CD                             0x08 /* Card Detect Change */
 143 #define EXCA_CSC_READY                          0x04
 144 #define EXCA_CSC_BATTWARN                       0x02
 145 #define EXCA_CSC_BATTDEAD                       0x01    /* for memory cards */
 146 #define EXCA_CSC_RI                             0x01    /* for i/o cards */
 147
 148 #define EXCA_ADDRWIN_ENABLE                     0x06    /* RW */
 149 #define EXCA_ADDRWIN_ENABLE_IO1                 0x80
 150 #define EXCA_ADDRWIN_ENABLE_IO0                 0x40
 151 #define EXCA_ADDRWIN_ENABLE_MEMCS16             0x20    /* rtfds if you care */
 152 #define EXCA_ADDRWIN_ENABLE_MEM4                0x10
 153 #define EXCA_ADDRWIN_ENABLE_MEM3                0x08
 154 #define EXCA_ADDRWIN_ENABLE_MEM2                0x04
 155 #define EXCA_ADDRWIN_ENABLE_MEM1                0x02
 156 #define EXCA_ADDRWIN_ENABLE_MEM0                0x01
 157
 158 #define EXCA_CARD_DETECT                        0x16    /* RW */
 159 #define EXCA_CARD_DETECT_RESERVED               0xC0
 160 #define EXCA_CARD_DETECT_SW_INTR                0x20
 161 #define EXCA_CARD_DETECT_RESUME_ENABLE          0x10
 162 #define EXCA_CARD_DETECT_GPI_TRANSCTL           0x08
 163 #define EXCA_CARD_DETECT_GPI_ENABLE             0x04
 164 #define EXCA_CARD_DETECT_CFGRST_ENABLE          0x02
 165 #define EXCA_CARD_DETECT_MEMDLY_INHIBIT         0x01
 166
 167 /* interrupt registers */
 168
 169 #define EXCA_INTR                               0x03    /* RW */
 170 #define EXCA_INTR_RI_ENABLE                     0x80
 171 #define EXCA_INTR_RESET                         0x40    /* active low (zero) */
 172 #define EXCA_INTR_CARDTYPE_MASK                 0x20
 173 #define EXCA_INTR_CARDTYPE_IO                   0x20
 174 #define EXCA_INTR_CARDTYPE_MEM                  0x00
 175 #define EXCA_INTR_ENABLE                        0x10
 176 #define EXCA_INTR_IRQ_MASK                      0x0F
 177 #define EXCA_INTR_IRQ_SHIFT                     0
 178 #define EXCA_INTR_IRQ_NONE                      0x00
 179 #define EXCA_INTR_IRQ_RESERVED1                 0x01
 180 #define EXCA_INTR_IRQ_RESERVED2                 0x02
 181 #define EXCA_INTR_IRQ3                          0x03
 182 #define EXCA_INTR_IRQ4                          0x04
 183 #define EXCA_INTR_IRQ5                          0x05
 184 #define EXCA_INTR_IRQ_RESERVED6                 0x06
 185 #define EXCA_INTR_IRQ7                          0x07
 186 #define EXCA_INTR_IRQ_RESERVED8                 0x08
 187 #define EXCA_INTR_IRQ9                          0x09
 188 #define EXCA_INTR_IRQ10                         0x0A
 189 #define EXCA_INTR_IRQ11                         0x0B
 190 #define EXCA_INTR_IRQ12                         0x0C
 191 #define EXCA_INTR_IRQ_RESERVED13                0x0D
 192 #define EXCA_INTR_IRQ14                         0x0E
 193 #define EXCA_INTR_IRQ15                         0x0F
 194
 195 #define EXCA_INTR_IRQ_VALIDMASK                 0xDEB8 /* 1101 1110 1011 1000 */
 196
 197 #define EXCA_CSC_INTR                           0x05    /* RW */
 198 #define EXCA_CSC_INTR_IRQ_MASK                  0xF0
 199 #define EXCA_CSC_INTR_IRQ_SHIFT                 4
 200 #define EXCA_CSC_INTR_IRQ_NONE                  0x00
 201 #define EXCA_CSC_INTR_IRQ_RESERVED1             0x10
 202 #define EXCA_CSC_INTR_IRQ_RESERVED2             0x20
 203 #define EXCA_CSC_INTR_IRQ3                      0x30
 204 #define EXCA_CSC_INTR_IRQ4                      0x40
 205 #define EXCA_CSC_INTR_IRQ5                      0x50
 206 #define EXCA_CSC_INTR_IRQ_RESERVED6             0x60
 207 #define EXCA_CSC_INTR_IRQ7                      0x70
 208 #define EXCA_CSC_INTR_IRQ_RESERVED8             0x80
 209 #define EXCA_CSC_INTR_IRQ9                      0x90
 210 #define EXCA_CSC_INTR_IRQ10                     0xA0
 211 #define EXCA_CSC_INTR_IRQ11                     0xB0
 212 #define EXCA_CSC_INTR_IRQ12                     0xC0
 213 #define EXCA_CSC_INTR_IRQ_RESERVED13            0xD0
 214 #define EXCA_CSC_INTR_IRQ14                     0xE0
 215 #define EXCA_CSC_INTR_IRQ15                     0xF0
 216 #define EXCA_CSC_INTR_CD_ENABLE                 0x08
 217 #define EXCA_CSC_INTR_READY_ENABLE              0x04
 218 #define EXCA_CSC_INTR_BATTWARN_ENABLE           0x02
 219 #define EXCA_CSC_INTR_BATTDEAD_ENABLE           0x01    /* for memory cards */
 220 #define EXCA_CSC_INTR_RI_ENABLE                 0x01    /* for I/O cards */
 221
 222 #define EXCA_CSC_INTR_IRQ_VALIDMASK             0xDEB8 /* 1101 1110 1011 1000 */
 223
 224 /* I/O registers */
 225
 226 #define EXCA_IO_WINS                            2
 227
 228 #define EXCA_IOCTL                              0x07    /* RW */
 229 #define EXCA_IOCTL_IO1_WAITSTATE                0x80
 230 #define EXCA_IOCTL_IO1_ZEROWAIT                 0x40
 231 #define EXCA_IOCTL_IO1_IOCS16SRC_MASK           0x20
 232 #define EXCA_IOCTL_IO1_IOCS16SRC_CARD           0x20
 233 #define EXCA_IOCTL_IO1_IOCS16SRC_DATASIZE       0x00
 234 #define EXCA_IOCTL_IO1_DATASIZE_MASK            0x10
 235 #define EXCA_IOCTL_IO1_DATASIZE_16BIT           0x10
 236 #define EXCA_IOCTL_IO1_DATASIZE_8BIT            0x00
 237 #define EXCA_IOCTL_IO0_WAITSTATE                0x08
 238 #define EXCA_IOCTL_IO0_ZEROWAIT                 0x04
 239 #define EXCA_IOCTL_IO0_IOCS16SRC_MASK           0x02
 240 #define EXCA_IOCTL_IO0_IOCS16SRC_CARD           0x02
 241 #define EXCA_IOCTL_IO0_IOCS16SRC_DATASIZE       0x00
 242 #define EXCA_IOCTL_IO0_DATASIZE_MASK            0x01
 243 #define EXCA_IOCTL_IO0_DATASIZE_16BIT           0x01
 244 #define EXCA_IOCTL_IO0_DATASIZE_8BIT            0x00
 245
 246 #define EXCA_IOADDR0_START_LSB                  0x08
 247 #define EXCA_IOADDR0_START_MSB                  0x09
 248 #define EXCA_IOADDR0_STOP_LSB                   0x0A
 249 #define EXCA_IOADDR0_STOP_MSB                   0x0B
 250 #define EXCA_IOADDR1_START_LSB                  0x0C
 251 #define EXCA_IOADDR1_START_MSB                  0x0D
 252 #define EXCA_IOADDR1_STOP_LSB                   0x0E
 253 #define EXCA_IOADDR1_STOP_MSB                   0x0F
 254
 255 /* memory registers */
 256
 257 /*
 258  * memory window addresses refer to bits A23-A12 of the ISA system memory
 259  * address.  This is a shift of 12 bits.  The LSB contains A19-A12, and the
 260  * MSB contains A23-A20, plus some other bits.
 261  */
 262
 263 #define EXCA_MEM_WINS                           5
 264
 265 #define EXCA_MEM_SHIFT                          12
 266 #define EXCA_MEM_PAGESIZE                       (1<<EXCA_MEM_SHIFT)
 267
 268 #define EXCA_SYSMEM_ADDRX_SHIFT                         EXCA_MEM_SHIFT
 269 #define EXCA_SYSMEM_ADDRX_START_MSB_DATASIZE_MASK       0x80
 270 #define EXCA_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT      0x80
 271 #define EXCA_SYSMEM_ADDRX_START_MSB_DATASIZE_8BIT       0x00
 272 #define EXCA_SYSMEM_ADDRX_START_MSB_ZEROWAIT            0x40
 273 #define EXCA_SYSMEM_ADDRX_START_MSB_SCRATCH_MASK        0x30
 274 #define EXCA_SYSMEM_ADDRX_START_MSB_ADDR_MASK           0x0F
 275
 276 #define EXCA_SYSMEM_ADDRX_STOP_MSB_WAIT_MASK            0xC0
 277 #define EXCA_SYSMEM_ADDRX_STOP_MSB_WAIT0                0x00
 278 #define EXCA_SYSMEM_ADDRX_STOP_MSB_WAIT1                0x40
 279 #define EXCA_SYSMEM_ADDRX_STOP_MSB_WAIT2                0x80
 280 #define EXCA_SYSMEM_ADDRX_STOP_MSB_WAIT3                0xC0
 281 #define EXCA_SYSMEM_ADDRX_STOP_MSB_ADDR_MASK            0x0F
 282
 283 /*
 284  * The card side of a memory mapping consists of bits A19-A12 of the card
 285  * memory address in the LSB, and A25-A20 plus some other bits in the MSB.
 286  * Again, the shift is 12 bits.
 287  */
 288
 289 #define EXCA_CARDMEM_ADDRX_SHIFT                EXCA_MEM_SHIFT
 290 #define EXCA_CARDMEM_ADDRX_MSB_WP               0x80
 291 #define EXCA_CARDMEM_ADDRX_MSB_REGACTIVE_MASK   0x40
 292 #define EXCA_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR   0x40
 293 #define EXCA_CARDMEM_ADDRX_MSB_REGACTIVE_COMMON 0x00
 294 #define EXCA_CARDMEM_ADDRX_MSB_ADDR_MASK        0x3F
 295
 296 #define EXCA_SYSMEM_ADDR0_START_LSB             0x10
 297 #define EXCA_SYSMEM_ADDR0_START_MSB             0x11
 298 #define EXCA_SYSMEM_ADDR0_STOP_LSB              0x12
 299 #define EXCA_SYSMEM_ADDR0_STOP_MSB              0x13
 300
 301 #define EXCA_CARDMEM_ADDR0_LSB                  0x14
 302 #define EXCA_CARDMEM_ADDR0_MSB                  0x15
 303
 304 /* #define      EXCA_RESERVED                   0x17 */
 305
 306 #define EXCA_SYSMEM_ADDR1_START_LSB             0x18
 307 #define EXCA_SYSMEM_ADDR1_START_MSB             0x19
 308 #define EXCA_SYSMEM_ADDR1_STOP_LSB              0x1A
 309 #define EXCA_SYSMEM_ADDR1_STOP_MSB              0x1B
 310
 311 #define EXCA_CARDMEM_ADDR1_LSB                  0x1C
 312 #define EXCA_CARDMEM_ADDR1_MSB                  0x1D
 313
 314 #define EXCA_SYSMEM_ADDR2_START_LSB             0x20
 315 #define EXCA_SYSMEM_ADDR2_START_MSB             0x21
 316 #define EXCA_SYSMEM_ADDR2_STOP_LSB              0x22
 317 #define EXCA_SYSMEM_ADDR2_STOP_MSB              0x23
 318
 319 #define EXCA_CARDMEM_ADDR2_LSB                  0x24
 320 #define EXCA_CARDMEM_ADDR2_MSB                  0x25
 321
 322 /* #define      EXCA_RESERVED                   0x26 */
 323 /* #define      EXCA_RESERVED                   0x27 */
 324
 325 #define EXCA_SYSMEM_ADDR3_START_LSB             0x28
 326 #define EXCA_SYSMEM_ADDR3_START_MSB             0x29
 327 #define EXCA_SYSMEM_ADDR3_STOP_LSB              0x2A
 328 #define EXCA_SYSMEM_ADDR3_STOP_MSB              0x2B
 329
 330 #define EXCA_CARDMEM_ADDR3_LSB                  0x2C
 331 #define EXCA_CARDMEM_ADDR3_MSB                  0x2D
 332
 333 /* #define      EXCA_RESERVED                   0x2E */
 334 /* #define      EXCA_RESERVED                   0x2F */
 335
 336 #define EXCA_SYSMEM_ADDR4_START_LSB             0x30
 337 #define EXCA_SYSMEM_ADDR4_START_MSB             0x31
 338 #define EXCA_SYSMEM_ADDR4_STOP_LSB              0x32
 339 #define EXCA_SYSMEM_ADDR4_STOP_MSB              0x33
 340
 341 #define EXCA_CARDMEM_ADDR4_LSB                  0x34
 342 #define EXCA_CARDMEM_ADDR4_MSB                  0x35
 343
 344 /* #define      EXCA_RESERVED                   0x36 */
 345 /* #define      EXCA_RESERVED                   0x37 */
 346 /* #define      EXCA_RESERVED                   0x38 */
 347 /* #define      EXCA_RESERVED                   0x39 */
 348 /* #define      EXCA_RESERVED                   0x3A */
 349 /* #define      EXCA_RESERVED                   0x3B */
 350 /* #define      EXCA_RESERVED                   0x3C */
 351 /* #define      EXCA_RESERVED                   0x3D */
 352 /* #define      EXCA_RESERVED                   0x3E */
 353 /* #define      EXCA_RESERVED                   0x3F */
 354
 355 /* cardbus extensions - memory window page registers */
 356
 357 #define EXCA_MEMREG_WIN_SHIFT                   24
 358 #define EXCA_SYSMEM_ADDR0_WIN                   0x40
 359 #define EXCA_SYSMEM_ADDR1_WIN                   0x41
 360 #define EXCA_SYSMEM_ADDR2_WIN                   0x42
 361 #define EXCA_SYSMEM_ADDR3_WIN                   0x43
 362 #define EXCA_SYSMEM_ADDR4_WIN                   0x44
 363
 364 /* vendor-specific registers */
 365
 366 #define EXCA_INTEL_GLOBAL_CTL                   0x1E    /* RW */
 367 #define EXCA_INTEL_GLOBAL_CTL_RESERVED          0xF0
 368 #define EXCA_INTEL_GLOBAL_CTL_IRQ14PULSE_ENABLE 0x08
 369 #define EXCA_INTEL_GLOBAL_CTL_EXPLICIT_CSC_ACK  0x04
 370 #define EXCA_INTEL_GLOBAL_CTL_IRQLEVEL_ENABLE   0x02
 371 #define EXCA_INTEL_GLOBAL_CTL_POWERDOWN         0x01
 372
 373 #define EXCA_CIRRUS_MISC_CTL_2                  0x1E
 374 #define EXCA_CIRRUS_MISC_CTL_2_SUSPEND          0x04
 375
 376 #define EXCA_CIRRUS_CHIP_INFO                   0x1F
 377 #define EXCA_CIRRUS_CHIP_INFO_CHIP_ID           0xC0
 378 #define EXCA_CIRRUS_CHIP_INFO_SLOTS             0x20
 379 #define EXCA_CIRRUS_CHIP_INFO_REV               0x1F
 380
 381 #define EXCA_CIRRUS_EXTENDED_INDEX              0x2E
 382 #define EXCA_CIRRUS_EXTENDED_DATA               0x2F
 383 #define EXCA_CIRRUS_EXT_CONTROL_1               0x03
 384 #define EXCA_CIRRUS_EXT_CONTROL_1_PCI_INTR_MASK 0x18
 385
 386 /* Plug and play */
 387 #define EXCA_PNP_ACTIONTEC      0x1802A904      /* AEI0218 */
 388 #define EXCA_PNP_IBM3765        0x65374d24      /* IBM3765 */
 389 #define EXCA_PNP_82365          0x000ED041      /* PNP0E00 */
 390 #define EXCA_PNP_CL_PD6720      0x010ED041      /* PNP0E01 */
 391 #define EXCA_PNP_VLSI_82C146    0x020ED041      /* PNP0E02 */
 392 #define EXCA_PNP_82365_CARDBUS  0x030ED041      /* PNP0E03 */
 393 #define EXCA_PNP_SCM_SWAPBOX    0x69046d4c      /* SMC0469 */
 394
 395 /* C-Bus PnP Definitions */
 396 #define EXCA_NEC_PC9801_102     0x9180a3b8      /* NEC8091 PC-9801-102 */
 397 #define EXCA_NEC_PC9821RA_E01   0x2181a3b8      /* NEC8121 PC-9821RA-E01 */
 398
 399 /*
 400  *      Mask of allowable interrupts.
 401  *
 402  *      For IBM-AT machines, irqs 3, 4, 5, 7, 9, 10, 11, 12, 14, 15 are
 403  *      allowed.  Nearly all IBM-AT machines with pcic cards or bridges
 404  *      wire these interrupts (or a subset thereof) to the corresponding
 405  *      pins on the ISA bus.  Some older laptops are reported to not route
 406  *      all the interrupt pins to the bus because the designers knew that
 407  *      some would conflict with builtin devices.  Older versions of Windows
 408  *      NT had a special device that would probe for conflicts early in the
 409  *      boot process and formulate a mapping table.  Maybe we should do
 410  *      something similar.
 411  *
 412  *      For NEC PC-98 machines, irq 3, 5, 6, 9, 10, 11, 12, 13 are allowed.
 413  *      These correspond to the C-BUS signals INT 0, 1, 2, 3, 41, 42, 5, 6
 414  *      respectively.
 415  *
 416  *      Hiroshi TSUKADA-san writes in FreeBSD98-testers that CBUS INT 2
 417  *      (mapped to IRQ 6) is routed to the IRQ 7 pin of the pcic in pc98
 418  *      cbus add-in cards.  He has confirmed this routing with a visual
 419  *      inspection of his card or a VOM.
 420  */
 421 #ifdef PC98
 422 #define EXCA_INT_MASK_ALLOWED   0x3E68          /* PC98 */
 423 #else
 424 #define EXCA_INT_MASK_ALLOWED   0xDEB8          /* AT */
 425 #endif
 426
 427 #endif /* !_SYS_DEV_EXCA_EXCAREG_H */