2 * Copyright (c) 1995 - 2001 John Hay. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. Neither the name of the author nor the names of any co-contributors
13 * may be used to endorse or promote products derived from this software
14 * without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY John Hay ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL John Hay BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * $FreeBSD: src/sys/dev/ar/if_ar.c,v 1.66 2005/01/06 01:42:28 imp Exp $
29 * $DragonFly: src/sys/dev/netif/ar/if_ar.c,v 1.22 2007/06/03 20:51:07 dillon Exp $
33 * Programming assumptions and other issues.
35 * The descriptors of a DMA channel will fit in a 16K memory window.
37 * The buffers of a transmit DMA channel will fit in a 16K memory window.
39 * Only the ISA bus cards with X.21 and V.35 is tested.
41 * When interface is going up, handshaking is set and it is only cleared
42 * when the interface is down'ed.
44 * There should be a way to set/reset Raw HDLC/PPP, Loopback, DCE/DTE,
45 * internal/external clock, etc.....
48 #include "opt_netgraph.h"
50 #include <sys/param.h>
51 #include <sys/systm.h>
52 #include <sys/kernel.h>
53 #include <sys/malloc.h>
55 #include <sys/socket.h>
56 #include <sys/sockio.h>
57 #include <sys/module.h>
59 #include <sys/serialize.h>
61 #include <sys/thread2.h>
65 #include <netgraph/ng_message.h>
66 #include <netgraph/netgraph.h>
67 #include <sys/syslog.h>
68 #include <dev/netif/ar/if_ar.h>
70 #include <net/sppp/if_sppp.h>
74 #include <machine/md_var.h>
76 #include <dev/netif/ic_layer/hd64570.h>
77 #include <dev/netif/ar/if_arregs.h>
87 #define PPP_HEADER_LEN 4
89 devclass_t ar_devclass;
95 int unit; /* With regards to all ar devices */
96 int subunit; /* With regards to this card */
100 u_int txdesc; /* On card address */
101 u_int txstart; /* On card address */
102 u_int txend; /* On card address */
103 u_int txtail; /* Index of first unused buffer */
104 u_int txmax; /* number of usable buffers/descriptors */
105 u_int txeda; /* Error descriptor addresses */
106 }block[AR_TX_BLOCKS];
108 char xmit_busy; /* Transmitter is busy */
109 char txb_inuse; /* Number of tx blocks currently in use */
110 u_char txb_new; /* Index to where new buffer will be added */
111 u_char txb_next_tx; /* Index to next block ready to tx */
113 u_int rxdesc; /* On card address */
114 u_int rxstart; /* On card address */
115 u_int rxend; /* On card address */
116 u_int rxhind; /* Index to the head of the rx buffers. */
117 u_int rxmax; /* number of usable buffers/descriptors */
123 int running; /* something is attached so we are running */
124 int dcd; /* do we have dcd? */
125 /* ---netgraph bits --- */
126 char nodename[NG_NODESIZ]; /* store our node name */
127 int datahooks; /* number of data hooks attached */
128 node_p node; /* netgraph node */
129 hook_p hook; /* data hook */
131 struct ifqueue xmitq_hipri; /* hi-priority transmit queue */
132 struct ifqueue xmitq; /* transmit queue */
133 int flags; /* state */
134 #define SCF_RUNNING 0x01 /* board is active */
135 #define SCF_OACTIVE 0x02 /* output is active */
136 int out_dog; /* watchdog cycles output count-down */
137 struct callout timer; /* watchdog timer */
138 u_long inbytes, outbytes; /* stats */
139 u_long lastinbytes, lastoutbytes; /* a second ago */
140 u_long inrate, outrate; /* highest rate seen */
141 u_long inlast; /* last input N secs ago */
142 u_long out_deficit; /* output since last input */
143 u_long oerrors, ierrors[6];
144 u_long opackets, ipackets;
145 #endif /* NETGRAPH */
148 static int next_ar_unit = 0;
149 static struct lwkt_serialize ar_serializer;
152 #define DOG_HOLDOFF 6 /* dog holds off for 6 secs */
153 #define QUITE_A_WHILE 300 /* 5 MINUTES */
154 #define LOTS_OF_PACKETS 100
155 #endif /* NETGRAPH */
158 * This translate from irq numbers to
159 * the value that the arnet card needs
160 * in the lower part of the AR_INT_SEL
163 static int irqtable[16] = {
183 DECLARE_DUMMY_MODULE(if_ar);
184 MODULE_DEPEND(if_ar, sppp, 1, 1, 1);
186 MODULE_DEPEND(ng_sync_ar, netgraph, 1, 1, 1);
189 static void arintr(void *arg);
190 static void ar_xmit(struct ar_softc *sc);
192 static void arstart(struct ifnet *ifp);
193 static int arioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *);
194 static void arwatchdog(struct ifnet *ifp);
196 static void arstart(struct ar_softc *sc);
197 static void arwatchdog(struct ar_softc *sc);
198 #endif /* NETGRAPH */
199 static int ar_packet_avail(struct ar_softc *sc, int *len, u_char *rxstat);
200 static void ar_copy_rxbuf(struct mbuf *m, struct ar_softc *sc, int len);
201 static void ar_eat_packet(struct ar_softc *sc, int single);
202 static void ar_get_packets(struct ar_softc *sc);
204 static int ar_read_pim_iface(volatile struct ar_hardc *hc, int channel);
205 static void ar_up(struct ar_softc *sc);
206 static void ar_down(struct ar_softc *sc);
207 static void arc_init(struct ar_hardc *hc);
208 static void ar_init_sca(struct ar_hardc *hc, int scano);
209 static void ar_init_msci(struct ar_softc *sc);
210 static void ar_init_rx_dmac(struct ar_softc *sc);
211 static void ar_init_tx_dmac(struct ar_softc *sc);
212 static void ar_dmac_intr(struct ar_hardc *hc, int scano, u_char isr);
213 static void ar_msci_intr(struct ar_hardc *hc, int scano, u_char isr);
214 static void ar_timer_intr(struct ar_hardc *hc, int scano, u_char isr);
217 static void ngar_watchdog_frame(void * arg);
218 static void ngar_init(void* ignored);
220 static ng_constructor_t ngar_constructor;
221 static ng_rcvmsg_t ngar_rcvmsg;
222 static ng_shutdown_t ngar_shutdown;
223 static ng_newhook_t ngar_newhook;
224 /*static ng_findhook_t ngar_findhook; */
225 static ng_connect_t ngar_connect;
226 static ng_rcvdata_t ngar_rcvdata;
227 static ng_disconnect_t ngar_disconnect;
229 static struct ng_type typestruct = {
245 static int ngar_done_init = 0;
246 #endif /* NETGRAPH */
249 ar_attach(device_t device)
256 #endif /* NETGRAPH */
260 hc = (struct ar_hardc *)device_get_softc(device);
261 lwkt_serialize_init(&ar_serializer);
263 kprintf("arc%d: %uK RAM, %u ports, rev %u.\n",
271 error = BUS_SETUP_INTR(device_get_parent(device), device, hc->res_irq,
273 &hc->intr_cookie, &ar_serializer);
279 for(unit=0;unit<hc->numports;unit+=NCHAN)
280 ar_init_sca(hc, unit / NCHAN);
283 * Now configure each port on the card.
285 for(unit=0;unit<hc->numports;sc++,unit++) {
288 sc->unit = next_ar_unit;
290 sc->scano = unit / NCHAN;
291 sc->scachan = unit%NCHAN;
298 ifp = &sc->ifsppp.pp_if;
301 if_initname(ifp, device_get_name(device), sc->unit);
302 ifp->if_mtu = PP_MTU;
303 ifp->if_flags = IFF_POINTOPOINT | IFF_MULTICAST;
304 ifp->if_ioctl = arioctl;
305 ifp->if_start = arstart;
306 ifp->if_watchdog = arwatchdog;
308 sc->ifsppp.pp_flags = PP_KEEPALIVE;
310 switch(hc->interface[unit]) {
311 default: iface = "UNKNOWN"; break;
312 case AR_IFACE_EIA_232: iface = "EIA-232"; break;
313 case AR_IFACE_V_35: iface = "EIA-232 or V.35"; break;
314 case AR_IFACE_EIA_530: iface = "EIA-530"; break;
315 case AR_IFACE_X_21: iface = "X.21"; break;
316 case AR_IFACE_COMBO: iface = "COMBO X.21 / EIA-530"; break;
319 kprintf("ar%d: Adapter %d, port %d, interface %s.\n",
325 sppp_attach((struct ifnet *)&sc->ifsppp);
326 if_attach(ifp, &ar_serializer);
328 bpfattach(ifp, DLT_PPP, PPP_HEADER_LEN);
331 * we have found a node, make sure our 'type' is availabe.
333 if (ngar_done_init == 0) ngar_init(NULL);
334 if (ng_make_node_common(&typestruct, &sc->node) != 0)
336 ksprintf(sc->nodename, "%s%d", NG_AR_NODE_TYPE, sc->unit);
337 if (ng_name_node(sc->node, sc->nodename)) {
338 NG_NODE_UNREF(sc->node); /* drop it again */
341 NG_NODE_SET_PRIVATE(sc->node, sc);
342 callout_init(&sc->timer);
343 sc->xmitq.ifq_maxlen = IFQ_MAXLEN;
344 sc->xmitq_hipri.ifq_maxlen = IFQ_MAXLEN;
346 #endif /* NETGRAPH */
349 if(hc->bustype == AR_BUS_ISA)
356 ar_detach(device_t device)
358 device_t parent = device_get_parent(device);
359 struct ar_hardc *hc = device_get_softc(device);
362 lwkt_serialize_enter(&ar_serializer);
364 if (hc->intr_cookie != NULL) {
365 if (BUS_TEARDOWN_INTR(parent, device,
366 hc->res_irq, hc->intr_cookie) != 0) {
367 kprintf("intr teardown failed.. continuing\n");
369 hc->intr_cookie = NULL;
373 * deallocate any system resources we may have
374 * allocated on behalf of this driver.
376 FREE(hc->sc, M_DEVBUF);
378 hc->mem_start = NULL;
379 error = ar_deallocate_resources(device);
380 lwkt_serialize_exit(&ar_serializer);
386 ar_allocate_ioport(device_t device, int rid, u_long size)
388 struct ar_hardc *hc = device_get_softc(device);
390 hc->rid_ioport = rid;
391 hc->res_ioport = bus_alloc_resource(device, SYS_RES_IOPORT,
392 &hc->rid_ioport, 0ul, ~0ul, size, RF_ACTIVE);
393 if (hc->res_ioport == NULL) {
396 hc->bt = rman_get_bustag(hc->res_ioport);
397 hc->bh = rman_get_bushandle(hc->res_ioport);
402 ar_deallocate_resources(device);
407 ar_allocate_irq(device_t device, int rid, u_long size)
409 struct ar_hardc *hc = device_get_softc(device);
412 hc->res_irq = bus_alloc_resource_any(device, SYS_RES_IRQ,
413 &hc->rid_irq, RF_SHAREABLE|RF_ACTIVE);
414 if (hc->res_irq == NULL) {
420 ar_deallocate_resources(device);
425 ar_allocate_memory(device_t device, int rid, u_long size)
427 struct ar_hardc *hc = device_get_softc(device);
429 hc->rid_memory = rid;
430 hc->res_memory = bus_alloc_resource(device, SYS_RES_MEMORY,
431 &hc->rid_memory, 0ul, ~0ul, size, RF_ACTIVE);
432 if (hc->res_memory == NULL) {
438 ar_deallocate_resources(device);
443 ar_allocate_plx_memory(device_t device, int rid, u_long size)
445 struct ar_hardc *hc = device_get_softc(device);
447 hc->rid_plx_memory = rid;
448 hc->res_plx_memory = bus_alloc_resource(device, SYS_RES_MEMORY,
449 &hc->rid_plx_memory, 0ul, ~0ul, size, RF_ACTIVE);
450 if (hc->res_plx_memory == NULL) {
456 ar_deallocate_resources(device);
461 ar_deallocate_resources(device_t device)
463 struct ar_hardc *hc = device_get_softc(device);
465 if (hc->res_irq != 0) {
466 bus_deactivate_resource(device, SYS_RES_IRQ,
467 hc->rid_irq, hc->res_irq);
468 bus_release_resource(device, SYS_RES_IRQ,
469 hc->rid_irq, hc->res_irq);
472 if (hc->res_ioport != 0) {
473 bus_deactivate_resource(device, SYS_RES_IOPORT,
474 hc->rid_ioport, hc->res_ioport);
475 bus_release_resource(device, SYS_RES_IOPORT,
476 hc->rid_ioport, hc->res_ioport);
479 if (hc->res_memory != 0) {
480 bus_deactivate_resource(device, SYS_RES_MEMORY,
481 hc->rid_memory, hc->res_memory);
482 bus_release_resource(device, SYS_RES_MEMORY,
483 hc->rid_memory, hc->res_memory);
486 if (hc->res_plx_memory != 0) {
487 bus_deactivate_resource(device, SYS_RES_MEMORY,
488 hc->rid_plx_memory, hc->res_plx_memory);
489 bus_release_resource(device, SYS_RES_MEMORY,
490 hc->rid_plx_memory, hc->res_plx_memory);
491 hc->res_plx_memory = 0;
497 * First figure out which SCA gave the interrupt.
499 * See if there is other interrupts pending.
500 * Repeat until there is no more interrupts.
505 struct ar_hardc *hc = (struct ar_hardc *)arg;
507 u_char isr0, isr1, isr2, arisr;
510 /* XXX Use the PCI interrupt score board register later */
511 if(hc->bustype == AR_BUS_PCI)
512 arisr = hc->orbase[AR_ISTAT * 4];
514 arisr = ar_inb(hc, AR_ISTAT);
516 while(arisr & AR_BD_INT) {
517 TRC(kprintf("arisr = %x\n", arisr));
520 else if(arisr & AR_INT_1)
523 /* XXX Oops this shouldn't happen. */
524 kprintf("arc%d: Interrupted with no interrupt.\n",
528 sca = hc->sca[scano];
530 if(hc->bustype == AR_BUS_ISA)
531 ARC_SET_SCA(hc, scano);
537 TRC(kprintf("arc%d: ARINTR isr0 %x, isr1 %x, isr2 %x\n",
543 ar_msci_intr(hc, scano, isr0);
546 ar_dmac_intr(hc, scano, isr1);
549 ar_timer_intr(hc, scano, isr2);
552 * Proccess the second sca's interrupt if available.
553 * Else see if there are any new interrupts.
555 if((arisr & AR_INT_0) && (arisr & AR_INT_1))
558 if(hc->bustype == AR_BUS_PCI)
559 arisr = hc->orbase[AR_ISTAT * 4];
561 arisr = ar_inb(hc, AR_ISTAT);
565 if(hc->bustype == AR_BUS_ISA)
571 * This will only start the transmitter. It is assumed that the data
572 * is already there. It is normally called from arstart() or ar_dmac_intr().
576 ar_xmit(struct ar_softc *sc)
580 #endif /* NETGRAPH */
584 ifp = &sc->ifsppp.pp_if;
585 #endif /* NETGRAPH */
586 dmac = &sc->sca->dmac[DMAC_TXCH(sc->scachan)];
588 if(sc->hc->bustype == AR_BUS_ISA)
589 ARC_SET_SCA(sc->hc, sc->scano);
590 dmac->cda = (u_short)(sc->block[sc->txb_next_tx].txdesc & 0xffff);
592 dmac->eda = (u_short)(sc->block[sc->txb_next_tx].txeda & 0xffff);
593 dmac->dsr = SCA_DSR_DE;
598 if(sc->txb_next_tx == AR_TX_BLOCKS)
602 ifp->if_timer = 2; /* Value in seconds. */
604 sc->out_dog = DOG_HOLDOFF; /* give ourself some breathing space*/
605 #endif /* NETGRAPH */
606 if(sc->hc->bustype == AR_BUS_ISA)
611 * This function will be called from the upper level when a user add a
612 * packet to be send, and from the interrupt handler after a finished
615 * This function only place the data in the oncard buffers. It does not
616 * start the transmition. ar_xmit() does that.
618 * Transmitter idle state is indicated by the IFF_OACTIVE flag. The function
619 * that clears that should ensure that the transmitter and its DMA is
620 * in a "good" idle state.
624 arstart(struct ifnet *ifp)
626 struct ar_softc *sc = ifp->if_softc;
629 arstart(struct ar_softc *sc)
631 #endif /* NETGRAPH */
635 sca_descriptor *txdesc;
636 struct buf_block *blkp;
639 if(!(ifp->if_flags & IFF_RUNNING))
643 #endif /* NETGRAPH */
648 * See if we have space for more packets.
650 if(sc->txb_inuse == AR_TX_BLOCKS) {
652 ifp->if_flags |= IFF_OACTIVE; /* yes, mark active */
654 /*XXX*/ /*ifp->if_flags |= IFF_OACTIVE;*/ /* yes, mark active */
655 #endif /* NETGRAPH */
660 mtx = sppp_dequeue(ifp);
662 IF_DEQUEUE(&sc->xmitq_hipri, mtx);
664 IF_DEQUEUE(&sc->xmitq, mtx);
666 #endif /* NETGRAPH */
671 * It is OK to set the memory window outside the loop because
672 * all tx buffers and descriptors are assumed to be in the same
675 if(sc->hc->bustype == AR_BUS_ISA)
676 ARC_SET_MEM(sc->hc, sc->block[0].txdesc);
679 * We stay in this loop until there is nothing in the
680 * TX queue left or the tx buffer is full.
683 blkp = &sc->block[sc->txb_new];
684 txdesc = (sca_descriptor *)
685 (sc->hc->mem_start + (blkp->txdesc & sc->hc->winmsk));
686 txdata = (u_char *)(sc->hc->mem_start + (blkp->txstart & sc->hc->winmsk));
688 len = mtx->m_pkthdr.len;
690 TRC(kprintf("ar%d: ARstart len %u\n", sc->unit, len));
693 * We can do this because the tx buffers don't wrap.
695 m_copydata(mtx, 0, len, txdata);
697 while(tlen > AR_BUF_SIZ) {
699 txdesc->len = AR_BUF_SIZ;
702 txdata += AR_BUF_SIZ;
705 /* XXX Move into the loop? */
706 txdesc->stat = SCA_DESC_EOM;
709 txdata += AR_BUF_SIZ;
715 ++sc->ifsppp.pp_if.if_opackets;
720 #endif /* NETGRAPH */
723 * Check if we have space for another mbuf.
724 * XXX This is hardcoded. A packet won't be larger
725 * than 3 buffers (3 x 512).
727 if((i + 3) >= blkp->txmax)
731 mtx = sppp_dequeue(ifp);
733 IF_DEQUEUE(&sc->xmitq_hipri, mtx);
735 IF_DEQUEUE(&sc->xmitq, mtx);
737 #endif /* NETGRAPH */
745 * Mark the last descriptor, so that the SCA know where
749 txdesc->stat |= SCA_DESC_EOT;
751 txdesc = (sca_descriptor *)blkp->txdesc;
752 blkp->txeda = (u_short)((u_int)&txdesc[i]);
755 kprintf("ARstart: %p desc->cp %x\n", &txdesc->cp, txdesc->cp);
756 kprintf("ARstart: %p desc->bp %x\n", &txdesc->bp, txdesc->bp);
757 kprintf("ARstart: %p desc->bpb %x\n", &txdesc->bpb, txdesc->bpb);
758 kprintf("ARstart: %p desc->len %x\n", &txdesc->len, txdesc->len);
759 kprintf("ARstart: %p desc->stat %x\n", &txdesc->stat, txdesc->stat);
764 if(sc->txb_new == AR_TX_BLOCKS)
767 if(sc->xmit_busy == 0)
770 if(sc->hc->bustype == AR_BUS_ISA)
778 arioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
781 int was_up, should_be_up;
782 struct ar_softc *sc = ifp->if_softc;
784 TRC(if_printf(ifp, "arioctl.\n");)
786 was_up = ifp->if_flags & IFF_RUNNING;
788 error = sppp_ioctl(ifp, cmd, data);
789 TRC(if_printf(ifp, "ioctl: ifsppp.pp_flags = %x, if_flags %x.\n",
790 ((struct sppp *)ifp)->pp_flags, ifp->if_flags);)
794 if((cmd != SIOCSIFFLAGS) && cmd != (SIOCSIFADDR))
797 TRC(if_printf(ifp, "arioctl %s.\n",
798 (cmd == SIOCSIFFLAGS) ? "SIOCSIFFLAGS" : "SIOCSIFADDR");)
800 should_be_up = ifp->if_flags & IFF_RUNNING;
802 if(!was_up && should_be_up) {
803 /* Interface should be up -- start it. */
806 /* XXX Maybe clear the IFF_UP flag so that the link
807 * will only go up after sppp lcp and ipcp negotiation.
809 } else if(was_up && !should_be_up) {
810 /* Interface should be down -- stop it. */
816 #endif /* NETGRAPH */
819 * This is to catch lost tx interrupts.
823 arwatchdog(struct ifnet *ifp)
825 struct ar_softc *sc = ifp->if_softc;
827 arwatchdog(struct ar_softc *sc)
829 #endif /* NETGRAPH */
830 msci_channel *msci = &sc->sca->msci[sc->scachan];
833 if(!(ifp->if_flags & IFF_RUNNING))
835 #endif /* NETGRAPH */
837 if(sc->hc->bustype == AR_BUS_ISA)
838 ARC_SET_SCA(sc->hc, sc->scano);
840 /* XXX if(sc->ifsppp.pp_if.if_flags & IFF_DEBUG) */
841 kprintf("ar%d: transmit failed, "
842 "ST0 %x, ST1 %x, ST3 %x, DSR %x.\n",
847 sc->sca->dmac[DMAC_TXCH(sc->scachan)].dsr);
849 if(msci->st1 & SCA_ST1_UDRN) {
850 msci->cmd = SCA_CMD_TXABORT;
851 msci->cmd = SCA_CMD_TXENABLE;
852 msci->st1 = SCA_ST1_UDRN;
857 ifp->if_flags &= ~IFF_OACTIVE;
859 /* XXX ifp->if_flags &= ~IFF_OACTIVE; */
860 #endif /* NETGRAPH */
862 if(sc->txb_inuse && --sc->txb_inuse)
869 #endif /* NETGRAPH */
873 ar_up(struct ar_softc *sc)
879 msci = &sca->msci[sc->scachan];
881 TRC(kprintf("ar%d: sca %p, msci %p, ch %d\n",
882 sc->unit, sca, msci, sc->scachan));
885 * Enable transmitter and receiver.
889 if(sc->hc->bustype == AR_BUS_ISA)
890 ARC_SET_SCA(sc->hc, sc->scano);
893 * What about using AUTO mode in msci->md0 ???
894 * And what about CTS/DCD etc... ?
896 if(sc->hc->handshake & AR_SHSK_RTS)
897 msci->ctl &= ~SCA_CTL_RTS;
898 if(sc->hc->handshake & AR_SHSK_DTR) {
899 sc->hc->txc_dtr[sc->scano] &= sc->scachan ?
900 ~AR_TXC_DTR_DTR1 : ~AR_TXC_DTR_DTR0;
901 if(sc->hc->bustype == AR_BUS_PCI)
902 sc->hc->orbase[sc->hc->txc_dtr_off[sc->scano]] =
903 sc->hc->txc_dtr[sc->scano];
905 ar_outb(sc->hc, sc->hc->txc_dtr_off[sc->scano],
906 sc->hc->txc_dtr[sc->scano]);
909 if(sc->scachan == 0) {
917 msci->cmd = SCA_CMD_RXENABLE;
918 if(sc->hc->bustype == AR_BUS_ISA)
919 ar_inb(sc->hc, AR_ID_5); /* XXX slow it down a bit. */
920 msci->cmd = SCA_CMD_TXENABLE;
922 if(sc->hc->bustype == AR_BUS_ISA)
925 callout_reset(&sc->timer, hz, ngar_watchdog_frame, sc);
927 #endif /* NETGRAPH */
931 ar_down(struct ar_softc *sc)
937 msci = &sca->msci[sc->scachan];
940 callout_stop(&sc->timer);
942 #endif /* NETGRAPH */
944 * Disable transmitter and receiver.
946 * Disable interrupts.
948 if(sc->hc->bustype == AR_BUS_ISA)
949 ARC_SET_SCA(sc->hc, sc->scano);
950 msci->cmd = SCA_CMD_RXDISABLE;
951 if(sc->hc->bustype == AR_BUS_ISA)
952 ar_inb(sc->hc, AR_ID_5); /* XXX slow it down a bit. */
953 msci->cmd = SCA_CMD_TXDISABLE;
955 if(sc->hc->handshake & AR_SHSK_RTS)
956 msci->ctl |= SCA_CTL_RTS;
957 if(sc->hc->handshake & AR_SHSK_DTR) {
958 sc->hc->txc_dtr[sc->scano] |= sc->scachan ?
959 AR_TXC_DTR_DTR1 : AR_TXC_DTR_DTR0;
960 if(sc->hc->bustype == AR_BUS_PCI)
961 sc->hc->orbase[sc->hc->txc_dtr_off[sc->scano]] =
962 sc->hc->txc_dtr[sc->scano];
964 ar_outb(sc->hc, sc->hc->txc_dtr_off[sc->scano],
965 sc->hc->txc_dtr[sc->scano]);
968 if(sc->scachan == 0) {
976 if(sc->hc->bustype == AR_BUS_ISA)
981 ar_read_pim_iface(volatile struct ar_hardc *hc, int channel)
983 int ctype, i, val, x;
984 volatile u_char *pimctrl;
989 pimctrl = hc->orbase + AR_PIMCTRL;
993 *pimctrl = AR_PIM_STROBE;
995 /* Check if there is a PIM */
997 *pimctrl = AR_PIM_READ;
999 TRC(kprintf("x = %x", x));
1000 if(x & AR_PIM_DATA) {
1001 kprintf("No PIM installed\n");
1002 return (AR_IFACE_UNKNOWN);
1005 x = (x >> 1) & 0x01;
1008 /* Now read the next 15 bits */
1009 for(i = 1; i < 16; i++) {
1010 *pimctrl = AR_PIM_READ;
1011 *pimctrl = AR_PIM_READ | AR_PIM_STROBE;
1013 TRC(kprintf(" %x ", x));
1014 x = (x >> 1) & 0x01;
1016 if(i == 8 && (val & 0x000f) == 0x0004) {
1020 *pimctrl = AR_PIM_A2D_DOUT | AR_PIM_A2D_STROBE;
1021 *pimctrl = AR_PIM_A2D_DOUT;
1024 *pimctrl = AR_PIM_A2D_DOUT | AR_PIM_A2D_STROBE;
1025 *pimctrl = AR_PIM_A2D_DOUT;
1028 *pimctrl = AR_PIM_A2D_DOUT | AR_PIM_A2D_STROBE;
1029 *pimctrl = AR_PIM_A2D_DOUT;
1031 /* Select channel */
1032 *pimctrl = AR_PIM_A2D_STROBE | ((channel & 2) << 2);
1033 *pimctrl = ((channel & 2) << 2);
1034 *pimctrl = AR_PIM_A2D_STROBE | ((channel & 1) << 3);
1035 *pimctrl = ((channel & 1) << 3);
1037 *pimctrl = AR_PIM_A2D_STROBE;
1041 kprintf("\nOops A2D start bit not zero (%X)\n", x);
1043 for(ii = 7; ii >= 0; ii--) {
1045 *pimctrl = AR_PIM_A2D_STROBE;
1052 TRC(kprintf("\nPIM val %x, ctype %x, %d\n", val, ctype, ctype));
1053 *pimctrl = AR_PIM_MODEG;
1054 *pimctrl = AR_PIM_MODEG | AR_PIM_AUTO_LED;
1056 return (AR_IFACE_UNKNOWN);
1058 return (AR_IFACE_V_35);
1060 return (AR_IFACE_EIA_232);
1062 return (AR_IFACE_X_21);
1064 return (AR_IFACE_EIA_530);
1066 return (AR_IFACE_UNKNOWN);
1068 return (AR_IFACE_LOOPBACK);
1069 return (AR_IFACE_UNKNOWN);
1073 * Initialize the card, allocate memory for the ar_softc structures
1074 * and fill in the pointers.
1077 arc_init(struct ar_hardc *hc)
1079 struct ar_softc *sc;
1088 MALLOC(sc, struct ar_softc *, hc->numports * sizeof(struct ar_softc),
1089 M_DEVBUF, M_WAITOK | M_ZERO);
1094 hc->txc_dtr[0] = AR_TXC_DTR_NOTRESET |
1095 AR_TXC_DTR_DTR0 | AR_TXC_DTR_DTR1;
1096 hc->txc_dtr[1] = AR_TXC_DTR_DTR0 | AR_TXC_DTR_DTR1;
1097 hc->txc_dtr_off[0] = AR_TXC_DTR0;
1098 hc->txc_dtr_off[1] = AR_TXC_DTR2;
1099 if(hc->bustype == AR_BUS_PCI) {
1100 hc->txc_dtr_off[0] *= 4;
1101 hc->txc_dtr_off[1] *= 4;
1105 * reset the card and wait at least 1uS.
1107 if(hc->bustype == AR_BUS_PCI)
1108 hc->orbase[AR_TXC_DTR0 * 4] = ~AR_TXC_DTR_NOTRESET &
1111 ar_outb(hc, AR_TXC_DTR0, ~AR_TXC_DTR_NOTRESET &
1114 if(hc->bustype == AR_BUS_PCI)
1115 hc->orbase[AR_TXC_DTR0 * 4] = hc->txc_dtr[0];
1117 ar_outb(hc, AR_TXC_DTR0, hc->txc_dtr[0]);
1119 if(hc->bustype == AR_BUS_ISA) {
1121 * Configure the card.
1124 memst = rman_get_start(hc->res_memory);
1126 isr = irqtable[hc->isa_irq] << 1;
1128 kprintf("ar%d: Warning illegal interrupt %d\n",
1129 hc->cunit, hc->isa_irq);
1130 isr = isr | ((memst & 0xc000) >> 10);
1132 hc->sca[0] = (sca_regs *)hc->mem_start;
1133 hc->sca[1] = (sca_regs *)hc->mem_start;
1135 ar_outb(hc, AR_MEM_SEL, mar);
1136 ar_outb(hc, AR_INT_SEL, isr | AR_INTS_CEN);
1139 if(hc->bustype == AR_BUS_PCI && hc->interface[0] == AR_IFACE_PIM)
1140 for(x = 0; x < hc->numports; x++)
1141 hc->interface[x] = ar_read_pim_iface(hc, x);
1144 * Set the TX clock direction and enable TX.
1146 for(x=0;x<hc->numports;x++) {
1147 switch(hc->interface[x]) {
1149 hc->txc_dtr[x / NCHAN] |= (x % NCHAN == 0) ?
1150 AR_TXC_DTR_TX0 : AR_TXC_DTR_TX1;
1151 hc->txc_dtr[x / NCHAN] |= (x % NCHAN == 0) ?
1152 AR_TXC_DTR_TXCS0 : AR_TXC_DTR_TXCS1;
1154 case AR_IFACE_EIA_530:
1155 case AR_IFACE_COMBO:
1157 hc->txc_dtr[x / NCHAN] |= (x % NCHAN == 0) ?
1158 AR_TXC_DTR_TX0 : AR_TXC_DTR_TX1;
1163 if(hc->bustype == AR_BUS_PCI)
1164 hc->orbase[AR_TXC_DTR0 * 4] = hc->txc_dtr[0];
1166 ar_outb(hc, AR_TXC_DTR0, hc->txc_dtr[0]);
1167 if(hc->numports > NCHAN) {
1168 if(hc->bustype == AR_BUS_PCI)
1169 hc->orbase[AR_TXC_DTR2 * 4] = hc->txc_dtr[1];
1171 ar_outb(hc, AR_TXC_DTR2, hc->txc_dtr[1]);
1174 chanmem = hc->memsize / hc->numports;
1177 for(x=0;x<hc->numports;x++, sc++) {
1180 sc->sca = hc->sca[x / NCHAN];
1182 for(blk = 0; blk < AR_TX_BLOCKS; blk++) {
1183 sc->block[blk].txdesc = next;
1184 bufmem = (16 * 1024) / AR_TX_BLOCKS;
1185 descneeded = bufmem / AR_BUF_SIZ;
1186 sc->block[blk].txstart = sc->block[blk].txdesc +
1187 ((((descneeded * sizeof(sca_descriptor)) /
1188 AR_BUF_SIZ) + 1) * AR_BUF_SIZ);
1189 sc->block[blk].txend = next + bufmem;
1190 sc->block[blk].txmax =
1191 (sc->block[blk].txend - sc->block[blk].txstart)
1195 TRC(kprintf("ar%d: blk %d: txdesc %x, txstart %x, "
1196 "txend %x, txmax %d\n",
1199 sc->block[blk].txdesc,
1200 sc->block[blk].txstart,
1201 sc->block[blk].txend,
1202 sc->block[blk].txmax));
1206 bufmem = chanmem - (bufmem * AR_TX_BLOCKS);
1207 descneeded = bufmem / AR_BUF_SIZ;
1208 sc->rxstart = sc->rxdesc +
1209 ((((descneeded * sizeof(sca_descriptor)) /
1210 AR_BUF_SIZ) + 1) * AR_BUF_SIZ);
1211 sc->rxend = next + bufmem;
1212 sc->rxmax = (sc->rxend - sc->rxstart) / AR_BUF_SIZ;
1214 TRC(kprintf("ar%d: rxdesc %x, rxstart %x, "
1215 "rxend %x, rxmax %d\n",
1216 x, sc->rxdesc, sc->rxstart, sc->rxend, sc->rxmax));
1219 if(hc->bustype == AR_BUS_PCI)
1220 hc->orbase[AR_PIMCTRL] = AR_PIM_MODEG | AR_PIM_AUTO_LED;
1225 * The things done here are channel independent.
1227 * Configure the sca waitstates.
1228 * Configure the global interrupt registers.
1229 * Enable master dma enable.
1232 ar_init_sca(struct ar_hardc *hc, int scano)
1236 sca = hc->sca[scano];
1237 if(hc->bustype == AR_BUS_ISA)
1238 ARC_SET_SCA(hc, scano);
1241 * Do the wait registers.
1242 * Set everything to 0 wait states.
1251 * Configure the interrupt registers.
1252 * Most are cleared until the interface is configured.
1254 sca->ier0 = 0x00; /* MSCI interrupts... Not used with dma. */
1255 sca->ier1 = 0x00; /* DMAC interrupts */
1256 sca->ier2 = 0x00; /* TIMER interrupts... Not used yet. */
1257 sca->itcr = 0x00; /* Use ivr and no intr ack */
1258 sca->ivr = 0x40; /* Fill in the interrupt vector. */
1262 * Configure the timers.
1268 * Set the DMA channel priority to rotate between
1269 * all four channels.
1271 * Enable all dma channels.
1273 if(hc->bustype == AR_BUS_PCI) {
1277 * Stupid problem with the PCI interface chip that break
1282 t[AR_PCI_SCA_PCR] = SCA_PCR_PR2;
1283 t[AR_PCI_SCA_DMER] = SCA_DMER_EN;
1285 sca->pcr = SCA_PCR_PR2;
1286 sca->dmer = SCA_DMER_EN;
1292 * Configure the msci
1294 * NOTE: The serial port configuration is hardcoded at the moment.
1297 ar_init_msci(struct ar_softc *sc)
1301 msci = &sc->sca->msci[sc->scachan];
1303 if(sc->hc->bustype == AR_BUS_ISA)
1304 ARC_SET_SCA(sc->hc, sc->scano);
1306 msci->cmd = SCA_CMD_RESET;
1308 msci->md0 = SCA_MD0_CRC_1 |
1310 SCA_MD0_CRC_ENABLE |
1312 msci->md1 = SCA_MD1_NOADDRCHK;
1313 msci->md2 = SCA_MD2_DUPLEX | SCA_MD2_NRZ;
1316 * Acording to the manual I should give a reset after changing the
1319 msci->cmd = SCA_CMD_RXRESET;
1320 msci->ctl = SCA_CTL_IDLPAT | SCA_CTL_UDRNC | SCA_CTL_RTS;
1323 * For now all interfaces are programmed to use the RX clock for
1326 switch(sc->hc->interface[sc->subunit]) {
1328 msci->rxs = SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1;
1329 msci->txs = SCA_TXS_CLK_TXC | SCA_TXS_DIV1;
1332 case AR_IFACE_EIA_530:
1333 case AR_IFACE_COMBO:
1334 msci->rxs = SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1;
1335 msci->txs = SCA_TXS_CLK_RX | SCA_TXS_DIV1;
1338 msci->tmc = 153; /* This give 64k for loopback */
1341 * Disable all interrupts for now. I think if you are using
1342 * the dmac you don't use these interrupts.
1345 msci->ie1 = 0x0C; /* XXX CTS and DCD (DSR on 570I) level change. */
1352 msci->idl = 0x7E; /* XXX This is what cisco does. */
1355 * This is what the ARNET diags use.
1363 * Configure the rx dma controller.
1366 ar_init_rx_dmac(struct ar_softc *sc)
1369 sca_descriptor *rxd;
1375 dmac = &sc->sca->dmac[DMAC_RXCH(sc->scachan)];
1377 if(sc->hc->bustype == AR_BUS_ISA)
1378 ARC_SET_MEM(sc->hc, sc->rxdesc);
1380 rxd = (sca_descriptor *)(sc->hc->mem_start + (sc->rxdesc&sc->hc->winmsk));
1381 rxda_d = (u_int)sc->hc->mem_start - (sc->rxdesc & ~sc->hc->winmsk);
1383 for(rxbuf=sc->rxstart;rxbuf<sc->rxend;rxbuf += AR_BUF_SIZ, rxd++) {
1384 rxda = (u_int)&rxd[1] - rxda_d;
1385 rxd->cp = (u_short)(rxda & 0xfffful);
1389 TRC(kprintf("Descrp %p, data pt %x, data %x, ",
1392 rxd->bp = (u_short)(rxbuf & 0xfffful);
1393 rxd->bpb = (u_char)((rxbuf >> 16) & 0xff);
1395 rxd->stat = 0xff; /* The sca write here when it is finished. */
1398 TRC(kprintf("bpb %x, bp %x.\n", rxd->bpb, rxd->bp));
1401 rxd->cp = (u_short)(sc->rxdesc & 0xfffful);
1405 if(sc->hc->bustype == AR_BUS_ISA)
1406 ARC_SET_SCA(sc->hc, sc->scano);
1408 dmac->dsr = 0; /* Disable DMA transfer */
1409 dmac->dcr = SCA_DCR_ABRT;
1411 /* XXX maybe also SCA_DMR_CNTE */
1412 dmac->dmr = SCA_DMR_TMOD | SCA_DMR_NF;
1413 dmac->bfl = AR_BUF_SIZ;
1415 dmac->cda = (u_short)(sc->rxdesc & 0xffff);
1416 dmac->sarb = (u_char)((sc->rxdesc >> 16) & 0xff);
1418 rxd = (sca_descriptor *)sc->rxstart;
1419 dmac->eda = (u_short)((u_int)&rxd[sc->rxmax - 1] & 0xffff);
1423 dmac->dsr = SCA_DSR_DE;
1427 * Configure the TX DMA descriptors.
1428 * Initialize the needed values and chain the descriptors.
1431 ar_init_tx_dmac(struct ar_softc *sc)
1434 struct buf_block *blkp;
1436 sca_descriptor *txd;
1441 dmac = &sc->sca->dmac[DMAC_TXCH(sc->scachan)];
1443 if(sc->hc->bustype == AR_BUS_ISA)
1444 ARC_SET_MEM(sc->hc, sc->block[0].txdesc);
1446 for(blk = 0; blk < AR_TX_BLOCKS; blk++) {
1447 blkp = &sc->block[blk];
1448 txd = (sca_descriptor *)(sc->hc->mem_start +
1449 (blkp->txdesc&sc->hc->winmsk));
1450 txda_d = (u_int)sc->hc->mem_start -
1451 (blkp->txdesc & ~sc->hc->winmsk);
1453 txbuf=blkp->txstart;
1454 for(;txbuf<blkp->txend;txbuf += AR_BUF_SIZ, txd++) {
1455 txda = (u_int)&txd[1] - txda_d;
1456 txd->cp = (u_short)(txda & 0xfffful);
1458 txd->bp = (u_short)(txbuf & 0xfffful);
1459 txd->bpb = (u_char)((txbuf >> 16) & 0xff);
1460 TRC(kprintf("ar%d: txbuf %x, bpb %x, bp %x\n",
1461 sc->unit, txbuf, txd->bpb, txd->bp));
1466 txd->cp = (u_short)(blkp->txdesc & 0xfffful);
1468 blkp->txtail = (u_int)txd - (u_int)sc->hc->mem_start;
1469 TRC(kprintf("TX Descriptors start %x, end %x.\n",
1474 if(sc->hc->bustype == AR_BUS_ISA)
1475 ARC_SET_SCA(sc->hc, sc->scano);
1477 dmac->dsr = 0; /* Disable DMA */
1478 dmac->dcr = SCA_DCR_ABRT;
1479 dmac->dmr = SCA_DMR_TMOD | SCA_DMR_NF;
1480 dmac->dir = SCA_DIR_EOT | SCA_DIR_BOF | SCA_DIR_COF;
1482 dmac->sarb = (u_char)((sc->block[0].txdesc >> 16) & 0xff);
1487 * Look through the descriptors to see if there is a complete packet
1488 * available. Stop if we get to where the sca is busy.
1490 * Return the length and status of the packet.
1491 * Return nonzero if there is a packet available.
1494 * It seems that we get the interrupt a bit early. The updateing of
1495 * descriptor values is not always completed when this is called.
1498 ar_packet_avail(struct ar_softc *sc,
1503 sca_descriptor *rxdesc;
1504 sca_descriptor *endp;
1505 sca_descriptor *cda;
1507 if(sc->hc->bustype == AR_BUS_ISA)
1508 ARC_SET_SCA(sc->hc, sc->scano);
1509 dmac = &sc->sca->dmac[DMAC_RXCH(sc->scachan)];
1510 cda = (sca_descriptor *)(sc->hc->mem_start +
1511 ((((u_int)dmac->sarb << 16) + dmac->cda) & sc->hc->winmsk));
1513 if(sc->hc->bustype == AR_BUS_ISA)
1514 ARC_SET_MEM(sc->hc, sc->rxdesc);
1515 rxdesc = (sca_descriptor *)
1516 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1518 rxdesc = &rxdesc[sc->rxhind];
1519 endp = &endp[sc->rxmax];
1523 while(rxdesc != cda) {
1524 *len += rxdesc->len;
1526 if(rxdesc->stat & SCA_DESC_EOM) {
1527 *rxstat = rxdesc->stat;
1528 TRC(kprintf("ar%d: PKT AVAIL len %d, %x.\n",
1529 sc->unit, *len, *rxstat));
1535 rxdesc = (sca_descriptor *)
1536 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1546 * Copy a packet from the on card memory into a provided mbuf.
1547 * Take into account that buffers wrap and that a packet may
1548 * be larger than a buffer.
1551 ar_copy_rxbuf(struct mbuf *m,
1552 struct ar_softc *sc,
1555 sca_descriptor *rxdesc;
1561 rxdata = sc->rxstart + (sc->rxhind * AR_BUF_SIZ);
1562 rxmax = sc->rxstart + (sc->rxmax * AR_BUF_SIZ);
1564 rxdesc = (sca_descriptor *)
1565 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1566 rxdesc = &rxdesc[sc->rxhind];
1569 tlen = (len < AR_BUF_SIZ) ? len : AR_BUF_SIZ;
1570 if(sc->hc->bustype == AR_BUS_ISA)
1571 ARC_SET_MEM(sc->hc, rxdata);
1572 bcopy(sc->hc->mem_start + (rxdata & sc->hc->winmsk),
1573 mtod(m, caddr_t) + off,
1579 if(sc->hc->bustype == AR_BUS_ISA)
1580 ARC_SET_MEM(sc->hc, sc->rxdesc);
1582 rxdesc->stat = 0xff;
1584 rxdata += AR_BUF_SIZ;
1586 if(rxdata == rxmax) {
1587 rxdata = sc->rxstart;
1588 rxdesc = (sca_descriptor *)
1589 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1595 * If single is set, just eat a packet. Otherwise eat everything up to
1596 * where cda points. Update pointers to point to the next packet.
1599 ar_eat_packet(struct ar_softc *sc, int single)
1602 sca_descriptor *rxdesc;
1603 sca_descriptor *endp;
1604 sca_descriptor *cda;
1608 if(sc->hc->bustype == AR_BUS_ISA)
1609 ARC_SET_SCA(sc->hc, sc->scano);
1610 dmac = &sc->sca->dmac[DMAC_RXCH(sc->scachan)];
1611 cda = (sca_descriptor *)(sc->hc->mem_start +
1612 ((((u_int)dmac->sarb << 16) + dmac->cda) & sc->hc->winmsk));
1615 * Loop until desc->stat == (0xff || EOM)
1616 * Clear the status and length in the descriptor.
1617 * Increment the descriptor.
1619 if(sc->hc->bustype == AR_BUS_ISA)
1620 ARC_SET_MEM(sc->hc, sc->rxdesc);
1621 rxdesc = (sca_descriptor *)
1622 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1624 rxdesc = &rxdesc[sc->rxhind];
1625 endp = &endp[sc->rxmax];
1627 while(rxdesc != cda) {
1629 if(loopcnt > sc->rxmax) {
1630 kprintf("ar%d: eat pkt %d loop, cda %p, "
1631 "rxdesc %p, stat %x.\n",
1640 stat = rxdesc->stat;
1643 rxdesc->stat = 0xff;
1647 if(rxdesc == endp) {
1648 rxdesc = (sca_descriptor *)
1649 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1653 if(single && (stat == SCA_DESC_EOM))
1658 * Update the eda to the previous descriptor.
1660 if(sc->hc->bustype == AR_BUS_ISA)
1661 ARC_SET_SCA(sc->hc, sc->scano);
1663 rxdesc = (sca_descriptor *)sc->rxdesc;
1664 rxdesc = &rxdesc[(sc->rxhind + sc->rxmax - 2 ) % sc->rxmax];
1666 sc->sca->dmac[DMAC_RXCH(sc->scachan)].eda =
1667 (u_short)((u_int)rxdesc & 0xffff);
1672 * While there is packets available in the rx buffer, read them out
1673 * into mbufs and ship them off.
1676 ar_get_packets(struct ar_softc *sc)
1678 sca_descriptor *rxdesc;
1679 struct mbuf *m = NULL;
1687 while(ar_packet_avail(sc, &len, &rxstat)) {
1688 TRC(kprintf("apa: len %d, rxstat %x\n", len, rxstat));
1689 if(((rxstat & SCA_DESC_ERRORS) == 0) && (len < MCLBYTES)) {
1690 m = m_getl(len, MB_DONTWAIT, MT_DATA, M_PKTHDR, NULL);
1692 /* eat packet if get mbuf fail!! */
1693 ar_eat_packet(sc, 1);
1697 m->m_pkthdr.rcvif = NULL;
1701 m->m_pkthdr.rcvif = &sc->ifsppp.pp_if;
1703 m->m_pkthdr.len = m->m_len = len;
1704 ar_copy_rxbuf(m, sc, len);
1706 NG_SEND_DATA_ONLY(error, sc->hook, m);
1709 BPF_MTAP(&sc->ifsppp.pp_if, m);
1710 sppp_input(&sc->ifsppp.pp_if, m);
1711 sc->ifsppp.pp_if.if_ipackets++;
1714 * Update the eda to the previous descriptor.
1716 i = (len + AR_BUF_SIZ - 1) / AR_BUF_SIZ;
1717 sc->rxhind = (sc->rxhind + i) % sc->rxmax;
1719 if(sc->hc->bustype == AR_BUS_ISA)
1720 ARC_SET_SCA(sc->hc, sc->scano);
1722 rxdesc = (sca_descriptor *)sc->rxdesc;
1724 &rxdesc[(sc->rxhind + sc->rxmax - 2 ) % sc->rxmax];
1726 sc->sca->dmac[DMAC_RXCH(sc->scachan)].eda =
1727 (u_short)((u_int)rxdesc & 0xffff);
1731 while((rxstat == 0xff) && --tries)
1732 ar_packet_avail(sc, &len, &rxstat);
1735 * It look like we get an interrupt early
1736 * sometimes and then the status is not
1739 if(tries && (tries != 5))
1742 ar_eat_packet(sc, 1);
1745 sc->ifsppp.pp_if.if_ierrors++;
1746 #else /* NETGRAPH */
1748 #endif /* NETGRAPH */
1750 if(sc->hc->bustype == AR_BUS_ISA)
1751 ARC_SET_SCA(sc->hc, sc->scano);
1753 TRCL(kprintf("ar%d: Receive error chan %d, "
1754 "stat %x, msci st3 %x,"
1755 "rxhind %d, cda %x, eda %x.\n",
1759 sc->sca->msci[sc->scachan].st3,
1762 DMAC_RXCH(sc->scachan)].cda,
1764 DMAC_RXCH(sc->scachan)].eda));
1771 * All DMA interrupts come here.
1773 * Each channel has two interrupts.
1774 * Interrupt A for errors and Interrupt B for normal stuff like end
1775 * of transmit or receive dmas.
1778 ar_dmac_intr(struct ar_hardc *hc, int scano, u_char isr1)
1781 u_char dotxstart = isr1;
1783 struct ar_softc *sc;
1787 sca = hc->sca[scano];
1790 * Shortcut if there is no interrupts for dma channel 0 or 1
1792 if((isr1 & 0x0F) == 0) {
1798 sc = &hc->sc[mch + (NCHAN * scano)];
1804 dmac = &sca->dmac[DMAC_TXCH(mch)];
1806 if(hc->bustype == AR_BUS_ISA)
1807 ARC_SET_SCA(hc, scano);
1812 /* Counter overflow */
1813 if(dsr & SCA_DSR_COF) {
1814 kprintf("ar%d: TX DMA Counter overflow, "
1815 "txpacket no %lu.\n",
1818 sc->ifsppp.pp_if.if_opackets);
1819 sc->ifsppp.pp_if.if_oerrors++;
1820 #else /* NETGRAPH */
1823 #endif /* NETGRAPH */
1826 /* Buffer overflow */
1827 if(dsr & SCA_DSR_BOF) {
1828 kprintf("ar%d: TX DMA Buffer overflow, "
1829 "txpacket no %lu, dsr %02x, "
1830 "cda %04x, eda %04x.\n",
1833 sc->ifsppp.pp_if.if_opackets,
1834 #else /* NETGRAPH */
1836 #endif /* NETGRAPH */
1841 sc->ifsppp.pp_if.if_oerrors++;
1842 #else /* NETGRAPH */
1844 #endif /* NETGRAPH */
1847 /* End of Transfer */
1848 if(dsr & SCA_DSR_EOT) {
1850 * This should be the most common case.
1852 * Clear the IFF_OACTIVE flag.
1854 * Call arstart to start a new transmit if
1855 * there is data to transmit.
1859 sc->ifsppp.pp_if.if_flags &= ~IFF_OACTIVE;
1860 sc->ifsppp.pp_if.if_timer = 0;
1861 #else /* NETGRAPH */
1862 /* XXX c->ifsppp.pp_if.if_flags &= ~IFF_OACTIVE; */
1863 sc->out_dog = 0; /* XXX */
1864 #endif /* NETGRAPH */
1866 if(sc->txb_inuse && --sc->txb_inuse)
1875 dmac = &sca->dmac[DMAC_RXCH(mch)];
1877 if(hc->bustype == AR_BUS_ISA)
1878 ARC_SET_SCA(hc, scano);
1883 TRC(kprintf("AR: RX DSR %x\n", dsr));
1886 if(dsr & SCA_DSR_EOM) {
1887 TRC(int tt = sc->ifsppp.pp_if.if_ipackets;)
1888 TRC(int ind = sc->rxhind;)
1892 #define IPACKETS sc->ifsppp.pp_if.if_ipackets
1893 #else /* NETGRAPH */
1894 #define IPACKETS sc->ipackets
1895 #endif /* NETGRAPH */
1896 TRC(if(tt == IPACKETS) {
1897 sca_descriptor *rxdesc;
1900 if(hc->bustype == AR_BUS_ISA)
1901 ARC_SET_SCA(hc, scano);
1902 kprintf("AR: RXINTR isr1 %x, dsr %x, "
1903 "no data %d pkts, orxhind %d.\n",
1908 kprintf("AR: rxdesc %x, rxstart %x, "
1909 "rxend %x, rxhind %d, "
1916 kprintf("AR: cda %x, eda %x.\n",
1920 if(sc->hc->bustype == AR_BUS_ISA)
1923 rxdesc = (sca_descriptor *)
1924 (sc->hc->mem_start +
1925 (sc->rxdesc & sc->hc->winmsk));
1926 rxdesc = &rxdesc[sc->rxhind];
1927 for(i=0;i<3;i++,rxdesc++)
1928 kprintf("AR: rxdesc->stat %x, "
1935 /* Counter overflow */
1936 if(dsr & SCA_DSR_COF) {
1937 kprintf("ar%d: RX DMA Counter overflow, "
1941 sc->ifsppp.pp_if.if_ipackets);
1942 sc->ifsppp.pp_if.if_ierrors++;
1943 #else /* NETGRAPH */
1946 #endif /* NETGRAPH */
1949 /* Buffer overflow */
1950 if(dsr & SCA_DSR_BOF) {
1951 if(hc->bustype == AR_BUS_ISA)
1952 ARC_SET_SCA(hc, scano);
1953 kprintf("ar%d: RX DMA Buffer overflow, "
1954 "rxpkts %lu, rxind %d, "
1955 "cda %x, eda %x, dsr %x.\n",
1958 sc->ifsppp.pp_if.if_ipackets,
1959 #else /* NETGRAPH */
1961 #endif /* NETGRAPH */
1967 * Make sure we eat as many as possible.
1968 * Then get the system running again.
1970 ar_eat_packet(sc, 0);
1972 sc->ifsppp.pp_if.if_ierrors++;
1973 #else /* NETGRAPH */
1975 #endif /* NETGRAPH */
1976 if(hc->bustype == AR_BUS_ISA)
1977 ARC_SET_SCA(hc, scano);
1978 sca->msci[mch].cmd = SCA_CMD_RXMSGREJ;
1979 dmac->dsr = SCA_DSR_DE;
1981 TRC(kprintf("ar%d: RX DMA Buffer overflow, "
1982 "rxpkts %lu, rxind %d, "
1983 "cda %x, eda %x, dsr %x. After\n",
1985 sc->ifsppp.pp_if.if_ipackets,
1992 /* End of Transfer */
1993 if(dsr & SCA_DSR_EOT) {
1995 * If this happen, it means that we are
1996 * receiving faster than what the processor
1999 * XXX We should enable the dma again.
2001 kprintf("ar%d: RX End of transfer, rxpkts %lu.\n",
2004 sc->ifsppp.pp_if.if_ipackets);
2005 sc->ifsppp.pp_if.if_ierrors++;
2006 #else /* NETGRAPH */
2009 #endif /* NETGRAPH */
2016 }while((mch<NCHAN) && isr1);
2019 * Now that we have done all the urgent things, see if we
2020 * can fill the transmit buffers.
2022 for(mch = 0; mch < NCHAN; mch++) {
2023 if(dotxstart & 0x0C) {
2024 sc = &hc->sc[mch + (NCHAN * scano)];
2026 arstart(&sc->ifsppp.pp_if);
2027 #else /* NETGRAPH */
2029 #endif /* NETGRAPH */
2036 ar_msci_intr(struct ar_hardc *hc, int scano, u_char isr0)
2038 kprintf("arc%d: ARINTR: MSCI\n", hc->cunit);
2042 ar_timer_intr(struct ar_hardc *hc, int scano, u_char isr2)
2044 kprintf("arc%d: ARINTR: TIMER\n", hc->cunit);
2049 /*****************************************
2050 * Device timeout/watchdog routine.
2051 * called once per second.
2052 * checks to see that if activity was expected, that it hapenned.
2053 * At present we only look to see if expected output was completed.
2056 ngar_watchdog_frame(void * arg)
2058 struct ar_softc * sc = arg;
2061 if (sc->running == 0) {
2062 return; /* if we are not running let timeouts die */
2065 lwkt_serialize_enter(&ar_serializer);
2068 * calculate the apparent throughputs
2071 speed = sc->inbytes - sc->lastinbytes;
2072 sc->lastinbytes = sc->inbytes;
2073 if ( sc->inrate < speed )
2075 speed = sc->outbytes - sc->lastoutbytes;
2076 sc->lastoutbytes = sc->outbytes;
2077 if ( sc->outrate < speed )
2078 sc->outrate = speed;
2081 if ((sc->inlast > QUITE_A_WHILE)
2082 && (sc->out_deficit > LOTS_OF_PACKETS)) {
2083 log(LOG_ERR, "ar%d: No response from remote end\n", sc->unit);
2087 sc->inlast = sc->out_deficit = 0;
2088 } else if ( sc->xmit_busy ) { /* no TX -> no TX timeouts */
2089 if (sc->out_dog == 0) {
2090 log(LOG_ERR, "ar%d: Transmit failure.. no clock?\n",
2098 sc->inlast = sc->out_deficit = 0;
2103 lwkt_serialize_exit(&ar_serializer);
2104 callout_reset(&sc->timer, hz, ngar_watchdog_frame, sc);
2107 /***********************************************************************
2108 * This section contains the methods for the Netgraph interface
2109 ***********************************************************************/
2111 * It is not possible or allowable to create a node of this type.
2112 * If the hardware exists, it will already have created it.
2115 ngar_constructor(node_p *nodep)
2121 * give our ok for a hook to be added...
2122 * If we are not running this should kick the device into life.
2123 * The hook's private info points to our stash of info about that
2127 ngar_newhook(node_p node, hook_p hook, const char *name)
2129 struct ar_softc * sc = NG_NODE_PRIVATE(node);
2132 * check if it's our friend the debug hook
2134 if (strcmp(name, NG_AR_HOOK_DEBUG) == 0) {
2135 NG_HOOK_SET_PRIVATE(hook, NULL); /* paranoid */
2136 sc->debug_hook = hook;
2141 * Check for raw mode hook.
2143 if (strcmp(name, NG_AR_HOOK_RAW) != 0) {
2146 NG_HOOK_SET_PRIVATE(hook, sc);
2154 * incoming messages.
2155 * Just respond to the generic TEXT_STATUS message
2158 ngar_rcvmsg(node_p node, struct ng_mesg *msg, const char *retaddr,
2159 struct ng_mesg **rptr)
2161 struct ar_softc *sc;
2163 struct ng_mesg *resp = NULL;
2165 sc = NG_NODE_PRIVATE(node);
2166 switch (msg->header.typecookie) {
2170 case NGM_GENERIC_COOKIE:
2171 switch(msg->header.cmd) {
2172 case NGM_TEXT_STATUS: {
2176 int resplen = sizeof(struct ng_mesg) + 512;
2177 NG_MKRESPONSE(resp, msg, resplen, M_INTWAIT);
2183 pos = ksprintf(arg, "%ld bytes in, %ld bytes out\n"
2184 "highest rate seen: %ld B/S in, %ld B/S out\n",
2185 sc->inbytes, sc->outbytes,
2186 sc->inrate, sc->outrate);
2187 pos += ksprintf(arg + pos,
2188 "%ld output errors\n",
2190 pos += ksprintf(arg + pos,
2191 "ierrors = %ld, %ld, %ld, %ld\n",
2197 (resp)->header.arglen = pos + 1;
2209 /* Take care of synchronous response, if any */
2210 NG_RESPOND_MSG(error, node, retaddr, resp, rptr);
2216 * get data from another node and transmit it to the correct channel
2219 ngar_rcvdata(hook_p hook, struct mbuf *m, meta_p meta)
2222 struct ar_softc * sc = NG_NODE_PRIVATE(NG_HOOK_NODE(hook));
2223 struct ifqueue *xmitq_p;
2226 * data doesn't come in from just anywhere (e.g control hook)
2228 if ( NG_HOOK_PRIVATE(hook) == NULL) {
2234 * Now queue the data for when it can be sent
2236 if (meta && meta->priority > 0)
2237 xmitq_p = (&sc->xmitq_hipri);
2239 xmitq_p = (&sc->xmitq);
2241 if (IF_QFULL(xmitq_p)) {
2247 IF_ENQUEUE(xmitq_p, m);
2254 * It was an error case.
2255 * check if we need to free the mbuf, and then return the error
2257 NG_FREE_DATA(m, meta);
2262 * do local shutdown processing..
2263 * this node will refuse to go away, unless the hardware says to..
2264 * don't unref the node, or remove our name. just clear our links up.
2267 ngar_shutdown(node_p node)
2269 struct ar_softc * sc = NG_NODE_PRIVATE(node);
2272 NG_NODE_UNREF(node);
2273 /* XXX need to drain the output queues! */
2275 /* The node is dead, long live the node! */
2276 /* stolen from the attach routine */
2277 if (ng_make_node_common(&typestruct, &sc->node) != 0)
2279 ksprintf(sc->nodename, "%s%d", NG_AR_NODE_TYPE, sc->unit);
2280 if (ng_name_node(sc->node, sc->nodename)) {
2282 kprintf("node naming failed\n");
2283 NG_NODE_UNREF(sc->node); /* node dissappears */
2286 NG_NODE_SET_PRIVATE(sc->node, sc);
2291 /* already linked */
2293 ngar_connect(hook_p hook)
2295 /* be really amiable and just say "YUP that's OK by me! " */
2300 * notify on hook disconnection (destruction)
2302 * Invalidate the private data associated with this dlci.
2303 * For this type, removal of the last link resets tries to destroy the node.
2304 * As the device still exists, the shutdown method will not actually
2305 * destroy the node, but reset the device and leave it 'fresh' :)
2307 * The node removal code will remove all references except that owned by the
2311 ngar_disconnect(hook_p hook)
2313 struct ar_softc * sc = NG_NODE_PRIVATE(NG_HOOK_NODE(hook));
2316 * If it's the data hook, then free resources etc.
2318 if (NG_HOOK_PRIVATE(hook)) {
2320 if (sc->datahooks == 0)
2323 sc->debug_hook = NULL;
2329 * called during bootup
2330 * or LKM loading to put this type into the list of known modules
2333 ngar_init(void *ignored)
2335 if (ng_newtype(&typestruct))
2336 kprintf("ngar install failed\n");
2339 #endif /* NETGRAPH */
2342 ********************************* END ************************************