2 * Copyright (c) 1994 Matt Thomas (thomas@lkg.dec.com)
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the author may not be used to endorse or promote products
11 * derived from this software withough specific prior written permission
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 * $FreeBSD: src/sys/i386/isa/if_le.c,v 1.56.2.4 2002/06/05 23:24:10 paul Exp $
25 * $DragonFly: src/sys/dev/netif/le/if_le.c,v 1.11 2004/05/04 12:09:36 hmp Exp $
29 * DEC EtherWORKS 2 Ethernet Controllers
30 * DEC EtherWORKS 3 Ethernet Controllers
32 * Written by Matt Thomas
33 * BPF support code stolen directly from if_ec.c
35 * This driver supports the DEPCA, DE100, DE101, DE200, DE201,
36 * DE2002, DE203, DE204, DE205, and DE422 cards.
43 #include <sys/param.h>
44 #include <sys/systm.h>
47 #include <sys/socket.h>
48 #include <sys/sockio.h>
49 #include <sys/malloc.h>
50 #include <sys/linker_set.h>
51 #include <sys/module.h>
53 #include <net/ethernet.h>
55 #include <net/if_types.h>
56 #include <net/if_dl.h>
58 #include <netinet/in.h>
59 #include <netinet/if_ether.h>
62 #include <machine/clock.h>
64 #include <bus/isa/i386/isa_device.h>
65 #include <i386/isa/icu.h>
72 /* Forward declarations */
73 typedef struct le_softc le_softc_t;
74 typedef struct le_board le_board_t;
76 typedef u_short le_mcbits_t;
77 #define LE_MC_NBPW_LOG2 4
78 #define LE_MC_NBPW (1 << LE_MC_NBPW_LOG2)
80 #if !defined(LE_NOLEMAC)
82 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
84 * Start of DEC EtherWORKS III (LEMAC) dependent structures
87 #include <i386/isa/ic/lemac.h> /* Include LEMAC definitions */
89 DECLARE_DUMMY_MODULE(if_le);
91 static int lemac_probe(le_softc_t *sc, const le_board_t *bd, int *msize);
93 struct le_lemac_info {
94 u_int lemac__lastpage; /* last 2K page */
95 u_int lemac__memmode; /* Are we in 2K, 32K, or 64K mode */
96 u_int lemac__membase; /* Physical address of start of RAM */
97 u_int lemac__txctl; /* Transmit Control Byte */
98 u_int lemac__txmax; /* Maximum # of outstanding transmits */
99 le_mcbits_t lemac__mctbl[LEMAC_MCTBL_SIZE/sizeof(le_mcbits_t)];
100 /* local copy of multicast table */
101 u_char lemac__eeprom[LEMAC_EEP_SIZE]; /* local copy eeprom */
102 char lemac__prodname[LEMAC_EEP_PRDNMSZ+1]; /* prodname name */
103 #define lemac_lastpage le_un.un_lemac.lemac__lastpage
104 #define lemac_memmode le_un.un_lemac.lemac__memmode
105 #define lemac_membase le_un.un_lemac.lemac__membase
106 #define lemac_txctl le_un.un_lemac.lemac__txctl
107 #define lemac_txmax le_un.un_lemac.lemac__txmax
108 #define lemac_mctbl le_un.un_lemac.lemac__mctbl
109 #define lemac_eeprom le_un.un_lemac.lemac__eeprom
110 #define lemac_prodname le_un.un_lemac.lemac__prodname
112 #endif /* !defined(LE_NOLEMAC) */
114 #if !defined(LE_NOLANCE)
116 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
118 * Start of DEC EtherWORKS II (LANCE) dependent structures
122 #include <i386/isa/ic/am7990.h>
128 static int depca_probe(le_softc_t *sc, const le_board_t *bd, int *msize);
130 typedef struct lance_descinfo lance_descinfo_t;
131 typedef struct lance_ring lance_ring_t;
133 typedef unsigned lance_addr_t;
135 struct lance_descinfo {
136 caddr_t di_addr; /* address of descriptor */
137 lance_addr_t di_bufaddr; /* LANCE address of buffer owned by descriptor */
138 unsigned di_buflen; /* size of buffer owned by descriptor */
139 struct mbuf *di_mbuf; /* mbuf being transmitted/received */
143 lance_descinfo_t *ri_first; /* Pointer to first descriptor in ring */
144 lance_descinfo_t *ri_last; /* Pointer to last + 1 descriptor in ring */
145 lance_descinfo_t *ri_nextin; /* Pointer to next one to be given to HOST */
146 lance_descinfo_t *ri_nextout; /* Pointer to next one to be given to LANCE */
147 unsigned ri_max; /* Size of Ring - 1 */
148 unsigned ri_free; /* Number of free rings entires (owned by HOST) */
149 lance_addr_t ri_heap; /* Start of RAM for this ring */
150 lance_addr_t ri_heapend; /* End + 1 of RAM for this ring */
151 lance_addr_t ri_outptr; /* Pointer to first output byte */
152 unsigned ri_outsize; /* Space remaining for output */
155 struct le_lance_info {
156 unsigned lance__csr1; /* LANCE Address of init block (low 16) */
157 unsigned lance__csr2; /* LANCE Address of init block (high 8) */
158 unsigned lance__csr3; /* Copy of CSR3 */
159 unsigned lance__rap; /* IO Port Offset of RAP */
160 unsigned lance__rdp; /* IO Port Offset of RDP */
161 unsigned lance__ramoffset; /* Offset to valid LANCE RAM */
162 unsigned lance__ramsize; /* Amount of RAM shared by LANCE */
163 unsigned lance__rxbufsize; /* Size of a receive buffer */
164 ln_initb_t lance__initb; /* local copy of LANCE initblock */
165 ln_initb_t *lance__raminitb; /* copy to board's LANCE initblock (debugging) */
166 ln_desc_t *lance__ramdesc; /* copy to board's LANCE descriptors (debugging) */
167 lance_ring_t lance__rxinfo; /* Receive ring information */
168 lance_ring_t lance__txinfo; /* Transmit ring information */
169 #define lance_csr1 le_un.un_lance.lance__csr1
170 #define lance_csr2 le_un.un_lance.lance__csr2
171 #define lance_csr3 le_un.un_lance.lance__csr3
172 #define lance_rap le_un.un_lance.lance__rap
173 #define lance_rdp le_un.un_lance.lance__rdp
174 #define lance_ramoffset le_un.un_lance.lance__ramoffset
175 #define lance_ramsize le_un.un_lance.lance__ramsize
176 #define lance_rxbufsize le_un.un_lance.lance__rxbufsize
177 #define lance_initb le_un.un_lance.lance__initb
178 #define lance_raminitb le_un.un_lance.lance__raminitb
179 #define lance_ramdesc le_un.un_lance.lance__ramdesc
180 #define lance_rxinfo le_un.un_lance.lance__rxinfo
181 #define lance_txinfo le_un.un_lance.lance__txinfo
183 #endif /* !defined(LE_NOLANCE) */
186 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
188 * Start of Common Code
192 static void (*le_intrvec[NLE])(le_softc_t *sc);
195 * Ethernet status, per interface.
198 struct arpcom le_ac; /* Common Ethernet/ARP Structure */
199 void (*if_init) (void *);/* Interface init routine */
200 void (*if_reset) (le_softc_t *);/* Interface reset routine */
201 caddr_t le_membase; /* Starting memory address (virtual) */
202 unsigned le_iobase; /* Starting I/O base address */
203 unsigned le_irq; /* Interrupt Request Value */
204 unsigned le_flags; /* local copy of if_flags */
205 #define LE_BRDCSTONLY 0x01000000 /* If only broadcast is enabled */
206 u_int le_mcmask; /* bit mask for CRC-32 for multicast hash */
207 le_mcbits_t *le_mctbl; /* pointer to multicast table */
208 const char *le_prodname; /* product name DE20x-xx */
209 u_char le_hwaddr[6]; /* local copy of hwaddr */
211 #if !defined(LE_NOLEMAC)
212 struct le_lemac_info un_lemac; /* LEMAC specific information */
214 #if !defined(LE_NOLANCE)
215 struct le_lance_info un_lance; /* Am7990 specific information */
219 #define le_if le_ac.ac_if
222 static int le_probe(struct isa_device *dvp);
223 static int le_attach(struct isa_device *dvp);
224 static ointhand2_t le_intr;
225 static int le_ioctl(struct ifnet *ifp, u_long command, caddr_t data,
227 static void le_input(le_softc_t *sc, caddr_t seg1, size_t total_len,
228 size_t len2, caddr_t seg2);
229 static void le_multi_filter(le_softc_t *sc);
230 static void le_multi_op(le_softc_t *sc, const u_char *mca, int oper_flg);
231 static int le_read_macaddr(le_softc_t *sc, int ioreg, int skippat);
233 #define LE_CRC32_POLY 0xEDB88320UL /* CRC-32 Poly -- Little Endian */
236 int (*bd_probe)(le_softc_t *sc, const le_board_t *bd, int *msize);
240 static le_softc_t le_softc[NLE];
242 static const le_board_t le_boards[] = {
243 #if !defined(LE_NOLEMAC)
244 { lemac_probe }, /* DE20[345] */
246 #if !defined(LE_NOLANCE)
247 { depca_probe }, /* DE{20[012],422} */
249 { NULL } /* Must Be Last! */
253 * This tells the autoconf code how to set us up.
255 struct isa_driver ledriver = {
256 le_probe, le_attach, "le",
259 static unsigned le_intrs[NLE];
261 #define LE_ADDREQUAL(a1, a2) \
262 (((u_short *)a1)[0] == ((u_short *)a2)[0] \
263 || ((u_short *)a1)[1] == ((u_short *)a2)[1] \
264 || ((u_short *)a1)[2] == ((u_short *)a2)[2])
265 #define LE_ADDRBRDCST(a1) \
266 (((u_short *)a1)[0] == 0xFFFFU \
267 || ((u_short *)a1)[1] == 0xFFFFU \
268 || ((u_short *)a1)[2] == 0xFFFFU)
270 #define LE_INL(sc, reg) \
272 __asm __volatile("inl %1, %0": "=a" (data): "d" ((u_short)((sc)->le_iobase + (reg)))); \
276 #define LE_OUTL(sc, reg, data) \
277 ({__asm __volatile("outl %0, %1"::"a" ((u_int)(data)), "d" ((u_short)((sc)->le_iobase + (reg))));})
279 #define LE_INW(sc, reg) \
281 __asm __volatile("inw %1, %0": "=a" (data): "d" ((u_short)((sc)->le_iobase + (reg)))); \
285 #define LE_OUTW(sc, reg, data) \
286 ({__asm __volatile("outw %0, %1"::"a" ((u_short)(data)), "d" ((u_short)((sc)->le_iobase + (reg))));})
288 #define LE_INB(sc, reg) \
290 __asm __volatile("inb %1, %0": "=a" (data): "d" ((u_short)((sc)->le_iobase + (reg)))); \
294 #define LE_OUTB(sc, reg, data) \
295 ({__asm __volatile("outb %0, %1"::"a" ((u_char)(data)), "d" ((u_short)((sc)->le_iobase + (reg))));})
297 #define MEMCPY(to, from, len) bcopy(from, to, len)
298 #define MEMSET(where, what, howmuch) bzero(where, howmuch)
299 #define MEMCMP(l, r, len) bcmp(l, r, len)
304 struct isa_device *dvp)
306 le_softc_t *sc = &le_softc[dvp->id_unit];
307 const le_board_t *bd;
310 if (dvp->id_unit >= NLE) {
311 printf("%s%d not configured -- too many devices\n",
312 ledriver.name, dvp->id_unit);
316 sc->le_iobase = dvp->id_iobase;
317 sc->le_membase = (u_char *) dvp->id_maddr;
318 sc->le_irq = dvp->id_irq;
319 if_initname(&(sc->le_if), ledriver.name, dvp->id_unit);
322 * Find and Initialize board..
325 sc->le_flags &= ~(IFF_UP|IFF_ALLMULTI);
327 for (bd = le_boards; bd->bd_probe != NULL; bd++) {
328 if ((iospace = (*bd->bd_probe)(sc, bd, &dvp->id_msize)) != 0) {
338 struct isa_device *dvp)
340 le_softc_t *sc = &le_softc[dvp->id_unit];
341 struct ifnet *ifp = &sc->le_if;
343 dvp->id_ointr = le_intr;
345 ifp->if_mtu = ETHERMTU;
346 printf("%s: %s ethernet address %6D\n",
349 sc->le_ac.ac_enaddr, ":");
351 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
352 ifp->if_output = ether_output;
353 ifp->if_ioctl = le_ioctl;
354 ifp->if_type = IFT_ETHER;
357 ifp->if_init = sc->if_init;
359 ether_ifattach(ifp, sc->le_ac.ac_enaddr);
371 (*le_intrvec[unit])(&le_softc[unit]);
386 struct ether_header eh;
389 if (total_len - sizeof(eh) > ETHERMTU
390 || total_len - sizeof(eh) < ETHERMIN) {
391 sc->le_if.if_ierrors++;
394 MEMCPY(&eh, seg1, sizeof(eh));
396 seg1 += sizeof(eh); total_len -= sizeof(eh); len1 -= sizeof(eh);
398 MGETHDR(m, M_DONTWAIT, MT_DATA);
400 sc->le_if.if_ierrors++;
403 m->m_pkthdr.len = total_len;
404 m->m_pkthdr.rcvif = &sc->le_if;
405 if (total_len + LE_XTRA > MHLEN /* >= MINCLSIZE */) {
406 MCLGET(m, M_DONTWAIT);
407 if ((m->m_flags & M_EXT) == 0) {
409 sc->le_if.if_ierrors++;
412 } else if (total_len + LE_XTRA > MHLEN && MINCLSIZE == (MHLEN+MLEN)) {
413 MGET(m->m_next, M_DONTWAIT, MT_DATA);
414 if (m->m_next == NULL) {
416 sc->le_if.if_ierrors++;
419 m->m_next->m_len = total_len - MHLEN - LE_XTRA;
420 len1 = total_len = MHLEN - LE_XTRA;
421 MEMCPY(mtod(m->m_next, caddr_t), &seg1[MHLEN-LE_XTRA], m->m_next->m_len);
422 } else if (total_len + LE_XTRA > MHLEN) {
423 panic("le_input: pkt of unknown length");
425 m->m_data += LE_XTRA;
426 m->m_len = total_len;
427 MEMCPY(mtod(m, caddr_t), seg1, len1);
429 MEMCPY(mtod(m, caddr_t) + len1, seg2, total_len - len1);
430 ether_input(&sc->le_if, &eh, m);
434 le_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
436 le_softc_t *sc = ifp->if_softc;
439 if ((sc->le_flags & IFF_UP) == 0)
448 error = ether_ioctl(ifp, cmd, data);
459 * Update multicast listeners
475 * This is the standard method of reading the DEC Address ROMS.
476 * I don't understand it but it does work.
484 int cksum, rom_cksum;
487 int idx, idx2, found, octet;
488 static u_char testpat[] = { 0xFF, 0, 0x55, 0xAA, 0xFF, 0, 0x55, 0xAA };
491 for (idx = 0; idx < 32; idx++) {
492 octet = LE_INB(sc, ioreg);
494 if (octet == testpat[idx2]) {
495 if (++idx2 == sizeof testpat) {
509 sc->le_hwaddr[0] = LE_INB(sc, ioreg);
510 sc->le_hwaddr[1] = LE_INB(sc, ioreg);
512 cksum = *(u_short *) &sc->le_hwaddr[0];
514 sc->le_hwaddr[2] = LE_INB(sc, ioreg);
515 sc->le_hwaddr[3] = LE_INB(sc, ioreg);
517 if (cksum > 65535) cksum -= 65535;
518 cksum += *(u_short *) &sc->le_hwaddr[2];
519 if (cksum > 65535) cksum -= 65535;
521 sc->le_hwaddr[4] = LE_INB(sc, ioreg);
522 sc->le_hwaddr[5] = LE_INB(sc, ioreg);
524 if (cksum > 65535) cksum -= 65535;
525 cksum += *(u_short *) &sc->le_hwaddr[4];
526 if (cksum >= 65535) cksum -= 65535;
528 rom_cksum = LE_INB(sc, ioreg);
529 rom_cksum |= LE_INB(sc, ioreg) << 8;
531 if (cksum != rom_cksum)
540 struct ifmultiaddr *ifma;
542 MEMSET(sc->le_mctbl, 0, (sc->le_mcmask + 1) / 8);
544 if (sc->le_if.if_flags & IFF_ALLMULTI) {
545 sc->le_flags |= IFF_MULTICAST|IFF_ALLMULTI;
548 sc->le_flags &= ~IFF_MULTICAST;
549 /* if (interface has had an address assigned) { */
550 le_multi_op(sc, etherbroadcastaddr, TRUE);
551 sc->le_flags |= LE_BRDCSTONLY|IFF_MULTICAST;
554 sc->le_flags |= IFF_MULTICAST;
556 for (ifma = sc->le_ac.ac_if.if_multiaddrs.lh_first; ifma;
557 ifma = ifma->ifma_link.le_next) {
558 if (ifma->ifma_addr->sa_family != AF_LINK)
561 le_multi_op(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1);
562 sc->le_flags &= ~LE_BRDCSTONLY;
572 u_int idx, bit, data, crc = 0xFFFFFFFFUL;
575 for (data = *(__unaligned u_long *) mca, bit = 0; bit < 48; bit++, data >>=
577 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? LE_CRC32_POLY : 0);
579 for (idx = 0; idx < 6; idx++)
580 for (data = *mca++, bit = 0; bit < 8; bit++, data >>= 1)
581 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? LE_CRC32_POLY : 0);
584 * The following two line convert the N bit index into a longword index
585 * and a longword mask.
587 crc &= sc->le_mcmask;
588 bit = 1 << (crc & (LE_MC_NBPW -1));
589 idx = crc >> (LE_MC_NBPW_LOG2);
592 * Set or clear hash filter bit in our table.
595 sc->le_mctbl[idx] |= bit; /* Set Bit */
597 sc->le_mctbl[idx] &= ~bit; /* Clear Bit */
601 #if !defined(LE_NOLEMAC)
603 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
605 * Start of DEC EtherWORKS III (LEMAC) dependent code
609 #define LEMAC_INTR_ENABLE(sc) \
610 LE_OUTB(sc, LEMAC_REG_IC, LE_INB(sc, LEMAC_REG_IC) | LEMAC_IC_ALL)
612 #define LEMAC_INTR_DISABLE(sc) \
613 LE_OUTB(sc, LEMAC_REG_IC, LE_INB(sc, LEMAC_REG_IC) & ~LEMAC_IC_ALL)
615 #define LEMAC_64K_MODE(mbase) (((mbase) >= 0x0A) && ((mbase) <= 0x0F))
616 #define LEMAC_32K_MODE(mbase) (((mbase) >= 0x14) && ((mbase) <= 0x1F))
617 #define LEMAC_2K_MODE(mbase) ( (mbase) >= 0x40)
619 static void lemac_init(void *xsc);
620 static void lemac_start(struct ifnet *ifp);
621 static void lemac_reset(le_softc_t *sc);
622 static void lemac_intr(le_softc_t *sc);
623 static void lemac_rne_intr(le_softc_t *sc);
624 static void lemac_tne_intr(le_softc_t *sc);
625 static void lemac_txd_intr(le_softc_t *sc, unsigned cs_value);
626 static void lemac_rxd_intr(le_softc_t *sc, unsigned cs_value);
627 static int lemac_read_eeprom(le_softc_t *sc);
628 static void lemac_init_adapmem(le_softc_t *sc);
630 #define LE_MCBITS_ALL_1S ((le_mcbits_t)~(le_mcbits_t)0)
632 static const le_mcbits_t lemac_allmulti_mctbl[16] = {
633 LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S,
634 LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S,
635 LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S,
636 LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S,
639 * An IRQ mapping table. Less space than switch statement.
641 static const int lemac_irqs[] = { IRQ5, IRQ10, IRQ11, IRQ15 };
644 * Some tuning/monitoring variables.
646 static unsigned lemac_deftxmax = 16; /* see lemac_max above */
647 static unsigned lemac_txnospc = 0; /* total # of tranmit starvations */
649 static unsigned lemac_tne_intrs = 0; /* total # of tranmit done intrs */
650 static unsigned lemac_rne_intrs = 0; /* total # of receive done intrs */
651 static unsigned lemac_txd_intrs = 0; /* total # of tranmit error intrs */
652 static unsigned lemac_rxd_intrs = 0; /* total # of receive error intrs */
658 const le_board_t *bd,
663 LE_OUTB(sc, LEMAC_REG_IOP, LEMAC_IOP_EEINIT);
664 DELAY(LEMAC_EEP_DELAY);
667 * Read Ethernet address if card is present.
669 if (le_read_macaddr(sc, LEMAC_REG_APD, 0) < 0)
672 MEMCPY(sc->le_ac.ac_enaddr, sc->le_hwaddr, 6);
674 * Clear interrupts and set IRQ.
677 portval = LE_INB(sc, LEMAC_REG_IC) & LEMAC_IC_IRQMSK;
678 irq = lemac_irqs[portval >> 5];
679 LE_OUTB(sc, LEMAC_REG_IC, portval);
682 * Make sure settings match.
685 if (irq != sc->le_irq) {
686 printf("%s: lemac configuration error: expected IRQ 0x%x actual 0x%x\n",
687 sc->le_if.if_xname, sc->le_irq, irq);
692 * Try to reset the unit
694 sc->if_init = lemac_init;
695 sc->le_if.if_start = lemac_start;
696 sc->if_reset = lemac_reset;
697 sc->lemac_memmode = 2;
699 if ((sc->le_flags & IFF_UP) == 0)
703 * Check for correct memory base configuration.
705 if (vtophys(sc->le_membase) != sc->lemac_membase) {
706 printf("%s: lemac configuration error: expected iomem 0x%llx actual 0x%x\n",
708 vtophys(sc->le_membase), sc->lemac_membase);
712 sc->le_prodname = sc->lemac_prodname;
713 sc->le_mctbl = sc->lemac_mctbl;
714 sc->le_mcmask = (1 << LEMAC_MCTBL_BITS) - 1;
715 sc->lemac_txmax = lemac_deftxmax;
717 le_intrvec[sc->le_if.if_dunit] = lemac_intr;
719 return LEMAC_IOSPACE;
723 * Do a hard reset of the board;
735 sc->le_flags &= IFF_UP;
736 sc->le_if.if_flags &= ~IFF_OACTIVE;
737 LEMAC_INTR_DISABLE(sc);
739 LE_OUTB(sc, LEMAC_REG_IOP, LEMAC_IOP_EEINIT);
740 DELAY(LEMAC_EEP_DELAY);
742 /* Disable Interrupts */
743 /* LE_OUTB(sc, LEMAC_REG_IC, LE_INB(sc, LEMAC_REG_IC) & ICR_IRQ_SEL); */
746 * Read EEPROM information. NOTE - the placement of this function
747 * is important because functions hereafter may rely on information
748 * read from the EEPROM.
750 if ((cksum = lemac_read_eeprom(sc)) != LEMAC_EEP_CKSUM) {
751 printf("%s: reset: EEPROM checksum failed (0x%x)\n",
752 sc->le_if.if_xname, cksum);
757 * Force to 2K mode if not already configured.
760 portval = LE_INB(sc, LEMAC_REG_MBR);
761 if (!LEMAC_2K_MODE(portval)) {
762 if (LEMAC_64K_MODE(portval)) {
763 portval = (((portval * 2) & 0xF) << 4);
764 sc->lemac_memmode = 64;
765 } else if (LEMAC_32K_MODE(portval)) {
766 portval = ((portval & 0xF) << 4);
767 sc->lemac_memmode = 32;
769 LE_OUTB(sc, LEMAC_REG_MBR, portval);
771 sc->lemac_membase = portval * (2 * 1024) + (512 * 1024);
774 * Initialize Free Memory Queue, Init mcast table with broadcast.
777 lemac_init_adapmem(sc);
778 sc->le_flags |= IFF_UP;
786 le_softc_t *sc = (le_softc_t *)xsc;
789 if ((sc->le_flags & IFF_UP) == 0)
795 * If the interface has the up flag
797 if (sc->le_if.if_flags & IFF_UP) {
798 int saved_cs = LE_INB(sc, LEMAC_REG_CS);
799 LE_OUTB(sc, LEMAC_REG_CS, saved_cs | (LEMAC_CS_TXD | LEMAC_CS_RXD));
800 LE_OUTB(sc, LEMAC_REG_PA0, sc->le_ac.ac_enaddr[0]);
801 LE_OUTB(sc, LEMAC_REG_PA1, sc->le_ac.ac_enaddr[1]);
802 LE_OUTB(sc, LEMAC_REG_PA2, sc->le_ac.ac_enaddr[2]);
803 LE_OUTB(sc, LEMAC_REG_PA3, sc->le_ac.ac_enaddr[3]);
804 LE_OUTB(sc, LEMAC_REG_PA4, sc->le_ac.ac_enaddr[4]);
805 LE_OUTB(sc, LEMAC_REG_PA5, sc->le_ac.ac_enaddr[5]);
807 LE_OUTB(sc, LEMAC_REG_IC, LE_INB(sc, LEMAC_REG_IC) | LEMAC_IC_IE);
809 if (sc->le_if.if_flags & IFF_PROMISC) {
810 LE_OUTB(sc, LEMAC_REG_CS, LEMAC_CS_MCE | LEMAC_CS_PME);
812 LEMAC_INTR_DISABLE(sc);
814 LE_OUTB(sc, LEMAC_REG_MPN, 0);
815 if ((sc->le_flags | sc->le_if.if_flags) & IFF_ALLMULTI) {
816 MEMCPY(&sc->le_membase[LEMAC_MCTBL_OFF], lemac_allmulti_mctbl, sizeof(lemac_allmulti_mctbl));
818 MEMCPY(&sc->le_membase[LEMAC_MCTBL_OFF], sc->lemac_mctbl, sizeof(sc->lemac_mctbl));
820 LE_OUTB(sc, LEMAC_REG_CS, LEMAC_CS_MCE);
823 LE_OUTB(sc, LEMAC_REG_CTL, LE_INB(sc, LEMAC_REG_CTL) ^ LEMAC_CTL_LED);
825 LEMAC_INTR_ENABLE(sc);
826 sc->le_if.if_flags |= IFF_RUNNING;
828 LE_OUTB(sc, LEMAC_REG_CS, LEMAC_CS_RXD|LEMAC_CS_TXD);
830 LEMAC_INTR_DISABLE(sc);
831 sc->le_if.if_flags &= ~IFF_RUNNING;
837 * What to do upon receipt of an interrupt.
845 LEMAC_INTR_DISABLE(sc); /* Mask interrupts */
848 * Determine cause of interrupt. Receive events take
849 * priority over Transmit.
852 cs_value = LE_INB(sc, LEMAC_REG_CS);
855 * Check for Receive Queue not being empty.
856 * Check for Transmit Done Queue not being empty.
859 if (cs_value & LEMAC_CS_RNE)
861 if (cs_value & LEMAC_CS_TNE)
865 * Check for Transmitter Disabled.
866 * Check for Receiver Disabled.
869 if (cs_value & LEMAC_CS_TXD)
870 lemac_txd_intr(sc, cs_value);
871 if (cs_value & LEMAC_CS_RXD)
872 lemac_rxd_intr(sc, cs_value);
875 * Toggle LED and unmask interrupts.
878 LE_OUTB(sc, LEMAC_REG_CTL, LE_INB(sc, LEMAC_REG_CTL) ^ LEMAC_CTL_LED);
879 LEMAC_INTR_ENABLE(sc); /* Unmask interrupts */
886 int rxcount, rxlen, rxpg;
890 rxcount = LE_INB(sc, LEMAC_REG_RQC);
892 rxpg = LE_INB(sc, LEMAC_REG_RQ);
893 LE_OUTB(sc, LEMAC_REG_MPN, rxpg);
895 rxptr = sc->le_membase;
896 sc->le_if.if_ipackets++;
897 if (*rxptr & LEMAC_RX_OK) {
900 * Get receive length - subtract out checksum.
903 rxlen = ((*(u_int *)rxptr >> 8) & 0x7FF) - 4;
904 le_input(sc, rxptr + sizeof(u_int), rxlen, rxlen, NULL);
905 } else { /* end if (*rxptr & LEMAC_RX_OK) */
906 sc->le_if.if_ierrors++;
908 LE_OUTB(sc, LEMAC_REG_FMQ, rxpg); /* Return this page to Free Memory Queue */
909 } /* end while (recv_count--) */
920 * Handle CS_RXD (Receiver disabled) here.
922 * Check Free Memory Queue Count. If not equal to zero
923 * then just turn Receiver back on. If it is equal to
924 * zero then check to see if transmitter is disabled.
925 * Process transmit TXD loop once more. If all else
926 * fails then do software init (0xC0 to EEPROM Init)
927 * and rebuild Free Memory Queue.
933 * Re-enable Receiver.
936 cs_value &= ~LEMAC_CS_RXD;
937 LE_OUTB(sc, LEMAC_REG_CS, cs_value);
939 if (LE_INB(sc, LEMAC_REG_FMC) > 0)
942 if (cs_value & LEMAC_CS_TXD)
943 lemac_txd_intr(sc, cs_value);
945 if ((LE_INB(sc, LEMAC_REG_CS) & LEMAC_CS_RXD) == 0)
948 printf("%s: fatal RXD error, attempting recovery\n",
952 if (sc->le_flags & IFF_UP) {
958 * Error during initializion. Mark card as disabled.
960 printf("%s: recovery failed -- board disabled\n",
969 le_softc_t *sc = (le_softc_t *) ifp;
970 struct ifqueue *ifq = &ifp->if_snd;
972 if ((ifp->if_flags & IFF_RUNNING) == 0)
975 LEMAC_INTR_DISABLE(sc);
977 while (ifq->ifq_head != NULL) {
982 if (LE_INB(sc, LEMAC_REG_TQC) >= sc->lemac_txmax) {
983 ifp->if_flags |= IFF_OACTIVE;
987 tx_pg = LE_INB(sc, LEMAC_REG_FMQ); /* get free memory page */
989 * Check for good transmit page.
991 if (tx_pg == 0 || tx_pg > sc->lemac_lastpage) {
993 ifp->if_flags |= IFF_OACTIVE;
998 LE_OUTB(sc, LEMAC_REG_MPN, tx_pg); /* Shift 2K window. */
1001 * The first four bytes of each transmit buffer are for
1002 * control information. The first byte is the control
1003 * byte, then the length (why not word aligned?), then
1004 * the off to the buffer.
1007 txoff = (mtod(m, u_int) & (sizeof(u_long) - 1)) + LEMAC_TX_HDRSZ;
1008 txhdr = sc->lemac_txctl | (m->m_pkthdr.len << 8) | (txoff << 24);
1009 *(u_int *) sc->le_membase = txhdr;
1012 * Copy the packet to the board
1015 m_copydata(m, 0, m->m_pkthdr.len, sc->le_membase + txoff);
1017 LE_OUTB(sc, LEMAC_REG_TQ, tx_pg); /* tell chip to transmit this packet */
1019 if (sc->le_if.if_bpf)
1020 bpf_mtap(&sc->le_if, m);
1022 m_freem(m); /* free the mbuf */
1024 LEMAC_INTR_ENABLE(sc);
1031 int txsts, txcount = LE_INB(sc, LEMAC_REG_TDC);
1035 txsts = LE_INB(sc, LEMAC_REG_TDQ);
1036 sc->le_if.if_opackets++; /* another one done */
1037 if ((txsts & LEMAC_TDQ_COL) != LEMAC_TDQ_NOCOL)
1038 sc->le_if.if_collisions++;
1040 sc->le_if.if_flags &= ~IFF_OACTIVE;
1041 lemac_start(&sc->le_if);
1050 * Read transmit status, remove transmit buffer from
1051 * transmit queue and place on free memory queue,
1052 * then reset transmitter.
1053 * Increment appropriate counters.
1057 sc->le_if.if_oerrors++;
1058 if (LE_INB(sc, LEMAC_REG_TS) & LEMAC_TS_ECL)
1059 sc->le_if.if_collisions++;
1060 sc->le_if.if_flags &= ~IFF_OACTIVE;
1062 LE_OUTB(sc, LEMAC_REG_FMQ, LE_INB(sc, LEMAC_REG_TQ));
1063 /* Get Page number and write it back out */
1065 LE_OUTB(sc, LEMAC_REG_CS, cs_value & ~LEMAC_CS_TXD);
1066 /* Turn back on transmitter */
1074 int word_off, cksum;
1079 ep = sc->lemac_eeprom;
1080 for (word_off = 0; word_off < LEMAC_EEP_SIZE / 2; word_off++) {
1081 LE_OUTB(sc, LEMAC_REG_PI1, word_off);
1082 LE_OUTB(sc, LEMAC_REG_IOP, LEMAC_IOP_EEREAD);
1084 DELAY(LEMAC_EEP_DELAY);
1086 *ep = LE_INB(sc, LEMAC_REG_EE1); cksum += *ep++;
1087 *ep = LE_INB(sc, LEMAC_REG_EE2); cksum += *ep++;
1091 * Set up Transmit Control Byte for use later during transmit.
1094 sc->lemac_txctl |= LEMAC_TX_FLAGS;
1096 if ((sc->lemac_eeprom[LEMAC_EEP_SWFLAGS] & LEMAC_EEP_SW_SQE) == 0)
1097 sc->lemac_txctl &= ~LEMAC_TX_SQE;
1099 if (sc->lemac_eeprom[LEMAC_EEP_SWFLAGS] & LEMAC_EEP_SW_LAB)
1100 sc->lemac_txctl |= LEMAC_TX_LAB;
1102 MEMCPY(sc->lemac_prodname, &sc->lemac_eeprom[LEMAC_EEP_PRDNM], LEMAC_EEP_PRDNMSZ);
1103 sc->lemac_prodname[LEMAC_EEP_PRDNMSZ] = '\0';
1114 conf = LE_INB(sc, LEMAC_REG_CNF);
1116 if ((sc->lemac_eeprom[LEMAC_EEP_SETUP] & LEMAC_EEP_ST_DRAM) == 0) {
1117 sc->lemac_lastpage = 63;
1118 conf &= ~LEMAC_CNF_DRAM;
1120 sc->lemac_lastpage = 127;
1121 conf |= LEMAC_CNF_DRAM;
1124 LE_OUTB(sc, LEMAC_REG_CNF, conf);
1126 for (pg = 1; pg <= sc->lemac_lastpage; pg++)
1127 LE_OUTB(sc, LEMAC_REG_FMQ, pg);
1131 #endif /* !defined(LE_NOLEMAC) */
1133 #if !defined(LE_NOLANCE)
1135 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
1137 * Start of DEPCA (DE200/DE201/DE202/DE422 etal) support.
1140 static void depca_intr(le_softc_t *sc);
1141 static int lance_init_adapmem(le_softc_t *sc);
1142 static int lance_init_ring(le_softc_t *sc, ln_ring_t *rp, lance_ring_t *ri,
1143 unsigned ndescs, unsigned bufoffset,
1144 unsigned descoffset);
1145 static void lance_init(void *xsc);
1146 static void lance_reset(le_softc_t *sc);
1147 static void lance_intr(le_softc_t *sc);
1148 static int lance_rx_intr(le_softc_t *sc);
1149 static void lance_start(struct ifnet *ifp);
1150 static int lance_tx_intr(le_softc_t *sc);
1152 #define LN_BUFSIZE /* 380 */ 304 /* 1520 / 4 */
1153 #define LN_TXDESC_RATIO 2048
1154 #define LN_DESC_MAX 128
1158 unsigned lance_rx_misses;
1159 unsigned lance_rx_badcrc;
1160 unsigned lance_rx_badalign;
1161 unsigned lance_rx_badframe;
1162 unsigned lance_rx_buferror;
1163 unsigned lance_tx_deferred;
1164 unsigned lance_tx_single_collisions;
1165 unsigned lance_tx_multiple_collisions;
1166 unsigned lance_tx_excessive_collisions;
1167 unsigned lance_tx_late_collisions;
1169 unsigned lance_memory_errors;
1170 unsigned lance_inits;
1171 unsigned lance_tx_intrs;
1172 unsigned lance_tx_nospc[2];
1173 unsigned lance_tx_drains[2];
1174 unsigned lance_tx_orphaned;
1175 unsigned lance_tx_adoptions;
1176 unsigned lance_tx_emptied;
1177 unsigned lance_tx_deftxint;
1178 unsigned lance_tx_buferror;
1179 unsigned lance_high_txoutptr;
1180 unsigned lance_low_txheapsize;
1181 unsigned lance_low_txfree;
1182 unsigned lance_tx_intr_hidescs;
1183 /* unsigned lance_tx_intr_descs[LN_DESC_MAX]; */
1185 unsigned lance_rx_intrs;
1186 unsigned lance_rx_badsop;
1187 unsigned lance_rx_contig;
1188 unsigned lance_rx_noncontig;
1189 unsigned lance_rx_intr_hidescs;
1190 unsigned lance_rx_ndescs[4096 / LN_BUFSIZE];
1191 /* unsigned lance_rx_intr_descs[LN_DESC_MAX]; */
1194 #define LN_STAT(stat) (lance_stats.lance_ ## stat)
1195 #define LN_MINSTAT(stat, val) (LN_STAT(stat > (val)) ? LN_STAT(stat = (val)) : 0)
1196 #define LN_MAXSTAT(stat, val) (LN_STAT(stat < (val)) ? LN_STAT(stat = (val)) : 0)
1199 #define LN_STAT(stat) 0
1200 #define LN_MINSTAT(stat, val) 0
1201 #define LN_MAXSTAT(stat, val) 0
1204 #define LN_SELCSR(sc, csrno) (LE_OUTW(sc, sc->lance_rap, csrno))
1205 #define LN_INQCSR(sc) (LE_INW(sc, sc->lance_rap))
1207 #define LN_WRCSR(sc, val) (LE_OUTW(sc, sc->lance_rdp, val))
1208 #define LN_RDCSR(sc) (LE_INW(sc, sc->lance_rdp))
1211 #define LN_ZERO(sc, vaddr, len) bzero(vaddr, len)
1212 #define LN_COPYTO(sc, from, to, len) bcopy(from, to, len)
1214 #define LN_SETFLAG(sc, vaddr, val) \
1215 (((volatile u_char *) vaddr)[3] = (val))
1217 #define LN_PUTDESC(sc, desc, vaddr) \
1218 (((volatile u_short *) vaddr)[0] = ((u_short *) desc)[0], \
1219 ((volatile u_short *) vaddr)[2] = ((u_short *) desc)[2], \
1220 ((volatile u_short *) vaddr)[1] = ((u_short *) desc)[1])
1223 * Only get the descriptor flags and length/status. All else
1226 #define LN_GETDESC(sc, desc, vaddr) \
1227 (((u_short *) desc)[1] = ((volatile u_short *) vaddr)[1], \
1228 ((u_short *) desc)[3] = ((volatile u_short *) vaddr)[3])
1232 * These definitions are specific to the DEC "DEPCA-style" NICs.
1233 * (DEPCA, DE10x, DE20[012], DE422)
1236 #define DEPCA_REG_NICSR 0 /* (RW;16) NI Control / Status */
1237 #define DEPCA_REG_RDP 4 /* (RW:16) LANCE RDP (data) register */
1238 #define DEPCA_REG_RAP 6 /* (RW:16) LANCE RAP (address) register */
1239 #define DEPCA_REG_ADDRROM 12 /* (R : 8) DEPCA Ethernet Address ROM */
1240 #define DEPCA_IOSPACE 16 /* DEPCAs use 16 bytes of IO space */
1242 #define DEPCA_NICSR_LED 0x0001 /* Light the LED on the back of the DEPCA */
1243 #define DEPCA_NICSR_ENABINTR 0x0002 /* Enable Interrupts */
1244 #define DEPCA_NICSR_MASKINTR 0x0004 /* Mask Interrupts */
1245 #define DEPCA_NICSR_AAC 0x0008 /* Address Counter Clear */
1246 #define DEPCA_NICSR_REMOTEBOOT 0x0010 /* Remote Boot Enabled (ignored) */
1247 #define DEPCA_NICSR_32KRAM 0x0020 /* DEPCA LANCE RAM size 64K (C) / 32K (S) */
1248 #define DEPCA_NICSR_LOW32K 0x0040 /* Bank Select (A15 = !This Bit) */
1249 #define DEPCA_NICSR_SHE 0x0080 /* Shared RAM Enabled (ie hide ROM) */
1250 #define DEPCA_NICSR_BOOTTMO 0x0100 /* Remote Boot Timeout (ignored) */
1252 #define DEPCA_RDNICSR(sc) (LE_INW(sc, DEPCA_REG_NICSR))
1253 #define DEPCA_WRNICSR(sc, val) (LE_OUTW(sc, DEPCA_REG_NICSR, val))
1255 #define DEPCA_IDSTR_OFFSET 0xC006 /* ID String Offset */
1257 #define DEPCA_REG_EISAID 0x80
1258 #define DEPCA_EISAID_MASK 0xf0ffffff
1259 #define DEPCA_EISAID_DE422 0x2042A310
1263 DEPCA_DE100, DEPCA_DE101,
1265 DEPCA_DE200, DEPCA_DE201, DEPCA_DE202,
1270 static const char *depca_signatures[] = {
1274 "DE200", "DE201", "DE202",
1282 const le_board_t *bd,
1285 unsigned nicsr, idx, idstr_offset = DEPCA_IDSTR_OFFSET;
1288 * Find out how memory we are dealing with. Adjust
1289 * the ID string offset approriately if we are at
1290 * 32K. Make sure the ROM is enabled.
1292 nicsr = DEPCA_RDNICSR(sc);
1293 nicsr &= ~(DEPCA_NICSR_SHE|DEPCA_NICSR_LED|DEPCA_NICSR_ENABINTR);
1295 if (nicsr & DEPCA_NICSR_32KRAM) {
1297 * Make we are going to read the upper
1298 * 32K so we do read the ROM.
1300 sc->lance_ramsize = 32 * 1024;
1301 nicsr &= ~DEPCA_NICSR_LOW32K;
1302 sc->lance_ramoffset = 32 * 1024;
1303 idstr_offset -= sc->lance_ramsize;
1305 sc->lance_ramsize = 64 * 1024;
1306 sc->lance_ramoffset = 0;
1308 DEPCA_WRNICSR(sc, nicsr);
1310 sc->le_prodname = NULL;
1311 for (idx = 0; depca_signatures[idx] != NULL; idx++) {
1312 if (bcmp(depca_signatures[idx], sc->le_membase + idstr_offset, 5) == 0) {
1313 sc->le_prodname = depca_signatures[idx];
1318 if (sc->le_prodname == NULL) {
1320 * Try to get the EISA device if it's a DE422.
1322 if (sc->le_iobase > 0x1000 && (sc->le_iobase & 0x0F00) == 0x0C00
1323 && (LE_INL(sc, DEPCA_REG_EISAID) & DEPCA_EISAID_MASK)
1324 == DEPCA_EISAID_DE422) {
1325 sc->le_prodname = "DE422";
1330 if (idx == DEPCA_CLASSIC)
1331 sc->lance_ramsize -= 16384; /* Can't use the ROM area on a DEPCA */
1334 * Try to read the address ROM.
1335 * Stop the LANCE, reset the Address ROM Counter (AAC),
1336 * read the NICSR to "clock" in the reset, and then
1337 * re-enable the Address ROM Counter. Now read the
1340 sc->lance_rdp = DEPCA_REG_RDP;
1341 sc->lance_rap = DEPCA_REG_RAP;
1342 sc->lance_csr3 = LN_CSR3_ALE;
1343 sc->le_mctbl = sc->lance_initb.ln_multi_mask;
1344 sc->le_mcmask = LN_MC_MASK;
1345 LN_SELCSR(sc, LN_CSR0);
1346 LN_WRCSR(sc, LN_CSR0_STOP);
1348 if (idx < DEPCA_DE200) {
1349 DEPCA_WRNICSR(sc, DEPCA_RDNICSR(sc) & ~DEPCA_NICSR_AAC);
1350 DEPCA_WRNICSR(sc, DEPCA_RDNICSR(sc) | DEPCA_NICSR_AAC);
1353 if (le_read_macaddr(sc, DEPCA_REG_ADDRROM, idx == DEPCA_CLASSIC) < 0)
1356 MEMCPY(sc->le_ac.ac_enaddr, sc->le_hwaddr, 6);
1358 * Renable shared RAM.
1360 DEPCA_WRNICSR(sc, DEPCA_RDNICSR(sc) | DEPCA_NICSR_SHE);
1362 le_intrvec[sc->le_if.if_dunit] = depca_intr;
1363 if (!lance_init_adapmem(sc))
1366 sc->if_reset = lance_reset;
1367 sc->if_init = lance_init;
1368 sc->le_if.if_start = lance_start;
1369 DEPCA_WRNICSR(sc, DEPCA_NICSR_SHE | DEPCA_NICSR_ENABINTR);
1372 LN_STAT(low_txfree = sc->lance_txinfo.ri_max);
1373 LN_STAT(low_txheapsize = 0xFFFFFFFF);
1374 *msize = sc->lance_ramsize;
1375 return DEPCA_IOSPACE;
1382 DEPCA_WRNICSR(sc, DEPCA_RDNICSR(sc) ^ DEPCA_NICSR_LED);
1387 * Here's as good a place to describe our paritioning of the
1388 * LANCE shared RAM space. (NOTE: this driver does not yet support
1389 * the concept of a LANCE being able to DMA).
1391 * First is the 24 (00:23) bytes for LANCE Initialization Block
1392 * Next are the recieve descriptors. The number is calculated from
1393 * how many LN_BUFSIZE buffers we can allocate (this number must
1394 * be a power of 2). Next are the transmit descriptors. The amount
1395 * of transmit descriptors is derived from the size of the RAM
1396 * divided by 1K. Now come the receive buffers (one for each receive
1397 * descriptor). Finally is the transmit heap. (no fixed buffers are
1398 * allocated so as to make the most use of the limited space).
1404 lance_addr_t rxbufoffset;
1405 lance_addr_t rxdescoffset, txdescoffset;
1406 unsigned rxdescs, txdescs;
1409 * First calculate how many descriptors we heap.
1410 * Note this assumes the ramsize is a power of two.
1412 sc->lance_rxbufsize = LN_BUFSIZE;
1414 while (rxdescs * sc->lance_rxbufsize < sc->lance_ramsize)
1417 if (rxdescs > LN_DESC_MAX) {
1418 sc->lance_rxbufsize *= rxdescs / LN_DESC_MAX;
1419 rxdescs = LN_DESC_MAX;
1421 txdescs = sc->lance_ramsize / LN_TXDESC_RATIO;
1422 if (txdescs > LN_DESC_MAX)
1423 txdescs = LN_DESC_MAX;
1426 * Now calculate where everything goes in memory
1428 rxdescoffset = sizeof(ln_initb_t);
1429 txdescoffset = rxdescoffset + sizeof(ln_desc_t) * rxdescs;
1430 rxbufoffset = txdescoffset + sizeof(ln_desc_t) * txdescs;
1432 sc->le_mctbl = (le_mcbits_t *) sc->lance_initb.ln_multi_mask;
1434 * Remember these for debugging.
1436 sc->lance_raminitb = (ln_initb_t *) sc->le_membase;
1437 sc->lance_ramdesc = (ln_desc_t *) (sc->le_membase + rxdescoffset);
1440 * Initialize the rings.
1442 if (!lance_init_ring(sc, &sc->lance_initb.ln_rxring, &sc->lance_rxinfo,
1443 rxdescs, rxbufoffset, rxdescoffset))
1445 sc->lance_rxinfo.ri_heap = rxbufoffset;
1446 sc->lance_rxinfo.ri_heapend = rxbufoffset + sc->lance_rxbufsize * rxdescs;
1448 if (!lance_init_ring(sc, &sc->lance_initb.ln_txring, &sc->lance_txinfo,
1449 txdescs, 0, txdescoffset))
1451 sc->lance_txinfo.ri_heap = sc->lance_rxinfo.ri_heapend;
1452 sc->lance_txinfo.ri_heapend = sc->lance_ramsize;
1455 * Set CSR1 and CSR2 to the address of the init block (which
1456 * for us is always 0.
1458 sc->lance_csr1 = LN_ADDR_LO(0 + sc->lance_ramoffset);
1459 sc->lance_csr2 = LN_ADDR_HI(0 + sc->lance_ramoffset);
1469 lance_addr_t bufoffset,
1470 lance_addr_t descoffset)
1472 lance_descinfo_t *di;
1475 * Initialize the ring pointer in the LANCE InitBlock
1477 rp->r_addr_lo = LN_ADDR_LO(descoffset + sc->lance_ramoffset);
1478 rp->r_addr_hi = LN_ADDR_HI(descoffset + sc->lance_ramoffset);
1479 rp->r_log2_size = ffs(ndescs) - 1;
1482 * Allocate the ring entry descriptors and initialize
1483 * our ring information data structure. All these are
1484 * our copies and do not live in the LANCE RAM.
1486 ri->ri_first = malloc(ndescs * sizeof(*di), M_DEVBUF, M_WAITOK);
1487 if (ri->ri_first == NULL) {
1488 printf("lance_init_ring: malloc(%d) failed\n", ndescs * sizeof(*di));
1491 ri->ri_free = ri->ri_max = ndescs;
1492 ri->ri_last = ri->ri_first + ri->ri_max;
1493 for (di = ri->ri_first; di < ri->ri_last; di++) {
1494 di->di_addr = sc->le_membase + descoffset;
1497 di->di_bufaddr = bufoffset;
1498 di->di_buflen = sc->lance_rxbufsize;
1499 bufoffset += sc->lance_rxbufsize;
1501 descoffset += sizeof(ln_desc_t);
1511 printf("%s: %s: nicsr=%04x",
1513 id, DEPCA_RDNICSR(sc));
1514 LN_SELCSR(sc, LN_CSR0); printf(" csr0=%04x", LN_RDCSR(sc));
1515 LN_SELCSR(sc, LN_CSR1); printf(" csr1=%04x", LN_RDCSR(sc));
1516 LN_SELCSR(sc, LN_CSR2); printf(" csr2=%04x", LN_RDCSR(sc));
1517 LN_SELCSR(sc, LN_CSR3); printf(" csr3=%04x\n", LN_RDCSR(sc));
1518 LN_SELCSR(sc, LN_CSR0);
1527 /* lance_dumpcsrs(sc, "lance_reset: start"); */
1529 LN_WRCSR(sc, LN_RDCSR(sc) & ~LN_CSR0_ENABINTR);
1530 LN_WRCSR(sc, LN_CSR0_STOP);
1533 sc->le_flags &= ~IFF_UP;
1534 sc->le_if.if_flags &= ~(IFF_UP|IFF_RUNNING);
1536 le_multi_filter(sc); /* initialize the multicast table */
1537 if ((sc->le_flags | sc->le_if.if_flags) & IFF_ALLMULTI) {
1538 sc->lance_initb.ln_multi_mask[0] = 0xFFFFU;
1539 sc->lance_initb.ln_multi_mask[1] = 0xFFFFU;
1540 sc->lance_initb.ln_multi_mask[2] = 0xFFFFU;
1541 sc->lance_initb.ln_multi_mask[3] = 0xFFFFU;
1543 sc->lance_initb.ln_physaddr[0] = ((u_short *) sc->le_ac.ac_enaddr)[0];
1544 sc->lance_initb.ln_physaddr[1] = ((u_short *) sc->le_ac.ac_enaddr)[1];
1545 sc->lance_initb.ln_physaddr[2] = ((u_short *) sc->le_ac.ac_enaddr)[2];
1546 if (sc->le_if.if_flags & IFF_PROMISC) {
1547 sc->lance_initb.ln_mode |= LN_MODE_PROMISC;
1549 sc->lance_initb.ln_mode &= ~LN_MODE_PROMISC;
1552 * We force the init block to be at the start
1553 * of the LANCE's RAM buffer.
1555 LN_COPYTO(sc, &sc->lance_initb, sc->le_membase, sizeof(sc->lance_initb));
1556 LN_SELCSR(sc, LN_CSR1); LN_WRCSR(sc, sc->lance_csr1);
1557 LN_SELCSR(sc, LN_CSR2); LN_WRCSR(sc, sc->lance_csr2);
1558 LN_SELCSR(sc, LN_CSR3); LN_WRCSR(sc, sc->lance_csr3);
1560 /* lance_dumpcsrs(sc, "lance_reset: preinit"); */
1563 * clear INITDONE and INIT the chip
1565 LN_SELCSR(sc, LN_CSR0);
1566 LN_WRCSR(sc, LN_CSR0_INIT|LN_CSR0_INITDONE);
1571 if (((csr = LN_RDCSR(sc)) & LN_CSR0_INITDONE) != 0)
1576 if ((csr & LN_CSR0_INITDONE) == 0) { /* make sure we got out okay */
1577 lance_dumpcsrs(sc, "lance_reset: reset failure");
1579 /* lance_dumpcsrs(sc, "lance_reset: end"); */
1580 sc->le_if.if_flags |= IFF_UP;
1581 sc->le_flags |= IFF_UP;
1589 le_softc_t *sc = (le_softc_t *)xsc;
1591 lance_descinfo_t *di;
1595 if (sc->le_if.if_flags & IFF_RUNNING) {
1599 * If we were running, requeue any pending transmits.
1601 ri = &sc->lance_txinfo;
1602 di = ri->ri_nextout;
1603 while (ri->ri_free < ri->ri_max) {
1604 if (--di == ri->ri_first)
1605 di = ri->ri_nextout - 1;
1606 if (di->di_mbuf == NULL)
1608 IF_PREPEND(&sc->le_if.if_snd, di->di_mbuf);
1617 * Reset the transmit ring. Make sure we own all the buffers.
1618 * Also reset the transmit heap.
1620 sc->le_if.if_flags &= ~IFF_OACTIVE;
1621 ri = &sc->lance_txinfo;
1622 for (di = ri->ri_first; di < ri->ri_last; di++) {
1623 if (di->di_mbuf != NULL) {
1624 m_freem(di->di_mbuf);
1628 desc.d_addr_lo = LN_ADDR_LO(ri->ri_heap + sc->lance_ramoffset);
1629 desc.d_addr_hi = LN_ADDR_HI(ri->ri_heap + sc->lance_ramoffset);
1631 LN_PUTDESC(sc, &desc, di->di_addr);
1633 ri->ri_nextin = ri->ri_nextout = ri->ri_first;
1634 ri->ri_free = ri->ri_max;
1635 ri->ri_outptr = ri->ri_heap;
1636 ri->ri_outsize = ri->ri_heapend - ri->ri_heap;
1638 ri = &sc->lance_rxinfo;
1639 desc.d_flag = LN_DFLAG_OWNER;
1640 desc.d_buflen = 0 - sc->lance_rxbufsize;
1641 for (di = ri->ri_first; di < ri->ri_last; di++) {
1642 desc.d_addr_lo = LN_ADDR_LO(di->di_bufaddr + sc->lance_ramoffset);
1643 desc.d_addr_hi = LN_ADDR_HI(di->di_bufaddr + sc->lance_ramoffset);
1644 LN_PUTDESC(sc, &desc, di->di_addr);
1646 ri->ri_nextin = ri->ri_nextout = ri->ri_first;
1647 ri->ri_outptr = ri->ri_heap;
1648 ri->ri_outsize = ri->ri_heapend - ri->ri_heap;
1651 if (sc->le_if.if_flags & IFF_UP) {
1652 sc->le_if.if_flags |= IFF_RUNNING;
1653 LN_WRCSR(sc, LN_CSR0_START|LN_CSR0_INITDONE|LN_CSR0_ENABINTR);
1654 /* lance_dumpcsrs(sc, "lance_init: up"); */
1655 lance_start(&sc->le_if);
1657 /* lance_dumpcsrs(sc, "lance_init: down"); */
1658 sc->le_if.if_flags &= ~IFF_RUNNING;
1668 oldcsr = LN_RDCSR(sc);
1669 oldcsr &= ~LN_CSR0_ENABINTR;
1670 LN_WRCSR(sc, oldcsr);
1671 LN_WRCSR(sc, LN_CSR0_ENABINTR);
1673 if (oldcsr & LN_CSR0_ERRSUM) {
1674 if (oldcsr & LN_CSR0_MISS) {
1676 * LN_CSR0_MISS is signaled when the LANCE receiver
1677 * loses a packet because it doesn't own a receive
1678 * descriptor. Rev. D LANCE chips, which are no
1679 * longer used, require a chip reset as described
1682 LN_STAT(rx_misses++);
1684 if (oldcsr & LN_CSR0_MEMERROR) {
1685 LN_STAT(memory_errors++);
1686 if (oldcsr & (LN_CSR0_RXON|LN_CSR0_TXON)) {
1693 if ((oldcsr & LN_CSR0_RXINT) && lance_rx_intr(sc)) {
1698 if (oldcsr & LN_CSR0_TXINT) {
1699 if (lance_tx_intr(sc))
1700 lance_start(&sc->le_if);
1703 if (oldcsr == (LN_CSR0_PENDINTR|LN_CSR0_RXON|LN_CSR0_TXON))
1704 printf("%s: lance_intr: stray interrupt\n",
1705 sc->le_if.if_xname);
1712 lance_ring_t *ri = &sc->lance_rxinfo;
1713 lance_descinfo_t *eop;
1715 int ndescs, total_len, rxdescs;
1717 LN_STAT(rx_intrs++);
1719 for (rxdescs = 0;;) {
1721 * Now to try to find the end of this packet chain.
1723 for (ndescs = 1, eop = ri->ri_nextin;; ndescs++) {
1725 * If we don't own this descriptor, the packet ain't
1726 * all here so return because we are done.
1728 LN_GETDESC(sc, &desc, eop->di_addr);
1729 if (desc.d_flag & LN_DFLAG_OWNER)
1732 * In case we have missed a packet and gotten the
1733 * LANCE confused, make sure we are pointing at the
1734 * start of a packet. If we aren't, something is really
1735 * strange so reinit the LANCE.
1737 if (desc.d_flag & LN_DFLAG_RxBUFERROR) {
1738 LN_STAT(rx_buferror++);
1741 if ((desc.d_flag & LN_DFLAG_SOP) && eop != ri->ri_nextin) {
1742 LN_STAT(rx_badsop++);
1745 if (desc.d_flag & LN_DFLAG_EOP)
1747 if (++eop == ri->ri_last)
1751 total_len = (desc.d_status & LN_DSTS_RxLENMASK) - 4;
1752 if ((desc.d_flag & LN_DFLAG_RxERRSUM) == 0) {
1754 * Valid Packet -- If the SOP is less than or equal to the EOP
1755 * or the length is less than the receive buffer size, then the
1756 * packet is contiguous in memory and can be copied in one shot.
1757 * Otherwise we need to copy two segments to get the entire
1760 if (ri->ri_nextin <= eop || total_len <= ri->ri_heapend - ri->ri_nextin->di_bufaddr) {
1761 le_input(sc, sc->le_membase + ri->ri_nextin->di_bufaddr,
1762 total_len, total_len, NULL);
1763 LN_STAT(rx_contig++);
1765 le_input(sc, sc->le_membase + ri->ri_nextin->di_bufaddr,
1767 ri->ri_heapend - ri->ri_nextin->di_bufaddr,
1768 sc->le_membase + ri->ri_first->di_bufaddr);
1769 LN_STAT(rx_noncontig++);
1773 * If the packet is bad, increment the
1776 sc->le_if.if_ierrors++;
1777 if (desc.d_flag & LN_DFLAG_RxBADCRC)
1778 LN_STAT(rx_badcrc++);
1779 if (desc.d_flag & LN_DFLAG_RxOVERFLOW)
1780 LN_STAT(rx_badalign++);
1781 if (desc.d_flag & LN_DFLAG_RxFRAMING)
1782 LN_STAT(rx_badframe++);
1784 sc->le_if.if_ipackets++;
1785 LN_STAT(rx_ndescs[ndescs-1]++);
1787 while (ndescs-- > 0) {
1788 LN_SETFLAG(sc, ri->ri_nextin->di_addr, LN_DFLAG_OWNER);
1789 if (++ri->ri_nextin == ri->ri_last)
1790 ri->ri_nextin = ri->ri_first;
1793 /* LN_STAT(rx_intr_descs[rxdescs]++); */
1794 LN_MAXSTAT(rx_intr_hidescs, rxdescs);
1803 le_softc_t *sc = (le_softc_t *) ifp;
1804 struct ifqueue *ifq = &ifp->if_snd;
1805 lance_ring_t *ri = &sc->lance_txinfo;
1806 lance_descinfo_t *di;
1809 struct mbuf *m, *m0;
1812 if ((ifp->if_flags & IFF_RUNNING) == 0)
1821 * Make the packet meets the minimum size for Ethernet.
1822 * The slop is so that we also use an even number of longwards.
1824 len = ETHERMIN + sizeof(struct ether_header);
1825 if (m->m_pkthdr.len > len)
1826 len = m->m_pkthdr.len;
1828 slop = (8 - len) & 3;
1830 * If there are no free ring entries (there must be always
1831 * one owned by the host), or there's not enough space for
1832 * this packet, or this packet would wrap around the end
1833 * of LANCE RAM then wait for the transmits to empty for
1834 * space and ring entries to become available.
1836 if (ri->ri_free == 1 || len + slop > ri->ri_outsize) {
1838 * Try to see if we can free up anything off the transit ring.
1840 if (lance_tx_intr(sc) > 0) {
1841 LN_STAT(tx_drains[0]++);
1845 LN_STAT(tx_nospc[0]++);
1849 if (len + slop > ri->ri_heapend - ri->ri_outptr) {
1851 * Since the packet won't fit in the end of the transmit
1852 * heap, see if there is space at the beginning of the transmit
1853 * heap. If not, try again when there is space.
1855 LN_STAT(tx_orphaned++);
1856 slop += ri->ri_heapend - ri->ri_outptr;
1857 if (len + slop > ri->ri_outsize) {
1858 LN_STAT(tx_nospc[1]++);
1862 * Point to the beginning of the heap
1864 ri->ri_outptr = ri->ri_heap;
1865 LN_STAT(tx_adoptions++);
1869 * Initialize the descriptor (saving the buffer address,
1870 * buffer length, and mbuf) and write the packet out
1873 di = ri->ri_nextout;
1874 di->di_bufaddr = ri->ri_outptr;
1875 di->di_buflen = len + slop;
1877 bp = sc->le_membase + di->di_bufaddr;
1878 for (m0 = m; m0 != NULL; m0 = m0->m_next) {
1879 LN_COPYTO(sc, mtod(m0, caddr_t), bp, m0->m_len);
1883 * Zero out the remainder if needed (< ETHERMIN).
1885 if (m->m_pkthdr.len < len)
1886 LN_ZERO(sc, bp, len - m->m_pkthdr.len);
1889 * Finally, copy out the descriptor and tell the
1890 * LANCE to transmit!.
1892 desc.d_buflen = 0 - len;
1893 desc.d_addr_lo = LN_ADDR_LO(di->di_bufaddr + sc->lance_ramoffset);
1894 desc.d_addr_hi = LN_ADDR_HI(di->di_bufaddr + sc->lance_ramoffset);
1895 desc.d_flag = LN_DFLAG_SOP|LN_DFLAG_EOP|LN_DFLAG_OWNER;
1896 LN_PUTDESC(sc, &desc, di->di_addr);
1897 LN_WRCSR(sc, LN_CSR0_TXDEMAND|LN_CSR0_ENABINTR);
1900 * Do our bookkeeping with our transmit heap.
1901 * (if we wrap, point back to the beginning).
1903 ri->ri_outptr += di->di_buflen;
1904 ri->ri_outsize -= di->di_buflen;
1905 LN_MAXSTAT(high_txoutptr, ri->ri_outptr);
1906 LN_MINSTAT(low_txheapsize, ri->ri_outsize);
1908 if (ri->ri_outptr == ri->ri_heapend)
1909 ri->ri_outptr = ri->ri_heap;
1912 if (++ri->ri_nextout == ri->ri_last)
1913 ri->ri_nextout = ri->ri_first;
1914 LN_MINSTAT(low_txfree, ri->ri_free);
1917 ifp->if_flags |= IFF_OACTIVE;
1926 lance_ring_t *ri = &sc->lance_txinfo;
1929 LN_STAT(tx_intrs++);
1930 for (xmits = 0; ri->ri_free < ri->ri_max; ) {
1933 LN_GETDESC(sc, &desc, ri->ri_nextin->di_addr);
1934 if (desc.d_flag & LN_DFLAG_OWNER)
1937 if (desc.d_flag & (LN_DFLAG_TxONECOLL|LN_DFLAG_TxMULTCOLL))
1938 sc->le_if.if_collisions++;
1939 if (desc.d_flag & LN_DFLAG_TxDEFERRED)
1940 LN_STAT(tx_deferred++);
1941 if (desc.d_flag & LN_DFLAG_TxONECOLL)
1942 LN_STAT(tx_single_collisions++);
1943 if (desc.d_flag & LN_DFLAG_TxMULTCOLL)
1944 LN_STAT(tx_multiple_collisions++);
1946 if (desc.d_flag & LN_DFLAG_TxERRSUM) {
1947 if (desc.d_status & (LN_DSTS_TxUNDERFLOW|LN_DSTS_TxBUFERROR|
1948 LN_DSTS_TxEXCCOLL|LN_DSTS_TxLATECOLL)) {
1949 if (desc.d_status & LN_DSTS_TxEXCCOLL) {
1951 LN_STAT(tx_excessive_collisions++);
1952 if ((tdr = (desc.d_status & LN_DSTS_TxTDRMASK)) > 0) {
1954 printf("%s: lance: warning: excessive collisions: TDR %dns (%d-%dm)\n",
1956 tdr, (tdr*99)/1000, (tdr*117)/1000);
1959 if (desc.d_status & LN_DSTS_TxBUFERROR)
1960 LN_STAT(tx_buferror++);
1961 sc->le_if.if_oerrors++;
1962 if ((desc.d_status & LN_DSTS_TxLATECOLL) == 0) {
1966 LN_STAT(tx_late_collisions++);
1970 m_freem(ri->ri_nextin->di_mbuf);
1971 ri->ri_nextin->di_mbuf = NULL;
1972 sc->le_if.if_opackets++;
1974 ri->ri_outsize += ri->ri_nextin->di_buflen;
1975 if (++ri->ri_nextin == ri->ri_last)
1976 ri->ri_nextin = ri->ri_first;
1977 sc->le_if.if_flags &= ~IFF_OACTIVE;
1980 if (ri->ri_free == ri->ri_max)
1981 LN_STAT(tx_emptied++);
1982 /* LN_STAT(tx_intr_descs[xmits]++); */
1983 LN_MAXSTAT(tx_intr_hidescs, xmits);
1986 #endif /* !defined(LE_NOLANCE) */