2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_xl.c,v 1.72.2.28 2003/10/08 06:01:57 murray Exp $
36 * 3Com 3c90x Etherlink XL PCI NIC driver
38 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI
39 * bus-master chips (3c90x cards and embedded controllers) including
42 * 3Com 3c900-TPO 10Mbps/RJ-45
43 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC
44 * 3Com 3c905-TX 10/100Mbps/RJ-45
45 * 3Com 3c905-T4 10/100Mbps/RJ-45
46 * 3Com 3c900B-TPO 10Mbps/RJ-45
47 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC
48 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC
49 * 3Com 3c900B-FL 10Mbps/Fiber-optic
50 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC
51 * 3Com 3c905B-TX 10/100Mbps/RJ-45
52 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic
53 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC)
54 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC)
55 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC)
56 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC)
57 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC)
58 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane)
59 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
60 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
61 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
62 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
63 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
64 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
65 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
66 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC)
67 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45
68 * Dell on-board 3c920 10/100Mbps/RJ-45
69 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45
70 * Dell Latitude laptop docking station embedded 3c905-TX
72 * Written by Bill Paul <wpaul@ctr.columbia.edu>
73 * Electrical Engineering Department
74 * Columbia University, New York City
78 * The 3c90x series chips use a bus-master DMA interface for transfering
79 * packets to and from the controller chip. Some of the "vortex" cards
80 * (3c59x) also supported a bus master mode, however for those chips
81 * you could only DMA packets to/from a contiguous memory buffer. For
82 * transmission this would mean copying the contents of the queued mbuf
83 * chain into an mbuf cluster and then DMAing the cluster. This extra
84 * copy would sort of defeat the purpose of the bus master support for
85 * any packet that doesn't fit into a single mbuf.
87 * By contrast, the 3c90x cards support a fragment-based bus master
88 * mode where mbuf chains can be encapsulated using TX descriptors.
89 * This is similar to other PCI chips such as the Texas Instruments
90 * ThunderLAN and the Intel 82557/82558.
92 * The "vortex" driver (if_vx.c) happens to work for the "boomerang"
93 * bus master chips because they maintain the old PIO interface for
94 * backwards compatibility, but starting with the 3c905B and the
95 * "cyclone" chips, the compatibility interface has been dropped.
96 * Since using bus master DMA is a big win, we use this driver to
97 * support the PCI "boomerang" chips even though they work with the
98 * "vortex" driver in order to obtain better performance.
101 #include "opt_polling.h"
103 #include <sys/param.h>
104 #include <sys/systm.h>
105 #include <sys/sockio.h>
106 #include <sys/endian.h>
107 #include <sys/mbuf.h>
108 #include <sys/kernel.h>
109 #include <sys/socket.h>
110 #include <sys/serialize.h>
112 #include <sys/rman.h>
113 #include <sys/thread2.h>
114 #include <sys/interrupt.h>
117 #include <net/ifq_var.h>
118 #include <net/if_arp.h>
119 #include <net/ethernet.h>
120 #include <net/if_dl.h>
121 #include <net/if_media.h>
122 #include <net/vlan/if_vlan_var.h>
126 #include "../mii_layer/mii.h"
127 #include "../mii_layer/miivar.h"
129 #include <bus/pci/pcireg.h>
130 #include <bus/pci/pcivar.h>
132 /* "controller miibus0" required. See GENERIC if you get errors here. */
133 #include "miibus_if.h"
135 #include "if_xlreg.h"
137 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
140 * Various supported device vendors/types and their names.
142 static struct xl_type xl_devs[] = {
143 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT,
144 "3Com 3c900-TPO Etherlink XL" },
145 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO,
146 "3Com 3c900-COMBO Etherlink XL" },
147 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT,
148 "3Com 3c905-TX Fast Etherlink XL" },
149 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4,
150 "3Com 3c905-T4 Fast Etherlink XL" },
151 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT,
152 "3Com 3c900B-TPO Etherlink XL" },
153 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO,
154 "3Com 3c900B-COMBO Etherlink XL" },
155 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC,
156 "3Com 3c900B-TPC Etherlink XL" },
157 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL,
158 "3Com 3c900B-FL Etherlink XL" },
159 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT,
160 "3Com 3c905B-TX Fast Etherlink XL" },
161 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4,
162 "3Com 3c905B-T4 Fast Etherlink XL" },
163 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX,
164 "3Com 3c905B-FX/SC Fast Etherlink XL" },
165 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO,
166 "3Com 3c905B-COMBO Fast Etherlink XL" },
167 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT,
168 "3Com 3c905C-TX Fast Etherlink XL" },
169 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B,
170 "3Com 3c920B-EMB Integrated Fast Etherlink XL" },
171 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV,
172 "3Com 3c980 Fast Etherlink XL" },
173 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV,
174 "3Com 3c980C Fast Etherlink XL" },
175 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX,
176 "3Com 3cSOHO100-TX OfficeConnect" },
177 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT,
178 "3Com 3c450-TX HomeConnect" },
179 { TC_VENDORID, TC_DEVICEID_HURRICANE_555,
180 "3Com 3c555 Fast Etherlink XL" },
181 { TC_VENDORID, TC_DEVICEID_HURRICANE_556,
182 "3Com 3c556 Fast Etherlink XL" },
183 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B,
184 "3Com 3c556B Fast Etherlink XL" },
185 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A,
186 "3Com 3c575TX Fast Etherlink XL" },
187 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B,
188 "3Com 3c575B Fast Etherlink XL" },
189 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C,
190 "3Com 3c575C Fast Etherlink XL" },
191 { TC_VENDORID, TC_DEVICEID_HURRICANE_656,
192 "3Com 3c656 Fast Etherlink XL" },
193 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B,
194 "3Com 3c656B Fast Etherlink XL" },
195 { TC_VENDORID, TC_DEVICEID_TORNADO_656C,
196 "3Com 3c656C Fast Etherlink XL" },
200 static int xl_probe (device_t);
201 static int xl_attach (device_t);
202 static int xl_detach (device_t);
203 static void xl_shutdown (device_t);
204 static int xl_suspend (device_t);
205 static int xl_resume (device_t);
207 static int xl_newbuf (struct xl_softc *, struct xl_chain_onefrag *,
209 static void xl_stats_update (void *);
210 static void xl_stats_update_serialized(void *);
211 static int xl_encap (struct xl_softc *, struct xl_chain *,
213 static void xl_rxeof (struct xl_softc *, int);
214 static int xl_rx_resync (struct xl_softc *);
215 static void xl_txeof (struct xl_softc *);
216 static void xl_txeof_90xB (struct xl_softc *);
217 static void xl_txeoc (struct xl_softc *);
218 static void xl_intr (void *);
219 static void xl_start_body (struct ifnet *, int);
220 static void xl_start (struct ifnet *);
221 static void xl_start_90xB (struct ifnet *);
222 static int xl_ioctl (struct ifnet *, u_long, caddr_t,
224 static void xl_init (void *);
225 static void xl_stop (struct xl_softc *);
226 static void xl_watchdog (struct ifnet *);
227 #ifdef DEVICE_POLLING
228 static void xl_start_poll (struct ifnet *);
229 static void xl_poll (struct ifnet *, enum poll_cmd, int);
231 static void xl_enable_intrs (struct xl_softc *, uint16_t);
233 static int xl_ifmedia_upd (struct ifnet *);
234 static void xl_ifmedia_sts (struct ifnet *, struct ifmediareq *);
236 static int xl_eeprom_wait (struct xl_softc *);
237 static int xl_read_eeprom (struct xl_softc *, caddr_t, int, int, int);
238 static void xl_mii_sync (struct xl_softc *);
239 static void xl_mii_send (struct xl_softc *, u_int32_t, int);
240 static int xl_mii_readreg (struct xl_softc *, struct xl_mii_frame *);
241 static int xl_mii_writereg (struct xl_softc *, struct xl_mii_frame *);
243 static void xl_setcfg (struct xl_softc *);
244 static void xl_setmode (struct xl_softc *, int);
245 static void xl_setmulti (struct xl_softc *);
246 static void xl_setmulti_hash (struct xl_softc *);
247 static void xl_reset (struct xl_softc *);
248 static int xl_list_rx_init (struct xl_softc *);
249 static void xl_list_tx_init (struct xl_softc *);
250 static void xl_list_tx_init_90xB(struct xl_softc *);
251 static void xl_wait (struct xl_softc *);
252 static void xl_mediacheck (struct xl_softc *);
253 static void xl_choose_xcvr (struct xl_softc *, int);
255 static int xl_dma_alloc (device_t);
256 static void xl_dma_free (device_t);
259 static void xl_testpacket (struct xl_softc *);
262 static int xl_miibus_readreg (device_t, int, int);
263 static int xl_miibus_writereg (device_t, int, int, int);
264 static void xl_miibus_statchg (device_t);
265 static void xl_miibus_mediainit (device_t);
267 static device_method_t xl_methods[] = {
268 /* Device interface */
269 DEVMETHOD(device_probe, xl_probe),
270 DEVMETHOD(device_attach, xl_attach),
271 DEVMETHOD(device_detach, xl_detach),
272 DEVMETHOD(device_shutdown, xl_shutdown),
273 DEVMETHOD(device_suspend, xl_suspend),
274 DEVMETHOD(device_resume, xl_resume),
277 DEVMETHOD(bus_print_child, bus_generic_print_child),
278 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
281 DEVMETHOD(miibus_readreg, xl_miibus_readreg),
282 DEVMETHOD(miibus_writereg, xl_miibus_writereg),
283 DEVMETHOD(miibus_statchg, xl_miibus_statchg),
284 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit),
289 static driver_t xl_driver = {
292 sizeof(struct xl_softc)
295 static devclass_t xl_devclass;
297 DECLARE_DUMMY_MODULE(if_xl);
298 MODULE_DEPEND(if_xl, miibus, 1, 1, 1);
299 DRIVER_MODULE(if_xl, pci, xl_driver, xl_devclass, NULL, NULL);
300 DRIVER_MODULE(if_xl, cardbus, xl_driver, xl_devclass, NULL, NULL);
301 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, NULL, NULL);
304 xl_enable_intrs(struct xl_softc *sc, uint16_t intrs)
306 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK | 0xFF);
307 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB | intrs);
308 if (sc->xl_flags & XL_FLAG_FUNCREG)
309 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
313 * Murphy's law says that it's possible the chip can wedge and
314 * the 'command in progress' bit may never clear. Hence, we wait
315 * only a finite amount of time to avoid getting caught in an
316 * infinite loop. Normally this delay routine would be a macro,
317 * but it isn't called during normal operation so we can afford
318 * to make it a function.
321 xl_wait(struct xl_softc *sc)
325 for (i = 0; i < XL_TIMEOUT; i++) {
326 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
331 if_printf(&sc->arpcom.ac_if, "command never completed!");
337 * MII access routines are provided for adapters with external
338 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in
339 * autoneg logic that's faked up to look like a PHY (3c905B-TX).
340 * Note: if you don't perform the MDIO operations just right,
341 * it's possible to end up with code that works correctly with
342 * some chips/CPUs/processor speeds/bus speeds/etc but not
346 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
347 CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x))
350 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
351 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x))
354 * Sync the PHYs by setting data bit and strobing the clock 32 times.
357 xl_mii_sync(struct xl_softc *sc)
362 MII_SET(XL_MII_DIR|XL_MII_DATA);
364 for (i = 0; i < 32; i++) {
366 MII_SET(XL_MII_DATA);
367 MII_SET(XL_MII_DATA);
369 MII_SET(XL_MII_DATA);
370 MII_SET(XL_MII_DATA);
377 * Clock a series of bits through the MII.
380 xl_mii_send(struct xl_softc *sc, u_int32_t bits, int cnt)
387 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
389 MII_SET(XL_MII_DATA);
391 MII_CLR(XL_MII_DATA);
399 * Read an PHY register through the MII.
402 xl_mii_readreg(struct xl_softc *sc, struct xl_mii_frame *frame)
407 * Set up frame for RX.
409 frame->mii_stdelim = XL_MII_STARTDELIM;
410 frame->mii_opcode = XL_MII_READOP;
411 frame->mii_turnaround = 0;
415 * Select register window 4.
420 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0);
429 * Send command/address info.
431 xl_mii_send(sc, frame->mii_stdelim, 2);
432 xl_mii_send(sc, frame->mii_opcode, 2);
433 xl_mii_send(sc, frame->mii_phyaddr, 5);
434 xl_mii_send(sc, frame->mii_regaddr, 5);
437 MII_CLR((XL_MII_CLK|XL_MII_DATA));
445 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA;
449 * Now try reading data bits. If the ack failed, we still
450 * need to clock through 16 cycles to keep the PHY(s) in sync.
453 for(i = 0; i < 16; i++) {
460 for (i = 0x8000; i; i >>= 1) {
463 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA)
464 frame->mii_data |= i;
480 * Write to a PHY register through the MII.
483 xl_mii_writereg(struct xl_softc *sc, struct xl_mii_frame *frame)
486 * Set up frame for TX.
489 frame->mii_stdelim = XL_MII_STARTDELIM;
490 frame->mii_opcode = XL_MII_WRITEOP;
491 frame->mii_turnaround = XL_MII_TURNAROUND;
494 * Select the window 4.
499 * Turn on data output.
505 xl_mii_send(sc, frame->mii_stdelim, 2);
506 xl_mii_send(sc, frame->mii_opcode, 2);
507 xl_mii_send(sc, frame->mii_phyaddr, 5);
508 xl_mii_send(sc, frame->mii_regaddr, 5);
509 xl_mii_send(sc, frame->mii_turnaround, 2);
510 xl_mii_send(sc, frame->mii_data, 16);
525 xl_miibus_readreg(device_t dev, int phy, int reg)
528 struct xl_mii_frame frame;
530 sc = device_get_softc(dev);
533 * Pretend that PHYs are only available at MII address 24.
534 * This is to guard against problems with certain 3Com ASIC
535 * revisions that incorrectly map the internal transceiver
536 * control registers at all MII addresses. This can cause
537 * the miibus code to attach the same PHY several times over.
539 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24)
542 bzero((char *)&frame, sizeof(frame));
544 frame.mii_phyaddr = phy;
545 frame.mii_regaddr = reg;
546 xl_mii_readreg(sc, &frame);
548 return(frame.mii_data);
552 xl_miibus_writereg(device_t dev, int phy, int reg, int data)
555 struct xl_mii_frame frame;
557 sc = device_get_softc(dev);
559 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24)
562 bzero((char *)&frame, sizeof(frame));
564 frame.mii_phyaddr = phy;
565 frame.mii_regaddr = reg;
566 frame.mii_data = data;
568 xl_mii_writereg(sc, &frame);
574 xl_miibus_statchg(device_t dev)
577 struct mii_data *mii;
579 sc = device_get_softc(dev);
580 mii = device_get_softc(sc->xl_miibus);
582 ASSERT_SERIALIZED(sc->arpcom.ac_if.if_serializer);
586 /* Set ASIC's duplex mode to match the PHY. */
588 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
589 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
591 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
592 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
596 * Special support for the 3c905B-COMBO. This card has 10/100 support
597 * plus BNC and AUI ports. This means we will have both an miibus attached
598 * plus some non-MII media settings. In order to allow this, we have to
599 * add the extra media to the miibus's ifmedia struct, but we can't do
600 * that during xl_attach() because the miibus hasn't been attached yet.
601 * So instead, we wait until the miibus probe/attach is done, at which
602 * point we will get a callback telling is that it's safe to add our
606 xl_miibus_mediainit(device_t dev)
609 struct mii_data *mii;
612 sc = device_get_softc(dev);
613 mii = device_get_softc(sc->xl_miibus);
614 ifm = &mii->mii_media;
616 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
618 * Check for a 10baseFL board in disguise.
620 if (sc->xl_type == XL_TYPE_905B &&
621 sc->xl_media == XL_MEDIAOPT_10FL) {
623 device_printf(dev, "found 10baseFL\n");
624 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL, 0, NULL);
625 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL|IFM_HDX, 0, NULL);
626 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
628 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
631 device_printf(dev, "found AUI\n");
632 ifmedia_add(ifm, IFM_ETHER|IFM_10_5, 0, NULL);
636 if (sc->xl_media & XL_MEDIAOPT_BNC) {
638 device_printf(dev, "found BNC\n");
639 ifmedia_add(ifm, IFM_ETHER|IFM_10_2, 0, NULL);
646 * The EEPROM is slow: give it time to come ready after issuing
650 xl_eeprom_wait(struct xl_softc *sc)
654 for (i = 0; i < 100; i++) {
655 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY)
662 if_printf(&sc->arpcom.ac_if, "eeprom failed to come ready\n");
670 * Read a sequence of words from the EEPROM. Note that ethernet address
671 * data is stored in the EEPROM in network byte order.
674 xl_read_eeprom(struct xl_softc *sc, caddr_t dest, int off, int cnt, int swap)
677 u_int16_t word = 0, *ptr;
678 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F))
679 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F)
681 * It's easy to accidentally overwrite the rom content!
682 * Note: the 3c575 uses 8bit EEPROM offsets.
686 if (xl_eeprom_wait(sc))
689 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30)
692 for (i = 0; i < cnt; i++) {
693 if (sc->xl_flags & XL_FLAG_8BITROM)
694 CSR_WRITE_2(sc, XL_W0_EE_CMD,
695 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i));
697 CSR_WRITE_2(sc, XL_W0_EE_CMD,
698 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i));
699 err = xl_eeprom_wait(sc);
702 word = CSR_READ_2(sc, XL_W0_EE_DATA);
703 ptr = (u_int16_t *)(dest + (i * 2));
714 * NICs older than the 3c905B have only one multicast option, which
715 * is to enable reception of all multicast frames.
718 xl_setmulti(struct xl_softc *sc)
721 struct ifmultiaddr *ifma;
725 ifp = &sc->arpcom.ac_if;
728 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
730 if (ifp->if_flags & IFF_ALLMULTI) {
731 rxfilt |= XL_RXFILTER_ALLMULTI;
732 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
736 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link)
740 rxfilt |= XL_RXFILTER_ALLMULTI;
742 rxfilt &= ~XL_RXFILTER_ALLMULTI;
744 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
750 * 3c905B adapters have a hash filter that we can program.
753 xl_setmulti_hash(struct xl_softc *sc)
757 struct ifmultiaddr *ifma;
761 ifp = &sc->arpcom.ac_if;
764 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
766 if (ifp->if_flags & IFF_ALLMULTI) {
767 rxfilt |= XL_RXFILTER_ALLMULTI;
768 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
771 rxfilt &= ~XL_RXFILTER_ALLMULTI;
774 /* first, zot all the existing hash bits */
775 for (i = 0; i < XL_HASHFILT_SIZE; i++)
776 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i);
778 /* now program new ones */
779 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
780 if (ifma->ifma_addr->sa_family != AF_LINK)
784 * Note: the 3c905B currently only supports a 64-bit
785 * hash table, which means we really only need 6 bits,
786 * but the manual indicates that future chip revisions
787 * will have a 256-bit hash table, hence the routine is
788 * set up to calculate 8 bits of position info in case
789 * we need it some day.
790 * Note II, The Sequel: _CURRENT_ versions of the 3c905B
791 * have a 256 bit hash table. This means we have to use
792 * all 8 bits regardless. On older cards, the upper 2
793 * bits will be ignored. Grrrr....
796 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
797 ETHER_ADDR_LEN) & 0xff;
798 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|XL_HASH_SET|h);
803 rxfilt |= XL_RXFILTER_MULTIHASH;
805 rxfilt &= ~XL_RXFILTER_MULTIHASH;
807 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
814 xl_testpacket(struct xl_softc *sc)
819 ifp = &sc->arpcom.ac_if;
821 MGETHDR(m, MB_DONTWAIT, MT_DATA);
826 bcopy(&sc->arpcom.ac_enaddr,
827 mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN);
828 bcopy(&sc->arpcom.ac_enaddr,
829 mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN);
830 mtod(m, struct ether_header *)->ether_type = htons(3);
831 mtod(m, unsigned char *)[14] = 0;
832 mtod(m, unsigned char *)[15] = 0;
833 mtod(m, unsigned char *)[16] = 0xE3;
834 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3;
835 IF_ENQUEUE(&ifp->if_snd, m);
843 xl_setcfg(struct xl_softc *sc)
848 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
849 icfg &= ~XL_ICFG_CONNECTOR_MASK;
850 if (sc->xl_media & XL_MEDIAOPT_MII ||
851 sc->xl_media & XL_MEDIAOPT_BT4)
852 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS);
853 if (sc->xl_media & XL_MEDIAOPT_BTX)
854 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS);
856 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
857 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
863 xl_setmode(struct xl_softc *sc, int media)
865 struct ifnet *ifp = &sc->arpcom.ac_if;
869 if_printf(ifp, "selecting ");
872 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
874 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
876 if (sc->xl_media & XL_MEDIAOPT_BT) {
877 if (IFM_SUBTYPE(media) == IFM_10_T) {
878 kprintf("10baseT transceiver, ");
879 sc->xl_xcvr = XL_XCVR_10BT;
880 icfg &= ~XL_ICFG_CONNECTOR_MASK;
881 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS);
882 mediastat |= XL_MEDIASTAT_LINKBEAT|
883 XL_MEDIASTAT_JABGUARD;
884 mediastat &= ~XL_MEDIASTAT_SQEENB;
888 if (sc->xl_media & XL_MEDIAOPT_BFX) {
889 if (IFM_SUBTYPE(media) == IFM_100_FX) {
890 kprintf("100baseFX port, ");
891 sc->xl_xcvr = XL_XCVR_100BFX;
892 icfg &= ~XL_ICFG_CONNECTOR_MASK;
893 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS);
894 mediastat |= XL_MEDIASTAT_LINKBEAT;
895 mediastat &= ~XL_MEDIASTAT_SQEENB;
899 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
900 if (IFM_SUBTYPE(media) == IFM_10_5) {
901 kprintf("AUI port, ");
902 sc->xl_xcvr = XL_XCVR_AUI;
903 icfg &= ~XL_ICFG_CONNECTOR_MASK;
904 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
905 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
906 XL_MEDIASTAT_JABGUARD);
907 mediastat |= ~XL_MEDIASTAT_SQEENB;
909 if (IFM_SUBTYPE(media) == IFM_10_FL) {
910 kprintf("10baseFL transceiver, ");
911 sc->xl_xcvr = XL_XCVR_AUI;
912 icfg &= ~XL_ICFG_CONNECTOR_MASK;
913 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
914 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
915 XL_MEDIASTAT_JABGUARD);
916 mediastat |= ~XL_MEDIASTAT_SQEENB;
920 if (sc->xl_media & XL_MEDIAOPT_BNC) {
921 if (IFM_SUBTYPE(media) == IFM_10_2) {
922 kprintf("BNC port, ");
923 sc->xl_xcvr = XL_XCVR_COAX;
924 icfg &= ~XL_ICFG_CONNECTOR_MASK;
925 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS);
926 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
927 XL_MEDIASTAT_JABGUARD|
928 XL_MEDIASTAT_SQEENB);
932 if ((media & IFM_GMASK) == IFM_FDX ||
933 IFM_SUBTYPE(media) == IFM_100_FX) {
934 kprintf("full duplex\n");
936 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
938 kprintf("half duplex\n");
940 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
941 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
944 if (IFM_SUBTYPE(media) == IFM_10_2)
945 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
947 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
948 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
950 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat);
956 xl_reset(struct xl_softc *sc)
961 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET |
962 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ?
963 XL_RESETOPT_DISADVFD:0));
966 * If we're using memory mapped register mode, pause briefly
967 * after issuing the reset command before trying to access any
968 * other registers. With my 3c575C cardbus card, failing to do
969 * this results in the system locking up while trying to poll
970 * the command busy bit in the status register.
972 if (sc->xl_flags & XL_FLAG_USE_MMIO)
975 for (i = 0; i < XL_TIMEOUT; i++) {
977 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
982 if_printf(&sc->arpcom.ac_if, "reset didn't complete\n");
984 /* Reset TX and RX. */
985 /* Note: the RX reset takes an absurd amount of time
986 * on newer versions of the Tornado chips such as those
987 * on the 3c905CX and newer 3c908C cards. We wait an
988 * extra amount of time so that xl_wait() doesn't complain
989 * and annoy the users.
991 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
994 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
997 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR ||
998 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) {
1000 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, CSR_READ_2(sc,
1001 XL_W2_RESET_OPTIONS)
1002 | ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR)?XL_RESETOPT_INVERT_LED:0)
1003 | ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR)?XL_RESETOPT_INVERT_MII:0)
1007 /* Wait a little while for the chip to get its brains in order. */
1013 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device
1014 * IDs against our list and return a device name if we find a match.
1017 xl_probe(device_t dev)
1022 vid = pci_get_vendor(dev);
1023 did = pci_get_device(dev);
1024 for (t = xl_devs; t->xl_name != NULL; t++) {
1025 if (vid == t->xl_vid && did == t->xl_did) {
1026 device_set_desc(dev, t->xl_name);
1034 * This routine is a kludge to work around possible hardware faults
1035 * or manufacturing defects that can cause the media options register
1036 * (or reset options register, as it's called for the first generation
1037 * 3c90x adapters) to return an incorrect result. I have encountered
1038 * one Dell Latitude laptop docking station with an integrated 3c905-TX
1039 * which doesn't have any of the 'mediaopt' bits set. This screws up
1040 * the attach routine pretty badly because it doesn't know what media
1041 * to look for. If we find ourselves in this predicament, this routine
1042 * will try to guess the media options values and warn the user of a
1043 * possible manufacturing defect with his adapter/system/whatever.
1046 xl_mediacheck(struct xl_softc *sc)
1048 struct ifnet *ifp = &sc->arpcom.ac_if;
1051 * If some of the media options bits are set, assume they are
1052 * correct. If not, try to figure it out down below.
1053 * XXX I should check for 10baseFL, but I don't have an adapter
1056 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) {
1058 * Check the XCVR value. If it's not in the normal range
1059 * of values, we need to fake it up here.
1061 if (sc->xl_xcvr <= XL_XCVR_AUTO)
1064 if_printf(ifp, "bogus xcvr value in EEPROM (%x)\n",
1067 "choosing new default based on card type\n");
1070 if (sc->xl_type == XL_TYPE_905B &&
1071 sc->xl_media & XL_MEDIAOPT_10FL)
1073 if_printf(ifp, "WARNING: no media options bits set in "
1074 "the media options register!!\n");
1075 if_printf(ifp, "this could be a manufacturing defect in "
1076 "your adapter or system\n");
1077 if_printf(ifp, "attempting to guess media type; you "
1078 "should probably consult your vendor\n");
1081 xl_choose_xcvr(sc, 1);
1085 xl_choose_xcvr(struct xl_softc *sc, int verbose)
1087 struct ifnet *ifp = &sc->arpcom.ac_if;
1091 * Read the device ID from the EEPROM.
1092 * This is what's loaded into the PCI device ID register, so it has
1093 * to be correct otherwise we wouldn't have gotten this far.
1095 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0);
1098 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */
1099 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */
1100 sc->xl_media = XL_MEDIAOPT_BT;
1101 sc->xl_xcvr = XL_XCVR_10BT;
1103 if_printf(ifp, "guessing 10BaseT transceiver\n");
1105 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */
1106 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */
1107 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1108 sc->xl_xcvr = XL_XCVR_10BT;
1110 if_printf(ifp, "guessing COMBO (AUI/BNC/TP)\n");
1112 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */
1113 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC;
1114 sc->xl_xcvr = XL_XCVR_10BT;
1116 if_printf(ifp, "guessing TPC (BNC/TP)\n");
1118 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */
1119 sc->xl_media = XL_MEDIAOPT_10FL;
1120 sc->xl_xcvr = XL_XCVR_AUI;
1122 if_printf(ifp, "guessing 10baseFL\n");
1124 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */
1125 case TC_DEVICEID_HURRICANE_555: /* 3c555 */
1126 case TC_DEVICEID_HURRICANE_556: /* 3c556 */
1127 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */
1128 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */
1129 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */
1130 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */
1131 case TC_DEVICEID_HURRICANE_656: /* 3c656 */
1132 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */
1133 case TC_DEVICEID_TORNADO_656C: /* 3c656C */
1134 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */
1135 sc->xl_media = XL_MEDIAOPT_MII;
1136 sc->xl_xcvr = XL_XCVR_MII;
1138 if_printf(ifp, "guessing MII\n");
1140 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */
1141 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */
1142 sc->xl_media = XL_MEDIAOPT_BT4;
1143 sc->xl_xcvr = XL_XCVR_MII;
1145 if_printf(ifp, "guessing 100BaseT4/MII\n");
1147 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */
1148 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */
1149 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */
1150 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */
1151 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */
1152 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */
1153 sc->xl_media = XL_MEDIAOPT_BTX;
1154 sc->xl_xcvr = XL_XCVR_AUTO;
1156 if_printf(ifp, "guessing 10/100 internal\n");
1158 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */
1159 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1160 sc->xl_xcvr = XL_XCVR_AUTO;
1162 if_printf(ifp, "guessing 10/100 plus BNC/AUI\n");
1166 "unknown device ID: %x -- defaulting to 10baseT\n", devid);
1167 sc->xl_media = XL_MEDIAOPT_BT;
1175 * Attach the interface. Allocate softc structures, do ifmedia
1176 * setup and ethernet/BPF attach.
1179 xl_attach(device_t dev)
1181 u_char eaddr[ETHER_ADDR_LEN];
1183 struct xl_softc *sc;
1185 int media = IFM_ETHER|IFM_100_TX|IFM_FDX;
1186 int error = 0, rid, res;
1189 sc = device_get_softc(dev);
1191 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts);
1193 did = pci_get_device(dev);
1196 if (did == TC_DEVICEID_HURRICANE_555)
1197 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK;
1198 if (did == TC_DEVICEID_HURRICANE_556 ||
1199 did == TC_DEVICEID_HURRICANE_556B)
1200 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK |
1201 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET |
1202 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR;
1203 if (did == TC_DEVICEID_HURRICANE_555 ||
1204 did == TC_DEVICEID_HURRICANE_556)
1205 sc->xl_flags |= XL_FLAG_8BITROM;
1206 if (did == TC_DEVICEID_HURRICANE_556B)
1207 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR;
1208 if (did == TC_DEVICEID_HURRICANE_575B ||
1209 did == TC_DEVICEID_HURRICANE_575C ||
1210 did == TC_DEVICEID_HURRICANE_656B ||
1211 did == TC_DEVICEID_TORNADO_656C)
1212 sc->xl_flags |= XL_FLAG_FUNCREG;
1213 if (did == TC_DEVICEID_HURRICANE_575A ||
1214 did == TC_DEVICEID_HURRICANE_575B ||
1215 did == TC_DEVICEID_HURRICANE_575C ||
1216 did == TC_DEVICEID_HURRICANE_656B ||
1217 did == TC_DEVICEID_TORNADO_656C)
1218 sc->xl_flags |= XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 |
1220 if (did == TC_DEVICEID_HURRICANE_656)
1221 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK;
1222 if (did == TC_DEVICEID_HURRICANE_575B)
1223 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR;
1224 if (did == TC_DEVICEID_HURRICANE_575C)
1225 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1226 if (did == TC_DEVICEID_TORNADO_656C)
1227 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1228 if (did == TC_DEVICEID_HURRICANE_656 ||
1229 did == TC_DEVICEID_HURRICANE_656B)
1230 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR |
1231 XL_FLAG_INVERT_LED_PWR;
1232 if (did == TC_DEVICEID_TORNADO_10_100BT_920B)
1233 sc->xl_flags |= XL_FLAG_PHYOK;
1234 #ifndef BURN_BRIDGES
1236 * If this is a 3c905B, we have to check one extra thing.
1237 * The 905B supports power management and may be placed in
1238 * a low-power mode (D3 mode), typically by certain operating
1239 * systems which shall not be named. The PCI BIOS is supposed
1240 * to reset the NIC and bring it out of low-power mode, but
1241 * some do not. Consequently, we have to see if this chip
1242 * supports power management, and if so, make sure it's not
1243 * in low-power mode. If power management is available, the
1244 * capid byte will be 0x01.
1246 * I _think_ that what actually happens is that the chip
1247 * loses its PCI configuration during the transition from
1248 * D3 back to D0; this means that it should be possible for
1249 * us to save the PCI iobase, membase and IRQ, put the chip
1250 * back in the D0 state, then restore the PCI config ourselves.
1253 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1254 u_int32_t iobase, membase, irq;
1256 /* Save important PCI config data. */
1257 iobase = pci_read_config(dev, XL_PCI_LOIO, 4);
1258 membase = pci_read_config(dev, XL_PCI_LOMEM, 4);
1259 irq = pci_read_config(dev, XL_PCI_INTLINE, 4);
1261 /* Reset the power state. */
1262 device_printf(dev, "chip is in D%d power mode "
1263 "-- setting to D0\n", pci_get_powerstate(dev));
1265 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1267 /* Restore PCI config data. */
1268 pci_write_config(dev, XL_PCI_LOIO, iobase, 4);
1269 pci_write_config(dev, XL_PCI_LOMEM, membase, 4);
1270 pci_write_config(dev, XL_PCI_INTLINE, irq, 4);
1274 * Map control/status registers.
1276 pci_enable_busmaster(dev);
1279 res = SYS_RES_MEMORY;
1282 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1285 if (sc->xl_res != NULL) {
1286 sc->xl_flags |= XL_FLAG_USE_MMIO;
1288 device_printf(dev, "using memory mapped I/O\n");
1291 res = SYS_RES_IOPORT;
1292 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1293 if (sc->xl_res == NULL) {
1294 device_printf(dev, "couldn't map ports/memory\n");
1299 device_printf(dev, "using port I/O\n");
1302 sc->xl_btag = rman_get_bustag(sc->xl_res);
1303 sc->xl_bhandle = rman_get_bushandle(sc->xl_res);
1305 if (sc->xl_flags & XL_FLAG_FUNCREG) {
1306 rid = XL_PCI_FUNCMEM;
1307 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1310 if (sc->xl_fres == NULL) {
1311 device_printf(dev, "couldn't map funcreg memory\n");
1316 sc->xl_ftag = rman_get_bustag(sc->xl_fres);
1317 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres);
1320 /* Allocate interrupt */
1322 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1323 RF_SHAREABLE | RF_ACTIVE);
1324 if (sc->xl_irq == NULL) {
1325 device_printf(dev, "couldn't map interrupt\n");
1330 ifp = &sc->arpcom.ac_if;
1331 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1333 /* Reset the adapter. */
1337 * Get station address from the EEPROM.
1339 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) {
1340 device_printf(dev, "failed to read station address\n");
1345 callout_init(&sc->xl_stat_timer);
1347 error = xl_dma_alloc(dev);
1352 * Figure out the card type. 3c905B adapters have the
1353 * 'supportsNoTxLength' bit set in the capabilities
1354 * word in the EEPROM.
1355 * Note: my 3c575C cardbus card lies. It returns a value
1356 * of 0x1578 for its capabilities word, which is somewhat
1357 * nonsensical. Another way to distinguish a 3c90x chip
1358 * from a 3c90xB/C chip is to check for the 'supportsLargePackets'
1359 * bit. This will only be set for 3c90x boomerage chips.
1361 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0);
1362 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH ||
1363 !(sc->xl_caps & XL_CAPS_LARGE_PKTS))
1364 sc->xl_type = XL_TYPE_905B;
1366 sc->xl_type = XL_TYPE_90X;
1368 device_printf(dev, "type %s\n",
1369 sc->xl_type == XL_TYPE_905B ? "90XB" : "90X");
1373 ifp->if_mtu = ETHERMTU;
1374 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1375 ifp->if_ioctl = xl_ioctl;
1376 if (sc->xl_type == XL_TYPE_905B) {
1377 ifp->if_start = xl_start_90xB;
1378 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_VLAN_MTU;
1380 ifp->if_start = xl_start;
1382 ifp->if_watchdog = xl_watchdog;
1383 ifp->if_init = xl_init;
1384 #ifdef DEVICE_POLLING
1385 ifp->if_poll = xl_poll;
1387 ifp->if_baudrate = 10000000;
1388 ifq_set_maxlen(&ifp->if_snd, XL_TX_LIST_CNT - 1);
1389 ifq_set_ready(&ifp->if_snd);
1391 * NOTE: Hardware checksum features disabled by default.
1392 * This seems to corrupt tx packet data one out of a
1393 * million packets or so and then generates a good checksum
1394 * so the receiver doesn't know the packet is bad
1396 ifp->if_capenable = ifp->if_capabilities & ~IFCAP_HWCSUM;
1397 if (ifp->if_capenable & IFCAP_TXCSUM)
1398 ifp->if_hwassist = XL905B_CSUM_FEATURES;
1401 * Now we have to see what sort of media we have.
1402 * This includes probing for an MII interace and a
1406 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT);
1408 if_printf(ifp, "media options word: %x\n", sc->xl_media);
1410 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0);
1411 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16;
1412 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK;
1413 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS;
1417 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX
1418 || sc->xl_media & XL_MEDIAOPT_BT4) {
1420 if_printf(ifp, "found MII/AUTO\n");
1423 error = mii_phy_probe(dev, &sc->xl_miibus,
1424 xl_ifmedia_upd, xl_ifmedia_sts);
1426 if_printf(ifp, "no PHY found!\n");
1434 * Sanity check. If the user has selected "auto" and this isn't
1435 * a 10/100 card of some kind, we need to force the transceiver
1436 * type to something sane.
1438 if (sc->xl_xcvr == XL_XCVR_AUTO)
1439 xl_choose_xcvr(sc, bootverbose);
1444 if (sc->xl_media & XL_MEDIAOPT_BT) {
1446 if_printf(ifp, "found 10baseT\n");
1447 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1448 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1449 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1450 ifmedia_add(&sc->ifmedia,
1451 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1454 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
1456 * Check for a 10baseFL board in disguise.
1458 if (sc->xl_type == XL_TYPE_905B &&
1459 sc->xl_media == XL_MEDIAOPT_10FL) {
1461 if_printf(ifp, "found 10baseFL\n");
1462 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL);
1463 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX,
1465 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1466 ifmedia_add(&sc->ifmedia,
1467 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
1470 if_printf(ifp, "found AUI\n");
1471 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1475 if (sc->xl_media & XL_MEDIAOPT_BNC) {
1477 if_printf(ifp, "found BNC\n");
1478 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL);
1481 if (sc->xl_media & XL_MEDIAOPT_BFX) {
1483 if_printf(ifp, "found 100baseFX\n");
1484 ifp->if_baudrate = 100000000;
1485 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL);
1488 /* Choose a default media. */
1489 switch(sc->xl_xcvr) {
1491 media = IFM_ETHER|IFM_10_T;
1492 xl_setmode(sc, media);
1495 if (sc->xl_type == XL_TYPE_905B &&
1496 sc->xl_media == XL_MEDIAOPT_10FL) {
1497 media = IFM_ETHER|IFM_10_FL;
1498 xl_setmode(sc, media);
1500 media = IFM_ETHER|IFM_10_5;
1501 xl_setmode(sc, media);
1505 media = IFM_ETHER|IFM_10_2;
1506 xl_setmode(sc, media);
1509 case XL_XCVR_100BTX:
1511 /* Chosen by miibus */
1513 case XL_XCVR_100BFX:
1514 media = IFM_ETHER|IFM_100_FX;
1517 if_printf(ifp, "unknown XCVR type: %d\n", sc->xl_xcvr);
1519 * This will probably be wrong, but it prevents
1520 * the ifmedia code from panicking.
1522 media = IFM_ETHER|IFM_10_T;
1526 if (sc->xl_miibus == NULL)
1527 ifmedia_set(&sc->ifmedia, media);
1531 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) {
1533 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS);
1537 * Call MI attach routine.
1539 ether_ifattach(ifp, eaddr, NULL);
1542 * Tell the upper layer(s) we support long frames.
1544 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1546 /* Hook interrupt last to avoid having to lock softc */
1547 error = bus_setup_intr(dev, sc->xl_irq, INTR_MPSAFE,
1548 xl_intr, sc, &sc->xl_intrhand,
1549 ifp->if_serializer);
1551 if_printf(ifp, "couldn't set up irq\n");
1552 ether_ifdetach(ifp);
1556 ifp->if_cpuid = rman_get_cpuid(sc->xl_irq);
1557 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
1567 * Shutdown hardware and free up resources. This can be called any
1568 * time after the mutex has been initialized. It is called in both
1569 * the error case in attach and the normal detach case so it needs
1570 * to be careful about only freeing resources that have actually been
1574 xl_detach(device_t dev)
1576 struct xl_softc *sc;
1580 sc = device_get_softc(dev);
1581 ifp = &sc->arpcom.ac_if;
1583 if (sc->xl_flags & XL_FLAG_USE_MMIO) {
1585 res = SYS_RES_MEMORY;
1588 res = SYS_RES_IOPORT;
1591 if (device_is_attached(dev)) {
1592 lwkt_serialize_enter(ifp->if_serializer);
1595 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand);
1596 lwkt_serialize_exit(ifp->if_serializer);
1598 ether_ifdetach(ifp);
1602 device_delete_child(dev, sc->xl_miibus);
1603 bus_generic_detach(dev);
1604 ifmedia_removeall(&sc->ifmedia);
1607 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1608 if (sc->xl_fres != NULL)
1609 bus_release_resource(dev, SYS_RES_MEMORY,
1610 XL_PCI_FUNCMEM, sc->xl_fres);
1612 bus_release_resource(dev, res, rid, sc->xl_res);
1620 xl_dma_alloc(device_t dev)
1622 struct xl_softc *sc;
1623 struct xl_chain_data *cd;
1624 struct xl_list_data *ld;
1628 sc = device_get_softc(dev);
1633 * Allocate the parent bus DMA tag appropriate for PCI.
1635 error = bus_dma_tag_create(NULL, 1, 0,
1636 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1638 BUS_SPACE_MAXSIZE_32BIT, 0,
1639 BUS_SPACE_MAXSIZE_32BIT,
1640 0, &sc->xl_parent_tag);
1642 device_printf(dev, "could not allocate parent dma tag\n");
1647 * Now allocate a tag for the DMA descriptor lists and a chunk
1648 * of DMA-able memory based on the tag. Also obtain the DMA
1649 * addresses of the RX and TX ring, which we'll need later.
1650 * All of our lists are allocated as a contiguous block
1653 error = bus_dmamem_coherent(sc->xl_parent_tag, XL_LIST_ALIGN, 0,
1654 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1655 XL_RX_LIST_SZ, BUS_DMA_WAITOK, &dmem);
1657 device_printf(dev, "failed to allocate rx list\n");
1660 ld->xl_rx_tag = dmem.dmem_tag;
1661 ld->xl_rx_dmamap = dmem.dmem_map;
1662 ld->xl_rx_list = dmem.dmem_addr;
1663 ld->xl_rx_dmaaddr = dmem.dmem_busaddr;
1665 error = bus_dmamem_coherent(sc->xl_parent_tag, XL_LIST_ALIGN, 0,
1666 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1667 XL_TX_LIST_SZ, BUS_DMA_WAITOK, &dmem);
1669 device_printf(dev, "failed to allocate tx list\n");
1672 ld->xl_tx_tag = dmem.dmem_tag;
1673 ld->xl_tx_dmamap = dmem.dmem_map;
1674 ld->xl_tx_list = dmem.dmem_addr;
1675 ld->xl_tx_dmaaddr = dmem.dmem_busaddr;
1678 * Allocate a DMA tag for the mapping of mbufs.
1680 error = bus_dma_tag_create(sc->xl_parent_tag, 1, 0,
1681 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1683 MCLBYTES, 1, MCLBYTES,
1684 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW,
1687 device_printf(dev, "failed to allocate RX mbuf dma tag\n");
1692 * Allocate a spare DMA map for the RX ring.
1694 error = bus_dmamap_create(sc->xl_rx_mtag, BUS_DMA_WAITOK,
1697 device_printf(dev, "failed to create RX mbuf tmp dma map\n");
1698 bus_dma_tag_destroy(sc->xl_rx_mtag);
1699 sc->xl_rx_mtag = NULL;
1703 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1704 error = bus_dmamap_create(sc->xl_rx_mtag, BUS_DMA_WAITOK,
1705 &cd->xl_rx_chain[i].xl_map);
1707 device_printf(dev, "failed to create %dth "
1708 "rx descriptor dma map!\n", i);
1711 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i];
1714 error = bus_dma_tag_create(sc->xl_parent_tag, 1, 0,
1715 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1717 MCLBYTES, XL_MAXFRAGS, MCLBYTES,
1718 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
1721 device_printf(dev, "failed to allocate TX mbuf dma tag\n");
1725 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1726 error = bus_dmamap_create(sc->xl_tx_mtag, BUS_DMA_WAITOK,
1727 &cd->xl_tx_chain[i].xl_map);
1729 device_printf(dev, "failed to create %dth "
1730 "tx descriptor dma map!\n", i);
1733 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1739 xl_dma_free(device_t dev)
1741 struct xl_softc *sc;
1742 struct xl_chain_data *cd;
1743 struct xl_list_data *ld;
1746 sc = device_get_softc(dev);
1750 for (i = 0; i < XL_RX_LIST_CNT; ++i) {
1751 if (cd->xl_rx_chain[i].xl_ptr != NULL) {
1752 if (cd->xl_rx_chain[i].xl_mbuf != NULL) {
1753 bus_dmamap_unload(sc->xl_rx_mtag,
1754 cd->xl_rx_chain[i].xl_map);
1755 m_freem(cd->xl_rx_chain[i].xl_mbuf);
1757 bus_dmamap_destroy(sc->xl_rx_mtag,
1758 cd->xl_rx_chain[i].xl_map);
1762 for (i = 0; i < XL_TX_LIST_CNT; ++i) {
1763 if (cd->xl_tx_chain[i].xl_ptr != NULL) {
1764 if (cd->xl_tx_chain[i].xl_mbuf != NULL) {
1765 bus_dmamap_unload(sc->xl_tx_mtag,
1766 cd->xl_tx_chain[i].xl_map);
1767 m_freem(cd->xl_tx_chain[i].xl_mbuf);
1769 bus_dmamap_destroy(sc->xl_tx_mtag,
1770 cd->xl_tx_chain[i].xl_map);
1774 if (ld->xl_rx_tag) {
1775 bus_dmamap_unload(ld->xl_rx_tag, ld->xl_rx_dmamap);
1776 bus_dmamem_free(ld->xl_rx_tag, ld->xl_rx_list,
1778 bus_dma_tag_destroy(ld->xl_rx_tag);
1781 if (ld->xl_tx_tag) {
1782 bus_dmamap_unload(ld->xl_tx_tag, ld->xl_tx_dmamap);
1783 bus_dmamem_free(ld->xl_tx_tag, ld->xl_tx_list,
1785 bus_dma_tag_destroy(ld->xl_tx_tag);
1788 if (sc->xl_rx_mtag) {
1789 bus_dmamap_destroy(sc->xl_rx_mtag, sc->xl_tmpmap);
1790 bus_dma_tag_destroy(sc->xl_rx_mtag);
1793 bus_dma_tag_destroy(sc->xl_tx_mtag);
1795 if (sc->xl_parent_tag)
1796 bus_dma_tag_destroy(sc->xl_parent_tag);
1800 * Initialize the transmit descriptors.
1803 xl_list_tx_init(struct xl_softc *sc)
1805 struct xl_chain_data *cd;
1806 struct xl_list_data *ld;
1811 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1812 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1813 i * sizeof(struct xl_list);
1814 if (i == (XL_TX_LIST_CNT - 1))
1815 cd->xl_tx_chain[i].xl_next = NULL;
1817 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1820 cd->xl_tx_free = &cd->xl_tx_chain[0];
1821 cd->xl_tx_tail = cd->xl_tx_head = NULL;
1825 * Initialize the transmit descriptors.
1828 xl_list_tx_init_90xB(struct xl_softc *sc)
1830 struct xl_chain_data *cd;
1831 struct xl_list_data *ld;
1836 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1837 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1838 i * sizeof(struct xl_list);
1839 if (i == (XL_TX_LIST_CNT - 1))
1840 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0];
1842 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1844 cd->xl_tx_chain[i].xl_prev =
1845 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1];
1847 cd->xl_tx_chain[i].xl_prev =
1848 &cd->xl_tx_chain[i - 1];
1852 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY);
1860 * Initialize the RX descriptors and allocate mbufs for them. Note that
1861 * we arrange the descriptors in a closed ring, so that the last descriptor
1862 * points back to the first.
1865 xl_list_rx_init(struct xl_softc *sc)
1867 struct xl_chain_data *cd;
1868 struct xl_list_data *ld;
1875 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1876 error = xl_newbuf(sc, &cd->xl_rx_chain[i], 1);
1879 if (i == (XL_RX_LIST_CNT - 1))
1883 nextptr = ld->xl_rx_dmaaddr +
1884 next * sizeof(struct xl_list_onefrag);
1885 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next];
1886 ld->xl_rx_list[i].xl_next = htole32(nextptr);
1889 cd->xl_rx_head = &cd->xl_rx_chain[0];
1895 * Initialize an RX descriptor and attach an MBUF cluster.
1896 * If we fail to do so, we need to leave the old mbuf and
1897 * the old DMA map untouched so that it can be reused.
1900 xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c, int init)
1905 bus_dma_segment_t seg;
1907 m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
1911 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1913 /* Force longword alignment for packet payload. */
1914 m_adj(m_new, ETHER_ALIGN);
1916 error = bus_dmamap_load_mbuf_segment(sc->xl_rx_mtag, sc->xl_tmpmap,
1917 m_new, &seg, 1, &nsegs, BUS_DMA_NOWAIT);
1921 if_printf(&sc->arpcom.ac_if,
1922 "can't map mbuf (error %d)\n", error);
1927 if (c->xl_mbuf != NULL) {
1928 bus_dmamap_sync(sc->xl_rx_mtag, c->xl_map,
1929 BUS_DMASYNC_POSTREAD);
1930 bus_dmamap_unload(sc->xl_rx_mtag, c->xl_map);
1934 c->xl_map = sc->xl_tmpmap;
1935 sc->xl_tmpmap = map;
1938 c->xl_ptr->xl_frag.xl_len = htole32(seg.ds_len | XL_LAST_FRAG);
1939 c->xl_ptr->xl_frag.xl_addr = htole32(seg.ds_addr);
1940 c->xl_ptr->xl_status = 0;
1946 xl_rx_resync(struct xl_softc *sc)
1948 struct xl_chain_onefrag *pos;
1951 pos = sc->xl_cdata.xl_rx_head;
1953 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1954 if (pos->xl_ptr->xl_status)
1959 if (i == XL_RX_LIST_CNT)
1962 sc->xl_cdata.xl_rx_head = pos;
1968 * A frame has been uploaded: pass the resulting mbuf chain up to
1969 * the higher level protocols.
1972 xl_rxeof(struct xl_softc *sc, int count)
1976 struct xl_chain_onefrag *cur_rx;
1979 struct mbuf_chain chain[MAXCPU];
1981 ifp = &sc->arpcom.ac_if;
1983 ether_input_chain_init(chain);
1985 while((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) {
1986 #ifdef DEVICE_POLLING
1987 if (count >= 0 && count-- == 0)
1990 cur_rx = sc->xl_cdata.xl_rx_head;
1991 sc->xl_cdata.xl_rx_head = cur_rx->xl_next;
1992 total_len = rxstat & XL_RXSTAT_LENMASK;
1995 * Since we have told the chip to allow large frames,
1996 * we need to trap giant frame errors in software. We allow
1997 * a little more than the normal frame size to account for
1998 * frames with VLAN tags.
2000 if (total_len > XL_MAX_FRAMELEN)
2001 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE);
2004 * If an error occurs, update stats, clear the
2005 * status word and leave the mbuf cluster in place:
2006 * it should simply get re-used next time this descriptor
2007 * comes up in the ring.
2009 if (rxstat & XL_RXSTAT_UP_ERROR) {
2011 cur_rx->xl_ptr->xl_status = 0;
2016 * If the error bit was not set, the upload complete
2017 * bit should be set which means we have a valid packet.
2018 * If not, something truly strange has happened.
2020 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) {
2022 "bad receive status -- packet dropped\n");
2024 cur_rx->xl_ptr->xl_status = 0;
2028 /* No errors; receive the packet. */
2029 m = cur_rx->xl_mbuf;
2032 * Try to conjure up a new mbuf cluster. If that
2033 * fails, it means we have an out of memory condition and
2034 * should leave the buffer in place and continue. This will
2035 * result in a lost packet, but there's little else we
2036 * can do in this situation.
2038 if (xl_newbuf(sc, cur_rx, 0)) {
2040 cur_rx->xl_ptr->xl_status = 0;
2045 m->m_pkthdr.rcvif = ifp;
2046 m->m_pkthdr.len = m->m_len = total_len;
2048 if (ifp->if_capenable & IFCAP_RXCSUM) {
2049 /* Do IP checksum checking. */
2050 if (rxstat & XL_RXSTAT_IPCKOK)
2051 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2052 if (!(rxstat & XL_RXSTAT_IPCKERR))
2053 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2054 if ((rxstat & XL_RXSTAT_TCPCOK &&
2055 !(rxstat & XL_RXSTAT_TCPCKERR)) ||
2056 (rxstat & XL_RXSTAT_UDPCKOK &&
2057 !(rxstat & XL_RXSTAT_UDPCKERR))) {
2058 m->m_pkthdr.csum_flags |=
2059 CSUM_DATA_VALID|CSUM_PSEUDO_HDR|
2060 CSUM_FRAG_NOT_CHECKED;
2061 m->m_pkthdr.csum_data = 0xffff;
2065 ether_input_chain(ifp, m, NULL, chain);
2068 if (sc->xl_type != XL_TYPE_905B) {
2070 * Handle the 'end of channel' condition. When the upload
2071 * engine hits the end of the RX ring, it will stall. This
2072 * is our cue to flush the RX ring, reload the uplist pointer
2073 * register and unstall the engine.
2074 * XXX This is actually a little goofy. With the ThunderLAN
2075 * chip, you get an interrupt when the receiver hits the end
2076 * of the receive ring, which tells you exactly when you
2077 * you need to reload the ring pointer. Here we have to
2078 * fake it. I'm mad at myself for not being clever enough
2079 * to avoid the use of a goto here.
2081 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 ||
2082 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) {
2083 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2085 CSR_WRITE_4(sc, XL_UPLIST_PTR,
2086 sc->xl_ldata.xl_rx_dmaaddr);
2087 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0];
2088 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2093 ether_input_dispatch(chain);
2097 * A frame was downloaded to the chip. It's safe for us to clean up
2101 xl_txeof(struct xl_softc *sc)
2103 struct xl_chain *cur_tx;
2106 ifp = &sc->arpcom.ac_if;
2108 /* Clear the timeout timer. */
2112 * Go through our tx list and free mbufs for those
2113 * frames that have been uploaded. Note: the 3c905B
2114 * sets a special bit in the status word to let us
2115 * know that a frame has been downloaded, but the
2116 * original 3c900/3c905 adapters don't do that.
2117 * Consequently, we have to use a different test if
2118 * xl_type != XL_TYPE_905B.
2120 while(sc->xl_cdata.xl_tx_head != NULL) {
2121 cur_tx = sc->xl_cdata.xl_tx_head;
2123 if (CSR_READ_4(sc, XL_DOWNLIST_PTR))
2126 sc->xl_cdata.xl_tx_head = cur_tx->xl_next;
2127 bus_dmamap_unload(sc->xl_tx_mtag, cur_tx->xl_map);
2128 m_freem(cur_tx->xl_mbuf);
2129 cur_tx->xl_mbuf = NULL;
2132 cur_tx->xl_next = sc->xl_cdata.xl_tx_free;
2133 sc->xl_cdata.xl_tx_free = cur_tx;
2136 if (sc->xl_cdata.xl_tx_head == NULL) {
2137 ifp->if_flags &= ~IFF_OACTIVE;
2138 sc->xl_cdata.xl_tx_tail = NULL;
2140 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED ||
2141 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) {
2142 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2143 sc->xl_cdata.xl_tx_head->xl_phys);
2144 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2152 xl_txeof_90xB(struct xl_softc *sc)
2154 struct xl_chain *cur_tx = NULL;
2158 ifp = &sc->arpcom.ac_if;
2160 idx = sc->xl_cdata.xl_tx_cons;
2161 while(idx != sc->xl_cdata.xl_tx_prod) {
2163 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2165 if (!(le32toh(cur_tx->xl_ptr->xl_status) &
2166 XL_TXSTAT_DL_COMPLETE))
2169 if (cur_tx->xl_mbuf != NULL) {
2170 bus_dmamap_unload(sc->xl_tx_mtag, cur_tx->xl_map);
2171 m_freem(cur_tx->xl_mbuf);
2172 cur_tx->xl_mbuf = NULL;
2177 sc->xl_cdata.xl_tx_cnt--;
2178 XL_INC(idx, XL_TX_LIST_CNT);
2182 sc->xl_cdata.xl_tx_cons = idx;
2185 ifp->if_flags &= ~IFF_OACTIVE;
2191 * TX 'end of channel' interrupt handler. Actually, we should
2192 * only get a 'TX complete' interrupt if there's a transmit error,
2193 * so this is really TX error handler.
2196 xl_txeoc(struct xl_softc *sc)
2198 struct ifnet *ifp = &sc->arpcom.ac_if;
2201 while((txstat = CSR_READ_1(sc, XL_TX_STATUS))) {
2202 if (txstat & XL_TXSTATUS_UNDERRUN ||
2203 txstat & XL_TXSTATUS_JABBER ||
2204 txstat & XL_TXSTATUS_RECLAIM) {
2205 if_printf(ifp, "transmission error: %x\n", txstat);
2206 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2208 if (sc->xl_type == XL_TYPE_905B) {
2209 if (sc->xl_cdata.xl_tx_cnt) {
2212 i = sc->xl_cdata.xl_tx_cons;
2213 c = &sc->xl_cdata.xl_tx_chain[i];
2214 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2216 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2219 if (sc->xl_cdata.xl_tx_head != NULL)
2220 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2221 sc->xl_cdata.xl_tx_head->xl_phys);
2224 * Remember to set this for the
2225 * first generation 3c90X chips.
2227 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2228 if (txstat & XL_TXSTATUS_UNDERRUN &&
2229 sc->xl_tx_thresh < XL_PACKET_SIZE) {
2230 sc->xl_tx_thresh += XL_MIN_FRAMELEN;
2231 if_printf(ifp, "tx underrun, increasing tx start"
2232 " threshold to %d bytes\n",
2235 CSR_WRITE_2(sc, XL_COMMAND,
2236 XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2237 if (sc->xl_type == XL_TYPE_905B) {
2238 CSR_WRITE_2(sc, XL_COMMAND,
2239 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2241 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2242 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2244 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2245 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2248 * Write an arbitrary byte to the TX_STATUS register
2249 * to clear this interrupt/error and advance to the next.
2251 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01);
2257 #ifdef DEVICE_POLLING
2260 xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2262 struct xl_softc *sc = ifp->if_softc;
2264 ASSERT_SERIALIZED(ifp->if_serializer);
2268 xl_enable_intrs(sc, 0);
2269 if (sc->xl_type != XL_TYPE_905B)
2270 ifp->if_start = xl_start_poll;
2272 case POLL_DEREGISTER:
2273 if (sc->xl_type != XL_TYPE_905B)
2274 ifp->if_start = xl_start;
2275 xl_enable_intrs(sc, XL_INTRS);
2278 case POLL_AND_CHECK_STATUS:
2279 xl_rxeof(sc, count);
2280 if (sc->xl_type == XL_TYPE_905B)
2285 if (!ifq_is_empty(&ifp->if_snd))
2288 if (cmd == POLL_AND_CHECK_STATUS) {
2291 /* XXX copy & pasted from xl_intr() */
2292 status = CSR_READ_2(sc, XL_STATUS);
2293 if ((status & XL_INTRS) && status != 0xFFFF) {
2294 CSR_WRITE_2(sc, XL_COMMAND,
2295 XL_CMD_INTR_ACK | (status & XL_INTRS));
2297 if (status & XL_STAT_TX_COMPLETE) {
2302 if (status & XL_STAT_ADFAIL) {
2307 if (status & XL_STAT_STATSOFLOW) {
2308 sc->xl_stats_no_timeout = 1;
2309 xl_stats_update_serialized(sc);
2310 sc->xl_stats_no_timeout = 0;
2318 #endif /* DEVICE_POLLING */
2323 struct xl_softc *sc;
2328 ifp = &sc->arpcom.ac_if;
2330 ASSERT_SERIALIZED(ifp->if_serializer);
2332 while(((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS) &&
2335 CSR_WRITE_2(sc, XL_COMMAND,
2336 XL_CMD_INTR_ACK|(status & XL_INTRS));
2338 if (status & XL_STAT_UP_COMPLETE) {
2341 curpkts = ifp->if_ipackets;
2343 if (curpkts == ifp->if_ipackets) {
2344 while (xl_rx_resync(sc))
2349 if (status & XL_STAT_DOWN_COMPLETE) {
2350 if (sc->xl_type == XL_TYPE_905B)
2356 if (status & XL_STAT_TX_COMPLETE) {
2361 if (status & XL_STAT_ADFAIL) {
2366 if (status & XL_STAT_STATSOFLOW) {
2367 sc->xl_stats_no_timeout = 1;
2368 xl_stats_update_serialized(sc);
2369 sc->xl_stats_no_timeout = 0;
2373 if (!ifq_is_empty(&ifp->if_snd))
2378 xl_stats_update(void *xsc)
2380 struct xl_softc *sc = xsc;
2382 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
2383 xl_stats_update_serialized(xsc);
2384 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
2388 xl_stats_update_serialized(void *xsc)
2390 struct xl_softc *sc;
2392 struct xl_stats xl_stats;
2395 struct mii_data *mii = NULL;
2397 bzero((char *)&xl_stats, sizeof(struct xl_stats));
2400 ifp = &sc->arpcom.ac_if;
2401 if (sc->xl_miibus != NULL)
2402 mii = device_get_softc(sc->xl_miibus);
2404 p = (u_int8_t *)&xl_stats;
2406 /* Read all the stats registers. */
2409 for (i = 0; i < 16; i++)
2410 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i);
2412 ifp->if_ierrors += xl_stats.xl_rx_overrun;
2414 ifp->if_collisions += xl_stats.xl_tx_multi_collision +
2415 xl_stats.xl_tx_single_collision +
2416 xl_stats.xl_tx_late_collision;
2419 * Boomerang and cyclone chips have an extra stats counter
2420 * in window 4 (BadSSD). We have to read this too in order
2421 * to clear out all the stats registers and avoid a statsoflow
2425 CSR_READ_1(sc, XL_W4_BADSSD);
2427 if ((mii != NULL) && (!sc->xl_stats_no_timeout))
2432 if (!sc->xl_stats_no_timeout)
2433 callout_reset(&sc->xl_stat_timer, hz, xl_stats_update, sc);
2439 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
2440 * pointers to the fragment pointers.
2443 xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf *m_head)
2445 int error, nsegs, i;
2447 bus_dma_segment_t segs[XL_MAXFRAGS];
2450 error = bus_dmamap_load_mbuf_defrag(sc->xl_tx_mtag, c->xl_map, &m_head,
2451 segs, XL_MAXFRAGS, &nsegs, BUS_DMA_NOWAIT);
2456 bus_dmamap_sync(sc->xl_tx_mtag, c->xl_map, BUS_DMASYNC_PREWRITE);
2458 if (sc->xl_type == XL_TYPE_905B) {
2459 status = XL_TXSTAT_RND_DEFEAT;
2460 if (m_head->m_pkthdr.csum_flags) {
2461 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2462 status |= XL_TXSTAT_IPCKSUM;
2463 if (m_head->m_pkthdr.csum_flags & CSUM_TCP)
2464 status |= XL_TXSTAT_TCPCKSUM;
2465 if (m_head->m_pkthdr.csum_flags & CSUM_UDP)
2466 status |= XL_TXSTAT_UDPCKSUM;
2469 status = m_head->m_pkthdr.len;
2473 for (i = 0; i < nsegs; i++) {
2474 l->xl_frag[i].xl_addr = htole32(segs[i].ds_addr);
2475 l->xl_frag[i].xl_len = htole32(segs[i].ds_len);
2477 l->xl_frag[nsegs - 1].xl_len =
2478 htole32(segs[nsegs - 1].ds_len | XL_LAST_FRAG);
2479 l->xl_status = htole32(status);
2482 c->xl_mbuf = m_head;
2488 xl_start(struct ifnet *ifp)
2490 ASSERT_SERIALIZED(ifp->if_serializer);
2491 xl_start_body(ifp, 1);
2494 #ifdef DEVICE_POLLING
2496 xl_start_poll(struct ifnet *ifp)
2498 xl_start_body(ifp, 0);
2503 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2504 * to the mbuf data regions directly in the transmit lists. We also save a
2505 * copy of the pointers since the transmit list fragment pointers are
2506 * physical addresses.
2509 xl_start_body(struct ifnet *ifp, int proc_rx)
2511 struct xl_softc *sc;
2512 struct mbuf *m_head = NULL;
2513 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2514 struct xl_chain *prev_tx;
2520 * Check for an available queue slot. If there are none,
2523 if (sc->xl_cdata.xl_tx_free == NULL) {
2526 if (sc->xl_cdata.xl_tx_free == NULL) {
2527 ifp->if_flags |= IFF_OACTIVE;
2532 start_tx = sc->xl_cdata.xl_tx_free;
2534 while(sc->xl_cdata.xl_tx_free != NULL) {
2535 m_head = ifq_dequeue(&ifp->if_snd, NULL);
2539 /* Pick a descriptor off the free list. */
2541 cur_tx = sc->xl_cdata.xl_tx_free;
2543 /* Pack the data into the descriptor. */
2544 error = xl_encap(sc, cur_tx, m_head);
2550 sc->xl_cdata.xl_tx_free = cur_tx->xl_next;
2551 cur_tx->xl_next = NULL;
2553 /* Chain it together. */
2555 prev->xl_next = cur_tx;
2556 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2560 BPF_MTAP(ifp, cur_tx->xl_mbuf);
2564 * If there are no packets queued, bail.
2570 * Place the request for the upload interrupt
2571 * in the last descriptor in the chain. This way, if
2572 * we're chaining several packets at once, we'll only
2573 * get an interupt once for the whole chain rather than
2574 * once for each packet.
2576 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) |
2580 * Queue the packets. If the TX channel is clear, update
2581 * the downlist pointer register.
2583 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2586 if (sc->xl_cdata.xl_tx_head != NULL) {
2587 sc->xl_cdata.xl_tx_tail->xl_next = start_tx;
2588 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next =
2589 htole32(start_tx->xl_phys);
2590 status = sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status;
2591 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status =
2592 htole32(le32toh(status) & ~XL_TXSTAT_DL_INTR);
2593 sc->xl_cdata.xl_tx_tail = cur_tx;
2595 sc->xl_cdata.xl_tx_head = start_tx;
2596 sc->xl_cdata.xl_tx_tail = cur_tx;
2599 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR))
2600 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys);
2602 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2607 * Set a timeout in case the chip goes out to lunch.
2613 * XXX Under certain conditions, usually on slower machines
2614 * where interrupts may be dropped, it's possible for the
2615 * adapter to chew up all the buffers in the receive ring
2616 * and stall, without us being able to do anything about it.
2617 * To guard against this, we need to make a pass over the
2618 * RX queue to make sure there aren't any packets pending.
2619 * Doing it here means we can flush the receive ring at the
2620 * same time the chip is DMAing the transmit descriptors we
2623 * 3Com goes to some lengths to emphasize the Parallel
2624 * Tasking (tm) nature of their chips in all their marketing
2625 * literature; we may as well take advantage of it. :)
2632 xl_start_90xB(struct ifnet *ifp)
2634 struct xl_softc *sc;
2635 struct mbuf *m_head = NULL;
2636 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2637 struct xl_chain *prev_tx;
2640 ASSERT_SERIALIZED(ifp->if_serializer);
2644 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING)
2647 idx = sc->xl_cdata.xl_tx_prod;
2648 start_tx = &sc->xl_cdata.xl_tx_chain[idx];
2650 while (sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL) {
2652 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) {
2653 ifp->if_flags |= IFF_OACTIVE;
2657 m_head = ifq_dequeue(&ifp->if_snd, NULL);
2662 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2664 /* Pack the data into the descriptor. */
2665 error = xl_encap(sc, cur_tx, m_head);
2671 /* Chain it together. */
2673 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2676 BPF_MTAP(ifp, cur_tx->xl_mbuf);
2678 XL_INC(idx, XL_TX_LIST_CNT);
2679 sc->xl_cdata.xl_tx_cnt++;
2683 * If there are no packets queued, bail.
2689 * Place the request for the upload interrupt
2690 * in the last descriptor in the chain. This way, if
2691 * we're chaining several packets at once, we'll only
2692 * get an interupt once for the whole chain rather than
2693 * once for each packet.
2695 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) |
2698 /* Start transmission */
2699 sc->xl_cdata.xl_tx_prod = idx;
2700 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys);
2703 * Set a timeout in case the chip goes out to lunch.
2711 struct xl_softc *sc = xsc;
2712 struct ifnet *ifp = &sc->arpcom.ac_if;
2714 u_int16_t rxfilt = 0;
2715 struct mii_data *mii = NULL;
2717 ASSERT_SERIALIZED(ifp->if_serializer);
2720 * Cancel pending I/O and free all RX/TX buffers.
2724 if (sc->xl_miibus == NULL) {
2725 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2728 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2732 if (sc->xl_miibus != NULL)
2733 mii = device_get_softc(sc->xl_miibus);
2735 /* Init our MAC address */
2737 for (i = 0; i < ETHER_ADDR_LEN; i++) {
2738 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i,
2739 sc->arpcom.ac_enaddr[i]);
2742 /* Clear the station mask. */
2743 for (i = 0; i < 3; i++)
2744 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0);
2746 /* Reset TX and RX. */
2747 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2749 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2752 /* Init circular RX list. */
2753 error = xl_list_rx_init(sc);
2755 if_printf(ifp, "initialization of the rx ring failed (%d)\n",
2761 /* Init TX descriptors. */
2762 if (sc->xl_type == XL_TYPE_905B)
2763 xl_list_tx_init_90xB(sc);
2765 xl_list_tx_init(sc);
2768 * Set the TX freethresh value.
2769 * Note that this has no effect on 3c905B "cyclone"
2770 * cards but is required for 3c900/3c905 "boomerang"
2771 * cards in order to enable the download engine.
2773 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2775 /* Set the TX start threshold for best performance. */
2776 sc->xl_tx_thresh = XL_MIN_FRAMELEN;
2777 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2780 * If this is a 3c905B, also set the tx reclaim threshold.
2781 * This helps cut down on the number of tx reclaim errors
2782 * that could happen on a busy network. The chip multiplies
2783 * the register value by 16 to obtain the actual threshold
2784 * in bytes, so we divide by 16 when setting the value here.
2785 * The existing threshold value can be examined by reading
2786 * the register at offset 9 in window 5.
2788 if (sc->xl_type == XL_TYPE_905B) {
2789 CSR_WRITE_2(sc, XL_COMMAND,
2790 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2793 /* Set RX filter bits. */
2795 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
2797 /* Set the individual bit to receive frames for this host only. */
2798 rxfilt |= XL_RXFILTER_INDIVIDUAL;
2800 /* If we want promiscuous mode, set the allframes bit. */
2801 if (ifp->if_flags & IFF_PROMISC) {
2802 rxfilt |= XL_RXFILTER_ALLFRAMES;
2803 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2805 rxfilt &= ~XL_RXFILTER_ALLFRAMES;
2806 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2810 * Set capture broadcast bit to capture broadcast frames.
2812 if (ifp->if_flags & IFF_BROADCAST) {
2813 rxfilt |= XL_RXFILTER_BROADCAST;
2814 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2816 rxfilt &= ~XL_RXFILTER_BROADCAST;
2817 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2821 * Program the multicast filter, if necessary.
2823 if (sc->xl_type == XL_TYPE_905B)
2824 xl_setmulti_hash(sc);
2828 if (sc->xl_type == XL_TYPE_905B) {
2829 /* Set UP polling interval */
2830 CSR_WRITE_1(sc, XL_UP_POLL, 64);
2834 * Load the address of the RX list. We have to
2835 * stall the upload engine before we can manipulate
2836 * the uplist pointer register, then unstall it when
2837 * we're finished. We also have to wait for the
2838 * stall command to complete before proceeding.
2839 * Note that we have to do this after any RX resets
2840 * have completed since the uplist register is cleared
2843 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2845 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
2846 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2849 if (sc->xl_type == XL_TYPE_905B) {
2850 /* Set DN polling interval */
2851 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2853 /* Load the address of the TX list */
2854 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2856 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2857 sc->xl_cdata.xl_tx_chain[0].xl_phys);
2858 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2863 * If the coax transceiver is on, make sure to enable
2864 * the DC-DC converter.
2867 if (sc->xl_xcvr == XL_XCVR_COAX)
2868 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
2870 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
2873 * increase packet size to allow reception of 802.1q or ISL packets.
2874 * For the 3c90x chip, set the 'allow large packets' bit in the MAC
2875 * control register. For 3c90xB/C chips, use the RX packet size
2879 if (sc->xl_type == XL_TYPE_905B) {
2880 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE);
2883 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);
2884 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK;
2885 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl);
2888 /* Clear out the stats counters. */
2889 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
2890 sc->xl_stats_no_timeout = 1;
2891 xl_stats_update_serialized(sc);
2892 sc->xl_stats_no_timeout = 0;
2894 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE);
2895 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE);
2898 * Enable interrupts.
2900 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB | XL_INTRS);
2901 #ifdef DEVICE_POLLING
2902 /* Do not enable interrupt if polling(4) is enabled */
2903 if ((ifp->if_flags & IFF_POLLING) != 0)
2904 xl_enable_intrs(sc, 0);
2907 xl_enable_intrs(sc, XL_INTRS);
2909 /* Set the RX early threshold */
2910 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2));
2911 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY);
2913 /* Enable receiver and transmitter. */
2914 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2916 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
2922 /* Select window 7 for normal operations. */
2925 ifp->if_flags |= IFF_RUNNING;
2926 ifp->if_flags &= ~IFF_OACTIVE;
2928 callout_reset(&sc->xl_stat_timer, hz, xl_stats_update, sc);
2932 * Set media options.
2935 xl_ifmedia_upd(struct ifnet *ifp)
2937 struct xl_softc *sc;
2938 struct ifmedia *ifm = NULL;
2939 struct mii_data *mii = NULL;
2941 ASSERT_SERIALIZED(ifp->if_serializer);
2944 if (sc->xl_miibus != NULL)
2945 mii = device_get_softc(sc->xl_miibus);
2949 ifm = &mii->mii_media;
2951 switch(IFM_SUBTYPE(ifm->ifm_media)) {
2956 xl_setmode(sc, ifm->ifm_media);
2963 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX
2964 || sc->xl_media & XL_MEDIAOPT_BT4) {
2967 xl_setmode(sc, ifm->ifm_media);
2974 * Report current media status.
2977 xl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2979 struct xl_softc *sc;
2981 struct mii_data *mii = NULL;
2983 ASSERT_SERIALIZED(ifp->if_serializer);
2986 if (sc->xl_miibus != NULL)
2987 mii = device_get_softc(sc->xl_miibus);
2990 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK;
2991 icfg >>= XL_ICFG_CONNECTOR_BITS;
2993 ifmr->ifm_active = IFM_ETHER;
2997 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
2998 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
2999 ifmr->ifm_active |= IFM_FDX;
3001 ifmr->ifm_active |= IFM_HDX;
3004 if (sc->xl_type == XL_TYPE_905B &&
3005 sc->xl_media == XL_MEDIAOPT_10FL) {
3006 ifmr->ifm_active = IFM_ETHER|IFM_10_FL;
3007 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
3008 ifmr->ifm_active |= IFM_FDX;
3010 ifmr->ifm_active |= IFM_HDX;
3012 ifmr->ifm_active = IFM_ETHER|IFM_10_5;
3015 ifmr->ifm_active = IFM_ETHER|IFM_10_2;
3018 * XXX MII and BTX/AUTO should be separate cases.
3021 case XL_XCVR_100BTX:
3026 ifmr->ifm_active = mii->mii_media_active;
3027 ifmr->ifm_status = mii->mii_media_status;
3030 case XL_XCVR_100BFX:
3031 ifmr->ifm_active = IFM_ETHER|IFM_100_FX;
3034 if_printf(ifp, "unknown XCVR type: %d\n", icfg);
3042 xl_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3044 struct xl_softc *sc = ifp->if_softc;
3045 struct ifreq *ifr = (struct ifreq *) data;
3047 struct mii_data *mii = NULL;
3050 ASSERT_SERIALIZED(ifp->if_serializer);
3055 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
3056 if (ifp->if_flags & IFF_UP) {
3057 if (ifp->if_flags & IFF_RUNNING &&
3058 ifp->if_flags & IFF_PROMISC &&
3059 !(sc->xl_if_flags & IFF_PROMISC)) {
3060 rxfilt |= XL_RXFILTER_ALLFRAMES;
3061 CSR_WRITE_2(sc, XL_COMMAND,
3062 XL_CMD_RX_SET_FILT|rxfilt);
3064 } else if (ifp->if_flags & IFF_RUNNING &&
3065 !(ifp->if_flags & IFF_PROMISC) &&
3066 sc->xl_if_flags & IFF_PROMISC) {
3067 rxfilt &= ~XL_RXFILTER_ALLFRAMES;
3068 CSR_WRITE_2(sc, XL_COMMAND,
3069 XL_CMD_RX_SET_FILT|rxfilt);
3074 if (ifp->if_flags & IFF_RUNNING)
3077 sc->xl_if_flags = ifp->if_flags;
3082 if (sc->xl_type == XL_TYPE_905B)
3083 xl_setmulti_hash(sc);
3090 if (sc->xl_miibus != NULL)
3091 mii = device_get_softc(sc->xl_miibus);
3093 error = ifmedia_ioctl(ifp, ifr,
3094 &sc->ifmedia, command);
3096 error = ifmedia_ioctl(ifp, ifr,
3097 &mii->mii_media, command);
3100 ifp->if_capenable &= ~IFCAP_HWCSUM;
3101 ifp->if_capenable |= (ifr->ifr_reqcap & IFCAP_HWCSUM);
3102 if (ifp->if_capenable & IFCAP_HWCSUM)
3103 ifp->if_hwassist = XL905B_CSUM_FEATURES;
3105 ifp->if_hwassist = 0;
3108 error = ether_ioctl(ifp, command, data);
3115 xl_watchdog(struct ifnet *ifp)
3117 struct xl_softc *sc;
3118 u_int16_t status = 0;
3120 ASSERT_SERIALIZED(ifp->if_serializer);
3126 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
3127 if_printf(ifp, "watchdog timeout\n");
3129 if (status & XL_MEDIASTAT_CARRIER)
3130 if_printf(ifp, "no carrier - transceiver cable problem?\n");
3137 if (!ifq_is_empty(&ifp->if_snd))
3142 * Stop the adapter and free any mbufs allocated to the
3146 xl_stop(struct xl_softc *sc)
3151 ifp = &sc->arpcom.ac_if;
3152 ASSERT_SERIALIZED(ifp->if_serializer);
3156 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE);
3157 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
3158 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB);
3159 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD);
3161 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE);
3162 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
3166 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
3168 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
3172 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH);
3173 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0);
3174 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
3175 if (sc->xl_flags & XL_FLAG_FUNCREG)
3176 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
3178 /* Stop the stats updater. */
3179 callout_stop(&sc->xl_stat_timer);
3182 * Free data in the RX lists.
3184 for (i = 0; i < XL_RX_LIST_CNT; i++) {
3185 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) {
3186 bus_dmamap_unload(sc->xl_rx_mtag,
3187 sc->xl_cdata.xl_rx_chain[i].xl_map);
3188 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf);
3189 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL;
3192 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ);
3195 * Free the TX list buffers.
3197 for (i = 0; i < XL_TX_LIST_CNT; i++) {
3198 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) {
3199 bus_dmamap_unload(sc->xl_tx_mtag,
3200 sc->xl_cdata.xl_tx_chain[i].xl_map);
3201 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf);
3202 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL;
3205 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ);
3207 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3211 * Stop all chip I/O so that the kernel's probe routines don't
3212 * get confused by errant DMAs when rebooting.
3215 xl_shutdown(device_t dev)
3217 struct xl_softc *sc = device_get_softc(dev);
3219 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
3222 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
3226 xl_suspend(device_t dev)
3228 struct xl_softc *sc = device_get_softc(dev);
3230 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
3232 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
3238 xl_resume(device_t dev)
3240 struct xl_softc *sc;
3243 sc = device_get_softc(dev);
3244 ifp = &sc->arpcom.ac_if;
3246 lwkt_serialize_enter(ifp->if_serializer);
3248 if (ifp->if_flags & IFF_UP)
3250 lwkt_serialize_exit(ifp->if_serializer);