sys/dev/drm/radeon/si_dpm.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <drm/drmP.h>
  25 #include "radeon.h"
  26 #include "radeon_asic.h"
  27 #include "sid.h"
  28 #include "r600_dpm.h"
  29 #include "si_dpm.h"
  30 #include "atom.h"
  31 #include <linux/math64.h>
  32 #include <linux/seq_file.h>
  33
  34 #define MC_CG_ARB_FREQ_F0           0x0a
  35 #define MC_CG_ARB_FREQ_F1           0x0b
  36 #define MC_CG_ARB_FREQ_F2           0x0c
  37 #define MC_CG_ARB_FREQ_F3           0x0d
  38
  39 #define SMC_RAM_END                 0x20000
  40
  41 #define SCLK_MIN_DEEPSLEEP_FREQ     1350
  42
  43 static const struct si_cac_config_reg cac_weights_tahiti[] =
  44 {
  45         { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
  46         { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  47         { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
  48         { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
  49         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  50         { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  51         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  52         { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  53         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  54         { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
  55         { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  56         { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
  57         { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
  58         { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
  59         { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
  60         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  61         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  62         { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
  63         { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  64         { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
  65         { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
  66         { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
  67         { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  68         { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  69         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  70         { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  71         { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  72         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  73         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  74         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  75         { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
  76         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  77         { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  78         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  79         { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
  80         { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  81         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  82         { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
  83         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  84         { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
  85         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  86         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  87         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  88         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  89         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  90         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  91         { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  92         { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  93         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  94         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  95         { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  96         { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  97         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  98         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  99         { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 100         { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 101         { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 102         { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 103         { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 104         { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
 105         { 0xFFFFFFFF }
 106 };
 107
 108 static const struct si_cac_config_reg lcac_tahiti[] =
 109 {
 110         { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 111         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 112         { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 113         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 114         { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 115         { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 116         { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 117         { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 118         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 119         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 120         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 121         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 122         { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 123         { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 124         { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 125         { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 126         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 127         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 128         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 129         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 130         { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 131         { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 132         { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 133         { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 134         { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 135         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 136         { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 137         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 138         { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 139         { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 140         { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 141         { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 142         { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 143         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 144         { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 145         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 146         { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 147         { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 148         { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 149         { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 150         { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 151         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 152         { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 153         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 154         { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 155         { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 156         { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 157         { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 158         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 159         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 160         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 161         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 162         { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 163         { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 164         { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 165         { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 166         { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 167         { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 168         { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 169         { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 170         { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 171         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 172         { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 173         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 174         { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 175         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 176         { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 177         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 178         { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 179         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 180         { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 181         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 182         { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
 183         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 184         { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 185         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 186         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 187         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 188         { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 189         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 190         { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 191         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 192         { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 193         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 194         { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 195         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 196         { 0xFFFFFFFF }
 197
 198 };
 199
 200 static const struct si_cac_config_reg cac_override_tahiti[] =
 201 {
 202         { 0xFFFFFFFF }
 203 };
 204
 205 static const struct si_powertune_data powertune_data_tahiti =
 206 {
 207         ((1 << 16) | 27027),
 208         6,
 209         0,
 210         4,
 211         95,
 212         {
 213                 0UL,
 214                 0UL,
 215                 4521550UL,
 216                 309631529UL,
 217                 -1270850L,
 218                 4513710L,
 219                 40
 220         },
 221         595000000UL,
 222         12,
 223         {
 224                 0,
 225                 0,
 226                 0,
 227                 0,
 228                 0,
 229                 0,
 230                 0,
 231                 0
 232         },
 233         true
 234 };
 235
 236 static const struct si_dte_data dte_data_tahiti =
 237 {
 238         { 1159409, 0, 0, 0, 0 },
 239         { 777, 0, 0, 0, 0 },
 240         2,
 241         54000,
 242         127000,
 243         25,
 244         2,
 245         10,
 246         13,
 247         { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
 248         { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
 249         { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
 250         85,
 251         false
 252 };
 253
 254 #if 0 /* unused */
 255 static const struct si_dte_data dte_data_tahiti_le =
 256 {
 257         { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 },
 258         { 0x7D, 0x7D, 0x4E4, 0xB00, 0 },
 259         0x5,
 260         0xAFC8,
 261         0x64,
 262         0x32,
 263         1,
 264         0,
 265         0x10,
 266         { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 },
 267         { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 },
 268         { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 },
 269         85,
 270         true
 271 };
 272 #endif
 273
 274 static const struct si_dte_data dte_data_tahiti_pro =
 275 {
 276         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 277         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 278         5,
 279         45000,
 280         100,
 281         0xA,
 282         1,
 283         0,
 284         0x10,
 285         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 286         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 287         { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 288         90,
 289         true
 290 };
 291
 292 static const struct si_dte_data dte_data_new_zealand =
 293 {
 294         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
 295         { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
 296         0x5,
 297         0xAFC8,
 298         0x69,
 299         0x32,
 300         1,
 301         0,
 302         0x10,
 303         { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
 304         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 305         { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
 306         85,
 307         true
 308 };
 309
 310 static const struct si_dte_data dte_data_aruba_pro =
 311 {
 312         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 313         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 314         5,
 315         45000,
 316         100,
 317         0xA,
 318         1,
 319         0,
 320         0x10,
 321         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 322         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 323         { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 324         90,
 325         true
 326 };
 327
 328 static const struct si_dte_data dte_data_malta =
 329 {
 330         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 331         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 332         5,
 333         45000,
 334         100,
 335         0xA,
 336         1,
 337         0,
 338         0x10,
 339         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 340         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 341         { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 342         90,
 343         true
 344 };
 345
 346 struct si_cac_config_reg cac_weights_pitcairn[] =
 347 {
 348         { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
 349         { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 350         { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 351         { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
 352         { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
 353         { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 354         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 355         { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
 356         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 357         { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
 358         { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
 359         { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
 360         { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
 361         { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
 362         { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 363         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 364         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 365         { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
 366         { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
 367         { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
 368         { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
 369         { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
 370         { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
 371         { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 372         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 373         { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
 374         { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
 375         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 376         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 377         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 378         { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
 379         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 380         { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
 381         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 382         { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
 383         { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
 384         { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
 385         { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 386         { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
 387         { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 388         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 389         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 390         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 391         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 392         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 393         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 394         { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 395         { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 396         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 397         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 398         { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 399         { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 400         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 401         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 402         { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 403         { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 404         { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 405         { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 406         { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 407         { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
 408         { 0xFFFFFFFF }
 409 };
 410
 411 static const struct si_cac_config_reg lcac_pitcairn[] =
 412 {
 413         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 414         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 415         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 416         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 417         { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 418         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 419         { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 420         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 421         { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 422         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 423         { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 424         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 425         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 426         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 427         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 428         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 429         { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 430         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 431         { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 432         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 433         { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 434         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 435         { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 436         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 437         { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 438         { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 439         { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 440         { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 441         { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 442         { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 443         { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 444         { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 445         { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 446         { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 447         { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 448         { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 449         { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 450         { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 451         { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 452         { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 453         { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 454         { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 455         { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 456         { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 457         { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 458         { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 459         { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 460         { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 461         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 462         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 463         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 464         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 465         { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 466         { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 467         { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 468         { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 469         { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 470         { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 471         { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 472         { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 473         { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 474         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 475         { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 476         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 477         { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 478         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 479         { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 480         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 481         { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 482         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 483         { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 484         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 485         { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 486         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 487         { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 488         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 489         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 490         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 491         { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 492         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 493         { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 494         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 495         { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 496         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 497         { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 498         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 499         { 0xFFFFFFFF }
 500 };
 501
 502 static const struct si_cac_config_reg cac_override_pitcairn[] =
 503 {
 504     { 0xFFFFFFFF }
 505 };
 506
 507 static const struct si_powertune_data powertune_data_pitcairn =
 508 {
 509         ((1 << 16) | 27027),
 510         5,
 511         0,
 512         6,
 513         100,
 514         {
 515                 51600000UL,
 516                 1800000UL,
 517                 7194395UL,
 518                 309631529UL,
 519                 -1270850L,
 520                 4513710L,
 521                 100
 522         },
 523         117830498UL,
 524         12,
 525         {
 526                 0,
 527                 0,
 528                 0,
 529                 0,
 530                 0,
 531                 0,
 532                 0,
 533                 0
 534         },
 535         true
 536 };
 537
 538 static const struct si_dte_data dte_data_pitcairn =
 539 {
 540         { 0, 0, 0, 0, 0 },
 541         { 0, 0, 0, 0, 0 },
 542         0,
 543         0,
 544         0,
 545         0,
 546         0,
 547         0,
 548         0,
 549         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 550         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 551         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 552         0,
 553         false
 554 };
 555
 556 static const struct si_dte_data dte_data_curacao_xt =
 557 {
 558         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 559         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 560         5,
 561         45000,
 562         100,
 563         0xA,
 564         1,
 565         0,
 566         0x10,
 567         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 568         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 569         { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 570         90,
 571         true
 572 };
 573
 574 static const struct si_dte_data dte_data_curacao_pro =
 575 {
 576         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 577         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 578         5,
 579         45000,
 580         100,
 581         0xA,
 582         1,
 583         0,
 584         0x10,
 585         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 586         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 587         { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 588         90,
 589         true
 590 };
 591
 592 static const struct si_dte_data dte_data_neptune_xt =
 593 {
 594         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 595         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 596         5,
 597         45000,
 598         100,
 599         0xA,
 600         1,
 601         0,
 602         0x10,
 603         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 604         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 605         { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 606         90,
 607         true
 608 };
 609
 610 static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
 611 {
 612         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 613         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 614         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 615         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 616         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 617         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 618         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 619         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 620         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 621         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 622         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 623         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 624         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 625         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 626         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 627         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 628         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 629         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 630         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 631         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 632         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 633         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 634         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 635         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 636         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 637         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 638         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 639         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 640         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 641         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 642         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 643         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 644         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 645         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 646         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 647         { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
 648         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 649         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 650         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 651         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 652         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 653         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 654         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 655         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 656         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 657         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 658         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 659         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 660         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 661         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 662         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 663         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 664         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 665         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 666         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 667         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 668         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 669         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 670         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 671         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 672         { 0xFFFFFFFF }
 673 };
 674
 675 static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
 676 {
 677         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 678         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 679         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 680         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 681         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 682         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 683         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 684         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 685         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 686         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 687         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 688         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 689         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 690         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 691         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 692         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 693         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 694         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 695         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 696         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 697         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 698         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 699         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 700         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 701         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 702         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 703         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 704         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 705         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 706         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 707         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 708         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 709         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 710         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 711         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 712         { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
 713         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 714         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 715         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 716         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 717         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 718         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 719         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 720         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 721         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 722         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 723         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 724         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 725         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 726         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 727         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 728         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 729         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 730         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 731         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 732         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 733         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 734         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 735         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 736         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 737         { 0xFFFFFFFF }
 738 };
 739
 740 static const struct si_cac_config_reg cac_weights_heathrow[] =
 741 {
 742         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 743         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 744         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 745         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 746         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 747         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 748         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 749         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 750         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 751         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 752         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 753         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 754         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 755         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 756         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 757         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 758         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 759         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 760         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 761         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 762         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 763         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 764         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 765         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 766         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 767         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 768         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 769         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 770         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 771         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 772         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 773         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 774         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 775         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 776         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 777         { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
 778         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 779         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 780         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 781         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 782         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 783         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 784         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 785         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 786         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 787         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 788         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 789         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 790         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 791         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 792         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 793         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 794         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 795         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 796         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 797         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 798         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 799         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 800         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 801         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 802         { 0xFFFFFFFF }
 803 };
 804
 805 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
 806 {
 807         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 808         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 809         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 810         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 811         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 812         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 813         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 814         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 815         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 816         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 817         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 818         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 819         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 820         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 821         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 822         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 823         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 824         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 825         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 826         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 827         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 828         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 829         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 830         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 831         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 832         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 833         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 834         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 835         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 836         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 837         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 838         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 839         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 840         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 841         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 842         { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
 843         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 844         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 845         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 846         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 847         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 848         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 849         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 850         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 851         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 852         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 853         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 854         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 855         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 856         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 857         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 858         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 859         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 860         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 861         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 862         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 863         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 864         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 865         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 866         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 867         { 0xFFFFFFFF }
 868 };
 869
 870 static const struct si_cac_config_reg cac_weights_cape_verde[] =
 871 {
 872         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 873         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 874         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 875         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 876         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 877         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 878         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 879         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 880         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 881         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 882         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 883         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 884         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 885         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 886         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 887         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 888         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 889         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 890         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 891         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 892         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 893         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 894         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 895         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 896         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 897         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 898         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 899         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 900         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 901         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 902         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 903         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 904         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 905         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 906         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 907         { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
 908         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 909         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 910         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 911         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 912         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 913         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 914         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 915         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 916         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 917         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 918         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 919         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 920         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 921         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 922         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 923         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 924         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 925         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 926         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 927         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 928         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 929         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 930         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 931         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 932         { 0xFFFFFFFF }
 933 };
 934
 935 static const struct si_cac_config_reg lcac_cape_verde[] =
 936 {
 937         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 938         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 939         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 940         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 941         { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 942         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 943         { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 944         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 945         { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 946         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 947         { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 948         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 949         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 950         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 951         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 952         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 953         { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 954         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 955         { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 956         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 957         { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 958         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 959         { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 960         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 961         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 962         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 963         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 964         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 965         { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 966         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 967         { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 968         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 969         { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 970         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 971         { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 972         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 973         { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 974         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 975         { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 976         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 977         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 978         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 979         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 980         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 981         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 982         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 983         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 984         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 985         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 986         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 987         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 988         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 989         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 990         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 991         { 0xFFFFFFFF }
 992 };
 993
 994 static const struct si_cac_config_reg cac_override_cape_verde[] =
 995 {
 996     { 0xFFFFFFFF }
 997 };
 998
 999 static const struct si_powertune_data powertune_data_cape_verde =
1000 {
1001         ((1 << 16) | 0x6993),
1002         5,
1003         0,
1004         7,
1005         105,
1006         {
1007                 0UL,
1008                 0UL,
1009                 7194395UL,
1010                 309631529UL,
1011                 -1270850L,
1012                 4513710L,
1013                 100
1014         },
1015         117830498UL,
1016         12,
1017         {
1018                 0,
1019                 0,
1020                 0,
1021                 0,
1022                 0,
1023                 0,
1024                 0,
1025                 0
1026         },
1027         true
1028 };
1029
1030 static const struct si_dte_data dte_data_cape_verde =
1031 {
1032         { 0, 0, 0, 0, 0 },
1033         { 0, 0, 0, 0, 0 },
1034         0,
1035         0,
1036         0,
1037         0,
1038         0,
1039         0,
1040         0,
1041         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1042         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1043         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1044         0,
1045         false
1046 };
1047
1048 static const struct si_dte_data dte_data_venus_xtx =
1049 {
1050         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1051         { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1052         5,
1053         55000,
1054         0x69,
1055         0xA,
1056         1,
1057         0,
1058         0x3,
1059         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1060         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1061         { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1062         90,
1063         true
1064 };
1065
1066 static const struct si_dte_data dte_data_venus_xt =
1067 {
1068         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1069         { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1070         5,
1071         55000,
1072         0x69,
1073         0xA,
1074         1,
1075         0,
1076         0x3,
1077         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1078         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1079         { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1080         90,
1081         true
1082 };
1083
1084 static const struct si_dte_data dte_data_venus_pro =
1085 {
1086         {  0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1087         { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1088         5,
1089         55000,
1090         0x69,
1091         0xA,
1092         1,
1093         0,
1094         0x3,
1095         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1096         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1097         { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1098         90,
1099         true
1100 };
1101
1102 struct si_cac_config_reg cac_weights_oland[] =
1103 {
1104         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1105         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1106         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1107         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1108         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1109         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1110         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1111         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1112         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1113         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1114         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1115         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1116         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1117         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1118         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1119         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1120         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1121         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1122         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1123         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1124         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1125         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1126         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1127         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1128         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1129         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1130         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1131         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1132         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1133         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1134         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1135         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1136         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1137         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1138         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1139         { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1140         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1141         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1142         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1143         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1144         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1145         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1146         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1147         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1148         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1149         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1150         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1151         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1152         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1153         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1154         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1155         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1156         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1157         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1158         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1159         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1160         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1161         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1162         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1163         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1164         { 0xFFFFFFFF }
1165 };
1166
1167 static const struct si_cac_config_reg cac_weights_mars_pro[] =
1168 {
1169         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1170         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1171         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1172         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1173         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1174         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1175         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1176         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1177         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1178         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1179         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1180         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1181         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1182         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1183         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1184         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1185         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1186         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1187         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1188         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1189         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1190         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1191         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1192         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1193         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1194         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1195         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1196         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1197         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1198         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1199         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1200         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1201         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1202         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1203         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1204         { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1205         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1206         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1207         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1208         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1209         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1210         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1211         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1212         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1213         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1214         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1215         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1216         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1217         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1218         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1219         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1220         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1221         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1222         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1223         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1224         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1225         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1226         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1227         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1228         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1229         { 0xFFFFFFFF }
1230 };
1231
1232 static const struct si_cac_config_reg cac_weights_mars_xt[] =
1233 {
1234         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1235         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1236         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1237         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1238         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1239         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1240         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1241         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1242         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1243         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1244         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1245         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1246         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1247         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1248         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1249         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1250         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1251         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1252         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1253         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1254         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1255         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1256         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1257         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1258         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1259         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1260         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1261         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1262         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1263         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1264         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1265         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1266         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1267         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1268         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1269         { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1270         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1271         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1272         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1273         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1274         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1275         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1276         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1277         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1278         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1279         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1280         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1281         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1282         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1283         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1284         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1285         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1286         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1287         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1288         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1289         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1290         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1291         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1292         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1293         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1294         { 0xFFFFFFFF }
1295 };
1296
1297 static const struct si_cac_config_reg cac_weights_oland_pro[] =
1298 {
1299         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1300         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1301         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1302         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1303         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1304         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1305         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1306         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1307         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1308         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1309         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1310         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1311         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1312         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1313         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1314         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1315         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1316         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1317         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1318         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1319         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1320         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1321         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1322         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1323         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1324         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1325         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1326         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1327         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1328         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1329         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1330         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1331         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1332         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1333         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1334         { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1335         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1336         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1337         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1338         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1339         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1340         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1341         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1342         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1343         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1344         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1345         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1346         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1347         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1348         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1349         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1350         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1351         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1352         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1353         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1354         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1355         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1356         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1357         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1358         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1359         { 0xFFFFFFFF }
1360 };
1361
1362 static const struct si_cac_config_reg cac_weights_oland_xt[] =
1363 {
1364         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1365         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1366         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1367         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1368         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1369         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1370         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1371         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1372         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1373         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1374         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1375         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1376         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1377         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1378         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1379         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1380         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1381         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1382         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1383         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1384         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1385         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1386         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1387         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1388         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1389         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1390         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1391         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1392         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1393         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1394         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1395         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1396         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1397         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1398         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1399         { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1400         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1401         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1402         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1403         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1404         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1405         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1406         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1407         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1408         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1409         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1410         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1411         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1412         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1413         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1414         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1415         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1416         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1417         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1418         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1419         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1420         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1421         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1422         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1423         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1424         { 0xFFFFFFFF }
1425 };
1426
1427 static const struct si_cac_config_reg lcac_oland[] =
1428 {
1429         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1430         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1431         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1432         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1433         { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1434         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1435         { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1436         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1437         { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1438         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1439         { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1440         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1441         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1442         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1443         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1444         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1445         { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1446         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1447         { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1448         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1449         { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1450         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1451         { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1452         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1453         { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1454         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1455         { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1456         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1457         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1458         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1459         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1460         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1461         { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1462         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1463         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1464         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1465         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1466         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1467         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1468         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1469         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1470         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1471         { 0xFFFFFFFF }
1472 };
1473
1474 static const struct si_cac_config_reg lcac_mars_pro[] =
1475 {
1476         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1477         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1478         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1479         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1480         { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1481         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1482         { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1483         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1484         { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1485         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1486         { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1487         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1488         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1489         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1490         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1491         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1492         { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1493         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1494         { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1495         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1496         { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1497         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1498         { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1499         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1500         { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1501         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1502         { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1503         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1504         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1505         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1506         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1507         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1508         { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1509         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1510         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1511         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1512         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1513         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1514         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1515         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1516         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1517         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1518         { 0xFFFFFFFF }
1519 };
1520
1521 static const struct si_cac_config_reg cac_override_oland[] =
1522 {
1523         { 0xFFFFFFFF }
1524 };
1525
1526 static const struct si_powertune_data powertune_data_oland =
1527 {
1528         ((1 << 16) | 0x6993),
1529         5,
1530         0,
1531         7,
1532         105,
1533         {
1534                 0UL,
1535                 0UL,
1536                 7194395UL,
1537                 309631529UL,
1538                 -1270850L,
1539                 4513710L,
1540                 100
1541         },
1542         117830498UL,
1543         12,
1544         {
1545                 0,
1546                 0,
1547                 0,
1548                 0,
1549                 0,
1550                 0,
1551                 0,
1552                 0
1553         },
1554         true
1555 };
1556
1557 static const struct si_powertune_data powertune_data_mars_pro =
1558 {
1559         ((1 << 16) | 0x6993),
1560         5,
1561         0,
1562         7,
1563         105,
1564         {
1565                 0UL,
1566                 0UL,
1567                 7194395UL,
1568                 309631529UL,
1569                 -1270850L,
1570                 4513710L,
1571                 100
1572         },
1573         117830498UL,
1574         12,
1575         {
1576                 0,
1577                 0,
1578                 0,
1579                 0,
1580                 0,
1581                 0,
1582                 0,
1583                 0
1584         },
1585         true
1586 };
1587
1588 static const struct si_dte_data dte_data_oland =
1589 {
1590         { 0, 0, 0, 0, 0 },
1591         { 0, 0, 0, 0, 0 },
1592         0,
1593         0,
1594         0,
1595         0,
1596         0,
1597         0,
1598         0,
1599         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1600         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1601         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1602         0,
1603         false
1604 };
1605
1606 static const struct si_dte_data dte_data_mars_pro =
1607 {
1608         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1609         { 0x0, 0x0, 0x0, 0x0, 0x0 },
1610         5,
1611         55000,
1612         105,
1613         0xA,
1614         1,
1615         0,
1616         0x10,
1617         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1618         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1619         { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1620         90,
1621         true
1622 };
1623
1624 static const struct si_dte_data dte_data_sun_xt =
1625 {
1626         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1627         { 0x0, 0x0, 0x0, 0x0, 0x0 },
1628         5,
1629         55000,
1630         105,
1631         0xA,
1632         1,
1633         0,
1634         0x10,
1635         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1636         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1637         { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1638         90,
1639         true
1640 };
1641
1642
1643 static const struct si_cac_config_reg cac_weights_hainan[] =
1644 {
1645         { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1646         { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1647         { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1648         { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1649         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1650         { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1651         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1652         { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1653         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1654         { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1655         { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1656         { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1657         { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1658         { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1659         { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1660         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1661         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1662         { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1663         { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1664         { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1665         { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1666         { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1667         { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1668         { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1669         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1670         { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1671         { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1672         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1673         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1674         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1675         { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1676         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1677         { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1678         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1679         { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1680         { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1681         { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1682         { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1683         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1684         { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1685         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1686         { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1687         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1688         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1689         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1690         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1691         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1692         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1693         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1694         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1695         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1696         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1697         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1698         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1699         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1700         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1701         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1702         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1703         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1704         { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1705         { 0xFFFFFFFF }
1706 };
1707
1708 static const struct si_powertune_data powertune_data_hainan =
1709 {
1710         ((1 << 16) | 0x6993),
1711         5,
1712         0,
1713         9,
1714         105,
1715         {
1716                 0UL,
1717                 0UL,
1718                 7194395UL,
1719                 309631529UL,
1720                 -1270850L,
1721                 4513710L,
1722                 100
1723         },
1724         117830498UL,
1725         12,
1726         {
1727                 0,
1728                 0,
1729                 0,
1730                 0,
1731                 0,
1732                 0,
1733                 0,
1734                 0
1735         },
1736         true
1737 };
1738
1739 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
1740 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
1741 struct ni_power_info *ni_get_pi(struct radeon_device *rdev);
1742 struct ni_ps *ni_get_ps(struct radeon_ps *rps);
1743
1744 static int si_populate_voltage_value(struct radeon_device *rdev,
1745                                      const struct atom_voltage_table *table,
1746                                      u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1747 static int si_get_std_voltage_value(struct radeon_device *rdev,
1748                                     SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1749                                     u16 *std_voltage);
1750 static int si_write_smc_soft_register(struct radeon_device *rdev,
1751                                       u16 reg_offset, u32 value);
1752 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
1753                                          struct rv7xx_pl *pl,
1754                                          SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1755 static int si_calculate_sclk_params(struct radeon_device *rdev,
1756                                     u32 engine_clock,
1757                                     SISLANDS_SMC_SCLK_VALUE *sclk);
1758
1759 static struct si_power_info *si_get_pi(struct radeon_device *rdev)
1760 {
1761         struct si_power_info *pi = rdev->pm.dpm.priv;
1762
1763         return pi;
1764 }
1765
1766 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1767                                                      u16 v, s32 t, u32 ileakage, u32 *leakage)
1768 {
1769         s64 kt, kv, leakage_w, i_leakage, vddc;
1770         s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1771         s64 tmp;
1772
1773         i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1774         vddc = div64_s64(drm_int2fixp(v), 1000);
1775         temperature = div64_s64(drm_int2fixp(t), 1000);
1776
1777         t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1778         t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1779         av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1780         bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1781         t_ref = drm_int2fixp(coeff->t_ref);
1782
1783         tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1784         kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1785         kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
1786         kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1787
1788         leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1789
1790         *leakage = drm_fixp2int(leakage_w * 1000);
1791 }
1792
1793 static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev,
1794                                              const struct ni_leakage_coeffients *coeff,
1795                                              u16 v,
1796                                              s32 t,
1797                                              u32 i_leakage,
1798                                              u32 *leakage)
1799 {
1800         si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1801 }
1802
1803 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1804                                                const u32 fixed_kt, u16 v,
1805                                                u32 ileakage, u32 *leakage)
1806 {
1807         s64 kt, kv, leakage_w, i_leakage, vddc;
1808
1809         i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1810         vddc = div64_s64(drm_int2fixp(v), 1000);
1811
1812         kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1813         kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1814                           drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1815
1816         leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1817
1818         *leakage = drm_fixp2int(leakage_w * 1000);
1819 }
1820
1821 static void si_calculate_leakage_for_v(struct radeon_device *rdev,
1822                                        const struct ni_leakage_coeffients *coeff,
1823                                        const u32 fixed_kt,
1824                                        u16 v,
1825                                        u32 i_leakage,
1826                                        u32 *leakage)
1827 {
1828         si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1829 }
1830
1831
1832 static void si_update_dte_from_pl2(struct radeon_device *rdev,
1833                                    struct si_dte_data *dte_data)
1834 {
1835         u32 p_limit1 = rdev->pm.dpm.tdp_limit;
1836         u32 p_limit2 = rdev->pm.dpm.near_tdp_limit;
1837         u32 k = dte_data->k;
1838         u32 t_max = dte_data->max_t;
1839         u32 t_split[5] = { 10, 15, 20, 25, 30 };
1840         u32 t_0 = dte_data->t0;
1841         u32 i;
1842
1843         if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1844                 dte_data->tdep_count = 3;
1845
1846                 for (i = 0; i < k; i++) {
1847                         dte_data->r[i] =
1848                                 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1849                                 (p_limit2  * (u32)100);
1850                 }
1851
1852                 dte_data->tdep_r[1] = dte_data->r[4] * 2;
1853
1854                 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1855                         dte_data->tdep_r[i] = dte_data->r[4];
1856                 }
1857         } else {
1858                 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1859         }
1860 }
1861
1862 static void si_initialize_powertune_defaults(struct radeon_device *rdev)
1863 {
1864         struct ni_power_info *ni_pi = ni_get_pi(rdev);
1865         struct si_power_info *si_pi = si_get_pi(rdev);
1866         bool update_dte_from_pl2 = false;
1867
1868         if (rdev->family == CHIP_TAHITI) {
1869                 si_pi->cac_weights = cac_weights_tahiti;
1870                 si_pi->lcac_config = lcac_tahiti;
1871                 si_pi->cac_override = cac_override_tahiti;
1872                 si_pi->powertune_data = &powertune_data_tahiti;
1873                 si_pi->dte_data = dte_data_tahiti;
1874
1875                 switch (rdev->pdev->device) {
1876                 case 0x6798:
1877                         si_pi->dte_data.enable_dte_by_default = true;
1878                         break;
1879                 case 0x6799:
1880                         si_pi->dte_data = dte_data_new_zealand;
1881                         break;
1882                 case 0x6790:
1883                 case 0x6791:
1884                 case 0x6792:
1885                 case 0x679E:
1886                         si_pi->dte_data = dte_data_aruba_pro;
1887                         update_dte_from_pl2 = true;
1888                         break;
1889                 case 0x679B:
1890                         si_pi->dte_data = dte_data_malta;
1891                         update_dte_from_pl2 = true;
1892                         break;
1893                 case 0x679A:
1894                         si_pi->dte_data = dte_data_tahiti_pro;
1895                         update_dte_from_pl2 = true;
1896                         break;
1897                 default:
1898                         if (si_pi->dte_data.enable_dte_by_default == true)
1899                                 DRM_ERROR("DTE is not enabled!\n");
1900                         break;
1901                 }
1902         } else if (rdev->family == CHIP_PITCAIRN) {
1903                 switch (rdev->pdev->device) {
1904                 case 0x6810:
1905                 case 0x6818:
1906                         si_pi->cac_weights = cac_weights_pitcairn;
1907                         si_pi->lcac_config = lcac_pitcairn;
1908                         si_pi->cac_override = cac_override_pitcairn;
1909                         si_pi->powertune_data = &powertune_data_pitcairn;
1910                         si_pi->dte_data = dte_data_curacao_xt;
1911                         update_dte_from_pl2 = true;
1912                         break;
1913                 case 0x6819:
1914                 case 0x6811:
1915                         si_pi->cac_weights = cac_weights_pitcairn;
1916                         si_pi->lcac_config = lcac_pitcairn;
1917                         si_pi->cac_override = cac_override_pitcairn;
1918                         si_pi->powertune_data = &powertune_data_pitcairn;
1919                         si_pi->dte_data = dte_data_curacao_pro;
1920                         update_dte_from_pl2 = true;
1921                         break;
1922                 case 0x6800:
1923                 case 0x6806:
1924                         si_pi->cac_weights = cac_weights_pitcairn;
1925                         si_pi->lcac_config = lcac_pitcairn;
1926                         si_pi->cac_override = cac_override_pitcairn;
1927                         si_pi->powertune_data = &powertune_data_pitcairn;
1928                         si_pi->dte_data = dte_data_neptune_xt;
1929                         update_dte_from_pl2 = true;
1930                         break;
1931                 default:
1932                         si_pi->cac_weights = cac_weights_pitcairn;
1933                         si_pi->lcac_config = lcac_pitcairn;
1934                         si_pi->cac_override = cac_override_pitcairn;
1935                         si_pi->powertune_data = &powertune_data_pitcairn;
1936                         si_pi->dte_data = dte_data_pitcairn;
1937                         break;
1938                 }
1939         } else if (rdev->family == CHIP_VERDE) {
1940                 si_pi->lcac_config = lcac_cape_verde;
1941                 si_pi->cac_override = cac_override_cape_verde;
1942                 si_pi->powertune_data = &powertune_data_cape_verde;
1943
1944                 switch (rdev->pdev->device) {
1945                 case 0x683B:
1946                 case 0x683F:
1947                 case 0x6829:
1948                 case 0x6835:
1949                         si_pi->cac_weights = cac_weights_cape_verde_pro;
1950                         si_pi->dte_data = dte_data_cape_verde;
1951                         break;
1952                 case 0x682C:
1953                         si_pi->cac_weights = cac_weights_cape_verde_pro;
1954                         si_pi->dte_data = dte_data_sun_xt;
1955                         break;
1956                 case 0x6825:
1957                 case 0x6827:
1958                         si_pi->cac_weights = cac_weights_heathrow;
1959                         si_pi->dte_data = dte_data_cape_verde;
1960                         break;
1961                 case 0x6824:
1962                 case 0x682D:
1963                         si_pi->cac_weights = cac_weights_chelsea_xt;
1964                         si_pi->dte_data = dte_data_cape_verde;
1965                         break;
1966                 case 0x682F:
1967                         si_pi->cac_weights = cac_weights_chelsea_pro;
1968                         si_pi->dte_data = dte_data_cape_verde;
1969                         break;
1970                 case 0x6820:
1971                         si_pi->cac_weights = cac_weights_heathrow;
1972                         si_pi->dte_data = dte_data_venus_xtx;
1973                         break;
1974                 case 0x6821:
1975                         si_pi->cac_weights = cac_weights_heathrow;
1976                         si_pi->dte_data = dte_data_venus_xt;
1977                         break;
1978                 case 0x6823:
1979                 case 0x682B:
1980                 case 0x6822:
1981                 case 0x682A:
1982                         si_pi->cac_weights = cac_weights_chelsea_pro;
1983                         si_pi->dte_data = dte_data_venus_pro;
1984                         break;
1985                 default:
1986                         si_pi->cac_weights = cac_weights_cape_verde;
1987                         si_pi->dte_data = dte_data_cape_verde;
1988                         break;
1989                 }
1990         } else if (rdev->family == CHIP_OLAND) {
1991                 switch (rdev->pdev->device) {
1992                 case 0x6601:
1993                 case 0x6621:
1994                 case 0x6603:
1995                 case 0x6605:
1996                         si_pi->cac_weights = cac_weights_mars_pro;
1997                         si_pi->lcac_config = lcac_mars_pro;
1998                         si_pi->cac_override = cac_override_oland;
1999                         si_pi->powertune_data = &powertune_data_mars_pro;
2000                         si_pi->dte_data = dte_data_mars_pro;
2001                         update_dte_from_pl2 = true;
2002                         break;
2003                 case 0x6600:
2004                 case 0x6606:
2005                 case 0x6620:
2006                 case 0x6604:
2007                         si_pi->cac_weights = cac_weights_mars_xt;
2008                         si_pi->lcac_config = lcac_mars_pro;
2009                         si_pi->cac_override = cac_override_oland;
2010                         si_pi->powertune_data = &powertune_data_mars_pro;
2011                         si_pi->dte_data = dte_data_mars_pro;
2012                         update_dte_from_pl2 = true;
2013                         break;
2014                 case 0x6611:
2015                 case 0x6613:
2016                 case 0x6608:
2017                         si_pi->cac_weights = cac_weights_oland_pro;
2018                         si_pi->lcac_config = lcac_mars_pro;
2019                         si_pi->cac_override = cac_override_oland;
2020                         si_pi->powertune_data = &powertune_data_mars_pro;
2021                         si_pi->dte_data = dte_data_mars_pro;
2022                         update_dte_from_pl2 = true;
2023                         break;
2024                 case 0x6610:
2025                         si_pi->cac_weights = cac_weights_oland_xt;
2026                         si_pi->lcac_config = lcac_mars_pro;
2027                         si_pi->cac_override = cac_override_oland;
2028                         si_pi->powertune_data = &powertune_data_mars_pro;
2029                         si_pi->dte_data = dte_data_mars_pro;
2030                         update_dte_from_pl2 = true;
2031                         break;
2032                 default:
2033                         si_pi->cac_weights = cac_weights_oland;
2034                         si_pi->lcac_config = lcac_oland;
2035                         si_pi->cac_override = cac_override_oland;
2036                         si_pi->powertune_data = &powertune_data_oland;
2037                         si_pi->dte_data = dte_data_oland;
2038                         break;
2039                 }
2040         } else if (rdev->family == CHIP_HAINAN) {
2041                 si_pi->cac_weights = cac_weights_hainan;
2042                 si_pi->lcac_config = lcac_oland;
2043                 si_pi->cac_override = cac_override_oland;
2044                 si_pi->powertune_data = &powertune_data_hainan;
2045                 si_pi->dte_data = dte_data_sun_xt;
2046                 update_dte_from_pl2 = true;
2047         } else {
2048                 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2049                 return;
2050         }
2051
2052         ni_pi->enable_power_containment = false;
2053         ni_pi->enable_cac = false;
2054         ni_pi->enable_sq_ramping = false;
2055         si_pi->enable_dte = false;
2056
2057         if (si_pi->powertune_data->enable_powertune_by_default) {
2058                 ni_pi->enable_power_containment= true;
2059                 ni_pi->enable_cac = true;
2060                 if (si_pi->dte_data.enable_dte_by_default) {
2061                         si_pi->enable_dte = true;
2062                         if (update_dte_from_pl2)
2063                                 si_update_dte_from_pl2(rdev, &si_pi->dte_data);
2064
2065                 }
2066                 ni_pi->enable_sq_ramping = true;
2067         }
2068
2069         ni_pi->driver_calculate_cac_leakage = true;
2070         ni_pi->cac_configuration_required = true;
2071
2072         if (ni_pi->cac_configuration_required) {
2073                 ni_pi->support_cac_long_term_average = true;
2074                 si_pi->dyn_powertune_data.l2_lta_window_size =
2075                         si_pi->powertune_data->l2_lta_window_size_default;
2076                 si_pi->dyn_powertune_data.lts_truncate =
2077                         si_pi->powertune_data->lts_truncate_default;
2078         } else {
2079                 ni_pi->support_cac_long_term_average = false;
2080                 si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2081                 si_pi->dyn_powertune_data.lts_truncate = 0;
2082         }
2083
2084         si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2085 }
2086
2087 static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev)
2088 {
2089         return 1;
2090 }
2091
2092 static u32 si_calculate_cac_wintime(struct radeon_device *rdev)
2093 {
2094         u32 xclk;
2095         u32 wintime;
2096         u32 cac_window;
2097         u32 cac_window_size;
2098
2099         xclk = radeon_get_xclk(rdev);
2100
2101         if (xclk == 0)
2102                 return 0;
2103
2104         cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
2105         cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2106
2107         wintime = (cac_window_size * 100) / xclk;
2108
2109         return wintime;
2110 }
2111
2112 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2113 {
2114         return power_in_watts;
2115 }
2116
2117 static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev,
2118                                             bool adjust_polarity,
2119                                             u32 tdp_adjustment,
2120                                             u32 *tdp_limit,
2121                                             u32 *near_tdp_limit)
2122 {
2123         u32 adjustment_delta, max_tdp_limit;
2124
2125         if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit)
2126                 return -EINVAL;
2127
2128         max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100;
2129
2130         if (adjust_polarity) {
2131                 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2132                 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit);
2133         } else {
2134                 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2135                 adjustment_delta  = rdev->pm.dpm.tdp_limit - *tdp_limit;
2136                 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted)
2137                         *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2138                 else
2139                         *near_tdp_limit = 0;
2140         }
2141
2142         if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2143                 return -EINVAL;
2144         if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2145                 return -EINVAL;
2146
2147         return 0;
2148 }
2149
2150 static int si_populate_smc_tdp_limits(struct radeon_device *rdev,
2151                                       struct radeon_ps *radeon_state)
2152 {
2153         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2154         struct si_power_info *si_pi = si_get_pi(rdev);
2155
2156         if (ni_pi->enable_power_containment) {
2157                 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2158                 PP_SIslands_PAPMParameters *papm_parm;
2159                 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
2160                 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2161                 u32 tdp_limit;
2162                 u32 near_tdp_limit;
2163                 int ret;
2164
2165                 if (scaling_factor == 0)
2166                         return -EINVAL;
2167
2168                 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2169
2170                 ret = si_calculate_adjusted_tdp_limits(rdev,
2171                                                        false, /* ??? */
2172                                                        rdev->pm.dpm.tdp_adjustment,
2173                                                        &tdp_limit,
2174                                                        &near_tdp_limit);
2175                 if (ret)
2176                         return ret;
2177
2178                 smc_table->dpm2Params.TDPLimit =
2179                         cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2180                 smc_table->dpm2Params.NearTDPLimit =
2181                         cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2182                 smc_table->dpm2Params.SafePowerLimit =
2183                         cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2184
2185                 ret = si_copy_bytes_to_smc(rdev,
2186                                            (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2187                                                  offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2188                                            (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2189                                            sizeof(u32) * 3,
2190                                            si_pi->sram_end);
2191                 if (ret)
2192                         return ret;
2193
2194                 if (si_pi->enable_ppm) {
2195                         papm_parm = &si_pi->papm_parm;
2196                         memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2197                         papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2198                         papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2199                         papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2200                         papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2201                         papm_parm->PlatformPowerLimit = 0xffffffff;
2202                         papm_parm->NearTDPLimitPAPM = 0xffffffff;
2203
2204                         ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start,
2205                                                    (u8 *)papm_parm,
2206                                                    sizeof(PP_SIslands_PAPMParameters),
2207                                                    si_pi->sram_end);
2208                         if (ret)
2209                                 return ret;
2210                 }
2211         }
2212         return 0;
2213 }
2214
2215 static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev,
2216                                         struct radeon_ps *radeon_state)
2217 {
2218         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2219         struct si_power_info *si_pi = si_get_pi(rdev);
2220
2221         if (ni_pi->enable_power_containment) {
2222                 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2223                 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2224                 int ret;
2225
2226                 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2227
2228                 smc_table->dpm2Params.NearTDPLimit =
2229                         cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2230                 smc_table->dpm2Params.SafePowerLimit =
2231                         cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2232
2233                 ret = si_copy_bytes_to_smc(rdev,
2234                                            (si_pi->state_table_start +
2235                                             offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2236                                             offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2237                                            (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2238                                            sizeof(u32) * 2,
2239                                            si_pi->sram_end);
2240                 if (ret)
2241                         return ret;
2242         }
2243
2244         return 0;
2245 }
2246
2247 static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev,
2248                                                const u16 prev_std_vddc,
2249                                                const u16 curr_std_vddc)
2250 {
2251         u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2252         u64 prev_vddc = (u64)prev_std_vddc;
2253         u64 curr_vddc = (u64)curr_std_vddc;
2254         u64 pwr_efficiency_ratio, n, d;
2255
2256         if ((prev_vddc == 0) || (curr_vddc == 0))
2257                 return 0;
2258
2259         n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2260         d = prev_vddc * prev_vddc;
2261         pwr_efficiency_ratio = div64_u64(n, d);
2262
2263         if (pwr_efficiency_ratio > (u64)0xFFFF)
2264                 return 0;
2265
2266         return (u16)pwr_efficiency_ratio;
2267 }
2268
2269 static bool si_should_disable_uvd_powertune(struct radeon_device *rdev,
2270                                             struct radeon_ps *radeon_state)
2271 {
2272         struct si_power_info *si_pi = si_get_pi(rdev);
2273
2274         if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2275             radeon_state->vclk && radeon_state->dclk)
2276                 return true;
2277
2278         return false;
2279 }
2280
2281 static int si_populate_power_containment_values(struct radeon_device *rdev,
2282                                                 struct radeon_ps *radeon_state,
2283                                                 SISLANDS_SMC_SWSTATE *smc_state)
2284 {
2285         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2286         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2287         struct ni_ps *state = ni_get_ps(radeon_state);
2288         SISLANDS_SMC_VOLTAGE_VALUE vddc;
2289         u32 prev_sclk;
2290         u32 max_sclk;
2291         u32 min_sclk;
2292         u16 prev_std_vddc;
2293         u16 curr_std_vddc;
2294         int i;
2295         u16 pwr_efficiency_ratio;
2296         u8 max_ps_percent;
2297         bool disable_uvd_power_tune;
2298         int ret;
2299
2300         if (ni_pi->enable_power_containment == false)
2301                 return 0;
2302
2303         if (state->performance_level_count == 0)
2304                 return -EINVAL;
2305
2306         if (smc_state->levelCount != state->performance_level_count)
2307                 return -EINVAL;
2308
2309         disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state);
2310
2311         smc_state->levels[0].dpm2.MaxPS = 0;
2312         smc_state->levels[0].dpm2.NearTDPDec = 0;
2313         smc_state->levels[0].dpm2.AboveSafeInc = 0;
2314         smc_state->levels[0].dpm2.BelowSafeInc = 0;
2315         smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2316
2317         for (i = 1; i < state->performance_level_count; i++) {
2318                 prev_sclk = state->performance_levels[i-1].sclk;
2319                 max_sclk  = state->performance_levels[i].sclk;
2320                 if (i == 1)
2321                         max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2322                 else
2323                         max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2324
2325                 if (prev_sclk > max_sclk)
2326                         return -EINVAL;
2327
2328                 if ((max_ps_percent == 0) ||
2329                     (prev_sclk == max_sclk) ||
2330                     disable_uvd_power_tune) {
2331                         min_sclk = max_sclk;
2332                 } else if (i == 1) {
2333                         min_sclk = prev_sclk;
2334                 } else {
2335                         min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2336                 }
2337
2338                 if (min_sclk < state->performance_levels[0].sclk)
2339                         min_sclk = state->performance_levels[0].sclk;
2340
2341                 if (min_sclk == 0)
2342                         return -EINVAL;
2343
2344                 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2345                                                 state->performance_levels[i-1].vddc, &vddc);
2346                 if (ret)
2347                         return ret;
2348
2349                 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc);
2350                 if (ret)
2351                         return ret;
2352
2353                 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2354                                                 state->performance_levels[i].vddc, &vddc);
2355                 if (ret)
2356                         return ret;
2357
2358                 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc);
2359                 if (ret)
2360                         return ret;
2361
2362                 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev,
2363                                                                            prev_std_vddc, curr_std_vddc);
2364
2365                 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2366                 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2367                 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2368                 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2369                 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2370         }
2371
2372         return 0;
2373 }
2374
2375 static int si_populate_sq_ramping_values(struct radeon_device *rdev,
2376                                          struct radeon_ps *radeon_state,
2377                                          SISLANDS_SMC_SWSTATE *smc_state)
2378 {
2379         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2380         struct ni_ps *state = ni_get_ps(radeon_state);
2381         u32 sq_power_throttle, sq_power_throttle2;
2382         bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2383         int i;
2384
2385         if (state->performance_level_count == 0)
2386                 return -EINVAL;
2387
2388         if (smc_state->levelCount != state->performance_level_count)
2389                 return -EINVAL;
2390
2391         if (rdev->pm.dpm.sq_ramping_threshold == 0)
2392                 return -EINVAL;
2393
2394         if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2395                 enable_sq_ramping = false;
2396
2397         if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2398                 enable_sq_ramping = false;
2399
2400         if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2401                 enable_sq_ramping = false;
2402
2403         if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2404                 enable_sq_ramping = false;
2405
2406         if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2407                 enable_sq_ramping = false;
2408
2409         for (i = 0; i < state->performance_level_count; i++) {
2410                 sq_power_throttle = 0;
2411                 sq_power_throttle2 = 0;
2412
2413                 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) &&
2414                     enable_sq_ramping) {
2415                         sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2416                         sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2417                         sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2418                         sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2419                         sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2420                 } else {
2421                         sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2422                         sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2423                 }
2424
2425                 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2426                 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2427         }
2428
2429         return 0;
2430 }
2431
2432 static int si_enable_power_containment(struct radeon_device *rdev,
2433                                        struct radeon_ps *radeon_new_state,
2434                                        bool enable)
2435 {
2436         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2437         PPSMC_Result smc_result;
2438         int ret = 0;
2439
2440         if (ni_pi->enable_power_containment) {
2441                 if (enable) {
2442                         if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2443                                 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive);
2444                                 if (smc_result != PPSMC_Result_OK) {
2445                                         ret = -EINVAL;
2446                                         ni_pi->pc_enabled = false;
2447                                 } else {
2448                                         ni_pi->pc_enabled = true;
2449                                 }
2450                         }
2451                 } else {
2452                         smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive);
2453                         if (smc_result != PPSMC_Result_OK)
2454                                 ret = -EINVAL;
2455                         ni_pi->pc_enabled = false;
2456                 }
2457         }
2458
2459         return ret;
2460 }
2461
2462 static int si_initialize_smc_dte_tables(struct radeon_device *rdev)
2463 {
2464         struct si_power_info *si_pi = si_get_pi(rdev);
2465         int ret = 0;
2466         struct si_dte_data *dte_data = &si_pi->dte_data;
2467         Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2468         u32 table_size;
2469         u8 tdep_count;
2470         u32 i;
2471
2472         if (dte_data == NULL)
2473                 si_pi->enable_dte = false;
2474
2475         if (si_pi->enable_dte == false)
2476                 return 0;
2477
2478         if (dte_data->k <= 0)
2479                 return -EINVAL;
2480
2481         dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2482         if (dte_tables == NULL) {
2483                 si_pi->enable_dte = false;
2484                 return -ENOMEM;
2485         }
2486
2487         table_size = dte_data->k;
2488
2489         if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2490                 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2491
2492         tdep_count = dte_data->tdep_count;
2493         if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2494                 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2495
2496         dte_tables->K = cpu_to_be32(table_size);
2497         dte_tables->T0 = cpu_to_be32(dte_data->t0);
2498         dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2499         dte_tables->WindowSize = dte_data->window_size;
2500         dte_tables->temp_select = dte_data->temp_select;
2501         dte_tables->DTE_mode = dte_data->dte_mode;
2502         dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2503
2504         if (tdep_count > 0)
2505                 table_size--;
2506
2507         for (i = 0; i < table_size; i++) {
2508                 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2509                 dte_tables->R[i]   = cpu_to_be32(dte_data->r[i]);
2510         }
2511
2512         dte_tables->Tdep_count = tdep_count;
2513
2514         for (i = 0; i < (u32)tdep_count; i++) {
2515                 dte_tables->T_limits[i] = dte_data->t_limits[i];
2516                 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2517                 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2518         }
2519
2520         ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables,
2521                                    sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end);
2522         kfree(dte_tables);
2523
2524         return ret;
2525 }
2526
2527 static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev,
2528                                           u16 *max, u16 *min)
2529 {
2530         struct si_power_info *si_pi = si_get_pi(rdev);
2531         struct radeon_cac_leakage_table *table =
2532                 &rdev->pm.dpm.dyn_state.cac_leakage_table;
2533         u32 i;
2534         u32 v0_loadline;
2535
2536
2537         if (table == NULL)
2538                 return -EINVAL;
2539
2540         *max = 0;
2541         *min = 0xFFFF;
2542
2543         for (i = 0; i < table->count; i++) {
2544                 if (table->entries[i].vddc > *max)
2545                         *max = table->entries[i].vddc;
2546                 if (table->entries[i].vddc < *min)
2547                         *min = table->entries[i].vddc;
2548         }
2549
2550         if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2551                 return -EINVAL;
2552
2553         v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2554
2555         if (v0_loadline > 0xFFFFUL)
2556                 return -EINVAL;
2557
2558         *min = (u16)v0_loadline;
2559
2560         if ((*min > *max) || (*max == 0) || (*min == 0))
2561                 return -EINVAL;
2562
2563         return 0;
2564 }
2565
2566 static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2567 {
2568         return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2569                 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2570 }
2571
2572 static int si_init_dte_leakage_table(struct radeon_device *rdev,
2573                                      PP_SIslands_CacConfig *cac_tables,
2574                                      u16 vddc_max, u16 vddc_min, u16 vddc_step,
2575                                      u16 t0, u16 t_step)
2576 {
2577         struct si_power_info *si_pi = si_get_pi(rdev);
2578         u32 leakage;
2579         unsigned int i, j;
2580         s32 t;
2581         u32 smc_leakage;
2582         u32 scaling_factor;
2583         u16 voltage;
2584
2585         scaling_factor = si_get_smc_power_scaling_factor(rdev);
2586
2587         for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2588                 t = (1000 * (i * t_step + t0));
2589
2590                 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2591                         voltage = vddc_max - (vddc_step * j);
2592
2593                         si_calculate_leakage_for_v_and_t(rdev,
2594                                                          &si_pi->powertune_data->leakage_coefficients,
2595                                                          voltage,
2596                                                          t,
2597                                                          si_pi->dyn_powertune_data.cac_leakage,
2598                                                          &leakage);
2599
2600                         smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2601
2602                         if (smc_leakage > 0xFFFF)
2603                                 smc_leakage = 0xFFFF;
2604
2605                         cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2606                                 cpu_to_be16((u16)smc_leakage);
2607                 }
2608         }
2609         return 0;
2610 }
2611
2612 static int si_init_simplified_leakage_table(struct radeon_device *rdev,
2613                                             PP_SIslands_CacConfig *cac_tables,
2614                                             u16 vddc_max, u16 vddc_min, u16 vddc_step)
2615 {
2616         struct si_power_info *si_pi = si_get_pi(rdev);
2617         u32 leakage;
2618         unsigned int i, j;
2619         u32 smc_leakage;
2620         u32 scaling_factor;
2621         u16 voltage;
2622
2623         scaling_factor = si_get_smc_power_scaling_factor(rdev);
2624
2625         for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2626                 voltage = vddc_max - (vddc_step * j);
2627
2628                 si_calculate_leakage_for_v(rdev,
2629                                            &si_pi->powertune_data->leakage_coefficients,
2630                                            si_pi->powertune_data->fixed_kt,
2631                                            voltage,
2632                                            si_pi->dyn_powertune_data.cac_leakage,
2633                                            &leakage);
2634
2635                 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2636
2637                 if (smc_leakage > 0xFFFF)
2638                         smc_leakage = 0xFFFF;
2639
2640                 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2641                         cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2642                                 cpu_to_be16((u16)smc_leakage);
2643         }
2644         return 0;
2645 }
2646
2647 static int si_initialize_smc_cac_tables(struct radeon_device *rdev)
2648 {
2649         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2650         struct si_power_info *si_pi = si_get_pi(rdev);
2651         PP_SIslands_CacConfig *cac_tables = NULL;
2652         u16 vddc_max, vddc_min, vddc_step;
2653         u16 t0, t_step;
2654         u32 load_line_slope, reg;
2655         int ret = 0;
2656         u32 ticks_per_us = radeon_get_xclk(rdev) / 100;
2657
2658         if (ni_pi->enable_cac == false)
2659                 return 0;
2660
2661         cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2662         if (!cac_tables)
2663                 return -ENOMEM;
2664
2665         reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
2666         reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);
2667         WREG32(CG_CAC_CTRL, reg);
2668
2669         si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage;
2670         si_pi->dyn_powertune_data.dc_pwr_value =
2671                 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2672         si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev);
2673         si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2674
2675         si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2676
2677         ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min);
2678         if (ret)
2679                 goto done_free;
2680
2681         vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2682         vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2683         t_step = 4;
2684         t0 = 60;
2685
2686         if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2687                 ret = si_init_dte_leakage_table(rdev, cac_tables,
2688                                                 vddc_max, vddc_min, vddc_step,
2689                                                 t0, t_step);
2690         else
2691                 ret = si_init_simplified_leakage_table(rdev, cac_tables,
2692                                                        vddc_max, vddc_min, vddc_step);
2693         if (ret)
2694                 goto done_free;
2695
2696         load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2697
2698         cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2699         cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2700         cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2701         cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2702         cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2703         cac_tables->R_LL = cpu_to_be32(load_line_slope);
2704         cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2705         cac_tables->calculation_repeats = cpu_to_be32(2);
2706         cac_tables->dc_cac = cpu_to_be32(0);
2707         cac_tables->log2_PG_LKG_SCALE = 12;
2708         cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2709         cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2710         cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2711
2712         ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables,
2713                                    sizeof(PP_SIslands_CacConfig), si_pi->sram_end);
2714
2715         if (ret)
2716                 goto done_free;
2717
2718         ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2719
2720 done_free:
2721         if (ret) {
2722                 ni_pi->enable_cac = false;
2723                 ni_pi->enable_power_containment = false;
2724         }
2725
2726         kfree(cac_tables);
2727
2728         return 0;
2729 }
2730
2731 static int si_program_cac_config_registers(struct radeon_device *rdev,
2732                                            const struct si_cac_config_reg *cac_config_regs)
2733 {
2734         const struct si_cac_config_reg *config_regs = cac_config_regs;
2735         u32 data = 0, offset;
2736
2737         if (!config_regs)
2738                 return -EINVAL;
2739
2740         while (config_regs->offset != 0xFFFFFFFF) {
2741                 switch (config_regs->type) {
2742                 case SISLANDS_CACCONFIG_CGIND:
2743                         offset = SMC_CG_IND_START + config_regs->offset;
2744                         if (offset < SMC_CG_IND_END)
2745                                 data = RREG32_SMC(offset);
2746                         break;
2747                 default:
2748                         data = RREG32(config_regs->offset << 2);
2749                         break;
2750                 }
2751
2752                 data &= ~config_regs->mask;
2753                 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2754
2755                 switch (config_regs->type) {
2756                 case SISLANDS_CACCONFIG_CGIND:
2757                         offset = SMC_CG_IND_START + config_regs->offset;
2758                         if (offset < SMC_CG_IND_END)
2759                                 WREG32_SMC(offset, data);
2760                         break;
2761                 default:
2762                         WREG32(config_regs->offset << 2, data);
2763                         break;
2764                 }
2765                 config_regs++;
2766         }
2767         return 0;
2768 }
2769
2770 static int si_initialize_hardware_cac_manager(struct radeon_device *rdev)
2771 {
2772         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2773         struct si_power_info *si_pi = si_get_pi(rdev);
2774         int ret;
2775
2776         if ((ni_pi->enable_cac == false) ||
2777             (ni_pi->cac_configuration_required == false))
2778                 return 0;
2779
2780         ret = si_program_cac_config_registers(rdev, si_pi->lcac_config);
2781         if (ret)
2782                 return ret;
2783         ret = si_program_cac_config_registers(rdev, si_pi->cac_override);
2784         if (ret)
2785                 return ret;
2786         ret = si_program_cac_config_registers(rdev, si_pi->cac_weights);
2787         if (ret)
2788                 return ret;
2789
2790         return 0;
2791 }
2792
2793 static int si_enable_smc_cac(struct radeon_device *rdev,
2794                              struct radeon_ps *radeon_new_state,
2795                              bool enable)
2796 {
2797         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2798         struct si_power_info *si_pi = si_get_pi(rdev);
2799         PPSMC_Result smc_result;
2800         int ret = 0;
2801
2802         if (ni_pi->enable_cac) {
2803                 if (enable) {
2804                         if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2805                                 if (ni_pi->support_cac_long_term_average) {
2806                                         smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable);
2807                                         if (smc_result != PPSMC_Result_OK)
2808                                                 ni_pi->support_cac_long_term_average = false;
2809                                 }
2810
2811                                 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
2812                                 if (smc_result != PPSMC_Result_OK) {
2813                                         ret = -EINVAL;
2814                                         ni_pi->cac_enabled = false;
2815                                 } else {
2816                                         ni_pi->cac_enabled = true;
2817                                 }
2818
2819                                 if (si_pi->enable_dte) {
2820                                         smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
2821                                         if (smc_result != PPSMC_Result_OK)
2822                                                 ret = -EINVAL;
2823                                 }
2824                         }
2825                 } else if (ni_pi->cac_enabled) {
2826                         if (si_pi->enable_dte)
2827                                 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
2828
2829                         smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
2830
2831                         ni_pi->cac_enabled = false;
2832
2833                         if (ni_pi->support_cac_long_term_average)
2834                                 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable);
2835                 }
2836         }
2837         return ret;
2838 }
2839
2840 static int si_init_smc_spll_table(struct radeon_device *rdev)
2841 {
2842         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2843         struct si_power_info *si_pi = si_get_pi(rdev);
2844         SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2845         SISLANDS_SMC_SCLK_VALUE sclk_params;
2846         u32 fb_div, p_div;
2847         u32 clk_s, clk_v;
2848         u32 sclk = 0;
2849         int ret = 0;
2850         u32 tmp;
2851         int i;
2852
2853         if (si_pi->spll_table_start == 0)
2854                 return -EINVAL;
2855
2856         spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2857         if (spll_table == NULL)
2858                 return -ENOMEM;
2859
2860         for (i = 0; i < 256; i++) {
2861                 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params);
2862                 if (ret)
2863                         break;
2864
2865                 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2866                 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2867                 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2868                 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2869
2870                 fb_div &= ~0x00001FFF;
2871                 fb_div >>= 1;
2872                 clk_v >>= 6;
2873
2874                 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2875                         ret = -EINVAL;
2876                 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2877                         ret = -EINVAL;
2878                 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2879                         ret = -EINVAL;
2880                 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2881                         ret = -EINVAL;
2882
2883                 if (ret)
2884                         break;
2885
2886                 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2887                         ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2888                 spll_table->freq[i] = cpu_to_be32(tmp);
2889
2890                 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2891                         ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2892                 spll_table->ss[i] = cpu_to_be32(tmp);
2893
2894                 sclk += 512;
2895         }
2896
2897
2898         if (!ret)
2899                 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start,
2900                                            (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
2901                                            si_pi->sram_end);
2902
2903         if (ret)
2904                 ni_pi->enable_power_containment = false;
2905
2906         kfree(spll_table);
2907
2908         return ret;
2909 }
2910
2911 struct si_dpm_quirk {
2912         u32 chip_vendor;
2913         u32 chip_device;
2914         u32 subsys_vendor;
2915         u32 subsys_device;
2916         u32 max_sclk;
2917         u32 max_mclk;
2918 };
2919
2920 /* cards with dpm stability problems */
2921 static struct si_dpm_quirk si_dpm_quirk_list[] = {
2922         /* PITCAIRN - https://bugs.freedesktop.org/show_bug.cgi?id=76490 */
2923         { PCI_VENDOR_ID_ATI, 0x6810, 0x1462, 0x3036, 0, 120000 },
2924         { 0, 0, 0, 0 },
2925 };
2926
2927 static void si_apply_state_adjust_rules(struct radeon_device *rdev,
2928                                         struct radeon_ps *rps)
2929 {
2930         struct ni_ps *ps = ni_get_ps(rps);
2931         struct radeon_clock_and_voltage_limits *max_limits;
2932         bool disable_mclk_switching = false;
2933         bool disable_sclk_switching = false;
2934         u32 mclk, sclk;
2935         u16 vddc, vddci;
2936         u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
2937         u32 max_sclk = 0, max_mclk = 0;
2938         int i;
2939         struct si_dpm_quirk *p = si_dpm_quirk_list;
2940
2941         /* Apply dpm quirks */
2942         while (p && p->chip_device != 0) {
2943                 if (rdev->pdev->vendor == p->chip_vendor &&
2944                     rdev->pdev->device == p->chip_device &&
2945                     rdev->pdev->subsystem_vendor == p->subsys_vendor &&
2946                     rdev->pdev->subsystem_device == p->subsys_device) {
2947                         max_sclk = p->max_sclk;
2948                         max_mclk = p->max_mclk;
2949                         break;
2950                 }
2951                 ++p;
2952         }
2953
2954         if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
2955             ni_dpm_vblank_too_short(rdev))
2956                 disable_mclk_switching = true;
2957
2958         if (rps->vclk || rps->dclk) {
2959                 disable_mclk_switching = true;
2960                 disable_sclk_switching = true;
2961         }
2962
2963         if (rdev->pm.dpm.ac_power)
2964                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
2965         else
2966                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
2967
2968         for (i = ps->performance_level_count - 2; i >= 0; i--) {
2969                 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
2970                         ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
2971         }
2972         if (rdev->pm.dpm.ac_power == false) {
2973                 for (i = 0; i < ps->performance_level_count; i++) {
2974                         if (ps->performance_levels[i].mclk > max_limits->mclk)
2975                                 ps->performance_levels[i].mclk = max_limits->mclk;
2976                         if (ps->performance_levels[i].sclk > max_limits->sclk)
2977                                 ps->performance_levels[i].sclk = max_limits->sclk;
2978                         if (ps->performance_levels[i].vddc > max_limits->vddc)
2979                                 ps->performance_levels[i].vddc = max_limits->vddc;
2980                         if (ps->performance_levels[i].vddci > max_limits->vddci)
2981                                 ps->performance_levels[i].vddci = max_limits->vddci;
2982                 }
2983         }
2984
2985         /* limit clocks to max supported clocks based on voltage dependency tables */
2986         btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
2987                                                         &max_sclk_vddc);
2988         btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2989                                                         &max_mclk_vddci);
2990         btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2991                                                         &max_mclk_vddc);
2992
2993         for (i = 0; i < ps->performance_level_count; i++) {
2994                 if (max_sclk_vddc) {
2995                         if (ps->performance_levels[i].sclk > max_sclk_vddc)
2996                                 ps->performance_levels[i].sclk = max_sclk_vddc;
2997                 }
2998                 if (max_mclk_vddci) {
2999                         if (ps->performance_levels[i].mclk > max_mclk_vddci)
3000                                 ps->performance_levels[i].mclk = max_mclk_vddci;
3001                 }
3002                 if (max_mclk_vddc) {
3003                         if (ps->performance_levels[i].mclk > max_mclk_vddc)
3004                                 ps->performance_levels[i].mclk = max_mclk_vddc;
3005                 }
3006                 if (max_mclk) {
3007                         if (ps->performance_levels[i].mclk > max_mclk)
3008                                 ps->performance_levels[i].mclk = max_mclk;
3009                 }
3010                 if (max_sclk) {
3011                         if (ps->performance_levels[i].sclk > max_sclk)
3012                                 ps->performance_levels[i].sclk = max_sclk;
3013                 }
3014         }
3015
3016         /* XXX validate the min clocks required for display */
3017
3018         if (disable_mclk_switching) {
3019                 mclk  = ps->performance_levels[ps->performance_level_count - 1].mclk;
3020                 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
3021         } else {
3022                 mclk = ps->performance_levels[0].mclk;
3023                 vddci = ps->performance_levels[0].vddci;
3024         }
3025
3026         if (disable_sclk_switching) {
3027                 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;
3028                 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
3029         } else {
3030                 sclk = ps->performance_levels[0].sclk;
3031                 vddc = ps->performance_levels[0].vddc;
3032         }
3033
3034         /* adjusted low state */
3035         ps->performance_levels[0].sclk = sclk;
3036         ps->performance_levels[0].mclk = mclk;
3037         ps->performance_levels[0].vddc = vddc;
3038         ps->performance_levels[0].vddci = vddci;
3039
3040         if (disable_sclk_switching) {
3041                 sclk = ps->performance_levels[0].sclk;
3042                 for (i = 1; i < ps->performance_level_count; i++) {
3043                         if (sclk < ps->performance_levels[i].sclk)
3044                                 sclk = ps->performance_levels[i].sclk;
3045                 }
3046                 for (i = 0; i < ps->performance_level_count; i++) {
3047                         ps->performance_levels[i].sclk = sclk;
3048                         ps->performance_levels[i].vddc = vddc;
3049                 }
3050         } else {
3051                 for (i = 1; i < ps->performance_level_count; i++) {
3052                         if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
3053                                 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
3054                         if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
3055                                 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
3056                 }
3057         }
3058
3059         if (disable_mclk_switching) {
3060                 mclk = ps->performance_levels[0].mclk;
3061                 for (i = 1; i < ps->performance_level_count; i++) {
3062                         if (mclk < ps->performance_levels[i].mclk)
3063                                 mclk = ps->performance_levels[i].mclk;
3064                 }
3065                 for (i = 0; i < ps->performance_level_count; i++) {
3066                         ps->performance_levels[i].mclk = mclk;
3067                         ps->performance_levels[i].vddci = vddci;
3068                 }
3069         } else {
3070                 for (i = 1; i < ps->performance_level_count; i++) {
3071                         if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
3072                                 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
3073                         if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
3074                                 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
3075                 }
3076         }
3077
3078         for (i = 0; i < ps->performance_level_count; i++)
3079                 btc_adjust_clock_combinations(rdev, max_limits,
3080                                               &ps->performance_levels[i]);
3081
3082         for (i = 0; i < ps->performance_level_count; i++) {
3083                 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3084                                                    ps->performance_levels[i].sclk,
3085                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3086                 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3087                                                    ps->performance_levels[i].mclk,
3088                                                    max_limits->vddci, &ps->performance_levels[i].vddci);
3089                 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3090                                                    ps->performance_levels[i].mclk,
3091                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3092                 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
3093                                                    rdev->clock.current_dispclk,
3094                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3095         }
3096
3097         for (i = 0; i < ps->performance_level_count; i++) {
3098                 btc_apply_voltage_delta_rules(rdev,
3099                                               max_limits->vddc, max_limits->vddci,
3100                                               &ps->performance_levels[i].vddc,
3101                                               &ps->performance_levels[i].vddci);
3102         }
3103
3104         ps->dc_compatible = true;
3105         for (i = 0; i < ps->performance_level_count; i++) {
3106                 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3107                         ps->dc_compatible = false;
3108         }
3109
3110 }
3111
3112 #if 0
3113 static int si_read_smc_soft_register(struct radeon_device *rdev,
3114                                      u16 reg_offset, u32 *value)
3115 {
3116         struct si_power_info *si_pi = si_get_pi(rdev);
3117
3118         return si_read_smc_sram_dword(rdev,
3119                                       si_pi->soft_regs_start + reg_offset, value,
3120                                       si_pi->sram_end);
3121 }
3122 #endif
3123
3124 static int si_write_smc_soft_register(struct radeon_device *rdev,
3125                                       u16 reg_offset, u32 value)
3126 {
3127         struct si_power_info *si_pi = si_get_pi(rdev);
3128
3129         return si_write_smc_sram_dword(rdev,
3130                                        si_pi->soft_regs_start + reg_offset,
3131                                        value, si_pi->sram_end);
3132 }
3133
3134 static bool si_is_special_1gb_platform(struct radeon_device *rdev)
3135 {
3136         bool ret = false;
3137         u32 tmp, width, row, column, bank, density;
3138         bool is_memory_gddr5, is_special;
3139
3140         tmp = RREG32(MC_SEQ_MISC0);
3141         is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3142         is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3143                 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3144
3145         WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3146         width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3147
3148         tmp = RREG32(MC_ARB_RAMCFG);
3149         row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
3150         column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
3151         bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
3152
3153         density = (1 << (row + column - 20 + bank)) * width;
3154
3155         if ((rdev->pdev->device == 0x6819) &&
3156             is_memory_gddr5 && is_special && (density == 0x400))
3157                 ret = true;
3158
3159         return ret;
3160 }
3161
3162 static void si_get_leakage_vddc(struct radeon_device *rdev)
3163 {
3164         struct si_power_info *si_pi = si_get_pi(rdev);
3165         u16 vddc, count = 0;
3166         int i, ret;
3167
3168         for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3169                 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3170
3171                 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3172                         si_pi->leakage_voltage.entries[count].voltage = vddc;
3173                         si_pi->leakage_voltage.entries[count].leakage_index =
3174                                 SISLANDS_LEAKAGE_INDEX0 + i;
3175                         count++;
3176                 }
3177         }
3178         si_pi->leakage_voltage.count = count;
3179 }
3180
3181 static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev,
3182                                                      u32 index, u16 *leakage_voltage)
3183 {
3184         struct si_power_info *si_pi = si_get_pi(rdev);
3185         int i;
3186
3187         if (leakage_voltage == NULL)
3188                 return -EINVAL;
3189
3190         if ((index & 0xff00) != 0xff00)
3191                 return -EINVAL;
3192
3193         if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3194                 return -EINVAL;
3195
3196         if (index < SISLANDS_LEAKAGE_INDEX0)
3197                 return -EINVAL;
3198
3199         for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3200                 if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3201                         *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3202                         return 0;
3203                 }
3204         }
3205         return -EAGAIN;
3206 }
3207
3208 static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
3209 {
3210         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3211         bool want_thermal_protection;
3212         enum radeon_dpm_event_src dpm_event_src;
3213
3214         switch (sources) {
3215         case 0:
3216         default:
3217                 want_thermal_protection = false;
3218                 break;
3219         case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
3220                 want_thermal_protection = true;
3221                 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
3222                 break;
3223         case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3224                 want_thermal_protection = true;
3225                 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
3226                 break;
3227         case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3228               (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3229                 want_thermal_protection = true;
3230                 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3231                 break;
3232         }
3233
3234         if (want_thermal_protection) {
3235                 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
3236                 if (pi->thermal_protection)
3237                         WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3238         } else {
3239                 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3240         }
3241 }
3242
3243 static void si_enable_auto_throttle_source(struct radeon_device *rdev,
3244                                            enum radeon_dpm_auto_throttle_src source,
3245                                            bool enable)
3246 {
3247         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3248
3249         if (enable) {
3250                 if (!(pi->active_auto_throttle_sources & (1 << source))) {
3251                         pi->active_auto_throttle_sources |= 1 << source;
3252                         si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3253                 }
3254         } else {
3255                 if (pi->active_auto_throttle_sources & (1 << source)) {
3256                         pi->active_auto_throttle_sources &= ~(1 << source);
3257                         si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3258                 }
3259         }
3260 }
3261
3262 static void si_start_dpm(struct radeon_device *rdev)
3263 {
3264         WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
3265 }
3266
3267 static void si_stop_dpm(struct radeon_device *rdev)
3268 {
3269         WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
3270 }
3271
3272 static void si_enable_sclk_control(struct radeon_device *rdev, bool enable)
3273 {
3274         if (enable)
3275                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3276         else
3277                 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3278
3279 }
3280
3281 #if 0
3282 static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev,
3283                                                u32 thermal_level)
3284 {
3285         PPSMC_Result ret;
3286
3287         if (thermal_level == 0) {
3288                 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
3289                 if (ret == PPSMC_Result_OK)
3290                         return 0;
3291                 else
3292                         return -EINVAL;
3293         }
3294         return 0;
3295 }
3296
3297 static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev)
3298 {
3299         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3300 }
3301 #endif
3302
3303 #if 0
3304 static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power)
3305 {
3306         if (ac_power)
3307                 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3308                         0 : -EINVAL;
3309
3310         return 0;
3311 }
3312 #endif
3313
3314 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
3315                                                       PPSMC_Msg msg, u32 parameter)
3316 {
3317         WREG32(SMC_SCRATCH0, parameter);
3318         return si_send_msg_to_smc(rdev, msg);
3319 }
3320
3321 static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev)
3322 {
3323         if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3324                 return -EINVAL;
3325
3326         return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3327                 0 : -EINVAL;
3328 }
3329
3330 int si_dpm_force_performance_level(struct radeon_device *rdev,
3331                                    enum radeon_dpm_forced_level level)
3332 {
3333         struct radeon_ps *rps = rdev->pm.dpm.current_ps;
3334         struct ni_ps *ps = ni_get_ps(rps);
3335         u32 levels = ps->performance_level_count;
3336
3337         if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
3338                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3339                         return -EINVAL;
3340
3341                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3342                         return -EINVAL;
3343         } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
3344                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3345                         return -EINVAL;
3346
3347                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3348                         return -EINVAL;
3349         } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
3350                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3351                         return -EINVAL;
3352
3353                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3354                         return -EINVAL;
3355         }
3356
3357         rdev->pm.dpm.forced_level = level;
3358
3359         return 0;
3360 }
3361
3362 #if 0
3363 static int si_set_boot_state(struct radeon_device *rdev)
3364 {
3365         return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3366                 0 : -EINVAL;
3367 }
3368 #endif
3369
3370 static int si_set_sw_state(struct radeon_device *rdev)
3371 {
3372         return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3373                 0 : -EINVAL;
3374 }
3375
3376 static int si_halt_smc(struct radeon_device *rdev)
3377 {
3378         if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3379                 return -EINVAL;
3380
3381         return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ?
3382                 0 : -EINVAL;
3383 }
3384
3385 static int si_resume_smc(struct radeon_device *rdev)
3386 {
3387         if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3388                 return -EINVAL;
3389
3390         return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3391                 0 : -EINVAL;
3392 }
3393
3394 static void si_dpm_start_smc(struct radeon_device *rdev)
3395 {
3396         si_program_jump_on_start(rdev);
3397         si_start_smc(rdev);
3398         si_start_smc_clock(rdev);
3399 }
3400
3401 static void si_dpm_stop_smc(struct radeon_device *rdev)
3402 {
3403         si_reset_smc(rdev);
3404         si_stop_smc_clock(rdev);
3405 }
3406
3407 static int si_process_firmware_header(struct radeon_device *rdev)
3408 {
3409         struct si_power_info *si_pi = si_get_pi(rdev);
3410         u32 tmp;
3411         int ret;
3412
3413         ret = si_read_smc_sram_dword(rdev,
3414                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3415                                      SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
3416                                      &tmp, si_pi->sram_end);
3417         if (ret)
3418                 return ret;
3419
3420         si_pi->state_table_start = tmp;
3421
3422         ret = si_read_smc_sram_dword(rdev,
3423                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3424                                      SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
3425                                      &tmp, si_pi->sram_end);
3426         if (ret)
3427                 return ret;
3428
3429         si_pi->soft_regs_start = tmp;
3430
3431         ret = si_read_smc_sram_dword(rdev,
3432                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3433                                      SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
3434                                      &tmp, si_pi->sram_end);
3435         if (ret)
3436                 return ret;
3437
3438         si_pi->mc_reg_table_start = tmp;
3439
3440         ret = si_read_smc_sram_dword(rdev,
3441                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3442                                      SISLANDS_SMC_FIRMWARE_HEADER_fanTable,
3443                                      &tmp, si_pi->sram_end);
3444         if (ret)
3445                 return ret;
3446
3447         si_pi->fan_table_start = tmp;
3448
3449         ret = si_read_smc_sram_dword(rdev,
3450                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3451                                      SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
3452                                      &tmp, si_pi->sram_end);
3453         if (ret)
3454                 return ret;
3455
3456         si_pi->arb_table_start = tmp;
3457
3458         ret = si_read_smc_sram_dword(rdev,
3459                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3460                                      SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
3461                                      &tmp, si_pi->sram_end);
3462         if (ret)
3463                 return ret;
3464
3465         si_pi->cac_table_start = tmp;
3466
3467         ret = si_read_smc_sram_dword(rdev,
3468                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3469                                      SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
3470                                      &tmp, si_pi->sram_end);
3471         if (ret)
3472                 return ret;
3473
3474         si_pi->dte_table_start = tmp;
3475
3476         ret = si_read_smc_sram_dword(rdev,
3477                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3478                                      SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
3479                                      &tmp, si_pi->sram_end);
3480         if (ret)
3481                 return ret;
3482
3483         si_pi->spll_table_start = tmp;
3484
3485         ret = si_read_smc_sram_dword(rdev,
3486                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3487                                      SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
3488                                      &tmp, si_pi->sram_end);
3489         if (ret)
3490                 return ret;
3491
3492         si_pi->papm_cfg_table_start = tmp;
3493
3494         return ret;
3495 }
3496
3497 static void si_read_clock_registers(struct radeon_device *rdev)
3498 {
3499         struct si_power_info *si_pi = si_get_pi(rdev);
3500
3501         si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
3502         si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
3503         si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
3504         si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
3505         si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
3506         si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
3507         si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
3508         si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
3509         si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
3510         si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
3511         si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
3512         si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
3513         si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
3514         si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
3515         si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
3516 }
3517
3518 static void si_enable_thermal_protection(struct radeon_device *rdev,
3519                                           bool enable)
3520 {
3521         if (enable)
3522                 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3523         else
3524                 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3525 }
3526
3527 static void si_enable_acpi_power_management(struct radeon_device *rdev)
3528 {
3529         WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
3530 }
3531
3532 #if 0
3533 static int si_enter_ulp_state(struct radeon_device *rdev)
3534 {
3535         WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
3536
3537         udelay(25000);
3538
3539         return 0;
3540 }
3541
3542 static int si_exit_ulp_state(struct radeon_device *rdev)
3543 {
3544         int i;
3545
3546         WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
3547
3548         udelay(7000);
3549
3550         for (i = 0; i < rdev->usec_timeout; i++) {
3551                 if (RREG32(SMC_RESP_0) == 1)
3552                         break;
3553                 udelay(1000);
3554         }
3555
3556         return 0;
3557 }
3558 #endif
3559
3560 static int si_notify_smc_display_change(struct radeon_device *rdev,
3561                                      bool has_display)
3562 {
3563         PPSMC_Msg msg = has_display ?
3564                 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
3565
3566         return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ?
3567                 0 : -EINVAL;
3568 }
3569
3570 static void si_program_response_times(struct radeon_device *rdev)
3571 {
3572         u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;
3573         u32 vddc_dly, acpi_dly, vbi_dly;
3574         u32 reference_clock;
3575
3576         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
3577
3578         voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;
3579         backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time;
3580
3581         if (voltage_response_time == 0)
3582                 voltage_response_time = 1000;
3583
3584         acpi_delay_time = 15000;
3585         vbi_time_out = 100000;
3586
3587         reference_clock = radeon_get_xclk(rdev);
3588
3589         vddc_dly = (voltage_response_time  * reference_clock) / 100;
3590         acpi_dly = (acpi_delay_time * reference_clock) / 100;
3591         vbi_dly  = (vbi_time_out * reference_clock) / 100;
3592
3593         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg,  vddc_dly);
3594         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi,  acpi_dly);
3595         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
3596         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
3597 }
3598
3599 static void si_program_ds_registers(struct radeon_device *rdev)
3600 {
3601         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3602         u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */
3603
3604         if (eg_pi->sclk_deep_sleep) {
3605                 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
3606                 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,
3607                          ~AUTOSCALE_ON_SS_CLEAR);
3608         }
3609 }
3610
3611 static void si_program_display_gap(struct radeon_device *rdev)
3612 {
3613         u32 tmp, pipe;
3614         int i;
3615
3616         tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3617         if (rdev->pm.dpm.new_active_crtc_count > 0)
3618                 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3619         else
3620                 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3621
3622         if (rdev->pm.dpm.new_active_crtc_count > 1)
3623                 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3624         else
3625                 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3626
3627         WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3628
3629         tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
3630         pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
3631
3632         if ((rdev->pm.dpm.new_active_crtc_count > 0) &&
3633             (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
3634                 /* find the first active crtc */
3635                 for (i = 0; i < rdev->num_crtc; i++) {
3636                         if (rdev->pm.dpm.new_active_crtcs & (1 << i))
3637                                 break;
3638                 }
3639                 if (i == rdev->num_crtc)
3640                         pipe = 0;
3641                 else
3642                         pipe = i;
3643
3644                 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
3645                 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
3646                 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
3647         }
3648
3649         /* Setting this to false forces the performance state to low if the crtcs are disabled.
3650          * This can be a problem on PowerXpress systems or if you want to use the card
3651          * for offscreen rendering or compute if there are no crtcs enabled.
3652          */
3653         si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0);
3654 }
3655
3656 static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
3657 {
3658         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3659
3660         if (enable) {
3661                 if (pi->sclk_ss)
3662                         WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
3663         } else {
3664                 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
3665                 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
3666         }
3667 }
3668
3669 static void si_setup_bsp(struct radeon_device *rdev)
3670 {
3671         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3672         u32 xclk = radeon_get_xclk(rdev);
3673
3674         r600_calculate_u_and_p(pi->asi,
3675                                xclk,
3676                                16,
3677                                &pi->bsp,
3678                                &pi->bsu);
3679
3680         r600_calculate_u_and_p(pi->pasi,
3681                                xclk,
3682                                16,
3683                                &pi->pbsp,
3684                                &pi->pbsu);
3685
3686
3687         pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
3688         pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
3689
3690         WREG32(CG_BSP, pi->dsp);
3691 }
3692
3693 static void si_program_git(struct radeon_device *rdev)
3694 {
3695         WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
3696 }
3697
3698 static void si_program_tp(struct radeon_device *rdev)
3699 {
3700         int i;
3701         enum r600_td td = R600_TD_DFLT;
3702
3703         for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
3704                 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
3705
3706         if (td == R600_TD_AUTO)
3707                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
3708         else
3709                 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
3710
3711         if (td == R600_TD_UP)
3712                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
3713
3714         if (td == R600_TD_DOWN)
3715                 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
3716 }
3717
3718 static void si_program_tpp(struct radeon_device *rdev)
3719 {
3720         WREG32(CG_TPC, R600_TPC_DFLT);
3721 }
3722
3723 static void si_program_sstp(struct radeon_device *rdev)
3724 {
3725         WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
3726 }
3727
3728 static void si_enable_display_gap(struct radeon_device *rdev)
3729 {
3730         u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
3731
3732         tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3733         tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
3734                 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
3735
3736         tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
3737         tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
3738                 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
3739         WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3740 }
3741
3742 static void si_program_vc(struct radeon_device *rdev)
3743 {
3744         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3745
3746         WREG32(CG_FTV, pi->vrc);
3747 }
3748
3749 static void si_clear_vc(struct radeon_device *rdev)
3750 {
3751         WREG32(CG_FTV, 0);
3752 }
3753
3754 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
3755 {
3756         u8 mc_para_index;
3757
3758         if (memory_clock < 10000)
3759                 mc_para_index = 0;
3760         else if (memory_clock >= 80000)
3761                 mc_para_index = 0x0f;
3762         else
3763                 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
3764         return mc_para_index;
3765 }
3766
3767 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
3768 {
3769         u8 mc_para_index;
3770
3771         if (strobe_mode) {
3772                 if (memory_clock < 12500)
3773                         mc_para_index = 0x00;
3774                 else if (memory_clock > 47500)
3775                         mc_para_index = 0x0f;
3776                 else
3777                         mc_para_index = (u8)((memory_clock - 10000) / 2500);
3778         } else {
3779                 if (memory_clock < 65000)
3780                         mc_para_index = 0x00;
3781                 else if (memory_clock > 135000)
3782                         mc_para_index = 0x0f;
3783                 else
3784                         mc_para_index = (u8)((memory_clock - 60000) / 5000);
3785         }
3786         return mc_para_index;
3787 }
3788
3789 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk)
3790 {
3791         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3792         bool strobe_mode = false;
3793         u8 result = 0;
3794
3795         if (mclk <= pi->mclk_strobe_mode_threshold)
3796                 strobe_mode = true;
3797
3798         if (pi->mem_gddr5)
3799                 result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
3800         else
3801                 result = si_get_ddr3_mclk_frequency_ratio(mclk);
3802
3803         if (strobe_mode)
3804                 result |= SISLANDS_SMC_STROBE_ENABLE;
3805
3806         return result;
3807 }
3808
3809 static int si_upload_firmware(struct radeon_device *rdev)
3810 {
3811         struct si_power_info *si_pi = si_get_pi(rdev);
3812         int ret;
3813
3814         si_reset_smc(rdev);
3815         si_stop_smc_clock(rdev);
3816
3817         ret = si_load_smc_ucode(rdev, si_pi->sram_end);
3818
3819         return ret;
3820 }
3821
3822 static bool si_validate_phase_shedding_tables(struct radeon_device *rdev,
3823                                               const struct atom_voltage_table *table,
3824                                               const struct radeon_phase_shedding_limits_table *limits)
3825 {
3826         u32 data, num_bits, num_levels;
3827
3828         if ((table == NULL) || (limits == NULL))
3829                 return false;
3830
3831         data = table->mask_low;
3832
3833         num_bits = hweight32(data);
3834
3835         if (num_bits == 0)
3836                 return false;
3837
3838         num_levels = (1 << num_bits);
3839
3840         if (table->count != num_levels)
3841                 return false;
3842
3843         if (limits->count != (num_levels - 1))
3844                 return false;
3845
3846         return true;
3847 }
3848
3849 void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
3850                                               u32 max_voltage_steps,
3851                                               struct atom_voltage_table *voltage_table)
3852 {
3853         unsigned int i, diff;
3854
3855         if (voltage_table->count <= max_voltage_steps)
3856                 return;
3857
3858         diff = voltage_table->count - max_voltage_steps;
3859
3860         for (i= 0; i < max_voltage_steps; i++)
3861                 voltage_table->entries[i] = voltage_table->entries[i + diff];
3862
3863         voltage_table->count = max_voltage_steps;
3864 }
3865
3866 static int si_get_svi2_voltage_table(struct radeon_device *rdev,
3867                                      struct radeon_clock_voltage_dependency_table *voltage_dependency_table,
3868                                      struct atom_voltage_table *voltage_table)
3869 {
3870         u32 i;
3871
3872         if (voltage_dependency_table == NULL)
3873                 return -EINVAL;
3874
3875         voltage_table->mask_low = 0;
3876         voltage_table->phase_delay = 0;
3877
3878         voltage_table->count = voltage_dependency_table->count;
3879         for (i = 0; i < voltage_table->count; i++) {
3880                 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
3881                 voltage_table->entries[i].smio_low = 0;
3882         }
3883
3884         return 0;
3885 }
3886
3887 static int si_construct_voltage_tables(struct radeon_device *rdev)
3888 {
3889         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3890         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3891         struct si_power_info *si_pi = si_get_pi(rdev);
3892         int ret;
3893
3894         if (pi->voltage_control) {
3895                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
3896                                                     VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
3897                 if (ret)
3898                         return ret;
3899
3900                 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3901                         si_trim_voltage_table_to_fit_state_table(rdev,
3902                                                                  SISLANDS_MAX_NO_VREG_STEPS,
3903                                                                  &eg_pi->vddc_voltage_table);
3904         } else if (si_pi->voltage_control_svi2) {
3905                 ret = si_get_svi2_voltage_table(rdev,
3906                                                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3907                                                 &eg_pi->vddc_voltage_table);
3908                 if (ret)
3909                         return ret;
3910         } else {
3911                 return -EINVAL;
3912         }
3913
3914         if (eg_pi->vddci_control) {
3915                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
3916                                                     VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
3917                 if (ret)
3918                         return ret;
3919
3920                 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3921                         si_trim_voltage_table_to_fit_state_table(rdev,
3922                                                                  SISLANDS_MAX_NO_VREG_STEPS,
3923                                                                  &eg_pi->vddci_voltage_table);
3924         }
3925         if (si_pi->vddci_control_svi2) {
3926                 ret = si_get_svi2_voltage_table(rdev,
3927                                                 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3928                                                 &eg_pi->vddci_voltage_table);
3929                 if (ret)
3930                         return ret;
3931         }
3932
3933         if (pi->mvdd_control) {
3934                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
3935                                                     VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
3936
3937                 if (ret) {
3938                         pi->mvdd_control = false;
3939                         return ret;
3940                 }
3941
3942                 if (si_pi->mvdd_voltage_table.count == 0) {
3943                         pi->mvdd_control = false;
3944                         return -EINVAL;
3945                 }
3946
3947                 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3948                         si_trim_voltage_table_to_fit_state_table(rdev,
3949                                                                  SISLANDS_MAX_NO_VREG_STEPS,
3950                                                                  &si_pi->mvdd_voltage_table);
3951         }
3952
3953         if (si_pi->vddc_phase_shed_control) {
3954                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
3955                                                     VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
3956                 if (ret)
3957                         si_pi->vddc_phase_shed_control = false;
3958
3959                 if ((si_pi->vddc_phase_shed_table.count == 0) ||
3960                     (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
3961                         si_pi->vddc_phase_shed_control = false;
3962         }
3963
3964         return 0;
3965 }
3966
3967 static void si_populate_smc_voltage_table(struct radeon_device *rdev,
3968                                           const struct atom_voltage_table *voltage_table,
3969                                           SISLANDS_SMC_STATETABLE *table)
3970 {
3971         unsigned int i;
3972
3973         for (i = 0; i < voltage_table->count; i++)
3974                 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
3975 }
3976
3977 static int si_populate_smc_voltage_tables(struct radeon_device *rdev,
3978                                           SISLANDS_SMC_STATETABLE *table)
3979 {
3980         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3981         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3982         struct si_power_info *si_pi = si_get_pi(rdev);
3983         u8 i;
3984
3985         if (si_pi->voltage_control_svi2) {
3986                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc,
3987                         si_pi->svc_gpio_id);
3988                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd,
3989                         si_pi->svd_gpio_id);
3990                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type,
3991                                            2);
3992         } else {
3993                 if (eg_pi->vddc_voltage_table.count) {
3994                         si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table);
3995                         table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
3996                                 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
3997
3998                         for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
3999                                 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
4000                                         table->maxVDDCIndexInPPTable = i;
4001                                         break;
4002                                 }
4003                         }
4004                 }
4005
4006                 if (eg_pi->vddci_voltage_table.count) {
4007                         si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table);
4008
4009                         table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
4010                                 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
4011                 }
4012
4013
4014                 if (si_pi->mvdd_voltage_table.count) {
4015                         si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table);
4016
4017                         table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
4018                                 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
4019                 }
4020
4021                 if (si_pi->vddc_phase_shed_control) {
4022                         if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table,
4023                                                               &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
4024                                 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table);
4025
4026                                 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
4027                                         cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
4028
4029                                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
4030                                                            (u32)si_pi->vddc_phase_shed_table.phase_delay);
4031                         } else {
4032                                 si_pi->vddc_phase_shed_control = false;
4033                         }
4034                 }
4035         }
4036
4037         return 0;
4038 }
4039
4040 static int si_populate_voltage_value(struct radeon_device *rdev,
4041                                      const struct atom_voltage_table *table,
4042                                      u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4043 {
4044         unsigned int i;
4045
4046         for (i = 0; i < table->count; i++) {
4047                 if (value <= table->entries[i].value) {
4048                         voltage->index = (u8)i;
4049                         voltage->value = cpu_to_be16(table->entries[i].value);
4050                         break;
4051                 }
4052         }
4053
4054         if (i >= table->count)
4055                 return -EINVAL;
4056
4057         return 0;
4058 }
4059
4060 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
4061                                   SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4062 {
4063         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4064         struct si_power_info *si_pi = si_get_pi(rdev);
4065
4066         if (pi->mvdd_control) {
4067                 if (mclk <= pi->mvdd_split_frequency)
4068                         voltage->index = 0;
4069                 else
4070                         voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
4071
4072                 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
4073         }
4074         return 0;
4075 }
4076
4077 static int si_get_std_voltage_value(struct radeon_device *rdev,
4078                                     SISLANDS_SMC_VOLTAGE_VALUE *voltage,
4079                                     u16 *std_voltage)
4080 {
4081         u16 v_index;
4082         bool voltage_found = false;
4083         *std_voltage = be16_to_cpu(voltage->value);
4084
4085         if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
4086                 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
4087                         if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
4088                                 return -EINVAL;
4089
4090                         for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4091                                 if (be16_to_cpu(voltage->value) ==
4092                                     (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4093                                         voltage_found = true;
4094                                         if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4095                                                 *std_voltage =
4096                                                         rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4097                                         else
4098                                                 *std_voltage =
4099                                                         rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4100                                         break;
4101                                 }
4102                         }
4103
4104                         if (!voltage_found) {
4105                                 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4106                                         if (be16_to_cpu(voltage->value) <=
4107                                             (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4108                                                 voltage_found = true;
4109                                                 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4110                                                         *std_voltage =
4111                                                                 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4112                                                 else
4113                                                         *std_voltage =
4114                                                                 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4115                                                 break;
4116                                         }
4117                                 }
4118                         }
4119                 } else {
4120                         if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4121                                 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4122                 }
4123         }
4124
4125         return 0;
4126 }
4127
4128 static int si_populate_std_voltage_value(struct radeon_device *rdev,
4129                                          u16 value, u8 index,
4130                                          SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4131 {
4132         voltage->index = index;
4133         voltage->value = cpu_to_be16(value);
4134
4135         return 0;
4136 }
4137
4138 static int si_populate_phase_shedding_value(struct radeon_device *rdev,
4139                                             const struct radeon_phase_shedding_limits_table *limits,
4140                                             u16 voltage, u32 sclk, u32 mclk,
4141                                             SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
4142 {
4143         unsigned int i;
4144
4145         for (i = 0; i < limits->count; i++) {
4146                 if ((voltage <= limits->entries[i].voltage) &&
4147                     (sclk <= limits->entries[i].sclk) &&
4148                     (mclk <= limits->entries[i].mclk))
4149                         break;
4150         }
4151
4152         smc_voltage->phase_settings = (u8)i;
4153
4154         return 0;
4155 }
4156
4157 static int si_init_arb_table_index(struct radeon_device *rdev)
4158 {
4159         struct si_power_info *si_pi = si_get_pi(rdev);
4160         u32 tmp;
4161         int ret;
4162
4163         ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end);
4164         if (ret)
4165                 return ret;
4166
4167         tmp &= 0x00FFFFFF;
4168         tmp |= MC_CG_ARB_FREQ_F1 << 24;
4169
4170         return si_write_smc_sram_dword(rdev, si_pi->arb_table_start,  tmp, si_pi->sram_end);
4171 }
4172
4173 static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
4174 {
4175         return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4176 }
4177
4178 static int si_reset_to_default(struct radeon_device *rdev)
4179 {
4180         return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4181                 0 : -EINVAL;
4182 }
4183
4184 static int si_force_switch_to_arb_f0(struct radeon_device *rdev)
4185 {
4186         struct si_power_info *si_pi = si_get_pi(rdev);
4187         u32 tmp;
4188         int ret;
4189
4190         ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start,
4191                                      &tmp, si_pi->sram_end);
4192         if (ret)
4193                 return ret;
4194
4195         tmp = (tmp >> 24) & 0xff;
4196
4197         if (tmp == MC_CG_ARB_FREQ_F0)
4198                 return 0;
4199
4200         return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
4201 }
4202
4203 static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev,
4204                                             u32 engine_clock)
4205 {
4206         u32 dram_rows;
4207         u32 dram_refresh_rate;
4208         u32 mc_arb_rfsh_rate;
4209         u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
4210
4211         if (tmp >= 4)
4212                 dram_rows = 16384;
4213         else
4214                 dram_rows = 1 << (tmp + 10);
4215
4216         dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4217         mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4218
4219         return mc_arb_rfsh_rate;
4220 }
4221
4222 static int si_populate_memory_timing_parameters(struct radeon_device *rdev,
4223                                                 struct rv7xx_pl *pl,
4224                                                 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4225 {
4226         u32 dram_timing;
4227         u32 dram_timing2;
4228         u32 burst_time;
4229
4230         arb_regs->mc_arb_rfsh_rate =
4231                 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk);
4232
4233         radeon_atom_set_engine_dram_timings(rdev,
4234                                             pl->sclk,
4235                                             pl->mclk);
4236
4237         dram_timing  = RREG32(MC_ARB_DRAM_TIMING);
4238         dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4239         burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4240
4241         arb_regs->mc_arb_dram_timing  = cpu_to_be32(dram_timing);
4242         arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4243         arb_regs->mc_arb_burst_time = (u8)burst_time;
4244
4245         return 0;
4246 }
4247
4248 static int si_do_program_memory_timing_parameters(struct radeon_device *rdev,
4249                                                   struct radeon_ps *radeon_state,
4250                                                   unsigned int first_arb_set)
4251 {
4252         struct si_power_info *si_pi = si_get_pi(rdev);
4253         struct ni_ps *state = ni_get_ps(radeon_state);
4254         SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4255         int i, ret = 0;
4256
4257         for (i = 0; i < state->performance_level_count; i++) {
4258                 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs);
4259                 if (ret)
4260                         break;
4261                 ret = si_copy_bytes_to_smc(rdev,
4262                                            si_pi->arb_table_start +
4263                                            offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4264                                            sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4265                                            (u8 *)&arb_regs,
4266                                            sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4267                                            si_pi->sram_end);
4268                 if (ret)
4269                         break;
4270         }
4271
4272         return ret;
4273 }
4274
4275 static int si_program_memory_timing_parameters(struct radeon_device *rdev,
4276                                                struct radeon_ps *radeon_new_state)
4277 {
4278         return si_do_program_memory_timing_parameters(rdev, radeon_new_state,
4279                                                       SISLANDS_DRIVER_STATE_ARB_INDEX);
4280 }
4281
4282 static int si_populate_initial_mvdd_value(struct radeon_device *rdev,
4283                                           struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4284 {
4285         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4286         struct si_power_info *si_pi = si_get_pi(rdev);
4287
4288         if (pi->mvdd_control)
4289                 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table,
4290                                                  si_pi->mvdd_bootup_value, voltage);
4291
4292         return 0;
4293 }
4294
4295 static int si_populate_smc_initial_state(struct radeon_device *rdev,
4296                                          struct radeon_ps *radeon_initial_state,
4297                                          SISLANDS_SMC_STATETABLE *table)
4298 {
4299         struct ni_ps *initial_state = ni_get_ps(radeon_initial_state);
4300         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4301         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4302         struct si_power_info *si_pi = si_get_pi(rdev);
4303         u32 reg;
4304         int ret;
4305
4306         table->initialState.levels[0].mclk.vDLL_CNTL =
4307                 cpu_to_be32(si_pi->clock_registers.dll_cntl);
4308         table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4309                 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4310         table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4311                 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4312         table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4313                 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4314         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
4315                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4316         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4317                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4318         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4319                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4320         table->initialState.levels[0].mclk.vMPLL_SS =
4321                 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4322         table->initialState.levels[0].mclk.vMPLL_SS2 =
4323                 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4324
4325         table->initialState.levels[0].mclk.mclk_value =
4326                 cpu_to_be32(initial_state->performance_levels[0].mclk);
4327
4328         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4329                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4330         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4331                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4332         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4333                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4334         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4335                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4336         table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
4337                 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4338         table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2  =
4339                 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4340
4341         table->initialState.levels[0].sclk.sclk_value =
4342                 cpu_to_be32(initial_state->performance_levels[0].sclk);
4343
4344         table->initialState.levels[0].arbRefreshState =
4345                 SISLANDS_INITIAL_STATE_ARB_INDEX;
4346
4347         table->initialState.levels[0].ACIndex = 0;
4348
4349         ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4350                                         initial_state->performance_levels[0].vddc,
4351                                         &table->initialState.levels[0].vddc);
4352
4353         if (!ret) {
4354                 u16 std_vddc;
4355
4356                 ret = si_get_std_voltage_value(rdev,
4357                                                &table->initialState.levels[0].vddc,
4358                                                &std_vddc);
4359                 if (!ret)
4360                         si_populate_std_voltage_value(rdev, std_vddc,
4361                                                       table->initialState.levels[0].vddc.index,
4362                                                       &table->initialState.levels[0].std_vddc);
4363         }
4364
4365         if (eg_pi->vddci_control)
4366                 si_populate_voltage_value(rdev,
4367                                           &eg_pi->vddci_voltage_table,
4368                                           initial_state->performance_levels[0].vddci,
4369                                           &table->initialState.levels[0].vddci);
4370
4371         if (si_pi->vddc_phase_shed_control)
4372                 si_populate_phase_shedding_value(rdev,
4373                                                  &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4374                                                  initial_state->performance_levels[0].vddc,
4375                                                  initial_state->performance_levels[0].sclk,
4376                                                  initial_state->performance_levels[0].mclk,
4377                                                  &table->initialState.levels[0].vddc);
4378
4379         si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd);
4380
4381         reg = CG_R(0xffff) | CG_L(0);
4382         table->initialState.levels[0].aT = cpu_to_be32(reg);
4383
4384         table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
4385
4386         table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
4387
4388         if (pi->mem_gddr5) {
4389                 table->initialState.levels[0].strobeMode =
4390                         si_get_strobe_mode_settings(rdev,
4391                                                     initial_state->performance_levels[0].mclk);
4392
4393                 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4394                         table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4395                 else
4396                         table->initialState.levels[0].mcFlags =  0;
4397         }
4398
4399         table->initialState.levelCount = 1;
4400
4401         table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4402
4403         table->initialState.levels[0].dpm2.MaxPS = 0;
4404         table->initialState.levels[0].dpm2.NearTDPDec = 0;
4405         table->initialState.levels[0].dpm2.AboveSafeInc = 0;
4406         table->initialState.levels[0].dpm2.BelowSafeInc = 0;
4407         table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4408
4409         reg = MIN_POWER_MASK | MAX_POWER_MASK;
4410         table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4411
4412         reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4413         table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4414
4415         return 0;
4416 }
4417
4418 static int si_populate_smc_acpi_state(struct radeon_device *rdev,
4419                                       SISLANDS_SMC_STATETABLE *table)
4420 {
4421         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4422         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4423         struct si_power_info *si_pi = si_get_pi(rdev);
4424         u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4425         u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4426         u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4427         u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4428         u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4429         u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4430         u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4431         u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4432         u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4433         u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4434         u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4435         u32 reg;
4436         int ret;
4437
4438         table->ACPIState = table->initialState;
4439
4440         table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
4441
4442         if (pi->acpi_vddc) {
4443                 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4444                                                 pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
4445                 if (!ret) {
4446                         u16 std_vddc;
4447
4448                         ret = si_get_std_voltage_value(rdev,
4449                                                        &table->ACPIState.levels[0].vddc, &std_vddc);
4450                         if (!ret)
4451                                 si_populate_std_voltage_value(rdev, std_vddc,
4452                                                               table->ACPIState.levels[0].vddc.index,
4453                                                               &table->ACPIState.levels[0].std_vddc);
4454                 }
4455                 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
4456
4457                 if (si_pi->vddc_phase_shed_control) {
4458                         si_populate_phase_shedding_value(rdev,
4459                                                          &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4460                                                          pi->acpi_vddc,
4461                                                          0,
4462                                                          0,
4463                                                          &table->ACPIState.levels[0].vddc);
4464                 }
4465         } else {
4466                 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4467                                                 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
4468                 if (!ret) {
4469                         u16 std_vddc;
4470
4471                         ret = si_get_std_voltage_value(rdev,
4472                                                        &table->ACPIState.levels[0].vddc, &std_vddc);
4473
4474                         if (!ret)
4475                                 si_populate_std_voltage_value(rdev, std_vddc,
4476                                                               table->ACPIState.levels[0].vddc.index,
4477                                                               &table->ACPIState.levels[0].std_vddc);
4478                 }
4479                 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev,
4480                                                                                     si_pi->sys_pcie_mask,
4481                                                                                     si_pi->boot_pcie_gen,
4482                                                                                     RADEON_PCIE_GEN1);
4483
4484                 if (si_pi->vddc_phase_shed_control)
4485                         si_populate_phase_shedding_value(rdev,
4486                                                          &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4487                                                          pi->min_vddc_in_table,
4488                                                          0,
4489                                                          0,
4490                                                          &table->ACPIState.levels[0].vddc);
4491         }
4492
4493         if (pi->acpi_vddc) {
4494                 if (eg_pi->acpi_vddci)
4495                         si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
4496                                                   eg_pi->acpi_vddci,
4497                                                   &table->ACPIState.levels[0].vddci);
4498         }
4499
4500         mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
4501         mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4502
4503         dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
4504
4505         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4506         spll_func_cntl_2 |= SCLK_MUX_SEL(4);
4507
4508         table->ACPIState.levels[0].mclk.vDLL_CNTL =
4509                 cpu_to_be32(dll_cntl);
4510         table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4511                 cpu_to_be32(mclk_pwrmgt_cntl);
4512         table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4513                 cpu_to_be32(mpll_ad_func_cntl);
4514         table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4515                 cpu_to_be32(mpll_dq_func_cntl);
4516         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
4517                 cpu_to_be32(mpll_func_cntl);
4518         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4519                 cpu_to_be32(mpll_func_cntl_1);
4520         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4521                 cpu_to_be32(mpll_func_cntl_2);
4522         table->ACPIState.levels[0].mclk.vMPLL_SS =
4523                 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4524         table->ACPIState.levels[0].mclk.vMPLL_SS2 =
4525                 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4526
4527         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4528                 cpu_to_be32(spll_func_cntl);
4529         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4530                 cpu_to_be32(spll_func_cntl_2);
4531         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4532                 cpu_to_be32(spll_func_cntl_3);
4533         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4534                 cpu_to_be32(spll_func_cntl_4);
4535
4536         table->ACPIState.levels[0].mclk.mclk_value = 0;
4537         table->ACPIState.levels[0].sclk.sclk_value = 0;
4538
4539         si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
4540
4541         if (eg_pi->dynamic_ac_timing)
4542                 table->ACPIState.levels[0].ACIndex = 0;
4543
4544         table->ACPIState.levels[0].dpm2.MaxPS = 0;
4545         table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
4546         table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
4547         table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
4548         table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4549
4550         reg = MIN_POWER_MASK | MAX_POWER_MASK;
4551         table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4552
4553         reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4554         table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4555
4556         return 0;
4557 }
4558
4559 static int si_populate_ulv_state(struct radeon_device *rdev,
4560                                  SISLANDS_SMC_SWSTATE *state)
4561 {
4562         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4563         struct si_power_info *si_pi = si_get_pi(rdev);
4564         struct si_ulv_param *ulv = &si_pi->ulv;
4565         u32 sclk_in_sr = 1350; /* ??? */
4566         int ret;
4567
4568         ret = si_convert_power_level_to_smc(rdev, &ulv->pl,
4569                                             &state->levels[0]);
4570         if (!ret) {
4571                 if (eg_pi->sclk_deep_sleep) {
4572                         if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
4573                                 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
4574                         else
4575                                 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
4576                 }
4577                 if (ulv->one_pcie_lane_in_ulv)
4578                         state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
4579                 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
4580                 state->levels[0].ACIndex = 1;
4581                 state->levels[0].std_vddc = state->levels[0].vddc;
4582                 state->levelCount = 1;
4583
4584                 state->flags |= PPSMC_SWSTATE_FLAG_DC;
4585         }
4586
4587         return ret;
4588 }
4589
4590 static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev)
4591 {
4592         struct si_power_info *si_pi = si_get_pi(rdev);
4593         struct si_ulv_param *ulv = &si_pi->ulv;
4594         SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4595         int ret;
4596
4597         ret = si_populate_memory_timing_parameters(rdev, &ulv->pl,
4598                                                    &arb_regs);
4599         if (ret)
4600                 return ret;
4601
4602         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
4603                                    ulv->volt_change_delay);
4604
4605         ret = si_copy_bytes_to_smc(rdev,
4606                                    si_pi->arb_table_start +
4607                                    offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4608                                    sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
4609                                    (u8 *)&arb_regs,
4610                                    sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4611                                    si_pi->sram_end);
4612
4613         return ret;
4614 }
4615
4616 static void si_get_mvdd_configuration(struct radeon_device *rdev)
4617 {
4618         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4619
4620         pi->mvdd_split_frequency = 30000;
4621 }
4622
4623 static int si_init_smc_table(struct radeon_device *rdev)
4624 {
4625         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4626         struct si_power_info *si_pi = si_get_pi(rdev);
4627         struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
4628         const struct si_ulv_param *ulv = &si_pi->ulv;
4629         SISLANDS_SMC_STATETABLE  *table = &si_pi->smc_statetable;
4630         int ret;
4631         u32 lane_width;
4632         u32 vr_hot_gpio;
4633
4634         si_populate_smc_voltage_tables(rdev, table);
4635
4636         switch (rdev->pm.int_thermal_type) {
4637         case THERMAL_TYPE_SI:
4638         case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
4639                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
4640                 break;
4641         case THERMAL_TYPE_NONE:
4642                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
4643                 break;
4644         default:
4645                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
4646                 break;
4647         }
4648
4649         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
4650                 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
4651
4652         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
4653                 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819))
4654                         table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
4655         }
4656
4657         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
4658                 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
4659
4660         if (pi->mem_gddr5)
4661                 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
4662
4663         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
4664                 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
4665
4666         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
4667                 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
4668                 vr_hot_gpio = rdev->pm.dpm.backbias_response_time;
4669                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
4670                                            vr_hot_gpio);
4671         }
4672
4673         ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table);
4674         if (ret)
4675                 return ret;
4676
4677         ret = si_populate_smc_acpi_state(rdev, table);
4678         if (ret)
4679                 return ret;
4680
4681         table->driverState = table->initialState;
4682
4683         ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state,
4684                                                      SISLANDS_INITIAL_STATE_ARB_INDEX);
4685         if (ret)
4686                 return ret;
4687
4688         if (ulv->supported && ulv->pl.vddc) {
4689                 ret = si_populate_ulv_state(rdev, &table->ULVState);
4690                 if (ret)
4691                         return ret;
4692
4693                 ret = si_program_ulv_memory_timing_parameters(rdev);
4694                 if (ret)
4695                         return ret;
4696
4697                 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
4698                 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
4699
4700                 lane_width = radeon_get_pcie_lanes(rdev);
4701                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
4702         } else {
4703                 table->ULVState = table->initialState;
4704         }
4705
4706         return si_copy_bytes_to_smc(rdev, si_pi->state_table_start,
4707                                     (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
4708                                     si_pi->sram_end);
4709 }
4710
4711 static int si_calculate_sclk_params(struct radeon_device *rdev,
4712                                     u32 engine_clock,
4713                                     SISLANDS_SMC_SCLK_VALUE *sclk)
4714 {
4715         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4716         struct si_power_info *si_pi = si_get_pi(rdev);
4717         struct atom_clock_dividers dividers;
4718         u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4719         u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4720         u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4721         u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4722         u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
4723         u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
4724         u64 tmp;
4725         u32 reference_clock = rdev->clock.spll.reference_freq;
4726         u32 reference_divider;
4727         u32 fbdiv;
4728         int ret;
4729
4730         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
4731                                              engine_clock, false, &dividers);
4732         if (ret)
4733                 return ret;
4734
4735         reference_divider = 1 + dividers.ref_div;
4736
4737         tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
4738         do_div(tmp, reference_clock);
4739         fbdiv = (u32) tmp;
4740
4741         spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
4742         spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
4743         spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
4744
4745         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4746         spll_func_cntl_2 |= SCLK_MUX_SEL(2);
4747
4748         spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
4749         spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
4750         spll_func_cntl_3 |= SPLL_DITHEN;
4751
4752         if (pi->sclk_ss) {
4753                 struct radeon_atom_ss ss;
4754                 u32 vco_freq = engine_clock * dividers.post_div;
4755
4756                 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4757                                                      ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
4758                         u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
4759                         u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
4760
4761                         cg_spll_spread_spectrum &= ~CLK_S_MASK;
4762                         cg_spll_spread_spectrum |= CLK_S(clk_s);
4763                         cg_spll_spread_spectrum |= SSEN;
4764
4765                         cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
4766                         cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
4767                 }
4768         }
4769
4770         sclk->sclk_value = engine_clock;
4771         sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
4772         sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
4773         sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
4774         sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
4775         sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
4776         sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
4777
4778         return 0;
4779 }
4780
4781 static int si_populate_sclk_value(struct radeon_device *rdev,
4782                                   u32 engine_clock,
4783                                   SISLANDS_SMC_SCLK_VALUE *sclk)
4784 {
4785         SISLANDS_SMC_SCLK_VALUE sclk_tmp;
4786         int ret;
4787
4788         ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp);
4789         if (!ret) {
4790                 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
4791                 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
4792                 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
4793                 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
4794                 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
4795                 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
4796                 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
4797         }
4798
4799         return ret;
4800 }
4801
4802 static int si_populate_mclk_value(struct radeon_device *rdev,
4803                                   u32 engine_clock,
4804                                   u32 memory_clock,
4805                                   SISLANDS_SMC_MCLK_VALUE *mclk,
4806                                   bool strobe_mode,
4807                                   bool dll_state_on)
4808 {
4809         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4810         struct si_power_info *si_pi = si_get_pi(rdev);
4811         u32  dll_cntl = si_pi->clock_registers.dll_cntl;
4812         u32  mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4813         u32  mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4814         u32  mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4815         u32  mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4816         u32  mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4817         u32  mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4818         u32  mpll_ss1 = si_pi->clock_registers.mpll_ss1;
4819         u32  mpll_ss2 = si_pi->clock_registers.mpll_ss2;
4820         struct atom_mpll_param mpll_param;
4821         int ret;
4822
4823         ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
4824         if (ret)
4825                 return ret;
4826
4827         mpll_func_cntl &= ~BWCTRL_MASK;
4828         mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
4829
4830         mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
4831         mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
4832                 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
4833
4834         mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
4835         mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
4836
4837         if (pi->mem_gddr5) {
4838                 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
4839                 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
4840                         YCLK_POST_DIV(mpll_param.post_div);
4841         }
4842
4843         if (pi->mclk_ss) {
4844                 struct radeon_atom_ss ss;
4845                 u32 freq_nom;
4846                 u32 tmp;
4847                 u32 reference_clock = rdev->clock.mpll.reference_freq;
4848
4849                 if (pi->mem_gddr5)
4850                         freq_nom = memory_clock * 4;
4851                 else
4852                         freq_nom = memory_clock * 2;
4853
4854                 tmp = freq_nom / reference_clock;
4855                 tmp = tmp * tmp;
4856                 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4857                                                      ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
4858                         u32 clks = reference_clock * 5 / ss.rate;
4859                         u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
4860
4861                         mpll_ss1 &= ~CLKV_MASK;
4862                         mpll_ss1 |= CLKV(clkv);
4863
4864                         mpll_ss2 &= ~CLKS_MASK;
4865                         mpll_ss2 |= CLKS(clks);
4866                 }
4867         }
4868
4869         mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
4870         mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
4871
4872         if (dll_state_on)
4873                 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
4874         else
4875                 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4876
4877         mclk->mclk_value = cpu_to_be32(memory_clock);
4878         mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
4879         mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
4880         mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
4881         mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
4882         mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
4883         mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
4884         mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
4885         mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
4886         mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
4887
4888         return 0;
4889 }
4890
4891 static void si_populate_smc_sp(struct radeon_device *rdev,
4892                                struct radeon_ps *radeon_state,
4893                                SISLANDS_SMC_SWSTATE *smc_state)
4894 {
4895         struct ni_ps *ps = ni_get_ps(radeon_state);
4896         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4897         int i;
4898
4899         for (i = 0; i < ps->performance_level_count - 1; i++)
4900                 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
4901
4902         smc_state->levels[ps->performance_level_count - 1].bSP =
4903                 cpu_to_be32(pi->psp);
4904 }
4905
4906 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
4907                                          struct rv7xx_pl *pl,
4908                                          SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
4909 {
4910         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4911         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4912         struct si_power_info *si_pi = si_get_pi(rdev);
4913         int ret;
4914         bool dll_state_on;
4915         u16 std_vddc;
4916         bool gmc_pg = false;
4917
4918         if (eg_pi->pcie_performance_request &&
4919             (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID))
4920                 level->gen2PCIE = (u8)si_pi->force_pcie_gen;
4921         else
4922                 level->gen2PCIE = (u8)pl->pcie_gen;
4923
4924         ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk);
4925         if (ret)
4926                 return ret;
4927
4928         level->mcFlags =  0;
4929
4930         if (pi->mclk_stutter_mode_threshold &&
4931             (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
4932             !eg_pi->uvd_enabled &&
4933             (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
4934             (rdev->pm.dpm.new_active_crtc_count <= 2)) {
4935                 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
4936
4937                 if (gmc_pg)
4938                         level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
4939         }
4940
4941         if (pi->mem_gddr5) {
4942                 if (pl->mclk > pi->mclk_edc_enable_threshold)
4943                         level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
4944
4945                 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
4946                         level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
4947
4948                 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk);
4949
4950                 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
4951                         if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
4952                             ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
4953                                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
4954                         else
4955                                 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
4956                 } else {
4957                         dll_state_on = false;
4958                 }
4959         } else {
4960                 level->strobeMode = si_get_strobe_mode_settings(rdev,
4961                                                                 pl->mclk);
4962
4963                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
4964         }
4965
4966         ret = si_populate_mclk_value(rdev,
4967                                      pl->sclk,
4968                                      pl->mclk,
4969                                      &level->mclk,
4970                                      (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
4971         if (ret)
4972                 return ret;
4973
4974         ret = si_populate_voltage_value(rdev,
4975                                         &eg_pi->vddc_voltage_table,
4976                                         pl->vddc, &level->vddc);
4977         if (ret)
4978                 return ret;
4979
4980
4981         ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc);
4982         if (ret)
4983                 return ret;
4984
4985         ret = si_populate_std_voltage_value(rdev, std_vddc,
4986                                             level->vddc.index, &level->std_vddc);
4987         if (ret)
4988                 return ret;
4989
4990         if (eg_pi->vddci_control) {
4991                 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
4992                                                 pl->vddci, &level->vddci);
4993                 if (ret)
4994                         return ret;
4995         }
4996
4997         if (si_pi->vddc_phase_shed_control) {
4998                 ret = si_populate_phase_shedding_value(rdev,
4999                                                        &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
5000                                                        pl->vddc,
5001                                                        pl->sclk,
5002                                                        pl->mclk,
5003                                                        &level->vddc);
5004                 if (ret)
5005                         return ret;
5006         }
5007
5008         level->MaxPoweredUpCU = si_pi->max_cu;
5009
5010         ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);
5011
5012         return ret;
5013 }
5014
5015 static int si_populate_smc_t(struct radeon_device *rdev,
5016                              struct radeon_ps *radeon_state,
5017                              SISLANDS_SMC_SWSTATE *smc_state)
5018 {
5019         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5020         struct ni_ps *state = ni_get_ps(radeon_state);
5021         u32 a_t;
5022         u32 t_l, t_h;
5023         u32 high_bsp;
5024         int i, ret;
5025
5026         if (state->performance_level_count >= 9)
5027                 return -EINVAL;
5028
5029         if (state->performance_level_count < 2) {
5030                 a_t = CG_R(0xffff) | CG_L(0);
5031                 smc_state->levels[0].aT = cpu_to_be32(a_t);
5032                 return 0;
5033         }
5034
5035         smc_state->levels[0].aT = cpu_to_be32(0);
5036
5037         for (i = 0; i <= state->performance_level_count - 2; i++) {
5038                 ret = r600_calculate_at(
5039                         (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
5040                         100 * R600_AH_DFLT,
5041                         state->performance_levels[i + 1].sclk,
5042                         state->performance_levels[i].sclk,
5043                         &t_l,
5044                         &t_h);
5045
5046                 if (ret) {
5047                         t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
5048                         t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
5049                 }
5050
5051                 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
5052                 a_t |= CG_R(t_l * pi->bsp / 20000);
5053                 smc_state->levels[i].aT = cpu_to_be32(a_t);
5054
5055                 high_bsp = (i == state->performance_level_count - 2) ?
5056                         pi->pbsp : pi->bsp;
5057                 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
5058                 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
5059         }
5060
5061         return 0;
5062 }
5063
5064 static int si_disable_ulv(struct radeon_device *rdev)
5065 {
5066         struct si_power_info *si_pi = si_get_pi(rdev);
5067         struct si_ulv_param *ulv = &si_pi->ulv;
5068
5069         if (ulv->supported)
5070                 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
5071                         0 : -EINVAL;
5072
5073         return 0;
5074 }
5075
5076 static bool si_is_state_ulv_compatible(struct radeon_device *rdev,
5077                                        struct radeon_ps *radeon_state)
5078 {
5079         const struct si_power_info *si_pi = si_get_pi(rdev);
5080         const struct si_ulv_param *ulv = &si_pi->ulv;
5081         const struct ni_ps *state = ni_get_ps(radeon_state);
5082         int i;
5083
5084         if (state->performance_levels[0].mclk != ulv->pl.mclk)
5085                 return false;
5086
5087         /* XXX validate against display requirements! */
5088
5089         for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
5090                 if (rdev->clock.current_dispclk <=
5091                     rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
5092                         if (ulv->pl.vddc <
5093                             rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
5094                                 return false;
5095                 }
5096         }
5097
5098         if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0))
5099                 return false;
5100
5101         return true;
5102 }
5103
5104 static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev,
5105                                                        struct radeon_ps *radeon_new_state)
5106 {
5107         const struct si_power_info *si_pi = si_get_pi(rdev);
5108         const struct si_ulv_param *ulv = &si_pi->ulv;
5109
5110         if (ulv->supported) {
5111                 if (si_is_state_ulv_compatible(rdev, radeon_new_state))
5112                         return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
5113                                 0 : -EINVAL;
5114         }
5115         return 0;
5116 }
5117
5118 static int si_convert_power_state_to_smc(struct radeon_device *rdev,
5119                                          struct radeon_ps *radeon_state,
5120                                          SISLANDS_SMC_SWSTATE *smc_state)
5121 {
5122         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5123         struct ni_power_info *ni_pi = ni_get_pi(rdev);
5124         struct si_power_info *si_pi = si_get_pi(rdev);
5125         struct ni_ps *state = ni_get_ps(radeon_state);
5126         int i, ret;
5127         u32 threshold;
5128         u32 sclk_in_sr = 1350; /* ??? */
5129
5130         if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
5131                 return -EINVAL;
5132
5133         threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
5134
5135         if (radeon_state->vclk && radeon_state->dclk) {
5136                 eg_pi->uvd_enabled = true;
5137                 if (eg_pi->smu_uvd_hs)
5138                         smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
5139         } else {
5140                 eg_pi->uvd_enabled = false;
5141         }
5142
5143         if (state->dc_compatible)
5144                 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
5145
5146         smc_state->levelCount = 0;
5147         for (i = 0; i < state->performance_level_count; i++) {
5148                 if (eg_pi->sclk_deep_sleep) {
5149                         if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
5150                                 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5151                                         smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5152                                 else
5153                                         smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5154                         }
5155                 }
5156
5157                 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i],
5158                                                     &smc_state->levels[i]);
5159                 smc_state->levels[i].arbRefreshState =
5160                         (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
5161
5162                 if (ret)
5163                         return ret;
5164
5165                 if (ni_pi->enable_power_containment)
5166                         smc_state->levels[i].displayWatermark =
5167                                 (state->performance_levels[i].sclk < threshold) ?
5168                                 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5169                 else
5170                         smc_state->levels[i].displayWatermark = (i < 2) ?
5171                                 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5172
5173                 if (eg_pi->dynamic_ac_timing)
5174                         smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5175                 else
5176                         smc_state->levels[i].ACIndex = 0;
5177
5178                 smc_state->levelCount++;
5179         }
5180
5181         si_write_smc_soft_register(rdev,
5182                                    SI_SMC_SOFT_REGISTER_watermark_threshold,
5183                                    threshold / 512);
5184
5185         si_populate_smc_sp(rdev, radeon_state, smc_state);
5186
5187         ret = si_populate_power_containment_values(rdev, radeon_state, smc_state);
5188         if (ret)
5189                 ni_pi->enable_power_containment = false;
5190
5191         ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state);
5192         if (ret)
5193                 ni_pi->enable_sq_ramping = false;
5194
5195         return si_populate_smc_t(rdev, radeon_state, smc_state);
5196 }
5197
5198 static int si_upload_sw_state(struct radeon_device *rdev,
5199                               struct radeon_ps *radeon_new_state)
5200 {
5201         struct si_power_info *si_pi = si_get_pi(rdev);
5202         struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5203         int ret;
5204         u32 address = si_pi->state_table_start +
5205                 offsetof(SISLANDS_SMC_STATETABLE, driverState);
5206         u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +
5207                 ((new_state->performance_level_count - 1) *
5208                  sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL));
5209         SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5210
5211         memset(smc_state, 0, state_size);
5212
5213         ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state);
5214         if (ret)
5215                 return ret;
5216
5217         ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5218                                    state_size, si_pi->sram_end);
5219
5220         return ret;
5221 }
5222
5223 static int si_upload_ulv_state(struct radeon_device *rdev)
5224 {
5225         struct si_power_info *si_pi = si_get_pi(rdev);
5226         struct si_ulv_param *ulv = &si_pi->ulv;
5227         int ret = 0;
5228
5229         if (ulv->supported && ulv->pl.vddc) {
5230                 u32 address = si_pi->state_table_start +
5231                         offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5232                 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;
5233                 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);
5234
5235                 memset(smc_state, 0, state_size);
5236
5237                 ret = si_populate_ulv_state(rdev, smc_state);
5238                 if (!ret)
5239                         ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5240                                                    state_size, si_pi->sram_end);
5241         }
5242
5243         return ret;
5244 }
5245
5246 static int si_upload_smc_data(struct radeon_device *rdev)
5247 {
5248         struct radeon_crtc *radeon_crtc = NULL;
5249         int i;
5250
5251         if (rdev->pm.dpm.new_active_crtc_count == 0)
5252                 return 0;
5253
5254         for (i = 0; i < rdev->num_crtc; i++) {
5255                 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) {
5256                         radeon_crtc = rdev->mode_info.crtcs[i];
5257                         break;
5258                 }
5259         }
5260
5261         if (radeon_crtc == NULL)
5262                 return 0;
5263
5264         if (radeon_crtc->line_time <= 0)
5265                 return 0;
5266
5267         if (si_write_smc_soft_register(rdev,
5268                                        SI_SMC_SOFT_REGISTER_crtc_index,
5269                                        radeon_crtc->crtc_id) != PPSMC_Result_OK)
5270                 return 0;
5271
5272         if (si_write_smc_soft_register(rdev,
5273                                        SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5274                                        radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK)
5275                 return 0;
5276
5277         if (si_write_smc_soft_register(rdev,
5278                                        SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5279                                        radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK)
5280                 return 0;
5281
5282         return 0;
5283 }
5284
5285 static int si_set_mc_special_registers(struct radeon_device *rdev,
5286                                        struct si_mc_reg_table *table)
5287 {
5288         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5289         u8 i, j, k;
5290         u32 temp_reg;
5291
5292         for (i = 0, j = table->last; i < table->last; i++) {
5293                 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5294                         return -EINVAL;
5295                 switch (table->mc_reg_address[i].s1 << 2) {
5296                 case MC_SEQ_MISC1:
5297                         temp_reg = RREG32(MC_PMG_CMD_EMRS);
5298                         table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
5299                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5300                         for (k = 0; k < table->num_entries; k++)
5301                                 table->mc_reg_table_entry[k].mc_data[j] =
5302                                         ((temp_reg & 0xffff0000)) |
5303                                         ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5304                         j++;
5305                         if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5306                                 return -EINVAL;
5307
5308                         temp_reg = RREG32(MC_PMG_CMD_MRS);
5309                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
5310                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5311                         for (k = 0; k < table->num_entries; k++) {
5312                                 table->mc_reg_table_entry[k].mc_data[j] =
5313                                         (temp_reg & 0xffff0000) |
5314                                         (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5315                                 if (!pi->mem_gddr5)
5316                                         table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5317                         }
5318                         j++;
5319                         if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5320                                 return -EINVAL;
5321
5322                         if (!pi->mem_gddr5) {
5323                                 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
5324                                 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
5325                                 for (k = 0; k < table->num_entries; k++)
5326                                         table->mc_reg_table_entry[k].mc_data[j] =
5327                                                 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5328                                 j++;
5329                                 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5330                                         return -EINVAL;
5331                         }
5332                         break;
5333                 case MC_SEQ_RESERVE_M:
5334                         temp_reg = RREG32(MC_PMG_CMD_MRS1);
5335                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
5336                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5337                         for(k = 0; k < table->num_entries; k++)
5338                                 table->mc_reg_table_entry[k].mc_data[j] =
5339                                         (temp_reg & 0xffff0000) |
5340                                         (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5341                         j++;
5342                         if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5343                                 return -EINVAL;
5344                         break;
5345                 default:
5346                         break;
5347                 }
5348         }
5349
5350         table->last = j;
5351
5352         return 0;
5353 }
5354
5355 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5356 {
5357         bool result = true;
5358
5359         switch (in_reg) {
5360         case  MC_SEQ_RAS_TIMING >> 2:
5361                 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
5362                 break;
5363         case MC_SEQ_CAS_TIMING >> 2:
5364                 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
5365                 break;
5366         case MC_SEQ_MISC_TIMING >> 2:
5367                 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
5368                 break;
5369         case MC_SEQ_MISC_TIMING2 >> 2:
5370                 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
5371                 break;
5372         case MC_SEQ_RD_CTL_D0 >> 2:
5373                 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
5374                 break;
5375         case MC_SEQ_RD_CTL_D1 >> 2:
5376                 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
5377                 break;
5378         case MC_SEQ_WR_CTL_D0 >> 2:
5379                 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
5380                 break;
5381         case MC_SEQ_WR_CTL_D1 >> 2:
5382                 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
5383                 break;
5384         case MC_PMG_CMD_EMRS >> 2:
5385                 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5386                 break;
5387         case MC_PMG_CMD_MRS >> 2:
5388                 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5389                 break;
5390         case MC_PMG_CMD_MRS1 >> 2:
5391                 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5392                 break;
5393         case MC_SEQ_PMG_TIMING >> 2:
5394                 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2;
5395                 break;
5396         case MC_PMG_CMD_MRS2 >> 2:
5397                 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
5398                 break;
5399         case MC_SEQ_WR_CTL_2 >> 2:
5400                 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2;
5401                 break;
5402         default:
5403                 result = false;
5404                 break;
5405         }
5406
5407         return result;
5408 }
5409
5410 static void si_set_valid_flag(struct si_mc_reg_table *table)
5411 {
5412         u8 i, j;
5413
5414         for (i = 0; i < table->last; i++) {
5415                 for (j = 1; j < table->num_entries; j++) {
5416                         if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
5417                                 table->valid_flag |= 1 << i;
5418                                 break;
5419                         }
5420                 }
5421         }
5422 }
5423
5424 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
5425 {
5426         u32 i;
5427         u16 address;
5428
5429         for (i = 0; i < table->last; i++)
5430                 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
5431                         address : table->mc_reg_address[i].s1;
5432
5433 }
5434
5435 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
5436                                       struct si_mc_reg_table *si_table)
5437 {
5438         u8 i, j;
5439
5440         if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5441                 return -EINVAL;
5442         if (table->num_entries > MAX_AC_TIMING_ENTRIES)
5443                 return -EINVAL;
5444
5445         for (i = 0; i < table->last; i++)
5446                 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
5447         si_table->last = table->last;
5448
5449         for (i = 0; i < table->num_entries; i++) {
5450                 si_table->mc_reg_table_entry[i].mclk_max =
5451                         table->mc_reg_table_entry[i].mclk_max;
5452                 for (j = 0; j < table->last; j++) {
5453                         si_table->mc_reg_table_entry[i].mc_data[j] =
5454                                 table->mc_reg_table_entry[i].mc_data[j];
5455                 }
5456         }
5457         si_table->num_entries = table->num_entries;
5458
5459         return 0;
5460 }
5461
5462 static int si_initialize_mc_reg_table(struct radeon_device *rdev)
5463 {
5464         struct si_power_info *si_pi = si_get_pi(rdev);
5465         struct atom_mc_reg_table *table;
5466         struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
5467         u8 module_index = rv770_get_memory_module_index(rdev);
5468         int ret;
5469
5470         table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
5471         if (!table)
5472                 return -ENOMEM;
5473
5474         WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
5475         WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
5476         WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
5477         WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
5478         WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
5479         WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
5480         WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
5481         WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
5482         WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
5483         WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
5484         WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
5485         WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
5486         WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
5487         WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
5488
5489         ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
5490         if (ret)
5491                 goto init_mc_done;
5492
5493         ret = si_copy_vbios_mc_reg_table(table, si_table);
5494         if (ret)
5495                 goto init_mc_done;
5496
5497         si_set_s0_mc_reg_index(si_table);
5498
5499         ret = si_set_mc_special_registers(rdev, si_table);
5500         if (ret)
5501                 goto init_mc_done;
5502
5503         si_set_valid_flag(si_table);
5504
5505 init_mc_done:
5506         kfree(table);
5507
5508         return ret;
5509
5510 }
5511
5512 static void si_populate_mc_reg_addresses(struct radeon_device *rdev,
5513                                          SMC_SIslands_MCRegisters *mc_reg_table)
5514 {
5515         struct si_power_info *si_pi = si_get_pi(rdev);
5516         u32 i, j;
5517
5518         for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
5519                 if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
5520                         if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5521                                 break;
5522                         mc_reg_table->address[i].s0 =
5523                                 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
5524                         mc_reg_table->address[i].s1 =
5525                                 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
5526                         i++;
5527                 }
5528         }
5529         mc_reg_table->last = (u8)i;
5530 }
5531
5532 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
5533                                     SMC_SIslands_MCRegisterSet *data,
5534                                     u32 num_entries, u32 valid_flag)
5535 {
5536         u32 i, j;
5537
5538         for(i = 0, j = 0; j < num_entries; j++) {
5539                 if (valid_flag & (1 << j)) {
5540                         data->value[i] = cpu_to_be32(entry->mc_data[j]);
5541                         i++;
5542                 }
5543         }
5544 }
5545
5546 static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
5547                                                  struct rv7xx_pl *pl,
5548                                                  SMC_SIslands_MCRegisterSet *mc_reg_table_data)
5549 {
5550         struct si_power_info *si_pi = si_get_pi(rdev);
5551         u32 i = 0;
5552
5553         for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
5554                 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
5555                         break;
5556         }
5557
5558         if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
5559                 --i;
5560
5561         si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
5562                                 mc_reg_table_data, si_pi->mc_reg_table.last,
5563                                 si_pi->mc_reg_table.valid_flag);
5564 }
5565
5566 static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
5567                                            struct radeon_ps *radeon_state,
5568                                            SMC_SIslands_MCRegisters *mc_reg_table)
5569 {
5570         struct ni_ps *state = ni_get_ps(radeon_state);
5571         int i;
5572
5573         for (i = 0; i < state->performance_level_count; i++) {
5574                 si_convert_mc_reg_table_entry_to_smc(rdev,
5575                                                      &state->performance_levels[i],
5576                                                      &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
5577         }
5578 }
5579
5580 static int si_populate_mc_reg_table(struct radeon_device *rdev,
5581                                     struct radeon_ps *radeon_boot_state)
5582 {
5583         struct ni_ps *boot_state = ni_get_ps(radeon_boot_state);
5584         struct si_power_info *si_pi = si_get_pi(rdev);
5585         struct si_ulv_param *ulv = &si_pi->ulv;
5586         SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5587
5588         memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5589
5590         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1);
5591
5592         si_populate_mc_reg_addresses(rdev, smc_mc_reg_table);
5593
5594         si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0],
5595                                              &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
5596
5597         si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5598                                 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
5599                                 si_pi->mc_reg_table.last,
5600                                 si_pi->mc_reg_table.valid_flag);
5601
5602         if (ulv->supported && ulv->pl.vddc != 0)
5603                 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl,
5604                                                      &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
5605         else
5606                 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5607                                         &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
5608                                         si_pi->mc_reg_table.last,
5609                                         si_pi->mc_reg_table.valid_flag);
5610
5611         si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table);
5612
5613         return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start,
5614                                     (u8 *)smc_mc_reg_table,
5615                                     sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
5616 }
5617
5618 static int si_upload_mc_reg_table(struct radeon_device *rdev,
5619                                   struct radeon_ps *radeon_new_state)
5620 {
5621         struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5622         struct si_power_info *si_pi = si_get_pi(rdev);
5623         u32 address = si_pi->mc_reg_table_start +
5624                 offsetof(SMC_SIslands_MCRegisters,
5625                          data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
5626         SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5627
5628         memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5629
5630         si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table);
5631
5632
5633         return si_copy_bytes_to_smc(rdev, address,
5634                                     (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
5635                                     sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
5636                                     si_pi->sram_end);
5637
5638 }
5639
5640 static void si_enable_voltage_control(struct radeon_device *rdev, bool enable)
5641 {
5642         if (enable)
5643                 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
5644         else
5645                 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
5646 }
5647
5648 static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev,
5649                                                       struct radeon_ps *radeon_state)
5650 {
5651         struct ni_ps *state = ni_get_ps(radeon_state);
5652         int i;
5653         u16 pcie_speed, max_speed = 0;
5654
5655         for (i = 0; i < state->performance_level_count; i++) {
5656                 pcie_speed = state->performance_levels[i].pcie_gen;
5657                 if (max_speed < pcie_speed)
5658                         max_speed = pcie_speed;
5659         }
5660         return max_speed;
5661 }
5662
5663 static u16 si_get_current_pcie_speed(struct radeon_device *rdev)
5664 {
5665         u32 speed_cntl;
5666
5667         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
5668         speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
5669
5670         return (u16)speed_cntl;
5671 }
5672
5673 static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev,
5674                                                              struct radeon_ps *radeon_new_state,
5675                                                              struct radeon_ps *radeon_current_state)
5676 {
5677         struct si_power_info *si_pi = si_get_pi(rdev);
5678         enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5679         enum radeon_pcie_gen current_link_speed;
5680
5681         if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)
5682                 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state);
5683         else
5684                 current_link_speed = si_pi->force_pcie_gen;
5685
5686         si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
5687         si_pi->pspp_notify_required = false;
5688         if (target_link_speed > current_link_speed) {
5689                 switch (target_link_speed) {
5690 #if defined(CONFIG_ACPI)
5691                 case RADEON_PCIE_GEN3:
5692                         if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
5693                                 break;
5694                         si_pi->force_pcie_gen = RADEON_PCIE_GEN2;
5695                         if (current_link_speed == RADEON_PCIE_GEN2)
5696                                 break;
5697                 case RADEON_PCIE_GEN2:
5698                         if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
5699                                 break;
5700 #endif
5701                 default:
5702                         si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev);
5703                         break;
5704                 }
5705         } else {
5706                 if (target_link_speed < current_link_speed)
5707                         si_pi->pspp_notify_required = true;
5708         }
5709 }
5710
5711 static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
5712                                                            struct radeon_ps *radeon_new_state,
5713                                                            struct radeon_ps *radeon_current_state)
5714 {
5715         struct si_power_info *si_pi = si_get_pi(rdev);
5716         enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5717         u8 request;
5718
5719         if (si_pi->pspp_notify_required) {
5720                 if (target_link_speed == RADEON_PCIE_GEN3)
5721                         request = PCIE_PERF_REQ_PECI_GEN3;
5722                 else if (target_link_speed == RADEON_PCIE_GEN2)
5723                         request = PCIE_PERF_REQ_PECI_GEN2;
5724                 else
5725                         request = PCIE_PERF_REQ_PECI_GEN1;
5726
5727                 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
5728                     (si_get_current_pcie_speed(rdev) > 0))
5729                         return;
5730
5731 #if defined(CONFIG_ACPI)
5732                 radeon_acpi_pcie_performance_request(rdev, request, false);
5733 #endif
5734         }
5735 }
5736
5737 #if 0
5738 static int si_ds_request(struct radeon_device *rdev,
5739                          bool ds_status_on, u32 count_write)
5740 {
5741         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5742
5743         if (eg_pi->sclk_deep_sleep) {
5744                 if (ds_status_on)
5745                         return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
5746                                 PPSMC_Result_OK) ?
5747                                 0 : -EINVAL;
5748                 else
5749                         return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
5750                                 PPSMC_Result_OK) ? 0 : -EINVAL;
5751         }
5752         return 0;
5753 }
5754 #endif
5755
5756 static void si_set_max_cu_value(struct radeon_device *rdev)
5757 {
5758         struct si_power_info *si_pi = si_get_pi(rdev);
5759
5760         if (rdev->family == CHIP_VERDE) {
5761                 switch (rdev->pdev->device) {
5762                 case 0x6820:
5763                 case 0x6825:
5764                 case 0x6821:
5765                 case 0x6823:
5766                 case 0x6827:
5767                         si_pi->max_cu = 10;
5768                         break;
5769                 case 0x682D:
5770                 case 0x6824:
5771                 case 0x682F:
5772                 case 0x6826:
5773                         si_pi->max_cu = 8;
5774                         break;
5775                 case 0x6828:
5776                 case 0x6830:
5777                 case 0x6831:
5778                 case 0x6838:
5779                 case 0x6839:
5780                 case 0x683D:
5781                         si_pi->max_cu = 10;
5782                         break;
5783                 case 0x683B:
5784                 case 0x683F:
5785                 case 0x6829:
5786                         si_pi->max_cu = 8;
5787                         break;
5788                 default:
5789                         si_pi->max_cu = 0;
5790                         break;
5791                 }
5792         } else {
5793                 si_pi->max_cu = 0;
5794         }
5795 }
5796
5797 static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev,
5798                                                              struct radeon_clock_voltage_dependency_table *table)
5799 {
5800         u32 i;
5801         int j;
5802         u16 leakage_voltage;
5803
5804         if (table) {
5805                 for (i = 0; i < table->count; i++) {
5806                         switch (si_get_leakage_voltage_from_leakage_index(rdev,
5807                                                                           table->entries[i].v,
5808                                                                           &leakage_voltage)) {
5809                         case 0:
5810                                 table->entries[i].v = leakage_voltage;
5811                                 break;
5812                         case -EAGAIN:
5813                                 return -EINVAL;
5814                         case -EINVAL:
5815                         default:
5816                                 break;
5817                         }
5818                 }
5819
5820                 for (j = (table->count - 2); j >= 0; j--) {
5821                         table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
5822                                 table->entries[j].v : table->entries[j + 1].v;
5823                 }
5824         }
5825         return 0;
5826 }
5827
5828 static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev)
5829 {
5830         int ret = 0;
5831
5832         ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5833                                                                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
5834         ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5835                                                                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
5836         ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5837                                                                 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
5838         return ret;
5839 }
5840
5841 static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev,
5842                                           struct radeon_ps *radeon_new_state,
5843                                           struct radeon_ps *radeon_current_state)
5844 {
5845         u32 lane_width;
5846         u32 new_lane_width =
5847                 (radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
5848         u32 current_lane_width =
5849                 (radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
5850
5851         if (new_lane_width != current_lane_width) {
5852                 radeon_set_pcie_lanes(rdev, new_lane_width);
5853                 lane_width = radeon_get_pcie_lanes(rdev);
5854                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5855         }
5856 }
5857
5858 void si_dpm_setup_asic(struct radeon_device *rdev)
5859 {
5860         int r;
5861
5862         r = si_mc_load_microcode(rdev);
5863         if (r)
5864                 DRM_ERROR("Failed to load MC firmware!\n");
5865         rv770_get_memory_type(rdev);
5866         si_read_clock_registers(rdev);
5867         si_enable_acpi_power_management(rdev);
5868 }
5869
5870 static int si_thermal_enable_alert(struct radeon_device *rdev,
5871                                    bool enable)
5872 {
5873         u32 thermal_int = RREG32(CG_THERMAL_INT);
5874
5875         if (enable) {
5876                 PPSMC_Result result;
5877
5878                 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
5879                 WREG32(CG_THERMAL_INT, thermal_int);
5880                 rdev->irq.dpm_thermal = false;
5881                 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
5882                 if (result != PPSMC_Result_OK) {
5883                         DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
5884                         return -EINVAL;
5885                 }
5886         } else {
5887                 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
5888                 WREG32(CG_THERMAL_INT, thermal_int);
5889                 rdev->irq.dpm_thermal = true;
5890         }
5891
5892         return 0;
5893 }
5894
5895 static int si_thermal_set_temperature_range(struct radeon_device *rdev,
5896                                             int min_temp, int max_temp)
5897 {
5898         int low_temp = 0 * 1000;
5899         int high_temp = 255 * 1000;
5900
5901         if (low_temp < min_temp)
5902                 low_temp = min_temp;
5903         if (high_temp > max_temp)
5904                 high_temp = max_temp;
5905         if (high_temp < low_temp) {
5906                 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
5907                 return -EINVAL;
5908         }
5909
5910         WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
5911         WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
5912         WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
5913
5914         rdev->pm.dpm.thermal.min_temp = low_temp;
5915         rdev->pm.dpm.thermal.max_temp = high_temp;
5916
5917         return 0;
5918 }
5919
5920 static void si_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode)
5921 {
5922         struct si_power_info *si_pi = si_get_pi(rdev);
5923         u32 tmp;
5924
5925         if (si_pi->fan_ctrl_is_in_default_mode) {
5926                 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
5927                 si_pi->fan_ctrl_default_mode = tmp;
5928                 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
5929                 si_pi->t_min = tmp;
5930                 si_pi->fan_ctrl_is_in_default_mode = false;
5931         }
5932
5933         tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
5934         tmp |= TMIN(0);
5935         WREG32(CG_FDO_CTRL2, tmp);
5936
5937         tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
5938         tmp |= FDO_PWM_MODE(mode);
5939         WREG32(CG_FDO_CTRL2, tmp);
5940 }
5941
5942 static int si_thermal_setup_fan_table(struct radeon_device *rdev)
5943 {
5944         struct si_power_info *si_pi = si_get_pi(rdev);
5945         PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE };
5946         u32 duty100;
5947         u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
5948         u16 fdo_min, slope1, slope2;
5949         u32 reference_clock, tmp;
5950         int ret;
5951         u64 tmp64;
5952
5953         if (!si_pi->fan_table_start) {
5954                 rdev->pm.dpm.fan.ucode_fan_control = false;
5955                 return 0;
5956         }
5957
5958         duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
5959
5960         if (duty100 == 0) {
5961                 rdev->pm.dpm.fan.ucode_fan_control = false;
5962                 return 0;
5963         }
5964
5965         tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100;
5966         do_div(tmp64, 10000);
5967         fdo_min = (u16)tmp64;
5968
5969         t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min;
5970         t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med;
5971
5972         pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min;
5973         pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med;
5974
5975         slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
5976         slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
5977
5978         fan_table.slope1 = cpu_to_be16(slope1);
5979         fan_table.slope2 = cpu_to_be16(slope2);
5980
5981         fan_table.fdo_min = cpu_to_be16(fdo_min);
5982
5983         fan_table.hys_down = cpu_to_be16(rdev->pm.dpm.fan.t_hyst);
5984
5985         fan_table.hys_up = cpu_to_be16(1);
5986
5987         fan_table.hys_slope = cpu_to_be16(1);
5988
5989         fan_table.temp_resp_lim = cpu_to_be16(5);
5990
5991         reference_clock = radeon_get_xclk(rdev);
5992
5993         fan_table.refresh_period = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay *
5994                                                 reference_clock) / 1600);
5995
5996         fan_table.fdo_max = cpu_to_be16((u16)duty100);
5997
5998         tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
5999         fan_table.temp_src = (uint8_t)tmp;
6000
6001         ret = si_copy_bytes_to_smc(rdev,
6002                                    si_pi->fan_table_start,
6003                                    (u8 *)(&fan_table),
6004                                    sizeof(fan_table),
6005                                    si_pi->sram_end);
6006
6007         if (ret) {
6008                 DRM_ERROR("Failed to load fan table to the SMC.");
6009                 rdev->pm.dpm.fan.ucode_fan_control = false;
6010         }
6011
6012         return 0;
6013 }
6014
6015 static int si_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev)
6016 {
6017         PPSMC_Result ret;
6018
6019         ret = si_send_msg_to_smc(rdev, PPSMC_StartFanControl);
6020         if (ret == PPSMC_Result_OK)
6021                 return 0;
6022         else
6023                 return -EINVAL;
6024 }
6025
6026 static int si_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev)
6027 {
6028         PPSMC_Result ret;
6029
6030         ret = si_send_msg_to_smc(rdev, PPSMC_StopFanControl);
6031         if (ret == PPSMC_Result_OK)
6032                 return 0;
6033         else
6034                 return -EINVAL;
6035 }
6036
6037 #if 0
6038 static int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev,
6039                                              u32 *speed)
6040 {
6041         u32 duty, duty100;
6042         u64 tmp64;
6043
6044         if (rdev->pm.no_fan)
6045                 return -ENOENT;
6046
6047         duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6048         duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;
6049
6050         if (duty100 == 0)
6051                 return -EINVAL;
6052
6053         tmp64 = (u64)duty * 100;
6054         do_div(tmp64, duty100);
6055         *speed = (u32)tmp64;
6056
6057         if (*speed > 100)
6058                 *speed = 100;
6059
6060         return 0;
6061 }
6062
6063 static int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev,
6064                                              u32 speed)
6065 {
6066         u32 tmp;
6067         u32 duty, duty100;
6068         u64 tmp64;
6069
6070         if (rdev->pm.no_fan)
6071                 return -ENOENT;
6072
6073         if (speed > 100)
6074                 return -EINVAL;
6075
6076         if (rdev->pm.dpm.fan.ucode_fan_control)
6077                 si_fan_ctrl_stop_smc_fan_control(rdev);
6078
6079         duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6080
6081         if (duty100 == 0)
6082                 return -EINVAL;
6083
6084         tmp64 = (u64)speed * duty100;
6085         do_div(tmp64, 100);
6086         duty = (u32)tmp64;
6087
6088         tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
6089         tmp |= FDO_STATIC_DUTY(duty);
6090         WREG32(CG_FDO_CTRL0, tmp);
6091
6092         si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC);
6093
6094         return 0;
6095 }
6096
6097 static int si_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev,
6098                                          u32 *speed)
6099 {
6100         u32 tach_period;
6101         u32 xclk = radeon_get_xclk(rdev);
6102
6103         if (rdev->pm.no_fan)
6104                 return -ENOENT;
6105
6106         if (rdev->pm.fan_pulses_per_revolution == 0)
6107                 return -ENOENT;
6108
6109         tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
6110         if (tach_period == 0)
6111                 return -ENOENT;
6112
6113         *speed = 60 * xclk * 10000 / tach_period;
6114
6115         return 0;
6116 }
6117
6118 static int si_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev,
6119                                          u32 speed)
6120 {
6121         u32 tach_period, tmp;
6122         u32 xclk = radeon_get_xclk(rdev);
6123
6124         if (rdev->pm.no_fan)
6125                 return -ENOENT;
6126
6127         if (rdev->pm.fan_pulses_per_revolution == 0)
6128                 return -ENOENT;
6129
6130         if ((speed < rdev->pm.fan_min_rpm) ||
6131             (speed > rdev->pm.fan_max_rpm))
6132                 return -EINVAL;
6133
6134         if (rdev->pm.dpm.fan.ucode_fan_control)
6135                 si_fan_ctrl_stop_smc_fan_control(rdev);
6136
6137         tach_period = 60 * xclk * 10000 / (8 * speed);
6138         tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
6139         tmp |= TARGET_PERIOD(tach_period);
6140         WREG32(CG_TACH_CTRL, tmp);
6141
6142         si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM);
6143
6144         return 0;
6145 }
6146 #endif
6147
6148 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev)
6149 {
6150         struct si_power_info *si_pi = si_get_pi(rdev);
6151         u32 tmp;
6152
6153         if (!si_pi->fan_ctrl_is_in_default_mode) {
6154                 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6155                 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode);
6156                 WREG32(CG_FDO_CTRL2, tmp);
6157
6158                 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6159                 tmp |= TMIN(si_pi->t_min);
6160                 WREG32(CG_FDO_CTRL2, tmp);
6161                 si_pi->fan_ctrl_is_in_default_mode = true;
6162         }
6163 }
6164
6165 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev)
6166 {
6167         if (rdev->pm.dpm.fan.ucode_fan_control) {
6168                 si_fan_ctrl_start_smc_fan_control(rdev);
6169                 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC);
6170         }
6171 }
6172
6173 static void si_thermal_initialize(struct radeon_device *rdev)
6174 {
6175         u32 tmp;
6176
6177         if (rdev->pm.fan_pulses_per_revolution) {
6178                 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
6179                 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1);
6180                 WREG32(CG_TACH_CTRL, tmp);
6181         }
6182
6183         tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
6184         tmp |= TACH_PWM_RESP_RATE(0x28);
6185         WREG32(CG_FDO_CTRL2, tmp);
6186 }
6187
6188 static int si_thermal_start_thermal_controller(struct radeon_device *rdev)
6189 {
6190         int ret;
6191
6192         si_thermal_initialize(rdev);
6193         ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6194         if (ret)
6195                 return ret;
6196         ret = si_thermal_enable_alert(rdev, true);
6197         if (ret)
6198                 return ret;
6199         if (rdev->pm.dpm.fan.ucode_fan_control) {
6200                 ret = si_halt_smc(rdev);
6201                 if (ret)
6202                         return ret;
6203                 ret = si_thermal_setup_fan_table(rdev);
6204                 if (ret)
6205                         return ret;
6206                 ret = si_resume_smc(rdev);
6207                 if (ret)
6208                         return ret;
6209                 si_thermal_start_smc_fan_control(rdev);
6210         }
6211
6212         return 0;
6213 }
6214
6215 static void si_thermal_stop_thermal_controller(struct radeon_device *rdev)
6216 {
6217         if (!rdev->pm.no_fan) {
6218                 si_fan_ctrl_set_default_mode(rdev);
6219                 si_fan_ctrl_stop_smc_fan_control(rdev);
6220         }
6221 }
6222
6223 int si_dpm_enable(struct radeon_device *rdev)
6224 {
6225         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6226         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6227         struct si_power_info *si_pi = si_get_pi(rdev);
6228         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
6229         int ret;
6230
6231         if (si_is_smc_running(rdev))
6232                 return -EINVAL;
6233         if (pi->voltage_control || si_pi->voltage_control_svi2)
6234                 si_enable_voltage_control(rdev, true);
6235         if (pi->mvdd_control)
6236                 si_get_mvdd_configuration(rdev);
6237         if (pi->voltage_control || si_pi->voltage_control_svi2) {
6238                 ret = si_construct_voltage_tables(rdev);
6239                 if (ret) {
6240                         DRM_ERROR("si_construct_voltage_tables failed\n");
6241                         return ret;
6242                 }
6243         }
6244         if (eg_pi->dynamic_ac_timing) {
6245                 ret = si_initialize_mc_reg_table(rdev);
6246                 if (ret)
6247                         eg_pi->dynamic_ac_timing = false;
6248         }
6249         if (pi->dynamic_ss)
6250                 si_enable_spread_spectrum(rdev, true);
6251         if (pi->thermal_protection)
6252                 si_enable_thermal_protection(rdev, true);
6253         si_setup_bsp(rdev);
6254         si_program_git(rdev);
6255         si_program_tp(rdev);
6256         si_program_tpp(rdev);
6257         si_program_sstp(rdev);
6258         si_enable_display_gap(rdev);
6259         si_program_vc(rdev);
6260         ret = si_upload_firmware(rdev);
6261         if (ret) {
6262                 DRM_ERROR("si_upload_firmware failed\n");
6263                 return ret;
6264         }
6265         ret = si_process_firmware_header(rdev);
6266         if (ret) {
6267                 DRM_ERROR("si_process_firmware_header failed\n");
6268                 return ret;
6269         }
6270         ret = si_initial_switch_from_arb_f0_to_f1(rdev);
6271         if (ret) {
6272                 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
6273                 return ret;
6274         }
6275         ret = si_init_smc_table(rdev);
6276         if (ret) {
6277                 DRM_ERROR("si_init_smc_table failed\n");
6278                 return ret;
6279         }
6280         ret = si_init_smc_spll_table(rdev);
6281         if (ret) {
6282                 DRM_ERROR("si_init_smc_spll_table failed\n");
6283                 return ret;
6284         }
6285         ret = si_init_arb_table_index(rdev);
6286         if (ret) {
6287                 DRM_ERROR("si_init_arb_table_index failed\n");
6288                 return ret;
6289         }
6290         if (eg_pi->dynamic_ac_timing) {
6291                 ret = si_populate_mc_reg_table(rdev, boot_ps);
6292                 if (ret) {
6293                         DRM_ERROR("si_populate_mc_reg_table failed\n");
6294                         return ret;
6295                 }
6296         }
6297         ret = si_initialize_smc_cac_tables(rdev);
6298         if (ret) {
6299                 DRM_ERROR("si_initialize_smc_cac_tables failed\n");
6300                 return ret;
6301         }
6302         ret = si_initialize_hardware_cac_manager(rdev);
6303         if (ret) {
6304                 DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
6305                 return ret;
6306         }
6307         ret = si_initialize_smc_dte_tables(rdev);
6308         if (ret) {
6309                 DRM_ERROR("si_initialize_smc_dte_tables failed\n");
6310                 return ret;
6311         }
6312         ret = si_populate_smc_tdp_limits(rdev, boot_ps);
6313         if (ret) {
6314                 DRM_ERROR("si_populate_smc_tdp_limits failed\n");
6315                 return ret;
6316         }
6317         ret = si_populate_smc_tdp_limits_2(rdev, boot_ps);
6318         if (ret) {
6319                 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
6320                 return ret;
6321         }
6322         si_program_response_times(rdev);
6323         si_program_ds_registers(rdev);
6324         si_dpm_start_smc(rdev);
6325         ret = si_notify_smc_display_change(rdev, false);
6326         if (ret) {
6327                 DRM_ERROR("si_notify_smc_display_change failed\n");
6328                 return ret;
6329         }
6330         si_enable_sclk_control(rdev, true);
6331         si_start_dpm(rdev);
6332
6333         si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
6334
6335         si_thermal_start_thermal_controller(rdev);
6336
6337         ni_update_current_ps(rdev, boot_ps);
6338
6339         return 0;
6340 }
6341
6342 static int si_set_temperature_range(struct radeon_device *rdev)
6343 {
6344         int ret;
6345
6346         ret = si_thermal_enable_alert(rdev, false);
6347         if (ret)
6348                 return ret;
6349         ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6350         if (ret)
6351                 return ret;
6352         ret = si_thermal_enable_alert(rdev, true);
6353         if (ret)
6354                 return ret;
6355
6356         return ret;
6357 }
6358
6359 int si_dpm_late_enable(struct radeon_device *rdev)
6360 {
6361         int ret;
6362
6363         ret = si_set_temperature_range(rdev);
6364         if (ret)
6365                 return ret;
6366
6367         return ret;
6368 }
6369
6370 void si_dpm_disable(struct radeon_device *rdev)
6371 {
6372         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6373         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
6374
6375         if (!si_is_smc_running(rdev))
6376                 return;
6377         si_thermal_stop_thermal_controller(rdev);
6378         si_disable_ulv(rdev);
6379         si_clear_vc(rdev);
6380         if (pi->thermal_protection)
6381                 si_enable_thermal_protection(rdev, false);
6382         si_enable_power_containment(rdev, boot_ps, false);
6383         si_enable_smc_cac(rdev, boot_ps, false);
6384         si_enable_spread_spectrum(rdev, false);
6385         si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
6386         si_stop_dpm(rdev);
6387         si_reset_to_default(rdev);
6388         si_dpm_stop_smc(rdev);
6389         si_force_switch_to_arb_f0(rdev);
6390
6391         ni_update_current_ps(rdev, boot_ps);
6392 }
6393
6394 int si_dpm_pre_set_power_state(struct radeon_device *rdev)
6395 {
6396         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6397         struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
6398         struct radeon_ps *new_ps = &requested_ps;
6399
6400         ni_update_requested_ps(rdev, new_ps);
6401
6402         si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps);
6403
6404         return 0;
6405 }
6406
6407 static int si_power_control_set_level(struct radeon_device *rdev)
6408 {
6409         struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
6410         int ret;
6411
6412         ret = si_restrict_performance_levels_before_switch(rdev);
6413         if (ret)
6414                 return ret;
6415         ret = si_halt_smc(rdev);
6416         if (ret)
6417                 return ret;
6418         ret = si_populate_smc_tdp_limits(rdev, new_ps);
6419         if (ret)
6420                 return ret;
6421         ret = si_populate_smc_tdp_limits_2(rdev, new_ps);
6422         if (ret)
6423                 return ret;
6424         ret = si_resume_smc(rdev);
6425         if (ret)
6426                 return ret;
6427         ret = si_set_sw_state(rdev);
6428         if (ret)
6429                 return ret;
6430         return 0;
6431 }
6432
6433 int si_dpm_set_power_state(struct radeon_device *rdev)
6434 {
6435         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6436         struct radeon_ps *new_ps = &eg_pi->requested_rps;
6437         struct radeon_ps *old_ps = &eg_pi->current_rps;
6438         int ret;
6439
6440         ret = si_disable_ulv(rdev);
6441         if (ret) {
6442                 DRM_ERROR("si_disable_ulv failed\n");
6443                 return ret;
6444         }
6445         ret = si_restrict_performance_levels_before_switch(rdev);
6446         if (ret) {
6447                 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
6448                 return ret;
6449         }
6450         if (eg_pi->pcie_performance_request)
6451                 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
6452         ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
6453         ret = si_enable_power_containment(rdev, new_ps, false);
6454         if (ret) {
6455                 DRM_ERROR("si_enable_power_containment failed\n");
6456                 return ret;
6457         }
6458         ret = si_enable_smc_cac(rdev, new_ps, false);
6459         if (ret) {
6460                 DRM_ERROR("si_enable_smc_cac failed\n");
6461                 return ret;
6462         }
6463         ret = si_halt_smc(rdev);
6464         if (ret) {
6465                 DRM_ERROR("si_halt_smc failed\n");
6466                 return ret;
6467         }
6468         ret = si_upload_sw_state(rdev, new_ps);
6469         if (ret) {
6470                 DRM_ERROR("si_upload_sw_state failed\n");
6471                 return ret;
6472         }
6473         ret = si_upload_smc_data(rdev);
6474         if (ret) {
6475                 DRM_ERROR("si_upload_smc_data failed\n");
6476                 return ret;
6477         }
6478         ret = si_upload_ulv_state(rdev);
6479         if (ret) {
6480                 DRM_ERROR("si_upload_ulv_state failed\n");
6481                 return ret;
6482         }
6483         if (eg_pi->dynamic_ac_timing) {
6484                 ret = si_upload_mc_reg_table(rdev, new_ps);
6485                 if (ret) {
6486                         DRM_ERROR("si_upload_mc_reg_table failed\n");
6487                         return ret;
6488                 }
6489         }
6490         ret = si_program_memory_timing_parameters(rdev, new_ps);
6491         if (ret) {
6492                 DRM_ERROR("si_program_memory_timing_parameters failed\n");
6493                 return ret;
6494         }
6495         si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps);
6496
6497         ret = si_resume_smc(rdev);
6498         if (ret) {
6499                 DRM_ERROR("si_resume_smc failed\n");
6500                 return ret;
6501         }
6502         ret = si_set_sw_state(rdev);
6503         if (ret) {
6504                 DRM_ERROR("si_set_sw_state failed\n");
6505                 return ret;
6506         }
6507         ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
6508         if (eg_pi->pcie_performance_request)
6509                 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
6510         ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps);
6511         if (ret) {
6512                 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
6513                 return ret;
6514         }
6515         ret = si_enable_smc_cac(rdev, new_ps, true);
6516         if (ret) {
6517                 DRM_ERROR("si_enable_smc_cac failed\n");
6518                 return ret;
6519         }
6520         ret = si_enable_power_containment(rdev, new_ps, true);
6521         if (ret) {
6522                 DRM_ERROR("si_enable_power_containment failed\n");
6523                 return ret;
6524         }
6525
6526         ret = si_power_control_set_level(rdev);
6527         if (ret) {
6528                 DRM_ERROR("si_power_control_set_level failed\n");
6529                 return ret;
6530         }
6531
6532         return 0;
6533 }
6534
6535 void si_dpm_post_set_power_state(struct radeon_device *rdev)
6536 {
6537         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6538         struct radeon_ps *new_ps = &eg_pi->requested_rps;
6539
6540         ni_update_current_ps(rdev, new_ps);
6541 }
6542
6543 #if 0
6544 void si_dpm_reset_asic(struct radeon_device *rdev)
6545 {
6546         si_restrict_performance_levels_before_switch(rdev);
6547         si_disable_ulv(rdev);
6548         si_set_boot_state(rdev);
6549 }
6550 #endif
6551
6552 void si_dpm_display_configuration_changed(struct radeon_device *rdev)
6553 {
6554         si_program_display_gap(rdev);
6555 }
6556
6557 union power_info {
6558         struct _ATOM_POWERPLAY_INFO info;
6559         struct _ATOM_POWERPLAY_INFO_V2 info_2;
6560         struct _ATOM_POWERPLAY_INFO_V3 info_3;
6561         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
6562         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
6563         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
6564 };
6565
6566 union pplib_clock_info {
6567         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
6568         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
6569         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
6570         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
6571         struct _ATOM_PPLIB_SI_CLOCK_INFO si;
6572 };
6573
6574 union pplib_power_state {
6575         struct _ATOM_PPLIB_STATE v1;
6576         struct _ATOM_PPLIB_STATE_V2 v2;
6577 };
6578
6579 static void si_parse_pplib_non_clock_info(struct radeon_device *rdev,
6580                                           struct radeon_ps *rps,
6581                                           struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
6582                                           u8 table_rev)
6583 {
6584         rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
6585         rps->class = le16_to_cpu(non_clock_info->usClassification);
6586         rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
6587
6588         if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
6589                 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
6590                 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
6591         } else if (r600_is_uvd_state(rps->class, rps->class2)) {
6592                 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
6593                 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
6594         } else {
6595                 rps->vclk = 0;
6596                 rps->dclk = 0;
6597         }
6598
6599         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
6600                 rdev->pm.dpm.boot_ps = rps;
6601         if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
6602                 rdev->pm.dpm.uvd_ps = rps;
6603 }
6604
6605 static void si_parse_pplib_clock_info(struct radeon_device *rdev,
6606                                       struct radeon_ps *rps, int index,
6607                                       union pplib_clock_info *clock_info)
6608 {
6609         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6610         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6611         struct si_power_info *si_pi = si_get_pi(rdev);
6612         struct ni_ps *ps = ni_get_ps(rps);
6613         u16 leakage_voltage;
6614         struct rv7xx_pl *pl = &ps->performance_levels[index];
6615         int ret;
6616
6617         ps->performance_level_count = index + 1;
6618
6619         pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
6620         pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
6621         pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
6622         pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
6623
6624         pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
6625         pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
6626         pl->flags = le32_to_cpu(clock_info->si.ulFlags);
6627         pl->pcie_gen = r600_get_pcie_gen_support(rdev,
6628                                                  si_pi->sys_pcie_mask,
6629                                                  si_pi->boot_pcie_gen,
6630                                                  clock_info->si.ucPCIEGen);
6631
6632         /* patch up vddc if necessary */
6633         ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc,
6634                                                         &leakage_voltage);
6635         if (ret == 0)
6636                 pl->vddc = leakage_voltage;
6637
6638         if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
6639                 pi->acpi_vddc = pl->vddc;
6640                 eg_pi->acpi_vddci = pl->vddci;
6641                 si_pi->acpi_pcie_gen = pl->pcie_gen;
6642         }
6643
6644         if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
6645             index == 0) {
6646                 /* XXX disable for A0 tahiti */
6647                 si_pi->ulv.supported = false;
6648                 si_pi->ulv.pl = *pl;
6649                 si_pi->ulv.one_pcie_lane_in_ulv = false;
6650                 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
6651                 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
6652                 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
6653         }
6654
6655         if (pi->min_vddc_in_table > pl->vddc)
6656                 pi->min_vddc_in_table = pl->vddc;
6657
6658         if (pi->max_vddc_in_table < pl->vddc)
6659                 pi->max_vddc_in_table = pl->vddc;
6660
6661         /* patch up boot state */
6662         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
6663                 u16 vddc, vddci, mvdd;
6664                 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
6665                 pl->mclk = rdev->clock.default_mclk;
6666                 pl->sclk = rdev->clock.default_sclk;
6667                 pl->vddc = vddc;
6668                 pl->vddci = vddci;
6669                 si_pi->mvdd_bootup_value = mvdd;
6670         }
6671
6672         if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
6673             ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
6674                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
6675                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
6676                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
6677                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
6678         }
6679 }
6680
6681 static int si_parse_power_table(struct radeon_device *rdev)
6682 {
6683         struct radeon_mode_info *mode_info = &rdev->mode_info;
6684         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
6685         union pplib_power_state *power_state;
6686         int i, j, k, non_clock_array_index, clock_array_index;
6687         union pplib_clock_info *clock_info;
6688         struct _StateArray *state_array;
6689         struct _ClockInfoArray *clock_info_array;
6690         struct _NonClockInfoArray *non_clock_info_array;
6691         union power_info *power_info;
6692         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
6693         u16 data_offset;
6694         u8 frev, crev;
6695         u8 *power_state_offset;
6696         struct ni_ps *ps;
6697
6698         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
6699                                    &frev, &crev, &data_offset))
6700                 return -EINVAL;
6701         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
6702
6703         state_array = (struct _StateArray *)
6704                 (mode_info->atom_context->bios + data_offset +
6705                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
6706         clock_info_array = (struct _ClockInfoArray *)
6707                 (mode_info->atom_context->bios + data_offset +
6708                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
6709         non_clock_info_array = (struct _NonClockInfoArray *)
6710                 (mode_info->atom_context->bios + data_offset +
6711                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
6712
6713         rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
6714                                   state_array->ucNumEntries, GFP_KERNEL);
6715         if (!rdev->pm.dpm.ps)
6716                 return -ENOMEM;
6717         power_state_offset = (u8 *)state_array->states;
6718         for (i = 0; i < state_array->ucNumEntries; i++) {
6719                 u8 *idx;
6720                 power_state = (union pplib_power_state *)power_state_offset;
6721                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
6722                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
6723                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
6724                 if (!rdev->pm.power_state[i].clock_info)
6725                         return -EINVAL;
6726                 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL);
6727                 if (ps == NULL) {
6728                         kfree(rdev->pm.dpm.ps);
6729                         return -ENOMEM;
6730                 }
6731                 rdev->pm.dpm.ps[i].ps_priv = ps;
6732                 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
6733                                               non_clock_info,
6734                                               non_clock_info_array->ucEntrySize);
6735                 k = 0;
6736                 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
6737                 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
6738                         clock_array_index = idx[j];
6739                         if (clock_array_index >= clock_info_array->ucNumEntries)
6740                                 continue;
6741                         if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
6742                                 break;
6743                         clock_info = (union pplib_clock_info *)
6744                                 ((u8 *)&clock_info_array->clockInfo[0] +
6745                                  (clock_array_index * clock_info_array->ucEntrySize));
6746                         si_parse_pplib_clock_info(rdev,
6747                                                   &rdev->pm.dpm.ps[i], k,
6748                                                   clock_info);
6749                         k++;
6750                 }
6751                 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
6752         }
6753         rdev->pm.dpm.num_ps = state_array->ucNumEntries;
6754         return 0;
6755 }
6756
6757 int si_dpm_init(struct radeon_device *rdev)
6758 {
6759         struct rv7xx_power_info *pi;
6760         struct evergreen_power_info *eg_pi;
6761         struct ni_power_info *ni_pi;
6762         struct si_power_info *si_pi;
6763         struct atom_clock_dividers dividers;
6764         int ret;
6765         u32 mask;
6766
6767         si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
6768         if (si_pi == NULL)
6769                 return -ENOMEM;
6770         rdev->pm.dpm.priv = si_pi;
6771         ni_pi = &si_pi->ni;
6772         eg_pi = &ni_pi->eg;
6773         pi = &eg_pi->rv7xx;
6774
6775         ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
6776         if (ret)
6777                 si_pi->sys_pcie_mask = 0;
6778         else
6779                 si_pi->sys_pcie_mask = mask;
6780         si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
6781         si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev);
6782
6783         si_set_max_cu_value(rdev);
6784
6785         rv770_get_max_vddc(rdev);
6786         si_get_leakage_vddc(rdev);
6787         si_patch_dependency_tables_based_on_leakage(rdev);
6788
6789         pi->acpi_vddc = 0;
6790         eg_pi->acpi_vddci = 0;
6791         pi->min_vddc_in_table = 0;
6792         pi->max_vddc_in_table = 0;
6793
6794         ret = r600_get_platform_caps(rdev);
6795         if (ret)
6796                 return ret;
6797
6798         ret = si_parse_power_table(rdev);
6799         if (ret)
6800                 return ret;
6801         ret = r600_parse_extended_power_table(rdev);
6802         if (ret)
6803                 return ret;
6804
6805         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
6806                 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL);
6807         if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
6808                 r600_free_extended_power_table(rdev);
6809                 return -ENOMEM;
6810         }
6811         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
6812         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
6813         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
6814         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
6815         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
6816         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
6817         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
6818         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
6819         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
6820
6821         if (rdev->pm.dpm.voltage_response_time == 0)
6822                 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
6823         if (rdev->pm.dpm.backbias_response_time == 0)
6824                 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
6825
6826         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
6827                                              0, false, &dividers);
6828         if (ret)
6829                 pi->ref_div = dividers.ref_div + 1;
6830         else
6831                 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
6832
6833         eg_pi->smu_uvd_hs = false;
6834
6835         pi->mclk_strobe_mode_threshold = 40000;
6836         if (si_is_special_1gb_platform(rdev))
6837                 pi->mclk_stutter_mode_threshold = 0;
6838         else
6839                 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
6840         pi->mclk_edc_enable_threshold = 40000;
6841         eg_pi->mclk_edc_wr_enable_threshold = 40000;
6842
6843         ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
6844
6845         pi->voltage_control =
6846                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
6847                                             VOLTAGE_OBJ_GPIO_LUT);
6848         if (!pi->voltage_control) {
6849                 si_pi->voltage_control_svi2 =
6850                         radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
6851                                                     VOLTAGE_OBJ_SVID2);
6852                 if (si_pi->voltage_control_svi2)
6853                         radeon_atom_get_svi2_info(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
6854                                                   &si_pi->svd_gpio_id, &si_pi->svc_gpio_id);
6855         }
6856
6857         pi->mvdd_control =
6858                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC,
6859                                             VOLTAGE_OBJ_GPIO_LUT);
6860
6861         eg_pi->vddci_control =
6862                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
6863                                             VOLTAGE_OBJ_GPIO_LUT);
6864         if (!eg_pi->vddci_control)
6865                 si_pi->vddci_control_svi2 =
6866                         radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
6867                                                     VOLTAGE_OBJ_SVID2);
6868
6869         si_pi->vddc_phase_shed_control =
6870                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
6871                                             VOLTAGE_OBJ_PHASE_LUT);
6872
6873         rv770_get_engine_memory_ss(rdev);
6874
6875         pi->asi = RV770_ASI_DFLT;
6876         pi->pasi = CYPRESS_HASI_DFLT;
6877         pi->vrc = SISLANDS_VRC_DFLT;
6878
6879         pi->gfx_clock_gating = true;
6880
6881         eg_pi->sclk_deep_sleep = true;
6882         si_pi->sclk_deep_sleep_above_low = false;
6883
6884         if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
6885                 pi->thermal_protection = true;
6886         else
6887                 pi->thermal_protection = false;
6888
6889         eg_pi->dynamic_ac_timing = true;
6890
6891         eg_pi->light_sleep = true;
6892 #if defined(CONFIG_ACPI)
6893         eg_pi->pcie_performance_request =
6894                 radeon_acpi_is_pcie_performance_request_supported(rdev);
6895 #else
6896         eg_pi->pcie_performance_request = false;
6897 #endif
6898
6899         si_pi->sram_end = SMC_RAM_END;
6900
6901         rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
6902         rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
6903         rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
6904         rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
6905         rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
6906         rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
6907         rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
6908
6909         si_initialize_powertune_defaults(rdev);
6910
6911         /* make sure dc limits are valid */
6912         if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
6913             (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
6914                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
6915                         rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
6916
6917         si_pi->fan_ctrl_is_in_default_mode = true;
6918         rdev->pm.dpm.fan.ucode_fan_control = false;
6919
6920         return 0;
6921 }
6922
6923 void si_dpm_fini(struct radeon_device *rdev)
6924 {
6925         int i;
6926
6927         for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
6928                 kfree(rdev->pm.dpm.ps[i].ps_priv);
6929         }
6930         kfree(rdev->pm.dpm.ps);
6931         kfree(rdev->pm.dpm.priv);
6932         kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
6933         r600_free_extended_power_table(rdev);
6934 }
6935
6936 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
6937                                                     struct seq_file *m)
6938 {
6939         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6940         struct radeon_ps *rps = &eg_pi->current_rps;
6941         struct ni_ps *ps = ni_get_ps(rps);
6942         struct rv7xx_pl *pl;
6943         u32 current_index =
6944                 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
6945                 CURRENT_STATE_INDEX_SHIFT;
6946
6947         if (current_index >= ps->performance_level_count) {
6948                 seq_printf(m, "invalid dpm profile %d\n", current_index);
6949         } else {
6950                 pl = &ps->performance_levels[current_index];
6951                 seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
6952                 seq_printf(m, "power level %d    sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
6953                            current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
6954         }
6955 }