2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_wb.c,v 1.26.2.6 2003/03/05 18:42:34 njl Exp $
33 * $DragonFly: src/sys/dev/netif/wb/if_wb.c,v 1.13 2004/07/29 08:46:23 dillon Exp $
35 * $FreeBSD: src/sys/pci/if_wb.c,v 1.26.2.6 2003/03/05 18:42:34 njl Exp $
39 * Winbond fast ethernet PCI NIC driver
41 * Supports various cheap network adapters based on the Winbond W89C840F
42 * fast ethernet controller chip. This includes adapters manufactured by
43 * Winbond itself and some made by Linksys.
45 * Written by Bill Paul <wpaul@ctr.columbia.edu>
46 * Electrical Engineering Department
47 * Columbia University, New York City
51 * The Winbond W89C840F chip is a bus master; in some ways it resembles
52 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has
53 * one major difference which is that while the registers do many of
54 * the same things as a tulip adapter, the offsets are different: where
55 * tulip registers are typically spaced 8 bytes apart, the Winbond
56 * registers are spaced 4 bytes apart. The receiver filter is also
57 * programmed differently.
59 * Like the tulip, the Winbond chip uses small descriptors containing
60 * a status word, a control word and 32-bit areas that can either be used
61 * to point to two external data blocks, or to point to a single block
62 * and another descriptor in a linked list. Descriptors can be grouped
63 * together in blocks to form fixed length rings or can be chained
64 * together in linked lists. A single packet may be spread out over
65 * several descriptors if necessary.
67 * For the receive ring, this driver uses a linked list of descriptors,
68 * each pointing to a single mbuf cluster buffer, which us large enough
69 * to hold an entire packet. The link list is looped back to created a
72 * For transmission, the driver creates a linked list of 'super descriptors'
73 * which each contain several individual descriptors linked toghether.
74 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we
75 * abuse as fragment pointers. This allows us to use a buffer managment
76 * scheme very similar to that used in the ThunderLAN and Etherlink XL
79 * Autonegotiation is performed using the external PHY via the MII bus.
80 * The sample boards I have all use a Davicom PHY.
82 * Note: the author of the Linux driver for the Winbond chip alludes
83 * to some sort of flaw in the chip's design that seems to mandate some
84 * drastic workaround which signigicantly impairs transmit performance.
85 * I have no idea what he's on about: transmit performance with all
86 * three of my test boards seems fine.
91 #include <sys/param.h>
92 #include <sys/systm.h>
93 #include <sys/sockio.h>
95 #include <sys/malloc.h>
96 #include <sys/kernel.h>
97 #include <sys/socket.h>
98 #include <sys/queue.h>
101 #include <net/if_arp.h>
102 #include <net/ethernet.h>
103 #include <net/if_dl.h>
104 #include <net/if_media.h>
108 #include <vm/vm.h> /* for vtophys */
109 #include <vm/pmap.h> /* for vtophys */
110 #include <machine/clock.h> /* for DELAY */
111 #include <machine/bus_memio.h>
112 #include <machine/bus_pio.h>
113 #include <machine/bus.h>
114 #include <machine/resource.h>
116 #include <sys/rman.h>
118 #include <bus/pci/pcireg.h>
119 #include <bus/pci/pcivar.h>
121 #include "../mii_layer/mii.h"
122 #include "../mii_layer/miivar.h"
124 /* "controller miibus0" required. See GENERIC if you get errors here. */
125 #include "miibus_if.h"
127 #define WB_USEIOSPACE
129 #include "if_wbreg.h"
132 * Various supported device vendors/types and their names.
134 static struct wb_type wb_devs[] = {
135 { WB_VENDORID, WB_DEVICEID_840F,
136 "Winbond W89C840F 10/100BaseTX" },
137 { CP_VENDORID, CP_DEVICEID_RL100,
138 "Compex RL100-ATX 10/100baseTX" },
142 static int wb_probe (device_t);
143 static int wb_attach (device_t);
144 static int wb_detach (device_t);
146 static void wb_bfree (caddr_t, u_int);
147 static int wb_newbuf (struct wb_softc *,
148 struct wb_chain_onefrag *,
150 static int wb_encap (struct wb_softc *, struct wb_chain *,
153 static void wb_rxeof (struct wb_softc *);
154 static void wb_rxeoc (struct wb_softc *);
155 static void wb_txeof (struct wb_softc *);
156 static void wb_txeoc (struct wb_softc *);
157 static void wb_intr (void *);
158 static void wb_tick (void *);
159 static void wb_start (struct ifnet *);
160 static int wb_ioctl (struct ifnet *, u_long, caddr_t,
162 static void wb_init (void *);
163 static void wb_stop (struct wb_softc *);
164 static void wb_watchdog (struct ifnet *);
165 static void wb_shutdown (device_t);
166 static int wb_ifmedia_upd (struct ifnet *);
167 static void wb_ifmedia_sts (struct ifnet *, struct ifmediareq *);
169 static void wb_eeprom_putbyte (struct wb_softc *, int);
170 static void wb_eeprom_getword (struct wb_softc *, int, u_int16_t *);
171 static void wb_read_eeprom (struct wb_softc *, caddr_t, int,
173 static void wb_mii_sync (struct wb_softc *);
174 static void wb_mii_send (struct wb_softc *, u_int32_t, int);
175 static int wb_mii_readreg (struct wb_softc *, struct wb_mii_frame *);
176 static int wb_mii_writereg (struct wb_softc *, struct wb_mii_frame *);
178 static void wb_setcfg (struct wb_softc *, u_int32_t);
179 static u_int8_t wb_calchash (caddr_t);
180 static void wb_setmulti (struct wb_softc *);
181 static void wb_reset (struct wb_softc *);
182 static void wb_fixmedia (struct wb_softc *);
183 static int wb_list_rx_init (struct wb_softc *);
184 static int wb_list_tx_init (struct wb_softc *);
186 static int wb_miibus_readreg (device_t, int, int);
187 static int wb_miibus_writereg (device_t, int, int, int);
188 static void wb_miibus_statchg (device_t);
191 #define WB_RES SYS_RES_IOPORT
192 #define WB_RID WB_PCI_LOIO
194 #define WB_RES SYS_RES_MEMORY
195 #define WB_RID WB_PCI_LOMEM
198 static device_method_t wb_methods[] = {
199 /* Device interface */
200 DEVMETHOD(device_probe, wb_probe),
201 DEVMETHOD(device_attach, wb_attach),
202 DEVMETHOD(device_detach, wb_detach),
203 DEVMETHOD(device_shutdown, wb_shutdown),
205 /* bus interface, for miibus */
206 DEVMETHOD(bus_print_child, bus_generic_print_child),
207 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
210 DEVMETHOD(miibus_readreg, wb_miibus_readreg),
211 DEVMETHOD(miibus_writereg, wb_miibus_writereg),
212 DEVMETHOD(miibus_statchg, wb_miibus_statchg),
216 static driver_t wb_driver = {
219 sizeof(struct wb_softc)
222 static devclass_t wb_devclass;
224 DECLARE_DUMMY_MODULE(if_wb);
225 DRIVER_MODULE(if_wb, pci, wb_driver, wb_devclass, 0, 0);
226 DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0);
228 #define WB_SETBIT(sc, reg, x) \
229 CSR_WRITE_4(sc, reg, \
230 CSR_READ_4(sc, reg) | x)
232 #define WB_CLRBIT(sc, reg, x) \
233 CSR_WRITE_4(sc, reg, \
234 CSR_READ_4(sc, reg) & ~x)
237 CSR_WRITE_4(sc, WB_SIO, \
238 CSR_READ_4(sc, WB_SIO) | x)
241 CSR_WRITE_4(sc, WB_SIO, \
242 CSR_READ_4(sc, WB_SIO) & ~x)
245 * Send a read command and address to the EEPROM, check for ACK.
247 static void wb_eeprom_putbyte(sc, addr)
253 d = addr | WB_EECMD_READ;
256 * Feed in each bit and stobe the clock.
258 for (i = 0x400; i; i >>= 1) {
260 SIO_SET(WB_SIO_EE_DATAIN);
262 SIO_CLR(WB_SIO_EE_DATAIN);
265 SIO_SET(WB_SIO_EE_CLK);
267 SIO_CLR(WB_SIO_EE_CLK);
275 * Read a word of data stored in the EEPROM at address 'addr.'
277 static void wb_eeprom_getword(sc, addr, dest)
285 /* Enter EEPROM access mode. */
286 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
289 * Send address of word we want to read.
291 wb_eeprom_putbyte(sc, addr);
293 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
296 * Start reading bits from EEPROM.
298 for (i = 0x8000; i; i >>= 1) {
299 SIO_SET(WB_SIO_EE_CLK);
301 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT)
303 SIO_CLR(WB_SIO_EE_CLK);
307 /* Turn off EEPROM access mode. */
308 CSR_WRITE_4(sc, WB_SIO, 0);
316 * Read a sequence of words from the EEPROM.
318 static void wb_read_eeprom(sc, dest, off, cnt, swap)
326 u_int16_t word = 0, *ptr;
328 for (i = 0; i < cnt; i++) {
329 wb_eeprom_getword(sc, off + i, &word);
330 ptr = (u_int16_t *)(dest + (i * 2));
341 * Sync the PHYs by setting data bit and strobing the clock 32 times.
343 static void wb_mii_sync(sc)
348 SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN);
350 for (i = 0; i < 32; i++) {
351 SIO_SET(WB_SIO_MII_CLK);
353 SIO_CLR(WB_SIO_MII_CLK);
361 * Clock a series of bits through the MII.
363 static void wb_mii_send(sc, bits, cnt)
370 SIO_CLR(WB_SIO_MII_CLK);
372 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
374 SIO_SET(WB_SIO_MII_DATAIN);
376 SIO_CLR(WB_SIO_MII_DATAIN);
379 SIO_CLR(WB_SIO_MII_CLK);
381 SIO_SET(WB_SIO_MII_CLK);
386 * Read an PHY register through the MII.
388 static int wb_mii_readreg(sc, frame)
390 struct wb_mii_frame *frame;
398 * Set up frame for RX.
400 frame->mii_stdelim = WB_MII_STARTDELIM;
401 frame->mii_opcode = WB_MII_READOP;
402 frame->mii_turnaround = 0;
405 CSR_WRITE_4(sc, WB_SIO, 0);
410 SIO_SET(WB_SIO_MII_DIR);
415 * Send command/address info.
417 wb_mii_send(sc, frame->mii_stdelim, 2);
418 wb_mii_send(sc, frame->mii_opcode, 2);
419 wb_mii_send(sc, frame->mii_phyaddr, 5);
420 wb_mii_send(sc, frame->mii_regaddr, 5);
423 SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN));
425 SIO_SET(WB_SIO_MII_CLK);
429 SIO_CLR(WB_SIO_MII_DIR);
431 SIO_CLR(WB_SIO_MII_CLK);
433 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT;
434 SIO_SET(WB_SIO_MII_CLK);
436 SIO_CLR(WB_SIO_MII_CLK);
438 SIO_SET(WB_SIO_MII_CLK);
442 * Now try reading data bits. If the ack failed, we still
443 * need to clock through 16 cycles to keep the PHY(s) in sync.
446 for(i = 0; i < 16; i++) {
447 SIO_CLR(WB_SIO_MII_CLK);
449 SIO_SET(WB_SIO_MII_CLK);
455 for (i = 0x8000; i; i >>= 1) {
456 SIO_CLR(WB_SIO_MII_CLK);
459 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT)
460 frame->mii_data |= i;
463 SIO_SET(WB_SIO_MII_CLK);
469 SIO_CLR(WB_SIO_MII_CLK);
471 SIO_SET(WB_SIO_MII_CLK);
482 * Write to a PHY register through the MII.
484 static int wb_mii_writereg(sc, frame)
486 struct wb_mii_frame *frame;
493 * Set up frame for TX.
496 frame->mii_stdelim = WB_MII_STARTDELIM;
497 frame->mii_opcode = WB_MII_WRITEOP;
498 frame->mii_turnaround = WB_MII_TURNAROUND;
501 * Turn on data output.
503 SIO_SET(WB_SIO_MII_DIR);
507 wb_mii_send(sc, frame->mii_stdelim, 2);
508 wb_mii_send(sc, frame->mii_opcode, 2);
509 wb_mii_send(sc, frame->mii_phyaddr, 5);
510 wb_mii_send(sc, frame->mii_regaddr, 5);
511 wb_mii_send(sc, frame->mii_turnaround, 2);
512 wb_mii_send(sc, frame->mii_data, 16);
515 SIO_SET(WB_SIO_MII_CLK);
517 SIO_CLR(WB_SIO_MII_CLK);
523 SIO_CLR(WB_SIO_MII_DIR);
530 static int wb_miibus_readreg(dev, phy, reg)
535 struct wb_mii_frame frame;
537 sc = device_get_softc(dev);
539 bzero((char *)&frame, sizeof(frame));
541 frame.mii_phyaddr = phy;
542 frame.mii_regaddr = reg;
543 wb_mii_readreg(sc, &frame);
545 return(frame.mii_data);
548 static int wb_miibus_writereg(dev, phy, reg, data)
553 struct wb_mii_frame frame;
555 sc = device_get_softc(dev);
557 bzero((char *)&frame, sizeof(frame));
559 frame.mii_phyaddr = phy;
560 frame.mii_regaddr = reg;
561 frame.mii_data = data;
563 wb_mii_writereg(sc, &frame);
568 static void wb_miibus_statchg(dev)
572 struct mii_data *mii;
574 sc = device_get_softc(dev);
575 mii = device_get_softc(sc->wb_miibus);
576 wb_setcfg(sc, mii->mii_media_active);
581 static u_int8_t wb_calchash(addr)
584 u_int32_t crc, carry;
588 /* Compute CRC for the address value. */
589 crc = 0xFFFFFFFF; /* initial value */
591 for (i = 0; i < 6; i++) {
593 for (j = 0; j < 8; j++) {
594 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
598 crc = (crc ^ 0x04c11db6) | carry;
603 * return the filter bit position
604 * Note: I arrived at the following nonsense
605 * through experimentation. It's not the usual way to
606 * generate the bit position but it's the only thing
607 * I could come up with that works.
609 return(~(crc >> 26) & 0x0000003F);
613 * Program the 64-bit multicast hash filter.
615 static void wb_setmulti(sc)
620 u_int32_t hashes[2] = { 0, 0 };
621 struct ifmultiaddr *ifma;
625 ifp = &sc->arpcom.ac_if;
627 rxfilt = CSR_READ_4(sc, WB_NETCFG);
629 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
630 rxfilt |= WB_NETCFG_RX_MULTI;
631 CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
632 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF);
633 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF);
637 /* first, zot all the existing hash bits */
638 CSR_WRITE_4(sc, WB_MAR0, 0);
639 CSR_WRITE_4(sc, WB_MAR1, 0);
641 /* now program new ones */
642 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
643 ifma = ifma->ifma_link.le_next) {
644 if (ifma->ifma_addr->sa_family != AF_LINK)
646 h = wb_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
648 hashes[0] |= (1 << h);
650 hashes[1] |= (1 << (h - 32));
655 rxfilt |= WB_NETCFG_RX_MULTI;
657 rxfilt &= ~WB_NETCFG_RX_MULTI;
659 CSR_WRITE_4(sc, WB_MAR0, hashes[0]);
660 CSR_WRITE_4(sc, WB_MAR1, hashes[1]);
661 CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
667 * The Winbond manual states that in order to fiddle with the
668 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
669 * first have to put the transmit and/or receive logic in the idle state.
671 static void wb_setcfg(sc, media)
677 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) {
679 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON));
681 for (i = 0; i < WB_TIMEOUT; i++) {
683 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) &&
684 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE))
689 printf("wb%d: failed to force tx and "
690 "rx to idle state\n", sc->wb_unit);
693 if (IFM_SUBTYPE(media) == IFM_10_T)
694 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
696 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
698 if ((media & IFM_GMASK) == IFM_FDX)
699 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
701 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
704 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON);
709 static void wb_reset(sc)
713 struct mii_data *mii;
715 CSR_WRITE_4(sc, WB_NETCFG, 0);
716 CSR_WRITE_4(sc, WB_BUSCTL, 0);
717 CSR_WRITE_4(sc, WB_TXADDR, 0);
718 CSR_WRITE_4(sc, WB_RXADDR, 0);
720 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
721 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
723 for (i = 0; i < WB_TIMEOUT; i++) {
725 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET))
729 printf("wb%d: reset never completed!\n", sc->wb_unit);
731 /* Wait a little while for the chip to get its brains in order. */
734 if (sc->wb_miibus == NULL)
737 mii = device_get_softc(sc->wb_miibus);
741 if (mii->mii_instance) {
742 struct mii_softc *miisc;
743 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
744 miisc = LIST_NEXT(miisc, mii_list))
745 mii_phy_reset(miisc);
751 static void wb_fixmedia(sc)
754 struct mii_data *mii = NULL;
758 if (sc->wb_miibus == NULL)
761 mii = device_get_softc(sc->wb_miibus);
762 ifp = &sc->arpcom.ac_if;
765 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) {
766 media = mii->mii_media_active & ~IFM_10_T;
768 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
769 media = mii->mii_media_active & ~IFM_100_TX;
774 ifmedia_set(&mii->mii_media, media);
780 * Probe for a Winbond chip. Check the PCI vendor and device
781 * IDs against our list and return a device name if we find a match.
783 static int wb_probe(dev)
790 while(t->wb_name != NULL) {
791 if ((pci_get_vendor(dev) == t->wb_vid) &&
792 (pci_get_device(dev) == t->wb_did)) {
793 device_set_desc(dev, t->wb_name);
803 * Attach the interface. Allocate softc structures, do ifmedia
804 * setup and ethernet/BPF attach.
806 static int wb_attach(dev)
810 u_char eaddr[ETHER_ADDR_LEN];
814 int unit, error = 0, rid;
818 sc = device_get_softc(dev);
819 unit = device_get_unit(dev);
822 * Handle power management nonsense.
825 command = pci_read_config(dev, WB_PCI_CAPID, 4) & 0x000000FF;
826 if (command == 0x01) {
828 command = pci_read_config(dev, WB_PCI_PWRMGMTCTRL, 4);
829 if (command & WB_PSTATE_MASK) {
830 u_int32_t iobase, membase, irq;
832 /* Save important PCI config data. */
833 iobase = pci_read_config(dev, WB_PCI_LOIO, 4);
834 membase = pci_read_config(dev, WB_PCI_LOMEM, 4);
835 irq = pci_read_config(dev, WB_PCI_INTLINE, 4);
837 /* Reset the power state. */
838 printf("wb%d: chip is in D%d power mode "
839 "-- setting to D0\n", unit, command & WB_PSTATE_MASK);
840 command &= 0xFFFFFFFC;
841 pci_write_config(dev, WB_PCI_PWRMGMTCTRL, command, 4);
843 /* Restore PCI config data. */
844 pci_write_config(dev, WB_PCI_LOIO, iobase, 4);
845 pci_write_config(dev, WB_PCI_LOMEM, membase, 4);
846 pci_write_config(dev, WB_PCI_INTLINE, irq, 4);
851 * Map control/status registers.
853 command = pci_read_config(dev, PCIR_COMMAND, 4);
854 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
855 pci_write_config(dev, PCIR_COMMAND, command, 4);
856 command = pci_read_config(dev, PCIR_COMMAND, 4);
859 if (!(command & PCIM_CMD_PORTEN)) {
860 printf("wb%d: failed to enable I/O ports!\n", unit);
865 if (!(command & PCIM_CMD_MEMEN)) {
866 printf("wb%d: failed to enable memory mapping!\n", unit);
873 sc->wb_res = bus_alloc_resource(dev, WB_RES, &rid,
874 0, ~0, 1, RF_ACTIVE);
876 if (sc->wb_res == NULL) {
877 printf("wb%d: couldn't map ports/memory\n", unit);
882 sc->wb_btag = rman_get_bustag(sc->wb_res);
883 sc->wb_bhandle = rman_get_bushandle(sc->wb_res);
885 /* Allocate interrupt */
887 sc->wb_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
888 RF_SHAREABLE | RF_ACTIVE);
890 if (sc->wb_irq == NULL) {
891 printf("wb%d: couldn't map interrupt\n", unit);
892 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
897 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET,
898 wb_intr, sc, &sc->wb_intrhand);
901 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
902 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
903 printf("wb%d: couldn't set up irq\n", unit);
907 /* Save the cache line size. */
908 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF;
910 /* Reset the adapter. */
914 * Get station address from the EEPROM.
916 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0);
920 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF,
921 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
923 if (sc->wb_ldata == NULL) {
924 printf("wb%d: no memory for list buffers!\n", unit);
925 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand);
926 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
927 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
932 bzero(sc->wb_ldata, sizeof(struct wb_list_data));
934 ifp = &sc->arpcom.ac_if;
936 if_initname(ifp, "wb", unit);
937 ifp->if_mtu = ETHERMTU;
938 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
939 ifp->if_ioctl = wb_ioctl;
940 ifp->if_start = wb_start;
941 ifp->if_watchdog = wb_watchdog;
942 ifp->if_init = wb_init;
943 ifp->if_baudrate = 10000000;
944 ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1;
949 if (mii_phy_probe(dev, &sc->wb_miibus,
950 wb_ifmedia_upd, wb_ifmedia_sts)) {
951 contigfree(sc->wb_ldata_ptr, sizeof(struct wb_list_data) + 8,
953 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand);
954 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
955 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
961 * Call MI attach routine.
963 ether_ifattach(ifp, eaddr);
967 device_delete_child(dev, sc->wb_miibus);
973 static int wb_detach(dev)
982 sc = device_get_softc(dev);
983 ifp = &sc->arpcom.ac_if;
988 /* Delete any miibus and phy devices attached to this interface */
989 bus_generic_detach(dev);
990 device_delete_child(dev, sc->wb_miibus);
992 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand);
993 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
994 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
996 contigfree(sc->wb_ldata_ptr, sizeof(struct wb_list_data) + 8,
1005 * Initialize the transmit descriptors.
1007 static int wb_list_tx_init(sc)
1008 struct wb_softc *sc;
1010 struct wb_chain_data *cd;
1011 struct wb_list_data *ld;
1017 for (i = 0; i < WB_TX_LIST_CNT; i++) {
1018 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i];
1019 if (i == (WB_TX_LIST_CNT - 1)) {
1020 cd->wb_tx_chain[i].wb_nextdesc =
1021 &cd->wb_tx_chain[0];
1023 cd->wb_tx_chain[i].wb_nextdesc =
1024 &cd->wb_tx_chain[i + 1];
1028 cd->wb_tx_free = &cd->wb_tx_chain[0];
1029 cd->wb_tx_tail = cd->wb_tx_head = NULL;
1036 * Initialize the RX descriptors and allocate mbufs for them. Note that
1037 * we arrange the descriptors in a closed ring, so that the last descriptor
1038 * points back to the first.
1040 static int wb_list_rx_init(sc)
1041 struct wb_softc *sc;
1043 struct wb_chain_data *cd;
1044 struct wb_list_data *ld;
1050 for (i = 0; i < WB_RX_LIST_CNT; i++) {
1051 cd->wb_rx_chain[i].wb_ptr =
1052 (struct wb_desc *)&ld->wb_rx_list[i];
1053 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i];
1054 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS)
1056 if (i == (WB_RX_LIST_CNT - 1)) {
1057 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0];
1058 ld->wb_rx_list[i].wb_next =
1059 vtophys(&ld->wb_rx_list[0]);
1061 cd->wb_rx_chain[i].wb_nextdesc =
1062 &cd->wb_rx_chain[i + 1];
1063 ld->wb_rx_list[i].wb_next =
1064 vtophys(&ld->wb_rx_list[i + 1]);
1068 cd->wb_rx_head = &cd->wb_rx_chain[0];
1073 static void wb_bfree(buf, size)
1081 * Initialize an RX descriptor and attach an MBUF cluster.
1083 static int wb_newbuf(sc, c, m)
1084 struct wb_softc *sc;
1085 struct wb_chain_onefrag *c;
1088 struct mbuf *m_new = NULL;
1091 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
1095 m_new->m_data = m_new->m_ext.ext_buf = c->wb_buf;
1096 m_new->m_flags |= M_EXT | M_EXT_OLD;
1097 m_new->m_ext.ext_size = m_new->m_pkthdr.len =
1098 m_new->m_len = WB_BUFBYTES;
1099 m_new->m_ext.ext_nfree.old = wb_bfree;
1100 m_new->m_ext.ext_nref.old = wb_bfree;
1103 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES;
1104 m_new->m_data = m_new->m_ext.ext_buf;
1107 m_adj(m_new, sizeof(u_int64_t));
1110 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t));
1111 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536;
1112 c->wb_ptr->wb_status = WB_RXSTAT;
1118 * A frame has been uploaded: pass the resulting mbuf chain up to
1119 * the higher level protocols.
1121 static void wb_rxeof(sc)
1122 struct wb_softc *sc;
1124 struct mbuf *m = NULL;
1126 struct wb_chain_onefrag *cur_rx;
1130 ifp = &sc->arpcom.ac_if;
1132 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) &
1134 struct mbuf *m0 = NULL;
1136 cur_rx = sc->wb_cdata.wb_rx_head;
1137 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc;
1139 m = cur_rx->wb_mbuf;
1141 if ((rxstat & WB_RXSTAT_MIIERR) ||
1142 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) ||
1143 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) ||
1144 !(rxstat & WB_RXSTAT_LASTFRAG) ||
1145 !(rxstat & WB_RXSTAT_RXCMP)) {
1147 wb_newbuf(sc, cur_rx, m);
1148 printf("wb%x: receiver babbling: possible chip "
1149 "bug, forcing reset\n", sc->wb_unit);
1156 if (rxstat & WB_RXSTAT_RXERR) {
1158 wb_newbuf(sc, cur_rx, m);
1162 /* No errors; receive the packet. */
1163 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status);
1166 * XXX The Winbond chip includes the CRC with every
1167 * received frame, and there's no way to turn this
1168 * behavior off (at least, I can't find anything in
1169 * the manual that explains how to do it) so we have
1170 * to trim off the CRC manually.
1172 total_len -= ETHER_CRC_LEN;
1174 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1175 total_len + ETHER_ALIGN, 0, ifp, NULL);
1176 wb_newbuf(sc, cur_rx, m);
1181 m_adj(m0, ETHER_ALIGN);
1185 (*ifp->if_input)(ifp, m);
1190 struct wb_softc *sc;
1194 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1195 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
1196 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1197 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND)
1198 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
1204 * A frame was downloaded to the chip. It's safe for us to clean up
1207 static void wb_txeof(sc)
1208 struct wb_softc *sc;
1210 struct wb_chain *cur_tx;
1213 ifp = &sc->arpcom.ac_if;
1215 /* Clear the timeout timer. */
1218 if (sc->wb_cdata.wb_tx_head == NULL)
1222 * Go through our tx list and free mbufs for those
1223 * frames that have been transmitted.
1225 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) {
1228 cur_tx = sc->wb_cdata.wb_tx_head;
1229 txstat = WB_TXSTATUS(cur_tx);
1231 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT)
1234 if (txstat & WB_TXSTAT_TXERR) {
1236 if (txstat & WB_TXSTAT_ABORT)
1237 ifp->if_collisions++;
1238 if (txstat & WB_TXSTAT_LATECOLL)
1239 ifp->if_collisions++;
1242 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3;
1245 m_freem(cur_tx->wb_mbuf);
1246 cur_tx->wb_mbuf = NULL;
1248 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) {
1249 sc->wb_cdata.wb_tx_head = NULL;
1250 sc->wb_cdata.wb_tx_tail = NULL;
1254 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc;
1261 * TX 'end of channel' interrupt handler.
1263 static void wb_txeoc(sc)
1264 struct wb_softc *sc;
1268 ifp = &sc->arpcom.ac_if;
1272 if (sc->wb_cdata.wb_tx_head == NULL) {
1273 ifp->if_flags &= ~IFF_OACTIVE;
1274 sc->wb_cdata.wb_tx_tail = NULL;
1276 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) {
1277 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN;
1279 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1286 static void wb_intr(arg)
1289 struct wb_softc *sc;
1294 ifp = &sc->arpcom.ac_if;
1296 if (!(ifp->if_flags & IFF_UP))
1299 /* Disable interrupts. */
1300 CSR_WRITE_4(sc, WB_IMR, 0x00000000);
1304 status = CSR_READ_4(sc, WB_ISR);
1306 CSR_WRITE_4(sc, WB_ISR, status);
1308 if ((status & WB_INTRS) == 0)
1311 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) {
1314 if (status & WB_ISR_RX_ERR)
1320 if (status & WB_ISR_RX_OK)
1323 if (status & WB_ISR_RX_IDLE)
1326 if (status & WB_ISR_TX_OK)
1329 if (status & WB_ISR_TX_NOBUF)
1332 if (status & WB_ISR_TX_IDLE) {
1334 if (sc->wb_cdata.wb_tx_head != NULL) {
1335 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1336 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1340 if (status & WB_ISR_TX_UNDERRUN) {
1343 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1344 /* Jack up TX threshold */
1345 sc->wb_txthresh += WB_TXTHRESH_CHUNK;
1346 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
1347 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
1348 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1351 if (status & WB_ISR_BUS_ERR) {
1358 /* Re-enable interrupts. */
1359 CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
1361 if (ifp->if_snd.ifq_head != NULL) {
1368 static void wb_tick(xsc)
1371 struct wb_softc *sc;
1372 struct mii_data *mii;
1378 mii = device_get_softc(sc->wb_miibus);
1382 sc->wb_stat_ch = timeout(wb_tick, sc, hz);
1390 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1391 * pointers to the fragment pointers.
1393 static int wb_encap(sc, c, m_head)
1394 struct wb_softc *sc;
1396 struct mbuf *m_head;
1399 struct wb_desc *f = NULL;
1404 * Start packing the mbufs in this chain into
1405 * the fragment pointers. Stop when we run out
1406 * of fragments or hit the end of the mbuf chain.
1411 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1412 if (m->m_len != 0) {
1413 if (frag == WB_MAXFRAGS)
1415 total_len += m->m_len;
1416 f = &c->wb_ptr->wb_frag[frag];
1417 f->wb_ctl = WB_TXCTL_TLINK | m->m_len;
1419 f->wb_ctl |= WB_TXCTL_FIRSTFRAG;
1422 f->wb_status = WB_TXSTAT_OWN;
1423 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]);
1424 f->wb_data = vtophys(mtod(m, vm_offset_t));
1430 * Handle special case: we used up all 16 fragments,
1431 * but we have more mbufs left in the chain. Copy the
1432 * data into an mbuf cluster. Note that we don't
1433 * bother clearing the values in the other fragment
1434 * pointers/counters; it wouldn't gain us anything,
1435 * and would waste cycles.
1438 struct mbuf *m_new = NULL;
1440 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
1443 if (m_head->m_pkthdr.len > MHLEN) {
1444 MCLGET(m_new, MB_DONTWAIT);
1445 if (!(m_new->m_flags & M_EXT)) {
1450 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1451 mtod(m_new, caddr_t));
1452 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1455 f = &c->wb_ptr->wb_frag[0];
1457 f->wb_data = vtophys(mtod(m_new, caddr_t));
1458 f->wb_ctl = total_len = m_new->m_len;
1459 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG;
1463 if (total_len < WB_MIN_FRAMELEN) {
1464 f = &c->wb_ptr->wb_frag[frag];
1465 f->wb_ctl = WB_MIN_FRAMELEN - total_len;
1466 f->wb_data = vtophys(&sc->wb_cdata.wb_pad);
1467 f->wb_ctl |= WB_TXCTL_TLINK;
1468 f->wb_status = WB_TXSTAT_OWN;
1472 c->wb_mbuf = m_head;
1473 c->wb_lastdesc = frag - 1;
1474 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG;
1475 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]);
1481 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1482 * to the mbuf data regions directly in the transmit lists. We also save a
1483 * copy of the pointers since the transmit list fragment pointers are
1484 * physical addresses.
1487 static void wb_start(ifp)
1490 struct wb_softc *sc;
1491 struct mbuf *m_head = NULL;
1492 struct wb_chain *cur_tx = NULL, *start_tx;
1497 * Check for an available queue slot. If there are none,
1500 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) {
1501 ifp->if_flags |= IFF_OACTIVE;
1505 start_tx = sc->wb_cdata.wb_tx_free;
1507 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) {
1508 IF_DEQUEUE(&ifp->if_snd, m_head);
1512 /* Pick a descriptor off the free list. */
1513 cur_tx = sc->wb_cdata.wb_tx_free;
1514 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc;
1516 /* Pack the data into the descriptor. */
1517 wb_encap(sc, cur_tx, m_head);
1519 if (cur_tx != start_tx)
1520 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN;
1523 * If there's a BPF listener, bounce a copy of this frame
1527 bpf_mtap(ifp, cur_tx->wb_mbuf);
1531 * If there are no packets queued, bail.
1537 * Place the request for the upload interrupt
1538 * in the last descriptor in the chain. This way, if
1539 * we're chaining several packets at once, we'll only
1540 * get an interupt once for the whole chain rather than
1541 * once for each packet.
1543 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT;
1544 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT;
1545 sc->wb_cdata.wb_tx_tail = cur_tx;
1547 if (sc->wb_cdata.wb_tx_head == NULL) {
1548 sc->wb_cdata.wb_tx_head = start_tx;
1549 WB_TXOWN(start_tx) = WB_TXSTAT_OWN;
1550 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1553 * We need to distinguish between the case where
1554 * the own bit is clear because the chip cleared it
1555 * and where the own bit is clear because we haven't
1556 * set it yet. The magic value WB_UNSET is just some
1557 * ramdomly chosen number which doesn't have the own
1558 * bit set. When we actually transmit the frame, the
1559 * status word will have _only_ the own bit set, so
1560 * the txeoc handler will be able to tell if it needs
1561 * to initiate another transmission to flush out pending
1564 WB_TXOWN(start_tx) = WB_UNSENT;
1568 * Set a timeout in case the chip goes out to lunch.
1575 static void wb_init(xsc)
1578 struct wb_softc *sc = xsc;
1579 struct ifnet *ifp = &sc->arpcom.ac_if;
1581 struct mii_data *mii;
1585 mii = device_get_softc(sc->wb_miibus);
1588 * Cancel pending I/O and free all RX/TX buffers.
1593 sc->wb_txthresh = WB_TXTHRESH_INIT;
1596 * Set cache alignment and burst length.
1599 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG);
1600 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
1601 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
1604 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION);
1605 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG);
1606 switch(sc->wb_cachesize) {
1608 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG);
1611 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG);
1614 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG);
1618 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE);
1622 /* This doesn't tend to work too well at 100Mbps. */
1623 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON);
1625 /* Init our MAC address */
1626 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1627 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]);
1630 /* Init circular RX list. */
1631 if (wb_list_rx_init(sc) == ENOBUFS) {
1632 printf("wb%d: initialization failed: no "
1633 "memory for rx buffers\n", sc->wb_unit);
1639 /* Init TX descriptors. */
1640 wb_list_tx_init(sc);
1642 /* If we want promiscuous mode, set the allframes bit. */
1643 if (ifp->if_flags & IFF_PROMISC) {
1644 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
1646 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
1650 * Set capture broadcast bit to capture broadcast frames.
1652 if (ifp->if_flags & IFF_BROADCAST) {
1653 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
1655 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
1659 * Program the multicast filter, if necessary.
1664 * Load the address of the RX list.
1666 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1667 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
1670 * Enable interrupts.
1672 CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
1673 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF);
1675 /* Enable receiver and transmitter. */
1676 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1677 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
1679 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1680 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0]));
1681 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1685 ifp->if_flags |= IFF_RUNNING;
1686 ifp->if_flags &= ~IFF_OACTIVE;
1690 sc->wb_stat_ch = timeout(wb_tick, sc, hz);
1696 * Set media options.
1698 static int wb_ifmedia_upd(ifp)
1701 struct wb_softc *sc;
1705 if (ifp->if_flags & IFF_UP)
1712 * Report current media status.
1714 static void wb_ifmedia_sts(ifp, ifmr)
1716 struct ifmediareq *ifmr;
1718 struct wb_softc *sc;
1719 struct mii_data *mii;
1723 mii = device_get_softc(sc->wb_miibus);
1726 ifmr->ifm_active = mii->mii_media_active;
1727 ifmr->ifm_status = mii->mii_media_status;
1732 static int wb_ioctl(ifp, command, data, cr)
1738 struct wb_softc *sc = ifp->if_softc;
1739 struct mii_data *mii;
1740 struct ifreq *ifr = (struct ifreq *) data;
1749 error = ether_ioctl(ifp, command, data);
1752 if (ifp->if_flags & IFF_UP) {
1755 if (ifp->if_flags & IFF_RUNNING)
1767 mii = device_get_softc(sc->wb_miibus);
1768 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1780 static void wb_watchdog(ifp)
1783 struct wb_softc *sc;
1788 printf("wb%d: watchdog timeout\n", sc->wb_unit);
1790 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
1791 printf("wb%d: no carrier - transceiver cable problem?\n",
1798 if (ifp->if_snd.ifq_head != NULL)
1805 * Stop the adapter and free any mbufs allocated to the
1808 static void wb_stop(sc)
1809 struct wb_softc *sc;
1814 ifp = &sc->arpcom.ac_if;
1817 untimeout(wb_tick, sc, sc->wb_stat_ch);
1819 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON));
1820 CSR_WRITE_4(sc, WB_IMR, 0x00000000);
1821 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000);
1822 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000);
1825 * Free data in the RX lists.
1827 for (i = 0; i < WB_RX_LIST_CNT; i++) {
1828 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) {
1829 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf);
1830 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL;
1833 bzero((char *)&sc->wb_ldata->wb_rx_list,
1834 sizeof(sc->wb_ldata->wb_rx_list));
1837 * Free the TX list buffers.
1839 for (i = 0; i < WB_TX_LIST_CNT; i++) {
1840 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) {
1841 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf);
1842 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL;
1846 bzero((char *)&sc->wb_ldata->wb_tx_list,
1847 sizeof(sc->wb_ldata->wb_tx_list));
1849 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1855 * Stop all chip I/O so that the kernel's probe routines don't
1856 * get confused by errant DMAs when rebooting.
1858 static void wb_shutdown(dev)
1861 struct wb_softc *sc;
1863 sc = device_get_softc(dev);