2 .\" Copyright (c) 1995, 1996, 1997, 1998, 2000
3 .\" Justin T. Gibbs. All rights reserved.
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27 .\" $FreeBSD: src/share/man/man4/ahc.4,v 1.22.2.8 2002/01/21 17:38:18 scottl Exp $
28 .\" $DragonFly: src/share/man/man4/ahc.4,v 1.3 2006/02/17 19:37:09 swildner Exp $
35 .Nd Adaptec VL/EISA/PCI SCSI host adapter driver
37 For one or more VL/EISA cards:
41 For one or more PCI cards:
45 To allow PCI adapters to use memory mapped I/O if enabled:
46 .Cd options AHC_ALLOW_MEMIO
48 To configure one or more controllers to assume the target role:
49 .Cd options AHC_TMODE_ENABLE <bitmask of units>
51 For one or more SCSI busses:
52 .Cd device scbus0 at ahc0
54 This driver provides access to the
56 bus(es) connected to Adaptec
71 These chips are found on many motherboards as well as the following
72 Adaptec SCSI controller cards:
107 Driver features include support for twin and wide busses,
108 fast, ultra or ultra2 synchronous transfers depending on controller type,
109 tagged queueing, SCB paging, and target mode.
111 Memory mapped I/O can be enabled for PCI devices with the
112 .Dq Dv AHC_ALLOW_MEMIO
113 configuration option.
114 Memory mapped I/O is more efficient than the alternative, programmed I/O.
115 Most PCI BIOSes will map devices so that either technique for communicating
116 with the card is available.
118 usually when the PCI device is sitting behind a PCI->PCI bridge,
119 the BIOS may fail to properly initialize the chip for memory mapped I/O.
120 The typical symptom of this problem is a system hang if memory mapped I/O
122 Most modern motherboards perform the initialization correctly and work fine
123 with this option enabled.
125 Individual controllers may be configured to operate in the target role
127 .Dq Dv AHC_TMODE_ENABLE
128 configuration option. The value assigned to this option should be a bitmap
129 of all units where target mode is desired.
130 For example, a value of 0x25, would enable target mode on units 0, 2, and 5.
132 Per target configuration performed in the
134 menu, accessible at boot
140 configuration utility for
143 is honored by this driver.
144 This includes synchronous/asynchronous transfers,
145 maximum synchronous negotiation rate,
148 the host adapter's SCSI ID,
152 Twin Channel controllers,
153 the primary channel selection.
154 For systems that store non-volatile settings in a system specific manner
155 rather than a serial eeprom directly connected to the aic7xxx controller,
158 must be enabled for the driver to access this information.
159 This restriction applies to all
161 and many motherboard configurations.
163 Note that I/O addresses are determined automatically by the probe routines,
164 but care should be taken when using a 284x
165 .Pq Tn VESA No local bus controller
168 system. The jumpers setting the I/O area for the 284x should match the
170 slot into which the card is inserted to prevent conflicts with other
174 Performance and feature sets vary throughout the aic7xxx product line.
175 The following table provides a comparison of the different chips supported
178 driver. Note that wide and twin channel features, although always supported
179 by a particular chip, may be disabled in a particular motherboard or card
182 .Bd -ragged -offset indent
183 .Bl -column "aic7770 " "10 " "EISA/VL " "10MHz " "16bit " "SCBs " Features
184 .Em "Chip MIPS Bus MaxSync MaxWidth SCBs Features"
185 aic7770 10 EISA/VL 10MHz 16Bit 4 1
186 aic7850 10 PCI/32 10MHz 8Bit 3
187 aic7860 10 PCI/32 20MHz 8Bit 3
188 aic7870 10 PCI/32 10MHz 16Bit 16
189 aic7880 10 PCI/32 20MHz 16Bit 16
190 aic7890 20 PCI/32 40MHz 16Bit 16 3 4 5 6 7 8
191 aic7891 20 PCI/64 40MHz 16Bit 16 3 4 5 6 7 8
192 aic7892 20 PCI/64 80MHz 16Bit 16 3 4 5 6 7 8
193 aic7895 15 PCI/32 20MHz 16Bit 16 2 3 4 5
194 aic7895C 15 PCI/32 20MHz 16Bit 16 2 3 4 5 8
195 aic7896 20 PCI/32 40MHz 16Bit 16 2 3 4 5 6 7 8
196 aic7897 20 PCI/64 40MHz 16Bit 16 2 3 4 5 6 7 8
197 aic7899 20 PCI/64 80MHz 16Bit 16 2 3 4 5 6 7 8
202 Multiplexed Twin Channel Device - One controller servicing two busses.
204 Multi-function Twin Channel Device - Two controllers on one chip.
206 Command Channel Secondary DMA Engine - Allows scatter gather list and
209 64 Byte SCB Support - SCSI CDB is embedded in the SCB to eliminate an extra DMA.
211 Block Move Instruction Support - Doubles the speed of certain sequencer
215 style Scatter Gather Engine - Improves S/G prefetch performance.
217 Queuing Registers - Allows queueing of new transactions without pausing the
220 Multiple Target IDs - Allows the controller to respond to selection as a
221 target on multiple SCSI IDs.
224 .Sh SCSI CONTROL BLOCKS (SCBs)
225 Every transaction sent to a device on the SCSI bus is assigned a
226 .Sq SCSI Control Block
227 (SCB). The SCB contains all of the information required by the
228 controller to process a transaction. The chip feature table lists
229 the number of SCBs that can be stored in on-chip memory. All chips
230 with model numbers greater than or equal to 7870 allow for the on chip
231 SCB space to be augmented with external SRAM up to a maximum of 255 SCBs.
232 Very few Adaptec controller configurations have external SRAM.
234 If external SRAM is not available, SCBs are a limited resource.
235 Using the SCBs in a straight forward manner would only allow the dirver to
236 handle as many concurrent transactions as there are physical SCBs.
237 To fully utilize the SCSI bus and the devices on it,
238 requires much more concurrency.
239 The solution to this problem is
241 a concept similar to memory paging. SCB paging takes advantage of
242 the fact that devices usually disconnect from the SCSI bus for long
243 periods of time without talking to the controller. The SCBs
244 for disconnected transactions are only of use to the controller
245 when the transfer is resumed. When the host queues another transaction
246 for the controller to execute, the controller firmware will use a
247 free SCB if one is available. Otherwise, the state of the most recently
248 disconnected (and therefore most likely to stay disconnected) SCB is
249 saved, via dma, to host memory, and the local SCB reused to start
250 the new transaction. This allows the controller to queue up to
251 255 transactions regardless of the amount of SCB space. Since the
252 local SCB space serves as a cache for disconnected transactions, the
253 more SCB space available, the less host bus traffic consumed saving
254 and restoring SCB data.
272 sequencer-code assembler,
273 and the firmware running on the aic7xxx chips was written by
274 .An Justin T. Gibbs .
276 Some Quantum drives (at least the Empire 2100 and 1080s) will not run on an
278 Rev B in synchronous mode at 10MHz. Controllers with this problem have a
279 42 MHz clock crystal on them and run slightly above 10MHz. This confuses
280 the drive and hangs the bus. Setting a maximum synchronous negotiation rate
283 utility will allow normal operation.
285 Although the Ultra2 and Ultra160 products have sufficient instruction
286 ram space to support both the initiator and target roles concurrently,
287 this configuration is disabled in favor of allowing the target role
288 to respond on multiple target ids. A method for configuring dual
289 role mode should be provided.
291 Tagged Queuing is not supported in target mode.
293 Reselection in target mode fails to function correctly on all high
294 voltage differential boards as shipped by Adaptec. Information on
295 how to modify HVD board to work correctly in target mode is available