2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
40 #include <sys/mplock2.h>
43 #include <vm/vm_param.h>
45 #include <vm/vm_kern.h>
46 #include <vm/vm_extern.h>
48 #include <vm/vm_map.h>
54 #include <machine/smp.h>
55 #include <machine_base/apic/apicreg.h>
56 #include <machine/atomic.h>
57 #include <machine/cpufunc.h>
58 #include <machine_base/apic/mpapic.h>
59 #include <machine/psl.h>
60 #include <machine/segments.h>
61 #include <machine/tss.h>
62 #include <machine/specialreg.h>
63 #include <machine/globaldata.h>
65 #include <machine/md_var.h> /* setidt() */
66 #include <machine_base/icu/icu.h> /* IPIs */
67 #include <machine_base/isa/intr_machdep.h> /* IPIs */
69 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
71 #define WARMBOOT_TARGET 0
72 #define WARMBOOT_OFF (KERNBASE + 0x0467)
73 #define WARMBOOT_SEG (KERNBASE + 0x0469)
75 #define BIOS_BASE (0xf0000)
76 #define BIOS_SIZE (0x10000)
77 #define BIOS_COUNT (BIOS_SIZE/4)
79 #define CMOS_REG (0x70)
80 #define CMOS_DATA (0x71)
81 #define BIOS_RESET (0x0f)
82 #define BIOS_WARM (0x0a)
84 #define PROCENTRY_FLAG_EN 0x01
85 #define PROCENTRY_FLAG_BP 0x02
86 #define IOAPICENTRY_FLAG_EN 0x01
89 /* MP Floating Pointer Structure */
90 typedef struct MPFPS {
103 /* MP Configuration Table Header */
104 typedef struct MPCTH {
106 u_short base_table_length;
110 u_char product_id[12];
111 u_int32_t oem_table_pointer;
112 u_short oem_table_size;
114 u_int32_t apic_address;
115 u_short extended_table_length;
116 u_char extended_table_checksum;
121 typedef struct PROCENTRY {
126 u_int32_t cpu_signature;
127 u_int32_t feature_flags;
132 typedef struct BUSENTRY {
138 typedef struct IOAPICENTRY {
143 u_int32_t apic_address;
144 } *io_apic_entry_ptr;
146 typedef struct INTENTRY {
156 /* descriptions of MP basetable entries */
157 typedef struct BASETABLE_ENTRY {
166 vm_size_t mp_cth_mapsz;
169 typedef int (*mptable_iter_func)(void *, const void *, int);
172 * this code MUST be enabled here and in mpboot.s.
173 * it follows the very early stages of AP boot by placing values in CMOS ram.
174 * it NORMALLY will never be needed and thus the primitive method for enabling.
177 #if defined(CHECK_POINTS)
178 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
179 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
181 #define CHECK_INIT(D); \
182 CHECK_WRITE(0x34, (D)); \
183 CHECK_WRITE(0x35, (D)); \
184 CHECK_WRITE(0x36, (D)); \
185 CHECK_WRITE(0x37, (D)); \
186 CHECK_WRITE(0x38, (D)); \
187 CHECK_WRITE(0x39, (D));
189 #define CHECK_PRINT(S); \
190 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
199 #else /* CHECK_POINTS */
201 #define CHECK_INIT(D)
202 #define CHECK_PRINT(S)
204 #endif /* CHECK_POINTS */
207 * Values to send to the POST hardware.
209 #define MP_BOOTADDRESS_POST 0x10
210 #define MP_PROBE_POST 0x11
211 #define MPTABLE_PASS1_POST 0x12
213 #define MP_START_POST 0x13
214 #define MP_ENABLE_POST 0x14
215 #define MPTABLE_PASS2_POST 0x15
217 #define START_ALL_APS_POST 0x16
218 #define INSTALL_AP_TRAMP_POST 0x17
219 #define START_AP_POST 0x18
221 #define MP_ANNOUNCE_POST 0x19
223 static int madt_probe_test;
224 TUNABLE_INT("hw.madt_probe_test", &madt_probe_test);
226 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
227 int current_postcode;
229 /** XXX FIXME: what system files declare these??? */
230 extern struct region_descriptor r_gdt, r_idt;
232 int mp_naps; /* # of Applications processors */
234 static int mp_nbusses; /* # of busses */
235 int mp_napics; /* # of IO APICs */
237 static vm_offset_t cpu_apic_address;
239 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
240 u_int32_t *io_apic_versions;
244 u_int32_t cpu_apic_versions[MAXCPU];
246 extern int64_t tsc_offsets[];
248 extern u_long ebda_addr;
251 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
255 * APIC ID logical/physical mapping structures.
256 * We oversize these to simplify boot-time config.
258 int cpu_num_to_apic_id[NAPICID];
260 int io_num_to_apic_id[NAPICID];
262 int apic_id_to_logical[NAPICID];
264 /* AP uses this during bootstrap. Do not staticize. */
269 * SMP page table page. Setup by locore to point to a page table
270 * page from which we allocate per-cpu privatespace areas io_apics,
274 #define IO_MAPPING_START_INDEX \
275 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
277 extern pt_entry_t *SMPpt;
279 struct pcb stoppcbs[MAXCPU];
281 extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
283 static basetable_entry basetable_entry_types[] =
285 {0, 20, "Processor"},
293 * Local data and functions.
296 static u_int boot_address;
297 static u_int base_memory;
298 static int mp_finish;
300 static void mp_enable(u_int boot_addr);
302 static int mptable_iterate_entries(const mpcth_t,
303 mptable_iter_func, void *);
304 static int mptable_probe(void);
305 static int mptable_check(vm_paddr_t);
306 static long mptable_search_sig(u_int32_t target, int count);
307 static int mptable_hyperthread_fixup(u_int, int);
308 static void mptable_pass1(struct mptable_pos *);
309 static int mptable_pass2(struct mptable_pos *);
310 static void mptable_default(int type);
311 static void mptable_fix(void);
312 static int mptable_map(struct mptable_pos *, vm_paddr_t);
313 static void mptable_unmap(struct mptable_pos *);
314 static void mptable_lapic_enumerate(struct mptable_pos *);
315 static void mptable_lapic_default(void);
318 static void setup_apic_irq_mapping(void);
319 static int apic_int_is_bus_type(int intr, int bus_type);
321 static int start_all_aps(u_int boot_addr);
323 static void install_ap_tramp(u_int boot_addr);
325 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
326 static void lapic_init(vm_offset_t);
327 static int smitest(void);
329 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
330 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
331 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
332 static u_int bootMP_size;
335 * Calculate usable address in base memory for AP trampoline code.
338 mp_bootaddress(u_int basemem)
340 POSTCODE(MP_BOOTADDRESS_POST);
342 base_memory = basemem;
344 bootMP_size = mptramp_end - mptramp_start;
345 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */
346 if (((basemem * 1024) - boot_address) < bootMP_size)
347 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
348 /* 3 levels of page table pages */
349 mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
351 return mptramp_pagetables;
356 * Look for an Intel MP spec table (ie, SMP capable hardware).
365 * Make sure our SMPpt[] page table is big enough to hold all the
368 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
370 POSTCODE(MP_PROBE_POST);
372 /* see if EBDA exists */
373 if (ebda_addr != 0) {
374 /* search first 1K of EBDA */
375 target = (u_int32_t)ebda_addr;
376 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
379 /* last 1K of base memory, effective 'top of base' passed in */
380 target = (u_int32_t)(base_memory - 0x400);
381 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
385 /* search the BIOS */
386 target = (u_int32_t)BIOS_BASE;
387 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
394 struct mptable_check_cbarg {
400 mptable_check_callback(void *xarg, const void *pos, int type)
402 const struct PROCENTRY *ent;
403 struct mptable_check_cbarg *arg = xarg;
409 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
413 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
414 if (arg->found_bsp) {
415 kprintf("more than one BSP in base MP table\n");
424 mptable_check(vm_paddr_t mpfps_paddr)
426 struct mptable_pos mpt;
427 struct mptable_check_cbarg arg;
431 if (mpfps_paddr == 0)
434 error = mptable_map(&mpt, mpfps_paddr);
438 if (mpt.mp_fps->mpfb1 != 0)
446 if (cth->apic_address == 0)
449 bzero(&arg, sizeof(arg));
450 error = mptable_iterate_entries(cth, mptable_check_callback, &arg);
452 if (arg.cpu_count == 0) {
453 kprintf("MP table contains no processor entries\n");
455 } else if (!arg.found_bsp) {
456 kprintf("MP table does not contains BSP entry\n");
466 mptable_iterate_entries(const mpcth_t cth, mptable_iter_func func, void *arg)
468 int count, total_size;
469 const void *position;
471 KKASSERT(cth->base_table_length >= sizeof(struct MPCTH));
472 total_size = cth->base_table_length - sizeof(struct MPCTH);
473 position = (const uint8_t *)cth + sizeof(struct MPCTH);
474 count = cth->entry_count;
479 KKASSERT(total_size >= 0);
480 if (total_size == 0) {
481 kprintf("invalid base MP table, "
482 "entry count and length mismatch\n");
486 type = *(const uint8_t *)position;
488 case 0: /* processor_entry */
489 case 1: /* bus_entry */
490 case 2: /* io_apic_entry */
491 case 3: /* int_entry */
492 case 4: /* int_entry */
495 kprintf("unknown base MP table entry type %d\n", type);
499 if (total_size < basetable_entry_types[type].length) {
500 kprintf("invalid base MP table length, "
501 "does not contain all entries\n");
504 total_size -= basetable_entry_types[type].length;
506 error = func(arg, position, type);
510 position = (const uint8_t *)position +
511 basetable_entry_types[type].length;
518 * Startup the SMP processors.
523 POSTCODE(MP_START_POST);
524 mp_enable(boot_address);
529 * Print various information about the SMP system hardware and setup.
536 POSTCODE(MP_ANNOUNCE_POST);
538 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
539 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
540 kprintf(", version: 0x%08x", cpu_apic_versions[0]);
541 kprintf(", at 0x%08jx\n", (intmax_t)cpu_apic_address);
542 for (x = 1; x <= mp_naps; ++x) {
543 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
544 kprintf(", version: 0x%08x", cpu_apic_versions[x]);
545 kprintf(", at 0x%08jx\n", (intmax_t)cpu_apic_address);
549 for (x = 0; x < mp_napics; ++x) {
550 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
551 kprintf(", version: 0x%08x", io_apic_versions[x]);
552 kprintf(", at 0x%08lx\n", io_apic_address[x]);
555 kprintf(" Warning: APIC I/O disabled\n");
560 * AP cpu's call this to sync up protected mode.
562 * WARNING! %gs is not set up on entry. This routine sets up %gs.
568 int x, myid = bootAP;
570 struct mdglobaldata *md;
571 struct privatespace *ps;
573 ps = &CPU_prvspace[myid];
575 gdt_segs[GPROC0_SEL].ssd_base =
576 (long) &ps->mdglobaldata.gd_common_tss;
577 ps->mdglobaldata.mi.gd_prvspace = ps;
579 /* We fill the 32-bit segment descriptors */
580 for (x = 0; x < NGDT; x++) {
581 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
582 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x]);
584 /* And now a 64-bit one */
585 ssdtosyssd(&gdt_segs[GPROC0_SEL],
586 (struct system_segment_descriptor *)&gdt[myid * NGDT + GPROC0_SEL]);
588 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
589 r_gdt.rd_base = (long) &gdt[myid * NGDT];
590 lgdt(&r_gdt); /* does magic intra-segment return */
592 /* lgdt() destroys the GSBASE value, so we load GSBASE after lgdt() */
593 wrmsr(MSR_FSBASE, 0); /* User value */
594 wrmsr(MSR_GSBASE, (u_int64_t)ps);
595 wrmsr(MSR_KGSBASE, 0); /* XXX User value while we're in the kernel */
601 mdcpu->gd_currentldt = _default_ldt;
604 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
605 gdt[myid * NGDT + GPROC0_SEL].sd_type = SDT_SYSTSS;
607 md = mdcpu; /* loaded through %gs:0 (mdglobaldata.mi.gd_prvspace)*/
609 md->gd_common_tss.tss_rsp0 = 0; /* not used until after switch */
611 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
613 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL];
614 md->gd_common_tssd = *md->gd_tss_gdt;
616 md->gd_common_tss.tss_ist1 = (long)&doublefault_stack[PAGE_SIZE];
621 * Set to a known state:
622 * Set by mpboot.s: CR0_PG, CR0_PE
623 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
626 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
629 /* Set up the fast syscall stuff */
630 msr = rdmsr(MSR_EFER) | EFER_SCE;
631 wrmsr(MSR_EFER, msr);
632 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
633 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
634 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
635 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
636 wrmsr(MSR_STAR, msr);
637 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
639 pmap_set_opt(); /* PSE/4MB pages, etc */
641 /* Initialize the PAT MSR. */
645 /* set up CPU registers and state */
648 /* set up SSE/NX registers */
651 /* set up FPU state on the AP */
652 npxinit(__INITIAL_NPXCW__);
654 /* disable the APIC, just to be SURE */
655 lapic->svr &= ~APIC_SVR_ENABLE;
657 /* data returned to BSP */
658 cpu_apic_versions[0] = lapic->version;
661 /*******************************************************************
662 * local functions and data
666 * start the SMP system
669 mp_enable(u_int boot_addr)
676 vm_paddr_t mpfps_paddr;
678 POSTCODE(MP_ENABLE_POST);
680 if (madt_probe_test) {
683 mpfps_paddr = mptable_probe();
684 if (mptable_check(mpfps_paddr))
689 struct mptable_pos mpt;
691 mptable_map(&mpt, mpfps_paddr);
693 mptable_lapic_enumerate(&mpt);
697 * We can safely map physical memory into SMPpt after
698 * mptable_pass1() completes.
703 * Examine the MP table for needed info
705 x = mptable_pass2(&mpt);
710 * Can't process default configs till the
711 * CPU APIC is pmapped
716 /* post scan cleanup */
720 vm_paddr_t madt_paddr;
721 vm_offset_t lapic_addr;
724 madt_paddr = madt_probe();
726 panic("mp_enable: madt_probe failed\n");
728 lapic_addr = madt_pass1(madt_paddr);
730 panic("mp_enable: no local apic (madt)!\n");
732 lapic_init(lapic_addr);
734 bsp_apic_id = APIC_ID(lapic->id);
735 if (madt_pass2(madt_paddr, bsp_apic_id))
736 panic("mp_enable: madt_pass2 failed\n");
741 setup_apic_irq_mapping();
743 /* fill the LOGICAL io_apic_versions table */
744 for (apic = 0; apic < mp_napics; ++apic) {
745 ux = io_apic_read(apic, IOAPIC_VER);
746 io_apic_versions[apic] = ux;
747 io_apic_set_id(apic, IO_TO_ID(apic));
750 /* program each IO APIC in the system */
751 for (apic = 0; apic < mp_napics; ++apic)
752 if (io_apic_setup(apic) < 0)
753 panic("IO APIC setup failure");
758 * These are required for SMP operation
761 /* install a 'Spurious INTerrupt' vector */
762 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
763 SDT_SYSIGT, SEL_KPL, 0);
765 /* install an inter-CPU IPI for TLB invalidation */
766 setidt(XINVLTLB_OFFSET, Xinvltlb,
767 SDT_SYSIGT, SEL_KPL, 0);
769 /* install an inter-CPU IPI for IPIQ messaging */
770 setidt(XIPIQ_OFFSET, Xipiq,
771 SDT_SYSIGT, SEL_KPL, 0);
773 /* install a timer vector */
774 setidt(XTIMER_OFFSET, Xtimer,
775 SDT_SYSIGT, SEL_KPL, 0);
777 /* install an inter-CPU IPI for CPU stop/restart */
778 setidt(XCPUSTOP_OFFSET, Xcpustop,
779 SDT_SYSIGT, SEL_KPL, 0);
781 /* start each Application Processor */
782 start_all_aps(boot_addr);
787 * look for the MP spec signature
790 /* string defined by the Intel MP Spec as identifying the MP table */
791 #define MP_SIG 0x5f504d5f /* _MP_ */
792 #define NEXT(X) ((X) += 4)
794 mptable_search_sig(u_int32_t target, int count)
800 KKASSERT(target != 0);
802 map_size = count * sizeof(u_int32_t);
803 addr = pmap_mapdev((vm_paddr_t)target, map_size);
806 for (x = 0; x < count; NEXT(x)) {
807 if (addr[x] == MP_SIG) {
808 /* make array index a byte index */
809 ret = target + (x * sizeof(u_int32_t));
814 pmap_unmapdev((vm_offset_t)addr, map_size);
819 typedef struct BUSDATA {
821 enum busTypes bus_type;
824 typedef struct INTDATA {
834 typedef struct BUSTYPENAME {
841 static bus_type_name bus_type_table[] =
847 {UNKNOWN_BUSTYPE, "---"},
850 {UNKNOWN_BUSTYPE, "---"},
851 {UNKNOWN_BUSTYPE, "---"},
852 {UNKNOWN_BUSTYPE, "---"},
853 {UNKNOWN_BUSTYPE, "---"},
854 {UNKNOWN_BUSTYPE, "---"},
856 {UNKNOWN_BUSTYPE, "---"},
857 {UNKNOWN_BUSTYPE, "---"},
858 {UNKNOWN_BUSTYPE, "---"},
859 {UNKNOWN_BUSTYPE, "---"},
861 {UNKNOWN_BUSTYPE, "---"}
864 /* from MP spec v1.4, table 5-1 */
865 static int default_data[7][5] =
867 /* nbus, id0, type0, id1, type1 */
868 {1, 0, ISA, 255, 255},
869 {1, 0, EISA, 255, 255},
870 {1, 0, EISA, 255, 255},
871 {1, 0, MCA, 255, 255},
873 {2, 0, EISA, 1, PCI},
878 static bus_datum *bus_data;
880 /* the IO INT data, one entry per possible APIC INTerrupt */
881 static io_int *io_apic_ints;
886 static int processor_entry (const struct PROCENTRY *entry, int cpu);
888 static int bus_entry (bus_entry_ptr entry, int bus);
889 static int io_apic_entry (io_apic_entry_ptr entry, int apic);
890 static int int_entry (int_entry_ptr entry, int intr);
891 static int lookup_bus_type (char *name);
896 * 1st pass on motherboard's Intel MP specification table.
905 mptable_pass1(struct mptable_pos *mpt)
917 POSTCODE(MPTABLE_PASS1_POST);
920 KKASSERT(fps != NULL);
923 /* clear various tables */
924 for (x = 0; x < NAPICID; ++x) {
925 io_apic_address[x] = ~0; /* IO APIC address table */
935 /* check for use of 'default' configuration */
936 if (fps->mpfb1 != 0) {
938 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
939 mp_nbusses = default_data[fps->mpfb1 - 1][0];
946 KKASSERT(cth != NULL);
948 /* walk the table, recording info of interest */
949 totalSize = cth->base_table_length - sizeof(struct MPCTH);
950 position = (u_char *) cth + sizeof(struct MPCTH);
951 count = cth->entry_count;
954 switch (type = *(u_char *) position) {
955 case 0: /* processor_entry */
957 case 1: /* bus_entry */
962 case 2: /* io_apic_entry */
964 if (((io_apic_entry_ptr)position)->apic_flags
965 & IOAPICENTRY_FLAG_EN)
966 io_apic_address[mp_napics++] =
967 (vm_offset_t)((io_apic_entry_ptr)
968 position)->apic_address;
971 case 3: /* int_entry */
976 case 4: /* int_entry */
979 panic("mpfps Base Table HOSED!");
983 totalSize -= basetable_entry_types[type].length;
984 position = (uint8_t *)position +
985 basetable_entry_types[type].length;
992 * 2nd pass on motherboard's Intel MP specification table.
995 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
996 * IO_TO_ID(N), logical IO to APIC ID table
1001 mptable_pass2(struct mptable_pos *mpt)
1010 int apic, bus, intr;
1015 POSTCODE(MPTABLE_PASS2_POST);
1018 KKASSERT(fps != NULL);
1021 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
1022 M_DEVBUF, M_WAITOK);
1023 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
1024 M_DEVBUF, M_WAITOK | M_ZERO);
1025 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
1026 M_DEVBUF, M_WAITOK);
1027 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
1028 M_DEVBUF, M_WAITOK);
1032 for (i = 0; i < mp_napics; i++) {
1033 ioapic[i] = permanent_io_mapping(io_apic_address[i]);
1037 /* clear various tables */
1038 for (x = 0; x < NAPICID; ++x) {
1040 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
1041 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
1046 /* clear bus data table */
1047 for (x = 0; x < mp_nbusses; ++x)
1048 bus_data[x].bus_id = 0xff;
1050 /* clear IO APIC INT table */
1051 for (x = 0; x < (nintrs + 1); ++x) {
1052 io_apic_ints[x].int_type = 0xff;
1053 io_apic_ints[x].int_vector = 0xff;
1057 /* record whether PIC or virtual-wire mode */
1058 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT, fps->mpfb2 & 0x80);
1060 /* check for use of 'default' configuration */
1061 if (fps->mpfb1 != 0)
1062 return fps->mpfb1; /* return default configuration type */
1065 KKASSERT(cth != NULL);
1067 /* walk the table, recording info of interest */
1068 totalSize = cth->base_table_length - sizeof(struct MPCTH);
1069 position = (u_char *) cth + sizeof(struct MPCTH);
1070 count = cth->entry_count;
1071 apic = bus = intr = 0;
1074 switch (type = *(u_char *) position) {
1079 if (bus_entry(position, bus))
1085 if (io_apic_entry(position, apic))
1091 if (int_entry(position, intr))
1096 /* int_entry(position); */
1099 panic("mpfps Base Table HOSED!");
1103 totalSize -= basetable_entry_types[type].length;
1104 position = (uint8_t *)position + basetable_entry_types[type].length;
1107 /* report fact that its NOT a default configuration */
1113 * Check if we should perform a hyperthreading "fix-up" to
1114 * enumerate any logical CPU's that aren't already listed
1117 * XXX: We assume that all of the physical CPUs in the
1118 * system have the same number of logical CPUs.
1120 * XXX: We assume that APIC ID's are allocated such that
1121 * the APIC ID's for a physical processor are aligned
1122 * with the number of logical CPU's in the processor.
1125 mptable_hyperthread_fixup(u_int id_mask, int cpu_count)
1127 int i, id, lcpus_max, logical_cpus;
1129 if ((cpu_feature & CPUID_HTT) == 0)
1132 lcpus_max = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1136 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
1138 * INSTRUCTION SET REFERENCE, A-M (#253666)
1139 * Page 3-181, Table 3-20
1140 * "The nearest power-of-2 integer that is not smaller
1141 * than EBX[23:16] is the number of unique initial APIC
1142 * IDs reserved for addressing different logical
1143 * processors in a physical package."
1145 for (i = 0; ; ++i) {
1146 if ((1 << i) >= lcpus_max) {
1153 KKASSERT(cpu_count != 0);
1154 if (cpu_count == lcpus_max) {
1155 /* We have nothing to fix */
1157 } else if (cpu_count == 1) {
1158 /* XXX this may be incorrect */
1159 logical_cpus = lcpus_max;
1161 int cur, prev, dist;
1164 * Calculate the distances between two nearest
1165 * APIC IDs. If all such distances are same,
1166 * then it is the number of missing cpus that
1167 * we are going to fill later.
1169 dist = cur = prev = -1;
1170 for (id = 0; id < MAXCPU; ++id) {
1171 if ((id_mask & 1 << id) == 0)
1176 int new_dist = cur - prev;
1182 * Make sure that all distances
1183 * between two nearest APIC IDs
1186 if (dist != new_dist)
1194 /* Must be power of 2 */
1195 if (dist & (dist - 1))
1198 /* Can't exceed CPU package capacity */
1199 if (dist > lcpus_max)
1200 logical_cpus = lcpus_max;
1202 logical_cpus = dist;
1206 * For each APIC ID of a CPU that is set in the mask,
1207 * scan the other candidate APIC ID's for this
1208 * physical processor. If any of those ID's are
1209 * already in the table, then kill the fixup.
1211 for (id = 0; id < MAXCPU; id++) {
1212 if ((id_mask & 1 << id) == 0)
1214 /* First, make sure we are on a logical_cpus boundary. */
1215 if (id % logical_cpus != 0)
1217 for (i = id + 1; i < id + logical_cpus; i++)
1218 if ((id_mask & 1 << i) != 0)
1221 return logical_cpus;
1225 mptable_map(struct mptable_pos *mpt, vm_paddr_t mpfps_paddr)
1229 vm_size_t cth_mapsz = 0;
1231 bzero(mpt, sizeof(*mpt));
1233 fps = pmap_mapdev(mpfps_paddr, sizeof(*fps));
1234 if (fps->pap != 0) {
1236 * Map configuration table header to get
1237 * the base table size
1239 cth = pmap_mapdev(fps->pap, sizeof(*cth));
1240 cth_mapsz = cth->base_table_length;
1241 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
1243 if (cth_mapsz < sizeof(*cth)) {
1244 kprintf("invalid base MP table length %d\n",
1246 pmap_unmapdev((vm_offset_t)fps, sizeof(*fps));
1251 * Map the base table
1253 cth = pmap_mapdev(fps->pap, cth_mapsz);
1258 mpt->mp_cth_mapsz = cth_mapsz;
1264 mptable_unmap(struct mptable_pos *mpt)
1266 if (mpt->mp_cth != NULL) {
1267 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
1269 mpt->mp_cth_mapsz = 0;
1271 if (mpt->mp_fps != NULL) {
1272 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
1280 assign_apic_irq(int apic, int intpin, int irq)
1284 if (int_to_apicintpin[irq].ioapic != -1)
1285 panic("assign_apic_irq: inconsistent table");
1287 int_to_apicintpin[irq].ioapic = apic;
1288 int_to_apicintpin[irq].int_pin = intpin;
1289 int_to_apicintpin[irq].apic_address = ioapic[apic];
1290 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1292 for (x = 0; x < nintrs; x++) {
1293 if ((io_apic_ints[x].int_type == 0 ||
1294 io_apic_ints[x].int_type == 3) &&
1295 io_apic_ints[x].int_vector == 0xff &&
1296 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1297 io_apic_ints[x].dst_apic_int == intpin)
1298 io_apic_ints[x].int_vector = irq;
1303 revoke_apic_irq(int irq)
1309 if (int_to_apicintpin[irq].ioapic == -1)
1310 panic("revoke_apic_irq: inconsistent table");
1312 oldapic = int_to_apicintpin[irq].ioapic;
1313 oldintpin = int_to_apicintpin[irq].int_pin;
1315 int_to_apicintpin[irq].ioapic = -1;
1316 int_to_apicintpin[irq].int_pin = 0;
1317 int_to_apicintpin[irq].apic_address = NULL;
1318 int_to_apicintpin[irq].redirindex = 0;
1320 for (x = 0; x < nintrs; x++) {
1321 if ((io_apic_ints[x].int_type == 0 ||
1322 io_apic_ints[x].int_type == 3) &&
1323 io_apic_ints[x].int_vector != 0xff &&
1324 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1325 io_apic_ints[x].dst_apic_int == oldintpin)
1326 io_apic_ints[x].int_vector = 0xff;
1334 allocate_apic_irq(int intr)
1340 if (io_apic_ints[intr].int_vector != 0xff)
1341 return; /* Interrupt handler already assigned */
1343 if (io_apic_ints[intr].int_type != 0 &&
1344 (io_apic_ints[intr].int_type != 3 ||
1345 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1346 io_apic_ints[intr].dst_apic_int == 0)))
1347 return; /* Not INT or ExtInt on != (0, 0) */
1350 while (irq < APIC_INTMAPSIZE &&
1351 int_to_apicintpin[irq].ioapic != -1)
1354 if (irq >= APIC_INTMAPSIZE)
1355 return; /* No free interrupt handlers */
1357 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1358 intpin = io_apic_ints[intr].dst_apic_int;
1360 assign_apic_irq(apic, intpin, irq);
1365 swap_apic_id(int apic, int oldid, int newid)
1372 return; /* Nothing to do */
1374 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1375 apic, oldid, newid);
1377 /* Swap physical APIC IDs in interrupt entries */
1378 for (x = 0; x < nintrs; x++) {
1379 if (io_apic_ints[x].dst_apic_id == oldid)
1380 io_apic_ints[x].dst_apic_id = newid;
1381 else if (io_apic_ints[x].dst_apic_id == newid)
1382 io_apic_ints[x].dst_apic_id = oldid;
1385 /* Swap physical APIC IDs in IO_TO_ID mappings */
1386 for (oapic = 0; oapic < mp_napics; oapic++)
1387 if (IO_TO_ID(oapic) == newid)
1390 if (oapic < mp_napics) {
1391 kprintf("Changing APIC ID for IO APIC #%d from "
1392 "%d to %d in MP table\n",
1393 oapic, newid, oldid);
1394 IO_TO_ID(oapic) = oldid;
1396 IO_TO_ID(apic) = newid;
1401 fix_id_to_io_mapping(void)
1405 for (x = 0; x < NAPICID; x++)
1408 for (x = 0; x <= mp_naps; x++)
1409 if (CPU_TO_ID(x) < NAPICID)
1410 ID_TO_IO(CPU_TO_ID(x)) = x;
1412 for (x = 0; x < mp_napics; x++)
1413 if (IO_TO_ID(x) < NAPICID)
1414 ID_TO_IO(IO_TO_ID(x)) = x;
1419 first_free_apic_id(void)
1423 for (freeid = 0; freeid < NAPICID; freeid++) {
1424 for (x = 0; x <= mp_naps; x++)
1425 if (CPU_TO_ID(x) == freeid)
1429 for (x = 0; x < mp_napics; x++)
1430 if (IO_TO_ID(x) == freeid)
1441 io_apic_id_acceptable(int apic, int id)
1443 int cpu; /* Logical CPU number */
1444 int oapic; /* Logical IO APIC number for other IO APIC */
1447 return 0; /* Out of range */
1449 for (cpu = 0; cpu <= mp_naps; cpu++)
1450 if (CPU_TO_ID(cpu) == id)
1451 return 0; /* Conflict with CPU */
1453 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1454 if (IO_TO_ID(oapic) == id)
1455 return 0; /* Conflict with other APIC */
1457 return 1; /* ID is acceptable for IO APIC */
1462 io_apic_find_int_entry(int apic, int pin)
1466 /* search each of the possible INTerrupt sources */
1467 for (x = 0; x < nintrs; ++x) {
1468 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1469 (pin == io_apic_ints[x].dst_apic_int))
1470 return (&io_apic_ints[x]);
1478 * parse an Intel MP specification table
1486 int apic; /* IO APIC unit number */
1487 int freeid; /* Free physical APIC ID */
1488 int physid; /* Current physical IO APIC ID */
1490 int bus_0 = 0; /* Stop GCC warning */
1491 int bus_pci = 0; /* Stop GCC warning */
1495 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1496 * did it wrong. The MP spec says that when more than 1 PCI bus
1497 * exists the BIOS must begin with bus entries for the PCI bus and use
1498 * actual PCI bus numbering. This implies that when only 1 PCI bus
1499 * exists the BIOS can choose to ignore this ordering, and indeed many
1500 * MP motherboards do ignore it. This causes a problem when the PCI
1501 * sub-system makes requests of the MP sub-system based on PCI bus
1502 * numbers. So here we look for the situation and renumber the
1503 * busses and associated INTs in an effort to "make it right".
1506 /* find bus 0, PCI bus, count the number of PCI busses */
1507 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1508 if (bus_data[x].bus_id == 0) {
1511 if (bus_data[x].bus_type == PCI) {
1517 * bus_0 == slot of bus with ID of 0
1518 * bus_pci == slot of last PCI bus encountered
1521 /* check the 1 PCI bus case for sanity */
1522 /* if it is number 0 all is well */
1523 if (num_pci_bus == 1 &&
1524 bus_data[bus_pci].bus_id != 0) {
1526 /* mis-numbered, swap with whichever bus uses slot 0 */
1528 /* swap the bus entry types */
1529 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1530 bus_data[bus_0].bus_type = PCI;
1532 /* swap each relavant INTerrupt entry */
1533 id = bus_data[bus_pci].bus_id;
1534 for (x = 0; x < nintrs; ++x) {
1535 if (io_apic_ints[x].src_bus_id == id) {
1536 io_apic_ints[x].src_bus_id = 0;
1538 else if (io_apic_ints[x].src_bus_id == 0) {
1539 io_apic_ints[x].src_bus_id = id;
1544 /* Assign IO APIC IDs.
1546 * First try the existing ID. If a conflict is detected, try
1547 * the ID in the MP table. If a conflict is still detected, find
1550 * We cannot use the ID_TO_IO table before all conflicts has been
1551 * resolved and the table has been corrected.
1553 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1555 /* First try to use the value set by the BIOS */
1556 physid = io_apic_get_id(apic);
1557 if (io_apic_id_acceptable(apic, physid)) {
1558 if (IO_TO_ID(apic) != physid)
1559 swap_apic_id(apic, IO_TO_ID(apic), physid);
1563 /* Then check if the value in the MP table is acceptable */
1564 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1567 /* Last resort, find a free APIC ID and use it */
1568 freeid = first_free_apic_id();
1569 if (freeid >= NAPICID)
1570 panic("No free physical APIC IDs found");
1572 if (io_apic_id_acceptable(apic, freeid)) {
1573 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1576 panic("Free physical APIC ID not usable");
1578 fix_id_to_io_mapping();
1580 /* detect and fix broken Compaq MP table */
1581 if (apic_int_type(0, 0) == -1) {
1582 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1583 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1584 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1585 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1586 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1587 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1589 } else if (apic_int_type(0, 0) == 0) {
1590 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1591 for (x = 0; x < nintrs; ++x)
1592 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1593 (0 == io_apic_ints[x].dst_apic_int)) {
1594 io_apic_ints[x].int_type = 3;
1595 io_apic_ints[x].int_vector = 0xff;
1601 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1602 * controllers universally come in pairs. If IRQ 14 is specified
1603 * as an ISA interrupt, then IRQ 15 had better be too.
1605 * [ Shuttle XPC / AMD Athlon X2 ]
1606 * The MPTable is missing an entry for IRQ 15. Note that the
1607 * ACPI table has an entry for both 14 and 15.
1609 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1610 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1611 io14 = io_apic_find_int_entry(0, 14);
1612 io_apic_ints[nintrs] = *io14;
1613 io_apic_ints[nintrs].src_bus_irq = 15;
1614 io_apic_ints[nintrs].dst_apic_int = 15;
1622 /* Assign low level interrupt handlers */
1624 setup_apic_irq_mapping(void)
1630 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1631 int_to_apicintpin[x].ioapic = -1;
1632 int_to_apicintpin[x].int_pin = 0;
1633 int_to_apicintpin[x].apic_address = NULL;
1634 int_to_apicintpin[x].redirindex = 0;
1637 /* First assign ISA/EISA interrupts */
1638 for (x = 0; x < nintrs; x++) {
1639 int_vector = io_apic_ints[x].src_bus_irq;
1640 if (int_vector < APIC_INTMAPSIZE &&
1641 io_apic_ints[x].int_vector == 0xff &&
1642 int_to_apicintpin[int_vector].ioapic == -1 &&
1643 (apic_int_is_bus_type(x, ISA) ||
1644 apic_int_is_bus_type(x, EISA)) &&
1645 io_apic_ints[x].int_type == 0) {
1646 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1647 io_apic_ints[x].dst_apic_int,
1652 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1653 for (x = 0; x < nintrs; x++) {
1654 if (io_apic_ints[x].dst_apic_int == 0 &&
1655 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1656 io_apic_ints[x].int_vector == 0xff &&
1657 int_to_apicintpin[0].ioapic == -1 &&
1658 io_apic_ints[x].int_type == 3) {
1659 assign_apic_irq(0, 0, 0);
1664 /* Assign PCI interrupts */
1665 for (x = 0; x < nintrs; ++x) {
1666 if (io_apic_ints[x].int_type == 0 &&
1667 io_apic_ints[x].int_vector == 0xff &&
1668 apic_int_is_bus_type(x, PCI))
1669 allocate_apic_irq(x);
1676 mp_set_cpuids(int cpu_id, int apic_id)
1678 CPU_TO_ID(cpu_id) = apic_id;
1679 ID_TO_CPU(apic_id) = cpu_id;
1683 processor_entry(const struct PROCENTRY *entry, int cpu)
1687 /* check for usability */
1688 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1691 /* check for BSP flag */
1692 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1693 mp_set_cpuids(0, entry->apic_id);
1694 return 0; /* its already been counted */
1697 /* add another AP to list, if less than max number of CPUs */
1698 else if (cpu < MAXCPU) {
1699 mp_set_cpuids(cpu, entry->apic_id);
1709 bus_entry(bus_entry_ptr entry, int bus)
1714 /* encode the name into an index */
1715 for (x = 0; x < 6; ++x) {
1716 if ((c = entry->bus_type[x]) == ' ')
1722 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1723 panic("unknown bus type: '%s'", name);
1725 bus_data[bus].bus_id = entry->bus_id;
1726 bus_data[bus].bus_type = x;
1732 io_apic_entry(io_apic_entry_ptr entry, int apic)
1734 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1737 IO_TO_ID(apic) = entry->apic_id;
1738 ID_TO_IO(entry->apic_id) = apic;
1744 lookup_bus_type(char *name)
1748 for (x = 0; x < MAX_BUSTYPE; ++x)
1749 if (strcmp(bus_type_table[x].name, name) == 0)
1750 return bus_type_table[x].type;
1752 return UNKNOWN_BUSTYPE;
1756 int_entry(int_entry_ptr entry, int intr)
1760 io_apic_ints[intr].int_type = entry->int_type;
1761 io_apic_ints[intr].int_flags = entry->int_flags;
1762 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1763 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1764 if (entry->dst_apic_id == 255) {
1765 /* This signal goes to all IO APICS. Select an IO APIC
1766 with sufficient number of interrupt pins */
1767 for (apic = 0; apic < mp_napics; apic++)
1768 if (((io_apic_read(apic, IOAPIC_VER) &
1769 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1770 entry->dst_apic_int)
1772 if (apic < mp_napics)
1773 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1775 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1777 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1778 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1784 apic_int_is_bus_type(int intr, int bus_type)
1788 for (bus = 0; bus < mp_nbusses; ++bus)
1789 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1790 && ((int) bus_data[bus].bus_type == bus_type))
1797 * Given a traditional ISA INT mask, return an APIC mask.
1800 isa_apic_mask(u_int isa_mask)
1805 #if defined(SKIP_IRQ15_REDIRECT)
1806 if (isa_mask == (1 << 15)) {
1807 kprintf("skipping ISA IRQ15 redirect\n");
1810 #endif /* SKIP_IRQ15_REDIRECT */
1812 isa_irq = ffs(isa_mask); /* find its bit position */
1813 if (isa_irq == 0) /* doesn't exist */
1815 --isa_irq; /* make it zero based */
1817 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1821 return (1 << apic_pin); /* convert pin# to a mask */
1825 * Determine which APIC pin an ISA/EISA INT is attached to.
1827 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1828 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1829 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1830 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1832 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1834 isa_apic_irq(int isa_irq)
1838 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1839 if (INTTYPE(intr) == 0) { /* standard INT */
1840 if (SRCBUSIRQ(intr) == isa_irq) {
1841 if (apic_int_is_bus_type(intr, ISA) ||
1842 apic_int_is_bus_type(intr, EISA)) {
1843 if (INTIRQ(intr) == 0xff)
1844 return -1; /* unassigned */
1845 return INTIRQ(intr); /* found */
1850 return -1; /* NOT found */
1855 * Determine which APIC pin a PCI INT is attached to.
1857 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1858 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1859 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1861 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1865 --pciInt; /* zero based */
1867 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1868 if ((INTTYPE(intr) == 0) /* standard INT */
1869 && (SRCBUSID(intr) == pciBus)
1870 && (SRCBUSDEVICE(intr) == pciDevice)
1871 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1872 if (apic_int_is_bus_type(intr, PCI)) {
1873 if (INTIRQ(intr) == 0xff) {
1874 kprintf("IOAPIC: pci_apic_irq() "
1876 return -1; /* unassigned */
1878 return INTIRQ(intr); /* exact match */
1883 return -1; /* NOT found */
1887 next_apic_irq(int irq)
1894 for (intr = 0; intr < nintrs; intr++) {
1895 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1897 bus = SRCBUSID(intr);
1898 bustype = apic_bus_type(bus);
1899 if (bustype != ISA &&
1905 if (intr >= nintrs) {
1908 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1909 if (INTTYPE(ointr) != 0)
1911 if (bus != SRCBUSID(ointr))
1913 if (bustype == PCI) {
1914 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1916 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1919 if (bustype == ISA || bustype == EISA) {
1920 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1923 if (INTPIN(intr) == INTPIN(ointr))
1927 if (ointr >= nintrs) {
1930 return INTIRQ(ointr);
1945 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1948 * Exactly what this means is unclear at this point. It is a solution
1949 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1950 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1951 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1955 undirect_isa_irq(int rirq)
1959 kprintf("Freeing redirected ISA irq %d.\n", rirq);
1960 /** FIXME: tickle the MB redirector chip */
1964 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1971 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1974 undirect_pci_irq(int rirq)
1978 kprintf("Freeing redirected PCI irq %d.\n", rirq);
1980 /** FIXME: tickle the MB redirector chip */
1984 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1994 * given a bus ID, return:
1995 * the bus type if found
1999 apic_bus_type(int id)
2003 for (x = 0; x < mp_nbusses; ++x)
2004 if (bus_data[x].bus_id == id)
2005 return bus_data[x].bus_type;
2011 * given a LOGICAL APIC# and pin#, return:
2012 * the associated src bus ID if found
2016 apic_src_bus_id(int apic, int pin)
2020 /* search each of the possible INTerrupt sources */
2021 for (x = 0; x < nintrs; ++x)
2022 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2023 (pin == io_apic_ints[x].dst_apic_int))
2024 return (io_apic_ints[x].src_bus_id);
2026 return -1; /* NOT found */
2030 * given a LOGICAL APIC# and pin#, return:
2031 * the associated src bus IRQ if found
2035 apic_src_bus_irq(int apic, int pin)
2039 for (x = 0; x < nintrs; x++)
2040 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2041 (pin == io_apic_ints[x].dst_apic_int))
2042 return (io_apic_ints[x].src_bus_irq);
2044 return -1; /* NOT found */
2049 * given a LOGICAL APIC# and pin#, return:
2050 * the associated INTerrupt type if found
2054 apic_int_type(int apic, int pin)
2058 /* search each of the possible INTerrupt sources */
2059 for (x = 0; x < nintrs; ++x) {
2060 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2061 (pin == io_apic_ints[x].dst_apic_int))
2062 return (io_apic_ints[x].int_type);
2064 return -1; /* NOT found */
2068 * Return the IRQ associated with an APIC pin
2071 apic_irq(int apic, int pin)
2076 for (x = 0; x < nintrs; ++x) {
2077 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2078 (pin == io_apic_ints[x].dst_apic_int)) {
2079 res = io_apic_ints[x].int_vector;
2082 if (apic != int_to_apicintpin[res].ioapic)
2083 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
2084 if (pin != int_to_apicintpin[res].int_pin)
2085 panic("apic_irq inconsistent table (2)");
2094 * given a LOGICAL APIC# and pin#, return:
2095 * the associated trigger mode if found
2099 apic_trigger(int apic, int pin)
2103 /* search each of the possible INTerrupt sources */
2104 for (x = 0; x < nintrs; ++x)
2105 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2106 (pin == io_apic_ints[x].dst_apic_int))
2107 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
2109 return -1; /* NOT found */
2114 * given a LOGICAL APIC# and pin#, return:
2115 * the associated 'active' level if found
2119 apic_polarity(int apic, int pin)
2123 /* search each of the possible INTerrupt sources */
2124 for (x = 0; x < nintrs; ++x)
2125 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2126 (pin == io_apic_ints[x].dst_apic_int))
2127 return (io_apic_ints[x].int_flags & 0x03);
2129 return -1; /* NOT found */
2135 * set data according to MP defaults
2136 * FIXME: probably not complete yet...
2139 mptable_default(int type)
2141 #if defined(APIC_IO)
2144 #endif /* APIC_IO */
2147 kprintf(" MP default config type: %d\n", type);
2150 kprintf(" bus: ISA, APIC: 82489DX\n");
2153 kprintf(" bus: EISA, APIC: 82489DX\n");
2156 kprintf(" bus: EISA, APIC: 82489DX\n");
2159 kprintf(" bus: MCA, APIC: 82489DX\n");
2162 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
2165 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
2168 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
2171 kprintf(" future type\n");
2177 #if defined(APIC_IO)
2178 /* one and only IO APIC */
2179 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
2182 * sanity check, refer to MP spec section 3.6.6, last paragraph
2183 * necessary as some hardware isn't properly setting up the IO APIC
2185 #if defined(REALLY_ANAL_IOAPICID_VALUE)
2186 if (io_apic_id != 2) {
2188 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
2189 #endif /* REALLY_ANAL_IOAPICID_VALUE */
2190 io_apic_set_id(0, 2);
2193 IO_TO_ID(0) = io_apic_id;
2194 ID_TO_IO(io_apic_id) = 0;
2195 #endif /* APIC_IO */
2197 /* fill out bus entries */
2207 bus_data[0].bus_id = default_data[type - 1][1];
2208 bus_data[0].bus_type = default_data[type - 1][2];
2209 bus_data[1].bus_id = default_data[type - 1][3];
2210 bus_data[1].bus_type = default_data[type - 1][4];
2214 /* case 4: case 7: MCA NOT supported */
2215 default: /* illegal/reserved */
2216 panic("BAD default MP config: %d", type);
2220 #if defined(APIC_IO)
2221 /* general cases from MP v1.4, table 5-2 */
2222 for (pin = 0; pin < 16; ++pin) {
2223 io_apic_ints[pin].int_type = 0;
2224 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2225 io_apic_ints[pin].src_bus_id = 0;
2226 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2227 io_apic_ints[pin].dst_apic_id = io_apic_id;
2228 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2231 /* special cases from MP v1.4, table 5-2 */
2233 io_apic_ints[2].int_type = 0xff; /* N/C */
2234 io_apic_ints[13].int_type = 0xff; /* N/C */
2235 #if !defined(APIC_MIXED_MODE)
2237 panic("sorry, can't support type 2 default yet");
2238 #endif /* APIC_MIXED_MODE */
2241 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2244 io_apic_ints[0].int_type = 0xff; /* N/C */
2246 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2247 #endif /* APIC_IO */
2251 * Map a physical memory address representing I/O into KVA. The I/O
2252 * block is assumed not to cross a page boundary.
2255 permanent_io_mapping(vm_paddr_t pa)
2257 KKASSERT(pa < 0x100000000LL);
2259 return pmap_mapdev_uncacheable(pa, PAGE_SIZE);
2263 * start each AP in our list
2266 start_all_aps(u_int boot_addr)
2268 vm_offset_t va = boot_address + KERNBASE;
2269 u_int64_t *pt4, *pt3, *pt2;
2275 u_char mpbiosreason;
2276 u_long mpbioswarmvec;
2277 struct mdglobaldata *gd;
2278 struct privatespace *ps;
2280 POSTCODE(START_ALL_APS_POST);
2282 /* Initialize BSP's local APIC */
2283 apic_initialize(TRUE);
2285 /* install the AP 1st level boot code */
2286 pmap_kenter(va, boot_address);
2287 cpu_invlpg((void *)va); /* JG XXX */
2288 bcopy(mptramp_start, (void *)va, bootMP_size);
2290 /* Locate the page tables, they'll be below the trampoline */
2291 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
2292 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
2293 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
2295 /* Create the initial 1GB replicated page tables */
2296 for (i = 0; i < 512; i++) {
2297 /* Each slot of the level 4 pages points to the same level 3 page */
2298 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
2299 pt4[i] |= PG_V | PG_RW | PG_U;
2301 /* Each slot of the level 3 pages points to the same level 2 page */
2302 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
2303 pt3[i] |= PG_V | PG_RW | PG_U;
2305 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
2306 pt2[i] = i * (2 * 1024 * 1024);
2307 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
2310 /* save the current value of the warm-start vector */
2311 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
2312 outb(CMOS_REG, BIOS_RESET);
2313 mpbiosreason = inb(CMOS_DATA);
2315 /* setup a vector to our boot code */
2316 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2317 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
2318 outb(CMOS_REG, BIOS_RESET);
2319 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2322 * If we have a TSC we can figure out the SMI interrupt rate.
2323 * The SMI does not necessarily use a constant rate. Spend
2324 * up to 250ms trying to figure it out.
2327 if (cpu_feature & CPUID_TSC) {
2328 set_apic_timer(275000);
2329 smilast = read_apic_timer();
2330 for (x = 0; x < 20 && read_apic_timer(); ++x) {
2331 smicount = smitest();
2332 if (smibest == 0 || smilast - smicount < smibest)
2333 smibest = smilast - smicount;
2336 if (smibest > 250000)
2339 smibest = smibest * (int64_t)1000000 /
2340 get_apic_timer_frequency();
2344 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
2345 1000000 / smibest, smibest);
2348 for (x = 1; x <= mp_naps; ++x) {
2350 /* This is a bit verbose, it will go away soon. */
2352 /* first page of AP's private space */
2353 pg = x * x86_64_btop(sizeof(struct privatespace));
2355 /* allocate new private data page(s) */
2356 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2357 MDGLOBALDATA_BASEALLOC_SIZE);
2359 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2360 bzero(gd, sizeof(*gd));
2361 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2363 /* prime data page for it to use */
2364 mi_gdinit(&gd->mi, x);
2366 gd->gd_CMAP1 = &SMPpt[pg + 0];
2367 gd->gd_CMAP2 = &SMPpt[pg + 1];
2368 gd->gd_CMAP3 = &SMPpt[pg + 2];
2369 gd->gd_PMAP1 = &SMPpt[pg + 3];
2370 gd->gd_CADDR1 = ps->CPAGE1;
2371 gd->gd_CADDR2 = ps->CPAGE2;
2372 gd->gd_CADDR3 = ps->CPAGE3;
2373 gd->gd_PADDR1 = (pt_entry_t *)ps->PPAGE1;
2374 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2375 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2377 /* setup a vector to our boot code */
2378 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2379 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2380 outb(CMOS_REG, BIOS_RESET);
2381 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2384 * Setup the AP boot stack
2386 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2389 /* attempt to start the Application Processor */
2390 CHECK_INIT(99); /* setup checkpoints */
2391 if (!start_ap(gd, boot_addr, smibest)) {
2392 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2393 CHECK_PRINT("trace"); /* show checkpoints */
2394 /* better panic as the AP may be running loose */
2395 kprintf("panic y/n? [y] ");
2396 if (cngetc() != 'n')
2399 CHECK_PRINT("trace"); /* show checkpoints */
2401 /* record its version info */
2402 cpu_apic_versions[x] = cpu_apic_versions[0];
2405 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2408 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2409 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2412 ncpus2_shift = shift;
2413 ncpus2 = 1 << shift;
2414 ncpus2_mask = ncpus2 - 1;
2416 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2417 if ((1 << shift) < ncpus)
2419 ncpus_fit = 1 << shift;
2420 ncpus_fit_mask = ncpus_fit - 1;
2422 /* build our map of 'other' CPUs */
2423 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2424 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2425 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2427 /* fill in our (BSP) APIC version */
2428 cpu_apic_versions[0] = lapic->version;
2430 /* restore the warmstart vector */
2431 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2432 outb(CMOS_REG, BIOS_RESET);
2433 outb(CMOS_DATA, mpbiosreason);
2436 * NOTE! The idlestack for the BSP was setup by locore. Finish
2437 * up, clean out the P==V mapping we did earlier.
2441 /* number of APs actually started */
2447 * load the 1st level AP boot code into base memory.
2450 /* targets for relocation */
2451 extern void bigJump(void);
2452 extern void bootCodeSeg(void);
2453 extern void bootDataSeg(void);
2454 extern void MPentry(void);
2455 extern u_int MP_GDT;
2456 extern u_int mp_gdtbase;
2461 install_ap_tramp(u_int boot_addr)
2464 int size = *(int *) ((u_long) & bootMP_size);
2465 u_char *src = (u_char *) ((u_long) bootMP);
2466 u_char *dst = (u_char *) boot_addr + KERNBASE;
2467 u_int boot_base = (u_int) bootMP;
2472 POSTCODE(INSTALL_AP_TRAMP_POST);
2474 for (x = 0; x < size; ++x)
2478 * modify addresses in code we just moved to basemem. unfortunately we
2479 * need fairly detailed info about mpboot.s for this to work. changes
2480 * to mpboot.s might require changes here.
2483 /* boot code is located in KERNEL space */
2484 dst = (u_char *) boot_addr + KERNBASE;
2486 /* modify the lgdt arg */
2487 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2488 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2490 /* modify the ljmp target for MPentry() */
2491 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2492 *dst32 = ((u_int) MPentry - KERNBASE);
2494 /* modify the target for boot code segment */
2495 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2496 dst8 = (u_int8_t *) (dst16 + 1);
2497 *dst16 = (u_int) boot_addr & 0xffff;
2498 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2500 /* modify the target for boot data segment */
2501 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2502 dst8 = (u_int8_t *) (dst16 + 1);
2503 *dst16 = (u_int) boot_addr & 0xffff;
2504 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2510 * This function starts the AP (application processor) identified
2511 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2512 * to accomplish this. This is necessary because of the nuances
2513 * of the different hardware we might encounter. It ain't pretty,
2514 * but it seems to work.
2516 * NOTE: eventually an AP gets to ap_init(), which is called just
2517 * before the AP goes into the LWKT scheduler's idle loop.
2520 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
2524 u_long icr_lo, icr_hi;
2526 POSTCODE(START_AP_POST);
2528 /* get the PHYSICAL APIC ID# */
2529 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2531 /* calculate the vector */
2532 vector = (boot_addr >> 12) & 0xff;
2534 /* We don't want anything interfering */
2537 /* Make sure the target cpu sees everything */
2541 * Try to detect when a SMI has occurred, wait up to 200ms.
2543 * If a SMI occurs during an AP reset but before we issue
2544 * the STARTUP command, the AP may brick. To work around
2545 * this problem we hold off doing the AP startup until
2546 * after we have detected the SMI. Hopefully another SMI
2547 * will not occur before we finish the AP startup.
2549 * Retries don't seem to help. SMIs have a window of opportunity
2550 * and if USB->legacy keyboard emulation is enabled in the BIOS
2551 * the interrupt rate can be quite high.
2553 * NOTE: Don't worry about the L1 cache load, it might bloat
2554 * ldelta a little but ndelta will be so huge when the SMI
2555 * occurs the detection logic will still work fine.
2558 set_apic_timer(200000);
2563 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2564 * and running the target CPU. OR this INIT IPI might be latched (P5
2565 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2568 * see apic/apicreg.h for icr bit definitions.
2570 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
2574 * Setup the address for the target AP. We can setup
2575 * icr_hi once and then just trigger operations with
2578 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
2579 icr_hi |= (physical_cpu << 24);
2580 icr_lo = lapic->icr_lo & 0xfff00000;
2581 lapic->icr_hi = icr_hi;
2584 * Do an INIT IPI: assert RESET
2586 * Use edge triggered mode to assert INIT
2588 lapic->icr_lo = icr_lo | 0x00004500;
2589 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2593 * The spec calls for a 10ms delay but we may have to use a
2594 * MUCH lower delay to avoid bricking an AP due to a fast SMI
2595 * interrupt. We have other loops here too and dividing by 2
2596 * doesn't seem to be enough even after subtracting 350us,
2597 * so we divide by 4.
2599 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
2600 * interrupt was detected we use the full 10ms.
2604 else if (smibest < 150 * 4 + 350)
2606 else if ((smibest - 350) / 4 < 10000)
2607 u_sleep((smibest - 350) / 4);
2612 * Do an INIT IPI: deassert RESET
2614 * Use level triggered mode to deassert. It is unclear
2615 * why we need to do this.
2617 lapic->icr_lo = icr_lo | 0x00008500;
2618 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2620 u_sleep(150); /* wait 150us */
2623 * Next we do a STARTUP IPI: the previous INIT IPI might still be
2624 * latched, (P5 bug) this 1st STARTUP would then terminate
2625 * immediately, and the previously started INIT IPI would continue. OR
2626 * the previous INIT IPI has already run. and this STARTUP IPI will
2627 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2630 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2631 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2633 u_sleep(200); /* wait ~200uS */
2636 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2637 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2638 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2639 * recognized after hardware RESET or INIT IPI.
2641 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2642 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2645 /* Resume normal operation */
2648 /* wait for it to start, see ap_init() */
2649 set_apic_timer(5000000);/* == 5 seconds */
2650 while (read_apic_timer()) {
2651 if (smp_startup_mask & (1 << gd->mi.gd_cpuid))
2652 return 1; /* return SUCCESS */
2655 return 0; /* return FAILURE */
2670 while (read_apic_timer()) {
2672 for (count = 0; count < 100; ++count)
2673 ntsc = rdtsc(); /* force loop to occur */
2675 ndelta = ntsc - ltsc;
2676 if (ldelta > ndelta)
2678 if (ndelta > ldelta * 2)
2681 ldelta = ntsc - ltsc;
2684 return(read_apic_timer());
2688 * Lazy flush the TLB on all other CPU's. DEPRECATED.
2690 * If for some reason we were unable to start all cpus we cannot safely
2691 * use broadcast IPIs.
2697 if (smp_startup_mask == smp_active_mask) {
2698 all_but_self_ipi(XINVLTLB_OFFSET);
2700 selected_apic_ipi(smp_active_mask, XINVLTLB_OFFSET,
2701 APIC_DELMODE_FIXED);
2707 * When called the executing CPU will send an IPI to all other CPUs
2708 * requesting that they halt execution.
2710 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2712 * - Signals all CPUs in map to stop.
2713 * - Waits for each to stop.
2720 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2721 * from executing at same time.
2724 stop_cpus(u_int map)
2726 map &= smp_active_mask;
2728 /* send the Xcpustop IPI to all CPUs in map */
2729 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2731 while ((stopped_cpus & map) != map)
2739 * Called by a CPU to restart stopped CPUs.
2741 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2743 * - Signals all CPUs in map to restart.
2744 * - Waits for each to restart.
2752 restart_cpus(u_int map)
2754 /* signal other cpus to restart */
2755 started_cpus = map & smp_active_mask;
2757 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2764 * This is called once the mpboot code has gotten us properly relocated
2765 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2766 * and when it returns the scheduler will call the real cpu_idle() main
2767 * loop for the idlethread. Interrupts are disabled on entry and should
2768 * remain disabled at return.
2776 * Adjust smp_startup_mask to signal the BSP that we have started
2777 * up successfully. Note that we do not yet hold the BGL. The BSP
2778 * is waiting for our signal.
2780 * We can't set our bit in smp_active_mask yet because we are holding
2781 * interrupts physically disabled and remote cpus could deadlock
2782 * trying to send us an IPI.
2784 smp_startup_mask |= 1 << mycpu->gd_cpuid;
2788 * Interlock for finalization. Wait until mp_finish is non-zero,
2789 * then get the MP lock.
2791 * Note: We are in a critical section.
2793 * Note: We have to synchronize td_mpcount to our desired MP state
2794 * before calling cpu_try_mplock().
2796 * Note: we are the idle thread, we can only spin.
2798 * Note: The load fence is memory volatile and prevents the compiler
2799 * from improperly caching mp_finish, and the cpu from improperly
2802 while (mp_finish == 0)
2804 ++curthread->td_mpcount;
2805 while (cpu_try_mplock() == 0)
2808 if (cpu_feature & CPUID_TSC) {
2810 * The BSP is constantly updating tsc0_offset, figure out the
2811 * relative difference to synchronize ktrdump.
2813 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2816 /* BSP may have changed PTD while we're waiting for the lock */
2819 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2823 /* Build our map of 'other' CPUs. */
2824 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2826 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
2828 /* A quick check from sanity claus */
2829 apic_id = (apic_id_to_logical[(lapic->id & 0x0f000000) >> 24]);
2830 if (mycpu->gd_cpuid != apic_id) {
2831 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2832 kprintf("SMP: apic_id = %d\n", apic_id);
2834 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2836 panic("cpuid mismatch! boom!!");
2839 /* Initialize AP's local APIC for irq's */
2840 apic_initialize(FALSE);
2842 /* Set memory range attributes for this CPU to match the BSP */
2843 mem_range_AP_init();
2846 * Once we go active we must process any IPIQ messages that may
2847 * have been queued, because no actual IPI will occur until we
2848 * set our bit in the smp_active_mask. If we don't the IPI
2849 * message interlock could be left set which would also prevent
2852 * The idle loop doesn't expect the BGL to be held and while
2853 * lwkt_switch() normally cleans things up this is a special case
2854 * because we returning almost directly into the idle loop.
2856 * The idle thread is never placed on the runq, make sure
2857 * nothing we've done put it there.
2859 KKASSERT(curthread->td_mpcount == 1);
2860 smp_active_mask |= 1 << mycpu->gd_cpuid;
2863 * Enable interrupts here. idle_restore will also do it, but
2864 * doing it here lets us clean up any strays that got posted to
2865 * the CPU during the AP boot while we are still in a critical
2868 __asm __volatile("sti; pause; pause"::);
2869 mdcpu->gd_fpending = 0;
2871 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2872 lwkt_process_ipiq();
2875 * Releasing the mp lock lets the BSP finish up the SMP init
2878 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2882 * Get SMP fully working before we start initializing devices.
2890 kprintf("Finish MP startup\n");
2891 if (cpu_feature & CPUID_TSC)
2892 tsc0_offset = rdtsc();
2895 while (smp_active_mask != smp_startup_mask) {
2897 if (cpu_feature & CPUID_TSC)
2898 tsc0_offset = rdtsc();
2900 while (try_mplock() == 0)
2903 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
2906 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2909 cpu_send_ipiq(int dcpu)
2911 if ((1 << dcpu) & smp_active_mask)
2912 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2915 #if 0 /* single_apic_ipi_passive() not working yet */
2917 * Returns 0 on failure, 1 on success
2920 cpu_send_ipiq_passive(int dcpu)
2923 if ((1 << dcpu) & smp_active_mask) {
2924 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2925 APIC_DELMODE_FIXED);
2931 struct mptable_lapic_cbarg1 {
2934 u_int ht_apicid_mask;
2938 mptable_lapic_pass1_callback(void *xarg, const void *pos, int type)
2940 const struct PROCENTRY *ent;
2941 struct mptable_lapic_cbarg1 *arg = xarg;
2947 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
2951 if (ent->apic_id < 32) {
2952 arg->ht_apicid_mask |= 1 << ent->apic_id;
2953 } else if (arg->ht_fixup) {
2954 kprintf("MPTABLE: lapic id > 32, disable HTT fixup\n");
2960 struct mptable_lapic_cbarg2 {
2967 mptable_lapic_pass2_callback(void *xarg, const void *pos, int type)
2969 const struct PROCENTRY *ent;
2970 struct mptable_lapic_cbarg2 *arg = xarg;
2976 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
2977 KKASSERT(!arg->found_bsp);
2981 if (processor_entry(ent, arg->cpu))
2984 if (arg->logical_cpus) {
2985 struct PROCENTRY proc;
2989 * Create fake mptable processor entries
2990 * and feed them to processor_entry() to
2991 * enumerate the logical CPUs.
2993 bzero(&proc, sizeof(proc));
2995 proc.cpu_flags = PROCENTRY_FLAG_EN;
2996 proc.apic_id = ent->apic_id;
2998 for (i = 1; i < arg->logical_cpus; i++) {
3000 processor_entry(&proc, arg->cpu);
3008 mptable_lapic_default(void)
3010 int ap_apicid, bsp_apicid;
3012 mp_naps = 1; /* exclude BSP */
3014 /* Map local apic before the id field is accessed */
3015 lapic_init(DEFAULT_APIC_BASE);
3017 bsp_apicid = APIC_ID(lapic->id);
3018 ap_apicid = (bsp_apicid == 0) ? 1 : 0;
3021 mp_set_cpuids(0, bsp_apicid);
3022 /* one and only AP */
3023 mp_set_cpuids(1, ap_apicid);
3028 * cpu_apic_address (common to all CPUs)
3030 * ID_TO_CPU(N), APIC ID to logical CPU table
3031 * CPU_TO_ID(N), logical CPU to APIC ID table
3034 mptable_lapic_enumerate(struct mptable_pos *mpt)
3036 struct mptable_lapic_cbarg1 arg1;
3037 struct mptable_lapic_cbarg2 arg2;
3039 int error, logical_cpus = 0;
3040 vm_offset_t lapic_addr;
3042 KKASSERT(mpt->mp_fps != NULL);
3045 * Check for use of 'default' configuration
3047 if (mpt->mp_fps->mpfb1 != 0) {
3048 mptable_lapic_default();
3053 KKASSERT(cth != NULL);
3055 /* Save local apic address */
3056 lapic_addr = (vm_offset_t)cth->apic_address;
3057 KKASSERT(lapic_addr != 0);
3060 * Find out how many CPUs do we have
3062 bzero(&arg1, sizeof(arg1));
3063 arg1.ht_fixup = 1; /* Apply ht fixup by default */
3065 error = mptable_iterate_entries(cth,
3066 mptable_lapic_pass1_callback, &arg1);
3068 panic("mptable_iterate_entries(lapic_pass1) failed\n");
3069 KKASSERT(arg1.cpu_count != 0);
3071 /* See if we need to fixup HT logical CPUs. */
3072 if (arg1.ht_fixup) {
3073 logical_cpus = mptable_hyperthread_fixup(arg1.ht_apicid_mask,
3075 if (logical_cpus != 0)
3076 arg1.cpu_count *= logical_cpus;
3078 mp_naps = arg1.cpu_count;
3080 /* Qualify the numbers again, after possible HT fixup */
3081 if (mp_naps > MAXCPU) {
3082 kprintf("Warning: only using %d of %d available CPUs!\n",
3087 --mp_naps; /* subtract the BSP */
3090 * Link logical CPU id to local apic id
3092 bzero(&arg2, sizeof(arg2));
3094 arg2.logical_cpus = logical_cpus;
3096 error = mptable_iterate_entries(cth,
3097 mptable_lapic_pass2_callback, &arg2);
3099 panic("mptable_iterate_entries(lapic_pass2) failed\n");
3100 KKASSERT(arg2.found_bsp);
3102 /* Map local apic */
3103 lapic_init(lapic_addr);
3107 lapic_init(vm_offset_t lapic_addr)
3110 * lapic not mapped yet (pmap_init is called too late)
3112 lapic = pmap_mapdev_uncacheable(lapic_addr, sizeof(struct LAPIC));
3115 /* Local apic is mapped on last page */
3116 SMPpt[NPTEPG - 1] = (pt_entry_t)(PG_V | PG_RW | PG_N |
3117 pmap_get_pgeflag() | (lapic_addr & PG_FRAME));
3120 /* Just for printing */
3121 cpu_apic_address = lapic_addr;