1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include <linux/async.h>
31 #include <drm/i915_drm.h>
32 #include <drm/drm_legacy.h>
34 #include "intel_drv.h"
35 #include "intel_ringbuffer.h"
36 #include <linux/workqueue.h>
38 extern struct drm_i915_private *i915_mch_dev;
40 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
42 #define BEGIN_LP_RING(n) \
43 intel_ring_begin(LP_RING(dev_priv), (n))
46 intel_ring_emit(LP_RING(dev_priv), x)
48 #define ADVANCE_LP_RING() \
49 __intel_ring_advance(LP_RING(dev_priv))
52 * Lock test for when it's just for synchronization of ring access.
54 * In that case, we don't need to do it when GEM is initialized as nobody else
55 * has access to the ring.
57 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \
58 if (LP_RING(dev->dev_private)->buffer->obj == NULL) \
59 LOCK_TEST_WITH_RETURN(dev, file); \
63 intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg)
65 if (I915_NEED_GFX_HWS(dev_priv->dev))
66 return ioread32(dev_priv->dri1.gfx_hws_cpu_addr + reg);
68 return intel_read_status_page(LP_RING(dev_priv), reg);
71 #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg)
72 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
73 #define I915_BREADCRUMB_INDEX 0x21
75 void i915_update_dri1_breadcrumb(struct drm_device *dev)
77 /* XXX: We don't care about dri1 */
81 static void i915_write_hws_pga(struct drm_device *dev)
83 struct drm_i915_private *dev_priv = dev->dev_private;
86 addr = dev_priv->status_page_dmah->busaddr;
87 if (INTEL_INFO(dev)->gen >= 4)
88 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
89 I915_WRITE(HWS_PGA, addr);
93 * Frees the hardware status page, whether it's a physical address or a virtual
94 * address set up by the X Server.
96 static void i915_free_hws(struct drm_device *dev)
98 struct drm_i915_private *dev_priv = dev->dev_private;
99 struct intel_engine_cs *ring = LP_RING(dev_priv);
101 if (dev_priv->status_page_dmah) {
102 drm_pci_free(dev, dev_priv->status_page_dmah);
103 dev_priv->status_page_dmah = NULL;
106 if (ring->status_page.gfx_addr) {
107 ring->status_page.gfx_addr = 0;
108 #if 0 /* We don't care about dri1 */
109 iounmap(dev_priv->dri1.gfx_hws_cpu_addr);
113 /* Need to rewrite hardware status page */
114 I915_WRITE(HWS_PGA, 0x1ffff000);
117 void i915_kernel_lost_context(struct drm_device *dev)
119 struct drm_i915_private *dev_priv = dev->dev_private;
120 struct drm_i915_private *master_priv = dev_priv;
121 struct intel_engine_cs *ring = LP_RING(dev_priv);
122 struct intel_ringbuffer *ringbuf = ring->buffer;
125 * We should never lose context on the ring with modesetting
126 * as we don't expose it to userspace
128 if (drm_core_check_feature(dev, DRIVER_MODESET))
131 ringbuf->head = I915_READ_HEAD(ring) & HEAD_ADDR;
132 ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
133 ringbuf->space = ringbuf->head - (ringbuf->tail + I915_RING_FREE_SPACE);
134 if (ringbuf->space < 0)
135 ringbuf->space += ringbuf->size;
138 if (!dev->primary->master)
141 master_priv = dev->primary->master->driver_priv;
143 if (ringbuf->head == ringbuf->tail && master_priv->sarea_priv)
144 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
147 static int i915_dma_cleanup(struct drm_device *dev)
149 struct drm_i915_private *dev_priv = dev->dev_private;
152 /* Make sure interrupts are disabled here because the uninstall ioctl
153 * may not have been called from userspace and after dev_private
154 * is freed, it's too late.
156 if (dev->irq_enabled)
157 drm_irq_uninstall(dev);
159 mutex_lock(&dev->struct_mutex);
160 for (i = 0; i < I915_NUM_RINGS; i++)
161 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
162 mutex_unlock(&dev->struct_mutex);
164 /* Clear the HWS virtual address at teardown */
165 if (I915_NEED_GFX_HWS(dev))
171 static int i915_initialize(struct drm_device *dev, drm_i915_init_t *init)
173 struct drm_i915_private *dev_priv = dev->dev_private;
176 dev_priv->sarea = drm_legacy_getsarea(dev);
177 if (!dev_priv->sarea) {
178 DRM_ERROR("can not find sarea!\n");
179 i915_dma_cleanup(dev);
183 dev_priv->sarea_priv = (drm_i915_sarea_t *)
184 ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset);
186 if (init->ring_size != 0) {
187 if (LP_RING(dev_priv)->buffer->obj != NULL) {
188 i915_dma_cleanup(dev);
189 DRM_ERROR("Client tried to initialize ringbuffer in "
194 ret = intel_render_ring_init_dri(dev,
198 i915_dma_cleanup(dev);
203 dev_priv->dri1.cpp = init->cpp;
204 dev_priv->dri1.back_offset = init->back_offset;
205 dev_priv->dri1.front_offset = init->front_offset;
206 dev_priv->dri1.current_page = 0;
207 dev_priv->sarea_priv->pf_current_page = 0;
210 /* Allow hardware batchbuffers unless told otherwise.
212 dev_priv->dri1.allow_batchbuffer = 1;
217 static int i915_dma_resume(struct drm_device *dev)
219 struct drm_i915_private *dev_priv = dev->dev_private;
220 struct intel_engine_cs *ring = LP_RING(dev_priv);
222 DRM_DEBUG_DRIVER("%s\n", __func__);
224 if (ring->buffer->virtual_start == NULL) {
225 DRM_ERROR("can not ioremap virtual address for"
230 /* Program Hardware Status Page */
231 if (!ring->status_page.page_addr) {
232 DRM_ERROR("Can not find hardware status page\n");
235 DRM_DEBUG_DRIVER("hw status page @ %p\n",
236 ring->status_page.page_addr);
237 if (ring->status_page.gfx_addr != 0)
238 intel_ring_setup_status_page(ring);
240 i915_write_hws_pga(dev);
242 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
247 static int i915_dma_init(struct drm_device *dev, void *data,
248 struct drm_file *file_priv)
250 drm_i915_init_t *init = data;
253 if (drm_core_check_feature(dev, DRIVER_MODESET))
256 switch (init->func) {
258 retcode = i915_initialize(dev, init);
260 case I915_CLEANUP_DMA:
261 retcode = i915_dma_cleanup(dev);
263 case I915_RESUME_DMA:
264 retcode = i915_dma_resume(dev);
274 /* Implement basically the same security restrictions as hardware does
275 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
277 * Most of the calculations below involve calculating the size of a
278 * particular instruction. It's important to get the size right as
279 * that tells us where the next instruction to check is. Any illegal
280 * instruction detected will be given a size of zero, which is a
281 * signal to abort the rest of the buffer.
283 static int validate_cmd(int cmd)
285 switch (((cmd >> 29) & 0x7)) {
287 switch ((cmd >> 23) & 0x3f) {
289 return 1; /* MI_NOOP */
291 return 1; /* MI_FLUSH */
293 return 0; /* disallow everything else */
297 return 0; /* reserved */
299 return (cmd & 0xff) + 2; /* 2d commands */
301 if (((cmd >> 24) & 0x1f) <= 0x18)
304 switch ((cmd >> 24) & 0x1f) {
308 switch ((cmd >> 16) & 0xff) {
310 return (cmd & 0x1f) + 2;
312 return (cmd & 0xf) + 2;
314 return (cmd & 0xffff) + 2;
318 return (cmd & 0xffff) + 1;
322 if ((cmd & (1 << 23)) == 0) /* inline vertices */
323 return (cmd & 0x1ffff) + 2;
324 else if (cmd & (1 << 17)) /* indirect random */
325 if ((cmd & 0xffff) == 0)
326 return 0; /* unknown length, too hard */
328 return (((cmd & 0xffff) + 1) / 2) + 1;
330 return 2; /* indirect sequential */
341 static int i915_emit_cmds(struct drm_device *dev, int *buffer, int dwords)
343 struct drm_i915_private *dev_priv = dev->dev_private;
346 if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->buffer->size - 8)
349 for (i = 0; i < dwords;) {
350 int sz = validate_cmd(buffer[i]);
352 if (sz == 0 || i + sz > dwords)
357 ret = BEGIN_LP_RING((dwords+1)&~1);
361 for (i = 0; i < dwords; i++)
372 i915_emit_box(struct drm_device *dev,
373 struct drm_clip_rect *box,
376 struct drm_i915_private *dev_priv = dev->dev_private;
379 if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
380 box->y2 <= 0 || box->x2 <= 0) {
381 DRM_ERROR("Bad box %d,%d..%d,%d\n",
382 box->x1, box->y1, box->x2, box->y2);
386 if (INTEL_INFO(dev)->gen >= 4) {
387 ret = BEGIN_LP_RING(4);
391 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
392 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
393 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
396 ret = BEGIN_LP_RING(6);
400 OUT_RING(GFX_OP_DRAWRECT_INFO);
402 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
403 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
412 /* XXX: Emitting the counter should really be moved to part of the IRQ
413 * emit. For now, do it in both places:
416 static void i915_emit_breadcrumb(struct drm_device *dev)
418 struct drm_i915_private *dev_priv = dev->dev_private;
420 dev_priv->dri1.counter++;
421 if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
422 dev_priv->dri1.counter = 0;
423 if (dev_priv->sarea_priv)
424 dev_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
426 if (BEGIN_LP_RING(4) == 0) {
427 OUT_RING(MI_STORE_DWORD_INDEX);
428 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
429 OUT_RING(dev_priv->dri1.counter);
435 static int i915_dispatch_cmdbuffer(struct drm_device *dev,
436 drm_i915_cmdbuffer_t *cmd,
437 struct drm_clip_rect *cliprects,
440 int nbox = cmd->num_cliprects;
441 int i = 0, count, ret;
444 DRM_ERROR("alignment");
448 i915_kernel_lost_context(dev);
450 count = nbox ? nbox : 1;
452 for (i = 0; i < count; i++) {
454 ret = i915_emit_box(dev, &cliprects[i],
460 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
465 i915_emit_breadcrumb(dev);
469 static int i915_dispatch_batchbuffer(struct drm_device *dev,
470 drm_i915_batchbuffer_t *batch,
471 struct drm_clip_rect *cliprects)
473 struct drm_i915_private *dev_priv = dev->dev_private;
474 int nbox = batch->num_cliprects;
477 if ((batch->start | batch->used) & 0x7) {
478 DRM_ERROR("alignment");
482 i915_kernel_lost_context(dev);
484 count = nbox ? nbox : 1;
485 for (i = 0; i < count; i++) {
487 ret = i915_emit_box(dev, &cliprects[i],
488 batch->DR1, batch->DR4);
493 if (!IS_I830(dev) && !IS_845G(dev)) {
494 ret = BEGIN_LP_RING(2);
498 if (INTEL_INFO(dev)->gen >= 4) {
499 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
500 OUT_RING(batch->start);
502 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
503 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
506 ret = BEGIN_LP_RING(4);
510 OUT_RING(MI_BATCH_BUFFER);
511 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
512 OUT_RING(batch->start + batch->used - 4);
519 if (IS_G4X(dev) || IS_GEN5(dev)) {
520 if (BEGIN_LP_RING(2) == 0) {
521 OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
527 i915_emit_breadcrumb(dev);
531 static int i915_dispatch_flip(struct drm_device *dev)
533 struct drm_i915_private *dev_priv = dev->dev_private;
536 if (!dev_priv->sarea_priv)
539 DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
541 dev_priv->dri1.current_page,
542 dev_priv->sarea_priv->pf_current_page);
544 i915_kernel_lost_context(dev);
546 ret = BEGIN_LP_RING(10);
550 OUT_RING(MI_FLUSH | MI_READ_FLUSH);
553 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
555 if (dev_priv->dri1.current_page == 0) {
556 OUT_RING(dev_priv->dri1.back_offset);
557 dev_priv->dri1.current_page = 1;
559 OUT_RING(dev_priv->dri1.front_offset);
560 dev_priv->dri1.current_page = 0;
564 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
569 dev_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter++;
571 if (BEGIN_LP_RING(4) == 0) {
572 OUT_RING(MI_STORE_DWORD_INDEX);
573 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
574 OUT_RING(dev_priv->dri1.counter);
579 dev_priv->sarea_priv->pf_current_page = dev_priv->dri1.current_page;
583 static int i915_quiescent(struct drm_device *dev)
585 i915_kernel_lost_context(dev);
586 return intel_ring_idle(LP_RING(dev->dev_private));
589 static int i915_flush_ioctl(struct drm_device *dev, void *data,
590 struct drm_file *file_priv)
594 if (drm_core_check_feature(dev, DRIVER_MODESET))
597 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
599 mutex_lock(&dev->struct_mutex);
600 ret = i915_quiescent(dev);
601 mutex_unlock(&dev->struct_mutex);
606 static int i915_batchbuffer(struct drm_device *dev, void *data,
607 struct drm_file *file_priv)
609 struct drm_i915_private *dev_priv = dev->dev_private;
610 drm_i915_sarea_t *sarea_priv;
611 drm_i915_batchbuffer_t *batch = data;
613 struct drm_clip_rect *cliprects = NULL;
615 if (drm_core_check_feature(dev, DRIVER_MODESET))
618 sarea_priv = (drm_i915_sarea_t *) dev_priv->sarea_priv;
620 if (!dev_priv->dri1.allow_batchbuffer) {
621 DRM_ERROR("Batchbuffer ioctl disabled\n");
625 DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
626 batch->start, batch->used, batch->num_cliprects);
628 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
630 if (batch->num_cliprects < 0)
633 if (batch->num_cliprects) {
634 cliprects = kcalloc(batch->num_cliprects,
637 if (cliprects == NULL)
640 ret = copy_from_user(cliprects, batch->cliprects,
641 batch->num_cliprects *
642 sizeof(struct drm_clip_rect));
649 mutex_lock(&dev->struct_mutex);
650 ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
651 mutex_unlock(&dev->struct_mutex);
654 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
662 static int i915_cmdbuffer(struct drm_device *dev, void *data,
663 struct drm_file *file_priv)
665 struct drm_i915_private *dev_priv = dev->dev_private;
666 drm_i915_sarea_t *sarea_priv;
667 drm_i915_cmdbuffer_t *cmdbuf = data;
668 struct drm_clip_rect *cliprects = NULL;
672 DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
673 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
675 if (drm_core_check_feature(dev, DRIVER_MODESET))
678 sarea_priv = (drm_i915_sarea_t *) dev_priv->sarea_priv;
680 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
682 if (cmdbuf->num_cliprects < 0)
685 batch_data = kmalloc(cmdbuf->sz, M_DRM, M_WAITOK);
686 if (batch_data == NULL)
689 ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
692 goto fail_batch_free;
695 if (cmdbuf->num_cliprects) {
696 cliprects = kcalloc(cmdbuf->num_cliprects,
697 sizeof(*cliprects), GFP_KERNEL);
698 if (cliprects == NULL) {
700 goto fail_batch_free;
703 ret = copy_from_user(cliprects, cmdbuf->cliprects,
704 cmdbuf->num_cliprects *
705 sizeof(struct drm_clip_rect));
712 mutex_lock(&dev->struct_mutex);
713 ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
714 mutex_unlock(&dev->struct_mutex);
716 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
721 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
731 static int i915_emit_irq(struct drm_device *dev)
733 struct drm_i915_private *dev_priv = dev->dev_private;
735 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
738 i915_kernel_lost_context(dev);
740 DRM_DEBUG_DRIVER("\n");
742 dev_priv->dri1.counter++;
743 if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
744 dev_priv->dri1.counter = 1;
745 if (dev_priv->sarea_priv)
746 dev_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
748 if (BEGIN_LP_RING(4) == 0) {
749 OUT_RING(MI_STORE_DWORD_INDEX);
750 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
751 OUT_RING(dev_priv->dri1.counter);
752 OUT_RING(MI_USER_INTERRUPT);
756 return dev_priv->dri1.counter;
759 static int i915_wait_irq(struct drm_device *dev, int irq_nr)
761 struct drm_i915_private *dev_priv = dev->dev_private;
763 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
766 struct intel_engine_cs *ring = LP_RING(dev_priv);
768 DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
769 READ_BREADCRUMB(dev_priv));
772 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
773 if (master_priv->sarea_priv)
774 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
778 if (master_priv->sarea_priv)
779 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
781 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
782 if (dev_priv->sarea_priv) {
783 dev_priv->sarea_priv->last_dispatch =
784 READ_BREADCRUMB(dev_priv);
789 if (dev_priv->sarea_priv)
790 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
793 if (ring->irq_get(ring)) {
794 DRM_WAIT_ON(ret, ring->irq_queue, 3 * HZ,
795 READ_BREADCRUMB(dev_priv) >= irq_nr);
797 } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
801 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
802 READ_BREADCRUMB(dev_priv), (int)dev_priv->dri1.counter);
808 /* Needs the lock as it touches the ring.
810 static int i915_irq_emit(struct drm_device *dev, void *data,
811 struct drm_file *file_priv)
813 struct drm_i915_private *dev_priv = dev->dev_private;
814 drm_i915_irq_emit_t *emit = data;
817 if (drm_core_check_feature(dev, DRIVER_MODESET))
820 if (!dev_priv || !LP_RING(dev_priv)->buffer->virtual_start) {
821 DRM_ERROR("called with no initialization\n");
825 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
827 mutex_lock(&dev->struct_mutex);
828 result = i915_emit_irq(dev);
829 mutex_unlock(&dev->struct_mutex);
831 if (copy_to_user(emit->irq_seq, &result, sizeof(int))) {
832 DRM_ERROR("copy_to_user\n");
839 /* Doesn't need the hardware lock.
841 static int i915_irq_wait(struct drm_device *dev, void *data,
842 struct drm_file *file_priv)
844 struct drm_i915_private *dev_priv = dev->dev_private;
845 drm_i915_irq_wait_t *irqwait = data;
847 if (drm_core_check_feature(dev, DRIVER_MODESET))
851 DRM_ERROR("called with no initialization\n");
855 return i915_wait_irq(dev, irqwait->irq_seq);
858 static int i915_vblank_pipe_get(struct drm_device *dev, void *data,
859 struct drm_file *file_priv)
861 struct drm_i915_private *dev_priv = dev->dev_private;
862 drm_i915_vblank_pipe_t *pipe = data;
864 if (drm_core_check_feature(dev, DRIVER_MODESET))
868 DRM_ERROR("called with no initialization\n");
872 pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
878 * Schedule buffer swap at given vertical blank.
880 static int i915_vblank_swap(struct drm_device *dev, void *data,
881 struct drm_file *file_priv)
883 /* The delayed swap mechanism was fundamentally racy, and has been
884 * removed. The model was that the client requested a delayed flip/swap
885 * from the kernel, then waited for vblank before continuing to perform
886 * rendering. The problem was that the kernel might wake the client
887 * up before it dispatched the vblank swap (since the lock has to be
888 * held while touching the ringbuffer), in which case the client would
889 * clear and start the next frame before the swap occurred, and
890 * flicker would occur in addition to likely missing the vblank.
892 * In the absence of this ioctl, userland falls back to a correct path
893 * of waiting for a vblank, then dispatching the swap on its own.
894 * Context switching to userland and back is plenty fast enough for
895 * meeting the requirements of vblank swapping.
900 static int i915_flip_bufs(struct drm_device *dev, void *data,
901 struct drm_file *file_priv)
905 if (drm_core_check_feature(dev, DRIVER_MODESET))
908 DRM_DEBUG_DRIVER("%s\n", __func__);
910 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
912 mutex_lock(&dev->struct_mutex);
913 ret = i915_dispatch_flip(dev);
914 mutex_unlock(&dev->struct_mutex);
919 static int i915_getparam(struct drm_device *dev, void *data,
920 struct drm_file *file_priv)
922 struct drm_i915_private *dev_priv = dev->dev_private;
923 drm_i915_getparam_t *param = data;
927 DRM_ERROR("called with no initialization\n");
931 switch (param->param) {
932 case I915_PARAM_IRQ_ACTIVE:
933 value = dev->irq_enabled ? 1 : 0;
935 case I915_PARAM_ALLOW_BATCHBUFFER:
936 value = dev_priv->dri1.allow_batchbuffer ? 1 : 0;
938 case I915_PARAM_LAST_DISPATCH:
939 value = READ_BREADCRUMB(dev_priv);
941 case I915_PARAM_CHIPSET_ID:
942 value = dev->pdev->device;
944 case I915_PARAM_HAS_GEM:
947 case I915_PARAM_NUM_FENCES_AVAIL:
948 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
950 case I915_PARAM_HAS_OVERLAY:
951 value = dev_priv->overlay ? 1 : 0;
953 case I915_PARAM_HAS_PAGEFLIPPING:
956 case I915_PARAM_HAS_EXECBUF2:
960 case I915_PARAM_HAS_BSD:
961 value = intel_ring_initialized(&dev_priv->ring[VCS]);
963 case I915_PARAM_HAS_BLT:
964 value = intel_ring_initialized(&dev_priv->ring[BCS]);
966 case I915_PARAM_HAS_VEBOX:
967 value = intel_ring_initialized(&dev_priv->ring[VECS]);
969 case I915_PARAM_HAS_RELAXED_FENCING:
972 case I915_PARAM_HAS_COHERENT_RINGS:
975 case I915_PARAM_HAS_EXEC_CONSTANTS:
976 value = INTEL_INFO(dev)->gen >= 4;
978 case I915_PARAM_HAS_RELAXED_DELTA:
981 case I915_PARAM_HAS_GEN7_SOL_RESET:
984 case I915_PARAM_HAS_LLC:
985 value = HAS_LLC(dev);
987 case I915_PARAM_HAS_WT:
990 case I915_PARAM_HAS_ALIASING_PPGTT:
991 value = USES_PPGTT(dev);
993 case I915_PARAM_HAS_WAIT_TIMEOUT:
996 case I915_PARAM_HAS_SEMAPHORES:
997 value = i915_semaphore_is_enabled(dev);
999 case I915_PARAM_HAS_PINNED_BATCHES:
1002 case I915_PARAM_HAS_EXEC_NO_RELOC:
1005 case I915_PARAM_HAS_EXEC_HANDLE_LUT:
1008 case I915_PARAM_CMD_PARSER_VERSION:
1009 value = i915_cmd_parser_get_version();
1012 DRM_DEBUG("Unknown parameter %d\n", param->param);
1016 if (copy_to_user(param->value, &value, sizeof(int))) {
1017 DRM_ERROR("copy_to_user failed\n");
1024 static int i915_setparam(struct drm_device *dev, void *data,
1025 struct drm_file *file_priv)
1027 struct drm_i915_private *dev_priv = dev->dev_private;
1028 drm_i915_setparam_t *param = data;
1031 DRM_ERROR("called with no initialization\n");
1035 switch (param->param) {
1036 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
1038 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
1040 case I915_SETPARAM_ALLOW_BATCHBUFFER:
1041 dev_priv->dri1.allow_batchbuffer = param->value ? 1 : 0;
1043 case I915_SETPARAM_NUM_USED_FENCES:
1044 if (param->value > dev_priv->num_fence_regs ||
1047 /* Userspace can use first N regs */
1048 dev_priv->fence_reg_start = param->value;
1051 DRM_DEBUG_DRIVER("unknown parameter %d\n",
1059 static int i915_set_status_page(struct drm_device *dev, void *data,
1060 struct drm_file *file_priv)
1062 #if 0 /* We don't care about dri1 */
1063 struct drm_i915_private *dev_priv = dev->dev_private;
1064 drm_i915_hws_addr_t *hws = data;
1065 struct intel_engine_cs *ring;
1067 if (drm_core_check_feature(dev, DRIVER_MODESET))
1070 if (!I915_NEED_GFX_HWS(dev))
1074 DRM_ERROR("called with no initialization\n");
1078 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1079 WARN(1, "tried to set status page when mode setting active\n");
1083 DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
1085 ring = LP_RING(dev_priv);
1086 ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
1088 dev_priv->dri1.gfx_hws_cpu_addr =
1089 ioremap_wc(dev_priv->gtt.mappable_base + hws->addr, 4096);
1090 if (dev_priv->dri1.gfx_hws_cpu_addr == NULL) {
1091 i915_dma_cleanup(dev);
1092 ring->status_page.gfx_addr = 0;
1093 DRM_ERROR("can not ioremap virtual address for"
1094 " G33 hw status page\n");
1098 memset_io(dev_priv->dri1.gfx_hws_cpu_addr, 0, PAGE_SIZE);
1099 I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
1101 DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
1102 ring->status_page.gfx_addr);
1103 DRM_DEBUG_DRIVER("load hws at %p\n",
1104 ring->status_page.page_addr);
1110 static int i915_get_bridge_dev(struct drm_device *dev)
1112 struct drm_i915_private *dev_priv = dev->dev_private;
1113 static struct pci_dev i915_bridge_dev;
1115 i915_bridge_dev.dev = pci_find_dbsf(0, 0, 0, 0);
1116 if (!i915_bridge_dev.dev) {
1117 DRM_ERROR("bridge device not found\n");
1121 dev_priv->bridge_dev = &i915_bridge_dev;
1125 #define MCHBAR_I915 0x44
1126 #define MCHBAR_I965 0x48
1127 #define MCHBAR_SIZE (4*4096)
1129 #define DEVEN_REG 0x54
1130 #define DEVEN_MCHBAR_EN (1 << 28)
1132 /* Allocate space for the MCH regs if needed, return nonzero on error */
1134 intel_alloc_mchbar_resource(struct drm_device *dev)
1136 struct drm_i915_private *dev_priv = dev->dev_private;
1137 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1139 u32 temp_lo, temp_hi = 0;
1142 if (INTEL_INFO(dev)->gen >= 4)
1143 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
1144 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
1145 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
1147 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
1150 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
1154 /* Get some space for it */
1155 vga = device_get_parent(dev->dev);
1156 dev_priv->mch_res_rid = 0x100;
1157 dev_priv->mch_res = BUS_ALLOC_RESOURCE(device_get_parent(vga),
1158 dev->dev, SYS_RES_MEMORY, &dev_priv->mch_res_rid, 0, ~0UL,
1159 MCHBAR_SIZE, RF_ACTIVE | RF_SHAREABLE, -1);
1160 if (dev_priv->mch_res == NULL) {
1161 DRM_ERROR("failed mchbar resource alloc\n");
1165 if (INTEL_INFO(dev)->gen >= 4)
1166 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
1167 upper_32_bits(rman_get_start(dev_priv->mch_res)));
1169 pci_write_config_dword(dev_priv->bridge_dev, reg,
1170 lower_32_bits(rman_get_start(dev_priv->mch_res)));
1174 /* Setup MCHBAR if possible, return true if we should disable it again */
1176 intel_setup_mchbar(struct drm_device *dev)
1178 struct drm_i915_private *dev_priv = dev->dev_private;
1179 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1183 if (IS_VALLEYVIEW(dev))
1186 dev_priv->mchbar_need_disable = false;
1188 if (IS_I915G(dev) || IS_I915GM(dev)) {
1189 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1190 enabled = !!(temp & DEVEN_MCHBAR_EN);
1192 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1196 /* If it's already enabled, don't have to do anything */
1200 if (intel_alloc_mchbar_resource(dev))
1203 dev_priv->mchbar_need_disable = true;
1205 /* Space is allocated or reserved, so enable it. */
1206 if (IS_I915G(dev) || IS_I915GM(dev)) {
1207 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
1208 temp | DEVEN_MCHBAR_EN);
1210 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1211 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
1216 intel_teardown_mchbar(struct drm_device *dev)
1218 struct drm_i915_private *dev_priv = dev->dev_private;
1219 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1223 if (dev_priv->mchbar_need_disable) {
1224 if (IS_I915G(dev) || IS_I915GM(dev)) {
1225 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1226 temp &= ~DEVEN_MCHBAR_EN;
1227 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
1229 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1231 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
1235 if (dev_priv->mch_res != NULL) {
1236 vga = device_get_parent(dev->dev);
1237 BUS_DEACTIVATE_RESOURCE(device_get_parent(vga), dev->dev,
1238 SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1239 BUS_RELEASE_RESOURCE(device_get_parent(vga), dev->dev,
1240 SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1241 dev_priv->mch_res = NULL;
1246 /* true = enable decode, false = disable decoder */
1247 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1249 struct drm_device *dev = cookie;
1251 intel_modeset_vga_set_state(dev, state);
1253 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1254 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1256 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1259 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1261 struct drm_device *dev = pci_get_drvdata(pdev);
1262 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1264 if (state == VGA_SWITCHEROO_ON) {
1265 pr_info("switched on\n");
1266 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1267 /* i915 resume handler doesn't set to D0 */
1268 pci_set_power_state(dev->pdev, PCI_D0);
1270 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1272 pr_err("switched off\n");
1273 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1274 i915_suspend(dev, pmm);
1275 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1279 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1281 struct drm_device *dev = pci_get_drvdata(pdev);
1284 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1285 * locking inversion with the driver load path. And the access here is
1286 * completely racy anyway. So don't bother with locking for now.
1288 return dev->open_count == 0;
1291 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
1292 .set_gpu_state = i915_switcheroo_set_state,
1294 .can_switch = i915_switcheroo_can_switch,
1298 static int i915_load_modeset_init(struct drm_device *dev)
1300 struct drm_i915_private *dev_priv = dev->dev_private;
1303 ret = intel_parse_bios(dev);
1305 DRM_INFO("failed to find VBIOS tables\n");
1308 /* If we have > 1 VGA cards, then we need to arbitrate access
1309 * to the common VGA resources.
1311 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1312 * then we do not take part in VGA arbitration and the
1313 * vga_client_register() fails with -ENODEV.
1315 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1316 if (ret && ret != -ENODEV)
1319 intel_register_dsm_handler();
1321 ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false);
1323 goto cleanup_vga_client;
1325 /* Initialise stolen first so that we may reserve preallocated
1326 * objects for the BIOS to KMS transition.
1328 ret = i915_gem_init_stolen(dev);
1330 goto cleanup_vga_switcheroo;
1333 intel_power_domains_init_hw(dev_priv);
1336 * We enable some interrupt sources in our postinstall hooks, so mark
1337 * interrupts as enabled _before_ actually enabling them to avoid
1338 * special cases in our ordering checks.
1340 dev_priv->pm._irqs_disabled = false;
1342 ret = drm_irq_install(dev, dev->irq);
1344 goto cleanup_gem_stolen;
1346 /* Important: The output setup functions called by modeset_init need
1347 * working irqs for e.g. gmbus and dp aux transfers. */
1348 intel_modeset_init(dev);
1350 ret = i915_gem_init(dev);
1354 intel_modeset_gem_init(dev);
1356 /* Always safe in the mode setting case. */
1357 /* FIXME: do pre/post-mode set stuff in core KMS code */
1358 dev->vblank_disable_allowed = 1;
1359 if (INTEL_INFO(dev)->num_pipes == 0) {
1363 ret = intel_fbdev_init(dev);
1367 /* Only enable hotplug handling once the fbdev is fully set up. */
1368 intel_hpd_init(dev);
1371 * Some ports require correctly set-up hpd registers for detection to
1372 * work properly (leading to ghost connected connector status), e.g. VGA
1373 * on gm45. Hence we can only set up the initial fbdev config after hpd
1374 * irqs are fully enabled. Now we should scan for the initial config
1375 * only once hotplug handling is enabled, but due to screwed-up locking
1376 * around kms/fbdev init we can't protect the fdbev initial config
1377 * scanning against hotplug events. Hence do this first and ignore the
1378 * tiny window where we will loose hotplug notifactions.
1380 async_schedule(intel_fbdev_initial_config, dev_priv);
1382 drm_kms_helper_poll_init(dev);
1387 mutex_lock(&dev->struct_mutex);
1388 i915_gem_cleanup_ringbuffer(dev);
1389 i915_gem_context_fini(dev);
1390 mutex_unlock(&dev->struct_mutex);
1392 drm_irq_uninstall(dev);
1395 i915_gem_cleanup_stolen(dev);
1396 cleanup_vga_switcheroo:
1397 vga_switcheroo_unregister_client(dev->pdev);
1399 vga_client_register(dev->pdev, NULL, NULL, NULL);
1406 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1408 struct drm_i915_master_private *master_priv;
1410 master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1414 master->driver_priv = master_priv;
1418 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1420 struct drm_i915_master_private *master_priv = master->driver_priv;
1427 master->driver_priv = NULL;
1431 #if IS_ENABLED(CONFIG_FB)
1432 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
1434 struct apertures_struct *ap;
1435 struct pci_dev *pdev = dev_priv->dev->pdev;
1439 ap = alloc_apertures(1);
1443 ap->ranges[0].base = dev_priv->gtt.mappable_base;
1444 ap->ranges[0].size = dev_priv->gtt.mappable_end;
1447 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
1449 ret = remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
1456 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
1462 #if !defined(CONFIG_VGA_CONSOLE)
1463 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
1467 #elif !defined(CONFIG_DUMMY_CONSOLE)
1468 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
1473 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
1477 DRM_INFO("Replacing VGA console driver\n");
1480 if (con_is_bound(&vga_con))
1481 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
1483 ret = do_unregister_con_driver(&vga_con);
1485 /* Ignore "already unregistered". */
1495 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
1498 const struct intel_device_info *info = &dev_priv->info;
1500 #define PRINT_S(name) "%s"
1502 #define PRINT_FLAG(name) info->name ? #name "," : ""
1504 DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x rev=0x%02x flags="
1505 DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY),
1507 dev_priv->dev->pdev->device,
1508 dev_priv->dev->pdev->revision,
1509 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA));
1518 * Determine various intel_device_info fields at runtime.
1520 * Use it when either:
1521 * - it's judged too laborious to fill n static structures with the limit
1522 * when a simple if statement does the job,
1523 * - run-time checks (eg read fuse/strap registers) are needed.
1525 * This function needs to be called:
1526 * - after the MMIO has been setup as we are reading registers,
1527 * - after the PCH has been detected,
1528 * - before the first usage of the fields it can tweak.
1530 static void intel_device_info_runtime_init(struct drm_device *dev)
1532 struct drm_i915_private *dev_priv = dev->dev_private;
1533 struct intel_device_info *info;
1534 enum i915_pipe pipe;
1536 info = (struct intel_device_info *)&dev_priv->info;
1538 if (IS_VALLEYVIEW(dev))
1539 for_each_pipe(dev_priv, pipe)
1540 info->num_sprites[pipe] = 2;
1542 for_each_pipe(dev_priv, pipe)
1543 info->num_sprites[pipe] = 1;
1545 if (i915.disable_display) {
1546 DRM_INFO("Display disabled (module parameter)\n");
1547 info->num_pipes = 0;
1548 } else if (info->num_pipes > 0 &&
1549 (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) &&
1550 !IS_VALLEYVIEW(dev)) {
1551 u32 fuse_strap = I915_READ(FUSE_STRAP);
1552 u32 sfuse_strap = I915_READ(SFUSE_STRAP);
1555 * SFUSE_STRAP is supposed to have a bit signalling the display
1556 * is fused off. Unfortunately it seems that, at least in
1557 * certain cases, fused off display means that PCH display
1558 * reads don't land anywhere. In that case, we read 0s.
1560 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
1561 * should be set when taking over after the firmware.
1563 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
1564 sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
1565 (dev_priv->pch_type == PCH_CPT &&
1566 !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
1567 DRM_INFO("Display fused off, disabling\n");
1568 info->num_pipes = 0;
1574 * i915_driver_load - setup chip and create an initial config
1576 * @flags: startup flags
1578 * The driver load routine has to do several things:
1579 * - drive output discovery via intel_modeset_init()
1580 * - initialize the memory manager
1581 * - allocate initial config memory
1582 * - setup the DRM framebuffer with the allocated memory
1584 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1586 struct drm_i915_private *dev_priv = dev->dev_private;
1587 struct intel_device_info *info, *device_info;
1588 unsigned long base, size;
1589 int ret = 0, mmio_bar, mmio_size;
1590 uint32_t aperture_size;
1591 static struct pci_dev i915_pdev;
1593 /* XXX: dev->pci_device not present in Linux drm */
1594 info = i915_get_device_id(dev->pci_device);
1596 /* XXX: struct pci_dev */
1597 i915_pdev.dev = dev->dev;
1598 dev->pdev = &i915_pdev;
1599 dev->pdev->device = dev->pci_device;
1601 /* Refuse to load on gen6+ without kms enabled. */
1602 if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET)) {
1603 DRM_INFO("Your hardware requires kernel modesetting (KMS)\n");
1604 DRM_INFO("See CONFIG_DRM_I915_KMS, nomodeset, and i915.modeset parameters\n");
1608 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1609 if (dev_priv == NULL)
1612 dev->dev_private = dev_priv;
1613 dev_priv->dev = dev;
1615 /* Setup the write-once "constant" device info */
1616 device_info = (struct intel_device_info *)&dev_priv->info;
1617 memcpy(device_info, info, sizeof(dev_priv->info));
1618 device_info->device_id = dev->pdev->device;
1620 lockinit(&dev_priv->irq_lock, "userirq", 0, LK_CANRECURSE);
1621 lockinit(&dev_priv->gpu_error.lock, "915err", 0, LK_CANRECURSE);
1622 spin_init(&dev_priv->backlight_lock, "i915bl");
1623 lockinit(&dev_priv->uncore.lock, "915gt", 0, LK_CANRECURSE);
1624 spin_init(&dev_priv->mm.object_stat_lock, "i915osl");
1625 spin_init(&dev_priv->mmio_flip_lock, "i915mfl");
1626 lockinit(&dev_priv->dpio_lock, "i915dpio", 0, LK_CANRECURSE);
1627 lockinit(&dev_priv->modeset_restore_lock, "i915mrl", 0, LK_CANRECURSE);
1629 intel_pm_setup(dev);
1631 intel_display_crc_init(dev);
1633 i915_dump_device_info(dev_priv);
1635 /* Not all pre-production machines fall into this category, only the
1636 * very first ones. Almost everything should work, except for maybe
1637 * suspend/resume. And we don't implement workarounds that affect only
1638 * pre-production machines. */
1639 if (IS_HSW_EARLY_SDV(dev))
1640 DRM_INFO("This is an early pre-production Haswell machine. "
1641 "It may not be fully functional.\n");
1643 if (i915_get_bridge_dev(dev)) {
1648 mmio_bar = IS_GEN2(dev) ? 1 : 0;
1649 /* Before gen4, the registers and the GTT are behind different BARs.
1650 * However, from gen4 onwards, the registers and the GTT are shared
1651 * in the same BAR, so we want to restrict this ioremap from
1652 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
1653 * the register BAR remains the same size for all the earlier
1654 * generations up to Ironlake.
1657 mmio_size = 512*1024;
1659 mmio_size = 2*1024*1024;
1662 dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
1663 if (!dev_priv->regs) {
1664 DRM_ERROR("failed to map registers\n");
1669 base = drm_get_resource_start(dev, mmio_bar);
1670 size = drm_get_resource_len(dev, mmio_bar);
1672 ret = drm_legacy_addmap(dev, base, size, _DRM_REGISTERS,
1673 _DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio_map);
1676 /* This must be called before any calls to HAS_PCH_* */
1677 intel_detect_pch(dev);
1679 intel_uncore_init(dev);
1681 ret = i915_gem_gtt_init(dev);
1685 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1686 /* WARNING: Apparently we must kick fbdev drivers before vgacon,
1687 * otherwise the vga fbdev driver falls over. */
1688 ret = i915_kick_out_firmware_fb(dev_priv);
1690 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1694 ret = i915_kick_out_vgacon(dev_priv);
1696 DRM_ERROR("failed to remove conflicting VGA console\n");
1702 pci_set_master(dev->pdev);
1704 /* overlay on gen2 is broken and can't address above 1G */
1706 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1708 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1709 * using 32bit addressing, overwriting memory if HWS is located
1712 * The documentation also mentions an issue with undefined
1713 * behaviour if any general state is accessed within a page above 4GB,
1714 * which also needs to be handled carefully.
1716 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1717 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1720 aperture_size = dev_priv->gtt.mappable_end;
1722 dev_priv->gtt.mappable =
1723 io_mapping_create_wc(dev_priv->gtt.mappable_base,
1725 if (dev_priv->gtt.mappable == NULL) {
1730 dev_priv->gtt.mtrr = arch_phys_wc_add(dev_priv->gtt.mappable_base,
1733 /* The i915 workqueue is primarily used for batched retirement of
1734 * requests (and thus managing bo) once the task has been completed
1735 * by the GPU. i915_gem_retire_requests() is called directly when we
1736 * need high-priority retirement, such as waiting for an explicit
1739 * It is also used for periodic low-priority events, such as
1740 * idle-timers and recording error state.
1742 * All tasks on the workqueue are expected to acquire the dev mutex
1743 * so there is no point in running more than one instance of the
1744 * workqueue at any time. Use an ordered one.
1746 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
1747 if (dev_priv->wq == NULL) {
1748 DRM_ERROR("Failed to create our workqueue.\n");
1753 dev_priv->dp_wq = alloc_ordered_workqueue("i915-dp", 0);
1754 if (dev_priv->dp_wq == NULL) {
1755 DRM_ERROR("Failed to create our dp workqueue.\n");
1760 intel_irq_init(dev);
1761 intel_uncore_sanitize(dev);
1763 /* Try to make sure MCHBAR is enabled before poking at it */
1764 intel_setup_mchbar(dev);
1765 intel_setup_gmbus(dev);
1766 intel_opregion_setup(dev);
1768 intel_setup_bios(dev);
1772 /* On the 945G/GM, the chipset reports the MSI capability on the
1773 * integrated graphics even though the support isn't actually there
1774 * according to the published specs. It doesn't appear to function
1775 * correctly in testing on 945G.
1776 * This may be a side effect of MSI having been made available for PEG
1777 * and the registers being closely associated.
1779 * According to chipset errata, on the 965GM, MSI interrupts may
1780 * be lost or delayed, but we use them anyways to avoid
1781 * stuck interrupts on some machines.
1784 if (!IS_I945G(dev) && !IS_I945GM(dev))
1785 pci_enable_msi(dev->pdev);
1788 intel_device_info_runtime_init(dev);
1790 if (INTEL_INFO(dev)->num_pipes) {
1791 ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
1793 goto out_gem_unload;
1796 intel_power_domains_init(dev_priv);
1798 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1799 ret = i915_load_modeset_init(dev);
1801 DRM_ERROR("failed to init modeset\n");
1802 goto out_power_well;
1805 /* Start out suspended in ums mode. */
1806 dev_priv->ums.mm_suspended = 1;
1810 i915_setup_sysfs(dev);
1813 if (INTEL_INFO(dev)->num_pipes) {
1814 /* Must be done after probing outputs */
1815 intel_opregion_init(dev);
1817 acpi_video_register();
1822 intel_gpu_ips_init(dev_priv);
1824 intel_init_runtime_pm(dev_priv);
1829 intel_power_domains_remove(dev_priv);
1830 drm_vblank_cleanup(dev);
1833 intel_teardown_gmbus(dev);
1834 intel_teardown_mchbar(dev);
1835 pm_qos_remove_request(&dev_priv->pm_qos);
1836 destroy_workqueue(dev_priv->dp_wq);
1838 destroy_workqueue(dev_priv->wq);
1840 arch_phys_wc_del(dev_priv->gtt.mtrr);
1842 io_mapping_free(dev_priv->gtt.mappable);
1845 i915_global_gtt_cleanup(dev);
1847 intel_uncore_fini(dev);
1853 int i915_driver_unload(struct drm_device *dev)
1855 struct drm_i915_private *dev_priv = dev->dev_private;
1858 ret = i915_gem_suspend(dev);
1860 DRM_ERROR("failed to idle hardware: %d\n", ret);
1864 intel_fini_runtime_pm(dev_priv);
1866 intel_gpu_ips_teardown();
1868 /* The i915.ko module is still not prepared to be loaded when
1869 * the power well is not enabled, so just enable it in case
1870 * we're going to unload/reload. */
1871 intel_display_set_init_power(dev_priv, true);
1872 intel_power_domains_remove(dev_priv);
1875 i915_teardown_sysfs(dev);
1877 WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier));
1878 unregister_shrinker(&dev_priv->mm.shrinker);
1880 io_mapping_free(dev_priv->gtt.mappable);
1882 arch_phys_wc_del(dev_priv->gtt.mtrr);
1885 acpi_video_unregister();
1888 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1889 intel_fbdev_fini(dev);
1890 intel_modeset_cleanup(dev);
1893 * free the memory space allocated for the child device
1894 * config parsed from VBT
1896 if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1897 kfree(dev_priv->vbt.child_dev);
1898 dev_priv->vbt.child_dev = NULL;
1899 dev_priv->vbt.child_dev_num = 0;
1904 /* Free error state after interrupts are fully disabled. */
1905 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
1906 cancel_work_sync(&dev_priv->gpu_error.work);
1908 i915_destroy_error_state(dev);
1911 intel_opregion_fini(dev);
1913 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1914 /* Flush any outstanding unpin_work. */
1915 flush_workqueue(dev_priv->wq);
1917 mutex_lock(&dev->struct_mutex);
1918 i915_gem_cleanup_ringbuffer(dev);
1919 i915_gem_context_fini(dev);
1920 mutex_unlock(&dev->struct_mutex);
1922 i915_gem_cleanup_stolen(dev);
1925 if (!I915_NEED_GFX_HWS(dev))
1929 drm_vblank_cleanup(dev);
1931 intel_teardown_gmbus(dev);
1932 intel_teardown_mchbar(dev);
1934 bus_generic_detach(dev->dev);
1935 drm_legacy_rmmap(dev, dev_priv->mmio_map);
1937 destroy_workqueue(dev_priv->dp_wq);
1938 destroy_workqueue(dev_priv->wq);
1939 pm_qos_remove_request(&dev_priv->pm_qos);
1941 i915_global_gtt_cleanup(dev);
1943 intel_uncore_fini(dev);
1945 if (dev_priv->regs != NULL)
1946 pci_iounmap(dev->pdev, dev_priv->regs);
1949 pci_dev_put(dev_priv->bridge_dev);
1955 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1959 ret = i915_gem_open(dev, file);
1967 * i915_driver_lastclose - clean up after all DRM clients have exited
1970 * Take care of cleaning up after all DRM clients have exited. In the
1971 * mode setting case, we want to restore the kernel's initial mode (just
1972 * in case the last client left us in a bad state).
1974 * Additionally, in the non-mode setting case, we'll tear down the GTT
1975 * and DMA structures, since the kernel won't be using them, and clea
1978 void i915_driver_lastclose(struct drm_device *dev)
1980 struct drm_i915_private *dev_priv = dev->dev_private;
1982 /* On gen6+ we refuse to init without kms enabled, but then the drm core
1983 * goes right around and calls lastclose. Check for this and don't clean
1988 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1990 intel_fbdev_restore_mode(dev);
1991 vga_switcheroo_process_delayed_switch();
1996 i915_gem_lastclose(dev);
1998 i915_dma_cleanup(dev);
2001 void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
2003 mutex_lock(&dev->struct_mutex);
2004 i915_gem_context_close(dev, file);
2005 i915_gem_release(dev, file);
2006 mutex_unlock(&dev->struct_mutex);
2008 if (drm_core_check_feature(dev, DRIVER_MODESET))
2009 intel_modeset_preclose(dev, file);
2012 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
2014 struct drm_i915_file_private *file_priv = file->driver_priv;
2016 if (file_priv && file_priv->bsd_ring)
2017 file_priv->bsd_ring = NULL;
2021 const struct drm_ioctl_desc i915_ioctls[] = {
2022 DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2023 DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
2024 DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
2025 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
2026 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
2027 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
2028 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
2029 DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2030 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2031 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2032 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2033 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
2034 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2035 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2036 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH),
2037 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
2038 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2039 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2040 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
2041 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
2042 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2043 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2044 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
2045 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2046 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2047 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
2048 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2049 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2050 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2051 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2052 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2053 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2054 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2055 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2056 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2057 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2058 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2059 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2060 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
2061 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2062 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2063 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2064 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2065 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2066 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
2067 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2068 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2069 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2070 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_get_reset_stats_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2072 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2076 int i915_max_ioctl = ARRAY_SIZE(i915_ioctls);
2079 * This is really ugly: Because old userspace abused the linux agp interface to
2080 * manage the gtt, we need to claim that all intel devices are agp. For
2081 * otherwise the drm core refuses to initialize the agp support code.
2083 int i915_driver_device_is_agp(struct drm_device *dev)