2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
28 #include <linux/bitops.h>
30 #include <drm/i915_drm.h>
33 /** @file i915_gem_tiling.c
35 * Support for managing tiling state of buffer objects.
37 * The idea behind tiling is to increase cache hit rates by rearranging
38 * pixel data so that a group of pixel accesses are in the same cacheline.
39 * Performance improvement from doing this on the back/depth buffer are on
42 * Intel architectures make this somewhat more complicated, though, by
43 * adjustments made to addressing of data when the memory is in interleaved
44 * mode (matched pairs of DIMMS) to improve memory bandwidth.
45 * For interleaved memory, the CPU sends every sequential 64 bytes
46 * to an alternate memory channel so it can get the bandwidth from both.
48 * The GPU also rearranges its accesses for increased bandwidth to interleaved
49 * memory, and it matches what the CPU does for non-tiled. However, when tiled
50 * it does it a little differently, since one walks addresses not just in the
51 * X direction but also Y. So, along with alternating channels when bit
52 * 6 of the address flips, it also alternates when other bits flip -- Bits 9
53 * (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines)
54 * are common to both the 915 and 965-class hardware.
56 * The CPU also sometimes XORs in higher bits as well, to improve
57 * bandwidth doing strided access like we do so frequently in graphics. This
58 * is called "Channel XOR Randomization" in the MCH documentation. The result
59 * is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address
62 * All of this bit 6 XORing has an effect on our memory management,
63 * as we need to make sure that the 3d driver can correctly address object
66 * If we don't have interleaved memory, all tiling is safe and no swizzling is
69 * When bit 17 is XORed in, we simply refuse to tile at all. Bit
70 * 17 is not just a page offset, so as we page an objet out and back in,
71 * individual pages in it will have different bit 17 addresses, resulting in
72 * each 64 bytes being swapped with its neighbor!
74 * Otherwise, if interleaved, we have to tell the 3d driver what the address
75 * swizzling it needs to do is, since it's writing with the CPU to the pages
76 * (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the
77 * pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling
78 * required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order
79 * to match what the GPU expects.
83 * Detects bit 6 swizzling of address lookup between IGD access and CPU
84 * access through main memory.
87 i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
89 struct drm_i915_private *dev_priv = dev->dev_private;
90 uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
91 uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
93 if (INTEL_INFO(dev)->gen >= 8 || IS_VALLEYVIEW(dev)) {
95 * On BDW+, swizzling is not used. We leave the CPU memory
96 * controller in charge of optimizing memory accesses without
97 * the extra address manipulation GPU side.
99 * VLV and CHV don't have GPU swizzling.
101 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
102 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
103 } else if (INTEL_INFO(dev)->gen >= 6) {
104 uint32_t dimm_c0, dimm_c1;
105 dimm_c0 = I915_READ(MAD_DIMM_C0);
106 dimm_c1 = I915_READ(MAD_DIMM_C1);
107 dimm_c0 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK;
108 dimm_c1 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK;
109 /* Enable swizzling when the channels are populated with
110 * identically sized dimms. We don't need to check the 3rd
111 * channel because no cpu with gpu attached ships in that
112 * configuration. Also, swizzling only makes sense for 2
113 * channels anyway. */
114 if (dimm_c0 == dimm_c1) {
115 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
116 swizzle_y = I915_BIT_6_SWIZZLE_9;
118 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
119 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
121 } else if (IS_GEN5(dev)) {
122 /* On Ironlake whatever DRAM config, GPU always do
123 * same swizzling setup.
125 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
126 swizzle_y = I915_BIT_6_SWIZZLE_9;
127 } else if (IS_GEN2(dev)) {
128 /* As far as we know, the 865 doesn't have these bit 6
131 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
132 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
133 } else if (IS_MOBILE(dev) || (IS_GEN3(dev) && !IS_G33(dev))) {
136 /* On 9xx chipsets, channel interleave by the CPU is
137 * determined by DCC. For single-channel, neither the CPU
138 * nor the GPU do swizzling. For dual channel interleaved,
139 * the GPU's interleave is bit 9 and 10 for X tiled, and bit
140 * 9 for Y tiled. The CPU's interleave is independent, and
141 * can be based on either bit 11 (haven't seen this yet) or
144 dcc = I915_READ(DCC);
145 switch (dcc & DCC_ADDRESSING_MODE_MASK) {
146 case DCC_ADDRESSING_MODE_SINGLE_CHANNEL:
147 case DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC:
148 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
149 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
151 case DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED:
152 if (dcc & DCC_CHANNEL_XOR_DISABLE) {
153 /* This is the base swizzling by the GPU for
156 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
157 swizzle_y = I915_BIT_6_SWIZZLE_9;
158 } else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) {
159 /* Bit 11 swizzling by the CPU in addition. */
160 swizzle_x = I915_BIT_6_SWIZZLE_9_10_11;
161 swizzle_y = I915_BIT_6_SWIZZLE_9_11;
163 /* Bit 17 swizzling by the CPU in addition. */
164 swizzle_x = I915_BIT_6_SWIZZLE_9_10_17;
165 swizzle_y = I915_BIT_6_SWIZZLE_9_17;
169 if (dcc == 0xffffffff) {
170 DRM_ERROR("Couldn't read from MCHBAR. "
171 "Disabling tiling.\n");
172 swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
173 swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
176 /* The 965, G33, and newer, have a very flexible memory
177 * configuration. It will enable dual-channel mode
178 * (interleaving) on as much memory as it can, and the GPU
179 * will additionally sometimes enable different bit 6
180 * swizzling for tiled objects from the CPU.
182 * Here's what I found on the G965:
183 * slot fill memory size swizzling
184 * 0A 0B 1A 1B 1-ch 2-ch
186 * 512 0 512 0 16 1008 X
187 * 512 0 0 512 16 1008 X
188 * 0 512 0 512 16 1008 X
189 * 1024 1024 1024 0 2048 1024 O
191 * We could probably detect this based on either the DRB
192 * matching, which was the case for the swizzling required in
193 * the table above, or from the 1-ch value being less than
194 * the minimum size of a rank.
196 if (I915_READ16(C0DRB3) != I915_READ16(C1DRB3)) {
197 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
198 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
200 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
201 swizzle_y = I915_BIT_6_SWIZZLE_9;
205 dev_priv->mm.bit_6_swizzle_x = swizzle_x;
206 dev_priv->mm.bit_6_swizzle_y = swizzle_y;
209 /* Check pitch constriants for all chips & tiling formats */
211 i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
215 /* Linear is always fine */
216 if (tiling_mode == I915_TILING_NONE)
220 (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
225 /* check maximum stride & object size */
226 /* i965+ stores the end address of the gtt mapping in the fence
227 * reg, so dont bother to check the size */
228 if (INTEL_INFO(dev)->gen >= 7) {
229 if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL)
231 } else if (INTEL_INFO(dev)->gen >= 4) {
232 if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
239 if (size > I830_FENCE_MAX_SIZE_VAL << 20)
242 if (size > I830_FENCE_MAX_SIZE_VAL << 19)
247 if (stride < tile_width)
250 /* 965+ just needs multiples of tile width */
251 if (INTEL_INFO(dev)->gen >= 4) {
252 if (stride & (tile_width - 1))
257 /* Pre-965 needs power of two tile widths */
258 if (stride & (stride - 1))
264 /* Is the current GTT allocation valid for the change in tiling? */
266 i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode)
270 if (tiling_mode == I915_TILING_NONE)
273 if (INTEL_INFO(obj->base.dev)->gen >= 4)
276 if (INTEL_INFO(obj->base.dev)->gen == 3) {
277 if (i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK)
280 if (i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK)
284 size = i915_gem_get_gtt_size(obj->base.dev, obj->base.size, tiling_mode);
285 if (i915_gem_obj_ggtt_size(obj) != size)
288 if (i915_gem_obj_ggtt_offset(obj) & (size - 1))
295 * Sets the tiling mode of an object, returning the required swizzling of
296 * bit 6 of addresses in the object.
299 i915_gem_set_tiling(struct drm_device *dev, void *data,
300 struct drm_file *file)
302 struct drm_i915_gem_set_tiling *args = data;
303 struct drm_i915_private *dev_priv = dev->dev_private;
304 struct drm_i915_gem_object *obj;
307 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
308 if (&obj->base == NULL)
311 if (!i915_tiling_ok(dev,
312 args->stride, obj->base.size, args->tiling_mode)) {
313 drm_gem_object_unreference_unlocked(&obj->base);
317 if (i915_gem_obj_is_pinned(obj) || obj->framebuffer_references) {
318 drm_gem_object_unreference_unlocked(&obj->base);
322 if (args->tiling_mode == I915_TILING_NONE) {
323 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
326 if (args->tiling_mode == I915_TILING_X)
327 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
329 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
331 /* Hide bit 17 swizzling from the user. This prevents old Mesa
332 * from aborting the application on sw fallbacks to bit 17,
333 * and we use the pread/pwrite bit17 paths to swizzle for it.
334 * If there was a user that was relying on the swizzle
335 * information for drm_intel_bo_map()ed reads/writes this would
336 * break it, but we don't have any of those.
338 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
339 args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
340 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
341 args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
343 /* If we can't handle the swizzling, make it untiled. */
344 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) {
345 args->tiling_mode = I915_TILING_NONE;
346 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
351 mutex_lock(&dev->struct_mutex);
352 if (args->tiling_mode != obj->tiling_mode ||
353 args->stride != obj->stride) {
354 /* We need to rebind the object if its current allocation
355 * no longer meets the alignment restrictions for its new
356 * tiling mode. Otherwise we can just leave it alone, but
357 * need to ensure that any fence register is updated before
358 * the next fenced (either through the GTT or by the BLT unit
359 * on older GPUs) access.
361 * After updating the tiling parameters, we then flag whether
362 * we need to update an associated fence register. Note this
363 * has to also include the unfenced register the GPU uses
364 * whilst executing a fenced command for an untiled object.
366 if (obj->map_and_fenceable &&
367 !i915_gem_object_fence_ok(obj, args->tiling_mode))
368 ret = i915_gem_object_ggtt_unbind(obj);
372 obj->last_fenced_seqno ||
373 obj->fence_reg != I915_FENCE_REG_NONE;
375 obj->tiling_mode = args->tiling_mode;
376 obj->stride = args->stride;
378 /* Force the fence to be reacquired for GTT access */
379 i915_gem_release_mmap(obj);
382 /* we have to maintain this existing ABI... */
383 args->stride = obj->stride;
384 args->tiling_mode = obj->tiling_mode;
386 /* Try to preallocate memory required to save swizzling on put-pages */
387 if (i915_gem_object_needs_bit17_swizzle(obj)) {
388 if (obj->bit_17 == NULL) {
389 obj->bit_17 = kcalloc(BITS_TO_LONGS(obj->base.size >> PAGE_SHIFT),
390 sizeof(long), GFP_KERNEL);
397 drm_gem_object_unreference(&obj->base);
398 mutex_unlock(&dev->struct_mutex);
404 * Returns the current tiling mode and required bit 6 swizzling for the object.
407 i915_gem_get_tiling(struct drm_device *dev, void *data,
408 struct drm_file *file)
410 struct drm_i915_gem_get_tiling *args = data;
411 struct drm_i915_private *dev_priv = dev->dev_private;
412 struct drm_i915_gem_object *obj;
414 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
415 if (&obj->base == NULL)
418 mutex_lock(&dev->struct_mutex);
420 args->tiling_mode = obj->tiling_mode;
421 switch (obj->tiling_mode) {
423 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
426 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
428 case I915_TILING_NONE:
429 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
432 DRM_ERROR("unknown tiling mode\n");
435 /* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */
436 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
437 args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
438 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
439 args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
441 drm_gem_object_unreference(&obj->base);
442 mutex_unlock(&dev->struct_mutex);
448 * Swap every 64 bytes of this page around, to account for it having a new
449 * bit 17 of its physical address and therefore being interpreted differently
453 i915_gem_swizzle_page(struct vm_page *page)
461 for (i = 0; i < PAGE_SIZE; i += 128) {
462 memcpy(temp, &vaddr[i], 64);
463 memcpy(&vaddr[i], &vaddr[i + 64], 64);
464 memcpy(&vaddr[i + 64], temp, 64);
471 i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj)
473 int page_count = obj->base.size >> PAGE_SHIFT;
476 if (obj->bit_17 == NULL)
479 for (i = 0; i < page_count; i++) {
480 struct vm_page *page = obj->pages[i];
481 char new_bit_17 = VM_PAGE_TO_PHYS(obj->pages[i]) >> 17;
482 if ((new_bit_17 & 0x1) !=
483 (test_bit(i, obj->bit_17) != 0)) {
484 i915_gem_swizzle_page(page);
485 set_page_dirty(page);
491 i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj)
493 int page_count = obj->base.size >> PAGE_SHIFT;
496 if (obj->bit_17 == NULL) {
497 obj->bit_17 = kcalloc(BITS_TO_LONGS(page_count),
498 sizeof(long), GFP_KERNEL);
499 if (obj->bit_17 == NULL) {
500 DRM_ERROR("Failed to allocate memory for bit 17 "
506 for (i = 0; i < page_count; i++) {
507 if (VM_PAGE_TO_PHYS(obj->pages[i]) & (1 << 17))
508 __set_bit(i, obj->bit_17);
510 __clear_bit(i, obj->bit_17);