2 .\" Copyright (c) 1995, 1996, 1997, 1998, 2000
3 .\" Justin T. Gibbs. All rights reserved.
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27 .\" $FreeBSD: src/share/man/man4/ahc.4,v 1.38.2.1 2006/06/05 19:30:28 brueffer Exp $
28 .\" $DragonFly: src/share/man/man4/ahc.4,v 1.5 2007/07/07 18:31:59 swildner Exp $
35 .Nd Adaptec VL/EISA/PCI SCSI host adapter driver
37 To compile this driver into the kernel,
38 place the following lines in your
39 kernel configuration file:
40 .Bd -ragged -offset indent
44 For one or more VL/EISA cards:
47 For one or more PCI cards:
50 To allow PCI adapters to use memory mapped I/O if enabled:
51 .Cd options AHC_ALLOW_MEMIO
53 To configure one or more controllers to assume the target role:
54 .Cd options AHC_TMODE_ENABLE <bitmask of units>
57 Alternatively, to load the driver as a
58 module at boot time, place the following lines in
60 .Bd -literal -offset indent
67 This driver provides access to the
69 bus(es) connected to the Adaptec AIC77xx and AIC78xx
72 Driver features include support for twin and wide busses,
73 fast, ultra or ultra2 synchronous transfers depending on controller type,
74 tagged queueing, SCB paging, and target mode.
76 Memory mapped I/O can be enabled for PCI devices with the
77 .Dq Dv AHC_ALLOW_MEMIO
79 Memory mapped I/O is more efficient than the alternative, programmed I/O.
80 Most PCI BIOSes will map devices so that either technique for communicating
81 with the card is available.
83 usually when the PCI device is sitting behind a PCI->PCI bridge,
84 the BIOS may fail to properly initialize the chip for memory mapped I/O.
85 The typical symptom of this problem is a system hang if memory mapped I/O
87 Most modern motherboards perform the initialization correctly and work fine
88 with this option enabled.
90 Individual controllers may be configured to operate in the target role
92 .Dq Dv AHC_TMODE_ENABLE
94 The value assigned to this option should be a bitmap
95 of all units where target mode is desired.
96 For example, a value of 0x25, would enable target mode on units 0, 2, and 5.
97 A value of 0x8a enables it for units 1, 3, and 7.
99 Per target configuration performed in the
101 menu, accessible at boot
107 configuration utility for
110 is honored by this driver.
111 This includes synchronous/asynchronous transfers,
112 maximum synchronous negotiation rate,
115 the host adapter's SCSI ID,
119 Twin Channel controllers,
120 the primary channel selection.
121 For systems that store non-volatile settings in a system specific manner
122 rather than a serial eeprom directly connected to the aic7xxx controller,
125 must be enabled for the driver to access this information.
126 This restriction applies to all
128 and many motherboard configurations.
130 Note that I/O addresses are determined automatically by the probe routines,
131 but care should be taken when using a 284x
132 .Pq Tn VESA No local bus controller
136 The jumpers setting the I/O area for the 284x should match the
138 slot into which the card is inserted to prevent conflicts with other
142 Performance and feature sets vary throughout the aic7xxx product line.
143 The following table provides a comparison of the different chips supported
147 Note that wide and twin channel features, although always supported
148 by a particular chip, may be disabled in a particular motherboard or card
151 .Bd -ragged -offset indent
152 .Bl -column "aic7770 " "10 " "EISA/VL " "10MHz " "16bit " "SCBs " Features
153 .Em "Chip MIPS Bus MaxSync MaxWidth SCBs Features"
154 aic7770 10 EISA/VL 10MHz 16Bit 4 1
155 aic7850 10 PCI/32 10MHz 8Bit 3
156 aic7860 10 PCI/32 20MHz 8Bit 3
157 aic7870 10 PCI/32 10MHz 16Bit 16
158 aic7880 10 PCI/32 20MHz 16Bit 16
159 aic7890 20 PCI/32 40MHz 16Bit 16 3 4 5 6 7 8
160 aic7891 20 PCI/64 40MHz 16Bit 16 3 4 5 6 7 8
161 aic7892 20 PCI/64 80MHz 16Bit 16 3 4 5 6 7 8
162 aic7895 15 PCI/32 20MHz 16Bit 16 2 3 4 5
163 aic7895C 15 PCI/32 20MHz 16Bit 16 2 3 4 5 8
164 aic7896 20 PCI/32 40MHz 16Bit 16 2 3 4 5 6 7 8
165 aic7897 20 PCI/64 40MHz 16Bit 16 2 3 4 5 6 7 8
166 aic7899 20 PCI/64 80MHz 16Bit 16 2 3 4 5 6 7 8
171 Multiplexed Twin Channel Device - One controller servicing two busses.
173 Multi-function Twin Channel Device - Two controllers on one chip.
175 Command Channel Secondary DMA Engine - Allows scatter gather list and
178 64 Byte SCB Support - SCSI CDB is embedded in the SCB to eliminate an extra DMA.
180 Block Move Instruction Support - Doubles the speed of certain sequencer
184 style Scatter Gather Engine - Improves S/G prefetch performance.
186 Queuing Registers - Allows queueing of new transactions without pausing the
189 Multiple Target IDs - Allows the controller to respond to selection as a
190 target on multiple SCSI IDs.
196 driver supports the following
198 host adapter chips and
354 NEC PC-9821Xt13 (PC-98)
358 NEC PC-9821X-B02L/B09 (PC-98)
360 NEC SV-98/2-B03 (PC-98)
362 Many motherboards with on-board
366 .Sh SCSI CONTROL BLOCKS (SCBs)
367 Every transaction sent to a device on the SCSI bus is assigned a
368 .Sq SCSI Control Block
370 The SCB contains all of the information required by the
371 controller to process a transaction.
372 The chip feature table lists
373 the number of SCBs that can be stored in on-chip memory.
375 with model numbers greater than or equal to 7870 allow for the on chip
376 SCB space to be augmented with external SRAM up to a maximum of 255 SCBs.
377 Very few Adaptec controller configurations have external SRAM.
379 If external SRAM is not available, SCBs are a limited resource.
380 Using the SCBs in a straight forward manner would only allow the driver to
381 handle as many concurrent transactions as there are physical SCBs.
382 To fully utilize the SCSI bus and the devices on it,
383 requires much more concurrency.
384 The solution to this problem is
386 a concept similar to memory paging.
387 SCB paging takes advantage of
388 the fact that devices usually disconnect from the SCSI bus for long
389 periods of time without talking to the controller.
390 The SCBs for disconnected transactions are only of use to the controller
391 when the transfer is resumed.
392 When the host queues another transaction
393 for the controller to execute, the controller firmware will use a
394 free SCB if one is available.
395 Otherwise, the state of the most recently
396 disconnected (and therefore most likely to stay disconnected) SCB is
397 saved, via dma, to host memory, and the local SCB reused to start
399 This allows the controller to queue up to
400 255 transactions regardless of the amount of SCB space.
402 local SCB space serves as a cache for disconnected transactions, the
403 more SCB space available, the less host bus traffic consumed saving
404 and restoring SCB data.
422 sequencer-code assembler,
423 and the firmware running on the aic7xxx chips was written by
424 .An Justin T. Gibbs .
426 Some Quantum drives (at least the Empire 2100 and 1080s) will not run on an
428 Rev B in synchronous mode at 10MHz.
429 Controllers with this problem have a
430 42 MHz clock crystal on them and run slightly above 10MHz.
431 This confuses the drive and hangs the bus.
432 Setting a maximum synchronous negotiation rate of 8MHz in the
434 utility will allow normal operation.
436 Although the Ultra2 and Ultra160 products have sufficient instruction
437 ram space to support both the initiator and target roles concurrently,
438 this configuration is disabled in favor of allowing the target role
439 to respond on multiple target ids.
440 A method for configuring dual role mode should be provided.
442 Tagged Queuing is not supported in target mode.
444 Reselection in target mode fails to function correctly on all high
445 voltage differential boards as shipped by Adaptec.
447 how to modify HVD board to work correctly in target mode is available