3 * ===================================
4 * HARP | Host ATM Research Platform
5 * ===================================
8 * This Host ATM Research Platform ("HARP") file (the "Software") is
9 * made available by Network Computing Services, Inc. ("NetworkCS")
10 * "AS IS". NetworkCS does not provide maintenance, improvements or
11 * support of any kind.
13 * NETWORKCS MAKES NO WARRANTIES OR REPRESENTATIONS, EXPRESS OR IMPLIED,
14 * INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY
15 * AND FITNESS FOR A PARTICULAR PURPOSE, AS TO ANY ELEMENT OF THE
16 * SOFTWARE OR ANY SUPPORT PROVIDED IN CONNECTION WITH THIS SOFTWARE.
17 * In no event shall NetworkCS be responsible for any damages, including
18 * but not limited to consequential damages, arising from or relating to
19 * any use of the Software or related support.
21 * Copyright 1994-1998 Network Computing Services, Inc.
23 * Copies of this Software may be made, however, the above copyright
24 * notice must be reproduced on all copies.
26 * @(#) $FreeBSD: src/sys/dev/hea/eni.h,v 1.2 1999/08/28 00:41:43 peter Exp $
27 * @(#) $DragonFly: src/sys/dev/atm/hea/eni.h,v 1.3 2003/08/07 21:16:49 dillon Exp $
32 * Efficient ENI Adapter Support
34 * Protocol and implementation definitions
41 #include <bus/pci/pcireg.h>
42 #include <bus/pci/pcivar.h>
45 * Physical device name - used to configure HARP devices
48 #define ENI_DEV_NAME "hea" /* HARP Efficient ATM */
51 #define ENI_MAX_UNITS 4
53 #define ENI_IFF_MTU 9188
54 #define ENI_MAX_VCI 1023 /* 0 - 1023 */
57 #define ENI_IFQ_MAXLEN 1000 /* rx/tx queue lengths */
61 * Size of small and large receive buffers
63 #define ENI_SMALL_BSIZE 64
64 #define ENI_LARGE_BSIZE MCLBYTES
68 * ENI memory map offsets IN WORDS, not bytes
70 * The Efficient Adapter implements a 4 MB address space. The lower
71 * 2 MB are used by bootprom (E)EPROM and by chipset registers such
72 * as the MIDWAY and SUNI chips. The (upto) upper 2 MB is used for
73 * RAM. Of the RAM, the lower 28 KB is used for fixed tables - the
74 * VCI table, the RX and TX DMA queues, and the Service List queue.
75 * Memory above the 28 KB range is available for RX and TX buffers.
77 * NOTE: Access to anything other then the (E)EPROM MUST be as a 32 bit
78 * access. Also note that Efficient uses both byte addresses and word
79 * addresses when describing offsets. BE CAREFUL or you'll get confused!
82 * Size of memory space reserved for registers and expansion (e)eprom.
84 #define ENI_REG_SIZE 0x200000 /* Two megabytes */
86 #define SUNI_OFFSET 0x008000 /* SUNI chip registers */
87 #define MIDWAY_OFFSET 0x010000 /* MIDWAY chip registers */
88 #define RAM_OFFSET 0x080000 /* Adapter RAM */
89 #define VCITBL_OFFSET 0x080000 /* VCI Table offset */
90 #define RXQUEUE_OFFSET 0x081000 /* RX DMA Queue offset */
91 #define TXQUEUE_OFFSET 0x081400 /* TX DMA Queue offset */
92 #define SVCLIST_OFFSET 0x081800 /* SVC List Queue offset */
94 #define SEGBUF_BASE 0x007000 /* Base from start of RAM */
96 #define DMA_LIST_SIZE 512 /* 1024 words / 2 words per entry */
97 #define SVC_LIST_SIZE 1024 /* 1024 words / 1 word per entry */
100 * Values for testing size of RAM on adapter
102 * Efficient has (at least) two different memory sizes available. One
103 * is a client card which has either 128 KB or 512 KB RAM, the other
104 * is a server card which has 2 MB RAM. The driver will size and test
105 * the memory to correctly determine what's available.
107 #define MAX_ENI_MEM 0x200000 /* 2 MB - max. mem supported */
108 #define TEST_STEP 0x000400 /* Look at 1 KB steps */
109 #define TEST_PAT 0xA5A5A5A5 /* Test pattern */
112 * Values for memory allocator
114 #define ENI_BUF_PGSZ 1024 /* Allocation unit of buffers */
115 #define ENI_BUF_NBIT 8 /* Number of bits to get from */
116 /* min buffer (1KB) to max (128KB) */
119 * Values for allocating TX buffers
121 #define MAX_CLIENT_RAM 512 /* Most RAM a client card will have */
122 #define TX_SMALL_BSIZE 32 /* Small buffer - 32KB */
123 #define TX_LARGE_BSIZE 128 /* Large buffer - 128KB */
126 * Values for allocating RX buffers
128 #define RX_SIG_BSIZE 4 /* Signalling buffer - 4KB */
129 #define RX_CLIENT_BSIZE 16 /* Client buffer - 16KB */
130 #define RX_SERVER_BSIZE 32 /* Server buffer - 32KB */
133 * Adapter bases all addresses off of some power from 1KB. Thus, it
134 * only needs to store the most sigificant bits and can drop the lower
137 #define ENI_LOC_PREDIV 10 /* Bits location is shifted */
138 /* Location is prescaled by 1KB */
139 /* before use in various places */
141 #define MIDWAY_DELAY 10 /* Time to wait for Midway finish */
144 * Define the MIDWAY register offsets and any interesting bits within
147 #define MIDWAY_ID 0x00 /* ID/Reset register */
148 #define MIDWAY_RESET 0 /* iWrite of any value */
149 #define ID_SHIFT 27 /* Midway ID version */
150 #define ID_MASK 0x1F /* ID mask */
151 #define MID_SHIFT 7 /* Mother board ID */
152 #define MID_MASK 0x7 /* MID mask */
153 #define DID_SHIFT 0 /* Daughter board ID */
154 #define DID_MASK 0x1F /* DID mask */
156 * Efficient defines the following IDs for their adapters:
157 * 0x420/0x620 - SONET MMF, client memory size
158 * 0x430/0x630 - SONET MMF, server memory size
159 * 0x424/0x624 - UTP-5, client memory size
160 * 0x434/0x634 - UTP-5, server memory size
162 #define MEDIA_MASK 0x04 /* Mask off UTP-5/MMF media */
164 #define MIDWAY_ISA 0x01 /* Interrupt Status Ack. */
165 /* Reading this register */
166 /* also acknowledges the */
167 /* posted interrupt(s) */
169 #define MIDWAY_IS 0x02 /* Interrupt Status */
170 /* Reading this register */
171 /* does NOT acknowledge the */
172 /* posted interrupt(s) */
173 /* Interrupt names */
174 #define ENI_INT_STAT 0x00000001
175 #define ENI_INT_SUNI 0x00000002
176 #define ENI_INT_SERVICE 0x00000004
177 #define ENI_INT_TX_DMA 0x00000008
178 #define ENI_INT_RX_DMA 0x00000010
179 #define ENI_INT_DMA_ERR 0x00000020
180 #define ENI_INT_DMA_LERR 0x00000040
181 #define ENI_INT_IDEN 0x00000080
182 #define ENI_INT_DMA_OVFL 0x00000100
183 #define ENI_INT_TX_MASK 0x0001FE00
185 #define MIDWAY_IE 0x03 /* Interrupt Enable register */
186 /* Interrupt enable bits are the same as the Interrupt names */
188 #define MIDWAY_MASTER 0x04 /* Master Control */
189 /* Master control bits */
190 #define ENI_M_WAIT500 0x00000001 /* Disable interrupts .5 ms */
191 #define ENI_M_WAIT1 0x00000002 /* Disable interrupts 1 ms */
192 #define ENI_M_RXENABLE 0x00000004 /* Enable RX engine */
193 #define ENI_M_TXENABLE 0x00000008 /* Enable TX engine */
194 #define ENI_M_DMAENABLE 0x00000010 /* Enable DMA */
195 #define ENI_M_TXLOCK 0x00000020 /* 0: Streaming, 1: Lock */
196 #define ENI_M_INTSEL 0x000001C0 /* Int Select mask */
197 #define ENI_ISEL_SHIFT 6 /* Bits to shift ISEL value */
199 #define MIDWAY_STAT 0x05 /* Statistics register */
201 #define MIDWAY_SVCWR 0x06 /* Svc List write pointer */
202 #define SVC_SIZE_MASK 0x3FF /* Valid bits in svc pointer */
204 #define MIDWAY_DMAADDR 0x07 /* Current virtual DMA addr */
206 #define MIDWAY_RX_WR 0x08 /* Write ptr to RX DMA queue */
208 #define MIDWAY_RX_RD 0x09 /* Read ptr to RX DMA queue */
210 #define MIDWAY_TX_WR 0x0A /* Write ptr to TX DMA queue */
212 #define MIDWAY_TX_RD 0x0B /* Read ptr to TX DMA queue */
215 * Registers 0x0C - 0x0F are unused
219 * MIDWAY supports 8 transmit channels. Each channel has 3 registers
220 * to control operation. Each new channel starts on N * 4 set. Thus,
221 * channel 0 uses register 0x10 - 0x13, channel 1 uses 0x14 - 0x17, etc.
222 * Register 0x13 + N * 4 is unused.
225 #define MIDWAY_TXPLACE 0x10 /* Channel N TX location */
226 #define TXSIZE_SHIFT 11 /* Bits to shift size by */
227 #define TX_PLACE_MASK 0x7FF /* Valid bits in TXPLACE */
229 #define MIDWAY_RDPTR 0x11 /* Channel N Read ptr */
231 #define MIDWAY_DESCR 0x12 /* Channel N Descr ptr */
234 * Register 0x30 on up are unused
238 * Part of PCI configuration registers but not defined in <pci/pcireg.h>
240 #define PCI_CONTROL_REG 0x60
241 #define ENDIAN_SWAP_DMA 0x80 /* Enable endian swaps on DMA */
244 * The Efficient adapter references adapter RAM through the use of
245 * location and size values. Eight sizes are defined. When allocating
246 * buffers, there size must be rounded up to the next size which will
247 * hold the requested size. Buffers are allocated on 'SIZE' boundaries.
248 * See eni_buffer.c for more info.
252 * Buffer SIZE definitions - in words, so from 1 KB to 128 KB
254 #define SIZE_256 0x00
255 #define SIZE_512 0x01
260 #define SIZE_16K 0x06
261 #define SIZE_32K 0x07
264 * Define values for DMA type - DMA descriptors include a type field and a
265 * count field except in the special case of JK (just-kidding). With type JK,
266 * the count field should be set to the address which will be loaded
267 * into the pointer, ie. where the pointer should next point to, since
268 * JK doesn't have a "size" associated with it. JK DMA is used to skip
269 * over descriptor words, and to strip off padding of AAL5 PDUs. The
270 * DMA_nWORDM types will do a n word DMA burst, but the count field
271 * does not have to equal n. Any difference results in garbage filling
272 * the remaining words of the DMA. These types could be used where a
273 * particular burst size yields better DMA performance.
275 #define DMA_WORD 0x00
276 #define DMA_BYTE 0x01
277 #define DMA_HWORD 0x02
279 #define DMA_4WORD 0x04
280 #define DMA_8WORD 0x05
281 #define DMA_16WORD 0x06
282 #define DMA_2WORD 0x07
283 #define DMA_4WORDM 0x0C
284 #define DMA_8WORDM 0x0D
285 #define DMA_16WORDM 0x0E
286 #define DMA_2WORDM 0x0F
289 * Define the size of the local DMA list we'll build before
290 * giving up on the PDU.
292 #define TEMP_DMA_SIZE 120 /* Enough for 58/59 buffers */
294 #define DMA_COUNT_SHIFT 16 /* Number of bits to shift count */
295 /* in DMA descriptor word */
296 #define DMA_VCC_SHIFT 6 /* Number of bits to shift RX VCC or */
297 /* TX channel in DMA descriptor word */
298 #define DMA_END_BIT 0x20 /* Signal end of DMA list */
301 * Defines for VCI table
303 * The VCI table is a 1K by 4 word table allowing up to 1024 (0-1023)
304 * VCIs. Entries into the table use the VCI number as the index.
307 u_long vci_control; /* Control word */
308 u_long vci_descr; /* Descr/ReadPtr */
309 u_long vci_write; /* WritePtr/State/Cell count */
310 u_long vci_crc; /* ongoing CRC calculation */
312 typedef volatile struct vci_table VCI_Table;
314 #define VCI_MODE_SHIFT 30 /* Shift to get MODE field */
315 #define VCI_MODE_MASK 0x3FFFFFFF /* Bits to strip MODE off */
316 #define VCI_PTI_SHIFT 29 /* Shift to get PTI mode field */
317 #define VCI_LOC_SHIFT 18 /* Shift to get location field */
318 #define VCI_LOC_MASK 0x7FF /* Valid bits in location field */
319 #define VCI_SIZE_SHIFT 15 /* Shift to get size field */
320 #define VCI_SIZE_MASK 7 /* Valid bits in size field */
321 #define VCI_IN_SERVICE 1 /* Mask for IN_SERVICE field */
324 * Defines for VC mode
326 #define VCI_MODE_TRASH 0x00 /* Trash all cells for this VC */
327 #define VCI_MODE_AAL0 0x01 /* Reassemble as AAL_0 PDU */
328 #define VCI_MODE_AAL5 0x02 /* Reassemble as AAL_5 PDU */
330 * Defines for handling cells with PTI(2) set to 1.
332 #define PTI_MODE_TRASH 0x00 /* Trash cell */
333 #define PTI_MODE_PRESV 0x01 /* Send cell to OAM channel */
335 * Current state of VC
337 #define VCI_STATE_IDLE 0x00 /* VC is idle */
338 #define VCI_STATE_REASM 0x01 /* VC is reassembling PDU */
339 #define VCI_STATE_TRASH 0x03 /* VC is trashing cells */
342 * RX Descriptor word values
344 #define DESCR_TRASH_BIT 0x1000 /* VCI was trashing cells */
345 #define DESCR_CRC_ERR 0x0800 /* PDU has CRC error */
346 #define DESCR_CELL_COUNT 0x07FF /* Mask to get cell count */
348 * TX Descriptor word values
350 #define TX_IDEN_SHIFT 28 /* Unique identifier location */
351 #define TX_MODE_SHIFT 27 /* AAL5 or AAL0 */
352 #define TX_VCI_SHIFT 4 /* Bits to shift VCI value */
355 * When setting up descriptor words (at head of segmentation queues), there
356 * is a unique identifier used to help detect sync problems.
358 #define MIDWAY_UNQ_ID 0x0B
361 * Defines for cell sizes
363 #define BYTES_PER_CELL 48 /* Number of data bytes per cell */
364 #define WORDS_PER_CELL 12 /* Number of data words per cell */
367 * Access to Serial EEPROM [as opposed to expansion (E)PROM].
369 * This is a ATMEL AT24C01 serial EEPROM part.
370 * See http://www.atmel.com/atmel/products/prod162.htm for timimg diagrams
371 * for START/STOP/ACK/READ cycles.
373 #define SEEPROM PCI_CONTROL_REG /* Serial EEPROM is accessed thru */
374 /* PCI control register */
375 #define SEPROM_DATA 0x02 /* SEEPROM DATA line */
376 #define SEPROM_CLK 0x01 /* SEEPROM CLK line */
377 #define SEPROM_SIZE 128 /* Size of Serial EEPROM */
378 #define SEPROM_MAC_OFF 64 /* Offset to MAC address */
379 #define SEPROM_SN_OFF 112 /* Offset to serial number */
380 #define SEPROM_DELAY 10 /* Delay when strobing CLK/DATA lines */
383 * Host protocol control blocks
390 * Contains the common and ENI-specific information for each VCC
391 * which is opened through a ENI device.
394 struct cmn_vcc ev_cmn; /* Common VCC stuff */
395 caddr_t ev_rxbuf; /* Receive buffer */
396 u_long ev_rxpos; /* Adapter buffer read pointer */
398 typedef struct eni_vcc Eni_vcc;
400 #define ev_next ev_cmn.cv_next
401 #define ev_toku ev_cmn.cv_toku
402 #define ev_upper ev_cmn.cv_upper
403 #define ev_connvc ev_cmn.cv_connvc
404 #define ev_state ev_cmn.cv_state
406 typedef volatile unsigned long * Eni_mem;
409 * Define the ID's we'll look for in the PCI config
410 * register when deciding if we'll support this device.
411 * The DEV_ID will need to be turned into an array of
412 * ID's in order to support multiple adapters with
415 #define EFF_VENDOR_ID 0x111A
416 #define EFF_DEV_ID 0x0002
419 * Memory allocator defines and buffer descriptors
424 typedef struct mbd Mbd;
428 caddr_t base; /* Adapter base address */
429 int size; /* Size of buffer */
430 int state; /* INUSE or FREE */
434 * We use a hack to allocate a smaller RX buffer for signalling
435 * channels as they tend to have small MTU lengths.
437 #define UNI_SIG_VCI 5
440 * Device Unit Structure
442 * Contains all the information for a single device (adapter).
445 Cmn_unit eu_cmn; /* Common unit stuff */
446 pcici_t eu_pcitag; /* PCI tag */
447 Eni_mem eu_base; /* Adapter memory base */
448 Eni_mem eu_ram; /* Adapter RAM */
451 Eni_mem eu_suni; /* SUNI registers */
453 Eni_mem eu_midway; /* MIDWAY registers */
455 VCI_Table *eu_vcitbl; /* VCI Table */
456 Eni_mem eu_rxdma; /* Receive DMA queue */
457 Eni_mem eu_txdma; /* Transmit DMA queue */
458 Eni_mem eu_svclist; /* Service list */
459 u_long eu_servread; /* Read pointer into Service list */
461 caddr_t eu_txbuf; /* One large TX buff for everything */
462 u_long eu_txsize; /* Size of TX buffer */
463 u_long eu_txpos; /* Current word being stored in RAM */
464 u_long eu_txfirst; /* First word of unack'ed data */
469 struct ifqueue eu_txqueue;
471 struct ifqueue eu_rxqueue;
472 u_long eu_rxdmawr; /* DMA list write pointer */
474 u_char eu_seeprom[SEPROM_SIZE]; /* Serial EEPROM contents */
475 u_int eu_sevar; /* Unique (per unit) seeprom var. */
477 Mbd *eu_memmap; /* Adapter RAM memory allocator map */
478 int eu_memclicks[ENI_BUF_NBIT];/* Count of INUSE buffers */
480 Eni_stats eu_stats; /* Statistics */
483 typedef struct eni_unit Eni_unit;
485 #define eu_pif eu_cmn.cu_pif
486 #define eu_unit eu_cmn.cu_unit
487 #define eu_flags eu_cmn.cu_flags
488 #define eu_mtu eu_cmn.cu_mtu
489 #define eu_open_vcc eu_cmn.cu_open_vcc
490 #define eu_vcc eu_cmn.cu_vcc
491 #define eu_vcc_pool eu_cmn.cu_vcc_pool
492 #define eu_nif_pool eu_cmn.cu_nif_pool
493 #define eu_ioctl eu_cmn.cu_ioctl
494 #define eu_instvcc eu_cmn.cu_instvcc
495 #define eu_openvcc eu_cmn.cu_openvcc
496 #define eu_closevcc eu_cmn.cu_closevcc
497 #define eu_output eu_cmn.cu_output
498 #define eu_config eu_cmn.cu_config
500 #endif /* _ENI_ENI_H */