2 * Product specific probe and attach routines for:
3 * aic7901 and aic7902 SCSI controllers
5 * Copyright (c) 1994-2001 Justin T. Gibbs.
6 * Copyright (c) 2000-2002 Adaptec Inc.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
16 * substantially similar to the "NO WARRANTY" disclaimer below
17 * ("Disclaimer") and any redistribution must be conditioned upon
18 * including a substantially similar Disclaimer requirement for further
19 * binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
37 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
38 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
39 * POSSIBILITY OF SUCH DAMAGES.
41 * $Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#75 $
43 * $FreeBSD: src/sys/dev/aic7xxx/aic79xx_pci.c,v 1.3.2.5 2003/06/10 03:26:07 gibbs Exp $
44 * $DragonFly: src/sys/dev/disk/aic7xxx/aic79xx_pci.c,v 1.6 2007/01/27 15:03:25 swildner Exp $
48 #include "aic79xx_osm.h"
49 #include "aic79xx_inline.h"
51 #include "aic79xx_osm.h"
52 #include "aic79xx_inline.h"
55 static __inline uint64_t
56 ahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor)
62 | ((uint64_t)vendor << 32)
63 | ((uint64_t)device << 48);
68 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull
69 #define ID_ALL_IROC_MASK 0xFFFFFF7FFFFFFFFFull
70 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull
71 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull
72 #define ID_9005_GENERIC_IROC_MASK 0xFFF0FF7F00000000ull
74 #define ID_AIC7901 0x800F9005FFFF9005ull
75 #define ID_AHA_29320A 0x8000900500609005ull
76 #define ID_AHA_29320ALP 0x8017900500449005ull
78 #define ID_AIC7901A 0x801E9005FFFF9005ull
79 #define ID_AHA_29320 0x8012900500429005ull
80 #define ID_AHA_29320B 0x8013900500439005ull
81 #define ID_AHA_29320LP 0x8014900500449005ull
83 #define ID_AIC7902 0x801F9005FFFF9005ull
84 #define ID_AIC7902_B 0x801D9005FFFF9005ull
85 #define ID_AHA_39320 0x8010900500409005ull
86 #define ID_AHA_39320_B 0x8015900500409005ull
87 #define ID_AHA_39320A 0x8016900500409005ull
88 #define ID_AHA_39320D 0x8011900500419005ull
89 #define ID_AHA_39320D_B 0x801C900500419005ull
90 #define ID_AHA_39320D_HP 0x8011900500AC0E11ull
91 #define ID_AHA_39320D_B_HP 0x801C900500AC0E11ull
92 #define ID_AIC7902_PCI_REV_A4 0x3
93 #define ID_AIC7902_PCI_REV_B0 0x10
94 #define SUBID_HP 0x0E11
96 #define DEVID_9005_TYPE(id) ((id) & 0xF)
97 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */
98 #define DEVID_9005_TYPE_HBA_2EXT 0x1 /* 2 External Ports */
99 #define DEVID_9005_TYPE_IROC 0x8 /* Raid(0,1,10) Card */
100 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */
102 #define DEVID_9005_MFUNC(id) ((id) & 0x10)
104 #define DEVID_9005_PACKETIZED(id) ((id) & 0x8000)
106 #define SUBID_9005_TYPE(id) ((id) & 0xF)
107 #define SUBID_9005_TYPE_HBA 0x0 /* Standard Card */
108 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */
110 #define SUBID_9005_AUTOTERM(id) (((id) & 0x10) == 0)
112 #define SUBID_9005_LEGACYCONN_FUNC(id) ((id) & 0x20)
114 #define SUBID_9005_SEEPTYPE(id) ((id) & 0x0C0) >> 6)
115 #define SUBID_9005_SEEPTYPE_NONE 0x0
116 #define SUBID_9005_SEEPTYPE_4K 0x1
118 static ahd_device_setup_t ahd_aic7901_setup;
119 static ahd_device_setup_t ahd_aic7901A_setup;
120 static ahd_device_setup_t ahd_aic7902_setup;
122 struct ahd_pci_identity ahd_pci_ident_table [] =
124 /* aic7901 based controllers */
128 "Adaptec 29320A Ultra320 SCSI adapter",
134 "Adaptec 29320ALP Ultra320 SCSI adapter",
137 /* aic7901A based controllers */
141 "Adaptec 29320 Ultra320 SCSI adapter",
147 "Adaptec 29320B Ultra320 SCSI adapter",
153 "Adaptec 29320LP Ultra320 SCSI adapter",
156 /* aic7902 based controllers */
160 "Adaptec 39320 Ultra320 SCSI adapter",
166 "Adaptec 39320 Ultra320 SCSI adapter",
172 "Adaptec 39320A Ultra320 SCSI adapter",
178 "Adaptec 39320D Ultra320 SCSI adapter",
184 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter",
190 "Adaptec 39320D Ultra320 SCSI adapter",
196 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter",
202 "Adaptec 29320 Ultra320 SCSI adapter",
208 "Adaptec 29320B Ultra320 SCSI adapter",
211 /* Generic chip probes for devices we don't know 'exactly' */
213 ID_AIC7901 & ID_DEV_VENDOR_MASK,
215 "Adaptec AIC7901 Ultra320 SCSI adapter",
219 ID_AIC7901A & ID_DEV_VENDOR_MASK,
221 "Adaptec AIC7901A Ultra320 SCSI adapter",
225 ID_AIC7902 & ID_9005_GENERIC_MASK,
226 ID_9005_GENERIC_MASK,
227 "Adaptec AIC7902 Ultra320 SCSI adapter",
232 const u_int ahd_num_pci_devs = NUM_ELEMENTS(ahd_pci_ident_table);
234 #define DEVCONFIG 0x40
235 #define PCIXINITPAT 0x0000E000ul
236 #define PCIXINIT_PCI33_66 0x0000E000ul
237 #define PCIXINIT_PCIX50_66 0x0000C000ul
238 #define PCIXINIT_PCIX66_100 0x0000A000ul
239 #define PCIXINIT_PCIX100_133 0x00008000ul
240 #define PCI_BUS_MODES_INDEX(devconfig) \
241 (((devconfig) & PCIXINITPAT) >> 13)
242 static const char *pci_bus_modes[] =
244 "PCI bus mode unknown",
245 "PCI bus mode unknown",
246 "PCI bus mode unknown",
247 "PCI bus mode unknown",
254 #define TESTMODE 0x00000800ul
255 #define IRDY_RST 0x00000200ul
256 #define FRAME_RST 0x00000100ul
257 #define PCI64BIT 0x00000080ul
258 #define MRDCEN 0x00000040ul
259 #define ENDIANSEL 0x00000020ul
260 #define MIXQWENDIANEN 0x00000008ul
261 #define DACEN 0x00000004ul
262 #define STPWLEVEL 0x00000002ul
263 #define QWENDIANSEL 0x00000001ul
265 #define DEVCONFIG1 0x44
268 #define CSIZE_LATTIME 0x0c
269 #define CACHESIZE 0x000000fful
270 #define LATTIME 0x0000ff00ul
272 static int ahd_check_extport(struct ahd_softc *ahd);
273 static void ahd_configure_termination(struct ahd_softc *ahd,
274 u_int adapter_control);
275 static void ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat);
277 struct ahd_pci_identity *
278 ahd_find_pci_device(ahd_dev_softc_t pci)
285 struct ahd_pci_identity *entry;
288 vendor = ahd_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2);
289 device = ahd_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2);
290 subvendor = ahd_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2);
291 subdevice = ahd_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2);
292 full_id = ahd_compose_id(device,
297 for (i = 0; i < ahd_num_pci_devs; i++) {
298 entry = &ahd_pci_ident_table[i];
299 if (entry->full_id == (full_id & entry->id_mask)) {
300 /* Honor exclusion entries. */
301 if (entry->name == NULL)
310 ahd_pci_config(struct ahd_softc *ahd, struct ahd_pci_identity *entry)
312 struct scb_data *shared_scb_data;
318 shared_scb_data = NULL;
319 ahd->description = entry->name;
321 * Record if this is an HP board.
323 subvendor = ahd_pci_read_config(ahd->dev_softc,
324 PCIR_SUBVEND_0, /*bytes*/2);
325 if (subvendor == SUBID_HP)
326 ahd->flags |= AHD_HP_BOARD;
328 error = entry->setup(ahd);
332 devconfig = ahd_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4);
333 if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) {
334 ahd->chip |= AHD_PCI;
335 /* Disable PCIX workarounds when running in PCI mode. */
336 ahd->bugs &= ~AHD_PCIX_BUG_MASK;
338 ahd->chip |= AHD_PCIX;
340 ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)];
342 ahd_power_state_change(ahd, AHD_POWER_STATE_D0);
344 error = ahd_pci_map_registers(ahd);
349 * If we need to support high memory, enable dual
350 * address cycles. This bit must be set to enable
351 * high address bit generation even if we are on a
352 * 64bit bus (PCI64BIT set in devconfig).
354 if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) {
358 kprintf("%s: Enabling 39Bit Addressing\n",
360 devconfig = ahd_pci_read_config(ahd->dev_softc,
361 DEVCONFIG, /*bytes*/4);
363 ahd_pci_write_config(ahd->dev_softc, DEVCONFIG,
364 devconfig, /*bytes*/4);
367 /* Ensure busmastering is enabled */
368 command = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2);
369 command |= PCIM_CMD_BUSMASTEREN;
370 ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, command, /*bytes*/2);
372 error = ahd_softc_init(ahd);
376 ahd->bus_intr = ahd_pci_intr;
378 error = ahd_reset(ahd, /*reinit*/FALSE);
383 ahd_pci_read_config(ahd->dev_softc, CSIZE_LATTIME,
384 /*bytes*/1) & CACHESIZE;
385 ahd->pci_cachesize *= 4;
387 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
388 /* See if we have a SEEPROM and perform auto-term */
389 error = ahd_check_extport(ahd);
393 /* Core initialization */
394 error = ahd_init(ahd);
399 * Allow interrupts now that we are completely setup.
401 error = ahd_pci_map_int(ahd);
406 * Link this softc in with all other ahd instances.
408 ahd_softc_insert(ahd);
413 * Perform some simple tests that should catch situations where
414 * our registers are invalidly mapped.
417 ahd_pci_test_register_access(struct ahd_softc *ahd)
428 * Enable PCI error interrupt status, but suppress NMIs
429 * generated by SERR raised due to target aborts.
431 cmd = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2);
432 ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
433 cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2);
436 * First a simple test to see if any
437 * registers can be read. Reading
438 * HCNTRL has no side effects and has
439 * at least one bit that is guaranteed to
440 * be zero so it is a good register to
443 hcntrl = ahd_inb(ahd, HCNTRL);
448 * Next create a situation where write combining
449 * or read prefetching could be initiated by the
450 * CPU or host bridge. Our device does not support
451 * either, so look for data corruption and/or flaged
454 ahd_outb(ahd, HCNTRL, hcntrl|PAUSE);
455 while (ahd_is_paused(ahd) == 0)
458 /* Clear any PCI errors that occurred before our driver attached. */
459 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
460 targpcistat = ahd_inb(ahd, TARGPCISTAT);
461 ahd_outb(ahd, TARGPCISTAT, targpcistat);
462 pci_status1 = ahd_pci_read_config(ahd->dev_softc,
463 PCIR_STATUS + 1, /*bytes*/1);
464 ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
465 pci_status1, /*bytes*/1);
466 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
467 ahd_outb(ahd, CLRINT, CLRPCIINT);
469 ahd_outb(ahd, SEQCTL0, PERRORDIS);
470 ahd_outl(ahd, SRAM_BASE, 0x5aa555aa);
471 if (ahd_inl(ahd, SRAM_BASE) != 0x5aa555aa)
474 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) {
477 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
478 targpcistat = ahd_inb(ahd, TARGPCISTAT);
479 if ((targpcistat & STA) != 0)
486 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) {
488 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
489 targpcistat = ahd_inb(ahd, TARGPCISTAT);
491 /* Silently clear any latched errors. */
492 ahd_outb(ahd, TARGPCISTAT, targpcistat);
493 pci_status1 = ahd_pci_read_config(ahd->dev_softc,
494 PCIR_STATUS + 1, /*bytes*/1);
495 ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
496 pci_status1, /*bytes*/1);
497 ahd_outb(ahd, CLRINT, CLRPCIINT);
499 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS);
500 ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2);
505 * Check the external port logic for a serial eeprom
506 * and termination/cable detection contrls.
509 ahd_check_extport(struct ahd_softc *ahd)
511 struct vpd_config vpd;
512 struct seeprom_config *sc;
513 u_int adapter_control;
517 sc = ahd->seep_config;
518 have_seeprom = ahd_acquire_seeprom(ahd);
523 * Fetch VPD for this function and parse it.
526 kprintf("%s: Reading VPD from SEEPROM...",
529 /* Address is always in units of 16bit words */
530 start_addr = ((2 * sizeof(*sc))
531 + (sizeof(vpd) * (ahd->channel - 'A'))) / 2;
533 error = ahd_read_seeprom(ahd, (uint16_t *)&vpd,
534 start_addr, sizeof(vpd)/2,
537 error = ahd_parse_vpddata(ahd, &vpd);
539 kprintf("%s: VPD parsing %s\n",
541 error == 0 ? "successful" : "failed");
544 kprintf("%s: Reading SEEPROM...", ahd_name(ahd));
546 /* Address is always in units of 16bit words */
547 start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A');
549 error = ahd_read_seeprom(ahd, (uint16_t *)sc,
550 start_addr, sizeof(*sc)/2,
551 /*bytestream*/FALSE);
554 kprintf("Unable to read SEEPROM\n");
557 have_seeprom = ahd_verify_cksum(sc);
560 if (have_seeprom == 0)
561 kprintf ("checksum error\n");
566 ahd_release_seeprom(ahd);
573 * Pull scratch ram settings and treat them as
574 * if they are the contents of an seeprom if
575 * the 'ADPT', 'BIOS', or 'ASPI' signature is found
576 * in SCB 0xFF. We manually compose the data as 16bit
577 * values to avoid endian issues.
579 ahd_set_scbptr(ahd, 0xFF);
580 nvram_scb = ahd_inb_scbram(ahd, SCB_BASE + NVRAM_SCB_OFFSET);
581 if (nvram_scb != 0xFF
582 && ((ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A'
583 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'D'
584 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P'
585 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'T')
586 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'B'
587 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'I'
588 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'O'
589 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'S')
590 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A'
591 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'S'
592 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P'
593 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'I'))) {
597 ahd_set_scbptr(ahd, nvram_scb);
598 sc_data = (uint16_t *)sc;
599 for (i = 0; i < 64; i += 2)
600 *sc_data++ = ahd_inw_scbram(ahd, SCB_BASE+i);
601 have_seeprom = ahd_verify_cksum(sc);
603 ahd->flags |= AHD_SCB_CONFIG_USED;
608 if (have_seeprom != 0
609 && (ahd_debug & AHD_DUMP_SEEPROM) != 0) {
613 kprintf("%s: Seeprom Contents:", ahd_name(ahd));
614 sc_data = (uint16_t *)sc;
615 for (i = 0; i < (sizeof(*sc)); i += 2)
616 kprintf("\n\t0x%.4x", sc_data[i]);
623 kprintf("%s: No SEEPROM available.\n", ahd_name(ahd));
624 ahd->flags |= AHD_USEDEFAULTS;
625 error = ahd_default_config(ahd);
626 adapter_control = CFAUTOTERM|CFSEAUTOTERM;
627 kfree(ahd->seep_config, M_DEVBUF);
628 ahd->seep_config = NULL;
630 error = ahd_parse_cfgdata(ahd, sc);
631 adapter_control = sc->adapter_control;
636 ahd_configure_termination(ahd, adapter_control);
642 ahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control)
649 devconfig = ahd_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4);
650 devconfig &= ~STPWLEVEL;
651 if ((ahd->flags & AHD_STPWLEVEL_A) != 0)
652 devconfig |= STPWLEVEL;
654 kprintf("%s: STPWLEVEL is %s\n",
655 ahd_name(ahd), (devconfig & STPWLEVEL) ? "on" : "off");
656 ahd_pci_write_config(ahd->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
658 /* Make sure current sensing is off. */
659 if ((ahd->flags & AHD_CURRENT_SENSING) != 0) {
660 (void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0);
664 * Read to sense. Write to set.
666 error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl);
667 if ((adapter_control & CFAUTOTERM) == 0) {
669 kprintf("%s: Manual Primary Termination\n",
671 termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH);
672 if ((adapter_control & CFSTERM) != 0)
673 termctl |= FLX_TERMCTL_ENPRILOW;
674 if ((adapter_control & CFWSTERM) != 0)
675 termctl |= FLX_TERMCTL_ENPRIHIGH;
676 } else if (error != 0) {
677 kprintf("%s: Primary Auto-Term Sensing failed! "
678 "Using Defaults.\n", ahd_name(ahd));
679 termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH;
682 if ((adapter_control & CFSEAUTOTERM) == 0) {
684 kprintf("%s: Manual Secondary Termination\n",
686 termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH);
687 if ((adapter_control & CFSELOWTERM) != 0)
688 termctl |= FLX_TERMCTL_ENSECLOW;
689 if ((adapter_control & CFSEHIGHTERM) != 0)
690 termctl |= FLX_TERMCTL_ENSECHIGH;
691 } else if (error != 0) {
692 kprintf("%s: Secondary Auto-Term Sensing failed! "
693 "Using Defaults.\n", ahd_name(ahd));
694 termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH;
698 * Now set the termination based on what we found.
700 sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN;
701 if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) {
702 ahd->flags |= AHD_TERM_ENB_A;
705 /* Must set the latch once in order to be effective. */
706 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN);
707 ahd_outb(ahd, SXFRCTL1, sxfrctl1);
709 error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl);
711 kprintf("%s: Unable to set termination settings!\n",
713 } else if (bootverbose) {
714 kprintf("%s: Primary High byte termination %sabled\n",
716 (termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis");
718 kprintf("%s: Primary Low byte termination %sabled\n",
720 (termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis");
722 kprintf("%s: Secondary High byte termination %sabled\n",
724 (termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis");
726 kprintf("%s: Secondary Low byte termination %sabled\n",
728 (termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis");
740 static const char *split_status_source[] =
748 static const char *pci_status_source[] =
760 static const char *split_status_strings[] =
762 "%s: Received split response in %s.\n",
763 "%s: Received split completion error message in %s\n",
764 "%s: Receive overrun in %s\n",
765 "%s: Count not complete in %s\n",
766 "%s: Split completion data bucket in %s\n",
767 "%s: Split completion address error in %s\n",
768 "%s: Split completion byte count error in %s\n",
769 "%s: Signaled Target-abort to early terminate a split in %s\n"
772 static const char *pci_status_strings[] =
774 "%s: Data Parity Error has been reported via PERR# in %s\n",
775 "%s: Target initial wait state error in %s\n",
776 "%s: Split completion read data parity error in %s\n",
777 "%s: Split completion address attribute parity error in %s\n",
778 "%s: Received a Target Abort in %s\n",
779 "%s: Received a Master Abort in %s\n",
780 "%s: Signal System Error Detected in %s\n",
781 "%s: Address or Write Phase Parity Error Detected in %s.\n"
785 ahd_pci_intr(struct ahd_softc *ahd)
787 uint8_t pci_status[8];
788 ahd_mode_state saved_modes;
794 intstat = ahd_inb(ahd, INTSTAT);
796 if ((intstat & SPLTINT) != 0)
797 ahd_pci_split_intr(ahd, intstat);
799 if ((intstat & PCIINT) == 0)
802 kprintf("%s: PCI error Interrupt\n", ahd_name(ahd));
803 saved_modes = ahd_save_modes(ahd);
804 ahd_dump_card_state(ahd);
805 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
806 for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) {
810 pci_status[i] = ahd_inb(ahd, reg);
811 /* Clear latched errors. So our interrupt deasserts. */
812 ahd_outb(ahd, reg, pci_status[i]);
815 for (i = 0; i < 8; i++) {
821 for (bit = 0; bit < 8; bit++) {
823 if ((pci_status[i] & (0x1 << bit)) != 0) {
824 static const char *s;
826 s = pci_status_strings[bit];
827 if (i == 7/*TARG*/ && bit == 3)
828 s = "%s: Signaled Target Abort\n";
829 kprintf(s, ahd_name(ahd), pci_status_source[i]);
833 pci_status1 = ahd_pci_read_config(ahd->dev_softc,
834 PCIR_STATUS + 1, /*bytes*/1);
835 ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
836 pci_status1, /*bytes*/1);
837 ahd_restore_modes(ahd, saved_modes);
838 ahd_outb(ahd, CLRINT, CLRPCIINT);
843 ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat)
845 uint8_t split_status[4];
846 uint8_t split_status1[4];
847 uint8_t sg_split_status[2];
848 uint8_t sg_split_status1[2];
849 ahd_mode_state saved_modes;
851 uint16_t pcix_status;
854 * Check for splits in all modes. Modes 0 and 1
855 * additionally have SG engine splits to look at.
857 pcix_status = ahd_pci_read_config(ahd->dev_softc, PCIXR_STATUS,
859 kprintf("%s: PCI Split Interrupt - PCI-X status = 0x%x\n",
860 ahd_name(ahd), pcix_status);
861 saved_modes = ahd_save_modes(ahd);
862 for (i = 0; i < 4; i++) {
863 ahd_set_modes(ahd, i, i);
865 split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0);
866 split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1);
867 /* Clear latched errors. So our interrupt deasserts. */
868 ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]);
869 ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]);
872 sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0);
873 sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1);
874 /* Clear latched errors. So our interrupt deasserts. */
875 ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]);
876 ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]);
879 for (i = 0; i < 4; i++) {
882 for (bit = 0; bit < 8; bit++) {
884 if ((split_status[i] & (0x1 << bit)) != 0) {
885 static const char *s;
887 s = split_status_strings[bit];
888 kprintf(s, ahd_name(ahd),
889 split_status_source[i]);
895 if ((sg_split_status[i] & (0x1 << bit)) != 0) {
896 static const char *s;
898 s = split_status_strings[bit];
899 kprintf(s, ahd_name(ahd), "SG");
904 * Clear PCI-X status bits.
906 ahd_pci_write_config(ahd->dev_softc, PCIXR_STATUS,
907 pcix_status, /*bytes*/2);
908 ahd_outb(ahd, CLRINT, CLRSPLTINT);
909 ahd_restore_modes(ahd, saved_modes);
913 ahd_aic7901_setup(struct ahd_softc *ahd)
917 error = ahd_aic7902_setup(ahd);
920 ahd->chip = AHD_AIC7901;
925 ahd_aic7901A_setup(struct ahd_softc *ahd)
929 error = ahd_aic7902_setup(ahd);
932 ahd->chip = AHD_AIC7901A;
937 ahd_aic7902_setup(struct ahd_softc *ahd)
942 pci = ahd->dev_softc;
943 rev = ahd_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
944 if (rev < ID_AIC7902_PCI_REV_A4) {
945 kprintf("%s: Unable to attach to unsupported chip revision %d\n",
947 ahd_pci_write_config(pci, PCIR_COMMAND, 0, /*bytes*/2);
950 ahd->channel = ahd_get_pci_function(pci) + 'A';
951 ahd->chip = AHD_AIC7902;
952 ahd->features = AHD_AIC7902_FE;
953 if (rev < ID_AIC7902_PCI_REV_B0) {
955 * Enable A series workarounds.
957 ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG
958 | AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG
959 | AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG
960 | AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG
961 | AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG
962 | AHD_PCIX_CHIPRST_BUG|AHD_PCIX_SCBRAM_RD_BUG
963 | AHD_PKTIZED_STATUS_BUG|AHD_PKT_LUN_BUG
964 | AHD_MDFF_WSCBPTR_BUG|AHD_REG_SLOW_SETTLE_BUG
965 | AHD_SET_MODE_BUG|AHD_BUSFREEREV_BUG
966 | AHD_NONPACKFIFO_BUG|AHD_PACED_NEGTABLE_BUG
970 * IO Cell paramter setup.
972 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29);
974 if ((ahd->flags & AHD_HP_BOARD) == 0)
975 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVA);
979 ahd->features |= AHD_RTI|AHD_NEW_IOCELL_OPTS
980 | AHD_NEW_DFCNTRL_OPTS;
981 ahd->bugs |= AHD_LQOOVERRUN_BUG|AHD_ABORT_LQI_BUG
982 | AHD_INTCOLLISION_BUG|AHD_EARLY_REQ_BUG;
985 * IO Cell paramter setup.
987 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29);
988 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB);
989 AHD_SET_AMPLITUDE(ahd, AHD_AMPLITUDE_DEF);
992 * Set the PREQDIS bit for H2B which disables some workaround
993 * that doesn't work on regular PCI busses.
994 * XXX - Find out exactly what this does from the hardware
997 devconfig1 = ahd_pci_read_config(pci, DEVCONFIG1, /*bytes*/1);
998 ahd_pci_write_config(pci, DEVCONFIG1,
999 devconfig1|PREQDIS, /*bytes*/1);
1000 devconfig1 = ahd_pci_read_config(pci, DEVCONFIG1, /*bytes*/1);