2 * Copyright (c) 1999,2000,2001 Jonathan Lemon
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * $FreeBSD: src/sys/dev/gx/if_gx.c,v 1.2.2.3 2001/12/14 19:51:39 jlemon Exp $
30 * $DragonFly: src/sys/dev/netif/gx/Attic/if_gx.c,v 1.26 2006/12/22 23:26:20 swildner Exp $
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/sockio.h>
37 #include <sys/malloc.h>
38 #include <sys/kernel.h>
39 #include <sys/socket.h>
40 #include <sys/queue.h>
41 #include <sys/serialize.h>
44 #include <sys/thread2.h>
47 #include <net/ifq_var.h>
48 #include <net/if_arp.h>
49 #include <net/ethernet.h>
50 #include <net/if_dl.h>
51 #include <net/if_media.h>
54 #include <net/if_types.h>
55 #include <net/vlan/if_vlan_var.h>
57 #include <netinet/in_systm.h>
58 #include <netinet/in.h>
59 #include <netinet/ip.h>
60 #include <netinet/tcp.h>
61 #include <netinet/udp.h>
63 #include <vm/vm.h> /* for vtophys */
64 #include <vm/pmap.h> /* for vtophys */
65 #include <machine/clock.h> /* for DELAY */
67 #include <bus/pci/pcidevs.h>
68 #include <bus/pci/pcireg.h>
69 #include <bus/pci/pcivar.h>
71 #include "../mii_layer/mii.h"
72 #include "../mii_layer/miivar.h"
77 #include "miibus_if.h"
79 #define TUNABLE_TX_INTR_DELAY 100
80 #define TUNABLE_RX_INTR_DELAY 100
82 #define GX_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS)
85 * Various supported device vendors/types and their names.
91 u_int32_t version_ipg;
95 static struct gx_device gx_devs[] = {
96 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82542,
97 GXF_FORCE_TBI | GXF_OLD_REGS,
98 10 | 2 << 10 | 10 << 20,
99 "Intel Gigabit Ethernet (82542)" },
100 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_FIBER,
101 GXF_DMA | GXF_ENABLE_MWI | GXF_CSUM,
102 6 | 8 << 10 | 6 << 20,
103 "Intel Gigabit Ethernet (82543GC-F)" },
104 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_COPPER,
105 GXF_DMA | GXF_ENABLE_MWI | GXF_CSUM,
106 8 | 8 << 10 | 6 << 20,
107 "Intel Gigabit Ethernet (82543GC-T)" },
110 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_FIBER,
111 GXF_DMA | GXF_ENABLE_MWI | GXF_CSUM,
112 6 | 8 << 10 | 6 << 20,
113 "Intel Gigabit Ethernet (82544EI-F)" },
114 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_COPPER,
115 GXF_DMA | GXF_ENABLE_MWI | GXF_CSUM,
116 8 | 8 << 10 | 6 << 20,
117 "Intel Gigabit Ethernet (82544EI-T)" },
118 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_LOM,
119 GXF_DMA | GXF_ENABLE_MWI | GXF_CSUM,
120 8 | 8 << 10 | 6 << 20,
121 "Intel Gigabit Ethernet (82544GC-T)" },
126 static struct gx_regs new_regs = {
127 GX_RX_RING_BASE, GX_RX_RING_LEN,
128 GX_RX_RING_HEAD, GX_RX_RING_TAIL,
129 GX_RX_INTR_DELAY, GX_RX_DMA_CTRL,
131 GX_TX_RING_BASE, GX_TX_RING_LEN,
132 GX_TX_RING_HEAD, GX_TX_RING_TAIL,
133 GX_TX_INTR_DELAY, GX_TX_DMA_CTRL,
135 static struct gx_regs old_regs = {
136 GX_RX_OLD_RING_BASE, GX_RX_OLD_RING_LEN,
137 GX_RX_OLD_RING_HEAD, GX_RX_OLD_RING_TAIL,
138 GX_RX_OLD_INTR_DELAY, GX_RX_OLD_DMA_CTRL,
140 GX_TX_OLD_RING_BASE, GX_TX_OLD_RING_LEN,
141 GX_TX_OLD_RING_HEAD, GX_TX_OLD_RING_TAIL,
142 GX_TX_OLD_INTR_DELAY, GX_TX_OLD_DMA_CTRL,
145 static int gx_probe(device_t dev);
146 static int gx_attach(device_t dev);
147 static int gx_detach(device_t dev);
148 static void gx_shutdown(device_t dev);
150 static void gx_intr(void *xsc);
151 static void gx_init(void *xsc);
153 static struct gx_device *gx_match(device_t dev);
154 static void gx_eeprom_getword(struct gx_softc *gx, int addr,
156 static int gx_read_eeprom(struct gx_softc *gx, caddr_t dest, int off,
158 static int gx_ifmedia_upd(struct ifnet *ifp);
159 static void gx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr);
160 static int gx_miibus_readreg(device_t dev, int phy, int reg);
161 static void gx_miibus_writereg(device_t dev, int phy, int reg, int value);
162 static void gx_miibus_statchg(device_t dev);
163 static int gx_ioctl(struct ifnet *ifp, u_long command, caddr_t data,
165 static void gx_setmulti(struct gx_softc *gx);
166 static void gx_reset(struct gx_softc *gx);
167 static void gx_phy_reset(struct gx_softc *gx);
168 static void gx_stop(struct gx_softc *gx);
169 static void gx_watchdog(struct ifnet *ifp);
170 static void gx_start(struct ifnet *ifp);
172 static int gx_init_rx_ring(struct gx_softc *gx);
173 static void gx_free_rx_ring(struct gx_softc *gx);
174 static int gx_init_tx_ring(struct gx_softc *gx);
175 static void gx_free_tx_ring(struct gx_softc *gx);
177 static device_method_t gx_methods[] = {
178 /* Device interface */
179 DEVMETHOD(device_probe, gx_probe),
180 DEVMETHOD(device_attach, gx_attach),
181 DEVMETHOD(device_detach, gx_detach),
182 DEVMETHOD(device_shutdown, gx_shutdown),
185 DEVMETHOD(miibus_readreg, gx_miibus_readreg),
186 DEVMETHOD(miibus_writereg, gx_miibus_writereg),
187 DEVMETHOD(miibus_statchg, gx_miibus_statchg),
192 static driver_t gx_driver = {
195 sizeof(struct gx_softc)
198 static devclass_t gx_devclass;
200 DECLARE_DUMMY_MODULE(if_gx);
201 MODULE_DEPEND(if_gx, miibus, 1, 1, 1);
202 DRIVER_MODULE(if_gx, pci, gx_driver, gx_devclass, 0, 0);
203 DRIVER_MODULE(miibus, gx, miibus_driver, miibus_devclass, 0, 0);
205 static struct gx_device *
206 gx_match(device_t dev)
210 for (i = 0; gx_devs[i].name != NULL; i++) {
211 if ((pci_get_vendor(dev) == gx_devs[i].vendor) &&
212 (pci_get_device(dev) == gx_devs[i].device))
213 return (&gx_devs[i]);
219 gx_probe(device_t dev)
221 struct gx_device *gx_dev;
223 gx_dev = gx_match(dev);
227 device_set_desc(dev, gx_dev->name);
232 gx_attach(device_t dev)
235 struct gx_device *gx_dev;
241 gx = device_get_softc(dev);
244 gx_dev = gx_match(dev);
245 gx->gx_vflags = gx_dev->version_flags;
246 gx->gx_ipg = gx_dev->version_ipg;
249 * Map control/status registers.
251 command = pci_read_config(dev, PCIR_COMMAND, 4);
252 command |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN;
253 if (gx->gx_vflags & GXF_ENABLE_MWI)
254 command |= PCIM_CMD_MWIEN;
255 pci_write_config(dev, PCIR_COMMAND, command, 4);
256 command = pci_read_config(dev, PCIR_COMMAND, 4);
258 /* XXX check cache line size? */
260 if ((command & PCIM_CMD_MEMEN) == 0) {
261 device_printf(dev, "failed to enable memory mapping!\n");
267 gx->gx_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
270 /* support PIO mode */
272 gx->gx_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
276 if (gx->gx_res == NULL) {
277 device_printf(dev, "couldn't map memory\n");
282 gx->gx_btag = rman_get_bustag(gx->gx_res);
283 gx->gx_bhandle = rman_get_bushandle(gx->gx_res);
285 /* Allocate interrupt */
287 gx->gx_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
288 RF_SHAREABLE | RF_ACTIVE);
290 if (gx->gx_irq == NULL) {
291 device_printf(dev, "couldn't map interrupt\n");
296 /* compensate for different register mappings */
297 if (gx->gx_vflags & GXF_OLD_REGS)
298 gx->gx_reg = old_regs;
300 gx->gx_reg = new_regs;
302 if (gx_read_eeprom(gx, (caddr_t)&gx->arpcom.ac_enaddr,
304 device_printf(dev, "failed to read station address\n");
309 /* Allocate the ring buffers. */
310 gx->gx_rdata = contigmalloc(sizeof(struct gx_ring_data), M_DEVBUF,
311 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
313 if (gx->gx_rdata == NULL) {
314 device_printf(dev, "no memory for list buffers!\n");
318 bzero(gx->gx_rdata, sizeof(struct gx_ring_data));
320 /* Set default tuneable values. */
321 gx->gx_tx_intr_delay = TUNABLE_TX_INTR_DELAY;
322 gx->gx_rx_intr_delay = TUNABLE_RX_INTR_DELAY;
324 /* Set up ifnet structure */
325 ifp = &gx->arpcom.ac_if;
327 if_initname(ifp, "gx", device_get_unit(dev));
328 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
329 ifp->if_ioctl = gx_ioctl;
330 ifp->if_start = gx_start;
331 ifp->if_watchdog = gx_watchdog;
332 ifp->if_init = gx_init;
333 ifp->if_mtu = ETHERMTU;
334 ifq_set_maxlen(&ifp->if_snd, GX_TX_RING_CNT - 1);
335 ifq_set_ready(&ifp->if_snd);
337 /* see if we can enable hardware checksumming */
338 if (gx->gx_vflags & GXF_CSUM) {
339 ifp->if_capabilities = IFCAP_HWCSUM;
340 ifp->if_capenable = ifp->if_capabilities;
343 /* figure out transciever type */
344 if (gx->gx_vflags & GXF_FORCE_TBI ||
345 CSR_READ_4(gx, GX_STATUS) & GX_STAT_TBIMODE)
348 if (gx->gx_tbimode) {
349 /* SERDES transceiver */
350 ifmedia_init(&gx->gx_media, IFM_IMASK, gx_ifmedia_upd,
352 ifmedia_add(&gx->gx_media,
353 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
354 ifmedia_add(&gx->gx_media, IFM_ETHER|IFM_AUTO, 0, NULL);
355 ifmedia_set(&gx->gx_media, IFM_ETHER|IFM_AUTO);
357 /* GMII/MII transceiver */
359 if (mii_phy_probe(dev, &gx->gx_miibus, gx_ifmedia_upd,
361 device_printf(dev, "GMII/MII, PHY not detected\n");
368 * Call MI attach routines.
370 ether_ifattach(ifp, gx->arpcom.ac_enaddr, NULL);
372 error = bus_setup_intr(dev, gx->gx_irq, INTR_NETSAFE,
373 gx_intr, gx, &gx->gx_intrhand,
377 device_printf(dev, "couldn't setup irq\n");
391 struct gx_softc *gx = (struct gx_softc *)xsc;
393 struct ifnet *ifp = &gx->arpcom.ac_if;
398 /* Disable host interrupts, halt chip. */
401 /* disable I/O, flush RX/TX FIFOs, and free RX/TX buffers */
404 /* Load our MAC address, invalidate other 15 RX addresses. */
405 m = (u_int16_t *)&gx->arpcom.ac_enaddr[0];
406 CSR_WRITE_4(gx, GX_RX_ADDR_BASE, (m[1] << 16) | m[0]);
407 CSR_WRITE_4(gx, GX_RX_ADDR_BASE + 4, m[2] | GX_RA_VALID);
408 for (i = 1; i < 16; i++)
409 CSR_WRITE_8(gx, GX_RX_ADDR_BASE + i * 8, (u_quad_t)0);
411 /* Program multicast filter. */
420 if (gx->gx_vflags & GXF_DMA) {
421 /* set up DMA control */
422 CSR_WRITE_4(gx, gx->gx_reg.r_rx_dma_ctrl, 0x00010000);
423 CSR_WRITE_4(gx, gx->gx_reg.r_tx_dma_ctrl, 0x00000000);
426 /* enable receiver */
427 ctrl = GX_RXC_ENABLE | GX_RXC_RX_THOLD_EIGHTH | GX_RXC_RX_BSIZE_2K;
428 ctrl |= GX_RXC_BCAST_ACCEPT;
430 /* Enable or disable promiscuous mode as needed. */
431 if (ifp->if_flags & IFF_PROMISC)
432 ctrl |= GX_RXC_UNI_PROMISC;
434 /* This is required if we want to accept jumbo frames */
435 if (ifp->if_mtu > ETHERMTU)
436 ctrl |= GX_RXC_LONG_PKT_ENABLE;
438 /* setup receive checksum control */
439 if (ifp->if_capenable & IFCAP_RXCSUM)
440 CSR_WRITE_4(gx, GX_RX_CSUM_CONTROL,
441 GX_CSUM_TCP/* | GX_CSUM_IP*/);
443 /* setup transmit checksum control */
444 if (ifp->if_capenable & IFCAP_TXCSUM)
445 ifp->if_hwassist = GX_CSUM_FEATURES;
447 ctrl |= GX_RXC_STRIP_ETHERCRC; /* not on 82542? */
448 CSR_WRITE_4(gx, GX_RX_CONTROL, ctrl);
450 /* enable transmitter */
451 ctrl = GX_TXC_ENABLE | GX_TXC_PAD_SHORT_PKTS | GX_TXC_COLL_RETRY_16;
453 /* XXX we should support half-duplex here too... */
454 ctrl |= GX_TXC_COLL_TIME_FDX;
456 CSR_WRITE_4(gx, GX_TX_CONTROL, ctrl);
459 * set up recommended IPG times, which vary depending on chip type:
460 * IPG transmit time: 80ns
461 * IPG receive time 1: 20ns
462 * IPG receive time 2: 80ns
464 CSR_WRITE_4(gx, GX_TX_IPG, gx->gx_ipg);
466 /* set up 802.3x MAC flow control address -- 01:80:c2:00:00:01 */
467 CSR_WRITE_4(gx, GX_FLOW_CTRL_BASE, 0x00C28001);
468 CSR_WRITE_4(gx, GX_FLOW_CTRL_BASE+4, 0x00000100);
470 /* set up 802.3x MAC flow control type -- 88:08 */
471 CSR_WRITE_4(gx, GX_FLOW_CTRL_TYPE, 0x8808);
473 /* Set up tuneables */
474 CSR_WRITE_4(gx, gx->gx_reg.r_rx_delay, gx->gx_rx_intr_delay);
475 CSR_WRITE_4(gx, gx->gx_reg.r_tx_delay, gx->gx_tx_intr_delay);
478 * Configure chip for correct operation.
480 ctrl = GX_CTRL_DUPLEX;
481 #if BYTE_ORDER == BIG_ENDIAN
482 ctrl |= GX_CTRL_BIGENDIAN;
484 ctrl |= GX_CTRL_VLAN_ENABLE;
486 if (gx->gx_tbimode) {
488 * It seems that TXCW must be initialized from the EEPROM
492 * should probably read the eeprom and re-insert the
495 #define TXCONFIG_WORD 0x000001A0
496 CSR_WRITE_4(gx, GX_TX_CONFIG, TXCONFIG_WORD);
498 /* turn on hardware autonegotiate */
499 GX_SETBIT(gx, GX_TX_CONFIG, GX_TXCFG_AUTONEG);
502 * Auto-detect speed from PHY, instead of using direct
503 * indication. The SLU bit doesn't force the link, but
504 * must be present for ASDE to work.
507 ctrl |= GX_CTRL_SET_LINK_UP | GX_CTRL_AUTOSPEED;
511 * Take chip out of reset and start it running.
513 CSR_WRITE_4(gx, GX_CTRL, ctrl);
515 /* Turn interrupts on. */
516 CSR_WRITE_4(gx, GX_INT_MASK_SET, GX_INT_WANTED);
518 ifp->if_flags |= IFF_RUNNING;
519 ifp->if_flags &= ~IFF_OACTIVE;
522 * Set the current media.
524 if (gx->gx_miibus != NULL) {
525 mii_mediachg(device_get_softc(gx->gx_miibus));
528 tmp = ifm->ifm_media;
529 ifm->ifm_media = ifm->ifm_cur->ifm_media;
531 ifm->ifm_media = tmp;
536 * Have the LINK0 flag force the link in TBI mode.
538 if (gx->gx_tbimode && ifp->if_flags & IFF_LINK0) {
539 GX_CLRBIT(gx, GX_TX_CONFIG, GX_TXCFG_AUTONEG);
540 GX_SETBIT(gx, GX_CTRL, GX_CTRL_SET_LINK_UP);
544 kprintf("66mhz: %s 64bit: %s\n",
545 CSR_READ_4(gx, GX_STATUS) & GX_STAT_PCI66 ? "yes" : "no",
546 CSR_READ_4(gx, GX_STATUS) & GX_STAT_BUS64 ? "yes" : "no");
551 * Stop all chip I/O so that the kernel's probe routines don't
552 * get confused by errant DMAs when rebooting.
555 gx_shutdown(device_t dev)
559 gx = device_get_softc(dev);
565 gx_detach(device_t dev)
567 struct gx_softc *gx = device_get_softc(dev);
568 struct ifnet *ifp = &gx->arpcom.ac_if;
570 if (device_is_attached(dev)) {
571 lwkt_serialize_enter(ifp->if_serializer);
574 bus_teardown_intr(gx->gx_dev, gx->gx_irq, gx->gx_intrhand);
575 lwkt_serialize_exit(ifp->if_serializer);
580 device_delete_child(gx->gx_dev, gx->gx_miibus);
581 bus_generic_detach(gx->gx_dev);
584 bus_release_resource(gx->gx_dev, SYS_RES_IRQ, 0, gx->gx_irq);
586 bus_release_resource(gx->gx_dev, SYS_RES_MEMORY,
587 GX_PCI_LOMEM, gx->gx_res);
590 contigfree(gx->gx_rdata, sizeof(struct gx_ring_data),
594 ifmedia_removeall(&gx->gx_media);
600 gx_eeprom_getword(struct gx_softc *gx, int addr, u_int16_t *dest)
606 addr = (GX_EE_OPC_READ << GX_EE_ADDR_SIZE) |
607 (addr & ((1 << GX_EE_ADDR_SIZE) - 1));
609 base = CSR_READ_4(gx, GX_EEPROM_CTRL);
610 base &= ~(GX_EE_DATA_OUT | GX_EE_DATA_IN | GX_EE_CLOCK);
611 base |= GX_EE_SELECT;
613 CSR_WRITE_4(gx, GX_EEPROM_CTRL, base);
615 for (x = 1 << ((GX_EE_OPC_SIZE + GX_EE_ADDR_SIZE) - 1); x; x >>= 1) {
616 reg = base | (addr & x ? GX_EE_DATA_IN : 0);
617 CSR_WRITE_4(gx, GX_EEPROM_CTRL, reg);
619 CSR_WRITE_4(gx, GX_EEPROM_CTRL, reg | GX_EE_CLOCK);
621 CSR_WRITE_4(gx, GX_EEPROM_CTRL, reg);
625 for (x = 1 << 15; x; x >>= 1) {
626 CSR_WRITE_4(gx, GX_EEPROM_CTRL, base | GX_EE_CLOCK);
628 reg = CSR_READ_4(gx, GX_EEPROM_CTRL);
629 if (reg & GX_EE_DATA_OUT)
631 CSR_WRITE_4(gx, GX_EEPROM_CTRL, base);
635 CSR_WRITE_4(gx, GX_EEPROM_CTRL, base & ~GX_EE_SELECT);
642 gx_read_eeprom(struct gx_softc *gx, caddr_t dest, int off, int cnt)
647 word = (u_int16_t *)dest;
648 for (i = 0; i < cnt; i ++) {
649 gx_eeprom_getword(gx, off + i, word);
659 gx_ifmedia_upd(struct ifnet *ifp)
663 struct mii_data *mii;
667 if (gx->gx_tbimode) {
669 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
671 switch (IFM_SUBTYPE(ifm->ifm_media)) {
673 GX_SETBIT(gx, GX_CTRL, GX_CTRL_LINK_RESET);
674 GX_SETBIT(gx, GX_TX_CONFIG, GX_TXCFG_AUTONEG);
675 GX_CLRBIT(gx, GX_CTRL, GX_CTRL_LINK_RESET);
678 device_printf(gx->gx_dev,
679 "manual config not supported yet.\n");
681 GX_CLRBIT(gx, GX_TX_CONFIG, GX_TXCFG_AUTONEG);
682 config = /* bit symbols for 802.3z */0;
683 ctrl |= GX_CTRL_SET_LINK_UP;
684 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
685 ctrl |= GX_CTRL_DUPLEX;
695 * 1000TX half duplex does not work.
697 if (IFM_TYPE(ifm->ifm_media) == IFM_ETHER &&
698 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_T &&
699 (IFM_OPTIONS(ifm->ifm_media) & IFM_FDX) == 0)
701 mii = device_get_softc(gx->gx_miibus);
708 * Report current media status.
711 gx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
714 struct mii_data *mii;
719 if (gx->gx_tbimode) {
720 ifmr->ifm_status = IFM_AVALID;
721 ifmr->ifm_active = IFM_ETHER;
723 status = CSR_READ_4(gx, GX_STATUS);
724 if ((status & GX_STAT_LINKUP) == 0)
727 ifmr->ifm_status |= IFM_ACTIVE;
728 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
730 mii = device_get_softc(gx->gx_miibus);
732 if ((mii->mii_media_active & (IFM_1000_T | IFM_HDX)) ==
733 (IFM_1000_T | IFM_HDX))
734 mii->mii_media_active = IFM_ETHER | IFM_NONE;
735 ifmr->ifm_active = mii->mii_media_active;
736 ifmr->ifm_status = mii->mii_media_status;
741 gx_mii_shiftin(struct gx_softc *gx, int data, int length)
746 * Set up default GPIO direction + PHY data out.
748 reg = CSR_READ_4(gx, GX_CTRL);
749 reg &= ~(GX_CTRL_GPIO_DIR_MASK | GX_CTRL_PHY_IO | GX_CTRL_PHY_CLK);
750 reg |= GX_CTRL_GPIO_DIR | GX_CTRL_PHY_IO_DIR;
753 * Shift in data to PHY.
755 for (x = 1 << (length - 1); x; x >>= 1) {
757 reg |= GX_CTRL_PHY_IO;
759 reg &= ~GX_CTRL_PHY_IO;
760 CSR_WRITE_4(gx, GX_CTRL, reg);
762 CSR_WRITE_4(gx, GX_CTRL, reg | GX_CTRL_PHY_CLK);
764 CSR_WRITE_4(gx, GX_CTRL, reg);
770 gx_mii_shiftout(struct gx_softc *gx)
777 * Set up default GPIO direction + PHY data in.
779 reg = CSR_READ_4(gx, GX_CTRL);
780 reg &= ~(GX_CTRL_GPIO_DIR_MASK | GX_CTRL_PHY_IO | GX_CTRL_PHY_CLK);
781 reg |= GX_CTRL_GPIO_DIR;
783 CSR_WRITE_4(gx, GX_CTRL, reg);
785 CSR_WRITE_4(gx, GX_CTRL, reg | GX_CTRL_PHY_CLK);
787 CSR_WRITE_4(gx, GX_CTRL, reg);
790 * Shift out data from PHY.
793 for (x = 1 << 15; x; x >>= 1) {
794 CSR_WRITE_4(gx, GX_CTRL, reg | GX_CTRL_PHY_CLK);
796 if (CSR_READ_4(gx, GX_CTRL) & GX_CTRL_PHY_IO)
798 CSR_WRITE_4(gx, GX_CTRL, reg);
801 CSR_WRITE_4(gx, GX_CTRL, reg | GX_CTRL_PHY_CLK);
803 CSR_WRITE_4(gx, GX_CTRL, reg);
810 gx_miibus_readreg(device_t dev, int phy, int reg)
814 gx = device_get_softc(dev);
820 * Note: Cordova has a MDIC register. livingood and < have mii bits
823 gx_mii_shiftin(gx, GX_PHY_PREAMBLE, GX_PHY_PREAMBLE_LEN);
824 gx_mii_shiftin(gx, (GX_PHY_SOF << 12) | (GX_PHY_OP_READ << 10) |
825 (phy << 5) | reg, GX_PHY_READ_LEN);
826 return (gx_mii_shiftout(gx));
830 gx_miibus_writereg(device_t dev, int phy, int reg, int value)
834 gx = device_get_softc(dev);
838 gx_mii_shiftin(gx, GX_PHY_PREAMBLE, GX_PHY_PREAMBLE_LEN);
839 gx_mii_shiftin(gx, (GX_PHY_SOF << 30) | (GX_PHY_OP_WRITE << 28) |
840 (phy << 23) | (reg << 18) | (GX_PHY_TURNAROUND << 16) |
841 (value & 0xffff), GX_PHY_WRITE_LEN);
845 gx_miibus_statchg(device_t dev)
847 struct gx_softc *gx = device_get_softc(dev);
848 struct mii_data *mii;
855 * Set flow control behavior to mirror what PHY negotiated.
857 mii = device_get_softc(gx->gx_miibus);
859 reg = CSR_READ_4(gx, GX_CTRL);
860 if (mii->mii_media_active & IFM_FLAG0)
861 reg |= GX_CTRL_RX_FLOWCTRL;
863 reg &= ~GX_CTRL_RX_FLOWCTRL;
864 if (mii->mii_media_active & IFM_FLAG1)
865 reg |= GX_CTRL_TX_FLOWCTRL;
867 reg &= ~GX_CTRL_TX_FLOWCTRL;
868 CSR_WRITE_4(gx, GX_CTRL, reg);
872 gx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
874 struct gx_softc *gx = ifp->if_softc;
875 struct ifreq *ifr = (struct ifreq *)data;
876 struct mii_data *mii;
881 if (ifr->ifr_mtu > GX_MAX_MTU) {
884 ifp->if_mtu = ifr->ifr_mtu;
889 if ((ifp->if_flags & IFF_UP) == 0) {
891 } else if (ifp->if_flags & IFF_RUNNING &&
892 ((ifp->if_flags & IFF_PROMISC) !=
893 (gx->gx_if_flags & IFF_PROMISC))) {
894 if (ifp->if_flags & IFF_PROMISC)
895 GX_SETBIT(gx, GX_RX_CONTROL, GX_RXC_UNI_PROMISC);
897 GX_CLRBIT(gx, GX_RX_CONTROL, GX_RXC_UNI_PROMISC);
901 gx->gx_if_flags = ifp->if_flags;
905 if (ifp->if_flags & IFF_RUNNING)
910 if (gx->gx_miibus != NULL) {
911 mii = device_get_softc(gx->gx_miibus);
912 error = ifmedia_ioctl(ifp, ifr,
913 &mii->mii_media, command);
915 error = ifmedia_ioctl(ifp, ifr, &gx->gx_media, command);
919 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
920 if (mask & IFCAP_HWCSUM) {
921 if (IFCAP_HWCSUM & ifp->if_capenable)
922 ifp->if_capenable &= ~IFCAP_HWCSUM;
924 ifp->if_capenable |= IFCAP_HWCSUM;
925 if (ifp->if_flags & IFF_RUNNING)
930 error = ether_ioctl(ifp, command, data);
937 gx_phy_reset(struct gx_softc *gx)
941 GX_SETBIT(gx, GX_CTRL, GX_CTRL_SET_LINK_UP);
944 * PHY reset is active low.
946 reg = CSR_READ_4(gx, GX_CTRL_EXT);
947 reg &= ~(GX_CTRLX_GPIO_DIR_MASK | GX_CTRLX_PHY_RESET);
948 reg |= GX_CTRLX_GPIO_DIR;
950 CSR_WRITE_4(gx, GX_CTRL_EXT, reg | GX_CTRLX_PHY_RESET);
952 CSR_WRITE_4(gx, GX_CTRL_EXT, reg);
954 CSR_WRITE_4(gx, GX_CTRL_EXT, reg | GX_CTRLX_PHY_RESET);
958 /* post-livingood (cordova) only */
959 GX_SETBIT(gx, GX_CTRL, 0x80000000);
961 GX_CLRBIT(gx, GX_CTRL, 0x80000000);
966 gx_reset(struct gx_softc *gx)
969 /* Disable host interrupts. */
970 CSR_WRITE_4(gx, GX_INT_MASK_CLR, GX_INT_ALL);
972 /* reset chip (THWAP!) */
973 GX_SETBIT(gx, GX_CTRL, GX_CTRL_DEVICE_RESET);
978 gx_stop(struct gx_softc *gx)
982 ifp = &gx->arpcom.ac_if;
984 /* reset and flush transmitter */
985 CSR_WRITE_4(gx, GX_TX_CONTROL, GX_TXC_RESET);
987 /* reset and flush receiver */
988 CSR_WRITE_4(gx, GX_RX_CONTROL, GX_RXC_RESET);
992 GX_SETBIT(gx, GX_CTRL, GX_CTRL_LINK_RESET);
994 /* Free the RX lists. */
997 /* Free TX buffers. */
1000 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1004 gx_watchdog(struct ifnet *ifp)
1006 struct gx_softc *gx;
1010 device_printf(gx->gx_dev, "watchdog timeout -- resetting\n");
1018 * Intialize a receive ring descriptor.
1021 gx_newbuf(struct gx_softc *gx, int idx, struct mbuf *m)
1023 struct mbuf *m_new = NULL;
1024 struct gx_rx_desc *r;
1027 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
1028 if (m_new == NULL) {
1029 device_printf(gx->gx_dev,
1030 "mbuf allocation failed -- packet dropped\n");
1033 MCLGET(m_new, MB_DONTWAIT);
1034 if ((m_new->m_flags & M_EXT) == 0) {
1035 device_printf(gx->gx_dev,
1036 "cluster allocation failed -- packet dropped\n");
1040 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1042 m->m_len = m->m_pkthdr.len = MCLBYTES;
1043 m->m_data = m->m_ext.ext_buf;
1050 * this will _NOT_ work for large MTU's; it will overwrite
1051 * the end of the buffer. E.g.: take this out for jumbograms,
1052 * but then that breaks alignment.
1054 if (gx->arpcom.ac_if.if_mtu <= ETHERMTU)
1055 m_adj(m_new, ETHER_ALIGN);
1057 gx->gx_cdata.gx_rx_chain[idx] = m_new;
1058 r = &gx->gx_rdata->gx_rx_ring[idx];
1059 r->rx_addr = vtophys(mtod(m_new, caddr_t));
1066 * The receive ring can have up to 64K descriptors, which at 2K per mbuf
1067 * cluster, could add up to 128M of memory. Due to alignment constraints,
1068 * the number of descriptors must be a multiple of 8. For now, we
1069 * allocate 256 entries and hope that our CPU is fast enough to keep up
1073 gx_init_rx_ring(struct gx_softc *gx)
1077 for (i = 0; i < GX_RX_RING_CNT; i++) {
1078 error = gx_newbuf(gx, i, NULL);
1083 /* bring receiver out of reset state, leave disabled */
1084 CSR_WRITE_4(gx, GX_RX_CONTROL, 0);
1086 /* set up ring registers */
1087 CSR_WRITE_8(gx, gx->gx_reg.r_rx_base,
1088 (u_quad_t)vtophys(gx->gx_rdata->gx_rx_ring));
1090 CSR_WRITE_4(gx, gx->gx_reg.r_rx_length,
1091 GX_RX_RING_CNT * sizeof(struct gx_rx_desc));
1092 CSR_WRITE_4(gx, gx->gx_reg.r_rx_head, 0);
1093 CSR_WRITE_4(gx, gx->gx_reg.r_rx_tail, GX_RX_RING_CNT - 1);
1094 gx->gx_rx_tail_idx = 0;
1100 gx_free_rx_ring(struct gx_softc *gx)
1105 mp = gx->gx_cdata.gx_rx_chain;
1106 for (i = 0; i < GX_RX_RING_CNT; i++, mp++) {
1112 bzero((void *)gx->gx_rdata->gx_rx_ring,
1113 GX_RX_RING_CNT * sizeof(struct gx_rx_desc));
1115 /* release any partially-received packet chain */
1116 if (gx->gx_pkthdr != NULL) {
1117 m_freem(gx->gx_pkthdr);
1118 gx->gx_pkthdr = NULL;
1123 gx_init_tx_ring(struct gx_softc *gx)
1126 /* bring transmitter out of reset state, leave disabled */
1127 CSR_WRITE_4(gx, GX_TX_CONTROL, 0);
1129 /* set up ring registers */
1130 CSR_WRITE_8(gx, gx->gx_reg.r_tx_base,
1131 (u_quad_t)vtophys(gx->gx_rdata->gx_tx_ring));
1132 CSR_WRITE_4(gx, gx->gx_reg.r_tx_length,
1133 GX_TX_RING_CNT * sizeof(struct gx_tx_desc));
1134 CSR_WRITE_4(gx, gx->gx_reg.r_tx_head, 0);
1135 CSR_WRITE_4(gx, gx->gx_reg.r_tx_tail, 0);
1136 gx->gx_tx_head_idx = 0;
1137 gx->gx_tx_tail_idx = 0;
1140 /* set up initial TX context */
1141 gx->gx_txcontext = GX_TXCONTEXT_NONE;
1147 gx_free_tx_ring(struct gx_softc *gx)
1152 mp = gx->gx_cdata.gx_tx_chain;
1153 for (i = 0; i < GX_TX_RING_CNT; i++, mp++) {
1159 bzero((void *)&gx->gx_rdata->gx_tx_ring,
1160 GX_TX_RING_CNT * sizeof(struct gx_tx_desc));
1164 gx_setmulti(struct gx_softc *gx)
1168 /* wipe out the multicast table */
1169 for (i = 1; i < 128; i++)
1170 CSR_WRITE_4(gx, GX_MULTICAST_BASE + i * 4, 0);
1174 gx_rxeof(struct gx_softc *gx)
1176 struct gx_rx_desc *rx;
1178 int idx, staterr, len;
1181 gx->gx_rx_interrupts++;
1183 ifp = &gx->arpcom.ac_if;
1184 idx = gx->gx_rx_tail_idx;
1186 while (gx->gx_rdata->gx_rx_ring[idx].rx_staterr & GX_RXSTAT_COMPLETED) {
1188 rx = &gx->gx_rdata->gx_rx_ring[idx];
1189 m = gx->gx_cdata.gx_rx_chain[idx];
1191 * gx_newbuf overwrites status and length bits, so we
1192 * make a copy of them here.
1195 staterr = rx->rx_staterr;
1197 if (staterr & GX_INPUT_ERROR)
1200 if (gx_newbuf(gx, idx, NULL) == ENOBUFS)
1203 GX_INC(idx, GX_RX_RING_CNT);
1205 if (staterr & GX_RXSTAT_INEXACT_MATCH) {
1207 * multicast packet, must verify against
1208 * multicast address.
1212 if ((staterr & GX_RXSTAT_END_OF_PACKET) == 0) {
1213 if (gx->gx_pkthdr == NULL) {
1215 m->m_pkthdr.len = len;
1217 gx->gx_pktnextp = &m->m_next;
1220 gx->gx_pkthdr->m_pkthdr.len += len;
1221 *(gx->gx_pktnextp) = m;
1222 gx->gx_pktnextp = &m->m_next;
1227 if (gx->gx_pkthdr == NULL) {
1229 m->m_pkthdr.len = len;
1232 gx->gx_pkthdr->m_pkthdr.len += len;
1233 *(gx->gx_pktnextp) = m;
1235 gx->gx_pkthdr = NULL;
1239 m->m_pkthdr.rcvif = ifp;
1241 #define IP_CSMASK (GX_RXSTAT_IGNORE_CSUM | GX_RXSTAT_HAS_IP_CSUM)
1242 #define TCP_CSMASK \
1243 (GX_RXSTAT_IGNORE_CSUM | GX_RXSTAT_HAS_TCP_CSUM | GX_RXERR_TCP_CSUM)
1244 if (ifp->if_capenable & IFCAP_RXCSUM) {
1247 * Intel Erratum #23 indicates that the Receive IP
1248 * Checksum offload feature has been completely
1251 if ((staterr & IP_CSUM_MASK) == GX_RXSTAT_HAS_IP_CSUM) {
1252 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1253 if ((staterr & GX_RXERR_IP_CSUM) == 0)
1254 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1257 if ((staterr & TCP_CSMASK) == GX_RXSTAT_HAS_TCP_CSUM) {
1258 m->m_pkthdr.csum_flags |=
1259 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
1260 m->m_pkthdr.csum_data = 0xffff;
1264 * If we received a packet with a vlan tag, pass it
1265 * to vlan_input() instead of ether_input().
1267 if (staterr & GX_RXSTAT_VLAN_PKT)
1268 VLAN_INPUT_TAG(m, rx->rx_special);
1270 ifp->if_input(ifp, m);
1275 gx_newbuf(gx, idx, m);
1279 * this isn't quite right. Suppose we have a packet that
1280 * spans 5 descriptors (9K split into 2K buffers). If
1281 * the 3rd descriptor sets an error, we need to ignore
1282 * the last two. The way things stand now, the last two
1283 * will be accepted as a single packet.
1285 * we don't worry about this -- the chip may not set an
1286 * error in this case, and the checksum of the upper layers
1287 * will catch the error.
1289 if (gx->gx_pkthdr != NULL) {
1290 m_freem(gx->gx_pkthdr);
1291 gx->gx_pkthdr = NULL;
1293 GX_INC(idx, GX_RX_RING_CNT);
1296 gx->gx_rx_tail_idx = idx;
1298 idx = GX_RX_RING_CNT - 1;
1299 CSR_WRITE_4(gx, gx->gx_reg.r_rx_tail, idx);
1303 gx_txeof(struct gx_softc *gx)
1308 gx->gx_tx_interrupts++;
1310 ifp = &gx->arpcom.ac_if;
1311 idx = gx->gx_tx_head_idx;
1315 * If the system chipset performs I/O write buffering, it is
1316 * possible for the PIO read of the head descriptor to bypass the
1317 * memory write of the descriptor, resulting in reading a descriptor
1318 * which has not been updated yet.
1321 struct gx_tx_desc_old *tx;
1323 tx = (struct gx_tx_desc_old *)&gx->gx_rdata->gx_tx_ring[idx];
1326 if ((tx->tx_command & GX_TXOLD_END_OF_PKT) == 0) {
1327 GX_INC(idx, GX_TX_RING_CNT);
1331 if ((tx->tx_status & GX_TXSTAT_DONE) == 0)
1336 m_freem(gx->gx_cdata.gx_tx_chain[idx]);
1337 gx->gx_cdata.gx_tx_chain[idx] = NULL;
1341 GX_INC(idx, GX_TX_RING_CNT);
1342 gx->gx_tx_head_idx = idx;
1345 if (gx->gx_txcnt == 0)
1346 ifp->if_flags &= ~IFF_OACTIVE;
1352 struct gx_softc *gx = xsc;
1353 struct ifnet *ifp = &gx->arpcom.ac_if;
1356 gx->gx_interrupts++;
1358 /* Disable host interrupts. */
1359 CSR_WRITE_4(gx, GX_INT_MASK_CLR, GX_INT_ALL);
1362 * find out why we're being bothered.
1363 * reading this register automatically clears all bits.
1365 intr = CSR_READ_4(gx, GX_INT_READ);
1367 /* Check RX return ring producer/consumer */
1368 if (intr & (GX_INT_RCV_TIMER | GX_INT_RCV_THOLD | GX_INT_RCV_OVERRUN))
1371 /* Check TX ring producer/consumer */
1372 if (intr & (GX_INT_XMIT_DONE | GX_INT_XMIT_EMPTY))
1376 * handle other interrupts here.
1380 * Link change interrupts are not reliable; the interrupt may
1381 * not be generated if the link is lost. However, the register
1382 * read is reliable, so check that. Use SEQ errors to possibly
1383 * indicate that the link has changed.
1385 if (intr & GX_INT_LINK_CHANGE) {
1386 if ((CSR_READ_4(gx, GX_STATUS) & GX_STAT_LINKUP) == 0) {
1387 device_printf(gx->gx_dev, "link down\n");
1389 device_printf(gx->gx_dev, "link up\n");
1393 /* Turn interrupts on. */
1394 CSR_WRITE_4(gx, GX_INT_MASK_SET, GX_INT_WANTED);
1396 if (ifp->if_flags & IFF_RUNNING && !ifq_is_empty(&ifp->if_snd))
1401 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
1402 * pointers to descriptors.
1405 gx_encap(struct gx_softc *gx, struct mbuf *m_head)
1407 struct gx_tx_desc_data *tx = NULL;
1408 struct gx_tx_desc_ctx *tctx;
1410 int idx, cnt, csumopts, txcontext;
1411 struct ifvlan *ifv = NULL;
1413 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
1414 m_head->m_pkthdr.rcvif != NULL &&
1415 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN)
1416 ifv = m_head->m_pkthdr.rcvif->if_softc;
1419 idx = gx->gx_tx_tail_idx;
1420 txcontext = gx->gx_txcontext;
1423 * Insure we have at least 4 descriptors pre-allocated.
1425 if (cnt >= GX_TX_RING_CNT - 4)
1429 * Set up the appropriate offload context if necessary.
1432 if (m_head->m_pkthdr.csum_flags) {
1433 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
1434 csumopts |= GX_TXTCP_OPT_IP_CSUM;
1435 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) {
1436 csumopts |= GX_TXTCP_OPT_TCP_CSUM;
1437 txcontext = GX_TXCONTEXT_TCPIP;
1438 } else if (m_head->m_pkthdr.csum_flags & CSUM_UDP) {
1439 csumopts |= GX_TXTCP_OPT_TCP_CSUM;
1440 txcontext = GX_TXCONTEXT_UDPIP;
1441 } else if (txcontext == GX_TXCONTEXT_NONE)
1442 txcontext = GX_TXCONTEXT_TCPIP;
1443 if (txcontext == gx->gx_txcontext)
1446 tctx = (struct gx_tx_desc_ctx *)&gx->gx_rdata->gx_tx_ring[idx];
1447 tctx->tx_ip_csum_start = ETHER_HDR_LEN;
1448 tctx->tx_ip_csum_end = ETHER_HDR_LEN + sizeof(struct ip) - 1;
1449 tctx->tx_ip_csum_offset =
1450 ETHER_HDR_LEN + offsetof(struct ip, ip_sum);
1451 tctx->tx_tcp_csum_start = ETHER_HDR_LEN + sizeof(struct ip);
1452 tctx->tx_tcp_csum_end = 0;
1453 if (txcontext == GX_TXCONTEXT_TCPIP)
1454 tctx->tx_tcp_csum_offset = ETHER_HDR_LEN +
1455 sizeof(struct ip) + offsetof(struct tcphdr, th_sum);
1457 tctx->tx_tcp_csum_offset = ETHER_HDR_LEN +
1458 sizeof(struct ip) + offsetof(struct udphdr, uh_sum);
1459 tctx->tx_command = GX_TXCTX_EXTENSION | GX_TXCTX_INT_DELAY;
1461 tctx->tx_status = 0;
1462 GX_INC(idx, GX_TX_RING_CNT);
1468 * Start packing the mbufs in this chain into the transmit
1469 * descriptors. Stop when we run out of descriptors or hit
1470 * the end of the mbuf chain.
1472 for (m = m_head; m != NULL; m = m->m_next) {
1476 if (cnt == GX_TX_RING_CNT) {
1477 kprintf("overflow(2): %d, %d\n", cnt, GX_TX_RING_CNT);
1481 tx = (struct gx_tx_desc_data *)&gx->gx_rdata->gx_tx_ring[idx];
1482 tx->tx_addr = vtophys(mtod(m, vm_offset_t));
1484 tx->tx_len = m->m_len;
1485 if (gx->arpcom.ac_if.if_hwassist) {
1487 tx->tx_command = GX_TXTCP_EXTENSION;
1488 tx->tx_options = csumopts;
1491 * This is really a struct gx_tx_desc_old.
1495 GX_INC(idx, GX_TX_RING_CNT);
1500 tx->tx_command |= GX_TXTCP_REPORT_STATUS | GX_TXTCP_INT_DELAY |
1501 GX_TXTCP_ETHER_CRC | GX_TXTCP_END_OF_PKT;
1503 tx->tx_command |= GX_TXTCP_VLAN_ENABLE;
1504 tx->tx_vlan = ifv->ifv_tag;
1507 gx->gx_tx_tail_idx = idx;
1508 gx->gx_txcontext = txcontext;
1509 idx = GX_PREV(idx, GX_TX_RING_CNT);
1510 gx->gx_cdata.gx_tx_chain[idx] = m_head;
1512 CSR_WRITE_4(gx, gx->gx_reg.r_tx_tail, gx->gx_tx_tail_idx);
1519 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1520 * to the mbuf data regions directly in the transmit descriptors.
1523 gx_start(struct ifnet *ifp)
1525 struct gx_softc *gx = ifp->if_softc;
1526 struct mbuf *m_head;
1529 m_head = ifq_poll(&ifp->if_snd);
1534 * Pack the data into the transmit ring. If we
1535 * don't have room, set the OACTIVE flag and wait
1536 * for the NIC to drain the ring.
1538 if (gx_encap(gx, m_head) != 0) {
1539 ifp->if_flags |= IFF_OACTIVE;
1542 ifq_dequeue(&ifp->if_snd, m_head);
1544 BPF_MTAP(ifp, m_head);
1547 * Set a timeout in case the chip goes out to lunch.