1 ; Options for the IA-32 and AMD64 ports of the compiler.
3 ; Copyright (C) 2005, 2006, 2007, 2008, 2009,
4 ; 2010, 2011 Free Software Foundation, Inc.
6 ; This file is part of GCC.
8 ; GCC is free software; you can redistribute it and/or modify it under
9 ; the terms of the GNU General Public License as published by the Free
10 ; Software Foundation; either version 3, or (at your option) any later
13 ; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 ; WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 ; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 ; You should have received a copy of the GNU General Public License
19 ; along with GCC; see the file COPYING3. If not see
20 ; <http://www.gnu.org/licenses/>.
23 config/i386/i386-opts.h
25 ; Bit flags that specify the ISA we are compiling for.
27 HOST_WIDE_INT ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT
29 ; A mask of ix86_isa_flags that includes bit X if X was set or cleared
30 ; on the command line.
32 HOST_WIDE_INT ix86_isa_flags_explicit
35 int recip_mask = RECIP_MASK_DEFAULT
38 int recip_mask_explicit
41 int x_recip_mask_explicit
43 ;; Definitions to add to the cl_target_option structure
54 unsigned char schedule
58 unsigned char branch_cost
60 ;; which flags were passed by the user
62 HOST_WIDE_INT x_ix86_isa_flags_explicit
64 ;; which flags were passed by the user
66 int ix86_target_flags_explicit
68 ;; whether -mtune was not specified
70 unsigned char tune_defaulted
72 ;; whether -march was specified
74 unsigned char arch_specified
78 Target RejectNegative Report Mask(128BIT_LONG_DOUBLE) Save
79 sizeof(long double) is 16
82 Target Report Mask(80387) Save
86 Target RejectNegative Report InverseMask(128BIT_LONG_DOUBLE) Save
87 sizeof(long double) is 12
89 maccumulate-outgoing-args
90 Target Report Mask(ACCUMULATE_OUTGOING_ARGS) Save
91 Reserve space for outgoing arguments in the function prologue
94 Target Report Mask(ALIGN_DOUBLE) Save
95 Align some doubles on dword boundary
98 Target RejectNegative Joined UInteger
99 Function starts are aligned to this power of 2
102 Target RejectNegative Joined UInteger
103 Jump targets are aligned to this power of 2
106 Target RejectNegative Joined UInteger
107 Loop code aligned to this power of 2
110 Target RejectNegative Report InverseMask(NO_ALIGN_STRINGOPS, ALIGN_STRINGOPS) Save
111 Align destination of the string operations
114 Target RejectNegative Joined Var(ix86_arch_string)
115 Generate code for given CPU
118 Target RejectNegative Joined Enum(asm_dialect) Var(ix86_asm_dialect) Init(ASM_ATT)
119 Use given assembler dialect
122 Name(asm_dialect) Type(enum asm_dialect)
123 Known assembler dialects (for use with the -masm-dialect= option):
126 Enum(asm_dialect) String(intel) Value(ASM_INTEL)
129 Enum(asm_dialect) String(att) Value(ASM_ATT)
132 Target RejectNegative Joined UInteger Var(ix86_branch_cost)
133 Branches are this expensive (1-5, arbitrary units)
135 mlarge-data-threshold=
136 Target RejectNegative Joined UInteger Var(ix86_section_threshold) Init(65536)
137 Data greater than given threshold will go into .ldata section in x86-64 medium model
140 Target RejectNegative Joined Enum(cmodel) Var(ix86_cmodel) Init(CM_32)
141 Use given x86-64 code model
144 Name(cmodel) Type(enum cmodel)
145 Known code models (for use with the -mcmodel= option):
148 Enum(cmodel) String(small) Value(CM_SMALL)
151 Enum(cmodel) String(medium) Value(CM_MEDIUM)
154 Enum(cmodel) String(large) Value(CM_LARGE)
157 Enum(cmodel) String(32) Value(CM_32)
160 Enum(cmodel) String(kernel) Value(CM_KERNEL)
163 Target RejectNegative Joined Undocumented Alias(mtune=) Warn(%<-mcpu=%> is deprecated; use %<-mtune=%> or %<-march=%> instead)
166 Target RejectNegative Report InverseMask(NO_FANCY_MATH_387, USE_FANCY_MATH_387) Save
167 Generate sin, cos, sqrt for FPU
170 Target Report Var(ix86_force_drap)
171 Always use Dynamic Realigned Argument Pointer (DRAP) to realign stack
174 Target Report Mask(FLOAT_RETURNS) Save
175 Return values of functions in FPU registers
178 Target RejectNegative Joined Var(ix86_fpmath) Enum(fpmath_unit) Init(FPMATH_387) Save
179 Generate floating point mathematics using given instruction set
182 Name(fpmath_unit) Type(enum fpmath_unit)
183 Valid arguments to -mfpmath=:
186 Enum(fpmath_unit) String(387) Value(FPMATH_387)
189 Enum(fpmath_unit) String(sse) Value(FPMATH_SSE)
192 Enum(fpmath_unit) String(387,sse) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)})
195 Enum(fpmath_unit) String(387+sse) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)})
198 Enum(fpmath_unit) String(sse,387) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)})
201 Enum(fpmath_unit) String(sse+387) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)})
204 Enum(fpmath_unit) String(both) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)})
207 Target RejectNegative Mask(80387) MaskExists Save
211 Target Report Mask(IEEE_FP) Save
212 Use IEEE math for fp comparisons
214 minline-all-stringops
215 Target Report Mask(INLINE_ALL_STRINGOPS) Save
216 Inline all known string operations
218 minline-stringops-dynamically
219 Target Report Mask(INLINE_STRINGOPS_DYNAMICALLY) Save
220 Inline memset/memcpy string operations, but perform inline version only for small blocks
223 Target Undocumented Alias(masm=, intel, att) Warn(%<-mintel-syntax%> and %<-mno-intel-syntax%> are deprecated; use %<-masm=intel%> and %<-masm=att%> instead)
227 Target Report Mask(MS_BITFIELD_LAYOUT) Save
228 Use native (MS) bitfield layout
231 Target RejectNegative Report Mask(NO_ALIGN_STRINGOPS) Undocumented Save
234 Target RejectNegative Report Mask(NO_FANCY_MATH_387) Undocumented Save
237 Target RejectNegative Report Mask(NO_PUSH_ARGS) Undocumented Save
240 Target RejectNegative Report Mask(NO_RED_ZONE) Undocumented Save
242 momit-leaf-frame-pointer
243 Target Report Mask(OMIT_LEAF_FRAME_POINTER) Save
244 Omit the frame pointer in leaf functions
247 Target RejectNegative Report
248 Set 80387 floating-point precision to 32-bit
251 Target RejectNegative Report
252 Set 80387 floating-point precision to 64-bit
255 Target RejectNegative Report
256 Set 80387 floating-point precision to 80-bit
258 mpreferred-stack-boundary=
259 Target RejectNegative Joined UInteger Var(ix86_preferred_stack_boundary_arg)
260 Attempt to keep stack aligned to this power of 2
262 mincoming-stack-boundary=
263 Target RejectNegative Joined UInteger Var(ix86_incoming_stack_boundary_arg)
264 Assume incoming stack aligned to this power of 2
267 Target Report InverseMask(NO_PUSH_ARGS, PUSH_ARGS) Save
268 Use push instructions to save outgoing arguments
271 Target RejectNegative Report InverseMask(NO_RED_ZONE, RED_ZONE) Save
272 Use red-zone in the x86-64 code
275 Target RejectNegative Joined UInteger Var(ix86_regparm)
276 Number of registers used to pass integer arguments
279 Target Report Mask(RTD) Save
280 Alternate calling convention
283 Target InverseMask(80387) Save
284 Do not use hardware fp
287 Target RejectNegative Mask(SSEREGPARM) Save
288 Use SSE register passing conventions for SF and DF mode
291 Target Report Var(ix86_force_align_arg_pointer) Init(-1)
292 Realign stack in prologue
295 Target Report Mask(STACK_PROBE) Save
299 Target RejectNegative Joined Enum(stringop_alg) Var(ix86_stringop_alg) Init(no_stringop)
300 Chose strategy to generate stringop using
303 Name(stringop_alg) Type(enum stringop_alg)
304 Valid arguments to -mstringop-strategy=:
307 Enum(stringop_alg) String(rep_byte) Value(rep_prefix_1_byte)
310 Enum(stringop_alg) String(libcall) Value(libcall)
313 Enum(stringop_alg) String(rep_4byte) Value(rep_prefix_4_byte)
316 Enum(stringop_alg) String(rep_8byte) Value(rep_prefix_8_byte)
319 Enum(stringop_alg) String(byte_loop) Value(loop_1_byte)
322 Enum(stringop_alg) String(loop) Value(loop)
325 Enum(stringop_alg) String(unrolled_loop) Value(unrolled_loop)
328 Target RejectNegative Joined Var(ix86_tls_dialect) Enum(tls_dialect) Init(TLS_DIALECT_GNU)
329 Use given thread-local storage dialect
332 Name(tls_dialect) Type(enum tls_dialect)
333 Known TLS dialects (for use with the -mtls-dialect= option):
336 Enum(tls_dialect) String(gnu) Value(TLS_DIALECT_GNU)
339 Enum(tls_dialect) String(gnu2) Value(TLS_DIALECT_GNU2)
342 Target Report Mask(TLS_DIRECT_SEG_REFS)
343 Use direct references against %gs when accessing tls data
346 Target RejectNegative Joined Var(ix86_tune_string)
347 Schedule code for given CPU
350 Target RejectNegative Joined Var(ix86_abi) Enum(calling_abi) Init(SYSV_ABI)
351 Generate code that conforms to the given ABI
354 Name(calling_abi) Type(enum calling_abi)
355 Known ABIs (for use with the -mabi= option):
358 Enum(calling_abi) String(sysv) Value(SYSV_ABI)
361 Enum(calling_abi) String(ms) Value(MS_ABI)
364 Target RejectNegative Joined Var(ix86_veclibabi_type) Enum(ix86_veclibabi) Init(ix86_veclibabi_type_none)
365 Vector library ABI to use
368 Name(ix86_veclibabi) Type(enum ix86_veclibabi)
369 Known vectorization library ABIs (for use with the -mveclibabi= option):
372 Enum(ix86_veclibabi) String(svml) Value(ix86_veclibabi_type_svml)
375 Enum(ix86_veclibabi) String(acml) Value(ix86_veclibabi_type_acml)
378 Target Report Mask(VECT8_RETURNS) Save
379 Return 8-byte vectors in memory
382 Target Report Mask(RECIP) Save
383 Generate reciprocals instead of divss and sqrtss.
386 Target Report RejectNegative Joined Var(ix86_recip_name)
387 Control generation of reciprocal estimates.
390 Target Report Mask(CLD) Save
391 Generate cld instruction in the function prologue.
394 Target Report Mask(VZEROUPPER) Save
395 Generate vzeroupper instruction before a transfer of control flow out of
399 Target RejectNegative Var(flag_dispatch_scheduler)
400 Do dispatch scheduling if processor is bdver1 or bdver2 and Haifa scheduling
404 Target Report Mask(PREFER_AVX128) SAVE
405 Use 128-bit AVX instructions instead of 256-bit AVX instructions in the auto-vectorizer.
410 Target RejectNegative Negative(m64) Report InverseMask(ISA_64BIT) Var(ix86_isa_flags) Save
411 Generate 32bit i386 code
414 Target RejectNegative Negative(mx32) Report Mask(ISA_64BIT) Var(ix86_isa_flags) Save
415 Generate 64bit x86-64 code
418 Target RejectNegative Negative(m32) Report Mask(ISA_X32) Var(ix86_isa_flags) Save
419 Generate 32bit x86-64 code
422 Target Report Mask(ISA_MMX) Var(ix86_isa_flags) Save
423 Support MMX built-in functions
426 Target Report Mask(ISA_3DNOW) Var(ix86_isa_flags) Save
427 Support 3DNow! built-in functions
430 Target Undocumented Mask(ISA_3DNOW_A) Var(ix86_isa_flags) Save
431 Support Athlon 3Dnow! built-in functions
434 Target Report Mask(ISA_SSE) Var(ix86_isa_flags) Save
435 Support MMX and SSE built-in functions and code generation
438 Target Report Mask(ISA_SSE2) Var(ix86_isa_flags) Save
439 Support MMX, SSE and SSE2 built-in functions and code generation
442 Target Report Mask(ISA_SSE3) Var(ix86_isa_flags) Save
443 Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation
446 Target Report Mask(ISA_SSSE3) Var(ix86_isa_flags) Save
447 Support MMX, SSE, SSE2, SSE3 and SSSE3 built-in functions and code generation
450 Target Report Mask(ISA_SSE4_1) Var(ix86_isa_flags) Save
451 Support MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 built-in functions and code generation
454 Target Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save
455 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation
458 Target RejectNegative Report Mask(ISA_SSE4_2) MaskExists Var(ix86_isa_flags) Save
459 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation
462 Target RejectNegative Report InverseMask(ISA_SSE4_1) MaskExists Var(ix86_isa_flags) Save
463 Do not support SSE4.1 and SSE4.2 built-in functions and code generation
466 Target Undocumented Alias(mavx) Warn(%<-msse5%> was removed)
470 Target Report Mask(ISA_AVX) Var(ix86_isa_flags) Save
471 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 and AVX built-in functions and code generation
474 Target Report Mask(ISA_AVX2) Var(ix86_isa_flags) Save
475 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and AVX2 built-in functions and code generation
478 Target Report Mask(ISA_FMA) Var(ix86_isa_flags) Save
479 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and FMA built-in functions and code generation
482 Target Report Mask(ISA_SSE4A) Var(ix86_isa_flags) Save
483 Support MMX, SSE, SSE2, SSE3 and SSE4A built-in functions and code generation
486 Target Report Mask(ISA_FMA4) Var(ix86_isa_flags) Save
487 Support FMA4 built-in functions and code generation
490 Target Report Mask(ISA_XOP) Var(ix86_isa_flags) Save
491 Support XOP built-in functions and code generation
494 Target Report Mask(ISA_LWP) Var(ix86_isa_flags) Save
495 Support LWP built-in functions and code generation
498 Target Report Mask(ISA_ABM) Var(ix86_isa_flags) Save
499 Support code generation of Advanced Bit Manipulation (ABM) instructions.
502 Target Report Mask(ISA_POPCNT) Var(ix86_isa_flags) Save
503 Support code generation of popcnt instruction.
506 Target Report Mask(ISA_BMI) Var(ix86_isa_flags) Save
507 Support BMI built-in functions and code generation
510 Target Report Mask(ISA_BMI2) Var(ix86_isa_flags) Save
511 Support BMI2 built-in functions and code generation
514 Target Report Mask(ISA_LZCNT) Var(ix86_isa_flags) Save
515 Support LZCNT built-in function and code generation
518 Target Report Mask(ISA_TBM) Var(ix86_isa_flags) Save
519 Support TBM built-in functions and code generation
522 Target Report Mask(ISA_CX16) Var(ix86_isa_flags) Save
523 Support code generation of cmpxchg16b instruction.
526 Target Report Mask(ISA_SAHF) Var(ix86_isa_flags) Save
527 Support code generation of sahf instruction in 64bit x86-64 code.
530 Target Report Mask(ISA_MOVBE) Var(ix86_isa_flags) Save
531 Support code generation of movbe instruction.
534 Target Report Mask(ISA_CRC32) Var(ix86_isa_flags) Save
535 Support code generation of crc32 instruction.
538 Target Report Mask(ISA_AES) Var(ix86_isa_flags) Save
539 Support AES built-in functions and code generation
542 Target Report Mask(ISA_PCLMUL) Var(ix86_isa_flags) Save
543 Support PCLMUL built-in functions and code generation
546 Target Report Var(ix86_sse2avx)
547 Encode SSE instructions with VEX prefix
550 Target Report Mask(ISA_FSGSBASE) Var(ix86_isa_flags) Save
551 Support FSGSBASE built-in functions and code generation
554 Target Report Mask(ISA_RDRND) Var(ix86_isa_flags) Save
555 Support RDRND built-in functions and code generation
558 Target Report Mask(ISA_F16C) Var(ix86_isa_flags) Save
559 Support F16C built-in functions and code generation
562 Target Report Var(flag_fentry) Init(-1)
563 Emit profiling counter call at function entry before prologue.
566 Target Report Mask(USE_8BIT_IDIV) Save
567 Expand 32bit/64bit integer divide into 8bit unsigned integer divide with run-time check
569 mavx256-split-unaligned-load
570 Target Report Mask(AVX256_SPLIT_UNALIGNED_LOAD) Save
571 Split 32-byte AVX unaligned load
573 mavx256-split-unaligned-store
574 Target Report Mask(AVX256_SPLIT_UNALIGNED_STORE) Save
575 Split 32-byte AVX unaligned store