sys/dev/drm/mga_dma.c

   1 /* mga_dma.c -- DMA support for mga g200/g400 -*- linux-c -*-
   2  * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
   3  */
   4 /* Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
   5  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25  * DEALINGS IN THE SOFTWARE.
  26  *
  27  * $DragonFly: src/sys/dev/drm/mga_dma.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
  28  */
  29
  30 /**
  31  * \file mga_dma.c
  32  * DMA support for MGA G200 / G400.
  33  *
  34  * \author Rickard E. (Rik) Faith <faith@valinux.com>
  35  * \author Jeff Hartmann <jhartmann@valinux.com>
  36  * \author Keith Whitwell <keith@tungstengraphics.com>
  37  * \author Gareth Hughes <gareth@valinux.com>
  38  */
  39
  40 #include "drmP.h"
  41 #include "drm.h"
  42 #include "drm_sarea.h"
  43 #include "mga_drm.h"
  44 #include "mga_drv.h"
  45
  46 #define MGA_DEFAULT_USEC_TIMEOUT        10000
  47 #define MGA_FREELIST_DEBUG              0
  48
  49 #define MINIMAL_CLEANUP    0
  50 #define FULL_CLEANUP       1
  51 static int mga_do_cleanup_dma(struct drm_device *dev, int full_cleanup);
  52
  53 /* ================================================================
  54  * Engine control
  55  */
  56
  57 int mga_do_wait_for_idle(drm_mga_private_t * dev_priv)
  58 {
  59         u32 status = 0;
  60         int i;
  61         DRM_DEBUG("\n");
  62
  63         for (i = 0; i < dev_priv->usec_timeout; i++) {
  64                 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
  65                 if (status == MGA_ENDPRDMASTS) {
  66                         MGA_WRITE8(MGA_CRTC_INDEX, 0);
  67                         return 0;
  68                 }
  69                 DRM_UDELAY(1);
  70         }
  71
  72 #if MGA_DMA_DEBUG
  73         DRM_ERROR("failed!\n");
  74         DRM_INFO("   status=0x%08x\n", status);
  75 #endif
  76         return -EBUSY;
  77 }
  78
  79 static int mga_do_dma_reset(drm_mga_private_t * dev_priv)
  80 {
  81         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
  82         drm_mga_primary_buffer_t *primary = &dev_priv->prim;
  83
  84         DRM_DEBUG("\n");
  85
  86         /* The primary DMA stream should look like new right about now.
  87          */
  88         primary->tail = 0;
  89         primary->space = primary->size;
  90         primary->last_flush = 0;
  91
  92         sarea_priv->last_wrap = 0;
  93
  94         /* FIXME: Reset counters, buffer ages etc...
  95          */
  96
  97         /* FIXME: What else do we need to reinitialize?  WARP stuff?
  98          */
  99
 100         return 0;
 101 }
 102
 103 /* ================================================================
 104  * Primary DMA stream
 105  */
 106
 107 void mga_do_dma_flush(drm_mga_private_t * dev_priv)
 108 {
 109         drm_mga_primary_buffer_t *primary = &dev_priv->prim;
 110         u32 head, tail;
 111         u32 status = 0;
 112         int i;
 113         DMA_LOCALS;
 114         DRM_DEBUG("\n");
 115
 116         /* We need to wait so that we can do an safe flush */
 117         for (i = 0; i < dev_priv->usec_timeout; i++) {
 118                 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
 119                 if (status == MGA_ENDPRDMASTS)
 120                         break;
 121                 DRM_UDELAY(1);
 122         }
 123
 124         if (primary->tail == primary->last_flush) {
 125                 DRM_DEBUG("   bailing out...\n");
 126                 return;
 127         }
 128
 129         tail = primary->tail + dev_priv->primary->offset;
 130
 131         /* We need to pad the stream between flushes, as the card
 132          * actually (partially?) reads the first of these commands.
 133          * See page 4-16 in the G400 manual, middle of the page or so.
 134          */
 135         BEGIN_DMA(1);
 136
 137         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 138                   MGA_DMAPAD, 0x00000000,
 139                   MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
 140
 141         ADVANCE_DMA();
 142
 143         primary->last_flush = primary->tail;
 144
 145         head = MGA_READ(MGA_PRIMADDRESS);
 146
 147         if (head <= tail) {
 148                 primary->space = primary->size - primary->tail;
 149         } else {
 150                 primary->space = head - tail;
 151         }
 152
 153         DRM_DEBUG("   head = 0x%06lx\n", head - dev_priv->primary->offset);
 154         DRM_DEBUG("   tail = 0x%06lx\n", tail - dev_priv->primary->offset);
 155         DRM_DEBUG("  space = 0x%06x\n", primary->space);
 156
 157         mga_flush_write_combine();
 158         MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access);
 159
 160         DRM_DEBUG("done.\n");
 161 }
 162
 163 void mga_do_dma_wrap_start(drm_mga_private_t * dev_priv)
 164 {
 165         drm_mga_primary_buffer_t *primary = &dev_priv->prim;
 166         u32 head, tail;
 167         DMA_LOCALS;
 168         DRM_DEBUG("\n");
 169
 170         BEGIN_DMA_WRAP();
 171
 172         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 173                   MGA_DMAPAD, 0x00000000,
 174                   MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
 175
 176         ADVANCE_DMA();
 177
 178         tail = primary->tail + dev_priv->primary->offset;
 179
 180         primary->tail = 0;
 181         primary->last_flush = 0;
 182         primary->last_wrap++;
 183
 184         head = MGA_READ(MGA_PRIMADDRESS);
 185
 186         if (head == dev_priv->primary->offset) {
 187                 primary->space = primary->size;
 188         } else {
 189                 primary->space = head - dev_priv->primary->offset;
 190         }
 191
 192         DRM_DEBUG("   head = 0x%06lx\n", head - dev_priv->primary->offset);
 193         DRM_DEBUG("   tail = 0x%06x\n", primary->tail);
 194         DRM_DEBUG("   wrap = %d\n", primary->last_wrap);
 195         DRM_DEBUG("  space = 0x%06x\n", primary->space);
 196
 197         mga_flush_write_combine();
 198         MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access);
 199
 200         set_bit(0, &primary->wrapped);
 201         DRM_DEBUG("done.\n");
 202 }
 203
 204 void mga_do_dma_wrap_end(drm_mga_private_t * dev_priv)
 205 {
 206         drm_mga_primary_buffer_t *primary = &dev_priv->prim;
 207         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 208         u32 head = dev_priv->primary->offset;
 209         DRM_DEBUG("\n");
 210
 211         sarea_priv->last_wrap++;
 212         DRM_DEBUG("   wrap = %d\n", sarea_priv->last_wrap);
 213
 214         mga_flush_write_combine();
 215         MGA_WRITE(MGA_PRIMADDRESS, head | MGA_DMA_GENERAL);
 216
 217         clear_bit(0, &primary->wrapped);
 218         DRM_DEBUG("done.\n");
 219 }
 220
 221 /* ================================================================
 222  * Freelist management
 223  */
 224
 225 #define MGA_BUFFER_USED         ~0
 226 #define MGA_BUFFER_FREE         0
 227
 228 #if MGA_FREELIST_DEBUG
 229 static void mga_freelist_print(struct drm_device * dev)
 230 {
 231         drm_mga_private_t *dev_priv = dev->dev_private;
 232         drm_mga_freelist_t *entry;
 233
 234         DRM_INFO("\n");
 235         DRM_INFO("current dispatch: last=0x%x done=0x%x\n",
 236                  dev_priv->sarea_priv->last_dispatch,
 237                  (unsigned int)(MGA_READ(MGA_PRIMADDRESS) -
 238                                 dev_priv->primary->offset));
 239         DRM_INFO("current freelist:\n");
 240
 241         for (entry = dev_priv->head->next; entry; entry = entry->next) {
 242                 DRM_INFO("   %p   idx=%2d  age=0x%x 0x%06lx\n",
 243                          entry, entry->buf->idx, entry->age.head,
 244                          entry->age.head - dev_priv->primary->offset);
 245         }
 246         DRM_INFO("\n");
 247 }
 248 #endif
 249
 250 static int mga_freelist_init(struct drm_device * dev, drm_mga_private_t * dev_priv)
 251 {
 252         struct drm_device_dma *dma = dev->dma;
 253         struct drm_buf *buf;
 254         drm_mga_buf_priv_t *buf_priv;
 255         drm_mga_freelist_t *entry;
 256         int i;
 257         DRM_DEBUG("count=%d\n", dma->buf_count);
 258
 259         dev_priv->head = drm_alloc(sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER);
 260         if (dev_priv->head == NULL)
 261                 return -ENOMEM;
 262
 263         memset(dev_priv->head, 0, sizeof(drm_mga_freelist_t));
 264         SET_AGE(&dev_priv->head->age, MGA_BUFFER_USED, 0);
 265
 266         for (i = 0; i < dma->buf_count; i++) {
 267                 buf = dma->buflist[i];
 268                 buf_priv = buf->dev_private;
 269
 270                 entry = drm_alloc(sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER);
 271                 if (entry == NULL)
 272                         return -ENOMEM;
 273
 274                 memset(entry, 0, sizeof(drm_mga_freelist_t));
 275
 276                 entry->next = dev_priv->head->next;
 277                 entry->prev = dev_priv->head;
 278                 SET_AGE(&entry->age, MGA_BUFFER_FREE, 0);
 279                 entry->buf = buf;
 280
 281                 if (dev_priv->head->next != NULL)
 282                         dev_priv->head->next->prev = entry;
 283                 if (entry->next == NULL)
 284                         dev_priv->tail = entry;
 285
 286                 buf_priv->list_entry = entry;
 287                 buf_priv->discard = 0;
 288                 buf_priv->dispatched = 0;
 289
 290                 dev_priv->head->next = entry;
 291         }
 292
 293         return 0;
 294 }
 295
 296 static void mga_freelist_cleanup(struct drm_device * dev)
 297 {
 298         drm_mga_private_t *dev_priv = dev->dev_private;
 299         drm_mga_freelist_t *entry;
 300         drm_mga_freelist_t *next;
 301         DRM_DEBUG("\n");
 302
 303         entry = dev_priv->head;
 304         while (entry) {
 305                 next = entry->next;
 306                 drm_free(entry, sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER);
 307                 entry = next;
 308         }
 309
 310         dev_priv->head = dev_priv->tail = NULL;
 311 }
 312
 313 #if 0
 314 /* FIXME: Still needed?
 315  */
 316 static void mga_freelist_reset(struct drm_device * dev)
 317 {
 318         drm_device_dma_t *dma = dev->dma;
 319         struct drm_buf *buf;
 320         drm_mga_buf_priv_t *buf_priv;
 321         int i;
 322
 323         for (i = 0; i < dma->buf_count; i++) {
 324                 buf = dma->buflist[i];
 325                 buf_priv = buf->dev_private;
 326                 SET_AGE(&buf_priv->list_entry->age, MGA_BUFFER_FREE, 0);
 327         }
 328 }
 329 #endif
 330
 331 static struct drm_buf *mga_freelist_get(struct drm_device * dev)
 332 {
 333         drm_mga_private_t *dev_priv = dev->dev_private;
 334         drm_mga_freelist_t *next;
 335         drm_mga_freelist_t *prev;
 336         drm_mga_freelist_t *tail = dev_priv->tail;
 337         u32 head, wrap;
 338         DRM_DEBUG("\n");
 339
 340         head = MGA_READ(MGA_PRIMADDRESS);
 341         wrap = dev_priv->sarea_priv->last_wrap;
 342
 343         DRM_DEBUG("   tail=0x%06lx %d\n",
 344                   tail->age.head ?
 345                   tail->age.head - dev_priv->primary->offset : 0,
 346                   tail->age.wrap);
 347         DRM_DEBUG("   head=0x%06lx %d\n",
 348                   head - dev_priv->primary->offset, wrap);
 349
 350         if (TEST_AGE(&tail->age, head, wrap)) {
 351                 prev = dev_priv->tail->prev;
 352                 next = dev_priv->tail;
 353                 prev->next = NULL;
 354                 next->prev = next->next = NULL;
 355                 dev_priv->tail = prev;
 356                 SET_AGE(&next->age, MGA_BUFFER_USED, 0);
 357                 return next->buf;
 358         }
 359
 360         DRM_DEBUG("returning NULL!\n");
 361         return NULL;
 362 }
 363
 364 int mga_freelist_put(struct drm_device * dev, struct drm_buf * buf)
 365 {
 366         drm_mga_private_t *dev_priv = dev->dev_private;
 367         drm_mga_buf_priv_t *buf_priv = buf->dev_private;
 368         drm_mga_freelist_t *head, *entry, *prev;
 369
 370         DRM_DEBUG("age=0x%06lx wrap=%d\n",
 371                   buf_priv->list_entry->age.head -
 372                   dev_priv->primary->offset, buf_priv->list_entry->age.wrap);
 373
 374         entry = buf_priv->list_entry;
 375         head = dev_priv->head;
 376
 377         if (buf_priv->list_entry->age.head == MGA_BUFFER_USED) {
 378                 SET_AGE(&entry->age, MGA_BUFFER_FREE, 0);
 379                 prev = dev_priv->tail;
 380                 prev->next = entry;
 381                 entry->prev = prev;
 382                 entry->next = NULL;
 383         } else {
 384                 prev = head->next;
 385                 head->next = entry;
 386                 prev->prev = entry;
 387                 entry->prev = head;
 388                 entry->next = prev;
 389         }
 390
 391         return 0;
 392 }
 393
 394 /* ================================================================
 395  * DMA initialization, cleanup
 396  */
 397
 398 int mga_driver_load(struct drm_device *dev, unsigned long flags)
 399 {
 400         drm_mga_private_t *dev_priv;
 401
 402         dev_priv = drm_alloc(sizeof(drm_mga_private_t), DRM_MEM_DRIVER);
 403         if (!dev_priv)
 404                 return -ENOMEM;
 405
 406         dev->dev_private = (void *)dev_priv;
 407         memset(dev_priv, 0, sizeof(drm_mga_private_t));
 408
 409         dev_priv->usec_timeout = MGA_DEFAULT_USEC_TIMEOUT;
 410         dev_priv->chipset = flags;
 411
 412         dev_priv->mmio_base = drm_get_resource_start(dev, 1);
 413         dev_priv->mmio_size = drm_get_resource_len(dev, 1);
 414
 415         dev->counters += 3;
 416         dev->types[6] = _DRM_STAT_IRQ;
 417         dev->types[7] = _DRM_STAT_PRIMARY;
 418         dev->types[8] = _DRM_STAT_SECONDARY;
 419
 420         return 0;
 421 }
 422
 423 /**
 424  * Bootstrap the driver for AGP DMA.
 425  *
 426  * \todo
 427  * Investigate whether there is any benifit to storing the WARP microcode in
 428  * AGP memory.  If not, the microcode may as well always be put in PCI
 429  * memory.
 430  *
 431  * \todo
 432  * This routine needs to set dma_bs->agp_mode to the mode actually configured
 433  * in the hardware.  Looking just at the Linux AGP driver code, I don't see
 434  * an easy way to determine this.
 435  *
 436  * \sa mga_do_dma_bootstrap, mga_do_pci_dma_bootstrap
 437  */
 438 static int mga_do_agp_dma_bootstrap(struct drm_device *dev,
 439                                     drm_mga_dma_bootstrap_t * dma_bs)
 440 {
 441         drm_mga_private_t *const dev_priv =
 442                 (drm_mga_private_t *)dev->dev_private;
 443         unsigned int warp_size = mga_warp_microcode_size(dev_priv);
 444         int err;
 445         unsigned offset;
 446         const unsigned secondary_size = dma_bs->secondary_bin_count
 447                 * dma_bs->secondary_bin_size;
 448         const unsigned agp_size = (dma_bs->agp_size << 20);
 449         struct drm_buf_desc req;
 450         struct drm_agp_mode mode;
 451         struct drm_agp_info info;
 452         struct drm_agp_buffer agp_req;
 453         struct drm_agp_binding bind_req;
 454
 455         /* Acquire AGP. */
 456         err = drm_agp_acquire(dev);
 457         if (err) {
 458                 DRM_ERROR("Unable to acquire AGP: %d\n", err);
 459                 return err;
 460         }
 461
 462         err = drm_agp_info(dev, &info);
 463         if (err) {
 464                 DRM_ERROR("Unable to get AGP info: %d\n", err);
 465                 return err;
 466         }
 467
 468         mode.mode = (info.mode & ~0x07) | dma_bs->agp_mode;
 469         err = drm_agp_enable(dev, mode);
 470         if (err) {
 471                 DRM_ERROR("Unable to enable AGP (mode = 0x%lx)\n", mode.mode);
 472                 return err;
 473         }
 474
 475         /* In addition to the usual AGP mode configuration, the G200 AGP cards
 476          * need to have the AGP mode "manually" set.
 477          */
 478
 479         if (dev_priv->chipset == MGA_CARD_TYPE_G200) {
 480                 if (mode.mode & 0x02) {
 481                         MGA_WRITE(MGA_AGP_PLL, MGA_AGP2XPLL_ENABLE);
 482                 } else {
 483                         MGA_WRITE(MGA_AGP_PLL, MGA_AGP2XPLL_DISABLE);
 484                 }
 485         }
 486
 487         /* Allocate and bind AGP memory. */
 488         agp_req.size = agp_size;
 489         agp_req.type = 0;
 490         err = drm_agp_alloc(dev, &agp_req);
 491         if (err) {
 492                 dev_priv->agp_size = 0;
 493                 DRM_ERROR("Unable to allocate %uMB AGP memory\n",
 494                           dma_bs->agp_size);
 495                 return err;
 496         }
 497
 498         dev_priv->agp_size = agp_size;
 499         dev_priv->agp_handle = agp_req.handle;
 500
 501         bind_req.handle = agp_req.handle;
 502         bind_req.offset = 0;
 503         err = drm_agp_bind( dev, &bind_req );
 504         if (err) {
 505                 DRM_ERROR("Unable to bind AGP memory: %d\n", err);
 506                 return err;
 507         }
 508
 509         /* Make drm_addbufs happy by not trying to create a mapping for less
 510          * than a page.
 511          */
 512         if (warp_size < PAGE_SIZE)
 513                 warp_size = PAGE_SIZE;
 514
 515         offset = 0;
 516         err = drm_addmap(dev, offset, warp_size,
 517                          _DRM_AGP, _DRM_READ_ONLY, &dev_priv->warp);
 518         if (err) {
 519                 DRM_ERROR("Unable to map WARP microcode: %d\n", err);
 520                 return err;
 521         }
 522
 523         offset += warp_size;
 524         err = drm_addmap(dev, offset, dma_bs->primary_size,
 525                          _DRM_AGP, _DRM_READ_ONLY, & dev_priv->primary);
 526         if (err) {
 527                 DRM_ERROR("Unable to map primary DMA region: %d\n", err);
 528                 return err;
 529         }
 530
 531         offset += dma_bs->primary_size;
 532         err = drm_addmap(dev, offset, secondary_size,
 533                          _DRM_AGP, 0, & dev->agp_buffer_map);
 534         if (err) {
 535                 DRM_ERROR("Unable to map secondary DMA region: %d\n", err);
 536                 return err;
 537         }
 538
 539         (void)memset( &req, 0, sizeof(req) );
 540         req.count = dma_bs->secondary_bin_count;
 541         req.size = dma_bs->secondary_bin_size;
 542         req.flags = _DRM_AGP_BUFFER;
 543         req.agp_start = offset;
 544
 545         err = drm_addbufs_agp(dev, &req);
 546         if (err) {
 547                 DRM_ERROR("Unable to add secondary DMA buffers: %d\n", err);
 548                 return err;
 549         }
 550
 551 #ifdef __linux__
 552         {
 553                 struct drm_map_list *_entry;
 554                 unsigned long agp_token = 0;
 555
 556                 list_for_each_entry(_entry, &dev->maplist, head) {
 557                         if (_entry->map == dev->agp_buffer_map)
 558                                 agp_token = _entry->user_token;
 559                 }
 560                 if (!agp_token)
 561                         return -EFAULT;
 562
 563                 dev->agp_buffer_token = agp_token;
 564         }
 565 #endif
 566
 567         offset += secondary_size;
 568         err = drm_addmap(dev, offset, agp_size - offset,
 569                          _DRM_AGP, 0, & dev_priv->agp_textures);
 570         if (err) {
 571                 DRM_ERROR("Unable to map AGP texture region: %d\n", err);
 572                 return err;
 573         }
 574
 575         drm_core_ioremap(dev_priv->warp, dev);
 576         drm_core_ioremap(dev_priv->primary, dev);
 577         drm_core_ioremap(dev->agp_buffer_map, dev);
 578
 579         if (!dev_priv->warp->handle ||
 580             !dev_priv->primary->handle || !dev->agp_buffer_map->handle) {
 581                 DRM_ERROR("failed to ioremap agp regions! (%p, %p, %p)\n",
 582                           dev_priv->warp->handle, dev_priv->primary->handle,
 583                           dev->agp_buffer_map->handle);
 584                 return -ENOMEM;
 585         }
 586
 587         dev_priv->dma_access = MGA_PAGPXFER;
 588         dev_priv->wagp_enable = MGA_WAGP_ENABLE;
 589
 590         DRM_INFO("Initialized card for AGP DMA.\n");
 591         return 0;
 592 }
 593
 594 /**
 595  * Bootstrap the driver for PCI DMA.
 596  *
 597  * \todo
 598  * The algorithm for decreasing the size of the primary DMA buffer could be
 599  * better.  The size should be rounded up to the nearest page size, then
 600  * decrease the request size by a single page each pass through the loop.
 601  *
 602  * \todo
 603  * Determine whether the maximum address passed to drm_pci_alloc is correct.
 604  * The same goes for drm_addbufs_pci.
 605  *
 606  * \sa mga_do_dma_bootstrap, mga_do_agp_dma_bootstrap
 607  */
 608 static int mga_do_pci_dma_bootstrap(struct drm_device * dev,
 609                                     drm_mga_dma_bootstrap_t * dma_bs)
 610 {
 611         drm_mga_private_t *const dev_priv =
 612                 (drm_mga_private_t *) dev->dev_private;
 613         unsigned int warp_size = mga_warp_microcode_size(dev_priv);
 614         unsigned int primary_size;
 615         unsigned int bin_count;
 616         int err;
 617         struct drm_buf_desc req;
 618
 619
 620         if (dev->dma == NULL) {
 621                 DRM_ERROR("dev->dma is NULL\n");
 622                 return -EFAULT;
 623         }
 624
 625         /* Make drm_addbufs happy by not trying to create a mapping for less
 626          * than a page.
 627          */
 628         if (warp_size < PAGE_SIZE)
 629                 warp_size = PAGE_SIZE;
 630
 631         /* The proper alignment is 0x100 for this mapping */
 632         err = drm_addmap(dev, 0, warp_size, _DRM_CONSISTENT,
 633                          _DRM_READ_ONLY, &dev_priv->warp);
 634         if (err != 0) {
 635                 DRM_ERROR("Unable to create mapping for WARP microcode: %d\n",
 636                           err);
 637                 return err;
 638         }
 639
 640         /* Other than the bottom two bits being used to encode other
 641          * information, there don't appear to be any restrictions on the
 642          * alignment of the primary or secondary DMA buffers.
 643          */
 644
 645         for (primary_size = dma_bs->primary_size; primary_size != 0;
 646              primary_size >>= 1 ) {
 647                 /* The proper alignment for this mapping is 0x04 */
 648                 err = drm_addmap(dev, 0, primary_size, _DRM_CONSISTENT,
 649                                  _DRM_READ_ONLY, &dev_priv->primary);
 650                 if (!err)
 651                         break;
 652         }
 653
 654         if (err != 0) {
 655                 DRM_ERROR("Unable to allocate primary DMA region: %d\n", err);
 656                 return -ENOMEM;
 657         }
 658
 659         if (dev_priv->primary->size != dma_bs->primary_size) {
 660                 DRM_INFO("Primary DMA buffer size reduced from %u to %u.\n",
 661                          dma_bs->primary_size,
 662                          (unsigned)dev_priv->primary->size);
 663                 dma_bs->primary_size = dev_priv->primary->size;
 664         }
 665
 666         for (bin_count = dma_bs->secondary_bin_count; bin_count > 0;
 667              bin_count-- ) {
 668                 (void)memset(&req, 0, sizeof(req));
 669                 req.count = bin_count;
 670                 req.size = dma_bs->secondary_bin_size;
 671
 672                 err = drm_addbufs_pci(dev, &req);
 673                 if (!err) {
 674                         break;
 675                 }
 676         }
 677
 678         if (bin_count == 0) {
 679                 DRM_ERROR("Unable to add secondary DMA buffers: %d\n", err);
 680                 return err;
 681         }
 682
 683         if (bin_count != dma_bs->secondary_bin_count) {
 684                 DRM_INFO("Secondary PCI DMA buffer bin count reduced from %u "
 685                          "to %u.\n", dma_bs->secondary_bin_count, bin_count);
 686
 687                 dma_bs->secondary_bin_count = bin_count;
 688         }
 689
 690         dev_priv->dma_access = 0;
 691         dev_priv->wagp_enable = 0;
 692
 693         dma_bs->agp_mode = 0;
 694
 695         DRM_INFO("Initialized card for PCI DMA.\n");
 696         return 0;
 697 }
 698
 699
 700 static int mga_do_dma_bootstrap(struct drm_device *dev,
 701                                 drm_mga_dma_bootstrap_t *dma_bs)
 702 {
 703         const int is_agp = (dma_bs->agp_mode != 0) && drm_device_is_agp(dev);
 704         int err;
 705         drm_mga_private_t *const dev_priv =
 706                 (drm_mga_private_t *) dev->dev_private;
 707
 708
 709         dev_priv->used_new_dma_init = 1;
 710
 711         /* The first steps are the same for both PCI and AGP based DMA.  Map
 712          * the cards MMIO registers and map a status page.
 713          */
 714         err = drm_addmap(dev, dev_priv->mmio_base, dev_priv->mmio_size,
 715                          _DRM_REGISTERS, _DRM_READ_ONLY, & dev_priv->mmio);
 716         if (err) {
 717                 DRM_ERROR("Unable to map MMIO region: %d\n", err);
 718                 return err;
 719         }
 720
 721
 722         err = drm_addmap(dev, 0, SAREA_MAX, _DRM_SHM,
 723                          _DRM_READ_ONLY | _DRM_LOCKED | _DRM_KERNEL,
 724                          & dev_priv->status);
 725         if (err) {
 726                 DRM_ERROR("Unable to map status region: %d\n", err);
 727                 return err;
 728         }
 729
 730
 731         /* The DMA initialization procedure is slightly different for PCI and
 732          * AGP cards.  AGP cards just allocate a large block of AGP memory and
 733          * carve off portions of it for internal uses.  The remaining memory
 734          * is returned to user-mode to be used for AGP textures.
 735          */
 736
 737         if (is_agp) {
 738                 err = mga_do_agp_dma_bootstrap(dev, dma_bs);
 739         }
 740
 741         /* If we attempted to initialize the card for AGP DMA but failed,
 742          * clean-up any mess that may have been created.
 743          */
 744
 745         if (err) {
 746                 mga_do_cleanup_dma(dev, MINIMAL_CLEANUP);
 747         }
 748
 749
 750         /* Not only do we want to try and initialized PCI cards for PCI DMA,
 751          * but we also try to initialized AGP cards that could not be
 752          * initialized for AGP DMA.  This covers the case where we have an AGP
 753          * card in a system with an unsupported AGP chipset.  In that case the
 754          * card will be detected as AGP, but we won't be able to allocate any
 755          * AGP memory, etc.
 756          */
 757
 758         if (!is_agp || err) {
 759                 err = mga_do_pci_dma_bootstrap(dev, dma_bs);
 760         }
 761
 762
 763         return err;
 764 }
 765
 766 int mga_dma_bootstrap(struct drm_device *dev, void *data,
 767                       struct drm_file *file_priv)
 768 {
 769         drm_mga_dma_bootstrap_t *bootstrap = data;
 770         int err;
 771         static const int modes[] = { 0, 1, 2, 2, 4, 4, 4, 4 };
 772         const drm_mga_private_t *const dev_priv =
 773                 (drm_mga_private_t *) dev->dev_private;
 774
 775
 776         err = mga_do_dma_bootstrap(dev, bootstrap);
 777         if (err) {
 778                 mga_do_cleanup_dma(dev, FULL_CLEANUP);
 779                 return err;
 780         }
 781
 782         if (dev_priv->agp_textures != NULL) {
 783                 bootstrap->texture_handle = dev_priv->agp_textures->offset;
 784                 bootstrap->texture_size = dev_priv->agp_textures->size;
 785         } else {
 786                 bootstrap->texture_handle = 0;
 787                 bootstrap->texture_size = 0;
 788         }
 789
 790         bootstrap->agp_mode = modes[bootstrap->agp_mode & 0x07];
 791
 792         return 0;
 793 }
 794
 795
 796 static int mga_do_init_dma(struct drm_device * dev, drm_mga_init_t * init)
 797 {
 798         drm_mga_private_t *dev_priv;
 799         int ret;
 800         DRM_DEBUG("\n");
 801
 802
 803         dev_priv = dev->dev_private;
 804
 805         if (init->sgram) {
 806                 dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_BLK;
 807         } else {
 808                 dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_RSTR;
 809         }
 810         dev_priv->maccess = init->maccess;
 811
 812         dev_priv->fb_cpp = init->fb_cpp;
 813         dev_priv->front_offset = init->front_offset;
 814         dev_priv->front_pitch = init->front_pitch;
 815         dev_priv->back_offset = init->back_offset;
 816         dev_priv->back_pitch = init->back_pitch;
 817
 818         dev_priv->depth_cpp = init->depth_cpp;
 819         dev_priv->depth_offset = init->depth_offset;
 820         dev_priv->depth_pitch = init->depth_pitch;
 821
 822         /* FIXME: Need to support AGP textures...
 823          */
 824         dev_priv->texture_offset = init->texture_offset[0];
 825         dev_priv->texture_size = init->texture_size[0];
 826
 827         dev_priv->sarea = drm_getsarea(dev);
 828         if (!dev_priv->sarea) {
 829                 DRM_ERROR("failed to find sarea!\n");
 830                 return -EINVAL;
 831         }
 832
 833         if (!dev_priv->used_new_dma_init) {
 834
 835                 dev_priv->dma_access = MGA_PAGPXFER;
 836                 dev_priv->wagp_enable = MGA_WAGP_ENABLE;
 837
 838                 dev_priv->status = drm_core_findmap(dev, init->status_offset);
 839                 if (!dev_priv->status) {
 840                         DRM_ERROR("failed to find status page!\n");
 841                         return -EINVAL;
 842                 }
 843                 dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
 844                 if (!dev_priv->mmio) {
 845                         DRM_ERROR("failed to find mmio region!\n");
 846                         return -EINVAL;
 847                 }
 848                 dev_priv->warp = drm_core_findmap(dev, init->warp_offset);
 849                 if (!dev_priv->warp) {
 850                         DRM_ERROR("failed to find warp microcode region!\n");
 851                         return -EINVAL;
 852                 }
 853                 dev_priv->primary = drm_core_findmap(dev, init->primary_offset);
 854                 if (!dev_priv->primary) {
 855                         DRM_ERROR("failed to find primary dma region!\n");
 856                         return -EINVAL;
 857                 }
 858                 dev->agp_buffer_token = init->buffers_offset;
 859                 dev->agp_buffer_map =
 860                         drm_core_findmap(dev, init->buffers_offset);
 861                 if (!dev->agp_buffer_map) {
 862                         DRM_ERROR("failed to find dma buffer region!\n");
 863                         return -EINVAL;
 864                 }
 865
 866                 drm_core_ioremap(dev_priv->warp, dev);
 867                 drm_core_ioremap(dev_priv->primary, dev);
 868                 drm_core_ioremap(dev->agp_buffer_map, dev);
 869         }
 870
 871         dev_priv->sarea_priv =
 872             (drm_mga_sarea_t *) ((u8 *) dev_priv->sarea->handle +
 873                                  init->sarea_priv_offset);
 874
 875         if (!dev_priv->warp->handle ||
 876             !dev_priv->primary->handle ||
 877             ((dev_priv->dma_access != 0) &&
 878              ((dev->agp_buffer_map == NULL) ||
 879               (dev->agp_buffer_map->handle == NULL)))) {
 880                 DRM_ERROR("failed to ioremap agp regions!\n");
 881                 return -ENOMEM;
 882         }
 883
 884         ret = mga_warp_install_microcode(dev_priv);
 885         if (ret != 0) {
 886                 DRM_ERROR("failed to install WARP ucode: %d!\n", ret);
 887                 return ret;
 888         }
 889
 890         ret = mga_warp_init(dev_priv);
 891         if (ret != 0) {
 892                 DRM_ERROR("failed to init WARP engine: %d!\n", ret);
 893                 return ret;
 894         }
 895
 896         dev_priv->prim.status = (u32 *) dev_priv->status->handle;
 897
 898         mga_do_wait_for_idle(dev_priv);
 899
 900         /* Init the primary DMA registers.
 901          */
 902         MGA_WRITE(MGA_PRIMADDRESS, dev_priv->primary->offset | MGA_DMA_GENERAL);
 903
 904         dev_priv->prim.start = (u8 *) dev_priv->primary->handle;
 905         dev_priv->prim.end = ((u8 *) dev_priv->primary->handle
 906                               + dev_priv->primary->size);
 907         dev_priv->prim.size = dev_priv->primary->size;
 908
 909         dev_priv->prim.tail = 0;
 910         dev_priv->prim.space = dev_priv->prim.size;
 911         dev_priv->prim.wrapped = 0;
 912
 913         dev_priv->prim.last_flush = 0;
 914         dev_priv->prim.last_wrap = 0;
 915
 916         dev_priv->prim.high_mark = 256 * DMA_BLOCK_SIZE;
 917
 918         dev_priv->prim.status[0] = dev_priv->primary->offset;
 919         dev_priv->prim.status[1] = 0;
 920
 921         dev_priv->sarea_priv->last_wrap = 0;
 922         dev_priv->sarea_priv->last_frame.head = 0;
 923         dev_priv->sarea_priv->last_frame.wrap = 0;
 924
 925         if (mga_freelist_init(dev, dev_priv) < 0) {
 926                 DRM_ERROR("could not initialize freelist\n");
 927                 return -ENOMEM;
 928         }
 929
 930         return 0;
 931 }
 932
 933 static int mga_do_cleanup_dma(struct drm_device *dev, int full_cleanup)
 934 {
 935         int err = 0;
 936         DRM_DEBUG("\n");
 937
 938         /* Make sure interrupts are disabled here because the uninstall ioctl
 939          * may not have been called from userspace and after dev_private
 940          * is freed, it's too late.
 941          */
 942         if (dev->irq_enabled)
 943                 drm_irq_uninstall(dev);
 944
 945         if (dev->dev_private) {
 946                 drm_mga_private_t *dev_priv = dev->dev_private;
 947
 948                 if ((dev_priv->warp != NULL)
 949                     && (dev_priv->warp->type != _DRM_CONSISTENT))
 950                         drm_core_ioremapfree(dev_priv->warp, dev);
 951
 952                 if ((dev_priv->primary != NULL)
 953                     && (dev_priv->primary->type != _DRM_CONSISTENT))
 954                         drm_core_ioremapfree(dev_priv->primary, dev);
 955
 956                 if (dev->agp_buffer_map != NULL)
 957                         drm_core_ioremapfree(dev->agp_buffer_map, dev);
 958
 959                 if (dev_priv->used_new_dma_init) {
 960                         if (dev_priv->agp_handle != 0) {
 961                                 struct drm_agp_binding unbind_req;
 962                                 struct drm_agp_buffer free_req;
 963
 964                                 unbind_req.handle = dev_priv->agp_handle;
 965                                 drm_agp_unbind(dev, &unbind_req);
 966
 967                                 free_req.handle = dev_priv->agp_handle;
 968                                 drm_agp_free(dev, &free_req);
 969
 970                                 dev_priv->agp_textures = NULL;
 971                                 dev_priv->agp_size = 0;
 972                                 dev_priv->agp_handle = 0;
 973                         }
 974
 975                         if ((dev->agp != NULL) && dev->agp->acquired) {
 976                                 err = drm_agp_release(dev);
 977                         }
 978                 }
 979
 980                 dev_priv->warp = NULL;
 981                 dev_priv->primary = NULL;
 982                 dev_priv->sarea = NULL;
 983                 dev_priv->sarea_priv = NULL;
 984                 dev->agp_buffer_map = NULL;
 985
 986                 if (full_cleanup) {
 987                         dev_priv->mmio = NULL;
 988                         dev_priv->status = NULL;
 989                         dev_priv->used_new_dma_init = 0;
 990                 }
 991
 992                 memset(&dev_priv->prim, 0, sizeof(dev_priv->prim));
 993                 dev_priv->warp_pipe = 0;
 994                 memset(dev_priv->warp_pipe_phys, 0,
 995                        sizeof(dev_priv->warp_pipe_phys));
 996
 997                 if (dev_priv->head != NULL) {
 998                         mga_freelist_cleanup(dev);
 999                 }
1000         }
1001
1002         return err;
1003 }
1004
1005 int mga_dma_init(struct drm_device *dev, void *data,
1006                  struct drm_file *file_priv)
1007 {
1008         drm_mga_init_t *init = data;
1009         int err;
1010
1011         LOCK_TEST_WITH_RETURN(dev, file_priv);
1012
1013         switch (init->func) {
1014         case MGA_INIT_DMA:
1015                 err = mga_do_init_dma(dev, init);
1016                 if (err) {
1017                         (void)mga_do_cleanup_dma(dev, FULL_CLEANUP);
1018                 }
1019                 return err;
1020         case MGA_CLEANUP_DMA:
1021                 return mga_do_cleanup_dma(dev, FULL_CLEANUP);
1022         }
1023
1024         return -EINVAL;
1025 }
1026
1027 /* ================================================================
1028  * Primary DMA stream management
1029  */
1030
1031 int mga_dma_flush(struct drm_device *dev, void *data,
1032                   struct drm_file *file_priv)
1033 {
1034         drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
1035         struct drm_lock *lock = data;
1036
1037         LOCK_TEST_WITH_RETURN(dev, file_priv);
1038
1039         DRM_DEBUG("%s%s%s\n",
1040                   (lock->flags & _DRM_LOCK_FLUSH) ? "flush, " : "",
1041                   (lock->flags & _DRM_LOCK_FLUSH_ALL) ? "flush all, " : "",
1042                   (lock->flags & _DRM_LOCK_QUIESCENT) ? "idle, " : "");
1043
1044         WRAP_WAIT_WITH_RETURN(dev_priv);
1045
1046         if (lock->flags & (_DRM_LOCK_FLUSH | _DRM_LOCK_FLUSH_ALL)) {
1047                 mga_do_dma_flush(dev_priv);
1048         }
1049
1050         if (lock->flags & _DRM_LOCK_QUIESCENT) {
1051 #if MGA_DMA_DEBUG
1052                 int ret = mga_do_wait_for_idle(dev_priv);
1053                 if (ret < 0)
1054                         DRM_INFO("-EBUSY\n");
1055                 return ret;
1056 #else
1057                 return mga_do_wait_for_idle(dev_priv);
1058 #endif
1059         } else {
1060                 return 0;
1061         }
1062 }
1063
1064 int mga_dma_reset(struct drm_device *dev, void *data,
1065                   struct drm_file *file_priv)
1066 {
1067         drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
1068
1069         LOCK_TEST_WITH_RETURN(dev, file_priv);
1070
1071         return mga_do_dma_reset(dev_priv);
1072 }
1073
1074 /* ================================================================
1075  * DMA buffer management
1076  */
1077
1078 static int mga_dma_get_buffers(struct drm_device * dev,
1079                                struct drm_file *file_priv, struct drm_dma * d)
1080 {
1081         struct drm_buf *buf;
1082         int i;
1083
1084         for (i = d->granted_count; i < d->request_count; i++) {
1085                 buf = mga_freelist_get(dev);
1086                 if (!buf)
1087                         return -EAGAIN;
1088
1089                 buf->file_priv = file_priv;
1090
1091                 if (DRM_COPY_TO_USER(&d->request_indices[i],
1092                                      &buf->idx, sizeof(buf->idx)))
1093                         return -EFAULT;
1094                 if (DRM_COPY_TO_USER(&d->request_sizes[i],
1095                                      &buf->total, sizeof(buf->total)))
1096                         return -EFAULT;
1097
1098                 d->granted_count++;
1099         }
1100         return 0;
1101 }
1102
1103 int mga_dma_buffers(struct drm_device *dev, void *data,
1104                     struct drm_file *file_priv)
1105 {
1106         struct drm_device_dma *dma = dev->dma;
1107         drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
1108         struct drm_dma *d = data;
1109         int ret = 0;
1110
1111         LOCK_TEST_WITH_RETURN(dev, file_priv);
1112
1113         /* Please don't send us buffers.
1114          */
1115         if (d->send_count != 0) {
1116                 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1117                           DRM_CURRENTPID, d->send_count);
1118                 return -EINVAL;
1119         }
1120
1121         /* We'll send you buffers.
1122          */
1123         if (d->request_count < 0 || d->request_count > dma->buf_count) {
1124                 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1125                           DRM_CURRENTPID, d->request_count, dma->buf_count);
1126                 return -EINVAL;
1127         }
1128
1129         WRAP_TEST_WITH_RETURN(dev_priv);
1130
1131         d->granted_count = 0;
1132
1133         if (d->request_count) {
1134                 ret = mga_dma_get_buffers(dev, file_priv, d);
1135         }
1136
1137         return ret;
1138 }
1139
1140 /**
1141  * Called just before the module is unloaded.
1142  */
1143 int mga_driver_unload(struct drm_device * dev)
1144 {
1145         drm_free(dev->dev_private, sizeof(drm_mga_private_t), DRM_MEM_DRIVER);
1146         dev->dev_private = NULL;
1147
1148         return 0;
1149 }
1150
1151 /**
1152  * Called when the last opener of the device is closed.
1153  */
1154 void mga_driver_lastclose(struct drm_device * dev)
1155 {
1156         mga_do_cleanup_dma(dev, FULL_CLEANUP);
1157 }
1158
1159 int mga_driver_dma_quiescent(struct drm_device * dev)
1160 {
1161         drm_mga_private_t *dev_priv = dev->dev_private;
1162         return mga_do_wait_for_idle(dev_priv);
1163 }