sys/dev/netif/bce/if_bce.c

   1 /*-
   2  * Copyright (c) 2006-2007 Broadcom Corporation
   3  *      David Christensen <davidch@broadcom.com>.  All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  *
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. Neither the name of Broadcom Corporation nor the name of its contributors
  15  *    may be used to endorse or promote products derived from this software
  16  *    without specific prior written consent.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
  19  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
  22  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  28  * THE POSSIBILITY OF SUCH DAMAGE.
  29  *
  30  * $FreeBSD: src/sys/dev/bce/if_bce.c,v 1.31 2007/05/16 23:34:11 davidch Exp $
  31  * $DragonFly: src/sys/dev/netif/bce/if_bce.c,v 1.2 2008/03/10 10:47:57 sephe Exp $
  32  */
  33
  34 /*
  35  * The following controllers are supported by this driver:
  36  *   BCM5706C A2, A3
  37  *   BCM5708C B1, B2
  38  *
  39  * The following controllers are not supported by this driver:
  40  *   BCM5706C A0, A1
  41  *   BCM5706S A0, A1, A2, A3
  42  *   BCM5708C A0, B0
  43  *   BCM5708S A0, B0, B1, B2
  44  */
  45
  46 #include "opt_bce.h"
  47 #include "opt_polling.h"
  48
  49 #include <sys/param.h>
  50 #include <sys/bus.h>
  51 #include <sys/endian.h>
  52 #include <sys/kernel.h>
  53 #include <sys/mbuf.h>
  54 #include <sys/malloc.h>
  55 #include <sys/queue.h>
  56 #ifdef BCE_DEBUG
  57 #include <sys/random.h>
  58 #endif
  59 #include <sys/rman.h>
  60 #include <sys/serialize.h>
  61 #include <sys/socket.h>
  62 #include <sys/sockio.h>
  63 #include <sys/sysctl.h>
  64
  65 #include <net/bpf.h>
  66 #include <net/ethernet.h>
  67 #include <net/if.h>
  68 #include <net/if_arp.h>
  69 #include <net/if_dl.h>
  70 #include <net/if_media.h>
  71 #include <net/if_types.h>
  72 #include <net/ifq_var.h>
  73 #include <net/vlan/if_vlan_var.h>
  74
  75 #include <dev/netif/mii_layer/mii.h>
  76 #include <dev/netif/mii_layer/miivar.h>
  77
  78 #include <bus/pci/pcireg.h>
  79 #include <bus/pci/pcivar.h>
  80
  81 #include "miibus_if.h"
  82
  83 #include "if_bcereg.h"
  84 #include "if_bcefw.h"
  85
  86 /****************************************************************************/
  87 /* BCE Debug Options                                                        */
  88 /****************************************************************************/
  89 #ifdef BCE_DEBUG
  90
  91 static uint32_t bce_debug = BCE_WARN;
  92
  93 /*
  94  *          0 = Never
  95  *          1 = 1 in 2,147,483,648
  96  *        256 = 1 in     8,388,608
  97  *       2048 = 1 in     1,048,576
  98  *      65536 = 1 in        32,768
  99  *    1048576 = 1 in         2,048
 100  *  268435456 = 1 in             8
 101  *  536870912 = 1 in             4
 102  * 1073741824 = 1 in             2
 103  *
 104  * bce_debug_l2fhdr_status_check:
 105  *     How often the l2_fhdr frame error check will fail.
 106  *
 107  * bce_debug_unexpected_attention:
 108  *     How often the unexpected attention check will fail.
 109  *
 110  * bce_debug_mbuf_allocation_failure:
 111  *     How often to simulate an mbuf allocation failure.
 112  *
 113  * bce_debug_dma_map_addr_failure:
 114  *     How often to simulate a DMA mapping failure.
 115  *
 116  * bce_debug_bootcode_running_failure:
 117  *     How often to simulate a bootcode failure.
 118  */
 119 static int      bce_debug_l2fhdr_status_check = 0;
 120 static int      bce_debug_unexpected_attention = 0;
 121 static int      bce_debug_mbuf_allocation_failure = 0;
 122 static int      bce_debug_dma_map_addr_failure = 0;
 123 static int      bce_debug_bootcode_running_failure = 0;
 124
 125 #endif  /* BCE_DEBUG */
 126
 127
 128 /****************************************************************************/
 129 /* PCI Device ID Table                                                      */
 130 /*                                                                          */
 131 /* Used by bce_probe() to identify the devices supported by this driver.    */
 132 /****************************************************************************/
 133 #define BCE_DEVDESC_MAX         64
 134
 135 static struct bce_type bce_devs[] = {
 136         /* BCM5706C Controllers and OEM boards. */
 137         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3101,
 138                 "HP NC370T Multifunction Gigabit Server Adapter" },
 139         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3106,
 140                 "HP NC370i Multifunction Gigabit Server Adapter" },
 141         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  PCI_ANY_ID,  PCI_ANY_ID,
 142                 "Broadcom NetXtreme II BCM5706 1000Base-T" },
 143
 144         /* BCM5706S controllers and OEM boards. */
 145         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102,
 146                 "HP NC370F Multifunction Gigabit Server Adapter" },
 147         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID,  PCI_ANY_ID,
 148                 "Broadcom NetXtreme II BCM5706 1000Base-SX" },
 149
 150         /* BCM5708C controllers and OEM boards. */
 151         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  PCI_ANY_ID,  PCI_ANY_ID,
 152                 "Broadcom NetXtreme II BCM5708 1000Base-T" },
 153
 154         /* BCM5708S controllers and OEM boards. */
 155         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  PCI_ANY_ID,  PCI_ANY_ID,
 156                 "Broadcom NetXtreme II BCM5708S 1000Base-T" },
 157         { 0, 0, 0, 0, NULL }
 158 };
 159
 160
 161 /****************************************************************************/
 162 /* Supported Flash NVRAM device data.                                       */
 163 /****************************************************************************/
 164 static const struct flash_spec flash_table[] =
 165 {
 166         /* Slow EEPROM */
 167         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
 168          1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 169          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 170          "EEPROM - slow"},
 171         /* Expansion entry 0001 */
 172         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
 173          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 174          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 175          "Entry 0001"},
 176         /* Saifun SA25F010 (non-buffered flash) */
 177         /* strap, cfg1, & write1 need updates */
 178         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
 179          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 180          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
 181          "Non-buffered flash (128kB)"},
 182         /* Saifun SA25F020 (non-buffered flash) */
 183         /* strap, cfg1, & write1 need updates */
 184         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
 185          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 186          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
 187          "Non-buffered flash (256kB)"},
 188         /* Expansion entry 0100 */
 189         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
 190          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 191          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 192          "Entry 0100"},
 193         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
 194         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
 195          0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 196          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
 197          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
 198         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
 199         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
 200          0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 201          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
 202          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
 203         /* Saifun SA25F005 (non-buffered flash) */
 204         /* strap, cfg1, & write1 need updates */
 205         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
 206          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 207          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
 208          "Non-buffered flash (64kB)"},
 209         /* Fast EEPROM */
 210         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
 211          1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 212          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 213          "EEPROM - fast"},
 214         /* Expansion entry 1001 */
 215         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
 216          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 217          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 218          "Entry 1001"},
 219         /* Expansion entry 1010 */
 220         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
 221          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 222          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 223          "Entry 1010"},
 224         /* ATMEL AT45DB011B (buffered flash) */
 225         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
 226          1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 227          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
 228          "Buffered flash (128kB)"},
 229         /* Expansion entry 1100 */
 230         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
 231          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 232          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 233          "Entry 1100"},
 234         /* Expansion entry 1101 */
 235         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
 236          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 237          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 238          "Entry 1101"},
 239         /* Ateml Expansion entry 1110 */
 240         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
 241          1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 242          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
 243          "Entry 1110 (Atmel)"},
 244         /* ATMEL AT45DB021B (buffered flash) */
 245         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
 246          1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 247          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
 248          "Buffered flash (256kB)"},
 249 };
 250
 251
 252 /****************************************************************************/
 253 /* DragonFly device entry points.                                           */
 254 /****************************************************************************/
 255 static int      bce_probe(device_t);
 256 static int      bce_attach(device_t);
 257 static int      bce_detach(device_t);
 258 static void     bce_shutdown(device_t);
 259
 260 /****************************************************************************/
 261 /* BCE Debug Data Structure Dump Routines                                   */
 262 /****************************************************************************/
 263 #ifdef BCE_DEBUG
 264 static void     bce_dump_mbuf(struct bce_softc *, struct mbuf *);
 265 static void     bce_dump_tx_mbuf_chain(struct bce_softc *, int, int);
 266 static void     bce_dump_rx_mbuf_chain(struct bce_softc *, int, int);
 267 static void     bce_dump_txbd(struct bce_softc *, int, struct tx_bd *);
 268 static void     bce_dump_rxbd(struct bce_softc *, int, struct rx_bd *);
 269 static void     bce_dump_l2fhdr(struct bce_softc *, int,
 270                                 struct l2_fhdr *) __unused;
 271 static void     bce_dump_tx_chain(struct bce_softc *, int, int);
 272 static void     bce_dump_rx_chain(struct bce_softc *, int, int);
 273 static void     bce_dump_status_block(struct bce_softc *);
 274 static void     bce_dump_driver_state(struct bce_softc *);
 275 static void     bce_dump_stats_block(struct bce_softc *) __unused;
 276 static void     bce_dump_hw_state(struct bce_softc *);
 277 static void     bce_dump_txp_state(struct bce_softc *);
 278 static void     bce_dump_rxp_state(struct bce_softc *) __unused;
 279 static void     bce_dump_tpat_state(struct bce_softc *) __unused;
 280 static void     bce_freeze_controller(struct bce_softc *) __unused;
 281 static void     bce_unfreeze_controller(struct bce_softc *) __unused;
 282 static void     bce_breakpoint(struct bce_softc *);
 283 #endif  /* BCE_DEBUG */
 284
 285
 286 /****************************************************************************/
 287 /* BCE Register/Memory Access Routines                                      */
 288 /****************************************************************************/
 289 static uint32_t bce_reg_rd_ind(struct bce_softc *, uint32_t);
 290 static void     bce_reg_wr_ind(struct bce_softc *, uint32_t, uint32_t);
 291 static void     bce_ctx_wr(struct bce_softc *, uint32_t, uint32_t, uint32_t);
 292 static int      bce_miibus_read_reg(device_t, int, int);
 293 static int      bce_miibus_write_reg(device_t, int, int, int);
 294 static void     bce_miibus_statchg(device_t);
 295
 296
 297 /****************************************************************************/
 298 /* BCE NVRAM Access Routines                                                */
 299 /****************************************************************************/
 300 static int      bce_acquire_nvram_lock(struct bce_softc *);
 301 static int      bce_release_nvram_lock(struct bce_softc *);
 302 static void     bce_enable_nvram_access(struct bce_softc *);
 303 static void     bce_disable_nvram_access(struct bce_softc *);
 304 static int      bce_nvram_read_dword(struct bce_softc *, uint32_t, uint8_t *,
 305                                      uint32_t);
 306 static int      bce_init_nvram(struct bce_softc *);
 307 static int      bce_nvram_read(struct bce_softc *, uint32_t, uint8_t *, int);
 308 static int      bce_nvram_test(struct bce_softc *);
 309 #ifdef BCE_NVRAM_WRITE_SUPPORT
 310 static int      bce_enable_nvram_write(struct bce_softc *);
 311 static void     bce_disable_nvram_write(struct bce_softc *);
 312 static int      bce_nvram_erase_page(struct bce_softc *, uint32_t);
 313 static int      bce_nvram_write_dword(struct bce_softc *, uint32_t, uint8_t *,                                        uint32_t);
 314 static int      bce_nvram_write(struct bce_softc *, uint32_t, uint8_t *,
 315                                 int) __unused;
 316 #endif
 317
 318 /****************************************************************************/
 319 /* BCE DMA Allocate/Free Routines                                           */
 320 /****************************************************************************/
 321 static int      bce_dma_alloc(struct bce_softc *);
 322 static void     bce_dma_free(struct bce_softc *);
 323 static void     bce_dma_map_addr(void *, bus_dma_segment_t *, int, int);
 324 static void     bce_dma_map_mbuf(void *, bus_dma_segment_t *, int,
 325                                  bus_size_t, int);
 326
 327 /****************************************************************************/
 328 /* BCE Firmware Synchronization and Load                                    */
 329 /****************************************************************************/
 330 static int      bce_fw_sync(struct bce_softc *, uint32_t);
 331 static void     bce_load_rv2p_fw(struct bce_softc *, uint32_t *,
 332                                  uint32_t, uint32_t);
 333 static void     bce_load_cpu_fw(struct bce_softc *, struct cpu_reg *,
 334                                 struct fw_info *);
 335 static void     bce_init_cpus(struct bce_softc *);
 336
 337 static void     bce_stop(struct bce_softc *);
 338 static int      bce_reset(struct bce_softc *, uint32_t);
 339 static int      bce_chipinit(struct bce_softc *);
 340 static int      bce_blockinit(struct bce_softc *);
 341 static int      bce_newbuf_std(struct bce_softc *, struct mbuf *,
 342                                uint16_t *, uint16_t *, uint32_t *);
 343
 344 static int      bce_init_tx_chain(struct bce_softc *);
 345 static int      bce_init_rx_chain(struct bce_softc *);
 346 static void     bce_free_rx_chain(struct bce_softc *);
 347 static void     bce_free_tx_chain(struct bce_softc *);
 348
 349 static int      bce_encap(struct bce_softc *, struct mbuf **);
 350 static void     bce_start(struct ifnet *);
 351 static int      bce_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 352 static void     bce_watchdog(struct ifnet *);
 353 static int      bce_ifmedia_upd(struct ifnet *);
 354 static void     bce_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 355 static void     bce_init(void *);
 356 static void     bce_mgmt_init(struct bce_softc *);
 357
 358 static void     bce_init_context(struct bce_softc *);
 359 static void     bce_get_mac_addr(struct bce_softc *);
 360 static void     bce_set_mac_addr(struct bce_softc *);
 361 static void     bce_phy_intr(struct bce_softc *);
 362 static void     bce_rx_intr(struct bce_softc *, int);
 363 static void     bce_tx_intr(struct bce_softc *);
 364 static void     bce_disable_intr(struct bce_softc *);
 365 static void     bce_enable_intr(struct bce_softc *);
 366
 367 #ifdef DEVICE_POLLING
 368 static void     bce_poll(struct ifnet *, enum poll_cmd, int);
 369 #endif
 370 static void     bce_intr(void *);
 371 static void     bce_set_rx_mode(struct bce_softc *);
 372 static void     bce_stats_update(struct bce_softc *);
 373 static void     bce_tick(void *);
 374 static void     bce_tick_serialized(struct bce_softc *);
 375 static void     bce_add_sysctls(struct bce_softc *);
 376
 377
 378 /****************************************************************************/
 379 /* DragonFly device dispatch table.                                         */
 380 /****************************************************************************/
 381 static device_method_t bce_methods[] = {
 382         /* Device interface */
 383         DEVMETHOD(device_probe,         bce_probe),
 384         DEVMETHOD(device_attach,        bce_attach),
 385         DEVMETHOD(device_detach,        bce_detach),
 386         DEVMETHOD(device_shutdown,      bce_shutdown),
 387
 388         /* bus interface */
 389         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 390         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 391
 392         /* MII interface */
 393         DEVMETHOD(miibus_readreg,       bce_miibus_read_reg),
 394         DEVMETHOD(miibus_writereg,      bce_miibus_write_reg),
 395         DEVMETHOD(miibus_statchg,       bce_miibus_statchg),
 396
 397         { 0, 0 }
 398 };
 399
 400 static driver_t bce_driver = {
 401         "bce",
 402         bce_methods,
 403         sizeof(struct bce_softc)
 404 };
 405
 406 static devclass_t bce_devclass;
 407
 408 MODULE_DEPEND(bce, pci, 1, 1, 1);
 409 MODULE_DEPEND(bce, ether, 1, 1, 1);
 410 MODULE_DEPEND(bce, miibus, 1, 1, 1);
 411
 412 DRIVER_MODULE(bce, pci, bce_driver, bce_devclass, 0, 0);
 413 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, 0, 0);
 414
 415
 416 /****************************************************************************/
 417 /* Device probe function.                                                   */
 418 /*                                                                          */
 419 /* Compares the device to the driver's list of supported devices and        */
 420 /* reports back to the OS whether this is the right driver for the device.  */
 421 /*                                                                          */
 422 /* Returns:                                                                 */
 423 /*   BUS_PROBE_DEFAULT on success, positive value on failure.               */
 424 /****************************************************************************/
 425 static int
 426 bce_probe(device_t dev)
 427 {
 428         struct bce_type *t;
 429         uint16_t vid, did, svid, sdid;
 430
 431         /* Get the data for the device to be probed. */
 432         vid  = pci_get_vendor(dev);
 433         did  = pci_get_device(dev);
 434         svid = pci_get_subvendor(dev);
 435         sdid = pci_get_subdevice(dev);
 436
 437         /* Look through the list of known devices for a match. */
 438         for (t = bce_devs; t->bce_name != NULL; ++t) {
 439                 if (vid == t->bce_vid && did == t->bce_did &&
 440                     (svid == t->bce_svid || t->bce_svid == PCI_ANY_ID) &&
 441                     (sdid == t->bce_sdid || t->bce_sdid == PCI_ANY_ID)) {
 442                         uint32_t revid = pci_read_config(dev, PCIR_REVID, 4);
 443                         char *descbuf;
 444
 445                         descbuf = kmalloc(BCE_DEVDESC_MAX, M_TEMP, M_WAITOK);
 446
 447                         /* Print out the device identity. */
 448                         ksnprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)",
 449                                   t->bce_name,
 450                                   ((revid & 0xf0) >> 4) + 'A', revid & 0xf);
 451
 452                         device_set_desc_copy(dev, descbuf);
 453                         kfree(descbuf, M_TEMP);
 454                         return 0;
 455                 }
 456         }
 457         return ENXIO;
 458 }
 459
 460
 461 /****************************************************************************/
 462 /* Device attach function.                                                  */
 463 /*                                                                          */
 464 /* Allocates device resources, performs secondary chip identification,      */
 465 /* resets and initializes the hardware, and initializes driver instance     */
 466 /* variables.                                                               */
 467 /*                                                                          */
 468 /* Returns:                                                                 */
 469 /*   0 on success, positive value on failure.                               */
 470 /****************************************************************************/
 471 static int
 472 bce_attach(device_t dev)
 473 {
 474         struct bce_softc *sc = device_get_softc(dev);
 475         struct ifnet *ifp = &sc->arpcom.ac_if;
 476         uint32_t val;
 477         int rid, rc = 0;
 478 #ifdef notyet
 479         int count;
 480 #endif
 481
 482         sc->bce_dev = dev;
 483         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 484
 485         pci_enable_busmaster(dev);
 486
 487         /* Allocate PCI memory resources. */
 488         rid = PCIR_BAR(0);
 489         sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
 490                                                  RF_ACTIVE | PCI_RF_DENSE);
 491         if (sc->bce_res_mem == NULL) {
 492                 device_printf(dev, "PCI memory allocation failed\n");
 493                 return ENXIO;
 494         }
 495         sc->bce_btag = rman_get_bustag(sc->bce_res_mem);
 496         sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem);
 497
 498         /* Allocate PCI IRQ resources. */
 499 #ifdef notyet
 500         count = pci_msi_count(dev);
 501         if (count == 1 && pci_alloc_msi(dev, &count) == 0) {
 502                 rid = 1;
 503                 sc->bce_flags |= BCE_USING_MSI_FLAG;
 504         } else
 505 #endif
 506         rid = 0;
 507         sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
 508                                                  RF_SHAREABLE | RF_ACTIVE);
 509         if (sc->bce_res_irq == NULL) {
 510                 device_printf(dev, "PCI map interrupt failed\n");
 511                 rc = ENXIO;
 512                 goto fail;
 513         }
 514
 515         /*
 516          * Configure byte swap and enable indirect register access.
 517          * Rely on CPU to do target byte swapping on big endian systems.
 518          * Access to registers outside of PCI configurtion space are not
 519          * valid until this is done.
 520          */
 521         pci_write_config(dev, BCE_PCICFG_MISC_CONFIG,
 522                          BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
 523                          BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4);
 524
 525         /* Save ASIC revsion info. */
 526         sc->bce_chipid =  REG_RD(sc, BCE_MISC_ID);
 527
 528         /* Weed out any non-production controller revisions. */
 529         switch(BCE_CHIP_ID(sc)) {
 530         case BCE_CHIP_ID_5706_A0:
 531         case BCE_CHIP_ID_5706_A1:
 532         case BCE_CHIP_ID_5708_A0:
 533         case BCE_CHIP_ID_5708_B0:
 534                 device_printf(dev, "Unsupported chip id 0x%08x!\n",
 535                               BCE_CHIP_ID(sc));
 536                 rc = ENODEV;
 537                 goto fail;
 538         }
 539
 540         /*
 541          * The embedded PCIe to PCI-X bridge (EPB)
 542          * in the 5708 cannot address memory above
 543          * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043).
 544          */
 545         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)
 546                 sc->max_bus_addr = BCE_BUS_SPACE_MAXADDR;
 547         else
 548                 sc->max_bus_addr = BUS_SPACE_MAXADDR;
 549
 550         /*
 551          * Find the base address for shared memory access.
 552          * Newer versions of bootcode use a signature and offset
 553          * while older versions use a fixed address.
 554          */
 555         val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE);
 556         if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) == BCE_SHM_HDR_SIGNATURE_SIG)
 557                 sc->bce_shmem_base = REG_RD_IND(sc, BCE_SHM_HDR_ADDR_0);
 558         else
 559                 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
 560
 561         DBPRINT(sc, BCE_INFO, "bce_shmem_base = 0x%08X\n", sc->bce_shmem_base);
 562
 563         /* Get PCI bus information (speed and type). */
 564         val = REG_RD(sc, BCE_PCICFG_MISC_STATUS);
 565         if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) {
 566                 uint32_t clkreg;
 567
 568                 sc->bce_flags |= BCE_PCIX_FLAG;
 569
 570                 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS) &
 571                          BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
 572                 switch (clkreg) {
 573                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
 574                         sc->bus_speed_mhz = 133;
 575                         break;
 576
 577                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
 578                         sc->bus_speed_mhz = 100;
 579                         break;
 580
 581                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
 582                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
 583                         sc->bus_speed_mhz = 66;
 584                         break;
 585
 586                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
 587                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
 588                         sc->bus_speed_mhz = 50;
 589                         break;
 590
 591                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
 592                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
 593                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
 594                         sc->bus_speed_mhz = 33;
 595                         break;
 596                 }
 597         } else {
 598                 if (val & BCE_PCICFG_MISC_STATUS_M66EN)
 599                         sc->bus_speed_mhz = 66;
 600                 else
 601                         sc->bus_speed_mhz = 33;
 602         }
 603
 604         if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET)
 605                 sc->bce_flags |= BCE_PCI_32BIT_FLAG;
 606
 607         device_printf(dev, "ASIC ID 0x%08X; Revision (%c%d); PCI%s %s %dMHz\n",
 608                       sc->bce_chipid,
 609                       ((BCE_CHIP_ID(sc) & 0xf000) >> 12) + 'A',
 610                       (BCE_CHIP_ID(sc) & 0x0ff0) >> 4,
 611                       (sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : "",
 612                       (sc->bce_flags & BCE_PCI_32BIT_FLAG) ?
 613                       "32-bit" : "64-bit", sc->bus_speed_mhz);
 614
 615         /* Reset the controller. */
 616         rc = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
 617         if (rc != 0)
 618                 goto fail;
 619
 620         /* Initialize the controller. */
 621         rc = bce_chipinit(sc);
 622         if (rc != 0) {
 623                 device_printf(dev, "Controller initialization failed!\n");
 624                 goto fail;
 625         }
 626
 627         /* Perform NVRAM test. */
 628         rc = bce_nvram_test(sc);
 629         if (rc != 0) {
 630                 device_printf(dev, "NVRAM test failed!\n");
 631                 goto fail;
 632         }
 633
 634         /* Fetch the permanent Ethernet MAC address. */
 635         bce_get_mac_addr(sc);
 636
 637         /*
 638          * Trip points control how many BDs
 639          * should be ready before generating an
 640          * interrupt while ticks control how long
 641          * a BD can sit in the chain before
 642          * generating an interrupt.  Set the default
 643          * values for the RX and TX rings.
 644          */
 645
 646 #ifdef BCE_DRBUG
 647         /* Force more frequent interrupts. */
 648         sc->bce_tx_quick_cons_trip_int = 1;
 649         sc->bce_tx_quick_cons_trip     = 1;
 650         sc->bce_tx_ticks_int           = 0;
 651         sc->bce_tx_ticks               = 0;
 652
 653         sc->bce_rx_quick_cons_trip_int = 1;
 654         sc->bce_rx_quick_cons_trip     = 1;
 655         sc->bce_rx_ticks_int           = 0;
 656         sc->bce_rx_ticks               = 0;
 657 #else
 658         sc->bce_tx_quick_cons_trip_int = 20;
 659         sc->bce_tx_quick_cons_trip     = 20;
 660         sc->bce_tx_ticks_int           = 80;
 661         sc->bce_tx_ticks               = 80;
 662
 663         sc->bce_rx_quick_cons_trip_int = 6;
 664         sc->bce_rx_quick_cons_trip     = 6;
 665         sc->bce_rx_ticks_int           = 18;
 666         sc->bce_rx_ticks               = 18;
 667 #endif
 668
 669         /* Update statistics once every second. */
 670         sc->bce_stats_ticks = 1000000 & 0xffff00;
 671
 672         /*
 673          * The copper based NetXtreme II controllers
 674          * use an integrated PHY at address 1 while
 675          * the SerDes controllers use a PHY at
 676          * address 2.
 677          */
 678         sc->bce_phy_addr = 1;
 679
 680         if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) {
 681                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
 682                 sc->bce_flags |= BCE_NO_WOL_FLAG;
 683                 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708) {
 684                         sc->bce_phy_addr = 2;
 685                         val = REG_RD_IND(sc, sc->bce_shmem_base +
 686                                          BCE_SHARED_HW_CFG_CONFIG);
 687                         if (val & BCE_SHARED_HW_CFG_PHY_2_5G)
 688                                 sc->bce_phy_flags |= BCE_PHY_2_5G_CAPABLE_FLAG;
 689                 }
 690         }
 691
 692         /* Allocate DMA memory resources. */
 693         rc = bce_dma_alloc(sc);
 694         if (rc != 0) {
 695                 device_printf(dev, "DMA resource allocation failed!\n");
 696                 goto fail;
 697         }
 698
 699         /* Initialize the ifnet interface. */
 700         ifp->if_softc = sc;
 701         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 702         ifp->if_ioctl = bce_ioctl;
 703         ifp->if_start = bce_start;
 704         ifp->if_init = bce_init;
 705         ifp->if_watchdog = bce_watchdog;
 706 #ifdef DEVICE_POLLING
 707         ifp->if_poll = bce_poll;
 708 #endif
 709         ifp->if_mtu = ETHERMTU;
 710         ifp->if_hwassist = BCE_IF_HWASSIST;
 711         ifp->if_capabilities = BCE_IF_CAPABILITIES;
 712         ifp->if_capenable = ifp->if_capabilities;
 713         ifq_set_maxlen(&ifp->if_snd, USABLE_TX_BD);
 714         ifq_set_ready(&ifp->if_snd);
 715
 716         if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
 717                 ifp->if_baudrate = IF_Gbps(2.5);
 718         else
 719                 ifp->if_baudrate = IF_Gbps(1);
 720
 721         /* Assume a standard 1500 byte MTU size for mbuf allocations. */
 722         sc->mbuf_alloc_size  = MCLBYTES;
 723
 724         /* Look for our PHY. */
 725         rc = mii_phy_probe(dev, &sc->bce_miibus,
 726                            bce_ifmedia_upd, bce_ifmedia_sts);
 727         if (rc != 0) {
 728                 device_printf(dev, "PHY probe failed!\n");
 729                 goto fail;
 730         }
 731
 732         /* Attach to the Ethernet interface list. */
 733         ether_ifattach(ifp, sc->eaddr, NULL);
 734
 735         callout_init(&sc->bce_stat_ch);
 736
 737         /* Hookup IRQ last. */
 738         rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_NETSAFE, bce_intr, sc,
 739                             &sc->bce_intrhand, ifp->if_serializer);
 740         if (rc != 0) {
 741                 device_printf(dev, "Failed to setup IRQ!\n");
 742                 ether_ifdetach(ifp);
 743                 goto fail;
 744         }
 745
 746         /* Print some important debugging info. */
 747         DBRUN(BCE_INFO, bce_dump_driver_state(sc));
 748
 749         /* Add the supported sysctls to the kernel. */
 750         bce_add_sysctls(sc);
 751
 752         /* Get the firmware running so IPMI still works */
 753         bce_mgmt_init(sc);
 754
 755         return 0;
 756 fail:
 757         bce_detach(dev);
 758         return(rc);
 759 }
 760
 761
 762 /****************************************************************************/
 763 /* Device detach function.                                                  */
 764 /*                                                                          */
 765 /* Stops the controller, resets the controller, and releases resources.     */
 766 /*                                                                          */
 767 /* Returns:                                                                 */
 768 /*   0 on success, positive value on failure.                               */
 769 /****************************************************************************/
 770 static int
 771 bce_detach(device_t dev)
 772 {
 773         struct bce_softc *sc = device_get_softc(dev);
 774
 775         if (device_is_attached(dev)) {
 776                 struct ifnet *ifp = &sc->arpcom.ac_if;
 777
 778                 /* Stop and reset the controller. */
 779                 lwkt_serialize_enter(ifp->if_serializer);
 780                 bce_stop(sc);
 781                 bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
 782                 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand);
 783                 lwkt_serialize_exit(ifp->if_serializer);
 784
 785                 ether_ifdetach(ifp);
 786         }
 787
 788         /* If we have a child device on the MII bus remove it too. */
 789         if (sc->bce_miibus)
 790                 device_delete_child(dev, sc->bce_miibus);
 791         bus_generic_detach(dev);
 792
 793         if (sc->bce_res_irq != NULL) {
 794                 bus_release_resource(dev, SYS_RES_IRQ,
 795                         sc->bce_flags & BCE_USING_MSI_FLAG ? 1 : 0,
 796                         sc->bce_res_irq);
 797         }
 798
 799 #ifdef notyet
 800         if (sc->bce_flags & BCE_USING_MSI_FLAG)
 801                 pci_release_msi(dev);
 802 #endif
 803
 804         if (sc->bce_res_mem != NULL) {
 805                 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
 806                                      sc->bce_res_mem);
 807         }
 808
 809         bce_dma_free(sc);
 810
 811         if (sc->bce_sysctl_tree != NULL)
 812                 sysctl_ctx_free(&sc->bce_sysctl_ctx);
 813
 814         return 0;
 815 }
 816
 817
 818 /****************************************************************************/
 819 /* Device shutdown function.                                                */
 820 /*                                                                          */
 821 /* Stops and resets the controller.                                         */
 822 /*                                                                          */
 823 /* Returns:                                                                 */
 824 /*   Nothing                                                                */
 825 /****************************************************************************/
 826 static void
 827 bce_shutdown(device_t dev)
 828 {
 829         struct bce_softc *sc = device_get_softc(dev);
 830         struct ifnet *ifp = &sc->arpcom.ac_if;
 831
 832         lwkt_serialize_enter(ifp->if_serializer);
 833         bce_stop(sc);
 834         bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
 835         lwkt_serialize_exit(ifp->if_serializer);
 836 }
 837
 838
 839 /****************************************************************************/
 840 /* Indirect register read.                                                  */
 841 /*                                                                          */
 842 /* Reads NetXtreme II registers using an index/data register pair in PCI    */
 843 /* configuration space.  Using this mechanism avoids issues with posted     */
 844 /* reads but is much slower than memory-mapped I/O.                         */
 845 /*                                                                          */
 846 /* Returns:                                                                 */
 847 /*   The value of the register.                                             */
 848 /****************************************************************************/
 849 static uint32_t
 850 bce_reg_rd_ind(struct bce_softc *sc, uint32_t offset)
 851 {
 852         device_t dev = sc->bce_dev;
 853
 854         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
 855 #ifdef BCE_DEBUG
 856         {
 857                 uint32_t val;
 858                 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
 859                 DBPRINT(sc, BCE_EXCESSIVE,
 860                         "%s(); offset = 0x%08X, val = 0x%08X\n",
 861                         __func__, offset, val);
 862                 return val;
 863         }
 864 #else
 865         return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
 866 #endif
 867 }
 868
 869
 870 /****************************************************************************/
 871 /* Indirect register write.                                                 */
 872 /*                                                                          */
 873 /* Writes NetXtreme II registers using an index/data register pair in PCI   */
 874 /* configuration space.  Using this mechanism avoids issues with posted     */
 875 /* writes but is muchh slower than memory-mapped I/O.                       */
 876 /*                                                                          */
 877 /* Returns:                                                                 */
 878 /*   Nothing.                                                               */
 879 /****************************************************************************/
 880 static void
 881 bce_reg_wr_ind(struct bce_softc *sc, uint32_t offset, uint32_t val)
 882 {
 883         device_t dev = sc->bce_dev;
 884
 885         DBPRINT(sc, BCE_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n",
 886                 __func__, offset, val);
 887
 888         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
 889         pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4);
 890 }
 891
 892
 893 /****************************************************************************/
 894 /* Context memory write.                                                    */
 895 /*                                                                          */
 896 /* The NetXtreme II controller uses context memory to track connection      */
 897 /* information for L2 and higher network protocols.                         */
 898 /*                                                                          */
 899 /* Returns:                                                                 */
 900 /*   Nothing.                                                               */
 901 /****************************************************************************/
 902 static void
 903 bce_ctx_wr(struct bce_softc *sc, uint32_t cid_addr, uint32_t offset,
 904            uint32_t val)
 905 {
 906         DBPRINT(sc, BCE_EXCESSIVE, "%s(); cid_addr = 0x%08X, offset = 0x%08X, "
 907                 "val = 0x%08X\n", __func__, cid_addr, offset, val);
 908
 909         offset += cid_addr;
 910         REG_WR(sc, BCE_CTX_DATA_ADR, offset);
 911         REG_WR(sc, BCE_CTX_DATA, val);
 912 }
 913
 914
 915 /****************************************************************************/
 916 /* PHY register read.                                                       */
 917 /*                                                                          */
 918 /* Implements register reads on the MII bus.                                */
 919 /*                                                                          */
 920 /* Returns:                                                                 */
 921 /*   The value of the register.                                             */
 922 /****************************************************************************/
 923 static int
 924 bce_miibus_read_reg(device_t dev, int phy, int reg)
 925 {
 926         struct bce_softc *sc = device_get_softc(dev);
 927         uint32_t val;
 928         int i;
 929
 930         /* Make sure we are accessing the correct PHY address. */
 931         if (phy != sc->bce_phy_addr) {
 932                 DBPRINT(sc, BCE_VERBOSE,
 933                         "Invalid PHY address %d for PHY read!\n", phy);
 934                 return 0;
 935         }
 936
 937         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
 938                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
 939                 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
 940
 941                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
 942                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
 943
 944                 DELAY(40);
 945         }
 946
 947         val = BCE_MIPHY(phy) | BCE_MIREG(reg) |
 948               BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT |
 949               BCE_EMAC_MDIO_COMM_START_BUSY;
 950         REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
 951
 952         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
 953                 DELAY(10);
 954
 955                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
 956                 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) {
 957                         DELAY(5);
 958
 959                         val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
 960                         val &= BCE_EMAC_MDIO_COMM_DATA;
 961                         break;
 962                 }
 963         }
 964
 965         if (val & BCE_EMAC_MDIO_COMM_START_BUSY) {
 966                 if_printf(&sc->arpcom.ac_if,
 967                           "Error: PHY read timeout! phy = %d, reg = 0x%04X\n",
 968                           phy, reg);
 969                 val = 0x0;
 970         } else {
 971                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
 972         }
 973
 974         DBPRINT(sc, BCE_EXCESSIVE,
 975                 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
 976                 __func__, phy, (uint16_t)reg & 0xffff, (uint16_t) val & 0xffff);
 977
 978         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
 979                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
 980                 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
 981
 982                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
 983                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
 984
 985                 DELAY(40);
 986         }
 987         return (val & 0xffff);
 988 }
 989
 990
 991 /****************************************************************************/
 992 /* PHY register write.                                                      */
 993 /*                                                                          */
 994 /* Implements register writes on the MII bus.                               */
 995 /*                                                                          */
 996 /* Returns:                                                                 */
 997 /*   The value of the register.                                             */
 998 /****************************************************************************/
 999 static int
1000 bce_miibus_write_reg(device_t dev, int phy, int reg, int val)
1001 {
1002         struct bce_softc *sc = device_get_softc(dev);
1003         uint32_t val1;
1004         int i;
1005
1006         /* Make sure we are accessing the correct PHY address. */
1007         if (phy != sc->bce_phy_addr) {
1008                 DBPRINT(sc, BCE_WARN,
1009                         "Invalid PHY address %d for PHY write!\n", phy);
1010                 return(0);
1011         }
1012
1013         DBPRINT(sc, BCE_EXCESSIVE,
1014                 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1015                 __func__, phy, (uint16_t)(reg & 0xffff),
1016                 (uint16_t)(val & 0xffff));
1017
1018         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1019                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1020                 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1021
1022                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1023                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1024
1025                 DELAY(40);
1026         }
1027
1028         val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val |
1029                 BCE_EMAC_MDIO_COMM_COMMAND_WRITE |
1030                 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT;
1031         REG_WR(sc, BCE_EMAC_MDIO_COMM, val1);
1032
1033         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1034                 DELAY(10);
1035
1036                 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1037                 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1038                         DELAY(5);
1039                         break;
1040                 }
1041         }
1042
1043         if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY)
1044                 if_printf(&sc->arpcom.ac_if, "PHY write timeout!\n");
1045
1046         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1047                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1048                 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1049
1050                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1051                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1052
1053                 DELAY(40);
1054         }
1055         return 0;
1056 }
1057
1058
1059 /****************************************************************************/
1060 /* MII bus status change.                                                   */
1061 /*                                                                          */
1062 /* Called by the MII bus driver when the PHY establishes link to set the    */
1063 /* MAC interface registers.                                                 */
1064 /*                                                                          */
1065 /* Returns:                                                                 */
1066 /*   Nothing.                                                               */
1067 /****************************************************************************/
1068 static void
1069 bce_miibus_statchg(device_t dev)
1070 {
1071         struct bce_softc *sc = device_get_softc(dev);
1072         struct mii_data *mii = device_get_softc(sc->bce_miibus);
1073
1074         DBPRINT(sc, BCE_INFO, "mii_media_active = 0x%08X\n",
1075                 mii->mii_media_active);
1076
1077 #ifdef BCE_DEBUG
1078         /* Decode the interface media flags. */
1079         if_printf(&sc->arpcom.ac_if, "Media: ( ");
1080         switch(IFM_TYPE(mii->mii_media_active)) {
1081         case IFM_ETHER:
1082                 kprintf("Ethernet )");
1083                 break;
1084         default:
1085                 kprintf("Unknown )");
1086                 break;
1087         }
1088
1089         kprintf(" Media Options: ( ");
1090         switch(IFM_SUBTYPE(mii->mii_media_active)) {
1091         case IFM_AUTO:
1092                 kprintf("Autoselect )");
1093                 break;
1094         case IFM_MANUAL:
1095                 kprintf("Manual )");
1096                 break;
1097         case IFM_NONE:
1098                 kprintf("None )");
1099                 break;
1100         case IFM_10_T:
1101                 kprintf("10Base-T )");
1102                 break;
1103         case IFM_100_TX:
1104                 kprintf("100Base-TX )");
1105                 break;
1106         case IFM_1000_SX:
1107                 kprintf("1000Base-SX )");
1108                 break;
1109         case IFM_1000_T:
1110                 kprintf("1000Base-T )");
1111                 break;
1112         default:
1113                 kprintf("Other )");
1114                 break;
1115         }
1116
1117         kprintf(" Global Options: (");
1118         if (mii->mii_media_active & IFM_FDX)
1119                 kprintf(" FullDuplex");
1120         if (mii->mii_media_active & IFM_HDX)
1121                 kprintf(" HalfDuplex");
1122         if (mii->mii_media_active & IFM_LOOP)
1123                 kprintf(" Loopback");
1124         if (mii->mii_media_active & IFM_FLAG0)
1125                 kprintf(" Flag0");
1126         if (mii->mii_media_active & IFM_FLAG1)
1127                 kprintf(" Flag1");
1128         if (mii->mii_media_active & IFM_FLAG2)
1129                 kprintf(" Flag2");
1130         kprintf(" )\n");
1131 #endif
1132
1133         BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT);
1134
1135         /*
1136          * Set MII or GMII interface based on the speed negotiated
1137          * by the PHY.
1138          */
1139         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
1140             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
1141                 DBPRINT(sc, BCE_INFO, "Setting GMII interface.\n");
1142                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_GMII);
1143         } else {
1144                 DBPRINT(sc, BCE_INFO, "Setting MII interface.\n");
1145                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_MII);
1146         }
1147
1148         /*
1149          * Set half or full duplex based on the duplicity negotiated
1150          * by the PHY.
1151          */
1152         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1153                 DBPRINT(sc, BCE_INFO, "Setting Full-Duplex interface.\n");
1154                 BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1155         } else {
1156                 DBPRINT(sc, BCE_INFO, "Setting Half-Duplex interface.\n");
1157                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1158         }
1159 }
1160
1161
1162 /****************************************************************************/
1163 /* Acquire NVRAM lock.                                                      */
1164 /*                                                                          */
1165 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock.  */
1166 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
1167 /* for use by the driver.                                                   */
1168 /*                                                                          */
1169 /* Returns:                                                                 */
1170 /*   0 on success, positive value on failure.                               */
1171 /****************************************************************************/
1172 static int
1173 bce_acquire_nvram_lock(struct bce_softc *sc)
1174 {
1175         uint32_t val;
1176         int j;
1177
1178         DBPRINT(sc, BCE_VERBOSE, "Acquiring NVRAM lock.\n");
1179
1180         /* Request access to the flash interface. */
1181         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2);
1182         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1183                 val = REG_RD(sc, BCE_NVM_SW_ARB);
1184                 if (val & BCE_NVM_SW_ARB_ARB_ARB2)
1185                         break;
1186
1187                 DELAY(5);
1188         }
1189
1190         if (j >= NVRAM_TIMEOUT_COUNT) {
1191                 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n");
1192                 return EBUSY;
1193         }
1194         return 0;
1195 }
1196
1197
1198 /****************************************************************************/
1199 /* Release NVRAM lock.                                                      */
1200 /*                                                                          */
1201 /* When the caller is finished accessing NVRAM the lock must be released.   */
1202 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
1203 /* for use by the driver.                                                   */
1204 /*                                                                          */
1205 /* Returns:                                                                 */
1206 /*   0 on success, positive value on failure.                               */
1207 /****************************************************************************/
1208 static int
1209 bce_release_nvram_lock(struct bce_softc *sc)
1210 {
1211         int j;
1212         uint32_t val;
1213
1214         DBPRINT(sc, BCE_VERBOSE, "Releasing NVRAM lock.\n");
1215
1216         /*
1217          * Relinquish nvram interface.
1218          */
1219         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2);
1220
1221         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1222                 val = REG_RD(sc, BCE_NVM_SW_ARB);
1223                 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2))
1224                         break;
1225
1226                 DELAY(5);
1227         }
1228
1229         if (j >= NVRAM_TIMEOUT_COUNT) {
1230                 DBPRINT(sc, BCE_WARN, "Timeout reeasing NVRAM lock!\n");
1231                 return EBUSY;
1232         }
1233         return 0;
1234 }
1235
1236
1237 #ifdef BCE_NVRAM_WRITE_SUPPORT
1238 /****************************************************************************/
1239 /* Enable NVRAM write access.                                               */
1240 /*                                                                          */
1241 /* Before writing to NVRAM the caller must enable NVRAM writes.             */
1242 /*                                                                          */
1243 /* Returns:                                                                 */
1244 /*   0 on success, positive value on failure.                               */
1245 /****************************************************************************/
1246 static int
1247 bce_enable_nvram_write(struct bce_softc *sc)
1248 {
1249         uint32_t val;
1250
1251         DBPRINT(sc, BCE_VERBOSE, "Enabling NVRAM write.\n");
1252
1253         val = REG_RD(sc, BCE_MISC_CFG);
1254         REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI);
1255
1256         if (!sc->bce_flash_info->buffered) {
1257                 int j;
1258
1259                 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1260                 REG_WR(sc, BCE_NVM_COMMAND,
1261                        BCE_NVM_COMMAND_WREN | BCE_NVM_COMMAND_DOIT);
1262
1263                 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1264                         DELAY(5);
1265
1266                         val = REG_RD(sc, BCE_NVM_COMMAND);
1267                         if (val & BCE_NVM_COMMAND_DONE)
1268                                 break;
1269                 }
1270
1271                 if (j >= NVRAM_TIMEOUT_COUNT) {
1272                         DBPRINT(sc, BCE_WARN, "Timeout writing NVRAM!\n");
1273                         return EBUSY;
1274                 }
1275         }
1276         return 0;
1277 }
1278
1279
1280 /****************************************************************************/
1281 /* Disable NVRAM write access.                                              */
1282 /*                                                                          */
1283 /* When the caller is finished writing to NVRAM write access must be        */
1284 /* disabled.                                                                */
1285 /*                                                                          */
1286 /* Returns:                                                                 */
1287 /*   Nothing.                                                               */
1288 /****************************************************************************/
1289 static void
1290 bce_disable_nvram_write(struct bce_softc *sc)
1291 {
1292         uint32_t val;
1293
1294         DBPRINT(sc, BCE_VERBOSE, "Disabling NVRAM write.\n");
1295
1296         val = REG_RD(sc, BCE_MISC_CFG);
1297         REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN);
1298 }
1299 #endif  /* BCE_NVRAM_WRITE_SUPPORT */
1300
1301
1302 /****************************************************************************/
1303 /* Enable NVRAM access.                                                     */
1304 /*                                                                          */
1305 /* Before accessing NVRAM for read or write operations the caller must      */
1306 /* enabled NVRAM access.                                                    */
1307 /*                                                                          */
1308 /* Returns:                                                                 */
1309 /*   Nothing.                                                               */
1310 /****************************************************************************/
1311 static void
1312 bce_enable_nvram_access(struct bce_softc *sc)
1313 {
1314         uint32_t val;
1315
1316         DBPRINT(sc, BCE_VERBOSE, "Enabling NVRAM access.\n");
1317
1318         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1319         /* Enable both bits, even on read. */
1320         REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1321                val | BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN);
1322 }
1323
1324
1325 /****************************************************************************/
1326 /* Disable NVRAM access.                                                    */
1327 /*                                                                          */
1328 /* When the caller is finished accessing NVRAM access must be disabled.     */
1329 /*                                                                          */
1330 /* Returns:                                                                 */
1331 /*   Nothing.                                                               */
1332 /****************************************************************************/
1333 static void
1334 bce_disable_nvram_access(struct bce_softc *sc)
1335 {
1336         uint32_t val;
1337
1338         DBPRINT(sc, BCE_VERBOSE, "Disabling NVRAM access.\n");
1339
1340         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1341
1342         /* Disable both bits, even after read. */
1343         REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1344                val & ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN));
1345 }
1346
1347
1348 #ifdef BCE_NVRAM_WRITE_SUPPORT
1349 /****************************************************************************/
1350 /* Erase NVRAM page before writing.                                         */
1351 /*                                                                          */
1352 /* Non-buffered flash parts require that a page be erased before it is      */
1353 /* written.                                                                 */
1354 /*                                                                          */
1355 /* Returns:                                                                 */
1356 /*   0 on success, positive value on failure.                               */
1357 /****************************************************************************/
1358 static int
1359 bce_nvram_erase_page(struct bce_softc *sc, uint32_t offset)
1360 {
1361         uint32_t cmd;
1362         int j;
1363
1364         /* Buffered flash doesn't require an erase. */
1365         if (sc->bce_flash_info->buffered)
1366                 return 0;
1367
1368         DBPRINT(sc, BCE_VERBOSE, "Erasing NVRAM page.\n");
1369
1370         /* Build an erase command. */
1371         cmd = BCE_NVM_COMMAND_ERASE | BCE_NVM_COMMAND_WR |
1372               BCE_NVM_COMMAND_DOIT;
1373
1374         /*
1375          * Clear the DONE bit separately, set the NVRAM adress to erase,
1376          * and issue the erase command.
1377          */
1378         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1379         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
1380         REG_WR(sc, BCE_NVM_COMMAND, cmd);
1381
1382         /* Wait for completion. */
1383         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1384                 uint32_t val;
1385
1386                 DELAY(5);
1387
1388                 val = REG_RD(sc, BCE_NVM_COMMAND);
1389                 if (val & BCE_NVM_COMMAND_DONE)
1390                         break;
1391         }
1392
1393         if (j >= NVRAM_TIMEOUT_COUNT) {
1394                 DBPRINT(sc, BCE_WARN, "Timeout erasing NVRAM.\n");
1395                 return EBUSY;
1396         }
1397         return 0;
1398 }
1399 #endif /* BCE_NVRAM_WRITE_SUPPORT */
1400
1401
1402 /****************************************************************************/
1403 /* Read a dword (32 bits) from NVRAM.                                       */
1404 /*                                                                          */
1405 /* Read a 32 bit word from NVRAM.  The caller is assumed to have already    */
1406 /* obtained the NVRAM lock and enabled the controller for NVRAM access.     */
1407 /*                                                                          */
1408 /* Returns:                                                                 */
1409 /*   0 on success and the 32 bit value read, positive value on failure.     */
1410 /****************************************************************************/
1411 static int
1412 bce_nvram_read_dword(struct bce_softc *sc, uint32_t offset, uint8_t *ret_val,
1413                      uint32_t cmd_flags)
1414 {
1415         uint32_t cmd;
1416         int i, rc = 0;
1417
1418         /* Build the command word. */
1419         cmd = BCE_NVM_COMMAND_DOIT | cmd_flags;
1420
1421         /* Calculate the offset for buffered flash. */
1422         if (sc->bce_flash_info->buffered) {
1423                 offset = ((offset / sc->bce_flash_info->page_size) <<
1424                           sc->bce_flash_info->page_bits) +
1425                          (offset % sc->bce_flash_info->page_size);
1426         }
1427
1428         /*
1429          * Clear the DONE bit separately, set the address to read,
1430          * and issue the read.
1431          */
1432         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1433         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
1434         REG_WR(sc, BCE_NVM_COMMAND, cmd);
1435
1436         /* Wait for completion. */
1437         for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
1438                 uint32_t val;
1439
1440                 DELAY(5);
1441
1442                 val = REG_RD(sc, BCE_NVM_COMMAND);
1443                 if (val & BCE_NVM_COMMAND_DONE) {
1444                         val = REG_RD(sc, BCE_NVM_READ);
1445
1446                         val = be32toh(val);
1447                         memcpy(ret_val, &val, 4);
1448                         break;
1449                 }
1450         }
1451
1452         /* Check for errors. */
1453         if (i >= NVRAM_TIMEOUT_COUNT) {
1454                 if_printf(&sc->arpcom.ac_if,
1455                           "Timeout error reading NVRAM at offset 0x%08X!\n",
1456                           offset);
1457                 rc = EBUSY;
1458         }
1459         return rc;
1460 }
1461
1462
1463 #ifdef BCE_NVRAM_WRITE_SUPPORT
1464 /****************************************************************************/
1465 /* Write a dword (32 bits) to NVRAM.                                        */
1466 /*                                                                          */
1467 /* Write a 32 bit word to NVRAM.  The caller is assumed to have already     */
1468 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and    */
1469 /* enabled NVRAM write access.                                              */
1470 /*                                                                          */
1471 /* Returns:                                                                 */
1472 /*   0 on success, positive value on failure.                               */
1473 /****************************************************************************/
1474 static int
1475 bce_nvram_write_dword(struct bce_softc *sc, uint32_t offset, uint8_t *val,
1476                       uint32_t cmd_flags)
1477 {
1478         uint32_t cmd, val32;
1479         int j;
1480
1481         /* Build the command word. */
1482         cmd = BCE_NVM_COMMAND_DOIT | BCE_NVM_COMMAND_WR | cmd_flags;
1483
1484         /* Calculate the offset for buffered flash. */
1485         if (sc->bce_flash_info->buffered) {
1486                 offset = ((offset / sc->bce_flash_info->page_size) <<
1487                           sc->bce_flash_info->page_bits) +
1488                          (offset % sc->bce_flash_info->page_size);
1489         }
1490
1491         /*
1492          * Clear the DONE bit separately, convert NVRAM data to big-endian,
1493          * set the NVRAM address to write, and issue the write command
1494          */
1495         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1496         memcpy(&val32, val, 4);
1497         val32 = htobe32(val32);
1498         REG_WR(sc, BCE_NVM_WRITE, val32);
1499         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
1500         REG_WR(sc, BCE_NVM_COMMAND, cmd);
1501
1502         /* Wait for completion. */
1503         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1504                 DELAY(5);
1505
1506                 if (REG_RD(sc, BCE_NVM_COMMAND) & BCE_NVM_COMMAND_DONE)
1507                         break;
1508         }
1509         if (j >= NVRAM_TIMEOUT_COUNT) {
1510                 if_printf(&sc->arpcom.ac_if,
1511                           "Timeout error writing NVRAM at offset 0x%08X\n",
1512                           offset);
1513                 return EBUSY;
1514         }
1515         return 0;
1516 }
1517 #endif /* BCE_NVRAM_WRITE_SUPPORT */
1518
1519
1520 /****************************************************************************/
1521 /* Initialize NVRAM access.                                                 */
1522 /*                                                                          */
1523 /* Identify the NVRAM device in use and prepare the NVRAM interface to      */
1524 /* access that device.                                                      */
1525 /*                                                                          */
1526 /* Returns:                                                                 */
1527 /*   0 on success, positive value on failure.                               */
1528 /****************************************************************************/
1529 static int
1530 bce_init_nvram(struct bce_softc *sc)
1531 {
1532         uint32_t val;
1533         int j, entry_count, rc = 0;
1534         const struct flash_spec *flash;
1535
1536         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
1537
1538         /* Determine the selected interface. */
1539         val = REG_RD(sc, BCE_NVM_CFG1);
1540
1541         entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
1542
1543         /*
1544          * Flash reconfiguration is required to support additional
1545          * NVRAM devices not directly supported in hardware.
1546          * Check if the flash interface was reconfigured
1547          * by the bootcode.
1548          */
1549
1550         if (val & 0x40000000) {
1551                 /* Flash interface reconfigured by bootcode. */
1552
1553                 DBPRINT(sc, BCE_INFO_LOAD,
1554                         "%s(): Flash WAS reconfigured.\n", __func__);
1555
1556                 for (j = 0, flash = flash_table; j < entry_count;
1557                      j++, flash++) {
1558                         if ((val & FLASH_BACKUP_STRAP_MASK) ==
1559                             (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
1560                                 sc->bce_flash_info = flash;
1561                                 break;
1562                         }
1563                 }
1564         } else {
1565                 /* Flash interface not yet reconfigured. */
1566                 uint32_t mask;
1567
1568                 DBPRINT(sc, BCE_INFO_LOAD,
1569                         "%s(): Flash was NOT reconfigured.\n", __func__);
1570
1571                 if (val & (1 << 23))
1572                         mask = FLASH_BACKUP_STRAP_MASK;
1573                 else
1574                         mask = FLASH_STRAP_MASK;
1575
1576                 /* Look for the matching NVRAM device configuration data. */
1577                 for (j = 0, flash = flash_table; j < entry_count;
1578                      j++, flash++) {
1579                         /* Check if the device matches any of the known devices. */
1580                         if ((val & mask) == (flash->strapping & mask)) {
1581                                 /* Found a device match. */
1582                                 sc->bce_flash_info = flash;
1583
1584                                 /* Request access to the flash interface. */
1585                                 rc = bce_acquire_nvram_lock(sc);
1586                                 if (rc != 0)
1587                                         return rc;
1588
1589                                 /* Reconfigure the flash interface. */
1590                                 bce_enable_nvram_access(sc);
1591                                 REG_WR(sc, BCE_NVM_CFG1, flash->config1);
1592                                 REG_WR(sc, BCE_NVM_CFG2, flash->config2);
1593                                 REG_WR(sc, BCE_NVM_CFG3, flash->config3);
1594                                 REG_WR(sc, BCE_NVM_WRITE1, flash->write1);
1595                                 bce_disable_nvram_access(sc);
1596                                 bce_release_nvram_lock(sc);
1597                                 break;
1598                         }
1599                 }
1600         }
1601
1602         /* Check if a matching device was found. */
1603         if (j == entry_count) {
1604                 sc->bce_flash_info = NULL;
1605                 if_printf(&sc->arpcom.ac_if, "Unknown Flash NVRAM found!\n");
1606                 rc = ENODEV;
1607         }
1608
1609         /* Write the flash config data to the shared memory interface. */
1610         val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_SHARED_HW_CFG_CONFIG2) &
1611               BCE_SHARED_HW_CFG2_NVM_SIZE_MASK;
1612         if (val)
1613                 sc->bce_flash_size = val;
1614         else
1615                 sc->bce_flash_size = sc->bce_flash_info->total_size;
1616
1617         DBPRINT(sc, BCE_INFO_LOAD, "%s() flash->total_size = 0x%08X\n",
1618                 __func__, sc->bce_flash_info->total_size);
1619
1620         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
1621
1622         return rc;
1623 }
1624
1625
1626 /****************************************************************************/
1627 /* Read an arbitrary range of data from NVRAM.                              */
1628 /*                                                                          */
1629 /* Prepares the NVRAM interface for access and reads the requested data     */
1630 /* into the supplied buffer.                                                */
1631 /*                                                                          */
1632 /* Returns:                                                                 */
1633 /*   0 on success and the data read, positive value on failure.             */
1634 /****************************************************************************/
1635 static int
1636 bce_nvram_read(struct bce_softc *sc, uint32_t offset, uint8_t *ret_buf,
1637                int buf_size)
1638 {
1639         uint32_t cmd_flags, offset32, len32, extra;
1640         int rc = 0;
1641
1642         if (buf_size == 0)
1643                 return 0;
1644
1645         /* Request access to the flash interface. */
1646         rc = bce_acquire_nvram_lock(sc);
1647         if (rc != 0)
1648                 return rc;
1649
1650         /* Enable access to flash interface */
1651         bce_enable_nvram_access(sc);
1652
1653         len32 = buf_size;
1654         offset32 = offset;
1655         extra = 0;
1656
1657         cmd_flags = 0;
1658
1659         /* XXX should we release nvram lock if read_dword() fails? */
1660         if (offset32 & 3) {
1661                 uint8_t buf[4];
1662                 uint32_t pre_len;
1663
1664                 offset32 &= ~3;
1665                 pre_len = 4 - (offset & 3);
1666
1667                 if (pre_len >= len32) {
1668                         pre_len = len32;
1669                         cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST;
1670                 } else {
1671                         cmd_flags = BCE_NVM_COMMAND_FIRST;
1672                 }
1673
1674                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1675                 if (rc)
1676                         return rc;
1677
1678                 memcpy(ret_buf, buf + (offset & 3), pre_len);
1679
1680                 offset32 += 4;
1681                 ret_buf += pre_len;
1682                 len32 -= pre_len;
1683         }
1684
1685         if (len32 & 3) {
1686                 extra = 4 - (len32 & 3);
1687                 len32 = (len32 + 4) & ~3;
1688         }
1689
1690         if (len32 == 4) {
1691                 uint8_t buf[4];
1692
1693                 if (cmd_flags)
1694                         cmd_flags = BCE_NVM_COMMAND_LAST;
1695                 else
1696                         cmd_flags = BCE_NVM_COMMAND_FIRST |
1697                                     BCE_NVM_COMMAND_LAST;
1698
1699                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1700
1701                 memcpy(ret_buf, buf, 4 - extra);
1702         } else if (len32 > 0) {
1703                 uint8_t buf[4];
1704
1705                 /* Read the first word. */
1706                 if (cmd_flags)
1707                         cmd_flags = 0;
1708                 else
1709                         cmd_flags = BCE_NVM_COMMAND_FIRST;
1710
1711                 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags);
1712
1713                 /* Advance to the next dword. */
1714                 offset32 += 4;
1715                 ret_buf += 4;
1716                 len32 -= 4;
1717
1718                 while (len32 > 4 && rc == 0) {
1719                         rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0);
1720
1721                         /* Advance to the next dword. */
1722                         offset32 += 4;
1723                         ret_buf += 4;
1724                         len32 -= 4;
1725                 }
1726
1727                 if (rc)
1728                         return rc;
1729
1730                 cmd_flags = BCE_NVM_COMMAND_LAST;
1731                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1732
1733                 memcpy(ret_buf, buf, 4 - extra);
1734         }
1735
1736         /* Disable access to flash interface and release the lock. */
1737         bce_disable_nvram_access(sc);
1738         bce_release_nvram_lock(sc);
1739
1740         return rc;
1741 }
1742
1743
1744 #ifdef BCE_NVRAM_WRITE_SUPPORT
1745 /****************************************************************************/
1746 /* Write an arbitrary range of data from NVRAM.                             */
1747 /*                                                                          */
1748 /* Prepares the NVRAM interface for write access and writes the requested   */
1749 /* data from the supplied buffer.  The caller is responsible for            */
1750 /* calculating any appropriate CRCs.                                        */
1751 /*                                                                          */
1752 /* Returns:                                                                 */
1753 /*   0 on success, positive value on failure.                               */
1754 /****************************************************************************/
1755 static int
1756 bce_nvram_write(struct bce_softc *sc, uint32_t offset, uint8_t *data_buf,
1757                 int buf_size)
1758 {
1759         uint32_t written, offset32, len32;
1760         uint8_t *buf, start[4], end[4];
1761         int rc = 0;
1762         int align_start, align_end;
1763
1764         buf = data_buf;
1765         offset32 = offset;
1766         len32 = buf_size;
1767         align_end = 0;
1768         align_start = (offset32 & 3);
1769
1770         if (align_start) {
1771                 offset32 &= ~3;
1772                 len32 += align_start;
1773                 rc = bce_nvram_read(sc, offset32, start, 4);
1774                 if (rc)
1775                         return rc;
1776         }
1777
1778         if (len32 & 3) {
1779                 if (len32 > 4 || !align_start) {
1780                         align_end = 4 - (len32 & 3);
1781                         len32 += align_end;
1782                         rc = bce_nvram_read(sc, offset32 + len32 - 4, end, 4);
1783                         if (rc)
1784                                 return rc;
1785                 }
1786         }
1787
1788         if (align_start || align_end) {
1789                 buf = kmalloc(len32, M_DEVBUF, M_NOWAIT);
1790                 if (buf == NULL)
1791                         return ENOMEM;
1792                 if (align_start)
1793                         memcpy(buf, start, 4);
1794                 if (align_end)
1795                         memcpy(buf + len32 - 4, end, 4);
1796                 memcpy(buf + align_start, data_buf, buf_size);
1797         }
1798
1799         written = 0;
1800         while (written < len32 && rc == 0) {
1801                 uint32_t page_start, page_end, data_start, data_end;
1802                 uint32_t addr, cmd_flags;
1803                 int i;
1804                 uint8_t flash_buffer[264];
1805
1806                 /* Find the page_start addr */
1807                 page_start = offset32 + written;
1808                 page_start -= (page_start % sc->bce_flash_info->page_size);
1809                 /* Find the page_end addr */
1810                 page_end = page_start + sc->bce_flash_info->page_size;
1811                 /* Find the data_start addr */
1812                 data_start = (written == 0) ? offset32 : page_start;
1813                 /* Find the data_end addr */
1814                 data_end = (page_end > offset32 + len32) ? (offset32 + len32)
1815                                                          : page_end;
1816
1817                 /* Request access to the flash interface. */
1818                 rc = bce_acquire_nvram_lock(sc);
1819                 if (rc != 0)
1820                         goto nvram_write_end;
1821
1822                 /* Enable access to flash interface */
1823                 bce_enable_nvram_access(sc);
1824
1825                 cmd_flags = BCE_NVM_COMMAND_FIRST;
1826                 if (sc->bce_flash_info->buffered == 0) {
1827                         int j;
1828
1829                         /*
1830                          * Read the whole page into the buffer
1831                          * (non-buffer flash only)
1832                          */
1833                         for (j = 0; j < sc->bce_flash_info->page_size; j += 4) {
1834                                 if (j == (sc->bce_flash_info->page_size - 4))
1835                                         cmd_flags |= BCE_NVM_COMMAND_LAST;
1836
1837                                 rc = bce_nvram_read_dword(sc, page_start + j,
1838                                                           &flash_buffer[j],
1839                                                           cmd_flags);
1840                                 if (rc)
1841                                         goto nvram_write_end;
1842
1843                                 cmd_flags = 0;
1844                         }
1845                 }
1846
1847                 /* Enable writes to flash interface (unlock write-protect) */
1848                 rc = bce_enable_nvram_write(sc);
1849                 if (rc != 0)
1850                         goto nvram_write_end;
1851
1852                 /* Erase the page */
1853                 rc = bce_nvram_erase_page(sc, page_start);
1854                 if (rc != 0)
1855                         goto nvram_write_end;
1856
1857                 /* Re-enable the write again for the actual write */
1858                 bce_enable_nvram_write(sc);
1859
1860                 /* Loop to write back the buffer data from page_start to
1861                  * data_start */
1862                 i = 0;
1863                 if (sc->bce_flash_info->buffered == 0) {
1864                         for (addr = page_start; addr < data_start;
1865                              addr += 4, i += 4) {
1866                                 rc = bce_nvram_write_dword(sc, addr,
1867                                                            &flash_buffer[i],
1868                                                            cmd_flags);
1869                                 if (rc != 0)
1870                                         goto nvram_write_end;
1871
1872                                 cmd_flags = 0;
1873                         }
1874                 }
1875
1876                 /* Loop to write the new data from data_start to data_end */
1877                 for (addr = data_start; addr < data_end; addr += 4, i++) {
1878                         if (addr == page_end - 4 ||
1879                             (sc->bce_flash_info->buffered &&
1880                              addr == data_end - 4))
1881                                 cmd_flags |= BCE_NVM_COMMAND_LAST;
1882
1883                         rc = bce_nvram_write_dword(sc, addr, buf, cmd_flags);
1884                         if (rc != 0)
1885                                 goto nvram_write_end;
1886
1887                         cmd_flags = 0;
1888                         buf += 4;
1889                 }
1890
1891                 /* Loop to write back the buffer data from data_end
1892                  * to page_end */
1893                 if (sc->bce_flash_info->buffered == 0) {
1894                         for (addr = data_end; addr < page_end;
1895                              addr += 4, i += 4) {
1896                                 if (addr == page_end-4)
1897                                         cmd_flags = BCE_NVM_COMMAND_LAST;
1898
1899                                 rc = bce_nvram_write_dword(sc, addr,
1900                                         &flash_buffer[i], cmd_flags);
1901                                 if (rc != 0)
1902                                         goto nvram_write_end;
1903
1904                                 cmd_flags = 0;
1905                         }
1906                 }
1907
1908                 /* Disable writes to flash interface (lock write-protect) */
1909                 bce_disable_nvram_write(sc);
1910
1911                 /* Disable access to flash interface */
1912                 bce_disable_nvram_access(sc);
1913                 bce_release_nvram_lock(sc);
1914
1915                 /* Increment written */
1916                 written += data_end - data_start;
1917         }
1918
1919 nvram_write_end:
1920         if (align_start || align_end)
1921                 kfree(buf, M_DEVBUF);
1922         return rc;
1923 }
1924 #endif /* BCE_NVRAM_WRITE_SUPPORT */
1925
1926
1927 /****************************************************************************/
1928 /* Verifies that NVRAM is accessible and contains valid data.               */
1929 /*                                                                          */
1930 /* Reads the configuration data from NVRAM and verifies that the CRC is     */
1931 /* correct.                                                                 */
1932 /*                                                                          */
1933 /* Returns:                                                                 */
1934 /*   0 on success, positive value on failure.                               */
1935 /****************************************************************************/
1936 static int
1937 bce_nvram_test(struct bce_softc *sc)
1938 {
1939         uint32_t buf[BCE_NVRAM_SIZE / 4];
1940         uint32_t magic, csum;
1941         uint8_t *data = (uint8_t *)buf;
1942         int rc = 0;
1943
1944         /*
1945          * Check that the device NVRAM is valid by reading
1946          * the magic value at offset 0.
1947          */
1948         rc = bce_nvram_read(sc, 0, data, 4);
1949         if (rc != 0)
1950                 return rc;
1951
1952         magic = be32toh(buf[0]);
1953         if (magic != BCE_NVRAM_MAGIC) {
1954                 if_printf(&sc->arpcom.ac_if,
1955                           "Invalid NVRAM magic value! Expected: 0x%08X, "
1956                           "Found: 0x%08X\n", BCE_NVRAM_MAGIC, magic);
1957                 return ENODEV;
1958         }
1959
1960         /*
1961          * Verify that the device NVRAM includes valid
1962          * configuration data.
1963          */
1964         rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE);
1965         if (rc != 0)
1966                 return rc;
1967
1968         csum = ether_crc32_le(data, 0x100);
1969         if (csum != BCE_CRC32_RESIDUAL) {
1970                 if_printf(&sc->arpcom.ac_if,
1971                           "Invalid Manufacturing Information NVRAM CRC! "
1972                           "Expected: 0x%08X, Found: 0x%08X\n",
1973                           BCE_CRC32_RESIDUAL, csum);
1974                 return ENODEV;
1975         }
1976
1977         csum = ether_crc32_le(data + 0x100, 0x100);
1978         if (csum != BCE_CRC32_RESIDUAL) {
1979                 if_printf(&sc->arpcom.ac_if,
1980                           "Invalid Feature Configuration Information "
1981                           "NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n",
1982                           BCE_CRC32_RESIDUAL, csum);
1983                 rc = ENODEV;
1984         }
1985         return rc;
1986 }
1987
1988
1989 /****************************************************************************/
1990 /* Free any DMA memory owned by the driver.                                 */
1991 /*                                                                          */
1992 /* Scans through each data structre that requires DMA memory and frees      */
1993 /* the memory if allocated.                                                 */
1994 /*                                                                          */
1995 /* Returns:                                                                 */
1996 /*   Nothing.                                                               */
1997 /****************************************************************************/
1998 static void
1999 bce_dma_free(struct bce_softc *sc)
2000 {
2001         int i;
2002
2003         /* Destroy the status block. */
2004         if (sc->status_tag != NULL) {
2005                 if (sc->status_block != NULL) {
2006                         bus_dmamap_unload(sc->status_tag, sc->status_map);
2007                         bus_dmamem_free(sc->status_tag, sc->status_block,
2008                                         sc->status_map);
2009                 }
2010                 bus_dma_tag_destroy(sc->status_tag);
2011         }
2012
2013
2014         /* Destroy the statistics block. */
2015         if (sc->stats_tag != NULL) {
2016                 if (sc->stats_block != NULL) {
2017                         bus_dmamap_unload(sc->stats_tag, sc->stats_map);
2018                         bus_dmamem_free(sc->stats_tag, sc->stats_block,
2019                                         sc->stats_map);
2020                 }
2021                 bus_dma_tag_destroy(sc->stats_tag);
2022         }
2023
2024         /* Destroy the TX buffer descriptor DMA stuffs. */
2025         if (sc->tx_bd_chain_tag != NULL) {
2026                 for (i = 0; i < TX_PAGES; i++) {
2027                         if (sc->tx_bd_chain[i] != NULL) {
2028                                 bus_dmamap_unload(sc->tx_bd_chain_tag,
2029                                                   sc->tx_bd_chain_map[i]);
2030                                 bus_dmamem_free(sc->tx_bd_chain_tag,
2031                                                 sc->tx_bd_chain[i],
2032                                                 sc->tx_bd_chain_map[i]);
2033                         }
2034                 }
2035                 bus_dma_tag_destroy(sc->tx_bd_chain_tag);
2036         }
2037
2038         /* Destroy the RX buffer descriptor DMA stuffs. */
2039         if (sc->rx_bd_chain_tag != NULL) {
2040                 for (i = 0; i < RX_PAGES; i++) {
2041                         if (sc->rx_bd_chain[i] != NULL) {
2042                                 bus_dmamap_unload(sc->rx_bd_chain_tag,
2043                                                   sc->rx_bd_chain_map[i]);
2044                                 bus_dmamem_free(sc->rx_bd_chain_tag,
2045                                                 sc->rx_bd_chain[i],
2046                                                 sc->rx_bd_chain_map[i]);
2047                         }
2048                 }
2049                 bus_dma_tag_destroy(sc->rx_bd_chain_tag);
2050         }
2051
2052         /* Destroy the TX mbuf DMA stuffs. */
2053         if (sc->tx_mbuf_tag != NULL) {
2054                 for (i = 0; i < TOTAL_TX_BD; i++) {
2055                         /* Must have been unloaded in bce_stop() */
2056                         KKASSERT(sc->tx_mbuf_ptr[i] == NULL);
2057                         bus_dmamap_destroy(sc->tx_mbuf_tag,
2058                                            sc->tx_mbuf_map[i]);
2059                 }
2060                 bus_dma_tag_destroy(sc->tx_mbuf_tag);
2061         }
2062
2063         /* Destroy the RX mbuf DMA stuffs. */
2064         if (sc->rx_mbuf_tag != NULL) {
2065                 for (i = 0; i < TOTAL_RX_BD; i++) {
2066                         /* Must have been unloaded in bce_stop() */
2067                         KKASSERT(sc->rx_mbuf_ptr[i] == NULL);
2068                         bus_dmamap_destroy(sc->rx_mbuf_tag,
2069                                            sc->rx_mbuf_map[i]);
2070                 }
2071                 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2072         }
2073
2074         /* Destroy the parent tag */
2075         if (sc->parent_tag != NULL)
2076                 bus_dma_tag_destroy(sc->parent_tag);
2077 }
2078
2079
2080 /****************************************************************************/
2081 /* Get DMA memory from the OS.                                              */
2082 /*                                                                          */
2083 /* Validates that the OS has provided DMA buffers in response to a          */
2084 /* bus_dmamap_load() call and saves the physical address of those buffers.  */
2085 /* When the callback is used the OS will return 0 for the mapping function  */
2086 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any  */
2087 /* failures back to the caller.                                             */
2088 /*                                                                          */
2089 /* Returns:                                                                 */
2090 /*   Nothing.                                                               */
2091 /****************************************************************************/
2092 static void
2093 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2094 {
2095         bus_addr_t *busaddr = arg;
2096
2097         /*
2098          * Simulate a mapping failure.
2099          * XXX not correct.
2100          */
2101         DBRUNIF(DB_RANDOMTRUE(bce_debug_dma_map_addr_failure),
2102                 kprintf("bce: %s(%d): Simulating DMA mapping error.\n",
2103                         __FILE__, __LINE__);
2104                 error = ENOMEM);
2105
2106         /* Check for an error and signal the caller that an error occurred. */
2107         if (error)
2108                 return;
2109
2110         KASSERT(nseg == 1, ("only one segment is allowed\n"));
2111         *busaddr = segs->ds_addr;
2112 }
2113
2114
2115 static void
2116 bce_dma_map_mbuf(void *arg, bus_dma_segment_t *segs, int nsegs,
2117                  bus_size_t mapsz __unused, int error)
2118 {
2119         struct bce_dmamap_arg *ctx = arg;
2120         int i;
2121
2122         if (error)
2123                 return;
2124
2125         if (nsegs > ctx->bce_maxsegs) {
2126                 ctx->bce_maxsegs = 0;
2127                 return;
2128         }
2129
2130         ctx->bce_maxsegs = nsegs;
2131         for (i = 0; i < nsegs; ++i)
2132                 ctx->bce_segs[i] = segs[i];
2133 }
2134
2135
2136 /****************************************************************************/
2137 /* Allocate any DMA memory needed by the driver.                            */
2138 /*                                                                          */
2139 /* Allocates DMA memory needed for the various global structures needed by  */
2140 /* hardware.                                                                */
2141 /*                                                                          */
2142 /* Returns:                                                                 */
2143 /*   0 for success, positive value for failure.                             */
2144 /****************************************************************************/
2145 static int
2146 bce_dma_alloc(struct bce_softc *sc)
2147 {
2148         struct ifnet *ifp = &sc->arpcom.ac_if;
2149         int i, j, rc = 0;
2150         bus_addr_t busaddr;
2151
2152         /*
2153          * Allocate the parent bus DMA tag appropriate for PCI.
2154          */
2155         rc = bus_dma_tag_create(NULL, 1, BCE_DMA_BOUNDARY,
2156                                 sc->max_bus_addr, BUS_SPACE_MAXADDR,
2157                                 NULL, NULL,
2158                                 MAXBSIZE, BUS_SPACE_UNRESTRICTED,
2159                                 BUS_SPACE_MAXSIZE_32BIT,
2160                                 0, &sc->parent_tag);
2161         if (rc != 0) {
2162                 if_printf(ifp, "Could not allocate parent DMA tag!\n");
2163                 return rc;
2164         }
2165
2166         /*
2167          * Create a DMA tag for the status block, allocate and clear the
2168          * memory, map the memory into DMA space, and fetch the physical
2169          * address of the block.
2170          */
2171         rc = bus_dma_tag_create(sc->parent_tag,
2172                                 BCE_DMA_ALIGN, BCE_DMA_BOUNDARY,
2173                                 sc->max_bus_addr, BUS_SPACE_MAXADDR,
2174                                 NULL, NULL,
2175                                 BCE_STATUS_BLK_SZ, 1, BCE_STATUS_BLK_SZ,
2176                                 0, &sc->status_tag);
2177         if (rc != 0) {
2178                 if_printf(ifp, "Could not allocate status block DMA tag!\n");
2179                 return rc;
2180         }
2181
2182         rc = bus_dmamem_alloc(sc->status_tag, (void **)&sc->status_block,
2183                               BUS_DMA_WAITOK | BUS_DMA_ZERO,
2184                               &sc->status_map);
2185         if (rc != 0) {
2186                 if_printf(ifp, "Could not allocate status block DMA memory!\n");
2187                 return rc;
2188         }
2189
2190         rc = bus_dmamap_load(sc->status_tag, sc->status_map,
2191                              sc->status_block, BCE_STATUS_BLK_SZ,
2192                              bce_dma_map_addr, &busaddr, BUS_DMA_WAITOK);
2193         if (rc != 0) {
2194                 if_printf(ifp, "Could not map status block DMA memory!\n");
2195                 bus_dmamem_free(sc->status_tag, sc->status_block,
2196                                 sc->status_map);
2197                 sc->status_block = NULL;
2198                 return rc;
2199         }
2200
2201         sc->status_block_paddr = busaddr;
2202         /* DRC - Fix for 64 bit addresses. */
2203         DBPRINT(sc, BCE_INFO, "status_block_paddr = 0x%08X\n",
2204                 (uint32_t)sc->status_block_paddr);
2205
2206         /*
2207          * Create a DMA tag for the statistics block, allocate and clear the
2208          * memory, map the memory into DMA space, and fetch the physical
2209          * address of the block.
2210          */
2211         rc = bus_dma_tag_create(sc->parent_tag,
2212                                 BCE_DMA_ALIGN, BCE_DMA_BOUNDARY,
2213                                 sc->max_bus_addr, BUS_SPACE_MAXADDR,
2214                                 NULL, NULL,
2215                                 BCE_STATS_BLK_SZ, 1, BCE_STATS_BLK_SZ,
2216                                 0, &sc->stats_tag);
2217         if (rc != 0) {
2218                 if_printf(ifp, "Could not allocate "
2219                           "statistics block DMA tag!\n");
2220                 return rc;
2221         }
2222
2223         rc = bus_dmamem_alloc(sc->stats_tag, (void **)&sc->stats_block,
2224                               BUS_DMA_WAITOK | BUS_DMA_ZERO,
2225                               &sc->stats_map);
2226         if (rc != 0) {
2227                 if_printf(ifp, "Could not allocate "
2228                           "statistics block DMA memory!\n");
2229                 return rc;
2230         }
2231
2232         rc = bus_dmamap_load(sc->stats_tag, sc->stats_map,
2233                              sc->stats_block, BCE_STATS_BLK_SZ,
2234                              bce_dma_map_addr, &busaddr, BUS_DMA_WAITOK);
2235         if (rc != 0) {
2236                 if_printf(ifp, "Could not map statistics block DMA memory!\n");
2237                 bus_dmamem_free(sc->stats_tag, sc->stats_block, sc->stats_map);
2238                 sc->stats_block = NULL;
2239                 return rc;
2240         }
2241
2242         sc->stats_block_paddr = busaddr;
2243         /* DRC - Fix for 64 bit address. */
2244         DBPRINT(sc, BCE_INFO, "stats_block_paddr = 0x%08X\n",
2245                 (uint32_t)sc->stats_block_paddr);
2246
2247         /*
2248          * Create a DMA tag for the TX buffer descriptor chain,
2249          * allocate and clear the  memory, and fetch the
2250          * physical address of the block.
2251          */
2252         rc = bus_dma_tag_create(sc->parent_tag,
2253                                 BCM_PAGE_SIZE, BCE_DMA_BOUNDARY,
2254                                 sc->max_bus_addr, BUS_SPACE_MAXADDR,
2255                                 NULL, NULL,
2256                                 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ,
2257                                 0, &sc->tx_bd_chain_tag);
2258         if (rc != 0) {
2259                 if_printf(ifp, "Could not allocate "
2260                           "TX descriptor chain DMA tag!\n");
2261                 return rc;
2262         }
2263
2264         for (i = 0; i < TX_PAGES; i++) {
2265                 rc = bus_dmamem_alloc(sc->tx_bd_chain_tag,
2266                                       (void **)&sc->tx_bd_chain[i],
2267                                       BUS_DMA_WAITOK, &sc->tx_bd_chain_map[i]);
2268                 if (rc != 0) {
2269                         if_printf(ifp, "Could not allocate %dth TX descriptor "
2270                                   "chain DMA memory!\n", i);
2271                         return rc;
2272                 }
2273
2274                 rc = bus_dmamap_load(sc->tx_bd_chain_tag,
2275                                      sc->tx_bd_chain_map[i],
2276                                      sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ,
2277                                      bce_dma_map_addr, &busaddr,
2278                                      BUS_DMA_WAITOK);
2279                 if (rc != 0) {
2280                         if_printf(ifp, "Could not map %dth TX descriptor "
2281                                   "chain DMA memory!\n", i);
2282                         bus_dmamem_free(sc->tx_bd_chain_tag,
2283                                         sc->tx_bd_chain[i],
2284                                         sc->tx_bd_chain_map[i]);
2285                         sc->tx_bd_chain[i] = NULL;
2286                         return rc;
2287                 }
2288
2289                 sc->tx_bd_chain_paddr[i] = busaddr;
2290                 /* DRC - Fix for 64 bit systems. */
2291                 DBPRINT(sc, BCE_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n",
2292                         i, (uint32_t)sc->tx_bd_chain_paddr[i]);
2293         }
2294
2295         /* Create a DMA tag for TX mbufs. */
2296         rc = bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY,
2297                                 sc->max_bus_addr, BUS_SPACE_MAXADDR,
2298                                 NULL, NULL,
2299                                 MCLBYTES * BCE_MAX_SEGMENTS,
2300                                 BCE_MAX_SEGMENTS, MCLBYTES,
2301                                 0, &sc->tx_mbuf_tag);
2302         if (rc != 0) {
2303                 if_printf(ifp, "Could not allocate TX mbuf DMA tag!\n");
2304                 return rc;
2305         }
2306
2307         /* Create DMA maps for the TX mbufs clusters. */
2308         for (i = 0; i < TOTAL_TX_BD; i++) {
2309                 rc = bus_dmamap_create(sc->tx_mbuf_tag, BUS_DMA_WAITOK,
2310                                        &sc->tx_mbuf_map[i]);
2311                 if (rc != 0) {
2312                         for (j = 0; j < i; ++j) {
2313                                 bus_dmamap_destroy(sc->tx_mbuf_tag,
2314                                                    sc->tx_mbuf_map[i]);
2315                         }
2316                         bus_dma_tag_destroy(sc->tx_mbuf_tag);
2317                         sc->tx_mbuf_tag = NULL;
2318
2319                         if_printf(ifp, "Unable to create "
2320                                   "%dth TX mbuf DMA map!\n", i);
2321                         return rc;
2322                 }
2323         }
2324
2325         /*
2326          * Create a DMA tag for the RX buffer descriptor chain,
2327          * allocate and clear the  memory, and fetch the physical
2328          * address of the blocks.
2329          */
2330         rc = bus_dma_tag_create(sc->parent_tag,
2331                                 BCM_PAGE_SIZE, BCE_DMA_BOUNDARY,
2332                                 sc->max_bus_addr, BUS_SPACE_MAXADDR,
2333                                 NULL, NULL,
2334                                 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ,
2335                                 0, &sc->rx_bd_chain_tag);
2336         if (rc != 0) {
2337                 if_printf(ifp, "Could not allocate "
2338                           "RX descriptor chain DMA tag!\n");
2339                 return rc;
2340         }
2341
2342         for (i = 0; i < RX_PAGES; i++) {
2343                 rc = bus_dmamem_alloc(sc->rx_bd_chain_tag,
2344                                       (void **)&sc->rx_bd_chain[i],
2345                                       BUS_DMA_WAITOK | BUS_DMA_ZERO,
2346                                       &sc->rx_bd_chain_map[i]);
2347                 if (rc != 0) {
2348                         if_printf(ifp, "Could not allocate %dth RX descriptor "
2349                                   "chain DMA memory!\n", i);
2350                         return rc;
2351                 }
2352
2353                 rc = bus_dmamap_load(sc->rx_bd_chain_tag,
2354                                      sc->rx_bd_chain_map[i],
2355                                      sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ,
2356                                      bce_dma_map_addr, &busaddr,
2357                                      BUS_DMA_WAITOK);
2358                 if (rc != 0) {
2359                         if_printf(ifp, "Could not map %dth RX descriptor "
2360                                   "chain DMA memory!\n", i);
2361                         bus_dmamem_free(sc->rx_bd_chain_tag,
2362                                         sc->rx_bd_chain[i],
2363                                         sc->rx_bd_chain_map[i]);
2364                         sc->rx_bd_chain[i] = NULL;
2365                         return rc;
2366                 }
2367
2368                 sc->rx_bd_chain_paddr[i] = busaddr;
2369                 /* DRC - Fix for 64 bit systems. */
2370                 DBPRINT(sc, BCE_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n",
2371                         i, (uint32_t)sc->rx_bd_chain_paddr[i]);
2372         }
2373
2374         /* Create a DMA tag for RX mbufs. */
2375         rc = bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY,
2376                                 sc->max_bus_addr, BUS_SPACE_MAXADDR,
2377                                 NULL, NULL,
2378                                 MCLBYTES, 1/* BCE_MAX_SEGMENTS */, MCLBYTES,
2379                                 0, &sc->rx_mbuf_tag);
2380         if (rc != 0) {
2381                 if_printf(ifp, "Could not allocate RX mbuf DMA tag!\n");
2382                 return rc;
2383         }
2384
2385         /* Create DMA maps for the RX mbuf clusters. */
2386         for (i = 0; i < TOTAL_RX_BD; i++) {
2387                 rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2388                                        &sc->rx_mbuf_map[i]);
2389                 if (rc != 0) {
2390                         for (j = 0; j < i; ++j) {
2391                                 bus_dmamap_destroy(sc->rx_mbuf_tag,
2392                                                    sc->rx_mbuf_map[j]);
2393                         }
2394                         bus_dma_tag_destroy(sc->rx_mbuf_tag);
2395                         sc->rx_mbuf_tag = NULL;
2396
2397                         if_printf(ifp, "Unable to create "
2398                                   "%dth RX mbuf DMA map!\n", i);
2399                         return rc;
2400                 }
2401         }
2402         return 0;
2403 }
2404
2405
2406 /****************************************************************************/
2407 /* Firmware synchronization.                                                */
2408 /*                                                                          */
2409 /* Before performing certain events such as a chip reset, synchronize with  */
2410 /* the firmware first.                                                      */
2411 /*                                                                          */
2412 /* Returns:                                                                 */
2413 /*   0 for success, positive value for failure.                             */
2414 /****************************************************************************/
2415 static int
2416 bce_fw_sync(struct bce_softc *sc, uint32_t msg_data)
2417 {
2418         int i, rc = 0;
2419         uint32_t val;
2420
2421         /* Don't waste any time if we've timed out before. */
2422         if (sc->bce_fw_timed_out)
2423                 return EBUSY;
2424
2425         /* Increment the message sequence number. */
2426         sc->bce_fw_wr_seq++;
2427         msg_data |= sc->bce_fw_wr_seq;
2428
2429         DBPRINT(sc, BCE_VERBOSE, "bce_fw_sync(): msg_data = 0x%08X\n", msg_data);
2430
2431         /* Send the message to the bootcode driver mailbox. */
2432         REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_MB, msg_data);
2433
2434         /* Wait for the bootcode to acknowledge the message. */
2435         for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) {
2436                 /* Check for a response in the bootcode firmware mailbox. */
2437                 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_FW_MB);
2438                 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ))
2439                         break;
2440                 DELAY(1000);
2441         }
2442
2443         /* If we've timed out, tell the bootcode that we've stopped waiting. */
2444         if ((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ) &&
2445             (msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0) {
2446                 if_printf(&sc->arpcom.ac_if,
2447                           "Firmware synchronization timeout! "
2448                           "msg_data = 0x%08X\n", msg_data);
2449
2450                 msg_data &= ~BCE_DRV_MSG_CODE;
2451                 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT;
2452
2453                 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_MB, msg_data);
2454
2455                 sc->bce_fw_timed_out = 1;
2456                 rc = EBUSY;
2457         }
2458         return rc;
2459 }
2460
2461
2462 /****************************************************************************/
2463 /* Load Receive Virtual 2 Physical (RV2P) processor firmware.               */
2464 /*                                                                          */
2465 /* Returns:                                                                 */
2466 /*   Nothing.                                                               */
2467 /****************************************************************************/
2468 static void
2469 bce_load_rv2p_fw(struct bce_softc *sc, uint32_t *rv2p_code,
2470                  uint32_t rv2p_code_len, uint32_t rv2p_proc)
2471 {
2472         int i;
2473         uint32_t val;
2474
2475         for (i = 0; i < rv2p_code_len; i += 8) {
2476                 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code);
2477                 rv2p_code++;
2478                 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code);
2479                 rv2p_code++;
2480
2481                 if (rv2p_proc == RV2P_PROC1) {
2482                         val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR;
2483                         REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
2484                 } else {
2485                         val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR;
2486                         REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
2487                 }
2488         }
2489
2490         /* Reset the processor, un-stall is done later. */
2491         if (rv2p_proc == RV2P_PROC1)
2492                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET);
2493         else
2494                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);
2495 }
2496
2497
2498 /****************************************************************************/
2499 /* Load RISC processor firmware.                                            */
2500 /*                                                                          */
2501 /* Loads firmware from the file if_bcefw.h into the scratchpad memory       */
2502 /* associated with a particular processor.                                  */
2503 /*                                                                          */
2504 /* Returns:                                                                 */
2505 /*   Nothing.                                                               */
2506 /****************************************************************************/
2507 static void
2508 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,
2509                 struct fw_info *fw)
2510 {
2511         uint32_t offset, val;
2512         int j;
2513
2514         /* Halt the CPU. */
2515         val = REG_RD_IND(sc, cpu_reg->mode);
2516         val |= cpu_reg->mode_value_halt;
2517         REG_WR_IND(sc, cpu_reg->mode, val);
2518         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2519
2520         /* Load the Text area. */
2521         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2522         if (fw->text) {
2523                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4)
2524                         REG_WR_IND(sc, offset, fw->text[j]);
2525         }
2526
2527         /* Load the Data area. */
2528         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2529         if (fw->data) {
2530                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4)
2531                         REG_WR_IND(sc, offset, fw->data[j]);
2532         }
2533
2534         /* Load the SBSS area. */
2535         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2536         if (fw->sbss) {
2537                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4)
2538                         REG_WR_IND(sc, offset, fw->sbss[j]);
2539         }
2540
2541         /* Load the BSS area. */
2542         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2543         if (fw->bss) {
2544                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4)
2545                         REG_WR_IND(sc, offset, fw->bss[j]);
2546         }
2547
2548         /* Load the Read-Only area. */
2549         offset = cpu_reg->spad_base +
2550                 (fw->rodata_addr - cpu_reg->mips_view_base);
2551         if (fw->rodata) {
2552                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4)
2553                         REG_WR_IND(sc, offset, fw->rodata[j]);
2554         }
2555
2556         /* Clear the pre-fetch instruction. */
2557         REG_WR_IND(sc, cpu_reg->inst, 0);
2558         REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
2559
2560         /* Start the CPU. */
2561         val = REG_RD_IND(sc, cpu_reg->mode);
2562         val &= ~cpu_reg->mode_value_halt;
2563         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2564         REG_WR_IND(sc, cpu_reg->mode, val);
2565 }
2566
2567
2568 /****************************************************************************/
2569 /* Initialize the RV2P, RX, TX, TPAT, and COM CPUs.                         */
2570 /*                                                                          */
2571 /* Loads the firmware for each CPU and starts the CPU.                      */
2572 /*                                                                          */
2573 /* Returns:                                                                 */
2574 /*   Nothing.                                                               */
2575 /****************************************************************************/
2576 static void
2577 bce_init_cpus(struct bce_softc *sc)
2578 {
2579         struct cpu_reg cpu_reg;
2580         struct fw_info fw;
2581
2582         /* Initialize the RV2P processor. */
2583         bce_load_rv2p_fw(sc, bce_rv2p_proc1, sizeof(bce_rv2p_proc1), RV2P_PROC1);
2584         bce_load_rv2p_fw(sc, bce_rv2p_proc2, sizeof(bce_rv2p_proc2), RV2P_PROC2);
2585
2586         /* Initialize the RX Processor. */
2587         cpu_reg.mode = BCE_RXP_CPU_MODE;
2588         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2589         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2590         cpu_reg.state = BCE_RXP_CPU_STATE;
2591         cpu_reg.state_value_clear = 0xffffff;
2592         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2593         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2594         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2595         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2596         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2597         cpu_reg.spad_base = BCE_RXP_SCRATCH;
2598         cpu_reg.mips_view_base = 0x8000000;
2599
2600         fw.ver_major = bce_RXP_b06FwReleaseMajor;
2601         fw.ver_minor = bce_RXP_b06FwReleaseMinor;
2602         fw.ver_fix = bce_RXP_b06FwReleaseFix;
2603         fw.start_addr = bce_RXP_b06FwStartAddr;
2604
2605         fw.text_addr = bce_RXP_b06FwTextAddr;
2606         fw.text_len = bce_RXP_b06FwTextLen;
2607         fw.text_index = 0;
2608         fw.text = bce_RXP_b06FwText;
2609
2610         fw.data_addr = bce_RXP_b06FwDataAddr;
2611         fw.data_len = bce_RXP_b06FwDataLen;
2612         fw.data_index = 0;
2613         fw.data = bce_RXP_b06FwData;
2614
2615         fw.sbss_addr = bce_RXP_b06FwSbssAddr;
2616         fw.sbss_len = bce_RXP_b06FwSbssLen;
2617         fw.sbss_index = 0;
2618         fw.sbss = bce_RXP_b06FwSbss;
2619
2620         fw.bss_addr = bce_RXP_b06FwBssAddr;
2621         fw.bss_len = bce_RXP_b06FwBssLen;
2622         fw.bss_index = 0;
2623         fw.bss = bce_RXP_b06FwBss;
2624
2625         fw.rodata_addr = bce_RXP_b06FwRodataAddr;
2626         fw.rodata_len = bce_RXP_b06FwRodataLen;
2627         fw.rodata_index = 0;
2628         fw.rodata = bce_RXP_b06FwRodata;
2629
2630         DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n");
2631         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2632
2633         /* Initialize the TX Processor. */
2634         cpu_reg.mode = BCE_TXP_CPU_MODE;
2635         cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;
2636         cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;
2637         cpu_reg.state = BCE_TXP_CPU_STATE;
2638         cpu_reg.state_value_clear = 0xffffff;
2639         cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;
2640         cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;
2641         cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;
2642         cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;
2643         cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;
2644         cpu_reg.spad_base = BCE_TXP_SCRATCH;
2645         cpu_reg.mips_view_base = 0x8000000;
2646
2647         fw.ver_major = bce_TXP_b06FwReleaseMajor;
2648         fw.ver_minor = bce_TXP_b06FwReleaseMinor;
2649         fw.ver_fix = bce_TXP_b06FwReleaseFix;
2650         fw.start_addr = bce_TXP_b06FwStartAddr;
2651
2652         fw.text_addr = bce_TXP_b06FwTextAddr;
2653         fw.text_len = bce_TXP_b06FwTextLen;
2654         fw.text_index = 0;
2655         fw.text = bce_TXP_b06FwText;
2656
2657         fw.data_addr = bce_TXP_b06FwDataAddr;
2658         fw.data_len = bce_TXP_b06FwDataLen;
2659         fw.data_index = 0;
2660         fw.data = bce_TXP_b06FwData;
2661
2662         fw.sbss_addr = bce_TXP_b06FwSbssAddr;
2663         fw.sbss_len = bce_TXP_b06FwSbssLen;
2664         fw.sbss_index = 0;
2665         fw.sbss = bce_TXP_b06FwSbss;
2666
2667         fw.bss_addr = bce_TXP_b06FwBssAddr;
2668         fw.bss_len = bce_TXP_b06FwBssLen;
2669         fw.bss_index = 0;
2670         fw.bss = bce_TXP_b06FwBss;
2671
2672         fw.rodata_addr = bce_TXP_b06FwRodataAddr;
2673         fw.rodata_len = bce_TXP_b06FwRodataLen;
2674         fw.rodata_index = 0;
2675         fw.rodata = bce_TXP_b06FwRodata;
2676
2677         DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n");
2678         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2679
2680         /* Initialize the TX Patch-up Processor. */
2681         cpu_reg.mode = BCE_TPAT_CPU_MODE;
2682         cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;
2683         cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;
2684         cpu_reg.state = BCE_TPAT_CPU_STATE;
2685         cpu_reg.state_value_clear = 0xffffff;
2686         cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;
2687         cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;
2688         cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;
2689         cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;
2690         cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;
2691         cpu_reg.spad_base = BCE_TPAT_SCRATCH;
2692         cpu_reg.mips_view_base = 0x8000000;
2693
2694         fw.ver_major = bce_TPAT_b06FwReleaseMajor;
2695         fw.ver_minor = bce_TPAT_b06FwReleaseMinor;
2696         fw.ver_fix = bce_TPAT_b06FwReleaseFix;
2697         fw.start_addr = bce_TPAT_b06FwStartAddr;
2698
2699         fw.text_addr = bce_TPAT_b06FwTextAddr;
2700         fw.text_len = bce_TPAT_b06FwTextLen;
2701         fw.text_index = 0;
2702         fw.text = bce_TPAT_b06FwText;
2703
2704         fw.data_addr = bce_TPAT_b06FwDataAddr;
2705         fw.data_len = bce_TPAT_b06FwDataLen;
2706         fw.data_index = 0;
2707         fw.data = bce_TPAT_b06FwData;
2708
2709         fw.sbss_addr = bce_TPAT_b06FwSbssAddr;
2710         fw.sbss_len = bce_TPAT_b06FwSbssLen;
2711         fw.sbss_index = 0;
2712         fw.sbss = bce_TPAT_b06FwSbss;
2713
2714         fw.bss_addr = bce_TPAT_b06FwBssAddr;
2715         fw.bss_len = bce_TPAT_b06FwBssLen;
2716         fw.bss_index = 0;
2717         fw.bss = bce_TPAT_b06FwBss;
2718
2719         fw.rodata_addr = bce_TPAT_b06FwRodataAddr;
2720         fw.rodata_len = bce_TPAT_b06FwRodataLen;
2721         fw.rodata_index = 0;
2722         fw.rodata = bce_TPAT_b06FwRodata;
2723
2724         DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n");
2725         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2726
2727         /* Initialize the Completion Processor. */
2728         cpu_reg.mode = BCE_COM_CPU_MODE;
2729         cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;
2730         cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;
2731         cpu_reg.state = BCE_COM_CPU_STATE;
2732         cpu_reg.state_value_clear = 0xffffff;
2733         cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;
2734         cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;
2735         cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;
2736         cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;
2737         cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;
2738         cpu_reg.spad_base = BCE_COM_SCRATCH;
2739         cpu_reg.mips_view_base = 0x8000000;
2740
2741         fw.ver_major = bce_COM_b06FwReleaseMajor;
2742         fw.ver_minor = bce_COM_b06FwReleaseMinor;
2743         fw.ver_fix = bce_COM_b06FwReleaseFix;
2744         fw.start_addr = bce_COM_b06FwStartAddr;
2745
2746         fw.text_addr = bce_COM_b06FwTextAddr;
2747         fw.text_len = bce_COM_b06FwTextLen;
2748         fw.text_index = 0;
2749         fw.text = bce_COM_b06FwText;
2750
2751         fw.data_addr = bce_COM_b06FwDataAddr;
2752         fw.data_len = bce_COM_b06FwDataLen;
2753         fw.data_index = 0;
2754         fw.data = bce_COM_b06FwData;
2755
2756         fw.sbss_addr = bce_COM_b06FwSbssAddr;
2757         fw.sbss_len = bce_COM_b06FwSbssLen;
2758         fw.sbss_index = 0;
2759         fw.sbss = bce_COM_b06FwSbss;
2760
2761         fw.bss_addr = bce_COM_b06FwBssAddr;
2762         fw.bss_len = bce_COM_b06FwBssLen;
2763         fw.bss_index = 0;
2764         fw.bss = bce_COM_b06FwBss;
2765
2766         fw.rodata_addr = bce_COM_b06FwRodataAddr;
2767         fw.rodata_len = bce_COM_b06FwRodataLen;
2768         fw.rodata_index = 0;
2769         fw.rodata = bce_COM_b06FwRodata;
2770
2771         DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n");
2772         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2773 }
2774
2775
2776 /****************************************************************************/
2777 /* Initialize context memory.                                               */
2778 /*                                                                          */
2779 /* Clears the memory associated with each Context ID (CID).                 */
2780 /*                                                                          */
2781 /* Returns:                                                                 */
2782 /*   Nothing.                                                               */
2783 /****************************************************************************/
2784 static void
2785 bce_init_context(struct bce_softc *sc)
2786 {
2787         uint32_t vcid;
2788
2789         vcid = 96;
2790         while (vcid) {
2791                 uint32_t vcid_addr, pcid_addr, offset;
2792
2793                 vcid--;
2794
2795                 vcid_addr = GET_CID_ADDR(vcid);
2796                 pcid_addr = vcid_addr;
2797
2798                 REG_WR(sc, BCE_CTX_VIRT_ADDR, 0x00);
2799                 REG_WR(sc, BCE_CTX_PAGE_TBL, pcid_addr);
2800
2801                 /* Zero out the context. */
2802                 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
2803                         CTX_WR(sc, 0x00, offset, 0);
2804
2805                 REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr);
2806                 REG_WR(sc, BCE_CTX_PAGE_TBL, pcid_addr);
2807         }
2808 }
2809
2810
2811 /****************************************************************************/
2812 /* Fetch the permanent MAC address of the controller.                       */
2813 /*                                                                          */
2814 /* Returns:                                                                 */
2815 /*   Nothing.                                                               */
2816 /****************************************************************************/
2817 static void
2818 bce_get_mac_addr(struct bce_softc *sc)
2819 {
2820         uint32_t mac_lo = 0, mac_hi = 0;
2821
2822         /*
2823          * The NetXtreme II bootcode populates various NIC
2824          * power-on and runtime configuration items in a
2825          * shared memory area.  The factory configured MAC
2826          * address is available from both NVRAM and the
2827          * shared memory area so we'll read the value from
2828          * shared memory for speed.
2829          */
2830
2831         mac_hi = REG_RD_IND(sc, sc->bce_shmem_base + BCE_PORT_HW_CFG_MAC_UPPER);
2832         mac_lo = REG_RD_IND(sc, sc->bce_shmem_base + BCE_PORT_HW_CFG_MAC_LOWER);
2833
2834         if (mac_lo == 0 && mac_hi == 0) {
2835                 if_printf(&sc->arpcom.ac_if, "Invalid Ethernet address!\n");
2836         } else {
2837                 sc->eaddr[0] = (u_char)(mac_hi >> 8);
2838                 sc->eaddr[1] = (u_char)(mac_hi >> 0);
2839                 sc->eaddr[2] = (u_char)(mac_lo >> 24);
2840                 sc->eaddr[3] = (u_char)(mac_lo >> 16);
2841                 sc->eaddr[4] = (u_char)(mac_lo >> 8);
2842                 sc->eaddr[5] = (u_char)(mac_lo >> 0);
2843         }
2844
2845         DBPRINT(sc, BCE_INFO, "Permanent Ethernet address = %6D\n", sc->eaddr, ":");
2846 }
2847
2848
2849 /****************************************************************************/
2850 /* Program the MAC address.                                                 */
2851 /*                                                                          */
2852 /* Returns:                                                                 */
2853 /*   Nothing.                                                               */
2854 /****************************************************************************/
2855 static void
2856 bce_set_mac_addr(struct bce_softc *sc)
2857 {
2858         const uint8_t *mac_addr = sc->eaddr;
2859         uint32_t val;
2860
2861         DBPRINT(sc, BCE_INFO, "Setting Ethernet address = %6D\n",
2862                 sc->eaddr, ":");
2863
2864         val = (mac_addr[0] << 8) | mac_addr[1];
2865         REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
2866
2867         val = (mac_addr[2] << 24) |
2868               (mac_addr[3] << 16) |
2869               (mac_addr[4] << 8) |
2870               mac_addr[5];
2871         REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
2872 }
2873
2874
2875 /****************************************************************************/
2876 /* Stop the controller.                                                     */
2877 /*                                                                          */
2878 /* Returns:                                                                 */
2879 /*   Nothing.                                                               */
2880 /****************************************************************************/
2881 static void
2882 bce_stop(struct bce_softc *sc)
2883 {
2884         struct ifnet *ifp = &sc->arpcom.ac_if;
2885         struct mii_data *mii = device_get_softc(sc->bce_miibus);
2886         struct ifmedia_entry *ifm;
2887         int mtmp, itmp;
2888
2889         ASSERT_SERIALIZED(ifp->if_serializer);
2890
2891         callout_stop(&sc->bce_stat_ch);
2892
2893         /* Disable the transmit/receive blocks. */
2894         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, 0x5ffffff);
2895         REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
2896         DELAY(20);
2897
2898         bce_disable_intr(sc);
2899
2900         /* Tell firmware that the driver is going away. */
2901         bce_reset(sc, BCE_DRV_MSG_CODE_SUSPEND_NO_WOL);
2902
2903         /* Free the RX lists. */
2904         bce_free_rx_chain(sc);
2905
2906         /* Free TX buffers. */
2907         bce_free_tx_chain(sc);
2908
2909         /*
2910          * Isolate/power down the PHY, but leave the media selection
2911          * unchanged so that things will be put back to normal when
2912          * we bring the interface back up.
2913          */
2914         itmp = ifp->if_flags;
2915         ifp->if_flags |= IFF_UP;
2916         ifm = mii->mii_media.ifm_cur;
2917         mtmp = ifm->ifm_media;
2918         ifm->ifm_media = IFM_ETHER | IFM_NONE;
2919         mii_mediachg(mii);
2920         ifm->ifm_media = mtmp;
2921         ifp->if_flags = itmp;
2922
2923         sc->bce_link = 0;
2924
2925         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2926         ifp->if_timer = 0;
2927
2928         bce_mgmt_init(sc);
2929 }
2930
2931
2932 static int
2933 bce_reset(struct bce_softc *sc, uint32_t reset_code)
2934 {
2935         uint32_t val;
2936         int i, rc = 0;
2937
2938         /* Wait for pending PCI transactions to complete. */
2939         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,
2940                BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
2941                BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
2942                BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
2943                BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
2944         val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
2945         DELAY(5);
2946
2947         /* Assume bootcode is running. */
2948         sc->bce_fw_timed_out = 0;
2949
2950         /* Give the firmware a chance to prepare for the reset. */
2951         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code);
2952         if (rc) {
2953                 if_printf(&sc->arpcom.ac_if,
2954                           "Firmware is not ready for reset\n");
2955                 return rc;
2956         }
2957
2958         /* Set a firmware reminder that this is a soft reset. */
2959         REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_RESET_SIGNATURE,
2960                    BCE_DRV_RESET_SIGNATURE_MAGIC);
2961
2962         /* Dummy read to force the chip to complete all current transactions. */
2963         val = REG_RD(sc, BCE_MISC_ID);
2964
2965         /* Chip reset. */
2966         val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
2967               BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
2968               BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
2969         REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
2970
2971         /* Allow up to 30us for reset to complete. */
2972         for (i = 0; i < 10; i++) {
2973                 val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG);
2974                 if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
2975                             BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
2976                         break;
2977                 }
2978                 DELAY(10);
2979         }
2980
2981         /* Check that reset completed successfully. */
2982         if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
2983                    BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
2984                 if_printf(&sc->arpcom.ac_if, "Reset failed!\n");
2985                 return EBUSY;
2986         }
2987
2988         /* Make sure byte swapping is properly configured. */
2989         val = REG_RD(sc, BCE_PCI_SWAP_DIAG0);
2990         if (val != 0x01020304) {
2991                 if_printf(&sc->arpcom.ac_if, "Byte swap is incorrect!\n");
2992                 return ENODEV;
2993         }
2994
2995         /* Just completed a reset, assume that firmware is running again. */
2996         sc->bce_fw_timed_out = 0;
2997
2998         /* Wait for the firmware to finish its initialization. */
2999         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code);
3000         if (rc) {
3001                 if_printf(&sc->arpcom.ac_if,
3002                           "Firmware did not complete initialization!\n");
3003         }
3004         return rc;
3005 }
3006
3007
3008 static int
3009 bce_chipinit(struct bce_softc *sc)
3010 {
3011         uint32_t val;
3012         int rc = 0;
3013
3014         /* Make sure the interrupt is not active. */
3015         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
3016
3017         /*
3018          * Initialize DMA byte/word swapping, configure the number of DMA
3019          * channels and PCI clock compensation delay.
3020          */
3021         val = BCE_DMA_CONFIG_DATA_BYTE_SWAP |
3022               BCE_DMA_CONFIG_DATA_WORD_SWAP |
3023 #if BYTE_ORDER == BIG_ENDIAN
3024               BCE_DMA_CONFIG_CNTL_BYTE_SWAP |
3025 #endif
3026               BCE_DMA_CONFIG_CNTL_WORD_SWAP |
3027               DMA_READ_CHANS << 12 |
3028               DMA_WRITE_CHANS << 16;
3029
3030         val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY;
3031
3032         if ((sc->bce_flags & BCE_PCIX_FLAG) && sc->bus_speed_mhz == 133)
3033                 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP;
3034
3035         /*
3036          * This setting resolves a problem observed on certain Intel PCI
3037          * chipsets that cannot handle multiple outstanding DMA operations.
3038          * See errata E9_5706A1_65.
3039          */
3040         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706 &&
3041             BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0 &&
3042             !(sc->bce_flags & BCE_PCIX_FLAG))
3043                 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA;
3044
3045         REG_WR(sc, BCE_DMA_CONFIG, val);
3046
3047         /* Clear the PCI-X relaxed ordering bit. See errata E3_5708CA0_570. */
3048         if (sc->bce_flags & BCE_PCIX_FLAG) {
3049                 uint16_t cmd;
3050
3051                 cmd = pci_read_config(sc->bce_dev, BCE_PCI_PCIX_CMD, 2);
3052                 pci_write_config(sc->bce_dev, BCE_PCI_PCIX_CMD, cmd & ~0x2, 2);
3053         }
3054
3055         /* Enable the RX_V2P and Context state machines before access. */
3056         REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3057                BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3058                BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3059                BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3060
3061         /* Initialize context mapping and zero out the quick contexts. */
3062         bce_init_context(sc);
3063
3064         /* Initialize the on-boards CPUs */
3065         bce_init_cpus(sc);
3066
3067         /* Prepare NVRAM for access. */
3068         rc = bce_init_nvram(sc);
3069         if (rc != 0)
3070                 return rc;
3071
3072         /* Set the kernel bypass block size */
3073         val = REG_RD(sc, BCE_MQ_CONFIG);
3074         val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3075         val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
3076         REG_WR(sc, BCE_MQ_CONFIG, val);
3077
3078         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
3079         REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);
3080         REG_WR(sc, BCE_MQ_KNL_WIND_END, val);
3081
3082         /* Set the page size and clear the RV2P processor stall bits. */
3083         val = (BCM_PAGE_BITS - 8) << 24;
3084         REG_WR(sc, BCE_RV2P_CONFIG, val);
3085
3086         /* Configure page size. */
3087         val = REG_RD(sc, BCE_TBDR_CONFIG);
3088         val &= ~BCE_TBDR_CONFIG_PAGE_SIZE;
3089         val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
3090         REG_WR(sc, BCE_TBDR_CONFIG, val);
3091
3092         return 0;
3093 }
3094
3095
3096 /****************************************************************************/
3097 /* Initialize the controller in preparation to send/receive traffic.        */
3098 /*                                                                          */
3099 /* Returns:                                                                 */
3100 /*   0 for success, positive value for failure.                             */
3101 /****************************************************************************/
3102 static int
3103 bce_blockinit(struct bce_softc *sc)
3104 {
3105         uint32_t reg, val;
3106         int rc = 0;
3107
3108         /* Load the hardware default MAC address. */
3109         bce_set_mac_addr(sc);
3110
3111         /* Set the Ethernet backoff seed value */
3112         val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) +
3113               sc->eaddr[3] + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16);
3114         REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val);
3115
3116         sc->last_status_idx = 0;
3117         sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE;
3118
3119         /* Set up link change interrupt generation. */
3120         REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK);
3121
3122         /* Program the physical address of the status block. */
3123         REG_WR(sc, BCE_HC_STATUS_ADDR_L, BCE_ADDR_LO(sc->status_block_paddr));
3124         REG_WR(sc, BCE_HC_STATUS_ADDR_H, BCE_ADDR_HI(sc->status_block_paddr));
3125
3126         /* Program the physical address of the statistics block. */
3127         REG_WR(sc, BCE_HC_STATISTICS_ADDR_L,
3128                BCE_ADDR_LO(sc->stats_block_paddr));
3129         REG_WR(sc, BCE_HC_STATISTICS_ADDR_H,
3130                BCE_ADDR_HI(sc->stats_block_paddr));
3131
3132         /* Program various host coalescing parameters. */
3133         REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
3134                (sc->bce_tx_quick_cons_trip_int << 16) |
3135                sc->bce_tx_quick_cons_trip);
3136         REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
3137                (sc->bce_rx_quick_cons_trip_int << 16) |
3138                sc->bce_rx_quick_cons_trip);
3139         REG_WR(sc, BCE_HC_COMP_PROD_TRIP,
3140                (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip);
3141         REG_WR(sc, BCE_HC_TX_TICKS,
3142                (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
3143         REG_WR(sc, BCE_HC_RX_TICKS,
3144                (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
3145         REG_WR(sc, BCE_HC_COM_TICKS,
3146                (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks);
3147         REG_WR(sc, BCE_HC_CMD_TICKS,
3148                (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks);
3149         REG_WR(sc, BCE_HC_STATS_TICKS, (sc->bce_stats_ticks & 0xffff00));
3150         REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8);   /* 3ms */
3151         REG_WR(sc, BCE_HC_CONFIG,
3152                BCE_HC_CONFIG_RX_TMR_MODE |
3153                BCE_HC_CONFIG_TX_TMR_MODE |
3154                BCE_HC_CONFIG_COLLECT_STATS);
3155
3156         /* Clear the internal statistics counters. */
3157         REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
3158
3159         /* Verify that bootcode is running. */
3160         reg = REG_RD_IND(sc, sc->bce_shmem_base + BCE_DEV_INFO_SIGNATURE);
3161
3162         DBRUNIF(DB_RANDOMTRUE(bce_debug_bootcode_running_failure),
3163                 if_printf(&sc->arpcom.ac_if,
3164                           "%s(%d): Simulating bootcode failure.\n",
3165                           __FILE__, __LINE__);
3166                 reg = 0);
3167
3168         if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
3169             BCE_DEV_INFO_SIGNATURE_MAGIC) {
3170                 if_printf(&sc->arpcom.ac_if,
3171                           "Bootcode not running! Found: 0x%08X, "
3172                           "Expected: 08%08X\n",
3173                           reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK,
3174                           BCE_DEV_INFO_SIGNATURE_MAGIC);
3175                 return ENODEV;
3176         }
3177
3178         /* Check if any management firmware is running. */
3179         reg = REG_RD_IND(sc, sc->bce_shmem_base + BCE_PORT_FEATURE);
3180         if (reg & (BCE_PORT_FEATURE_ASF_ENABLED |
3181                    BCE_PORT_FEATURE_IMD_ENABLED)) {
3182                 DBPRINT(sc, BCE_INFO, "Management F/W Enabled.\n");
3183                 sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
3184         }
3185
3186         sc->bce_fw_ver =
3187                 REG_RD_IND(sc, sc->bce_shmem_base + BCE_DEV_INFO_BC_REV);
3188         DBPRINT(sc, BCE_INFO, "bootcode rev = 0x%08X\n", sc->bce_fw_ver);
3189
3190         /* Allow bootcode to apply any additional fixes before enabling MAC. */
3191         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | BCE_DRV_MSG_CODE_RESET);
3192
3193         /* Enable link state change interrupt generation. */
3194         REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
3195
3196         /* Enable all remaining blocks in the MAC. */
3197         REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 0x5ffffff);
3198         REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
3199         DELAY(20);
3200
3201         return 0;
3202 }
3203
3204
3205 /****************************************************************************/
3206 /* Encapsulate an mbuf cluster into the rx_bd chain.                        */
3207 /*                                                                          */
3208 /* The NetXtreme II can support Jumbo frames by using multiple rx_bd's.     */
3209 /* This routine will map an mbuf cluster into 1 or more rx_bd's as          */
3210 /* necessary.                                                               */
3211 /*                                                                          */
3212 /* Returns:                                                                 */
3213 /*   0 for success, positive value for failure.                             */
3214 /****************************************************************************/
3215 static int
3216 bce_newbuf_std(struct bce_softc *sc, struct mbuf *m,
3217                uint16_t *prod, uint16_t *chain_prod, uint32_t *prod_bseq)
3218 {
3219         bus_dmamap_t map;
3220         struct bce_dmamap_arg ctx;
3221         bus_dma_segment_t seg;
3222         struct mbuf *m_new;
3223         struct rx_bd *rxbd;
3224         int error;
3225 #ifdef BCE_DEBUG
3226         uint16_t debug_chain_prod = *chain_prod;
3227 #endif
3228
3229         /* Make sure the inputs are valid. */
3230         DBRUNIF((*chain_prod > MAX_RX_BD),
3231                 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3232                           "RX producer out of range: 0x%04X > 0x%04X\n",
3233                           __FILE__, __LINE__,
3234                           *chain_prod, (uint16_t)MAX_RX_BD));
3235
3236         DBPRINT(sc, BCE_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = 0x%04X, "
3237                 "prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, *prod_bseq);
3238
3239         if (m == NULL) {
3240                 DBRUNIF(DB_RANDOMTRUE(bce_debug_mbuf_allocation_failure),
3241                         if_printf(&sc->arpcom.ac_if, "%s(%d): "
3242                                   "Simulating mbuf allocation failure.\n",
3243                                   __FILE__, __LINE__);
3244                         sc->mbuf_alloc_failed++;
3245                         return ENOBUFS);
3246
3247                 /* This is a new mbuf allocation. */
3248                 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
3249                 if (m_new == NULL)
3250                         return ENOBUFS;
3251                 DBRUNIF(1, sc->rx_mbuf_alloc++);
3252         } else {
3253                 m_new = m;
3254                 m_new->m_data = m_new->m_ext.ext_buf;
3255         }
3256         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
3257
3258         /* Map the mbuf cluster into device memory. */
3259         map = sc->rx_mbuf_map[*chain_prod];
3260
3261         ctx.bce_maxsegs = 1;
3262         ctx.bce_segs = &seg;
3263         error = bus_dmamap_load_mbuf(sc->rx_mbuf_tag, map, m_new,
3264                                      bce_dma_map_mbuf, &ctx, BUS_DMA_NOWAIT);
3265         if (error || ctx.bce_maxsegs == 0) {
3266                 if_printf(&sc->arpcom.ac_if,
3267                           "Error mapping mbuf into RX chain!\n");
3268
3269                 if (m == NULL)
3270                         m_freem(m_new);
3271
3272                 DBRUNIF(1, sc->rx_mbuf_alloc--);
3273                 return ENOBUFS;
3274         }
3275
3276         /* Watch for overflow. */
3277         DBRUNIF((sc->free_rx_bd > USABLE_RX_BD),
3278                 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3279                           "Too many free rx_bd (0x%04X > 0x%04X)!\n",
3280                           __FILE__, __LINE__, sc->free_rx_bd,
3281                           (uint16_t)USABLE_RX_BD));
3282
3283         /* Update some debug statistic counters */
3284         DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
3285                 sc->rx_low_watermark = sc->free_rx_bd);
3286         DBRUNIF((sc->free_rx_bd == 0), sc->rx_empty_count++);
3287
3288         /* Setup the rx_bd for the first segment. */
3289         rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)];
3290
3291         rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(seg.ds_addr));
3292         rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(seg.ds_addr));
3293         rxbd->rx_bd_len = htole32(seg.ds_len);
3294         rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START);
3295         *prod_bseq += seg.ds_len;
3296
3297         rxbd->rx_bd_flags |= htole32(RX_BD_FLAGS_END);
3298
3299         /* Save the mbuf and update our counter. */
3300         sc->rx_mbuf_ptr[*chain_prod] = m_new;
3301         sc->free_rx_bd--;
3302
3303         DBRUN(BCE_VERBOSE_RECV,
3304               bce_dump_rx_mbuf_chain(sc, debug_chain_prod, 1));
3305
3306         DBPRINT(sc, BCE_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod = 0x%04X, "
3307                 "prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, *prod_bseq);
3308
3309         return 0;
3310 }
3311
3312
3313 /****************************************************************************/
3314 /* Allocate memory and initialize the TX data structures.                   */
3315 /*                                                                          */
3316 /* Returns:                                                                 */
3317 /*   0 for success, positive value for failure.                             */
3318 /****************************************************************************/
3319 static int
3320 bce_init_tx_chain(struct bce_softc *sc)
3321 {
3322         struct tx_bd *txbd;
3323         uint32_t val;
3324         int i, rc = 0;
3325
3326         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
3327
3328         /* Set the initial TX producer/consumer indices. */
3329         sc->tx_prod = 0;
3330         sc->tx_cons = 0;
3331         sc->tx_prod_bseq   = 0;
3332         sc->used_tx_bd = 0;
3333         sc->max_tx_bd = USABLE_TX_BD;
3334         DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD);
3335         DBRUNIF(1, sc->tx_full_count = 0);
3336
3337         /*
3338          * The NetXtreme II supports a linked-list structre called
3339          * a Buffer Descriptor Chain (or BD chain).  A BD chain
3340          * consists of a series of 1 or more chain pages, each of which
3341          * consists of a fixed number of BD entries.
3342          * The last BD entry on each page is a pointer to the next page
3343          * in the chain, and the last pointer in the BD chain
3344          * points back to the beginning of the chain.
3345          */
3346
3347         /* Set the TX next pointer chain entries. */
3348         for (i = 0; i < TX_PAGES; i++) {
3349                 int j;
3350
3351                 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE];
3352
3353                 /* Check if we've reached the last page. */
3354                 if (i == (TX_PAGES - 1))
3355                         j = 0;
3356                 else
3357                         j = i + 1;
3358
3359                 txbd->tx_bd_haddr_hi =
3360                         htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j]));
3361                 txbd->tx_bd_haddr_lo =
3362                         htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j]));
3363         }
3364
3365         for (i = 0; i < TX_PAGES; ++i) {
3366                 bus_dmamap_sync(sc->tx_bd_chain_tag, sc->tx_bd_chain_map[i],
3367                                 BUS_DMASYNC_PREWRITE);
3368         }
3369
3370         /* Initialize the context ID for an L2 TX chain. */
3371         val = BCE_L2CTX_TYPE_TYPE_L2;
3372         val |= BCE_L2CTX_TYPE_SIZE_L2;
3373         CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TYPE, val);
3374
3375         val = BCE_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
3376         CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_CMD_TYPE, val);
3377
3378         /* Point the hardware to the first page in the chain. */
3379         val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
3380         CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TBDR_BHADDR_HI, val);
3381         val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
3382         CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TBDR_BHADDR_LO, val);
3383
3384         DBRUN(BCE_VERBOSE_SEND, bce_dump_tx_chain(sc, 0, TOTAL_TX_BD));
3385
3386         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
3387
3388         return(rc);
3389 }
3390
3391
3392 /****************************************************************************/
3393 /* Free memory and clear the TX data structures.                            */
3394 /*                                                                          */
3395 /* Returns:                                                                 */
3396 /*   Nothing.                                                               */
3397 /****************************************************************************/
3398 static void
3399 bce_free_tx_chain(struct bce_softc *sc)
3400 {
3401         int i;
3402
3403         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
3404
3405         /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */
3406         for (i = 0; i < TOTAL_TX_BD; i++) {
3407                 if (sc->tx_mbuf_ptr[i] != NULL) {
3408                         bus_dmamap_sync(sc->tx_mbuf_tag, sc->tx_mbuf_map[i],
3409                                         BUS_DMASYNC_POSTWRITE);
3410                         bus_dmamap_unload(sc->tx_mbuf_tag, sc->tx_mbuf_map[i]);
3411                         m_freem(sc->tx_mbuf_ptr[i]);
3412                         sc->tx_mbuf_ptr[i] = NULL;
3413                         DBRUNIF(1, sc->tx_mbuf_alloc--);
3414                 }
3415         }
3416
3417         /* Clear each TX chain page. */
3418         for (i = 0; i < TX_PAGES; i++)
3419                 bzero(sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ);
3420
3421         /* Check if we lost any mbufs in the process. */
3422         DBRUNIF((sc->tx_mbuf_alloc),
3423                 if_printf(&sc->arpcom.ac_if,
3424                           "%s(%d): Memory leak! "
3425                           "Lost %d mbufs from tx chain!\n",
3426                           __FILE__, __LINE__, sc->tx_mbuf_alloc));
3427
3428         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
3429 }
3430
3431
3432 /****************************************************************************/
3433 /* Allocate memory and initialize the RX data structures.                   */
3434 /*                                                                          */
3435 /* Returns:                                                                 */
3436 /*   0 for success, positive value for failure.                             */
3437 /****************************************************************************/
3438 static int
3439 bce_init_rx_chain(struct bce_softc *sc)
3440 {
3441         struct rx_bd *rxbd;
3442         int i, rc = 0;
3443         uint16_t prod, chain_prod;
3444         uint32_t prod_bseq, val;
3445
3446         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
3447
3448         /* Initialize the RX producer and consumer indices. */
3449         sc->rx_prod = 0;
3450         sc->rx_cons = 0;
3451         sc->rx_prod_bseq = 0;
3452         sc->free_rx_bd = USABLE_RX_BD;
3453         sc->max_rx_bd = USABLE_RX_BD;
3454         DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD);
3455         DBRUNIF(1, sc->rx_empty_count = 0);
3456
3457         /* Initialize the RX next pointer chain entries. */
3458         for (i = 0; i < RX_PAGES; i++) {
3459                 int j;
3460
3461                 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE];
3462
3463                 /* Check if we've reached the last page. */
3464                 if (i == (RX_PAGES - 1))
3465                         j = 0;
3466                 else
3467                         j = i + 1;
3468
3469                 /* Setup the chain page pointers. */
3470                 rxbd->rx_bd_haddr_hi =
3471                         htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j]));
3472                 rxbd->rx_bd_haddr_lo =
3473                         htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j]));
3474         }
3475
3476         /* Initialize the context ID for an L2 RX chain. */
3477         val = BCE_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
3478         val |= BCE_L2CTX_CTX_TYPE_SIZE_L2;
3479         val |= 0x02 << 8;
3480         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_CTX_TYPE, val);
3481
3482         /* Point the hardware to the first page in the chain. */
3483         /* XXX shouldn't this after RX descriptor initialization? */
3484         val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]);
3485         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_NX_BDHADDR_HI, val);
3486         val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]);
3487         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_NX_BDHADDR_LO, val);
3488
3489         /* Allocate mbuf clusters for the rx_bd chain. */
3490         prod = prod_bseq = 0;
3491         while (prod < TOTAL_RX_BD) {
3492                 chain_prod = RX_CHAIN_IDX(prod);
3493                 if (bce_newbuf_std(sc, NULL, &prod, &chain_prod, &prod_bseq)) {
3494                         if_printf(&sc->arpcom.ac_if,
3495                                   "Error filling RX chain: rx_bd[0x%04X]!\n",
3496                                   chain_prod);
3497                         rc = ENOBUFS;
3498                         break;
3499                 }
3500                 prod = NEXT_RX_BD(prod);
3501         }
3502
3503         /* Save the RX chain producer index. */
3504         sc->rx_prod = prod;
3505         sc->rx_prod_bseq = prod_bseq;
3506
3507         for (i = 0; i < RX_PAGES; i++) {
3508                 bus_dmamap_sync(sc->rx_bd_chain_tag, sc->rx_bd_chain_map[i],
3509                                 BUS_DMASYNC_PREWRITE);
3510         }
3511
3512         /* Tell the chip about the waiting rx_bd's. */
3513         REG_WR16(sc, MB_RX_CID_ADDR + BCE_L2CTX_HOST_BDIDX, sc->rx_prod);
3514         REG_WR(sc, MB_RX_CID_ADDR + BCE_L2CTX_HOST_BSEQ, sc->rx_prod_bseq);
3515
3516         DBRUN(BCE_VERBOSE_RECV, bce_dump_rx_chain(sc, 0, TOTAL_RX_BD));
3517
3518         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
3519
3520         return(rc);
3521 }
3522
3523
3524 /****************************************************************************/
3525 /* Free memory and clear the RX data structures.                            */
3526 /*                                                                          */
3527 /* Returns:                                                                 */
3528 /*   Nothing.                                                               */
3529 /****************************************************************************/
3530 static void
3531 bce_free_rx_chain(struct bce_softc *sc)
3532 {
3533         int i;
3534
3535         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
3536
3537         /* Free any mbufs still in the RX mbuf chain. */
3538         for (i = 0; i < TOTAL_RX_BD; i++) {
3539                 if (sc->rx_mbuf_ptr[i] != NULL) {
3540                         bus_dmamap_sync(sc->rx_mbuf_tag, sc->rx_mbuf_map[i],
3541                                         BUS_DMASYNC_POSTREAD);
3542                         bus_dmamap_unload(sc->rx_mbuf_tag, sc->rx_mbuf_map[i]);
3543                         m_freem(sc->rx_mbuf_ptr[i]);
3544                         sc->rx_mbuf_ptr[i] = NULL;
3545                         DBRUNIF(1, sc->rx_mbuf_alloc--);
3546                 }
3547         }
3548
3549         /* Clear each RX chain page. */
3550         for (i = 0; i < RX_PAGES; i++)
3551                 bzero(sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ);
3552
3553         /* Check if we lost any mbufs in the process. */
3554         DBRUNIF((sc->rx_mbuf_alloc),
3555                 if_printf(&sc->arpcom.ac_if,
3556                           "%s(%d): Memory leak! "
3557                           "Lost %d mbufs from rx chain!\n",
3558                           __FILE__, __LINE__, sc->rx_mbuf_alloc));
3559
3560         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
3561 }
3562
3563
3564 /****************************************************************************/
3565 /* Set media options.                                                       */
3566 /*                                                                          */
3567 /* Returns:                                                                 */
3568 /*   0 for success, positive value for failure.                             */
3569 /****************************************************************************/
3570 static int
3571 bce_ifmedia_upd(struct ifnet *ifp)
3572 {
3573         struct bce_softc *sc = ifp->if_softc;
3574         struct mii_data *mii = device_get_softc(sc->bce_miibus);
3575
3576         /*
3577          * 'mii' will be NULL, when this function is called on following
3578          * code path: bce_attach() -> bce_mgmt_init()
3579          */
3580         if (mii != NULL) {
3581                 /* Make sure the MII bus has been enumerated. */
3582                 sc->bce_link = 0;
3583                 if (mii->mii_instance) {
3584                         struct mii_softc *miisc;
3585
3586                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3587                                 mii_phy_reset(miisc);
3588                 }
3589                 mii_mediachg(mii);
3590         }
3591         return 0;
3592 }
3593
3594
3595 /****************************************************************************/
3596 /* Reports current media status.                                            */
3597 /*                                                                          */
3598 /* Returns:                                                                 */
3599 /*   Nothing.                                                               */
3600 /****************************************************************************/
3601 static void
3602 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3603 {
3604         struct bce_softc *sc = ifp->if_softc;
3605         struct mii_data *mii = device_get_softc(sc->bce_miibus);
3606
3607         mii_pollstat(mii);
3608         ifmr->ifm_active = mii->mii_media_active;
3609         ifmr->ifm_status = mii->mii_media_status;
3610 }
3611
3612
3613 /****************************************************************************/
3614 /* Handles PHY generated interrupt events.                                  */
3615 /*                                                                          */
3616 /* Returns:                                                                 */
3617 /*   Nothing.                                                               */
3618 /****************************************************************************/
3619 static void
3620 bce_phy_intr(struct bce_softc *sc)
3621 {
3622         uint32_t new_link_state, old_link_state;
3623         struct ifnet *ifp = &sc->arpcom.ac_if;
3624
3625         ASSERT_SERIALIZED(ifp->if_serializer);
3626
3627         new_link_state = sc->status_block->status_attn_bits &
3628                          STATUS_ATTN_BITS_LINK_STATE;
3629         old_link_state = sc->status_block->status_attn_bits_ack &
3630                          STATUS_ATTN_BITS_LINK_STATE;
3631
3632         /* Handle any changes if the link state has changed. */
3633         if (new_link_state != old_link_state) { /* XXX redundant? */
3634                 DBRUN(BCE_VERBOSE_INTR, bce_dump_status_block(sc));
3635
3636                 sc->bce_link = 0;
3637                 callout_stop(&sc->bce_stat_ch);
3638                 bce_tick_serialized(sc);
3639
3640                 /* Update the status_attn_bits_ack field in the status block. */
3641                 if (new_link_state) {
3642                         REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD,
3643                                STATUS_ATTN_BITS_LINK_STATE);
3644                         if (bootverbose)
3645                                 if_printf(ifp, "Link is now UP.\n");
3646                 } else {
3647                         REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD,
3648                                STATUS_ATTN_BITS_LINK_STATE);
3649                         if (bootverbose)
3650                                 if_printf(ifp, "Link is now DOWN.\n");
3651                 }
3652         }
3653
3654         /* Acknowledge the link change interrupt. */
3655         REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE);
3656 }
3657
3658
3659 /****************************************************************************/
3660 /* Handles received frame interrupt events.                                 */
3661 /*                                                                          */
3662 /* Returns:                                                                 */
3663 /*   Nothing.                                                               */
3664 /****************************************************************************/
3665 static void
3666 bce_rx_intr(struct bce_softc *sc, int count)
3667 {
3668         struct status_block *sblk = sc->status_block;
3669         struct ifnet *ifp = &sc->arpcom.ac_if;
3670         uint16_t hw_cons, sw_cons, sw_chain_cons, sw_prod, sw_chain_prod;
3671         uint32_t sw_prod_bseq;
3672         int i;
3673
3674         ASSERT_SERIALIZED(ifp->if_serializer);
3675
3676         DBRUNIF(1, sc->rx_interrupts++);
3677
3678         /* Prepare the RX chain pages to be accessed by the host CPU. */
3679         for (i = 0; i < RX_PAGES; i++) {
3680                 bus_dmamap_sync(sc->rx_bd_chain_tag,
3681                                 sc->rx_bd_chain_map[i], BUS_DMASYNC_POSTREAD);
3682         }
3683
3684         /* Get the hardware's view of the RX consumer index. */
3685         hw_cons = sc->hw_rx_cons = sblk->status_rx_quick_consumer_index0;
3686         if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
3687                 hw_cons++;
3688
3689         /* Get working copies of the driver's view of the RX indices. */
3690         sw_cons = sc->rx_cons;
3691         sw_prod = sc->rx_prod;
3692         sw_prod_bseq = sc->rx_prod_bseq;
3693
3694         DBPRINT(sc, BCE_INFO_RECV, "%s(enter): sw_prod = 0x%04X, "
3695                 "sw_cons = 0x%04X, sw_prod_bseq = 0x%08X\n",
3696                 __func__, sw_prod, sw_cons, sw_prod_bseq);
3697
3698         /* Prevent speculative reads from getting ahead of the status block. */
3699         bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
3700                           BUS_SPACE_BARRIER_READ);
3701
3702         /* Update some debug statistics counters */
3703         DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
3704                 sc->rx_low_watermark = sc->free_rx_bd);
3705         DBRUNIF((sc->free_rx_bd == 0), sc->rx_empty_count++);
3706
3707         /* Scan through the receive chain as long as there is work to do. */
3708         while (sw_cons != hw_cons) {
3709                 struct mbuf *m = NULL;
3710                 struct l2_fhdr *l2fhdr = NULL;
3711                 struct rx_bd *rxbd;
3712                 unsigned int len;
3713                 uint32_t status = 0;
3714
3715 #ifdef foo /* DEVICE_POLLING */
3716                 /*
3717                  * Even if polling(4) is enabled, we can't just reap
3718                  * 'count' RX descriptors and leave.  It seems that RX
3719                  * engine would be left in a wired state, if we broke
3720                  * out the loop in the middle.
3721                  */
3722                 if (count >= 0 && count-- == 0)
3723                         break;
3724 #endif
3725
3726                 /*
3727                  * Convert the producer/consumer indices
3728                  * to an actual rx_bd index.
3729                  */
3730                 sw_chain_cons = RX_CHAIN_IDX(sw_cons);
3731                 sw_chain_prod = RX_CHAIN_IDX(sw_prod);
3732
3733                 /* Get the used rx_bd. */
3734                 rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)]
3735                                        [RX_IDX(sw_chain_cons)];
3736                 sc->free_rx_bd++;
3737
3738                 DBRUN(BCE_VERBOSE_RECV,
3739                       if_printf(ifp, "%s(): ", __func__);
3740                       bce_dump_rxbd(sc, sw_chain_cons, rxbd));
3741
3742                 /* The mbuf is stored with the last rx_bd entry of a packet. */
3743                 if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) {
3744                         /* Validate that this is the last rx_bd. */
3745                         DBRUNIF((!(rxbd->rx_bd_flags & RX_BD_FLAGS_END)),
3746                                 if_printf(ifp, "%s(%d): "
3747                                 "Unexpected mbuf found in rx_bd[0x%04X]!\n",
3748                                 __FILE__, __LINE__, sw_chain_cons);
3749                                 bce_breakpoint(sc));
3750
3751                         /*
3752                          * ToDo: If the received packet is small enough
3753                          * to fit into a single, non-M_EXT mbuf,
3754                          * allocate a new mbuf here, copy the data to
3755                          * that mbuf, and recycle the mapped jumbo frame.
3756                          */
3757
3758                         /* Unmap the mbuf from DMA space. */
3759                         bus_dmamap_sync(sc->rx_mbuf_tag,
3760                                         sc->rx_mbuf_map[sw_chain_cons],
3761                                         BUS_DMASYNC_POSTREAD);
3762                         bus_dmamap_unload(sc->rx_mbuf_tag,
3763                                           sc->rx_mbuf_map[sw_chain_cons]);
3764
3765                         /* Remove the mbuf from the driver's chain. */
3766                         m = sc->rx_mbuf_ptr[sw_chain_cons];
3767                         sc->rx_mbuf_ptr[sw_chain_cons] = NULL;
3768
3769                         /*
3770                          * Frames received on the NetXteme II are prepended
3771                          * with an l2_fhdr structure which provides status
3772                          * information about the received frame (including
3773                          * VLAN tags and checksum info).  The frames are also
3774                          * automatically adjusted to align the IP header
3775                          * (i.e. two null bytes are inserted before the
3776                          * Ethernet header).
3777                          */
3778                         l2fhdr = mtod(m, struct l2_fhdr *);
3779
3780                         len = l2fhdr->l2_fhdr_pkt_len;
3781                         status = l2fhdr->l2_fhdr_status;
3782
3783                         DBRUNIF(DB_RANDOMTRUE(bce_debug_l2fhdr_status_check),
3784                                 if_printf(ifp,
3785                                 "Simulating l2_fhdr status error.\n");
3786                                 status = status | L2_FHDR_ERRORS_PHY_DECODE);
3787
3788                         /* Watch for unusual sized frames. */
3789                         DBRUNIF((len < BCE_MIN_MTU ||
3790                                  len > BCE_MAX_JUMBO_ETHER_MTU_VLAN),
3791                                 if_printf(ifp,
3792                                 "%s(%d): Unusual frame size found. "
3793                                 "Min(%d), Actual(%d), Max(%d)\n",
3794                                 __FILE__, __LINE__,
3795                                 (int)BCE_MIN_MTU, len,
3796                                 (int)BCE_MAX_JUMBO_ETHER_MTU_VLAN);
3797                                 bce_dump_mbuf(sc, m);
3798                                 bce_breakpoint(sc));
3799
3800                         len -= ETHER_CRC_LEN;
3801
3802                         /* Check the received frame for errors. */
3803                         if (status & (L2_FHDR_ERRORS_BAD_CRC |
3804                                       L2_FHDR_ERRORS_PHY_DECODE |
3805                                       L2_FHDR_ERRORS_ALIGNMENT |
3806                                       L2_FHDR_ERRORS_TOO_SHORT |
3807                                       L2_FHDR_ERRORS_GIANT_FRAME)) {
3808                                 ifp->if_ierrors++;
3809                                 DBRUNIF(1, sc->l2fhdr_status_errors++);
3810
3811                                 /* Reuse the mbuf for a new frame. */
3812                                 if (bce_newbuf_std(sc, m, &sw_prod,
3813                                                    &sw_chain_prod,
3814                                                    &sw_prod_bseq)) {
3815                                         DBRUNIF(1, bce_breakpoint(sc));
3816                                         /* XXX */
3817                                         panic("%s: Can't reuse RX mbuf!\n",
3818                                               ifp->if_xname);
3819                                 }
3820                                 m = NULL;
3821                                 goto bce_rx_int_next_rx;
3822                         }
3823
3824                         /*
3825                          * Get a new mbuf for the rx_bd.   If no new
3826                          * mbufs are available then reuse the current mbuf,
3827                          * log an ierror on the interface, and generate
3828                          * an error in the system log.
3829                          */
3830                         if (bce_newbuf_std(sc, NULL, &sw_prod, &sw_chain_prod,
3831                                            &sw_prod_bseq)) {
3832                                 DBRUN(BCE_WARN,
3833                                       if_printf(ifp,
3834                                       "%s(%d): Failed to allocate new mbuf, "
3835                                       "incoming frame dropped!\n",
3836                                       __FILE__, __LINE__));
3837
3838                                 ifp->if_ierrors++;
3839
3840                                 /* Try and reuse the exisitng mbuf. */
3841                                 if (bce_newbuf_std(sc, m, &sw_prod,
3842                                                    &sw_chain_prod,
3843                                                    &sw_prod_bseq)) {
3844                                         DBRUNIF(1, bce_breakpoint(sc));
3845                                         /* XXX */
3846                                         panic("%s: Double mbuf allocation "
3847                                               "failure!", ifp->if_xname);
3848                                 }
3849                                 m = NULL;
3850                                 goto bce_rx_int_next_rx;
3851                         }
3852
3853                         /*
3854                          * Skip over the l2_fhdr when passing
3855                          * the data up the stack.
3856                          */
3857                         m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN);
3858
3859                         m->m_pkthdr.len = m->m_len = len;
3860                         m->m_pkthdr.rcvif = ifp;
3861
3862                         DBRUN(BCE_VERBOSE_RECV,
3863                               struct ether_header *eh;
3864                               eh = mtod(m, struct ether_header *);
3865                               if_printf(ifp, "%s(): to: %6D, from: %6D, "
3866                                         "type: 0x%04X\n", __func__,
3867                                         eh->ether_dhost, ":",
3868                                         eh->ether_shost, ":",
3869                                         htons(eh->ether_type)));
3870
3871                         /* Validate the checksum if offload enabled. */
3872                         if (ifp->if_capenable & IFCAP_RXCSUM) {
3873                                 /* Check for an IP datagram. */
3874                                 if (status & L2_FHDR_STATUS_IP_DATAGRAM) {
3875                                         m->m_pkthdr.csum_flags |=
3876                                                 CSUM_IP_CHECKED;
3877
3878                                         /* Check if the IP checksum is valid. */
3879                                         if ((l2fhdr->l2_fhdr_ip_xsum ^
3880                                              0xffff) == 0) {
3881                                                 m->m_pkthdr.csum_flags |=
3882                                                         CSUM_IP_VALID;
3883                                         } else {
3884                                                 DBPRINT(sc, BCE_WARN_RECV,
3885                                                         "%s(): Invalid IP checksum = 0x%04X!\n",
3886                                                         __func__, l2fhdr->l2_fhdr_ip_xsum);
3887                                         }
3888                                 }
3889
3890                                 /* Check for a valid TCP/UDP frame. */
3891                                 if (status & (L2_FHDR_STATUS_TCP_SEGMENT |
3892                                               L2_FHDR_STATUS_UDP_DATAGRAM)) {
3893
3894                                         /* Check for a good TCP/UDP checksum. */
3895                                         if ((status &
3896                                              (L2_FHDR_ERRORS_TCP_XSUM |
3897                                               L2_FHDR_ERRORS_UDP_XSUM)) == 0) {
3898                                                 m->m_pkthdr.csum_data =
3899                                                 l2fhdr->l2_fhdr_tcp_udp_xsum;
3900                                                 m->m_pkthdr.csum_flags |=
3901                                                         CSUM_DATA_VALID |
3902                                                         CSUM_PSEUDO_HDR;
3903                                         } else {
3904                                                 DBPRINT(sc, BCE_WARN_RECV,
3905                                                         "%s(): Invalid TCP/UDP checksum = 0x%04X!\n",
3906                                                         __func__, l2fhdr->l2_fhdr_tcp_udp_xsum);
3907                                         }
3908                                 }
3909                         }
3910
3911                         ifp->if_ipackets++;
3912 bce_rx_int_next_rx:
3913                         sw_prod = NEXT_RX_BD(sw_prod);
3914                 }
3915
3916                 sw_cons = NEXT_RX_BD(sw_cons);
3917
3918                 /* If we have a packet, pass it up the stack */
3919                 if (m) {
3920                         DBPRINT(sc, BCE_VERBOSE_RECV,
3921                                 "%s(): Passing received frame up.\n", __func__);
3922
3923                         if (status & L2_FHDR_STATUS_L2_VLAN_TAG)
3924                                 VLAN_INPUT_TAG(m, l2fhdr->l2_fhdr_vlan_tag);
3925                         else
3926                                 ifp->if_input(ifp, m);
3927
3928                         DBRUNIF(1, sc->rx_mbuf_alloc--);
3929                 }
3930
3931                 /*
3932                  * If polling(4) is not enabled, refresh hw_cons to see
3933                  * whether there's new work.
3934                  *
3935                  * If polling(4) is enabled, i.e count >= 0, refreshing
3936                  * should not be performed, so that we would not spend
3937                  * too much time in RX processing.
3938                  */
3939                 if (count < 0 && sw_cons == hw_cons) {
3940                         hw_cons = sc->hw_rx_cons =
3941                                 sblk->status_rx_quick_consumer_index0;
3942                         if ((hw_cons & USABLE_RX_BD_PER_PAGE) ==
3943                             USABLE_RX_BD_PER_PAGE)
3944                                 hw_cons++;
3945                 }
3946
3947                 /*
3948                  * Prevent speculative reads from getting ahead
3949                  * of the status block.
3950                  */
3951                 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
3952                                   BUS_SPACE_BARRIER_READ);
3953         }
3954
3955         for (i = 0; i < RX_PAGES; i++) {
3956                 bus_dmamap_sync(sc->rx_bd_chain_tag,
3957                                 sc->rx_bd_chain_map[i], BUS_DMASYNC_PREWRITE);
3958         }
3959
3960         sc->rx_cons = sw_cons;
3961         sc->rx_prod = sw_prod;
3962         sc->rx_prod_bseq = sw_prod_bseq;
3963
3964         REG_WR16(sc, MB_RX_CID_ADDR + BCE_L2CTX_HOST_BDIDX, sc->rx_prod);
3965         REG_WR(sc, MB_RX_CID_ADDR + BCE_L2CTX_HOST_BSEQ, sc->rx_prod_bseq);
3966
3967         DBPRINT(sc, BCE_INFO_RECV, "%s(exit): rx_prod = 0x%04X, "
3968                 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
3969                 __func__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
3970 }
3971
3972
3973 /****************************************************************************/
3974 /* Handles transmit completion interrupt events.                            */
3975 /*                                                                          */
3976 /* Returns:                                                                 */
3977 /*   Nothing.                                                               */
3978 /****************************************************************************/
3979 static void
3980 bce_tx_intr(struct bce_softc *sc)
3981 {
3982         struct status_block *sblk = sc->status_block;
3983         struct ifnet *ifp = &sc->arpcom.ac_if;
3984         uint16_t hw_tx_cons, sw_tx_cons, sw_tx_chain_cons;
3985
3986         ASSERT_SERIALIZED(ifp->if_serializer);
3987
3988         DBRUNIF(1, sc->tx_interrupts++);
3989
3990         /* Get the hardware's view of the TX consumer index. */
3991         hw_tx_cons = sc->hw_tx_cons = sblk->status_tx_quick_consumer_index0;
3992
3993         /* Skip to the next entry if this is a chain page pointer. */
3994         if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
3995                 hw_tx_cons++;
3996
3997         sw_tx_cons = sc->tx_cons;
3998
3999         /* Prevent speculative reads from getting ahead of the status block. */
4000         bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4001                           BUS_SPACE_BARRIER_READ);
4002
4003         /* Cycle through any completed TX chain page entries. */
4004         while (sw_tx_cons != hw_tx_cons) {
4005 #ifdef BCE_DEBUG
4006                 struct tx_bd *txbd = NULL;
4007 #endif
4008                 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons);
4009
4010                 DBPRINT(sc, BCE_INFO_SEND,
4011                         "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, "
4012                         "sw_tx_chain_cons = 0x%04X\n",
4013                         __func__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons);
4014
4015                 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD),
4016                         if_printf(ifp, "%s(%d): "
4017                                   "TX chain consumer out of range! "
4018                                   " 0x%04X > 0x%04X\n",
4019                                   __FILE__, __LINE__, sw_tx_chain_cons,
4020                                   (int)MAX_TX_BD);
4021                         bce_breakpoint(sc));
4022
4023                 DBRUNIF(1, txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)]
4024                                 [TX_IDX(sw_tx_chain_cons)]);
4025
4026                 DBRUNIF((txbd == NULL),
4027                         if_printf(ifp, "%s(%d): "
4028                                   "Unexpected NULL tx_bd[0x%04X]!\n",
4029                                   __FILE__, __LINE__, sw_tx_chain_cons);
4030                         bce_breakpoint(sc));
4031
4032                 DBRUN(BCE_INFO_SEND,
4033                       if_printf(ifp, "%s(): ", __func__);
4034                       bce_dump_txbd(sc, sw_tx_chain_cons, txbd));
4035
4036                 /*
4037                  * Free the associated mbuf. Remember
4038                  * that only the last tx_bd of a packet
4039                  * has an mbuf pointer and DMA map.
4040                  */
4041                 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) {
4042                         /* Validate that this is the last tx_bd. */
4043                         DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)),
4044                                 if_printf(ifp, "%s(%d): "
4045                                 "tx_bd END flag not set but "
4046                                 "txmbuf == NULL!\n", __FILE__, __LINE__);
4047                                 bce_breakpoint(sc));
4048
4049                         DBRUN(BCE_INFO_SEND,
4050                               if_printf(ifp, "%s(): Unloading map/freeing mbuf "
4051                                         "from tx_bd[0x%04X]\n", __func__,
4052                                         sw_tx_chain_cons));
4053
4054                         /* Unmap the mbuf. */
4055                         bus_dmamap_unload(sc->tx_mbuf_tag,
4056                                           sc->tx_mbuf_map[sw_tx_chain_cons]);
4057
4058                         /* Free the mbuf. */
4059                         m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]);
4060                         sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL;
4061                         DBRUNIF(1, sc->tx_mbuf_alloc--);
4062
4063                         ifp->if_opackets++;
4064                 }
4065
4066                 sc->used_tx_bd--;
4067                 sw_tx_cons = NEXT_TX_BD(sw_tx_cons);
4068
4069                 if (sw_tx_cons == hw_tx_cons) {
4070                         /* Refresh hw_cons to see if there's new work. */
4071                         hw_tx_cons = sc->hw_tx_cons =
4072                                 sblk->status_tx_quick_consumer_index0;
4073                         if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) ==
4074                             USABLE_TX_BD_PER_PAGE)
4075                                 hw_tx_cons++;
4076                 }
4077
4078                 /*
4079                  * Prevent speculative reads from getting
4080                  * ahead of the status block.
4081                  */
4082                 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4083                                   BUS_SPACE_BARRIER_READ);
4084         }
4085
4086         if (sc->used_tx_bd == 0) {
4087                 /* Clear the TX timeout timer. */
4088                 ifp->if_timer = 0;
4089         }
4090
4091         /* Clear the tx hardware queue full flag. */
4092         if (sc->max_tx_bd - sc->used_tx_bd >= BCE_TX_SPARE_SPACE) {
4093                 DBRUNIF((ifp->if_flags & IFF_OACTIVE),
4094                         DBPRINT(sc, BCE_WARN_SEND,
4095                                 "%s(): Open TX chain! %d/%d (used/total)\n",
4096                                 __func__, sc->used_tx_bd, sc->max_tx_bd));
4097                 ifp->if_flags &= ~IFF_OACTIVE;
4098         }
4099         sc->tx_cons = sw_tx_cons;
4100 }
4101
4102
4103 /****************************************************************************/
4104 /* Disables interrupt generation.                                           */
4105 /*                                                                          */
4106 /* Returns:                                                                 */
4107 /*   Nothing.                                                               */
4108 /****************************************************************************/
4109 static void
4110 bce_disable_intr(struct bce_softc *sc)
4111 {
4112         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
4113         REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
4114         lwkt_serialize_handler_disable(sc->arpcom.ac_if.if_serializer);
4115 }
4116
4117
4118 /****************************************************************************/
4119 /* Enables interrupt generation.                                            */
4120 /*                                                                          */
4121 /* Returns:                                                                 */
4122 /*   Nothing.                                                               */
4123 /****************************************************************************/
4124 static void
4125 bce_enable_intr(struct bce_softc *sc)
4126 {
4127         uint32_t val;
4128
4129         lwkt_serialize_handler_enable(sc->arpcom.ac_if.if_serializer);
4130
4131         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4132                BCE_PCICFG_INT_ACK_CMD_INDEX_VALID |
4133                BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx);
4134
4135         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4136                BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx);
4137
4138         val = REG_RD(sc, BCE_HC_COMMAND);
4139         REG_WR(sc, BCE_HC_COMMAND, val | BCE_HC_COMMAND_COAL_NOW);
4140 }
4141
4142
4143 /****************************************************************************/
4144 /* Handles controller initialization.                                       */
4145 /*                                                                          */
4146 /* Returns:                                                                 */
4147 /*   Nothing.                                                               */
4148 /****************************************************************************/
4149 static void
4150 bce_init(void *xsc)
4151 {
4152         struct bce_softc *sc = xsc;
4153         struct ifnet *ifp = &sc->arpcom.ac_if;
4154         uint32_t ether_mtu;
4155         int error;
4156
4157         ASSERT_SERIALIZED(ifp->if_serializer);
4158
4159         /* Check if the driver is still running and bail out if it is. */
4160         if (ifp->if_flags & IFF_RUNNING)
4161                 return;
4162
4163         bce_stop(sc);
4164
4165         error = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
4166         if (error) {
4167                 if_printf(ifp, "Controller reset failed!\n");
4168                 goto back;
4169         }
4170
4171         error = bce_chipinit(sc);
4172         if (error) {
4173                 if_printf(ifp, "Controller initialization failed!\n");
4174                 goto back;
4175         }
4176
4177         error = bce_blockinit(sc);
4178         if (error) {
4179                 if_printf(ifp, "Block initialization failed!\n");
4180                 goto back;
4181         }
4182
4183         /* Load our MAC address. */
4184         bcopy(IF_LLADDR(ifp), sc->eaddr, ETHER_ADDR_LEN);
4185         bce_set_mac_addr(sc);
4186
4187         /* Calculate and program the Ethernet MTU size. */
4188         ether_mtu = ETHER_HDR_LEN + EVL_ENCAPLEN + ifp->if_mtu + ETHER_CRC_LEN;
4189
4190         DBPRINT(sc, BCE_INFO, "%s(): setting mtu = %d\n", __func__, ether_mtu);
4191
4192         /*
4193          * Program the mtu, enabling jumbo frame
4194          * support if necessary.  Also set the mbuf
4195          * allocation count for RX frames.
4196          */
4197         if (ether_mtu > ETHER_MAX_LEN + EVL_ENCAPLEN) {
4198 #ifdef notyet
4199                 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE,
4200                        min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) |
4201                        BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA);
4202                 sc->mbuf_alloc_size = MJUM9BYTES;
4203 #else
4204                 panic("jumbo buffer is not supported yet\n");
4205 #endif
4206         } else {
4207                 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu);
4208                 sc->mbuf_alloc_size = MCLBYTES;
4209         }
4210
4211         /* Calculate the RX Ethernet frame size for rx_bd's. */
4212         sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8;
4213
4214         DBPRINT(sc, BCE_INFO,
4215                 "%s(): mclbytes = %d, mbuf_alloc_size = %d, "
4216                 "max_frame_size = %d\n",
4217                 __func__, (int)MCLBYTES, sc->mbuf_alloc_size,
4218                 sc->max_frame_size);
4219
4220         /* Program appropriate promiscuous/multicast filtering. */
4221         bce_set_rx_mode(sc);
4222
4223         /* Init RX buffer descriptor chain. */
4224         bce_init_rx_chain(sc);  /* XXX return value */
4225
4226         /* Init TX buffer descriptor chain. */
4227         bce_init_tx_chain(sc);  /* XXX return value */
4228
4229 #ifdef DEVICE_POLLING
4230         /* Disable interrupts if we are polling. */
4231         if (ifp->if_flags & IFF_POLLING) {
4232                 bce_disable_intr(sc);
4233
4234                 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
4235                        (1 << 16) | sc->bce_rx_quick_cons_trip);
4236                 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
4237                        (1 << 16) | sc->bce_tx_quick_cons_trip);
4238         } else
4239 #endif
4240         /* Enable host interrupts. */
4241         bce_enable_intr(sc);
4242
4243         bce_ifmedia_upd(ifp);
4244
4245         ifp->if_flags |= IFF_RUNNING;
4246         ifp->if_flags &= ~IFF_OACTIVE;
4247
4248         callout_reset(&sc->bce_stat_ch, hz, bce_tick, sc);
4249 back:
4250         if (error)
4251                 bce_stop(sc);
4252 }
4253
4254
4255 /****************************************************************************/
4256 /* Initialize the controller just enough so that any management firmware    */
4257 /* running on the device will continue to operate corectly.                 */
4258 /*                                                                          */
4259 /* Returns:                                                                 */
4260 /*   Nothing.                                                               */
4261 /****************************************************************************/
4262 static void
4263 bce_mgmt_init(struct bce_softc *sc)
4264 {
4265         struct ifnet *ifp = &sc->arpcom.ac_if;
4266         uint32_t val;
4267
4268         /* Check if the driver is still running and bail out if it is. */
4269         if (ifp->if_flags & IFF_RUNNING)
4270                 return;
4271
4272         /* Initialize the on-boards CPUs */
4273         bce_init_cpus(sc);
4274
4275         /* Set the page size and clear the RV2P processor stall bits. */
4276         val = (BCM_PAGE_BITS - 8) << 24;
4277         REG_WR(sc, BCE_RV2P_CONFIG, val);
4278
4279         /* Enable all critical blocks in the MAC. */
4280         REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
4281                BCE_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE |
4282                BCE_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE |
4283                BCE_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE);
4284         REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
4285         DELAY(20);
4286
4287         bce_ifmedia_upd(ifp);
4288 }
4289
4290
4291 /****************************************************************************/
4292 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */
4293 /* memory visible to the controller.                                        */
4294 /*                                                                          */
4295 /* Returns:                                                                 */
4296 /*   0 for success, positive value for failure.                             */
4297 /****************************************************************************/
4298 static int
4299 bce_encap(struct bce_softc *sc, struct mbuf **m_head)
4300 {
4301         struct bce_dmamap_arg ctx;
4302         bus_dma_segment_t segs[BCE_MAX_SEGMENTS];
4303         bus_dmamap_t map, tmp_map;
4304         struct mbuf *m0 = *m_head;
4305         struct tx_bd *txbd = NULL;
4306         uint16_t vlan_tag = 0, flags = 0;
4307         uint16_t chain_prod, chain_prod_start, prod;
4308         uint32_t prod_bseq;
4309         int i, error, maxsegs;
4310 #ifdef BCE_DEBUG
4311         uint16_t debug_prod;
4312 #endif
4313
4314         /* Transfer any checksum offload flags to the bd. */
4315         if (m0->m_pkthdr.csum_flags) {
4316                 if (m0->m_pkthdr.csum_flags & CSUM_IP)
4317                         flags |= TX_BD_FLAGS_IP_CKSUM;
4318                 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
4319                         flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
4320         }
4321
4322         /* Transfer any VLAN tags to the bd. */
4323         if (m0->m_flags & M_VLANTAG) {
4324                 flags |= TX_BD_FLAGS_VLAN_TAG;
4325                 vlan_tag = m0->m_pkthdr.ether_vlantag;
4326         }
4327
4328         prod = sc->tx_prod;
4329         chain_prod_start = chain_prod = TX_CHAIN_IDX(prod);
4330
4331         /* Map the mbuf into DMAable memory. */
4332         map = sc->tx_mbuf_map[chain_prod_start];
4333
4334         maxsegs = sc->max_tx_bd - sc->used_tx_bd;
4335         KASSERT(maxsegs >= BCE_TX_SPARE_SPACE,
4336                 ("not enough segements %d\n", maxsegs));
4337         if (maxsegs > BCE_MAX_SEGMENTS)
4338                 maxsegs = BCE_MAX_SEGMENTS;
4339
4340         /* Map the mbuf into our DMA address space. */
4341         ctx.bce_maxsegs = maxsegs;
4342         ctx.bce_segs = segs;
4343         error = bus_dmamap_load_mbuf(sc->tx_mbuf_tag, map, m0,
4344                                      bce_dma_map_mbuf, &ctx, BUS_DMA_NOWAIT);
4345         if (error == EFBIG || ctx.bce_maxsegs == 0) {
4346                 DBPRINT(sc, BCE_WARN, "%s(): fragmented mbuf\n", __func__);
4347                 DBRUNIF(1, bce_dump_mbuf(sc, m0););
4348
4349                 m0 = m_defrag(*m_head, MB_DONTWAIT);
4350                 if (m0 == NULL) {
4351                         error = ENOBUFS;
4352                         goto back;
4353                 }
4354                 *m_head = m0;
4355
4356                 ctx.bce_maxsegs = maxsegs;
4357                 ctx.bce_segs = segs;
4358                 error = bus_dmamap_load_mbuf(sc->tx_mbuf_tag, map, m0,
4359                                              bce_dma_map_mbuf, &ctx,
4360                                              BUS_DMA_NOWAIT);
4361                 if (error || ctx.bce_maxsegs == 0) {
4362                         if_printf(&sc->arpcom.ac_if,
4363                                   "Error mapping mbuf into TX chain\n");
4364                         if (error == 0)
4365                                 error = EFBIG;
4366                         goto back;
4367                 }
4368         } else if (error) {
4369                 if_printf(&sc->arpcom.ac_if,
4370                           "Error mapping mbuf into TX chain\n");
4371                 goto back;
4372         }
4373
4374         /* prod points to an empty tx_bd at this point. */
4375         prod_bseq  = sc->tx_prod_bseq;
4376
4377 #ifdef BCE_DEBUG
4378         debug_prod = chain_prod;
4379 #endif
4380
4381         DBPRINT(sc, BCE_INFO_SEND,
4382                 "%s(): Start: prod = 0x%04X, chain_prod = %04X, "
4383                 "prod_bseq = 0x%08X\n",
4384                 __func__, prod, chain_prod, prod_bseq);
4385
4386         /*
4387          * Cycle through each mbuf segment that makes up
4388          * the outgoing frame, gathering the mapping info
4389          * for that segment and creating a tx_bd to for
4390          * the mbuf.
4391          */
4392         for (i = 0; i < ctx.bce_maxsegs; i++) {
4393                 chain_prod = TX_CHAIN_IDX(prod);
4394                 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)];
4395
4396                 txbd->tx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[i].ds_addr));
4397                 txbd->tx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[i].ds_addr));
4398                 txbd->tx_bd_mss_nbytes = htole16(segs[i].ds_len);
4399                 txbd->tx_bd_vlan_tag = htole16(vlan_tag);
4400                 txbd->tx_bd_flags = htole16(flags);
4401                 prod_bseq += segs[i].ds_len;
4402                 if (i == 0)
4403                         txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START);
4404                 prod = NEXT_TX_BD(prod);
4405         }
4406
4407         /* Set the END flag on the last TX buffer descriptor. */
4408         txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END);
4409
4410         DBRUN(BCE_EXCESSIVE_SEND,
4411               bce_dump_tx_chain(sc, debug_prod, ctx.bce_maxsegs));
4412
4413         DBPRINT(sc, BCE_INFO_SEND,
4414                 "%s(): End: prod = 0x%04X, chain_prod = %04X, "
4415                 "prod_bseq = 0x%08X\n",
4416                 __func__, prod, chain_prod, prod_bseq);
4417
4418         bus_dmamap_sync(sc->tx_mbuf_tag, map, BUS_DMASYNC_PREWRITE);
4419
4420         /*
4421          * Ensure that the mbuf pointer for this transmission
4422          * is placed at the array index of the last
4423          * descriptor in this chain.  This is done
4424          * because a single map is used for all
4425          * segments of the mbuf and we don't want to
4426          * unload the map before all of the segments
4427          * have been freed.
4428          */
4429         sc->tx_mbuf_ptr[chain_prod] = m0;
4430
4431         tmp_map = sc->tx_mbuf_map[chain_prod];
4432         sc->tx_mbuf_map[chain_prod] = map;
4433         sc->tx_mbuf_map[chain_prod_start] = tmp_map;
4434
4435         sc->used_tx_bd += ctx.bce_maxsegs;
4436
4437         /* Update some debug statistic counters */
4438         DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark),
4439                 sc->tx_hi_watermark = sc->used_tx_bd);
4440         DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++);
4441         DBRUNIF(1, sc->tx_mbuf_alloc++);
4442
4443         DBRUN(BCE_VERBOSE_SEND,
4444               bce_dump_tx_mbuf_chain(sc, chain_prod, ctx.bce_maxsegs));
4445
4446         /* prod points to the next free tx_bd at this point. */
4447         sc->tx_prod = prod;
4448         sc->tx_prod_bseq = prod_bseq;
4449 back:
4450         if (error) {
4451                 m_freem(*m_head);
4452                 *m_head = NULL;
4453         }
4454         return error;
4455 }
4456
4457
4458 /****************************************************************************/
4459 /* Main transmit routine when called from another routine with a lock.      */
4460 /*                                                                          */
4461 /* Returns:                                                                 */
4462 /*   Nothing.                                                               */
4463 /****************************************************************************/
4464 static void
4465 bce_start(struct ifnet *ifp)
4466 {
4467         struct bce_softc *sc = ifp->if_softc;
4468         int count = 0;
4469
4470         ASSERT_SERIALIZED(ifp->if_serializer);
4471
4472         /* If there's no link or the transmit queue is empty then just exit. */
4473         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING ||
4474             !sc->bce_link)
4475                 return;
4476
4477         DBPRINT(sc, BCE_INFO_SEND,
4478                 "%s(): Start: tx_prod = 0x%04X, tx_chain_prod = %04X, "
4479                 "tx_prod_bseq = 0x%08X\n",
4480                 __func__,
4481                 sc->tx_prod, TX_CHAIN_IDX(sc->tx_prod), sc->tx_prod_bseq);
4482
4483         for (;;) {
4484                 struct mbuf *m_head;
4485
4486                 /*
4487                  * We keep BCE_TX_SPARE_SPACE entries, so bce_encap() is
4488                  * unlikely to fail.
4489                  */
4490                 if (sc->max_tx_bd - sc->used_tx_bd < BCE_TX_SPARE_SPACE) {
4491                         ifp->if_flags |= IFF_OACTIVE;
4492                         break;
4493                 }
4494
4495                 /* Check for any frames to send. */
4496                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
4497                 if (m_head == NULL)
4498                         break;
4499
4500                 /*
4501                  * Pack the data into the transmit ring. If we
4502                  * don't have room, place the mbuf back at the
4503                  * head of the queue and set the OACTIVE flag
4504                  * to wait for the NIC to drain the chain.
4505                  */
4506                 if (bce_encap(sc, &m_head)) {
4507                         ifp->if_flags |= IFF_OACTIVE;
4508                         DBPRINT(sc, BCE_INFO_SEND,
4509                                 "TX chain is closed for business! "
4510                                 "Total tx_bd used = %d\n",
4511                                 sc->used_tx_bd);
4512                         break;
4513                 }
4514
4515                 count++;
4516
4517                 /* Send a copy of the frame to any BPF listeners. */
4518                 BPF_MTAP(ifp, m_head);
4519         }
4520
4521         if (count == 0) {
4522                 /* no packets were dequeued */
4523                 DBPRINT(sc, BCE_VERBOSE_SEND,
4524                         "%s(): No packets were dequeued\n", __func__);
4525                 return;
4526         }
4527
4528         DBPRINT(sc, BCE_INFO_SEND,
4529                 "%s(): End: tx_prod = 0x%04X, tx_chain_prod = 0x%04X, "
4530                 "tx_prod_bseq = 0x%08X\n",
4531                 __func__,
4532                 sc->tx_prod, TX_CHAIN_IDX(sc->tx_prod), sc->tx_prod_bseq);
4533
4534         /* Start the transmit. */
4535         REG_WR16(sc, MB_TX_CID_ADDR + BCE_L2CTX_TX_HOST_BIDX, sc->tx_prod);
4536         REG_WR(sc, MB_TX_CID_ADDR + BCE_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq);
4537
4538         /* Set the tx timeout. */
4539         ifp->if_timer = BCE_TX_TIMEOUT;
4540 }
4541
4542
4543 /****************************************************************************/
4544 /* Handles any IOCTL calls from the operating system.                       */
4545 /*                                                                          */
4546 /* Returns:                                                                 */
4547 /*   0 for success, positive value for failure.                             */
4548 /****************************************************************************/
4549 static int
4550 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
4551 {
4552         struct bce_softc *sc = ifp->if_softc;
4553         struct ifreq *ifr = (struct ifreq *)data;
4554         struct mii_data *mii;
4555         int mask, error = 0;
4556
4557         ASSERT_SERIALIZED(ifp->if_serializer);
4558
4559         switch(command) {
4560         case SIOCSIFMTU:
4561                 /* Check that the MTU setting is supported. */
4562                 if (ifr->ifr_mtu < BCE_MIN_MTU ||
4563 #ifdef notyet
4564                     ifr->ifr_mtu > BCE_MAX_JUMBO_MTU
4565 #else
4566                     ifr->ifr_mtu > ETHERMTU
4567 #endif
4568                    ) {
4569                         error = EINVAL;
4570                         break;
4571                 }
4572
4573                 DBPRINT(sc, BCE_INFO, "Setting new MTU of %d\n", ifr->ifr_mtu);
4574
4575                 ifp->if_mtu = ifr->ifr_mtu;
4576                 ifp->if_flags &= ~IFF_RUNNING;  /* Force reinitialize */
4577                 bce_init(sc);
4578                 break;
4579
4580         case SIOCSIFFLAGS:
4581                 if (ifp->if_flags & IFF_UP) {
4582                         if (ifp->if_flags & IFF_RUNNING) {
4583                                 mask = ifp->if_flags ^ sc->bce_if_flags;
4584
4585                                 if (mask & (IFF_PROMISC | IFF_ALLMULTI))
4586                                         bce_set_rx_mode(sc);
4587                         } else {
4588                                 bce_init(sc);
4589                         }
4590                 } else if (ifp->if_flags & IFF_RUNNING) {
4591                         bce_stop(sc);
4592                 }
4593                 sc->bce_if_flags = ifp->if_flags;
4594                 break;
4595
4596         case SIOCADDMULTI:
4597         case SIOCDELMULTI:
4598                 if (ifp->if_flags & IFF_RUNNING)
4599                         bce_set_rx_mode(sc);
4600                 break;
4601
4602         case SIOCSIFMEDIA:
4603         case SIOCGIFMEDIA:
4604                 DBPRINT(sc, BCE_VERBOSE, "bce_phy_flags = 0x%08X\n",
4605                         sc->bce_phy_flags);
4606                 DBPRINT(sc, BCE_VERBOSE, "Copper media set/get\n");
4607
4608                 mii = device_get_softc(sc->bce_miibus);
4609                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
4610                 break;
4611
4612         case SIOCSIFCAP:
4613                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
4614                 DBPRINT(sc, BCE_INFO, "Received SIOCSIFCAP = 0x%08X\n",
4615                         (uint32_t) mask);
4616
4617                 if (mask & IFCAP_HWCSUM) {
4618                         ifp->if_capenable ^= IFCAP_HWCSUM;
4619                         if (IFCAP_HWCSUM & ifp->if_capenable)
4620                                 ifp->if_hwassist = BCE_IF_HWASSIST;
4621                         else
4622                                 ifp->if_hwassist = 0;
4623                 }
4624                 break;
4625
4626         default:
4627                 error = ether_ioctl(ifp, command, data);
4628                 break;
4629         }
4630         return error;
4631 }
4632
4633
4634 /****************************************************************************/
4635 /* Transmit timeout handler.                                                */
4636 /*                                                                          */
4637 /* Returns:                                                                 */
4638 /*   Nothing.                                                               */
4639 /****************************************************************************/
4640 static void
4641 bce_watchdog(struct ifnet *ifp)
4642 {
4643         struct bce_softc *sc = ifp->if_softc;
4644
4645         ASSERT_SERIALIZED(ifp->if_serializer);
4646
4647         DBRUN(BCE_VERBOSE_SEND,
4648               bce_dump_driver_state(sc);
4649               bce_dump_status_block(sc));
4650
4651         /*
4652          * If we are in this routine because of pause frames, then
4653          * don't reset the hardware.
4654          */
4655         if (REG_RD(sc, BCE_EMAC_TX_STATUS) & BCE_EMAC_TX_STATUS_XOFFED)
4656                 return;
4657
4658         if_printf(ifp, "Watchdog timeout occurred, resetting!\n");
4659
4660         /* DBRUN(BCE_FATAL, bce_breakpoint(sc)); */
4661
4662         ifp->if_flags &= ~IFF_RUNNING;  /* Force reinitialize */
4663         bce_init(sc);
4664
4665         ifp->if_oerrors++;
4666
4667         if (!ifq_is_empty(&ifp->if_snd))
4668                 ifp->if_start(ifp);
4669 }
4670
4671
4672 #ifdef DEVICE_POLLING
4673
4674 static void
4675 bce_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
4676 {
4677         struct bce_softc *sc = ifp->if_softc;
4678         struct status_block *sblk = sc->status_block;
4679
4680         ASSERT_SERIALIZED(ifp->if_serializer);
4681
4682         switch (cmd) {
4683         case POLL_REGISTER:
4684                 bce_disable_intr(sc);
4685
4686                 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
4687                        (1 << 16) | sc->bce_rx_quick_cons_trip);
4688                 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
4689                        (1 << 16) | sc->bce_tx_quick_cons_trip);
4690                 return;
4691         case POLL_DEREGISTER:
4692                 bce_enable_intr(sc);
4693
4694                 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
4695                        (sc->bce_tx_quick_cons_trip_int << 16) |
4696                        sc->bce_tx_quick_cons_trip);
4697                 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
4698                        (sc->bce_rx_quick_cons_trip_int << 16) |
4699                        sc->bce_rx_quick_cons_trip);
4700                 return;
4701         default:
4702                 break;
4703         }
4704
4705         bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_POSTREAD);
4706
4707         if (cmd == POLL_AND_CHECK_STATUS) {
4708                 uint32_t status_attn_bits;
4709
4710                 status_attn_bits = sblk->status_attn_bits;
4711
4712                 DBRUNIF(DB_RANDOMTRUE(bce_debug_unexpected_attention),
4713                         if_printf(ifp,
4714                         "Simulating unexpected status attention bit set.");
4715                         status_attn_bits |= STATUS_ATTN_BITS_PARITY_ERROR);
4716
4717                 /* Was it a link change interrupt? */
4718                 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
4719                     (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE))
4720                         bce_phy_intr(sc);
4721
4722                 /*
4723                  * If any other attention is asserted then
4724                  * the chip is toast.
4725                  */
4726                 if ((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
4727                      (sblk->status_attn_bits_ack &
4728                       ~STATUS_ATTN_BITS_LINK_STATE)) {
4729                         DBRUN(1, sc->unexpected_attentions++);
4730
4731                         if_printf(ifp, "Fatal attention detected: 0x%08X\n",
4732                                   sblk->status_attn_bits);
4733
4734                         DBRUN(BCE_FATAL,
4735                         if (bce_debug_unexpected_attention == 0)
4736                                 bce_breakpoint(sc));
4737
4738                         bce_init(sc);
4739                         return;
4740                 }
4741         }
4742
4743         /* Check for any completed RX frames. */
4744         if (sblk->status_rx_quick_consumer_index0 != sc->hw_rx_cons)
4745                 bce_rx_intr(sc, count);
4746
4747         /* Check for any completed TX frames. */
4748         if (sblk->status_tx_quick_consumer_index0 != sc->hw_tx_cons)
4749                 bce_tx_intr(sc);
4750
4751         bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_PREWRITE);
4752
4753         /* Check for new frames to transmit. */
4754         if (!ifq_is_empty(&ifp->if_snd))
4755                 ifp->if_start(ifp);
4756 }
4757
4758 #endif  /* DEVICE_POLLING */
4759
4760
4761 #if 0
4762 static inline int
4763 bce_has_work(struct bce_softc *sc)
4764 {
4765         struct status_block *stat = sc->status_block;
4766
4767         if ((stat->status_rx_quick_consumer_index0 != sc->hw_rx_cons) ||
4768             (stat->status_tx_quick_consumer_index0 != sc->hw_tx_cons))
4769                 return 1;
4770
4771         if (((stat->status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 0) !=
4772             bp->link_up)
4773                 return 1;
4774
4775         return 0;
4776 }
4777 #endif
4778
4779
4780 /*
4781  * Interrupt handler.
4782  */
4783 /****************************************************************************/
4784 /* Main interrupt entry point.  Verifies that the controller generated the  */
4785 /* interrupt and then calls a separate routine for handle the various       */
4786 /* interrupt causes (PHY, TX, RX).                                          */
4787 /*                                                                          */
4788 /* Returns:                                                                 */
4789 /*   0 for success, positive value for failure.                             */
4790 /****************************************************************************/
4791 static void
4792 bce_intr(void *xsc)
4793 {
4794         struct bce_softc *sc = xsc;
4795         struct ifnet *ifp = &sc->arpcom.ac_if;
4796         struct status_block *sblk;
4797
4798         ASSERT_SERIALIZED(ifp->if_serializer);
4799
4800         DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __func__);
4801         DBRUNIF(1, sc->interrupts_generated++);
4802
4803         bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_POSTREAD);
4804         sblk = sc->status_block;
4805
4806         /*
4807          * If the hardware status block index matches the last value
4808          * read by the driver and we haven't asserted our interrupt
4809          * then there's nothing to do.
4810          */
4811         if (sblk->status_idx == sc->last_status_idx &&
4812             (REG_RD(sc, BCE_PCICFG_MISC_STATUS) &
4813              BCE_PCICFG_MISC_STATUS_INTA_VALUE))
4814                 return;
4815
4816         /* Ack the interrupt and stop others from occuring. */
4817         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4818                BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
4819                BCE_PCICFG_INT_ACK_CMD_MASK_INT);
4820
4821         /* Keep processing data as long as there is work to do. */
4822         for (;;) {
4823                 uint32_t status_attn_bits;
4824
4825                 status_attn_bits = sblk->status_attn_bits;
4826
4827                 DBRUNIF(DB_RANDOMTRUE(bce_debug_unexpected_attention),
4828                         if_printf(ifp,
4829                         "Simulating unexpected status attention bit set.");
4830                         status_attn_bits |= STATUS_ATTN_BITS_PARITY_ERROR);
4831
4832                 /* Was it a link change interrupt? */
4833                 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
4834                     (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE))
4835                         bce_phy_intr(sc);
4836
4837                 /*
4838                  * If any other attention is asserted then
4839                  * the chip is toast.
4840                  */
4841                 if ((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
4842                      (sblk->status_attn_bits_ack &
4843                       ~STATUS_ATTN_BITS_LINK_STATE)) {
4844                         DBRUN(1, sc->unexpected_attentions++);
4845
4846                         if_printf(ifp, "Fatal attention detected: 0x%08X\n",
4847                                   sblk->status_attn_bits);
4848
4849                         DBRUN(BCE_FATAL,
4850                         if (bce_debug_unexpected_attention == 0)
4851                                 bce_breakpoint(sc));
4852
4853                         bce_init(sc);
4854                         return;
4855                 }
4856
4857                 /* Check for any completed RX frames. */
4858                 if (sblk->status_rx_quick_consumer_index0 != sc->hw_rx_cons)
4859                         bce_rx_intr(sc, -1);
4860
4861                 /* Check for any completed TX frames. */
4862                 if (sblk->status_tx_quick_consumer_index0 != sc->hw_tx_cons)
4863                         bce_tx_intr(sc);
4864
4865                 /*
4866                  * Save the status block index value
4867                  * for use during the next interrupt.
4868                  */
4869                 sc->last_status_idx = sblk->status_idx;
4870
4871                 /*
4872                  * Prevent speculative reads from getting
4873                  * ahead of the status block.
4874                  */
4875                 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4876                                   BUS_SPACE_BARRIER_READ);
4877
4878                 /*
4879                  * If there's no work left then exit the
4880                  * interrupt service routine.
4881                  */
4882                 if (sblk->status_rx_quick_consumer_index0 == sc->hw_rx_cons &&
4883                     sblk->status_tx_quick_consumer_index0 == sc->hw_tx_cons)
4884                         break;
4885         }
4886
4887         bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_PREWRITE);
4888
4889         /* Re-enable interrupts. */
4890         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4891                BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx |
4892                BCE_PCICFG_INT_ACK_CMD_MASK_INT);
4893         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4894                BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx);
4895
4896         /* Handle any frames that arrived while handling the interrupt. */
4897         if (!ifq_is_empty(&ifp->if_snd))
4898                 ifp->if_start(ifp);
4899 }
4900
4901
4902 /****************************************************************************/
4903 /* Programs the various packet receive modes (broadcast and multicast).     */
4904 /*                                                                          */
4905 /* Returns:                                                                 */
4906 /*   Nothing.                                                               */
4907 /****************************************************************************/
4908 static void
4909 bce_set_rx_mode(struct bce_softc *sc)
4910 {
4911         struct ifnet *ifp = &sc->arpcom.ac_if;
4912         struct ifmultiaddr *ifma;
4913         uint32_t hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 };
4914         uint32_t rx_mode, sort_mode;
4915         int h, i;
4916
4917         ASSERT_SERIALIZED(ifp->if_serializer);
4918
4919         /* Initialize receive mode default settings. */
4920         rx_mode = sc->rx_mode &
4921                   ~(BCE_EMAC_RX_MODE_PROMISCUOUS |
4922                     BCE_EMAC_RX_MODE_KEEP_VLAN_TAG);
4923         sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN;
4924
4925         /*
4926          * ASF/IPMI/UMP firmware requires that VLAN tag stripping
4927          * be enbled.
4928          */
4929         if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) &&
4930             !(sc->bce_flags & BCE_MFW_ENABLE_FLAG))
4931                 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG;
4932
4933         /*
4934          * Check for promiscuous, all multicast, or selected
4935          * multicast address filtering.
4936          */
4937         if (ifp->if_flags & IFF_PROMISC) {
4938                 DBPRINT(sc, BCE_INFO, "Enabling promiscuous mode.\n");
4939
4940                 /* Enable promiscuous mode. */
4941                 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS;
4942                 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN;
4943         } else if (ifp->if_flags & IFF_ALLMULTI) {
4944                 DBPRINT(sc, BCE_INFO, "Enabling all multicast mode.\n");
4945
4946                 /* Enable all multicast addresses. */
4947                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
4948                         REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
4949                                0xffffffff);
4950                 }
4951                 sort_mode |= BCE_RPM_SORT_USER0_MC_EN;
4952         } else {
4953                 /* Accept one or more multicast(s). */
4954                 DBPRINT(sc, BCE_INFO, "Enabling selective multicast mode.\n");
4955
4956                 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
4957                         if (ifma->ifma_addr->sa_family != AF_LINK)
4958                                 continue;
4959                         h = ether_crc32_le(
4960                             LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
4961                             ETHER_ADDR_LEN) & 0xFF;
4962                         hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F);
4963                 }
4964
4965                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
4966                         REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
4967                                hashes[i]);
4968                 }
4969                 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN;
4970         }
4971
4972         /* Only make changes if the recive mode has actually changed. */
4973         if (rx_mode != sc->rx_mode) {
4974                 DBPRINT(sc, BCE_VERBOSE, "Enabling new receive mode: 0x%08X\n",
4975                         rx_mode);
4976
4977                 sc->rx_mode = rx_mode;
4978                 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode);
4979         }
4980
4981         /* Disable and clear the exisitng sort before enabling a new sort. */
4982         REG_WR(sc, BCE_RPM_SORT_USER0, 0x0);
4983         REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode);
4984         REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA);
4985 }
4986
4987
4988 /****************************************************************************/
4989 /* Called periodically to updates statistics from the controllers           */
4990 /* statistics block.                                                        */
4991 /*                                                                          */
4992 /* Returns:                                                                 */
4993 /*   Nothing.                                                               */
4994 /****************************************************************************/
4995 static void
4996 bce_stats_update(struct bce_softc *sc)
4997 {
4998         struct ifnet *ifp = &sc->arpcom.ac_if;
4999         struct statistics_block *stats = sc->stats_block;
5000
5001         DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __func__);
5002
5003         ASSERT_SERIALIZED(ifp->if_serializer);
5004
5005         /*
5006          * Update the interface statistics from the hardware statistics.
5007          */
5008         ifp->if_collisions = (u_long)stats->stat_EtherStatsCollisions;
5009
5010         ifp->if_ierrors = (u_long)stats->stat_EtherStatsUndersizePkts +
5011                           (u_long)stats->stat_EtherStatsOverrsizePkts +
5012                           (u_long)stats->stat_IfInMBUFDiscards +
5013                           (u_long)stats->stat_Dot3StatsAlignmentErrors +
5014                           (u_long)stats->stat_Dot3StatsFCSErrors;
5015
5016         ifp->if_oerrors =
5017         (u_long)stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors +
5018         (u_long)stats->stat_Dot3StatsExcessiveCollisions +
5019         (u_long)stats->stat_Dot3StatsLateCollisions;
5020
5021         /*
5022          * Certain controllers don't report carrier sense errors correctly.
5023          * See errata E11_5708CA0_1165.
5024          */
5025         if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
5026             !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0)) {
5027                 ifp->if_oerrors +=
5028                         (u_long)stats->stat_Dot3StatsCarrierSenseErrors;
5029         }
5030
5031         /*
5032          * Update the sysctl statistics from the hardware statistics.
5033          */
5034         sc->stat_IfHCInOctets =
5035                 ((uint64_t)stats->stat_IfHCInOctets_hi << 32) +
5036                  (uint64_t)stats->stat_IfHCInOctets_lo;
5037
5038         sc->stat_IfHCInBadOctets =
5039                 ((uint64_t)stats->stat_IfHCInBadOctets_hi << 32) +
5040                  (uint64_t)stats->stat_IfHCInBadOctets_lo;
5041
5042         sc->stat_IfHCOutOctets =
5043                 ((uint64_t)stats->stat_IfHCOutOctets_hi << 32) +
5044                  (uint64_t)stats->stat_IfHCOutOctets_lo;
5045
5046         sc->stat_IfHCOutBadOctets =
5047                 ((uint64_t)stats->stat_IfHCOutBadOctets_hi << 32) +
5048                  (uint64_t)stats->stat_IfHCOutBadOctets_lo;
5049
5050         sc->stat_IfHCInUcastPkts =
5051                 ((uint64_t)stats->stat_IfHCInUcastPkts_hi << 32) +
5052                  (uint64_t)stats->stat_IfHCInUcastPkts_lo;
5053
5054         sc->stat_IfHCInMulticastPkts =
5055                 ((uint64_t)stats->stat_IfHCInMulticastPkts_hi << 32) +
5056                  (uint64_t)stats->stat_IfHCInMulticastPkts_lo;
5057
5058         sc->stat_IfHCInBroadcastPkts =
5059                 ((uint64_t)stats->stat_IfHCInBroadcastPkts_hi << 32) +
5060                  (uint64_t)stats->stat_IfHCInBroadcastPkts_lo;
5061
5062         sc->stat_IfHCOutUcastPkts =
5063                 ((uint64_t)stats->stat_IfHCOutUcastPkts_hi << 32) +
5064                  (uint64_t)stats->stat_IfHCOutUcastPkts_lo;
5065
5066         sc->stat_IfHCOutMulticastPkts =
5067                 ((uint64_t)stats->stat_IfHCOutMulticastPkts_hi << 32) +
5068                  (uint64_t)stats->stat_IfHCOutMulticastPkts_lo;
5069
5070         sc->stat_IfHCOutBroadcastPkts =
5071                 ((uint64_t)stats->stat_IfHCOutBroadcastPkts_hi << 32) +
5072                  (uint64_t)stats->stat_IfHCOutBroadcastPkts_lo;
5073
5074         sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors =
5075                 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
5076
5077         sc->stat_Dot3StatsCarrierSenseErrors =
5078                 stats->stat_Dot3StatsCarrierSenseErrors;
5079
5080         sc->stat_Dot3StatsFCSErrors =
5081                 stats->stat_Dot3StatsFCSErrors;
5082
5083         sc->stat_Dot3StatsAlignmentErrors =
5084                 stats->stat_Dot3StatsAlignmentErrors;
5085
5086         sc->stat_Dot3StatsSingleCollisionFrames =
5087                 stats->stat_Dot3StatsSingleCollisionFrames;
5088
5089         sc->stat_Dot3StatsMultipleCollisionFrames =
5090                 stats->stat_Dot3StatsMultipleCollisionFrames;
5091
5092         sc->stat_Dot3StatsDeferredTransmissions =
5093                 stats->stat_Dot3StatsDeferredTransmissions;
5094
5095         sc->stat_Dot3StatsExcessiveCollisions =
5096                 stats->stat_Dot3StatsExcessiveCollisions;
5097
5098         sc->stat_Dot3StatsLateCollisions =
5099                 stats->stat_Dot3StatsLateCollisions;
5100
5101         sc->stat_EtherStatsCollisions =
5102                 stats->stat_EtherStatsCollisions;
5103
5104         sc->stat_EtherStatsFragments =
5105                 stats->stat_EtherStatsFragments;
5106
5107         sc->stat_EtherStatsJabbers =
5108                 stats->stat_EtherStatsJabbers;
5109
5110         sc->stat_EtherStatsUndersizePkts =
5111                 stats->stat_EtherStatsUndersizePkts;
5112
5113         sc->stat_EtherStatsOverrsizePkts =
5114                 stats->stat_EtherStatsOverrsizePkts;
5115
5116         sc->stat_EtherStatsPktsRx64Octets =
5117                 stats->stat_EtherStatsPktsRx64Octets;
5118
5119         sc->stat_EtherStatsPktsRx65Octetsto127Octets =
5120                 stats->stat_EtherStatsPktsRx65Octetsto127Octets;
5121
5122         sc->stat_EtherStatsPktsRx128Octetsto255Octets =
5123                 stats->stat_EtherStatsPktsRx128Octetsto255Octets;
5124
5125         sc->stat_EtherStatsPktsRx256Octetsto511Octets =
5126                 stats->stat_EtherStatsPktsRx256Octetsto511Octets;
5127
5128         sc->stat_EtherStatsPktsRx512Octetsto1023Octets =
5129                 stats->stat_EtherStatsPktsRx512Octetsto1023Octets;
5130
5131         sc->stat_EtherStatsPktsRx1024Octetsto1522Octets =
5132                 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets;
5133
5134         sc->stat_EtherStatsPktsRx1523Octetsto9022Octets =
5135                 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets;
5136
5137         sc->stat_EtherStatsPktsTx64Octets =
5138                 stats->stat_EtherStatsPktsTx64Octets;
5139
5140         sc->stat_EtherStatsPktsTx65Octetsto127Octets =
5141                 stats->stat_EtherStatsPktsTx65Octetsto127Octets;
5142
5143         sc->stat_EtherStatsPktsTx128Octetsto255Octets =
5144                 stats->stat_EtherStatsPktsTx128Octetsto255Octets;
5145
5146         sc->stat_EtherStatsPktsTx256Octetsto511Octets =
5147                 stats->stat_EtherStatsPktsTx256Octetsto511Octets;
5148
5149         sc->stat_EtherStatsPktsTx512Octetsto1023Octets =
5150                 stats->stat_EtherStatsPktsTx512Octetsto1023Octets;
5151
5152         sc->stat_EtherStatsPktsTx1024Octetsto1522Octets =
5153                 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets;
5154
5155         sc->stat_EtherStatsPktsTx1523Octetsto9022Octets =
5156                 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets;
5157
5158         sc->stat_XonPauseFramesReceived =
5159                 stats->stat_XonPauseFramesReceived;
5160
5161         sc->stat_XoffPauseFramesReceived =
5162                 stats->stat_XoffPauseFramesReceived;
5163
5164         sc->stat_OutXonSent =
5165                 stats->stat_OutXonSent;
5166
5167         sc->stat_OutXoffSent =
5168                 stats->stat_OutXoffSent;
5169
5170         sc->stat_FlowControlDone =
5171                 stats->stat_FlowControlDone;
5172
5173         sc->stat_MacControlFramesReceived =
5174                 stats->stat_MacControlFramesReceived;
5175
5176         sc->stat_XoffStateEntered =
5177                 stats->stat_XoffStateEntered;
5178
5179         sc->stat_IfInFramesL2FilterDiscards =
5180                 stats->stat_IfInFramesL2FilterDiscards;
5181
5182         sc->stat_IfInRuleCheckerDiscards =
5183                 stats->stat_IfInRuleCheckerDiscards;
5184
5185         sc->stat_IfInFTQDiscards =
5186                 stats->stat_IfInFTQDiscards;
5187
5188         sc->stat_IfInMBUFDiscards =
5189                 stats->stat_IfInMBUFDiscards;
5190
5191         sc->stat_IfInRuleCheckerP4Hit =
5192                 stats->stat_IfInRuleCheckerP4Hit;
5193
5194         sc->stat_CatchupInRuleCheckerDiscards =
5195                 stats->stat_CatchupInRuleCheckerDiscards;
5196
5197         sc->stat_CatchupInFTQDiscards =
5198                 stats->stat_CatchupInFTQDiscards;
5199
5200         sc->stat_CatchupInMBUFDiscards =
5201                 stats->stat_CatchupInMBUFDiscards;
5202
5203         sc->stat_CatchupInRuleCheckerP4Hit =
5204                 stats->stat_CatchupInRuleCheckerP4Hit;
5205
5206         sc->com_no_buffers = REG_RD_IND(sc, 0x120084);
5207
5208         DBPRINT(sc, BCE_EXCESSIVE, "Exiting %s()\n", __func__);
5209 }
5210
5211
5212 /****************************************************************************/
5213 /* Periodic function to perform maintenance tasks.                          */
5214 /*                                                                          */
5215 /* Returns:                                                                 */
5216 /*   Nothing.                                                               */
5217 /****************************************************************************/
5218 static void
5219 bce_tick_serialized(struct bce_softc *sc)
5220 {
5221         struct ifnet *ifp = &sc->arpcom.ac_if;
5222         struct mii_data *mii;
5223         uint32_t msg;
5224
5225         ASSERT_SERIALIZED(ifp->if_serializer);
5226
5227         /* Tell the firmware that the driver is still running. */
5228 #ifdef BCE_DEBUG
5229         msg = (uint32_t)BCE_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE;
5230 #else
5231         msg = (uint32_t)++sc->bce_fw_drv_pulse_wr_seq;
5232 #endif
5233         REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_PULSE_MB, msg);
5234
5235         /* Update the statistics from the hardware statistics block. */
5236         bce_stats_update(sc);
5237
5238         /* Schedule the next tick. */
5239         callout_reset(&sc->bce_stat_ch, hz, bce_tick, sc);
5240
5241         /* If link is up already up then we're done. */
5242         if (sc->bce_link)
5243                 return;
5244
5245         mii = device_get_softc(sc->bce_miibus);
5246         mii_tick(mii);
5247
5248         /* Check if the link has come up. */
5249         if (!sc->bce_link && (mii->mii_media_status & IFM_ACTIVE) &&
5250             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
5251                 sc->bce_link++;
5252                 /* Now that link is up, handle any outstanding TX traffic. */
5253                 if (!ifq_is_empty(&ifp->if_snd))
5254                         ifp->if_start(ifp);
5255         }
5256 }
5257
5258
5259 static void
5260 bce_tick(void *xsc)
5261 {
5262         struct bce_softc *sc = xsc;
5263         struct ifnet *ifp = &sc->arpcom.ac_if;
5264
5265         lwkt_serialize_enter(ifp->if_serializer);
5266         bce_tick_serialized(sc);
5267         lwkt_serialize_exit(ifp->if_serializer);
5268 }
5269
5270
5271 #ifdef BCE_DEBUG
5272 /****************************************************************************/
5273 /* Allows the driver state to be dumped through the sysctl interface.       */
5274 /*                                                                          */
5275 /* Returns:                                                                 */
5276 /*   0 for success, positive value for failure.                             */
5277 /****************************************************************************/
5278 static int
5279 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS)
5280 {
5281         int error;
5282         int result;
5283         struct bce_softc *sc;
5284
5285         result = -1;
5286         error = sysctl_handle_int(oidp, &result, 0, req);
5287
5288         if (error || !req->newptr)
5289                 return (error);
5290
5291         if (result == 1) {
5292                 sc = (struct bce_softc *)arg1;
5293                 bce_dump_driver_state(sc);
5294         }
5295
5296         return error;
5297 }
5298
5299
5300 /****************************************************************************/
5301 /* Allows the hardware state to be dumped through the sysctl interface.     */
5302 /*                                                                          */
5303 /* Returns:                                                                 */
5304 /*   0 for success, positive value for failure.                             */
5305 /****************************************************************************/
5306 static int
5307 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS)
5308 {
5309         int error;
5310         int result;
5311         struct bce_softc *sc;
5312
5313         result = -1;
5314         error = sysctl_handle_int(oidp, &result, 0, req);
5315
5316         if (error || !req->newptr)
5317                 return (error);
5318
5319         if (result == 1) {
5320                 sc = (struct bce_softc *)arg1;
5321                 bce_dump_hw_state(sc);
5322         }
5323
5324         return error;
5325 }
5326
5327
5328 /****************************************************************************/
5329 /* Provides a sysctl interface to allows dumping the RX chain.              */
5330 /*                                                                          */
5331 /* Returns:                                                                 */
5332 /*   0 for success, positive value for failure.                             */
5333 /****************************************************************************/
5334 static int
5335 bce_sysctl_dump_rx_chain(SYSCTL_HANDLER_ARGS)
5336 {
5337         int error;
5338         int result;
5339         struct bce_softc *sc;
5340
5341         result = -1;
5342         error = sysctl_handle_int(oidp, &result, 0, req);
5343
5344         if (error || !req->newptr)
5345                 return (error);
5346
5347         if (result == 1) {
5348                 sc = (struct bce_softc *)arg1;
5349                 bce_dump_rx_chain(sc, 0, USABLE_RX_BD);
5350         }
5351
5352         return error;
5353 }
5354
5355
5356 /****************************************************************************/
5357 /* Provides a sysctl interface to allows dumping the TX chain.              */
5358 /*                                                                          */
5359 /* Returns:                                                                 */
5360 /*   0 for success, positive value for failure.                             */
5361 /****************************************************************************/
5362 static int
5363 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS)
5364 {
5365         int error;
5366         int result;
5367         struct bce_softc *sc;
5368
5369         result = -1;
5370         error = sysctl_handle_int(oidp, &result, 0, req);
5371
5372         if (error || !req->newptr)
5373                 return (error);
5374
5375         if (result == 1) {
5376                 sc = (struct bce_softc *)arg1;
5377                 bce_dump_tx_chain(sc, 0, USABLE_TX_BD);
5378         }
5379
5380         return error;
5381 }
5382
5383
5384 /****************************************************************************/
5385 /* Provides a sysctl interface to allow reading arbitrary registers in the  */
5386 /* device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                            */
5387 /*                                                                          */
5388 /* Returns:                                                                 */
5389 /*   0 for success, positive value for failure.                             */
5390 /****************************************************************************/
5391 static int
5392 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
5393 {
5394         struct bce_softc *sc;
5395         int error;
5396         uint32_t val, result;
5397
5398         result = -1;
5399         error = sysctl_handle_int(oidp, &result, 0, req);
5400         if (error || (req->newptr == NULL))
5401                 return (error);
5402
5403         /* Make sure the register is accessible. */
5404         if (result < 0x8000) {
5405                 sc = (struct bce_softc *)arg1;
5406                 val = REG_RD(sc, result);
5407                 if_printf(&sc->arpcom.ac_if, "reg 0x%08X = 0x%08X\n",
5408                           result, val);
5409         } else if (result < 0x0280000) {
5410                 sc = (struct bce_softc *)arg1;
5411                 val = REG_RD_IND(sc, result);
5412                 if_printf(&sc->arpcom.ac_if, "reg 0x%08X = 0x%08X\n",
5413                           result, val);
5414         }
5415         return (error);
5416 }
5417
5418
5419 /****************************************************************************/
5420 /* Provides a sysctl interface to allow reading arbitrary PHY registers in  */\r
5421 /* the device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                        */\r
5422 /*                                                                          */
5423 /* Returns:                                                                 */
5424 /*   0 for success, positive value for failure.                             */
5425 /****************************************************************************/
5426 static int
5427 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS)
5428 {
5429         struct bce_softc *sc;
5430         device_t dev;
5431         int error, result;
5432         uint16_t val;
5433
5434         result = -1;
5435         error = sysctl_handle_int(oidp, &result, 0, req);
5436         if (error || (req->newptr == NULL))
5437                 return (error);
5438
5439         /* Make sure the register is accessible. */
5440         if (result < 0x20) {
5441                 sc = (struct bce_softc *)arg1;
5442                 dev = sc->bce_dev;
5443                 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result);
5444                 if_printf(&sc->arpcom.ac_if,
5445                           "phy 0x%02X = 0x%04X\n", result, val);
5446         }
5447         return (error);
5448 }
5449
5450
5451 /****************************************************************************/
5452 /* Provides a sysctl interface to forcing the driver to dump state and      */\r
5453 /* enter the debugger.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                */
5454 /*                                                                          */
5455 /* Returns:                                                                 */
5456 /*   0 for success, positive value for failure.                             */
5457 /****************************************************************************/
5458 static int
5459 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS)
5460 {
5461         int error;
5462         int result;
5463         struct bce_softc *sc;
5464
5465         result = -1;
5466         error = sysctl_handle_int(oidp, &result, 0, req);
5467
5468         if (error || !req->newptr)
5469                 return (error);
5470
5471         if (result == 1) {
5472                 sc = (struct bce_softc *)arg1;
5473                 bce_breakpoint(sc);
5474         }
5475
5476         return error;
5477 }
5478 #endif
5479
5480
5481 /****************************************************************************/
5482 /* Adds any sysctl parameters for tuning or debugging purposes.             */
5483 /*                                                                          */
5484 /* Returns:                                                                 */
5485 /*   0 for success, positive value for failure.                             */
5486 /****************************************************************************/
5487 static void
5488 bce_add_sysctls(struct bce_softc *sc)
5489 {
5490         struct sysctl_ctx_list *ctx;
5491         struct sysctl_oid_list *children;
5492
5493         sysctl_ctx_init(&sc->bce_sysctl_ctx);
5494         sc->bce_sysctl_tree = SYSCTL_ADD_NODE(&sc->bce_sysctl_ctx,
5495                                               SYSCTL_STATIC_CHILDREN(_hw),
5496                                               OID_AUTO,
5497                                               device_get_nameunit(sc->bce_dev),
5498                                               CTLFLAG_RD, 0, "");
5499         if (sc->bce_sysctl_tree == NULL) {
5500                 device_printf(sc->bce_dev, "can't add sysctl node\n");
5501                 return;
5502         }
5503
5504         ctx = &sc->bce_sysctl_ctx;
5505         children = SYSCTL_CHILDREN(sc->bce_sysctl_tree);
5506
5507 #ifdef BCE_DEBUG
5508         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5509                 "rx_low_watermark",
5510                 CTLFLAG_RD, &sc->rx_low_watermark,
5511                 0, "Lowest level of free rx_bd's");
5512
5513         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5514                 "rx_empty_count",
5515                 CTLFLAG_RD, &sc->rx_empty_count,
5516                 0, "Number of times the RX chain was empty");
5517
5518         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5519                 "tx_hi_watermark",
5520                 CTLFLAG_RD, &sc->tx_hi_watermark,
5521                 0, "Highest level of used tx_bd's");
5522
5523         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5524                 "tx_full_count",
5525                 CTLFLAG_RD, &sc->tx_full_count,
5526                 0, "Number of times the TX chain was full");
5527
5528         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5529                 "l2fhdr_status_errors",
5530                 CTLFLAG_RD, &sc->l2fhdr_status_errors,
5531                 0, "l2_fhdr status errors");
5532
5533         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5534                 "unexpected_attentions",
5535                 CTLFLAG_RD, &sc->unexpected_attentions,
5536                 0, "unexpected attentions");
5537
5538         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5539                 "lost_status_block_updates",
5540                 CTLFLAG_RD, &sc->lost_status_block_updates,
5541                 0, "lost status block updates");
5542
5543         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5544                 "mbuf_alloc_failed",
5545                 CTLFLAG_RD, &sc->mbuf_alloc_failed,
5546                 0, "mbuf cluster allocation failures");
5547 #endif
5548
5549         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5550                 "stat_IfHcInOctets",
5551                 CTLFLAG_RD, &sc->stat_IfHCInOctets,
5552                 "Bytes received");
5553
5554         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5555                 "stat_IfHCInBadOctets",
5556                 CTLFLAG_RD, &sc->stat_IfHCInBadOctets,
5557                 "Bad bytes received");
5558
5559         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5560                 "stat_IfHCOutOctets",
5561                 CTLFLAG_RD, &sc->stat_IfHCOutOctets,
5562                 "Bytes sent");
5563
5564         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5565                 "stat_IfHCOutBadOctets",
5566                 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets,
5567                 "Bad bytes sent");
5568
5569         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5570                 "stat_IfHCInUcastPkts",
5571                 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts,
5572                 "Unicast packets received");
5573
5574         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5575                 "stat_IfHCInMulticastPkts",
5576                 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts,
5577                 "Multicast packets received");
5578
5579         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5580                 "stat_IfHCInBroadcastPkts",
5581                 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts,
5582                 "Broadcast packets received");
5583
5584         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5585                 "stat_IfHCOutUcastPkts",
5586                 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts,
5587                 "Unicast packets sent");
5588
5589         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5590                 "stat_IfHCOutMulticastPkts",
5591                 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts,
5592                 "Multicast packets sent");
5593
5594         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5595                 "stat_IfHCOutBroadcastPkts",
5596                 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts,
5597                 "Broadcast packets sent");
5598
5599         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5600                 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors",
5601                 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors,
5602                 0, "Internal MAC transmit errors");
5603
5604         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5605                 "stat_Dot3StatsCarrierSenseErrors",
5606                 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors,
5607                 0, "Carrier sense errors");
5608
5609         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5610                 "stat_Dot3StatsFCSErrors",
5611                 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors,
5612                 0, "Frame check sequence errors");
5613
5614         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5615                 "stat_Dot3StatsAlignmentErrors",
5616                 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors,
5617                 0, "Alignment errors");
5618
5619         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5620                 "stat_Dot3StatsSingleCollisionFrames",
5621                 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames,
5622                 0, "Single Collision Frames");
5623
5624         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5625                 "stat_Dot3StatsMultipleCollisionFrames",
5626                 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames,
5627                 0, "Multiple Collision Frames");
5628
5629         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5630                 "stat_Dot3StatsDeferredTransmissions",
5631                 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions,
5632                 0, "Deferred Transmissions");
5633
5634         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5635                 "stat_Dot3StatsExcessiveCollisions",
5636                 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions,
5637                 0, "Excessive Collisions");
5638
5639         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5640                 "stat_Dot3StatsLateCollisions",
5641                 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions,
5642                 0, "Late Collisions");
5643
5644         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5645                 "stat_EtherStatsCollisions",
5646                 CTLFLAG_RD, &sc->stat_EtherStatsCollisions,
5647                 0, "Collisions");
5648
5649         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5650                 "stat_EtherStatsFragments",
5651                 CTLFLAG_RD, &sc->stat_EtherStatsFragments,
5652                 0, "Fragments");
5653
5654         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5655                 "stat_EtherStatsJabbers",
5656                 CTLFLAG_RD, &sc->stat_EtherStatsJabbers,
5657                 0, "Jabbers");
5658
5659         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5660                 "stat_EtherStatsUndersizePkts",
5661                 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts,
5662                 0, "Undersize packets");
5663
5664         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5665                 "stat_EtherStatsOverrsizePkts",
5666                 CTLFLAG_RD, &sc->stat_EtherStatsOverrsizePkts,
5667                 0, "stat_EtherStatsOverrsizePkts");
5668
5669         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5670                 "stat_EtherStatsPktsRx64Octets",
5671                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets,
5672                 0, "Bytes received in 64 byte packets");
5673
5674         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5675                 "stat_EtherStatsPktsRx65Octetsto127Octets",
5676                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets,
5677                 0, "Bytes received in 65 to 127 byte packets");
5678
5679         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5680                 "stat_EtherStatsPktsRx128Octetsto255Octets",
5681                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets,
5682                 0, "Bytes received in 128 to 255 byte packets");
5683
5684         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5685                 "stat_EtherStatsPktsRx256Octetsto511Octets",
5686                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets,
5687                 0, "Bytes received in 256 to 511 byte packets");
5688
5689         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5690                 "stat_EtherStatsPktsRx512Octetsto1023Octets",
5691                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets,
5692                 0, "Bytes received in 512 to 1023 byte packets");
5693
5694         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5695                 "stat_EtherStatsPktsRx1024Octetsto1522Octets",
5696                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets,
5697                 0, "Bytes received in 1024 t0 1522 byte packets");
5698
5699         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5700                 "stat_EtherStatsPktsRx1523Octetsto9022Octets",
5701                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets,
5702                 0, "Bytes received in 1523 to 9022 byte packets");
5703
5704         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5705                 "stat_EtherStatsPktsTx64Octets",
5706                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets,
5707                 0, "Bytes sent in 64 byte packets");
5708
5709         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5710                 "stat_EtherStatsPktsTx65Octetsto127Octets",
5711                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets,
5712                 0, "Bytes sent in 65 to 127 byte packets");
5713
5714         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5715                 "stat_EtherStatsPktsTx128Octetsto255Octets",
5716                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets,
5717                 0, "Bytes sent in 128 to 255 byte packets");
5718
5719         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5720                 "stat_EtherStatsPktsTx256Octetsto511Octets",
5721                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets,
5722                 0, "Bytes sent in 256 to 511 byte packets");
5723
5724         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5725                 "stat_EtherStatsPktsTx512Octetsto1023Octets",
5726                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets,
5727                 0, "Bytes sent in 512 to 1023 byte packets");
5728
5729         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5730                 "stat_EtherStatsPktsTx1024Octetsto1522Octets",
5731                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets,
5732                 0, "Bytes sent in 1024 to 1522 byte packets");
5733
5734         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5735                 "stat_EtherStatsPktsTx1523Octetsto9022Octets",
5736                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets,
5737                 0, "Bytes sent in 1523 to 9022 byte packets");
5738
5739         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5740                 "stat_XonPauseFramesReceived",
5741                 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived,
5742                 0, "XON pause frames receved");
5743
5744         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5745                 "stat_XoffPauseFramesReceived",
5746                 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived,
5747                 0, "XOFF pause frames received");
5748
5749         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5750                 "stat_OutXonSent",
5751                 CTLFLAG_RD, &sc->stat_OutXonSent,
5752                 0, "XON pause frames sent");
5753
5754         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5755                 "stat_OutXoffSent",
5756                 CTLFLAG_RD, &sc->stat_OutXoffSent,
5757                 0, "XOFF pause frames sent");
5758
5759         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5760                 "stat_FlowControlDone",
5761                 CTLFLAG_RD, &sc->stat_FlowControlDone,
5762                 0, "Flow control done");
5763
5764         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5765                 "stat_MacControlFramesReceived",
5766                 CTLFLAG_RD, &sc->stat_MacControlFramesReceived,
5767                 0, "MAC control frames received");
5768
5769         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5770                 "stat_XoffStateEntered",
5771                 CTLFLAG_RD, &sc->stat_XoffStateEntered,
5772                 0, "XOFF state entered");
5773
5774         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5775                 "stat_IfInFramesL2FilterDiscards",
5776                 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards,
5777                 0, "Received L2 packets discarded");
5778
5779         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5780                 "stat_IfInRuleCheckerDiscards",
5781                 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards,
5782                 0, "Received packets discarded by rule");
5783
5784         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5785                 "stat_IfInFTQDiscards",
5786                 CTLFLAG_RD, &sc->stat_IfInFTQDiscards,
5787                 0, "Received packet FTQ discards");
5788
5789         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5790                 "stat_IfInMBUFDiscards",
5791                 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards,
5792                 0, "Received packets discarded due to lack of controller buffer memory");
5793
5794         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5795                 "stat_IfInRuleCheckerP4Hit",
5796                 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit,
5797                 0, "Received packets rule checker hits");
5798
5799         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5800                 "stat_CatchupInRuleCheckerDiscards",
5801                 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards,
5802                 0, "Received packets discarded in Catchup path");
5803
5804         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5805                 "stat_CatchupInFTQDiscards",
5806                 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards,
5807                 0, "Received packets discarded in FTQ in Catchup path");
5808
5809         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5810                 "stat_CatchupInMBUFDiscards",
5811                 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards,
5812                 0, "Received packets discarded in controller buffer memory in Catchup path");
5813
5814         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5815                 "stat_CatchupInRuleCheckerP4Hit",
5816                 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit,
5817                 0, "Received packets rule checker hits in Catchup path");
5818
5819         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
5820                 "com_no_buffers",
5821                 CTLFLAG_RD, &sc->com_no_buffers,
5822                 0, "Valid packets received but no RX buffers available");
5823
5824 #ifdef BCE_DEBUG
5825         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
5826                 "driver_state", CTLTYPE_INT | CTLFLAG_RW,
5827                 (void *)sc, 0,
5828                 bce_sysctl_driver_state, "I", "Drive state information");
5829
5830         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
5831                 "hw_state", CTLTYPE_INT | CTLFLAG_RW,
5832                 (void *)sc, 0,
5833                 bce_sysctl_hw_state, "I", "Hardware state information");
5834
5835         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
5836                 "dump_rx_chain", CTLTYPE_INT | CTLFLAG_RW,
5837                 (void *)sc, 0,
5838                 bce_sysctl_dump_rx_chain, "I", "Dump rx_bd chain");
5839
5840         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
5841                 "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW,
5842                 (void *)sc, 0,
5843                 bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain");
5844
5845         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
5846                 "breakpoint", CTLTYPE_INT | CTLFLAG_RW,
5847                 (void *)sc, 0,
5848                 bce_sysctl_breakpoint, "I", "Driver breakpoint");
5849
5850         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
5851                 "reg_read", CTLTYPE_INT | CTLFLAG_RW,
5852                 (void *)sc, 0,
5853                 bce_sysctl_reg_read, "I", "Register read");
5854
5855         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, \r
5856                 "phy_read", CTLTYPE_INT | CTLFLAG_RW, \r
5857                 (void *)sc, 0, \r
5858                 bce_sysctl_phy_read, "I", "PHY register read");
5859
5860 #endif
5861
5862 }
5863
5864
5865 /****************************************************************************/
5866 /* BCE Debug Routines                                                       */
5867 /****************************************************************************/
5868 #ifdef BCE_DEBUG
5869
5870 /****************************************************************************/
5871 /* Freezes the controller to allow for a cohesive state dump.               */
5872 /*                                                                          */
5873 /* Returns:                                                                 */
5874 /*   Nothing.                                                               */
5875 /****************************************************************************/
5876 static void
5877 bce_freeze_controller(struct bce_softc *sc)
5878 {
5879         uint32_t val;
5880
5881         val = REG_RD(sc, BCE_MISC_COMMAND);
5882         val |= BCE_MISC_COMMAND_DISABLE_ALL;
5883         REG_WR(sc, BCE_MISC_COMMAND, val);
5884 }
5885
5886
5887 /****************************************************************************/
5888 /* Unfreezes the controller after a freeze operation.  This may not always  */\r
5889 /* work and the controller will require a reset!                            */
5890 /*                                                                          */
5891 /* Returns:                                                                 */
5892 /*   Nothing.                                                               */
5893 /****************************************************************************/
5894 static void
5895 bce_unfreeze_controller(struct bce_softc *sc)
5896 {
5897         uint32_t val;
5898
5899         val = REG_RD(sc, BCE_MISC_COMMAND);
5900         val |= BCE_MISC_COMMAND_ENABLE_ALL;
5901         REG_WR(sc, BCE_MISC_COMMAND, val);
5902 }
5903
5904
5905 /****************************************************************************/
5906 /* Prints out information about an mbuf.                                    */
5907 /*                                                                          */
5908 /* Returns:                                                                 */
5909 /*   Nothing.                                                               */
5910 /****************************************************************************/
5911 static void
5912 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m)
5913 {
5914         struct ifnet *ifp = &sc->arpcom.ac_if;
5915         uint32_t val_hi, val_lo;
5916         struct mbuf *mp = m;
5917
5918         if (m == NULL) {
5919                 /* Index out of range. */
5920                 if_printf(ifp, "mbuf: null pointer\n");
5921                 return;
5922         }
5923
5924         while (mp) {
5925                 val_hi = BCE_ADDR_HI(mp);
5926                 val_lo = BCE_ADDR_LO(mp);
5927                 if_printf(ifp, "mbuf: vaddr = 0x%08X:%08X, m_len = %d, "
5928                           "m_flags = ( ", val_hi, val_lo, mp->m_len);
5929
5930                 if (mp->m_flags & M_EXT)
5931                         kprintf("M_EXT ");
5932                 if (mp->m_flags & M_PKTHDR)
5933                         kprintf("M_PKTHDR ");
5934                 if (mp->m_flags & M_EOR)
5935                         kprintf("M_EOR ");
5936 #ifdef M_RDONLY
5937                 if (mp->m_flags & M_RDONLY)
5938                         kprintf("M_RDONLY ");
5939 #endif
5940
5941                 val_hi = BCE_ADDR_HI(mp->m_data);
5942                 val_lo = BCE_ADDR_LO(mp->m_data);
5943                 kprintf(") m_data = 0x%08X:%08X\n", val_hi, val_lo);
5944
5945                 if (mp->m_flags & M_PKTHDR) {
5946                         if_printf(ifp, "- m_pkthdr: flags = ( ");
5947                         if (mp->m_flags & M_BCAST)
5948                                 kprintf("M_BCAST ");
5949                         if (mp->m_flags & M_MCAST)
5950                                 kprintf("M_MCAST ");
5951                         if (mp->m_flags & M_FRAG)
5952                                 kprintf("M_FRAG ");
5953                         if (mp->m_flags & M_FIRSTFRAG)
5954                                 kprintf("M_FIRSTFRAG ");
5955                         if (mp->m_flags & M_LASTFRAG)
5956                                 kprintf("M_LASTFRAG ");
5957 #ifdef M_VLANTAG
5958                         if (mp->m_flags & M_VLANTAG)
5959                                 kprintf("M_VLANTAG ");
5960 #endif
5961 #ifdef M_PROMISC
5962                         if (mp->m_flags & M_PROMISC)
5963                                 kprintf("M_PROMISC ");
5964 #endif
5965                         kprintf(") csum_flags = ( ");
5966                         if (mp->m_pkthdr.csum_flags & CSUM_IP)
5967                                 kprintf("CSUM_IP ");
5968                         if (mp->m_pkthdr.csum_flags & CSUM_TCP)
5969                                 kprintf("CSUM_TCP ");
5970                         if (mp->m_pkthdr.csum_flags & CSUM_UDP)
5971                                 kprintf("CSUM_UDP ");
5972                         if (mp->m_pkthdr.csum_flags & CSUM_IP_FRAGS)
5973                                 kprintf("CSUM_IP_FRAGS ");
5974                         if (mp->m_pkthdr.csum_flags & CSUM_FRAGMENT)
5975                                 kprintf("CSUM_FRAGMENT ");
5976 #ifdef CSUM_TSO
5977                         if (mp->m_pkthdr.csum_flags & CSUM_TSO)
5978                                 kprintf("CSUM_TSO ");
5979 #endif
5980                         if (mp->m_pkthdr.csum_flags & CSUM_IP_CHECKED)
5981                                 kprintf("CSUM_IP_CHECKED ");
5982                         if (mp->m_pkthdr.csum_flags & CSUM_IP_VALID)
5983                                 kprintf("CSUM_IP_VALID ");
5984                         if (mp->m_pkthdr.csum_flags & CSUM_DATA_VALID)
5985                                 kprintf("CSUM_DATA_VALID ");
5986                         kprintf(")\n");
5987                 }
5988
5989                 if (mp->m_flags & M_EXT) {
5990                         val_hi = BCE_ADDR_HI(mp->m_ext.ext_buf);
5991                         val_lo = BCE_ADDR_LO(mp->m_ext.ext_buf);
5992                         if_printf(ifp, "- m_ext: vaddr = 0x%08X:%08X, "
5993                                   "ext_size = %d\n",
5994                                   val_hi, val_lo, mp->m_ext.ext_size);
5995                 }
5996                 mp = mp->m_next;
5997         }
5998 }
5999
6000
6001 /****************************************************************************/
6002 /* Prints out the mbufs in the TX mbuf chain.                               */
6003 /*                                                                          */
6004 /* Returns:                                                                 */
6005 /*   Nothing.                                                               */
6006 /****************************************************************************/
6007 static void
6008 bce_dump_tx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count)
6009 {
6010         struct ifnet *ifp = &sc->arpcom.ac_if;
6011         int i;
6012
6013         if_printf(ifp,
6014         "----------------------------"
6015         "  tx mbuf data  "
6016         "----------------------------\n");
6017
6018         for (i = 0; i < count; i++) {
6019                 if_printf(ifp, "txmbuf[%d]\n", chain_prod);
6020                 bce_dump_mbuf(sc, sc->tx_mbuf_ptr[chain_prod]);
6021                 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod));
6022         }
6023
6024         if_printf(ifp,
6025         "----------------------------"
6026         "----------------"
6027         "----------------------------\n");
6028 }
6029
6030
6031 /****************************************************************************/
6032 /* Prints out the mbufs in the RX mbuf chain.                               */
6033 /*                                                                          */
6034 /* Returns:                                                                 */
6035 /*   Nothing.                                                               */
6036 /****************************************************************************/
6037 static void
6038 bce_dump_rx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count)
6039 {
6040         struct ifnet *ifp = &sc->arpcom.ac_if;
6041         int i;
6042
6043         if_printf(ifp,
6044         "----------------------------"
6045         "  rx mbuf data  "
6046         "----------------------------\n");
6047
6048         for (i = 0; i < count; i++) {
6049                 if_printf(ifp, "rxmbuf[0x%04X]\n", chain_prod);
6050                 bce_dump_mbuf(sc, sc->rx_mbuf_ptr[chain_prod]);
6051                 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod));
6052         }
6053
6054         if_printf(ifp,
6055         "----------------------------"
6056         "----------------"
6057         "----------------------------\n");
6058 }
6059
6060
6061 /****************************************************************************/
6062 /* Prints out a tx_bd structure.                                            */
6063 /*                                                                          */
6064 /* Returns:                                                                 */
6065 /*   Nothing.                                                               */
6066 /****************************************************************************/
6067 static void
6068 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd)
6069 {
6070         struct ifnet *ifp = &sc->arpcom.ac_if;
6071
6072         if (idx > MAX_TX_BD) {
6073                 /* Index out of range. */
6074                 if_printf(ifp, "tx_bd[0x%04X]: Invalid tx_bd index!\n", idx);
6075         } else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) {
6076                 /* TX Chain page pointer. */
6077                 if_printf(ifp, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6078                           "chain page pointer\n",
6079                           idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo);
6080         } else {
6081                 /* Normal tx_bd entry. */
6082                 if_printf(ifp, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6083                           "nbytes = 0x%08X, "
6084                           "vlan tag= 0x%04X, flags = 0x%04X (",
6085                           idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo,
6086                           txbd->tx_bd_mss_nbytes,
6087                           txbd->tx_bd_vlan_tag, txbd->tx_bd_flags);
6088
6089                 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT)
6090                         kprintf(" CONN_FAULT");
6091
6092                 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM)
6093                         kprintf(" TCP_UDP_CKSUM");
6094
6095                 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM)
6096                         kprintf(" IP_CKSUM");
6097
6098                 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG)
6099                         kprintf("  VLAN");
6100
6101                 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW)
6102                         kprintf(" COAL_NOW");
6103
6104                 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC)
6105                         kprintf(" DONT_GEN_CRC");
6106
6107                 if (txbd->tx_bd_flags & TX_BD_FLAGS_START)
6108                         kprintf(" START");
6109
6110                 if (txbd->tx_bd_flags & TX_BD_FLAGS_END)
6111                         kprintf(" END");
6112
6113                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO)
6114                         kprintf(" LSO");
6115
6116                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD)
6117                         kprintf(" OPTION_WORD");
6118
6119                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS)
6120                         kprintf(" FLAGS");
6121
6122                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP)
6123                         kprintf(" SNAP");
6124
6125                 kprintf(" )\n");
6126         }
6127 }
6128
6129
6130 /****************************************************************************/
6131 /* Prints out a rx_bd structure.                                            */
6132 /*                                                                          */
6133 /* Returns:                                                                 */
6134 /*   Nothing.                                                               */
6135 /****************************************************************************/
6136 static void
6137 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd)
6138 {
6139         struct ifnet *ifp = &sc->arpcom.ac_if;
6140
6141         if (idx > MAX_RX_BD) {
6142                 /* Index out of range. */
6143                 if_printf(ifp, "rx_bd[0x%04X]: Invalid rx_bd index!\n", idx);
6144         } else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) {
6145                 /* TX Chain page pointer. */
6146                 if_printf(ifp, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6147                           "chain page pointer\n",
6148                           idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo);
6149         } else {
6150                 /* Normal tx_bd entry. */
6151                 if_printf(ifp, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6152                           "nbytes = 0x%08X, flags = 0x%08X\n",
6153                           idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo,
6154                           rxbd->rx_bd_len, rxbd->rx_bd_flags);
6155         }
6156 }
6157
6158
6159 /****************************************************************************/
6160 /* Prints out a l2_fhdr structure.                                          */
6161 /*                                                                          */
6162 /* Returns:                                                                 */
6163 /*   Nothing.                                                               */
6164 /****************************************************************************/
6165 static void
6166 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr)
6167 {
6168         if_printf(&sc->arpcom.ac_if, "l2_fhdr[0x%04X]: status = 0x%08X, "
6169                   "pkt_len = 0x%04X, vlan = 0x%04x, "
6170                   "ip_xsum = 0x%04X, tcp_udp_xsum = 0x%04X\n",
6171                   idx, l2fhdr->l2_fhdr_status,
6172                   l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag,
6173                   l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum);
6174 }
6175
6176
6177 /****************************************************************************/
6178 /* Prints out the tx chain.                                                 */
6179 /*                                                                          */
6180 /* Returns:                                                                 */
6181 /*   Nothing.                                                               */
6182 /****************************************************************************/
6183 static void
6184 bce_dump_tx_chain(struct bce_softc *sc, int tx_prod, int count)
6185 {
6186         struct ifnet *ifp = &sc->arpcom.ac_if;
6187         int i;
6188
6189         /* First some info about the tx_bd chain structure. */
6190         if_printf(ifp,
6191         "----------------------------"
6192         "  tx_bd  chain  "
6193         "----------------------------\n");
6194
6195         if_printf(ifp, "page size      = 0x%08X, "
6196                   "tx chain pages        = 0x%08X\n",
6197                   (uint32_t)BCM_PAGE_SIZE, (uint32_t)TX_PAGES);
6198
6199         if_printf(ifp, "tx_bd per page = 0x%08X, "
6200                   "usable tx_bd per page = 0x%08X\n",
6201                   (uint32_t)TOTAL_TX_BD_PER_PAGE,
6202                   (uint32_t)USABLE_TX_BD_PER_PAGE);
6203
6204         if_printf(ifp, "total tx_bd    = 0x%08X\n", (uint32_t)TOTAL_TX_BD);
6205
6206         if_printf(ifp,
6207         "----------------------------"
6208         "  tx_bd data    "
6209         "----------------------------\n");
6210
6211         /* Now print out the tx_bd's themselves. */
6212         for (i = 0; i < count; i++) {
6213                 struct tx_bd *txbd;
6214
6215                 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)];
6216                 bce_dump_txbd(sc, tx_prod, txbd);
6217                 tx_prod = TX_CHAIN_IDX(NEXT_TX_BD(tx_prod));
6218         }
6219
6220         if_printf(ifp,
6221         "----------------------------"
6222         "----------------"
6223         "----------------------------\n");
6224 }
6225
6226
6227 /****************************************************************************/
6228 /* Prints out the rx chain.                                                 */
6229 /*                                                                          */
6230 /* Returns:                                                                 */
6231 /*   Nothing.                                                               */
6232 /****************************************************************************/
6233 static void
6234 bce_dump_rx_chain(struct bce_softc *sc, int rx_prod, int count)
6235 {
6236         struct ifnet *ifp = &sc->arpcom.ac_if;
6237         int i;
6238
6239         /* First some info about the tx_bd chain structure. */
6240         if_printf(ifp,
6241         "----------------------------"
6242         "  rx_bd  chain  "
6243         "----------------------------\n");
6244
6245         if_printf(ifp, "page size      = 0x%08X, "
6246                   "rx chain pages        = 0x%08X\n",
6247                   (uint32_t)BCM_PAGE_SIZE, (uint32_t)RX_PAGES);
6248
6249         if_printf(ifp, "rx_bd per page = 0x%08X, "
6250                   "usable rx_bd per page = 0x%08X\n",
6251                   (uint32_t)TOTAL_RX_BD_PER_PAGE,
6252                   (uint32_t)USABLE_RX_BD_PER_PAGE);
6253
6254         if_printf(ifp, "total rx_bd    = 0x%08X\n", (uint32_t)TOTAL_RX_BD);
6255
6256         if_printf(ifp,
6257         "----------------------------"
6258         "   rx_bd data   "
6259         "----------------------------\n");
6260
6261         /* Now print out the rx_bd's themselves. */
6262         for (i = 0; i < count; i++) {
6263                 struct rx_bd *rxbd;
6264
6265                 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)];
6266                 bce_dump_rxbd(sc, rx_prod, rxbd);
6267                 rx_prod = RX_CHAIN_IDX(NEXT_RX_BD(rx_prod));
6268         }
6269
6270         if_printf(ifp,
6271         "----------------------------"
6272         "----------------"
6273         "----------------------------\n");
6274 }
6275
6276
6277 /****************************************************************************/
6278 /* Prints out the status block from host memory.                            */
6279 /*                                                                          */
6280 /* Returns:                                                                 */
6281 /*   Nothing.                                                               */
6282 /****************************************************************************/
6283 static void
6284 bce_dump_status_block(struct bce_softc *sc)
6285 {
6286         struct status_block *sblk = sc->status_block;
6287         struct ifnet *ifp = &sc->arpcom.ac_if;
6288
6289         if_printf(ifp,
6290         "----------------------------"
6291         "  Status Block  "
6292         "----------------------------\n");
6293
6294         if_printf(ifp, "    0x%08X - attn_bits\n", sblk->status_attn_bits);
6295
6296         if_printf(ifp, "    0x%08X - attn_bits_ack\n",
6297                   sblk->status_attn_bits_ack);
6298
6299         if_printf(ifp, "0x%04X(0x%04X) - rx_cons0\n",
6300             sblk->status_rx_quick_consumer_index0,
6301             (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index0));
6302
6303         if_printf(ifp, "0x%04X(0x%04X) - tx_cons0\n",
6304             sblk->status_tx_quick_consumer_index0,
6305             (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index0));
6306
6307         if_printf(ifp, "        0x%04X - status_idx\n", sblk->status_idx);
6308
6309         /* Theses indices are not used for normal L2 drivers. */
6310         if (sblk->status_rx_quick_consumer_index1) {
6311                 if_printf(ifp, "0x%04X(0x%04X) - rx_cons1\n",
6312                 sblk->status_rx_quick_consumer_index1,
6313                 (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index1));
6314         }
6315
6316         if (sblk->status_tx_quick_consumer_index1) {
6317                 if_printf(ifp, "0x%04X(0x%04X) - tx_cons1\n",
6318                 sblk->status_tx_quick_consumer_index1,
6319                 (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index1));
6320         }
6321
6322         if (sblk->status_rx_quick_consumer_index2) {
6323                 if_printf(ifp, "0x%04X(0x%04X)- rx_cons2\n",
6324                 sblk->status_rx_quick_consumer_index2,
6325                 (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index2));
6326         }
6327
6328         if (sblk->status_tx_quick_consumer_index2) {
6329                 if_printf(ifp, "0x%04X(0x%04X) - tx_cons2\n",
6330                 sblk->status_tx_quick_consumer_index2,
6331                 (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index2));
6332         }
6333
6334         if (sblk->status_rx_quick_consumer_index3) {
6335                 if_printf(ifp, "0x%04X(0x%04X) - rx_cons3\n",
6336                 sblk->status_rx_quick_consumer_index3,
6337                 (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index3));
6338         }
6339
6340         if (sblk->status_tx_quick_consumer_index3) {
6341                 if_printf(ifp, "0x%04X(0x%04X) - tx_cons3\n",
6342                 sblk->status_tx_quick_consumer_index3,
6343                 (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index3));
6344         }
6345
6346         if (sblk->status_rx_quick_consumer_index4 ||
6347             sblk->status_rx_quick_consumer_index5) {
6348                 if_printf(ifp, "rx_cons4  = 0x%08X, rx_cons5      = 0x%08X\n",
6349                           sblk->status_rx_quick_consumer_index4,
6350                           sblk->status_rx_quick_consumer_index5);
6351         }
6352
6353         if (sblk->status_rx_quick_consumer_index6 ||
6354             sblk->status_rx_quick_consumer_index7) {
6355                 if_printf(ifp, "rx_cons6  = 0x%08X, rx_cons7      = 0x%08X\n",
6356                           sblk->status_rx_quick_consumer_index6,
6357                           sblk->status_rx_quick_consumer_index7);
6358         }
6359
6360         if (sblk->status_rx_quick_consumer_index8 ||
6361             sblk->status_rx_quick_consumer_index9) {
6362                 if_printf(ifp, "rx_cons8  = 0x%08X, rx_cons9      = 0x%08X\n",
6363                           sblk->status_rx_quick_consumer_index8,
6364                           sblk->status_rx_quick_consumer_index9);
6365         }
6366
6367         if (sblk->status_rx_quick_consumer_index10 ||
6368             sblk->status_rx_quick_consumer_index11) {
6369                 if_printf(ifp, "rx_cons10 = 0x%08X, rx_cons11     = 0x%08X\n",
6370                           sblk->status_rx_quick_consumer_index10,
6371                           sblk->status_rx_quick_consumer_index11);
6372         }
6373
6374         if (sblk->status_rx_quick_consumer_index12 ||
6375             sblk->status_rx_quick_consumer_index13) {
6376                 if_printf(ifp, "rx_cons12 = 0x%08X, rx_cons13     = 0x%08X\n",
6377                           sblk->status_rx_quick_consumer_index12,
6378                           sblk->status_rx_quick_consumer_index13);
6379         }
6380
6381         if (sblk->status_rx_quick_consumer_index14 ||
6382             sblk->status_rx_quick_consumer_index15) {
6383                 if_printf(ifp, "rx_cons14 = 0x%08X, rx_cons15     = 0x%08X\n",
6384                           sblk->status_rx_quick_consumer_index14,
6385                           sblk->status_rx_quick_consumer_index15);
6386         }
6387
6388         if (sblk->status_completion_producer_index ||
6389             sblk->status_cmd_consumer_index) {
6390                 if_printf(ifp, "com_prod  = 0x%08X, cmd_cons      = 0x%08X\n",
6391                           sblk->status_completion_producer_index,
6392                           sblk->status_cmd_consumer_index);
6393         }
6394
6395         if_printf(ifp,
6396         "----------------------------"
6397         "----------------"
6398         "----------------------------\n");
6399 }
6400
6401
6402 /****************************************************************************/
6403 /* Prints out the statistics block.                                         */
6404 /*                                                                          */
6405 /* Returns:                                                                 */
6406 /*   Nothing.                                                               */
6407 /****************************************************************************/
6408 static void
6409 bce_dump_stats_block(struct bce_softc *sc)
6410 {
6411         struct statistics_block *sblk = sc->stats_block;
6412         struct ifnet *ifp = &sc->arpcom.ac_if;
6413
6414         if_printf(ifp,
6415         "---------------"
6416         " Stats Block  (All Stats Not Shown Are 0) "
6417         "---------------\n");
6418
6419         if (sblk->stat_IfHCInOctets_hi || sblk->stat_IfHCInOctets_lo) {
6420                 if_printf(ifp, "0x%08X:%08X : IfHcInOctets\n",
6421                           sblk->stat_IfHCInOctets_hi,
6422                           sblk->stat_IfHCInOctets_lo);
6423         }
6424
6425         if (sblk->stat_IfHCInBadOctets_hi || sblk->stat_IfHCInBadOctets_lo) {
6426                 if_printf(ifp, "0x%08X:%08X : IfHcInBadOctets\n",
6427                           sblk->stat_IfHCInBadOctets_hi,
6428                           sblk->stat_IfHCInBadOctets_lo);
6429         }
6430
6431         if (sblk->stat_IfHCOutOctets_hi || sblk->stat_IfHCOutOctets_lo) {
6432                 if_printf(ifp, "0x%08X:%08X : IfHcOutOctets\n",
6433                           sblk->stat_IfHCOutOctets_hi,
6434                           sblk->stat_IfHCOutOctets_lo);
6435         }
6436
6437         if (sblk->stat_IfHCOutBadOctets_hi || sblk->stat_IfHCOutBadOctets_lo) {
6438                 if_printf(ifp, "0x%08X:%08X : IfHcOutBadOctets\n",
6439                           sblk->stat_IfHCOutBadOctets_hi,
6440                           sblk->stat_IfHCOutBadOctets_lo);
6441         }
6442
6443         if (sblk->stat_IfHCInUcastPkts_hi || sblk->stat_IfHCInUcastPkts_lo) {
6444                 if_printf(ifp, "0x%08X:%08X : IfHcInUcastPkts\n",
6445                           sblk->stat_IfHCInUcastPkts_hi,
6446                           sblk->stat_IfHCInUcastPkts_lo);
6447         }
6448
6449         if (sblk->stat_IfHCInBroadcastPkts_hi ||
6450             sblk->stat_IfHCInBroadcastPkts_lo) {
6451                 if_printf(ifp, "0x%08X:%08X : IfHcInBroadcastPkts\n",
6452                           sblk->stat_IfHCInBroadcastPkts_hi,
6453                           sblk->stat_IfHCInBroadcastPkts_lo);
6454         }
6455
6456         if (sblk->stat_IfHCInMulticastPkts_hi ||
6457             sblk->stat_IfHCInMulticastPkts_lo) {
6458                 if_printf(ifp, "0x%08X:%08X : IfHcInMulticastPkts\n",
6459                           sblk->stat_IfHCInMulticastPkts_hi,
6460                           sblk->stat_IfHCInMulticastPkts_lo);
6461         }
6462
6463         if (sblk->stat_IfHCOutUcastPkts_hi || sblk->stat_IfHCOutUcastPkts_lo) {
6464                 if_printf(ifp, "0x%08X:%08X : IfHcOutUcastPkts\n",
6465                           sblk->stat_IfHCOutUcastPkts_hi,
6466                           sblk->stat_IfHCOutUcastPkts_lo);
6467         }
6468
6469         if (sblk->stat_IfHCOutBroadcastPkts_hi ||
6470             sblk->stat_IfHCOutBroadcastPkts_lo) {
6471                 if_printf(ifp, "0x%08X:%08X : IfHcOutBroadcastPkts\n",
6472                           sblk->stat_IfHCOutBroadcastPkts_hi,
6473                           sblk->stat_IfHCOutBroadcastPkts_lo);
6474         }
6475
6476         if (sblk->stat_IfHCOutMulticastPkts_hi ||
6477             sblk->stat_IfHCOutMulticastPkts_lo) {
6478                 if_printf(ifp, "0x%08X:%08X : IfHcOutMulticastPkts\n",
6479                           sblk->stat_IfHCOutMulticastPkts_hi,
6480                           sblk->stat_IfHCOutMulticastPkts_lo);
6481         }
6482
6483         if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) {
6484                 if_printf(ifp, "         0x%08X : "
6485                 "emac_tx_stat_dot3statsinternalmactransmiterrors\n",
6486                 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors);
6487         }
6488
6489         if (sblk->stat_Dot3StatsCarrierSenseErrors) {
6490                 if_printf(ifp, "         0x%08X : "
6491                           "Dot3StatsCarrierSenseErrors\n",
6492                           sblk->stat_Dot3StatsCarrierSenseErrors);
6493         }
6494
6495         if (sblk->stat_Dot3StatsFCSErrors) {
6496                 if_printf(ifp, "         0x%08X : Dot3StatsFCSErrors\n",
6497                           sblk->stat_Dot3StatsFCSErrors);
6498         }
6499
6500         if (sblk->stat_Dot3StatsAlignmentErrors) {
6501                 if_printf(ifp, "         0x%08X : Dot3StatsAlignmentErrors\n",
6502                           sblk->stat_Dot3StatsAlignmentErrors);
6503         }
6504
6505         if (sblk->stat_Dot3StatsSingleCollisionFrames) {
6506                 if_printf(ifp, "         0x%08X : "
6507                           "Dot3StatsSingleCollisionFrames\n",
6508                           sblk->stat_Dot3StatsSingleCollisionFrames);
6509         }
6510
6511         if (sblk->stat_Dot3StatsMultipleCollisionFrames) {
6512                 if_printf(ifp, "         0x%08X : "
6513                           "Dot3StatsMultipleCollisionFrames\n",
6514                           sblk->stat_Dot3StatsMultipleCollisionFrames);
6515         }
6516
6517         if (sblk->stat_Dot3StatsDeferredTransmissions) {
6518                 if_printf(ifp, "         0x%08X : "
6519                           "Dot3StatsDeferredTransmissions\n",
6520                           sblk->stat_Dot3StatsDeferredTransmissions);
6521         }
6522
6523         if (sblk->stat_Dot3StatsExcessiveCollisions) {
6524                 if_printf(ifp, "         0x%08X : "
6525                           "Dot3StatsExcessiveCollisions\n",
6526                           sblk->stat_Dot3StatsExcessiveCollisions);
6527         }
6528
6529         if (sblk->stat_Dot3StatsLateCollisions) {
6530                 if_printf(ifp, "         0x%08X : Dot3StatsLateCollisions\n",
6531                           sblk->stat_Dot3StatsLateCollisions);
6532         }
6533
6534         if (sblk->stat_EtherStatsCollisions) {
6535                 if_printf(ifp, "         0x%08X : EtherStatsCollisions\n",
6536                           sblk->stat_EtherStatsCollisions);
6537         }
6538
6539         if (sblk->stat_EtherStatsFragments)  {
6540                 if_printf(ifp, "         0x%08X : EtherStatsFragments\n",
6541                           sblk->stat_EtherStatsFragments);
6542         }
6543
6544         if (sblk->stat_EtherStatsJabbers) {
6545                 if_printf(ifp, "         0x%08X : EtherStatsJabbers\n",
6546                           sblk->stat_EtherStatsJabbers);
6547         }
6548
6549         if (sblk->stat_EtherStatsUndersizePkts) {
6550                 if_printf(ifp, "         0x%08X : EtherStatsUndersizePkts\n",
6551                           sblk->stat_EtherStatsUndersizePkts);
6552         }
6553
6554         if (sblk->stat_EtherStatsOverrsizePkts) {
6555                 if_printf(ifp, "         0x%08X : EtherStatsOverrsizePkts\n",
6556                           sblk->stat_EtherStatsOverrsizePkts);
6557         }
6558
6559         if (sblk->stat_EtherStatsPktsRx64Octets) {
6560                 if_printf(ifp, "         0x%08X : EtherStatsPktsRx64Octets\n",
6561                           sblk->stat_EtherStatsPktsRx64Octets);
6562         }
6563
6564         if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) {
6565                 if_printf(ifp, "         0x%08X : "
6566                           "EtherStatsPktsRx65Octetsto127Octets\n",
6567                           sblk->stat_EtherStatsPktsRx65Octetsto127Octets);
6568         }
6569
6570         if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) {
6571                 if_printf(ifp, "         0x%08X : "
6572                           "EtherStatsPktsRx128Octetsto255Octets\n",
6573                           sblk->stat_EtherStatsPktsRx128Octetsto255Octets);
6574         }
6575
6576         if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) {
6577                 if_printf(ifp, "         0x%08X : "
6578                           "EtherStatsPktsRx256Octetsto511Octets\n",
6579                           sblk->stat_EtherStatsPktsRx256Octetsto511Octets);
6580         }
6581
6582         if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) {
6583                 if_printf(ifp, "         0x%08X : "
6584                           "EtherStatsPktsRx512Octetsto1023Octets\n",
6585                           sblk->stat_EtherStatsPktsRx512Octetsto1023Octets);
6586         }
6587
6588         if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) {
6589                 if_printf(ifp, "         0x%08X : "
6590                           "EtherStatsPktsRx1024Octetsto1522Octets\n",
6591                           sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets);
6592         }
6593
6594         if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) {
6595                 if_printf(ifp, "         0x%08X : "
6596                           "EtherStatsPktsRx1523Octetsto9022Octets\n",
6597                           sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets);
6598         }
6599
6600         if (sblk->stat_EtherStatsPktsTx64Octets) {
6601                 if_printf(ifp, "         0x%08X : EtherStatsPktsTx64Octets\n",
6602                           sblk->stat_EtherStatsPktsTx64Octets);
6603         }
6604
6605         if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) {
6606                 if_printf(ifp, "         0x%08X : "
6607                           "EtherStatsPktsTx65Octetsto127Octets\n",
6608                           sblk->stat_EtherStatsPktsTx65Octetsto127Octets);
6609         }
6610
6611         if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) {
6612                 if_printf(ifp, "         0x%08X : "
6613                           "EtherStatsPktsTx128Octetsto255Octets\n",
6614                           sblk->stat_EtherStatsPktsTx128Octetsto255Octets);
6615         }
6616
6617         if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) {
6618                 if_printf(ifp, "         0x%08X : "
6619                           "EtherStatsPktsTx256Octetsto511Octets\n",
6620                           sblk->stat_EtherStatsPktsTx256Octetsto511Octets);
6621         }
6622
6623         if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) {
6624                 if_printf(ifp, "         0x%08X : "
6625                           "EtherStatsPktsTx512Octetsto1023Octets\n",
6626                           sblk->stat_EtherStatsPktsTx512Octetsto1023Octets);
6627         }
6628
6629         if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) {
6630                 if_printf(ifp, "         0x%08X : "
6631                           "EtherStatsPktsTx1024Octetsto1522Octets\n",
6632                           sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets);
6633         }
6634
6635         if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) {
6636                 if_printf(ifp, "         0x%08X : "
6637                           "EtherStatsPktsTx1523Octetsto9022Octets\n",
6638                           sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets);
6639         }
6640
6641         if (sblk->stat_XonPauseFramesReceived) {
6642                 if_printf(ifp, "         0x%08X : XonPauseFramesReceived\n",
6643                           sblk->stat_XonPauseFramesReceived);
6644         }
6645
6646         if (sblk->stat_XoffPauseFramesReceived) {
6647                 if_printf(ifp, "          0x%08X : XoffPauseFramesReceived\n",
6648                           sblk->stat_XoffPauseFramesReceived);
6649         }
6650
6651         if (sblk->stat_OutXonSent) {
6652                 if_printf(ifp, "         0x%08X : OutXoffSent\n",
6653                           sblk->stat_OutXonSent);
6654         }
6655
6656         if (sblk->stat_OutXoffSent) {
6657                 if_printf(ifp, "         0x%08X : OutXoffSent\n",
6658                           sblk->stat_OutXoffSent);
6659         }
6660
6661         if (sblk->stat_FlowControlDone) {
6662                 if_printf(ifp, "         0x%08X : FlowControlDone\n",
6663                           sblk->stat_FlowControlDone);
6664         }
6665
6666         if (sblk->stat_MacControlFramesReceived) {
6667                 if_printf(ifp, "         0x%08X : MacControlFramesReceived\n",
6668                           sblk->stat_MacControlFramesReceived);
6669         }
6670
6671         if (sblk->stat_XoffStateEntered) {
6672                 if_printf(ifp, "         0x%08X : XoffStateEntered\n",
6673                           sblk->stat_XoffStateEntered);
6674         }
6675
6676         if (sblk->stat_IfInFramesL2FilterDiscards) {
6677                 if_printf(ifp, "         0x%08X : IfInFramesL2FilterDiscards\n",                          sblk->stat_IfInFramesL2FilterDiscards);
6678         }
6679
6680         if (sblk->stat_IfInRuleCheckerDiscards) {
6681                 if_printf(ifp, "         0x%08X : IfInRuleCheckerDiscards\n",
6682                           sblk->stat_IfInRuleCheckerDiscards);
6683         }
6684
6685         if (sblk->stat_IfInFTQDiscards) {
6686                 if_printf(ifp, "         0x%08X : IfInFTQDiscards\n",
6687                           sblk->stat_IfInFTQDiscards);
6688         }
6689
6690         if (sblk->stat_IfInMBUFDiscards) {
6691                 if_printf(ifp, "         0x%08X : IfInMBUFDiscards\n",
6692                           sblk->stat_IfInMBUFDiscards);
6693         }
6694
6695         if (sblk->stat_IfInRuleCheckerP4Hit) {
6696                 if_printf(ifp, "         0x%08X : IfInRuleCheckerP4Hit\n",
6697                           sblk->stat_IfInRuleCheckerP4Hit);
6698         }
6699
6700         if (sblk->stat_CatchupInRuleCheckerDiscards) {
6701                 if_printf(ifp, "         0x%08X : "
6702                           "CatchupInRuleCheckerDiscards\n",
6703                           sblk->stat_CatchupInRuleCheckerDiscards);
6704         }
6705
6706         if (sblk->stat_CatchupInFTQDiscards) {
6707                 if_printf(ifp, "         0x%08X : CatchupInFTQDiscards\n",
6708                           sblk->stat_CatchupInFTQDiscards);
6709         }
6710
6711         if (sblk->stat_CatchupInMBUFDiscards) {
6712                 if_printf(ifp, "         0x%08X : CatchupInMBUFDiscards\n",
6713                           sblk->stat_CatchupInMBUFDiscards);
6714         }
6715
6716         if (sblk->stat_CatchupInRuleCheckerP4Hit) {
6717                 if_printf(ifp, "         0x%08X : CatchupInRuleCheckerP4Hit\n",
6718                           sblk->stat_CatchupInRuleCheckerP4Hit);
6719         }
6720
6721         if_printf(ifp,
6722         "----------------------------"
6723         "----------------"
6724         "----------------------------\n");
6725 }
6726
6727
6728 /****************************************************************************/
6729 /* Prints out a summary of the driver state.                                */
6730 /*                                                                          */
6731 /* Returns:                                                                 */
6732 /*   Nothing.                                                               */
6733 /****************************************************************************/
6734 static void
6735 bce_dump_driver_state(struct bce_softc *sc)
6736 {
6737         struct ifnet *ifp = &sc->arpcom.ac_if;
6738         uint32_t val_hi, val_lo;
6739
6740         if_printf(ifp,
6741         "-----------------------------"
6742         " Driver State "
6743         "-----------------------------\n");
6744
6745         val_hi = BCE_ADDR_HI(sc);
6746         val_lo = BCE_ADDR_LO(sc);
6747         if_printf(ifp, "0x%08X:%08X - (sc) driver softc structure "
6748                   "virtual address\n", val_hi, val_lo);
6749
6750         val_hi = BCE_ADDR_HI(sc->status_block);
6751         val_lo = BCE_ADDR_LO(sc->status_block);
6752         if_printf(ifp, "0x%08X:%08X - (sc->status_block) status block "
6753                   "virtual address\n", val_hi, val_lo);
6754
6755         val_hi = BCE_ADDR_HI(sc->stats_block);
6756         val_lo = BCE_ADDR_LO(sc->stats_block);
6757         if_printf(ifp, "0x%08X:%08X - (sc->stats_block) statistics block "
6758                   "virtual address\n", val_hi, val_lo);
6759
6760         val_hi = BCE_ADDR_HI(sc->tx_bd_chain);
6761         val_lo = BCE_ADDR_LO(sc->tx_bd_chain);
6762         if_printf(ifp, "0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain "
6763                   "virtual adddress\n", val_hi, val_lo);
6764
6765         val_hi = BCE_ADDR_HI(sc->rx_bd_chain);
6766         val_lo = BCE_ADDR_LO(sc->rx_bd_chain);
6767         if_printf(ifp, "0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain "
6768                   "virtual address\n", val_hi, val_lo);
6769
6770         val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr);
6771         val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr);
6772         if_printf(ifp, "0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain "
6773                   "virtual address\n", val_hi, val_lo);
6774
6775         val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr);
6776         val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr);
6777         if_printf(ifp, "0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain "
6778                   "virtual address\n", val_hi, val_lo);
6779
6780         if_printf(ifp, "         0x%08X - (sc->interrupts_generated) "
6781                   "h/w intrs\n", sc->interrupts_generated);
6782
6783         if_printf(ifp, "         0x%08X - (sc->rx_interrupts) "
6784                   "rx interrupts handled\n", sc->rx_interrupts);
6785
6786         if_printf(ifp, "         0x%08X - (sc->tx_interrupts) "
6787                   "tx interrupts handled\n", sc->tx_interrupts);
6788
6789         if_printf(ifp, "         0x%08X - (sc->last_status_idx) "
6790                   "status block index\n", sc->last_status_idx);
6791
6792         if_printf(ifp, "     0x%04X(0x%04X) - (sc->tx_prod) "
6793                   "tx producer index\n",
6794                   sc->tx_prod, (uint16_t)TX_CHAIN_IDX(sc->tx_prod));
6795
6796         if_printf(ifp, "     0x%04X(0x%04X) - (sc->tx_cons) "
6797                   "tx consumer index\n",
6798                   sc->tx_cons, (uint16_t)TX_CHAIN_IDX(sc->tx_cons));
6799
6800         if_printf(ifp, "         0x%08X - (sc->tx_prod_bseq) "
6801                   "tx producer bseq index\n", sc->tx_prod_bseq);
6802
6803         if_printf(ifp, "     0x%04X(0x%04X) - (sc->rx_prod) "
6804                   "rx producer index\n",
6805                   sc->rx_prod, (uint16_t)RX_CHAIN_IDX(sc->rx_prod));
6806
6807         if_printf(ifp, "     0x%04X(0x%04X) - (sc->rx_cons) "
6808                   "rx consumer index\n",
6809                   sc->rx_cons, (uint16_t)RX_CHAIN_IDX(sc->rx_cons));
6810
6811         if_printf(ifp, "         0x%08X - (sc->rx_prod_bseq) "
6812                   "rx producer bseq index\n", sc->rx_prod_bseq);
6813
6814         if_printf(ifp, "         0x%08X - (sc->rx_mbuf_alloc) "
6815                   "rx mbufs allocated\n", sc->rx_mbuf_alloc);
6816
6817         if_printf(ifp, "         0x%08X - (sc->free_rx_bd) "
6818                   "free rx_bd's\n", sc->free_rx_bd);
6819
6820         if_printf(ifp, "0x%08X/%08X - (sc->rx_low_watermark) rx "
6821                   "low watermark\n", sc->rx_low_watermark, sc->max_rx_bd);
6822
6823         if_printf(ifp, "         0x%08X - (sc->txmbuf_alloc) "
6824                   "tx mbufs allocated\n", sc->tx_mbuf_alloc);
6825
6826         if_printf(ifp, "         0x%08X - (sc->rx_mbuf_alloc) "
6827                   "rx mbufs allocated\n", sc->rx_mbuf_alloc);
6828
6829         if_printf(ifp, "         0x%08X - (sc->used_tx_bd) used tx_bd's\n",
6830                   sc->used_tx_bd);
6831
6832         if_printf(ifp, "0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n",
6833                   sc->tx_hi_watermark, sc->max_tx_bd);
6834
6835         if_printf(ifp, "         0x%08X - (sc->mbuf_alloc_failed) "
6836                   "failed mbuf alloc\n", sc->mbuf_alloc_failed);
6837
6838         if_printf(ifp,
6839         "----------------------------"
6840         "----------------"
6841         "----------------------------\n");
6842 }
6843
6844
6845 /****************************************************************************/
6846 /* Prints out the hardware state through a summary of important registers,  */\r
6847 /* followed by a complete register dump.                                    */
6848 /*                                                                          */
6849 /* Returns:                                                                 */
6850 /*   Nothing.                                                               */
6851 /****************************************************************************/
6852 static void
6853 bce_dump_hw_state(struct bce_softc *sc)
6854 {
6855         struct ifnet *ifp = &sc->arpcom.ac_if;
6856         uint32_t val1;
6857         int i;
6858
6859         if_printf(ifp,
6860         "----------------------------"
6861         " Hardware State "
6862         "----------------------------\n");
6863
6864         if_printf(ifp, "0x%08X - bootcode version\n", sc->bce_fw_ver);
6865
6866         val1 = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS);
6867         if_printf(ifp, "0x%08X - (0x%06X) misc_enable_status_bits\n",
6868                   val1, BCE_MISC_ENABLE_STATUS_BITS);
6869
6870         val1 = REG_RD(sc, BCE_DMA_STATUS);
6871         if_printf(ifp, "0x%08X - (0x%04X) dma_status\n", val1, BCE_DMA_STATUS);
6872
6873         val1 = REG_RD(sc, BCE_CTX_STATUS);
6874         if_printf(ifp, "0x%08X - (0x%04X) ctx_status\n", val1, BCE_CTX_STATUS);
6875
6876         val1 = REG_RD(sc, BCE_EMAC_STATUS);
6877         if_printf(ifp, "0x%08X - (0x%04X) emac_status\n",
6878                   val1, BCE_EMAC_STATUS);
6879
6880         val1 = REG_RD(sc, BCE_RPM_STATUS);
6881         if_printf(ifp, "0x%08X - (0x%04X) rpm_status\n", val1, BCE_RPM_STATUS);
6882
6883         val1 = REG_RD(sc, BCE_TBDR_STATUS);
6884         if_printf(ifp, "0x%08X - (0x%04X) tbdr_status\n",
6885                   val1, BCE_TBDR_STATUS);
6886
6887         val1 = REG_RD(sc, BCE_TDMA_STATUS);
6888         if_printf(ifp, "0x%08X - (0x%04X) tdma_status\n",
6889                   val1, BCE_TDMA_STATUS);
6890
6891         val1 = REG_RD(sc, BCE_HC_STATUS);
6892         if_printf(ifp, "0x%08X - (0x%06X) hc_status\n", val1, BCE_HC_STATUS);
6893
6894         val1 = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
6895         if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_state\n",
6896                   val1, BCE_TXP_CPU_STATE);
6897
6898         val1 = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
6899         if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_state\n",
6900                   val1, BCE_TPAT_CPU_STATE);
6901
6902         val1 = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
6903         if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_state\n",
6904                   val1, BCE_RXP_CPU_STATE);
6905
6906         val1 = REG_RD_IND(sc, BCE_COM_CPU_STATE);
6907         if_printf(ifp, "0x%08X - (0x%06X) com_cpu_state\n",
6908                   val1, BCE_COM_CPU_STATE);
6909
6910         val1 = REG_RD_IND(sc, BCE_MCP_CPU_STATE);
6911         if_printf(ifp, "0x%08X - (0x%06X) mcp_cpu_state\n",
6912                   val1, BCE_MCP_CPU_STATE);
6913
6914         val1 = REG_RD_IND(sc, BCE_CP_CPU_STATE);
6915         if_printf(ifp, "0x%08X - (0x%06X) cp_cpu_state\n",
6916                   val1, BCE_CP_CPU_STATE);
6917
6918         if_printf(ifp,
6919         "----------------------------"
6920         "----------------"
6921         "----------------------------\n");
6922
6923         if_printf(ifp,
6924         "----------------------------"
6925         " Register  Dump "
6926         "----------------------------\n");
6927
6928         for (i = 0x400; i < 0x8000; i += 0x10) {
6929                 if_printf(ifp, "0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i,
6930                           REG_RD(sc, i),
6931                           REG_RD(sc, i + 0x4),
6932                           REG_RD(sc, i + 0x8),
6933                           REG_RD(sc, i + 0xc));
6934         }
6935
6936         if_printf(ifp,
6937         "----------------------------"
6938         "----------------"
6939         "----------------------------\n");
6940 }
6941
6942
6943 /****************************************************************************/
6944 /* Prints out the TXP state.                                                */\r
6945 /*                                                                          */
6946 /* Returns:                                                                 */
6947 /*   Nothing.                                                               */
6948 /****************************************************************************/
6949 static void
6950 bce_dump_txp_state(struct bce_softc *sc)
6951 {
6952         struct ifnet *ifp = &sc->arpcom.ac_if;
6953         uint32_t val1;
6954         int i;
6955
6956         if_printf(ifp,
6957         "----------------------------"
6958         "   TXP  State   "
6959         "----------------------------\n");
6960
6961         val1 = REG_RD_IND(sc, BCE_TXP_CPU_MODE);
6962         if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_mode\n",
6963                   val1, BCE_TXP_CPU_MODE);
6964
6965         val1 = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
6966         if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_state\n",
6967                   val1, BCE_TXP_CPU_STATE);
6968
6969         val1 = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK);
6970         if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_event_mask\n",
6971                   val1, BCE_TXP_CPU_EVENT_MASK);
6972
6973         if_printf(ifp,
6974         "----------------------------"
6975         " Register  Dump "
6976         "----------------------------\n");
6977
6978         for (i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) {
6979                 /* Skip the big blank spaces */
6980                 if (i < 0x454000 && i > 0x5ffff) {
6981                         if_printf(ifp, "0x%04X: "
6982                                   "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
6983                                   REG_RD_IND(sc, i),
6984                                   REG_RD_IND(sc, i + 0x4),
6985                                   REG_RD_IND(sc, i + 0x8),
6986                                   REG_RD_IND(sc, i + 0xc));
6987                 }
6988         }
6989
6990         if_printf(ifp,
6991         "----------------------------"
6992         "----------------"
6993         "----------------------------\n");
6994 }
6995
6996
6997 /****************************************************************************/
6998 /* Prints out the RXP state.                                                */\r
6999 /*                                                                          */
7000 /* Returns:                                                                 */
7001 /*   Nothing.                                                               */
7002 /****************************************************************************/
7003 static void
7004 bce_dump_rxp_state(struct bce_softc *sc)
7005 {
7006         struct ifnet *ifp = &sc->arpcom.ac_if;
7007         uint32_t val1;
7008         int i;
7009
7010         if_printf(ifp,
7011         "----------------------------"
7012         "   RXP  State   "
7013         "----------------------------\n");
7014
7015         val1 = REG_RD_IND(sc, BCE_RXP_CPU_MODE);
7016         if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_mode\n",
7017                   val1, BCE_RXP_CPU_MODE);
7018
7019         val1 = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
7020         if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_state\n",
7021                   val1, BCE_RXP_CPU_STATE);
7022
7023         val1 = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK);
7024         if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_event_mask\n",
7025                   val1, BCE_RXP_CPU_EVENT_MASK);
7026
7027         if_printf(ifp,
7028         "----------------------------"
7029         " Register  Dump "
7030         "----------------------------\n");
7031
7032         for (i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) {
7033                 /* Skip the big blank sapces */
7034                 if (i < 0xc5400 && i > 0xdffff) {
7035                         if_printf(ifp, "0x%04X: "
7036                                   "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7037                                   REG_RD_IND(sc, i),
7038                                   REG_RD_IND(sc, i + 0x4),
7039                                   REG_RD_IND(sc, i + 0x8),
7040                                   REG_RD_IND(sc, i + 0xc));
7041                 }
7042         }
7043
7044         if_printf(ifp,
7045         "----------------------------"
7046         "----------------"
7047         "----------------------------\n");
7048 }
7049
7050
7051 /****************************************************************************/
7052 /* Prints out the TPAT state.                                               */\r
7053 /*                                                                          */
7054 /* Returns:                                                                 */
7055 /*   Nothing.                                                               */
7056 /****************************************************************************/
7057 static void
7058 bce_dump_tpat_state(struct bce_softc *sc)
7059 {
7060         struct ifnet *ifp = &sc->arpcom.ac_if;
7061         uint32_t val1;
7062         int i;
7063
7064         if_printf(ifp,
7065         "----------------------------"
7066         "   TPAT State   "
7067         "----------------------------\n");
7068
7069         val1 = REG_RD_IND(sc, BCE_TPAT_CPU_MODE);
7070         if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_mode\n",
7071                   val1, BCE_TPAT_CPU_MODE);
7072
7073         val1 = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
7074         if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_state\n",
7075                   val1, BCE_TPAT_CPU_STATE);
7076
7077         val1 = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK);
7078         if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_event_mask\n",
7079                   val1, BCE_TPAT_CPU_EVENT_MASK);
7080
7081         if_printf(ifp,
7082         "----------------------------"
7083         " Register  Dump "
7084         "----------------------------\n");
7085
7086         for (i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) {
7087                 /* Skip the big blank spaces */
7088                 if (i < 0x854000 && i > 0x9ffff) {
7089                         if_printf(ifp, "0x%04X: "
7090                                   "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7091                                   REG_RD_IND(sc, i),
7092                                   REG_RD_IND(sc, i + 0x4),
7093                                   REG_RD_IND(sc, i + 0x8),
7094                                   REG_RD_IND(sc, i + 0xc));
7095                 }
7096         }
7097
7098         if_printf(ifp,
7099         "----------------------------"
7100         "----------------"
7101         "----------------------------\n");
7102 }
7103
7104
7105 /****************************************************************************/
7106 /* Prints out the driver state and then enters the debugger.                */
7107 /*                                                                          */
7108 /* Returns:                                                                 */
7109 /*   Nothing.                                                               */
7110 /****************************************************************************/
7111 static void
7112 bce_breakpoint(struct bce_softc *sc)
7113 {
7114 #if 0
7115         bce_freeze_controller(sc);
7116 #endif
7117
7118         bce_dump_driver_state(sc);
7119         bce_dump_status_block(sc);
7120         bce_dump_tx_chain(sc, 0, TOTAL_TX_BD);
7121         bce_dump_hw_state(sc);
7122         bce_dump_txp_state(sc);
7123
7124 #if 0
7125         bce_unfreeze_controller(sc);
7126 #endif
7127
7128         /* Call the debugger. */
7129         breakpoint();
7130 }
7131
7132 #endif  /* BCE_DEBUG */